diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-12-19 05:46:54 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-12-19 05:46:54 +0100 |
| commit | 574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch) | |
| tree | 3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/src/arm64/hisilicon/hi6220.dtsi | |
| parent | 179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff) | |
| download | barebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.gz barebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.xz | |
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/hisilicon/hi6220.dtsi')
| -rw-r--r-- | dts/src/arm64/hisilicon/hi6220.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi index 108e2a4227..2072b637b5 100644 --- a/dts/src/arm64/hisilicon/hi6220.dtsi +++ b/dts/src/arm64/hisilicon/hi6220.dtsi @@ -260,6 +260,7 @@ compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; #clock-cells = <1>; + #reset-cells = <1>; }; sys_ctrl: sys_ctrl@f7030000 { @@ -1021,6 +1022,43 @@ clock-names = "apb_pclk"; cpu = <&cpu7>; }; + + mali: gpu@f4080000 { + compatible = "hisilicon,hi6220-mali", "arm,mali-450"; + reg = <0x0 0xf4080000 0x0 0x00040000>; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + clock-names = "core", "bus"; + assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + assigned-clock-rates = <500000000>, <144000000>; + reset-names = "ao_g3d", "media_g3d"; + resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; + }; }; }; |