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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-09-08 08:40:45 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-09-08 08:40:45 +0200 |
commit | f196eb03d84047a76e0ae1ad625139861e16a03b (patch) | |
tree | 49a54678c8e8225c62159d8d05ebd69c05c87f44 /dts/src/arm64/marvell | |
parent | b16768baec218997372bc4abef4b4a41375dd849 (diff) | |
download | barebox-f196eb03d84047a76e0ae1ad625139861e16a03b.tar.gz barebox-f196eb03d84047a76e0ae1ad625139861e16a03b.tar.xz |
dts: update to v4.13-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/marvell')
-rw-r--r-- | dts/src/arm64/marvell/armada-37xx.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm64/marvell/armada-cp110-master.dtsi | 1 | ||||
-rw-r--r-- | dts/src/arm64/marvell/armada-cp110-slave.dtsi | 3 |
3 files changed, 4 insertions, 2 deletions
diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi index dbcc3d4e2e..51763d6740 100644 --- a/dts/src/arm64/marvell/armada-37xx.dtsi +++ b/dts/src/arm64/marvell/armada-37xx.dtsi @@ -219,7 +219,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi index 726528ce54..4c68605675 100644 --- a/dts/src/arm64/marvell/armada-cp110-master.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi @@ -270,6 +270,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; + dma-coherent; }; }; diff --git a/dts/src/arm64/marvell/armada-cp110-slave.dtsi b/dts/src/arm64/marvell/armada-cp110-slave.dtsi index 95f8e5f607..923f354b02 100644 --- a/dts/src/arm64/marvell/armada-cp110-slave.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-slave.dtsi @@ -64,7 +64,7 @@ compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; reg-names = "rtc", "rtc-soc"; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; }; cps_ethernet: ethernet@0 { @@ -261,6 +261,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; + dma-coherent; /* * The cryptographic engine found on the cp110 * master is enabled by default at the SoC |