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authorSascha Hauer <s.hauer@pengutronix.de>2021-08-09 21:17:55 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2021-08-09 21:17:55 +0200
commit3fafe407e0832406f222cf78cdaeabce5605f694 (patch)
tree731bafc8c6accb0154e9459cf4ac3319bb14fac2 /dts/src/arm64/nvidia/tegra194.dtsi
parent6187b17da4b277417f34fe0b0b90bbaddcbc599e (diff)
downloadbarebox-3fafe407e0832406f222cf78cdaeabce5605f694.tar.gz
barebox-3fafe407e0832406f222cf78cdaeabce5605f694.tar.xz
dts: update to v5.14-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/nvidia/tegra194.dtsi')
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/dts/src/arm64/nvidia/tegra194.dtsi b/dts/src/arm64/nvidia/tegra194.dtsi
index b7d5328413..076d5efc4c 100644
--- a/dts/src/arm64/nvidia/tegra194.dtsi
+++ b/dts/src/arm64/nvidia/tegra194.dtsi
@@ -948,6 +948,10 @@
<&bpmp TEGRA194_CLK_XUSB_SS>,
<&bpmp TEGRA194_CLK_XUSB_FS>;
clock-names = "dev", "ss", "ss_src", "fs_src";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
power-domain-names = "dev", "ss";
@@ -977,6 +981,10 @@
"xusb_ss", "xusb_ss_src", "xusb_hs_src",
"xusb_fs_src", "pll_u_480m", "clk_m",
"pll_e";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
@@ -2469,6 +2477,11 @@
* for 8x and 11.025x sample rate streams.
*/
assigned-clock-rates = <258000000>;
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_APE>;
};
tcu: tcu {