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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-09 14:49:17 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 09:37:13 +0100 |
| commit | f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch) | |
| tree | dd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/src/arm64/nvidia/tegra194.dtsi | |
| parent | 0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff) | |
| download | barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz | |
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/nvidia/tegra194.dtsi')
| -rw-r--r-- | dts/src/arm64/nvidia/tegra194.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/dts/src/arm64/nvidia/tegra194.dtsi b/dts/src/arm64/nvidia/tegra194.dtsi index 25f36d6118..9449156fae 100644 --- a/dts/src/arm64/nvidia/tegra194.dtsi +++ b/dts/src/arm64/nvidia/tegra194.dtsi @@ -609,6 +609,34 @@ status = "disabled"; }; + spi@3270000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x3270000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA194_CLK_QSPI0>, + <&bpmp TEGRA194_CLK_QSPI0_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA194_RESET_QSPI0>; + reset-names = "qspi"; + status = "disabled"; + }; + + spi@3300000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x3300000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA194_CLK_QSPI1>, + <&bpmp TEGRA194_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA194_RESET_QSPI1>; + reset-names = "qspi"; + status = "disabled"; + }; + pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; @@ -2323,6 +2351,26 @@ method = "smc"; }; + sound { + status = "disabled"; + + clocks = <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>, + <&bpmp TEGRA194_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>; + /* + * PLLA supports dynamic ramp. Below initial rate is chosen + * for this to work and oscillate between base rates required + * for 8x and 11.025x sample rate streams. + */ + assigned-clock-rates = <258000000>; + }; + tcu: tcu { compatible = "nvidia,tegra194-tcu"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, |