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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-23 12:14:59 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-05 20:49:06 +0200 |
| commit | abef60363d8ecac66e45853f328afa8eeb9e00fd (patch) | |
| tree | c7d6f1dcf0ef5154b9182da86f1acad048cb7da1 /dts/src/arm64/qcom | |
| parent | e307bc559a2830b7f695150212ea1b26cdca69fb (diff) | |
| download | barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.gz barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.xz | |
dts: update to v5.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/qcom')
31 files changed, 3535 insertions, 801 deletions
diff --git a/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi deleted file mode 100644 index aff218c1b7..0000000000 --- a/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> - -&pm8916_gpios { - - usb_hub_reset_pm: usb_hub_reset_pm { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - input-disable; - output-high; - }; - }; - - usb_hub_reset_pm_device: usb_hub_reset_pm_device { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; - - usb_sw_sel_pm: usb_sw_sel_pm { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <PM8916_GPIO_VPH>; - input-disable; - output-high; - }; - }; - - usb_sw_sel_pm_device: usb_sw_sel_pm_device { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <PM8916_GPIO_VPH>; - input-disable; - output-low; - }; - }; - - pm8916_gpios_leds: pm8916_gpios_leds { - pinconf { - pins = "gpio1", "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; -}; - -&pm8916_mpps { - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f>; - - ls_exp_gpio_f: pm8916_mpp4 { - pinconf { - pins = "mpp4"; - function = "digital"; - output-low; - power-source = <PM8916_MPP_L5>; // 1.8V - }; - }; - - pm8916_mpps_leds: pm8916_mpps_leds { - pinconf { - pins = "mpp2", "mpp3"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi deleted file mode 100644 index 21d0822f1c..0000000000 --- a/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/gpio/gpio.h> - -&msmgpio { - - msmgpio_leds: msmgpio_leds { - pinconf { - pins = "gpio21", "gpio120"; - function = "gpio"; - output-low; - }; - }; - - usb_id_default: usb-id-default { - pinmux { - function = "gpio"; - pins = "gpio121"; - }; - - pinconf { - pins = "gpio121"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; - - adv7533_int_active: adv533_int_active { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_int_suspend: adv7533_int_suspend { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <2>; - bias-disable; - }; - }; - - adv7533_switch_active: adv7533_switch_active { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_switch_suspend: adv7533_switch_suspend { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <2>; - bias-disable; - }; - }; - - msm_key_volp_n_default: msm_key_volp_n_default { - pinmux { - function = "gpio"; - pins = "gpio107"; - }; - pinconf { - pins = "gpio107"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; -}; diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi index 06aab44d79..8a4b790aa7 100644 --- a/dts/src/arm64/qcom/apq8016-sbc.dtsi +++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi @@ -5,10 +5,10 @@ #include "msm8916.dtsi" #include "pm8916.dtsi" -#include "apq8016-sbc-soc-pins.dtsi" -#include "apq8016-sbc-pmic-pins.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include <dt-bindings/sound/apq8016-lpass.h> /* @@ -51,6 +51,30 @@ stdout-path = "serial0"; }; + camera_vdddo_1v8: camera-vdddo-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera-vdda-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera-vddd-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + reserved-memory { ramoops@bff00000{ compatible = "ramoops"; @@ -495,6 +519,27 @@ wcnss@a21b000 { status = "okay"; }; + + tpiu@820000 { status = "okay"; }; + funnel@821000 { status = "okay"; }; + replicator@824000 { status = "okay"; }; + etf@825000 { status = "okay"; }; + etr@826000 { status = "okay"; }; + funnel@841000 { status = "okay"; }; + debug@850000 { status = "okay"; }; + debug@852000 { status = "okay"; }; + debug@854000 { status = "okay"; }; + debug@856000 { status = "okay"; }; + etm@85c000 { status = "okay"; }; + etm@85d000 { status = "okay"; }; + etm@85e000 { status = "okay"; }; + etm@85f000 { status = "okay"; }; + cti@810000 { status = "okay"; }; + cti@811000 { status = "okay"; }; + cti@858000 { status = "okay"; }; + cti@859000 { status = "okay"; }; + cti@85a000 { status = "okay"; }; + cti@85b000 { status = "okay"; }; }; usb2513 { @@ -521,7 +566,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; @@ -538,6 +583,58 @@ }; }; +&camss { + status = "ok"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + status = "okay"; + }; + }; + }; +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + clock-frequency = <23880000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + /* No camera mezzanine by default */ + status = "disabled"; + + port { + ov5640_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + &spmi_bus { pm8916_0: pm8916@0 { pon@800 { @@ -680,3 +777,157 @@ regulator-max-microvolt = <3337000>; }; }; + +&msmgpio { + msmgpio_leds: msmgpio-leds { + pinconf { + pins = "gpio21", "gpio120"; + function = "gpio"; + output-low; + }; + }; + + usb_id_default: usb-id-default { + pinmux { + function = "gpio"; + pins = "gpio121"; + }; + + pinconf { + pins = "gpio121"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; + + adv7533_int_active: adv533-int-active { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_int_suspend: adv7533-int-suspend { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + adv7533_switch_active: adv7533-switch-active { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_switch_suspend: adv7533-switch-suspend { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + msm_key_volp_n_default: msm-key-volp-n-default { + pinmux { + function = "gpio"; + pins = "gpio107"; + }; + pinconf { + pins = "gpio107"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; +}; + +&pm8916_gpios { + usb_hub_reset_pm: usb-hub-reset-pm { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; + + usb_sw_sel_pm: usb-sw-sel-pm { + pinconf { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-high; + }; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device { + pinconf { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-low; + }; + }; + + pm8916_gpios_leds: pm8916-gpios-leds { + pinconf { + pins = "gpio1", "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; +}; + +&pm8916_mpps { + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8916-mpp4 { + pinconf { + pins = "mpp4"; + function = "digital"; + output-low; + power-source = <PM8916_MPP_L5>; // 1.8V + }; + }; + + pm8916_mpps_leds: pm8916-mpps-leds { + pinconf { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; + }; +}; diff --git a/dts/src/arm64/qcom/apq8096-db820c.dtsi b/dts/src/arm64/qcom/apq8096-db820c.dtsi index c4abbccf2b..defcbd15ed 100644 --- a/dts/src/arm64/qcom/apq8096-db820c.dtsi +++ b/dts/src/arm64/qcom/apq8096-db820c.dtsi @@ -117,16 +117,6 @@ regulator-max-microvolt = <3700000>; }; - vreg_s8a_l3a_input: vreg-s8a-l3a-input { - compatible = "regulator-fixed"; - regulator-name = "vreg_s8a_l3a_input"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - }; - wlan_en: wlan-en-1-8v { pinctrl-names = "default"; pinctrl-0 = <&wlan_en_gpios>; @@ -251,6 +241,10 @@ status = "okay"; }; +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + &msmgpio { gpio-line-names = "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ @@ -688,6 +682,15 @@ }; }; +&pmi8994_spmi_regulators { + vdd_gfx: s2@1700 { + reg = <0x1700 0x100>; + regulator-name = "VDD_GFX"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; @@ -704,15 +707,20 @@ vdd_s10-supply = <&vph_pwr>; vdd_s11-supply = <&vph_pwr>; vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p025>; vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s8a_l3a_input>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; vdd_l5_l7-supply = <&vreg_s5a_2p15>; vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; vreg_s3a_1p3: s3 { regulator-name = "vreg_s3a_1p3"; @@ -895,6 +903,27 @@ regulator-name = "vreg_lvs2a_1p8"; }; }; + + pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vph_pwr_bbyp: boost-bypass { + regulator-name = "vph_pwr_bbyp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_s1b_1p025: s1 { + regulator-name = "vreg_s1b_1p025"; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + }; }; &sdhc2 { diff --git a/dts/src/arm64/qcom/ipq8074-hk01.dts b/dts/src/arm64/qcom/ipq8074-hk01.dts index 70be3f9520..6754cb0638 100644 --- a/dts/src/arm64/qcom/ipq8074-hk01.dts +++ b/dts/src/arm64/qcom/ipq8074-hk01.dts @@ -24,63 +24,61 @@ device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; +}; + +&blsp1_i2c2 { + status = "ok"; +}; + +&blsp1_spi1 { + status = "ok"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; + +&blsp1_uart5 { + status = "ok"; +}; + +&pcie0 { + status = "ok"; + perst-gpio = <&tlmm 61 0x1>; +}; + +&pcie1 { + status = "ok"; + perst-gpio = <&tlmm 58 0x1>; +}; + +&pcie_phy0 { + status = "ok"; +}; + +&pcie_phy1 { + status = "ok"; +}; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; - soc { - serial@78b3000 { - status = "ok"; - }; - - spi@78b5000 { - status = "ok"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - serial@78b1000 { - status = "ok"; - }; - - i2c@78b6000 { - status = "ok"; - }; - - dma@7984000 { - status = "ok"; - }; - - nand@79b0000 { - status = "ok"; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - phy@86000 { - status = "ok"; - }; - - phy@8e000 { - status = "ok"; - }; - - pci@20000000 { - status = "ok"; - perst-gpio = <&tlmm 58 0x1>; - }; - - pci@10000000 { - status = "ok"; - perst-gpio = <&tlmm 61 0x1>; - }; + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; }; }; diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi index 2b31823d3c..5303821300 100644 --- a/dts/src/arm64/qcom/ipq8074.dtsi +++ b/dts/src/arm64/qcom/ipq8074.dtsi @@ -10,15 +10,111 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + pcie_phy0: phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x00086000 0x1000>; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + + pcie_phy1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x0008e000 0x1000>; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq8074-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; gpio-ranges = <&tlmm 0 0 70>; @@ -66,102 +162,16 @@ }; }; - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0xb000000 0x1000>, <0xb002000 0x1000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; - clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xb128000 0x1000>; - status = "disabled"; - }; - }; - gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; #clock-cells = <0x1>; #reset-cells = <0x1>; }; - blsp1_uart5: serial@78b3000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b3000 0x200>; - interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-0 = <&serial_4_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - blsp_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x7884000 0x2b000>; + reg = <0x07884000 0x2b000>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; @@ -171,7 +181,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -181,7 +191,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b1000 0x200>; + reg = <0x078b1000 0x200>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -194,11 +204,23 @@ status = "disabled"; }; + blsp1_uart5: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b3000 0x200>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b5000 0x600>; + reg = <0x078b5000 0x600>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, @@ -215,7 +237,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b6000 0x600>; + reg = <0x078b6000 0x600>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; @@ -232,7 +254,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b7000 0x600>; + reg = <0x078b7000 0x600>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; @@ -245,7 +267,7 @@ qpic_bam: dma@7984000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1a000>; + reg = <0x07984000 0x1a000>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QPIC_AHB_CLK>; clock-names = "bam_clk"; @@ -256,7 +278,7 @@ qpic_nand: nand@79b0000 { compatible = "qcom,ipq8074-nand"; - reg = <0x79b0000 0x10000>; + reg = <0x079b0000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QPIC_CLK>, @@ -272,104 +294,85 @@ status = "disabled"; }; - pcie_phy0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x86000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy0_pipe_clk"; + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x20000000 0xf1d - 0x20000f20 0xa8 - 0x80000 0x2000 - 0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; - phys = <&pcie_phy0>; - phy-names = "pciephy"; + frame@b120000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; - ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ + frame@b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; + frame@b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; + frame@b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; - pcie_phy1: phy@8e000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x8e000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy1_pipe_clk"; + frame@b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b127000 0x1000>; + status = "disabled"; + }; - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; + frame@b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; }; pcie1: pci@10000000 { compatible = "qcom,pcie-ipq8074"; reg = <0x10000000 0xf1d 0x10000f20 0xa8 - 0x88000 0x2000 + 0x00088000 0x2000 0x10100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; @@ -426,71 +429,68 @@ "axi_m_sticky"; status = "disabled"; }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - next-level-cache = <&L2_0>; - }; - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - next-level-cache = <&L2_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; - next-level-cache = <&L2_0>; - }; + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x20000000 0xf1d + 0x20000f20 0xa8 + 0x00080000 0x2000 + 0x20100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; + phys = <&pcie_phy0>; + phy-names = "pciephy"; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; + ranges = <0x81000000 0 0x20200000 0x20200000 + 0 0x100000 /* downstream I/O */ + 0x82000000 0 0x20300000 0x20300000 + 0 0xd00000>; /* non-prefetchable memory */ - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky"; + status = "disabled"; }; }; }; diff --git a/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts b/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts index d1ccb9472c..d5230cb76e 100644 --- a/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts +++ b/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts @@ -82,29 +82,6 @@ wcnss@a21b000 { status = "okay"; }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; }; // FIXME: Use extcon device provided by charger driver when available @@ -132,7 +109,7 @@ }; &msmgpio { - gpio_keys_default: gpio_keys_default { + gpio_keys_default: gpio-keys-default { pinmux { function = "gpio"; pins = "gpio107"; diff --git a/dts/src/arm64/qcom/msm8916-pins.dtsi b/dts/src/arm64/qcom/msm8916-pins.dtsi index 242aaea688..e9c00367f7 100644 --- a/dts/src/arm64/qcom/msm8916-pins.dtsi +++ b/dts/src/arm64/qcom/msm8916-pins.dtsi @@ -5,7 +5,7 @@ &msmgpio { - blsp1_uart1_default: blsp1_uart1_default { + blsp1_uart1_default: blsp1-uart1-default { pinmux { function = "blsp_uart1"; // TX, RX, CTS_N, RTS_N @@ -20,7 +20,7 @@ }; }; - blsp1_uart1_sleep: blsp1_uart1_sleep { + blsp1_uart1_sleep: blsp1-uart1-sleep { pinmux { function = "gpio"; pins = "gpio0", "gpio1", @@ -34,7 +34,7 @@ }; }; - blsp1_uart2_default: blsp1_uart2_default { + blsp1_uart2_default: blsp1-uart2-default { pinmux { function = "blsp_uart2"; pins = "gpio4", "gpio5"; @@ -46,7 +46,7 @@ }; }; - blsp1_uart2_sleep: blsp1_uart2_sleep { + blsp1_uart2_sleep: blsp1-uart2-sleep { pinmux { function = "gpio"; pins = "gpio4", "gpio5"; @@ -58,12 +58,12 @@ }; }; - spi1_default: spi1_default { + spi1_default: spi1-default { pinmux { function = "blsp_spi1"; pins = "gpio0", "gpio1", "gpio3"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio2"; }; @@ -72,7 +72,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio2"; drive-strength = <16>; bias-disable; @@ -80,7 +80,7 @@ }; }; - spi1_sleep: spi1_sleep { + spi1_sleep: spi1-sleep { pinmux { function = "gpio"; pins = "gpio0", "gpio1", "gpio2", "gpio3"; @@ -92,12 +92,12 @@ }; }; - spi2_default: spi2_default { + spi2_default: spi2-default { pinmux { function = "blsp_spi2"; pins = "gpio4", "gpio5", "gpio7"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio6"; }; @@ -106,7 +106,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio6"; drive-strength = <16>; bias-disable; @@ -114,7 +114,7 @@ }; }; - spi2_sleep: spi2_sleep { + spi2_sleep: spi2-sleep { pinmux { function = "gpio"; pins = "gpio4", "gpio5", "gpio6", "gpio7"; @@ -126,12 +126,12 @@ }; }; - spi3_default: spi3_default { + spi3_default: spi3-default { pinmux { function = "blsp_spi3"; pins = "gpio8", "gpio9", "gpio11"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio10"; }; @@ -140,7 +140,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio10"; drive-strength = <16>; bias-disable; @@ -148,7 +148,7 @@ }; }; - spi3_sleep: spi3_sleep { + spi3_sleep: spi3-sleep { pinmux { function = "gpio"; pins = "gpio8", "gpio9", "gpio10", "gpio11"; @@ -160,12 +160,12 @@ }; }; - spi4_default: spi4_default { + spi4_default: spi4-default { pinmux { function = "blsp_spi4"; pins = "gpio12", "gpio13", "gpio15"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio14"; }; @@ -174,7 +174,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio14"; drive-strength = <16>; bias-disable; @@ -182,7 +182,7 @@ }; }; - spi4_sleep: spi4_sleep { + spi4_sleep: spi4-sleep { pinmux { function = "gpio"; pins = "gpio12", "gpio13", "gpio14", "gpio15"; @@ -194,12 +194,12 @@ }; }; - spi5_default: spi5_default { + spi5_default: spi5-default { pinmux { function = "blsp_spi5"; pins = "gpio16", "gpio17", "gpio19"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio18"; }; @@ -208,7 +208,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio18"; drive-strength = <16>; bias-disable; @@ -216,7 +216,7 @@ }; }; - spi5_sleep: spi5_sleep { + spi5_sleep: spi5-sleep { pinmux { function = "gpio"; pins = "gpio16", "gpio17", "gpio18", "gpio19"; @@ -228,12 +228,12 @@ }; }; - spi6_default: spi6_default { + spi6_default: spi6-default { pinmux { function = "blsp_spi6"; pins = "gpio20", "gpio21", "gpio23"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio22"; }; @@ -242,7 +242,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio22"; drive-strength = <16>; bias-disable; @@ -250,7 +250,7 @@ }; }; - spi6_sleep: spi6_sleep { + spi6_sleep: spi6-sleep { pinmux { function = "gpio"; pins = "gpio20", "gpio21", "gpio22", "gpio23"; @@ -262,7 +262,31 @@ }; }; - i2c2_default: i2c2_default { + i2c1_default: i2c1-default { + pinmux { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c1_sleep: i2c1-sleep { + pinmux { + function = "gpio"; + pins = "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c2_default: i2c2-default { pinmux { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; @@ -274,7 +298,7 @@ }; }; - i2c2_sleep: i2c2_sleep { + i2c2_sleep: i2c2-sleep { pinmux { function = "gpio"; pins = "gpio6", "gpio7"; @@ -286,7 +310,7 @@ }; }; - i2c4_default: i2c4_default { + i2c4_default: i2c4-default { pinmux { function = "blsp_i2c4"; pins = "gpio14", "gpio15"; @@ -298,7 +322,7 @@ }; }; - i2c4_sleep: i2c4_sleep { + i2c4_sleep: i2c4-sleep { pinmux { function = "gpio"; pins = "gpio14", "gpio15"; @@ -310,7 +334,31 @@ }; }; - i2c6_default: i2c6_default { + i2c5_default: i2c5-default { + pinmux { + function = "blsp_i2c5"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c5_sleep: i2c5-sleep { + pinmux { + function = "gpio"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c6_default: i2c6-default { pinmux { function = "blsp_i2c6"; pins = "gpio22", "gpio23"; @@ -322,7 +370,7 @@ }; }; - i2c6_sleep: i2c6_sleep { + i2c6_sleep: i2c6-sleep { pinmux { function = "gpio"; pins = "gpio22", "gpio23"; @@ -334,8 +382,8 @@ }; }; - pmx_sdc1_clk { - sdc1_clk_on: clk_on { + pmx-sdc1-clk { + sdc1_clk_on: clk-on { pinmux { pins = "sdc1_clk"; }; @@ -345,7 +393,7 @@ drive-strength = <16>; }; }; - sdc1_clk_off: clk_off { + sdc1_clk_off: clk-off { pinmux { pins = "sdc1_clk"; }; @@ -357,8 +405,8 @@ }; }; - pmx_sdc1_cmd { - sdc1_cmd_on: cmd_on { + pmx-sdc1-cmd { + sdc1_cmd_on: cmd-on { pinmux { pins = "sdc1_cmd"; }; @@ -368,7 +416,7 @@ drive-strength = <10>; }; }; - sdc1_cmd_off: cmd_off { + sdc1_cmd_off: cmd-off { pinmux { pins = "sdc1_cmd"; }; @@ -380,8 +428,8 @@ }; }; - pmx_sdc1_data { - sdc1_data_on: data_on { + pmx-sdc1-data { + sdc1_data_on: data-on { pinmux { pins = "sdc1_data"; }; @@ -391,7 +439,7 @@ drive-strength = <10>; }; }; - sdc1_data_off: data_off { + sdc1_data_off: data-off { pinmux { pins = "sdc1_data"; }; @@ -403,8 +451,8 @@ }; }; - pmx_sdc2_clk { - sdc2_clk_on: clk_on { + pmx-sdc2-clk { + sdc2_clk_on: clk-on { pinmux { pins = "sdc2_clk"; }; @@ -414,7 +462,7 @@ drive-strength = <16>; }; }; - sdc2_clk_off: clk_off { + sdc2_clk_off: clk-off { pinmux { pins = "sdc2_clk"; }; @@ -426,8 +474,8 @@ }; }; - pmx_sdc2_cmd { - sdc2_cmd_on: cmd_on { + pmx-sdc2-cmd { + sdc2_cmd_on: cmd-on { pinmux { pins = "sdc2_cmd"; }; @@ -437,7 +485,7 @@ drive-strength = <10>; }; }; - sdc2_cmd_off: cmd_off { + sdc2_cmd_off: cmd-off { pinmux { pins = "sdc2_cmd"; }; @@ -449,8 +497,8 @@ }; }; - pmx_sdc2_data { - sdc2_data_on: data_on { + pmx-sdc2-data { + sdc2_data_on: data-on { pinmux { pins = "sdc2_data"; }; @@ -460,7 +508,7 @@ drive-strength = <10>; }; }; - sdc2_data_off: data_off { + sdc2_data_off: data-off { pinmux { pins = "sdc2_data"; }; @@ -472,8 +520,8 @@ }; }; - pmx_sdc2_cd_pin { - sdc2_cd_on: cd_on { + pmx-sdc2-cd-pin { + sdc2_cd_on: cd-on { pinmux { function = "gpio"; pins = "gpio38"; @@ -484,7 +532,7 @@ bias-pull-up; }; }; - sdc2_cd_off: cd_off { + sdc2_cd_off: cd-off { pinmux { function = "gpio"; pins = "gpio38"; @@ -498,7 +546,7 @@ }; cdc-pdm-lines { - cdc_pdm_lines_act: pdm_lines_on { + cdc_pdm_lines_act: pdm-lines-on { pinmux { function = "cdc_pdm0"; pins = "gpio63", "gpio64", "gpio65", "gpio66", @@ -511,7 +559,7 @@ bias-pull-none; }; }; - cdc_pdm_lines_sus: pdm_lines_off { + cdc_pdm_lines_sus: pdm-lines-off { pinmux { function = "cdc_pdm0"; pins = "gpio63", "gpio64", "gpio65", "gpio66", @@ -527,7 +575,7 @@ }; ext-pri-tlmm-lines { - ext_pri_tlmm_lines_act: ext_pa_on { + ext_pri_tlmm_lines_act: ext-pa-on { pinmux { function = "pri_mi2s"; pins = "gpio113", "gpio114", "gpio115", @@ -541,7 +589,7 @@ }; }; - ext_pri_tlmm_lines_sus: ext_pa_off { + ext_pri_tlmm_lines_sus: ext-pa-off { pinmux { function = "pri_mi2s"; pins = "gpio113", "gpio114", "gpio115", @@ -557,7 +605,7 @@ }; ext-pri-ws-line { - ext_pri_ws_act: ext_pa_on { + ext_pri_ws_act: ext-pa-on { pinmux { function = "pri_mi2s_ws"; pins = "gpio110"; @@ -569,7 +617,7 @@ }; }; - ext_pri_ws_sus: ext_pa_off { + ext_pri_ws_sus: ext-pa-off { pinmux { function = "pri_mi2s_ws"; pins = "gpio110"; @@ -583,7 +631,7 @@ }; ext-mclk-tlmm-lines { - ext_mclk_tlmm_lines_act: mclk_lines_on { + ext_mclk_tlmm_lines_act: mclk-lines-on { pinmux { function = "pri_mi2s"; pins = "gpio116"; @@ -594,7 +642,7 @@ bias-pull-none; }; }; - ext_mclk_tlmm_lines_sus: mclk_lines_off { + ext_mclk_tlmm_lines_sus: mclk-lines-off { pinmux { function = "pri_mi2s"; pins = "gpio116"; @@ -609,7 +657,7 @@ /* secondary Mi2S */ ext-sec-tlmm-lines { - ext_sec_tlmm_lines_act: tlmm_lines_on { + ext_sec_tlmm_lines_act: tlmm-lines-on { pinmux { function = "sec_mi2s"; pins = "gpio112", "gpio117", "gpio118", @@ -622,7 +670,7 @@ bias-pull-none; }; }; - ext_sec_tlmm_lines_sus: tlmm_lines_off { + ext_sec_tlmm_lines_sus: tlmm-lines-off { pinmux { function = "sec_mi2s"; pins = "gpio112", "gpio117", "gpio118", @@ -638,12 +686,12 @@ }; cdc-dmic-lines { - cdc_dmic_lines_act: dmic_lines_on { - pinmux_dmic0_clk { + cdc_dmic_lines_act: dmic-lines-on { + pinmux-dmic0-clk { function = "dmic0_clk"; pins = "gpio0"; }; - pinmux_dmic0_data { + pinmux-dmic0-data { function = "dmic0_data"; pins = "gpio1"; }; @@ -652,12 +700,12 @@ drive-strength = <8>; }; }; - cdc_dmic_lines_sus: dmic_lines_off { - pinmux_dmic0_clk { + cdc_dmic_lines_sus: dmic-lines-off { + pinmux-dmic0-clk { function = "dmic0_clk"; pins = "gpio0"; }; - pinmux_dmic0_data { + pinmux-dmic0-data { function = "dmic0_data"; pins = "gpio1"; }; @@ -674,7 +722,6 @@ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; }; - pinconf { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; drive-strength = <6>; @@ -682,7 +729,7 @@ }; }; - cci0_default: cci0_default { + cci0_default: cci0-default { pinmux { function = "cci_i2c"; pins = "gpio29", "gpio30"; @@ -694,64 +741,64 @@ }; }; - camera_front_default: camera_front_default { - pinmux_pwdn { + camera_front_default: camera-front-default { + pinmux-pwdn { function = "gpio"; pins = "gpio33"; }; - pinconf_pwdn { + pinconf-pwdn { pins = "gpio33"; drive-strength = <16>; bias-disable; }; - pinmux_rst { + pinmux-rst { function = "gpio"; pins = "gpio28"; }; - pinconf_rst { + pinconf-rst { pins = "gpio28"; drive-strength = <16>; bias-disable; }; - pinmux_mclk1 { + pinmux-mclk1 { function = "cam_mclk1"; pins = "gpio27"; }; - pinconf_mclk1 { + pinconf-mclk1 { pins = "gpio27"; drive-strength = <16>; bias-disable; }; }; - camera_rear_default: camera_rear_default { - pinmux_pwdn { + camera_rear_default: camera-rear-default { + pinmux-pwdn { function = "gpio"; pins = "gpio34"; }; - pinconf_pwdn { + pinconf-pwdn { pins = "gpio34"; drive-strength = <16>; bias-disable; }; - pinmux_rst { + pinmux-rst { function = "gpio"; pins = "gpio35"; }; - pinconf_rst { + pinconf-rst { pins = "gpio35"; drive-strength = <16>; bias-disable; }; - pinmux_mclk0 { + pinmux-mclk0 { function = "cam_mclk0"; pins = "gpio26"; }; - pinconf_mclk0 { + pinconf-mclk0 { pins = "gpio26"; drive-strength = <16>; bias-disable; diff --git a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi index 43c5e0f882..ea52adf07a 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi +++ b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi @@ -72,32 +72,27 @@ }; }; + mdss@1a00000 { + dsi@1a98000 { + #address-cells = <1>; + #size-cells = <0>; + + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; + }; + + dsi-phy@1a98300 { + vddio-supply = <&pm8916_l6>; + }; + }; + wcnss@a21b000 { status = "okay"; }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; }; gpio-keys { @@ -138,6 +133,19 @@ }; }; + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -160,7 +168,7 @@ }; &msmgpio { - gpio_keys_default: gpio_keys_default { + gpio_keys_default: gpio-keys-default { pinmux { function = "gpio"; pins = "gpio107", "gpio109"; @@ -172,7 +180,7 @@ }; }; - gpio_hall_sensor_default: gpio_hall_sensor_default { + gpio_hall_sensor_default: gpio-hall-sensor-default { pinmux { function = "gpio"; pins = "gpio52"; @@ -184,7 +192,7 @@ }; }; - muic_int_default: muic_int_default { + muic_int_default: muic-int-default { pinmux { function = "gpio"; pins = "gpio12"; @@ -195,6 +203,44 @@ bias-disable; }; }; + + tsp_en_default: tsp-en-default { + pinmux { + function = "gpio"; + pins = "gpio73"; + }; + pinconf { + pins = "gpio73"; + drive-strength = <2>; + bias-disable; + }; + }; + + pmx-mdss { + mdss_default: mdss-default { + pinmux { + function = "gpio"; + pins = "gpio25"; + }; + pinconf { + pins = "gpio25"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdss_sleep: mdss-sleep { + pinmux { + function = "gpio"; + pins = "gpio25"; + }; + pinconf { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; &smd_rpm_regulators { diff --git a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts index d10f7ac508..b46c872890 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts +++ b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts @@ -7,4 +7,58 @@ / { model = "Samsung Galaxy A3U (EUR)"; compatible = "samsung,a3u-eur", "qcom,msm8916"; + + reg_panel_vdd3: regulator-panel-vdd3 { + compatible = "regulator-fixed"; + regulator-name = "panel_vdd3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_vdd3_default>; + }; +}; + +&dsi0 { + panel@0 { + reg = <0>; + + compatible = "samsung,s6e88a0-ams452ef01"; + + vdd3-supply = <®_panel_vdd3>; + vci-supply = <&pm8916_l17>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1>; + }; + }; + }; +}; + +&msmgpio { + panel_vdd3_default: panel-vdd3-default { + pinmux { + function = "gpio"; + pins = "gpio9"; + }; + pinconf { + pins = "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; }; diff --git a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts index 6629a62113..a555db8f6b 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts +++ b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts @@ -9,8 +9,43 @@ compatible = "samsung,a5u-eur", "qcom,msm8916"; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms345l"; + + reg = <0x48>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + avdd-supply = <®_vdd_tsp>; + vdd-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; +}; + &pronto { iris { compatible = "qcom,wcn3680"; }; }; + +&msmgpio { + ts_int_default: ts-int-default { + pinmux { + function = "gpio"; + pins = "gpio13"; + }; + pinconf { + pins = "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi index a88a15f235..32bd140ac9 100644 --- a/dts/src/arm64/qcom/msm8916.dtsi +++ b/dts/src/arm64/qcom/msm8916.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/arm/coresight-cti-dt.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8916.h> #include <dt-bindings/reset/qcom,gcc-msm8916.h> @@ -165,6 +166,9 @@ min-residency-us = <2000>; local-timer-stop; }; + }; + + domain-idle-states { CLUSTER_RET: cluster-retention { compatible = "domain-idle-state"; @@ -188,31 +192,31 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu-pd0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD1: cpu-pd1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD2: cpu-pd2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD3: cpu-pd3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CLUSTER_PD: cluster-pd { + CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; @@ -261,7 +265,7 @@ thermal-sensors = <&tsens 4>; trips { - cpu2_3_alert0: trip-point@0 { + cpu2_3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -291,7 +295,7 @@ thermal-sensors = <&tsens 2>; trips { - gpu_alert0: trip-point@0 { + gpu_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -311,7 +315,7 @@ thermal-sensors = <&tsens 1>; trips { - cam_alert0: trip-point@0 { + cam_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "hot"; @@ -326,7 +330,7 @@ thermal-sensors = <&tsens 0>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <85000>; hysteresis = <2000>; type = "hot"; @@ -336,7 +340,7 @@ }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; @@ -354,17 +358,6 @@ }; }; - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - }; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -374,13 +367,13 @@ }; clocks { - xo_board: xo_board { + xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; - sleep_clk: sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -608,6 +601,21 @@ status = "disabled"; }; + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x500>; @@ -638,6 +646,21 @@ status = "disabled"; }; + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; @@ -955,6 +978,17 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&gpu_opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; }; mdss: mdss@1a00000 { @@ -1224,6 +1258,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { tpiu_in: endpoint { @@ -1240,6 +1276,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { #address-cells = <1>; #size-cells = <0>; @@ -1279,6 +1317,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + out-ports { #address-cells = <1>; #size-cells = <0>; @@ -1313,6 +1353,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { etf_in: endpoint { @@ -1337,6 +1379,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { etr_in: endpoint { @@ -1353,6 +1397,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { #address-cells = <1>; #size-cells = <0>; @@ -1398,6 +1444,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU0>; + status = "disabled"; }; debug@852000 { @@ -1406,6 +1453,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU1>; + status = "disabled"; }; debug@854000 { @@ -1414,6 +1462,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU2>; + status = "disabled"; }; debug@856000 { @@ -1422,9 +1471,10 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU3>; + status = "disabled"; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1434,6 +1484,8 @@ cpu = <&CPU0>; + status = "disabled"; + out-ports { port { etm0_out: endpoint { @@ -1443,7 +1495,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1453,6 +1505,8 @@ cpu = <&CPU1>; + status = "disabled"; + out-ports { port { etm1_out: endpoint { @@ -1462,7 +1516,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1472,6 +1526,8 @@ cpu = <&CPU2>; + status = "disabled"; + out-ports { port { etm2_out: endpoint { @@ -1481,7 +1537,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1491,6 +1547,8 @@ cpu = <&CPU3>; + status = "disabled"; + out-ports { port { etm3_out: endpoint { @@ -1500,6 +1558,93 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + status = "disabled"; + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + + status = "disabled"; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + + status = "disabled"; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + + status = "disabled"; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; @@ -1601,6 +1746,33 @@ #size-cells = <0>; }; }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; smd { @@ -1611,7 +1783,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-msm8916"; qcom,smd-channels = "rpm_requests"; diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi index 98634d5c44..9951286db7 100644 --- a/dts/src/arm64/qcom/msm8996.dtsi +++ b/dts/src/arm64/qcom/msm8996.dtsi @@ -639,7 +639,7 @@ "mem", "mem_iface"; - power-domains = <&mmcc GPU_GDSC>; + power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; nvmem-cells = <&gpu_speed_bin>; @@ -989,16 +989,16 @@ "csi_clk_mux", "vfe0", "vfe1"; - interrupts = <GIC_SPI 78 0>, - <GIC_SPI 79 0>, - <GIC_SPI 80 0>, - <GIC_SPI 296 0>, - <GIC_SPI 297 0>, - <GIC_SPI 298 0>, - <GIC_SPI 299 0>, - <GIC_SPI 309 0>, - <GIC_SPI 314 0>, - <GIC_SPI 315 0>; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy0", "csiphy1", "csiphy2", @@ -1093,6 +1093,43 @@ }; }; + cci: cci@a0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; + power-domains = <&mmcc CAMSS_GDSC>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default &cci1_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + adreno_smmu: iommu@b40000 { compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; reg = <0x00b40000 0x10000>; @@ -2180,7 +2217,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2201,7 +2238,7 @@ thermal-sensors = <&tsens0 5>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2222,7 +2259,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2243,7 +2280,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2264,7 +2301,7 @@ thermal-sensors = <&tsens1 6>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2279,7 +2316,7 @@ thermal-sensors = <&tsens1 7>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2294,7 +2331,7 @@ thermal-sensors = <&tsens0 1>; trips { - m4m_alert0: trip-point@0 { + m4m_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2309,7 +2346,7 @@ thermal-sensors = <&tsens0 2>; trips { - l3_or_venus_alert0: trip-point@0 { + l3_or_venus_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2324,7 +2361,7 @@ thermal-sensors = <&tsens0 7>; trips { - cluster0_l2_alert0: trip-point@0 { + cluster0_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2339,7 +2376,7 @@ thermal-sensors = <&tsens0 12>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2354,7 +2391,7 @@ thermal-sensors = <&tsens1 1>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2369,7 +2406,7 @@ thermal-sensors = <&tsens1 2>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2384,7 +2421,7 @@ thermal-sensors = <&tsens1 3>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2399,7 +2436,7 @@ thermal-sensors = <&tsens1 4>; trips { - modemtx_alert0: trip-point@0 { + modemtx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/msm8998.dtsi b/dts/src/arm64/qcom/msm8998.dtsi index c07fee6fd7..c458706009 100644 --- a/dts/src/arm64/qcom/msm8998.dtsi +++ b/dts/src/arm64/qcom/msm8998.dtsi @@ -500,7 +500,7 @@ thermal-sensors = <&tsens0 1>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -521,7 +521,7 @@ thermal-sensors = <&tsens0 2>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -542,7 +542,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -563,7 +563,7 @@ thermal-sensors = <&tsens0 4>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -584,7 +584,7 @@ thermal-sensors = <&tsens0 7>; trips { - cpu4_alert0: trip-point@0 { + cpu4_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -605,7 +605,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu5_alert0: trip-point@0 { + cpu5_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -626,7 +626,7 @@ thermal-sensors = <&tsens0 9>; trips { - cpu6_alert0: trip-point@0 { + cpu6_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -647,7 +647,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu7_alert0: trip-point@0 { + cpu7_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -668,7 +668,7 @@ thermal-sensors = <&tsens0 12>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -683,7 +683,7 @@ thermal-sensors = <&tsens0 13>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -698,7 +698,7 @@ thermal-sensors = <&tsens0 5>; trips { - cluster0_mhm_alert0: trip-point@0 { + cluster0_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -713,7 +713,7 @@ thermal-sensors = <&tsens0 6>; trips { - cluster1_mhm_alert0: trip-point@0 { + cluster1_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -728,7 +728,7 @@ thermal-sensors = <&tsens0 11>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -743,7 +743,7 @@ thermal-sensors = <&tsens1 1>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -758,7 +758,7 @@ thermal-sensors = <&tsens1 2>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -773,7 +773,7 @@ thermal-sensors = <&tsens1 3>; trips { - wlan_alert0: trip-point@0 { + wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -788,7 +788,7 @@ thermal-sensors = <&tsens1 4>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -803,7 +803,7 @@ thermal-sensors = <&tsens1 5>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -818,7 +818,7 @@ thermal-sensors = <&tsens1 6>; trips { - multimedia_alert0: trip-point@0 { + multimedia_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/pm8150.dtsi b/dts/src/arm64/qcom/pm8150.dtsi index b6e304748a..c0b1974586 100644 --- a/dts/src/arm64/qcom/pm8150.dtsi +++ b/dts/src/arm64/qcom/pm8150.dtsi @@ -73,18 +73,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x0 0xc0 0x0 IRQ_TYPE_NONE>, - <0x0 0xc1 0x0 IRQ_TYPE_NONE>, - <0x0 0xc2 0x0 IRQ_TYPE_NONE>, - <0x0 0xc3 0x0 IRQ_TYPE_NONE>, - <0x0 0xc4 0x0 IRQ_TYPE_NONE>, - <0x0 0xc5 0x0 IRQ_TYPE_NONE>, - <0x0 0xc6 0x0 IRQ_TYPE_NONE>, - <0x0 0xc7 0x0 IRQ_TYPE_NONE>, - <0x0 0xc8 0x0 IRQ_TYPE_NONE>, - <0x0 0xc9 0x0 IRQ_TYPE_NONE>, - <0x0 0xca 0x0 IRQ_TYPE_NONE>, - <0x0 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/dts/src/arm64/qcom/pm8150b.dtsi b/dts/src/arm64/qcom/pm8150b.dtsi index 322379d5c3..40b5d75a4a 100644 --- a/dts/src/arm64/qcom/pm8150b.dtsi +++ b/dts/src/arm64/qcom/pm8150b.dtsi @@ -62,18 +62,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>, - <0x2 0xc1 0x0 IRQ_TYPE_NONE>, - <0x2 0xc2 0x0 IRQ_TYPE_NONE>, - <0x2 0xc3 0x0 IRQ_TYPE_NONE>, - <0x2 0xc4 0x0 IRQ_TYPE_NONE>, - <0x2 0xc5 0x0 IRQ_TYPE_NONE>, - <0x2 0xc6 0x0 IRQ_TYPE_NONE>, - <0x2 0xc7 0x0 IRQ_TYPE_NONE>, - <0x2 0xc8 0x0 IRQ_TYPE_NONE>, - <0x2 0xc9 0x0 IRQ_TYPE_NONE>, - <0x2 0xca 0x0 IRQ_TYPE_NONE>, - <0x2 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/dts/src/arm64/qcom/pm8150l.dtsi b/dts/src/arm64/qcom/pm8150l.dtsi index eb0e9a090e..cf05e0685d 100644 --- a/dts/src/arm64/qcom/pm8150l.dtsi +++ b/dts/src/arm64/qcom/pm8150l.dtsi @@ -56,18 +56,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>, - <0x4 0xc1 0x0 IRQ_TYPE_NONE>, - <0x4 0xc2 0x0 IRQ_TYPE_NONE>, - <0x4 0xc3 0x0 IRQ_TYPE_NONE>, - <0x4 0xc4 0x0 IRQ_TYPE_NONE>, - <0x4 0xc5 0x0 IRQ_TYPE_NONE>, - <0x4 0xc6 0x0 IRQ_TYPE_NONE>, - <0x4 0xc7 0x0 IRQ_TYPE_NONE>, - <0x4 0xc8 0x0 IRQ_TYPE_NONE>, - <0x4 0xc9 0x0 IRQ_TYPE_NONE>, - <0x4 0xca 0x0 IRQ_TYPE_NONE>, - <0x4 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/dts/src/arm64/qcom/pmi8994.dtsi b/dts/src/arm64/qcom/pmi8994.dtsi index 21e05215ab..e5ed28ab9b 100644 --- a/dts/src/arm64/qcom/pmi8994.dtsi +++ b/dts/src/arm64/qcom/pmi8994.dtsi @@ -26,5 +26,11 @@ reg = <0x3 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmi8994_spmi_regulators: regulators { + compatible = "qcom,pmi8994-regulators"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/dts/src/arm64/qcom/qcs404-evb.dtsi b/dts/src/arm64/qcom/qcs404-evb.dtsi index afe69e8f31..6422cf9d58 100644 --- a/dts/src/arm64/qcom/qcs404-evb.dtsi +++ b/dts/src/arm64/qcom/qcs404-evb.dtsi @@ -4,6 +4,8 @@ #include <dt-bindings/gpio/gpio.h> #include "qcs404.dtsi" #include "pms405.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { aliases { @@ -31,6 +33,21 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + + /* TODO: Drop this when introducing role switching */ + regulator-always-on; + }; }; &blsp1_uart3 { @@ -186,7 +203,7 @@ }; vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; + regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; }; @@ -270,6 +287,72 @@ bias-pull-down; }; }; + + usb3_id_pin: usb3-id-pin { + pinmux { + pins = "gpio116"; + function = "gpio"; + }; + + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&pms405_gpios { + usb_vbus_boost_pin: usb-vbus-boost-pin { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; + usb3_vbus_pin: usb3-vbus-pin { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3 { + status = "okay"; + + dwc3@7580000 { + dr_mode = "host"; + }; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + status = "okay"; }; &wifi { diff --git a/dts/src/arm64/qcom/qcs404.dtsi b/dts/src/arm64/qcom/qcs404.dtsi index f149a538c1..c685a16648 100644 --- a/dts/src/arm64/qcom/qcs404.dtsi +++ b/dts/src/arm64/qcom/qcs404.dtsi @@ -323,6 +323,48 @@ reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -486,6 +528,64 @@ }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, diff --git a/dts/src/arm64/qcom/sc7180-idp.dts b/dts/src/arm64/qcom/sc7180-idp.dts index 043c9b9b50..4e9149d82d 100644 --- a/dts/src/arm64/qcom/sc7180-idp.dts +++ b/dts/src/arm64/qcom/sc7180-idp.dts @@ -28,6 +28,59 @@ }; }; +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + * + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &aop_mem; +/delete-node/ &sec_apps_mem; +/delete-node/ &tz_mem; + +/* Increase the size from 2MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x84400000 0x0 0x800000>; +}; + +/ { + reserved-memory { + atf_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + mpss_mem: memory@86000000 { + reg = <0x0 0x86000000 0x0 0x8c00000>; + no-map; + }; + + camera_mem: memory@8ec00000 { + reg = <0x0 0x8ec00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8f600000 { + reg = <0 0x8f600000 0 0x500000>; + no-map; + }; + + wlan_mem: memory@94100000 { + reg = <0x0 0x94100000 0x0 0x200000>; + no-map; + }; + + mba_mem: memory@94400000 { + reg = <0x0 0x94400000 0x0 0x200000>; + no-map; + }; + }; +}; + &apps_rsc { pm6150-rpmh-regulators { compatible = "qcom,pm6150-rpmh-regulators"; @@ -256,6 +309,13 @@ status = "okay"; }; +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7180-mss-pil"; + iommus = <&apps_smmu 0x460 0x1>, <&apps_smmu 0x444 0x3>; + memory-region = <&mba_mem &mpss_mem>; +}; + &sdhc_1 { status = "okay"; @@ -310,9 +370,11 @@ vdda-pll-supply = <&vreg_l11a_1p8>; vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; - qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_15_PERCENT>; qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; }; &usb_1_qmpphy { diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi index 998f101ad6..31b9217bb5 100644 --- a/dts/src/arm64/qcom/sc7180.dtsi +++ b/dts/src/arm64/qcom/sc7180.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,gpucc-sc7180.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sc7180.h> +#include <dt-bindings/interconnect/qcom,sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/power/qcom-aoss-qmp.h> @@ -69,9 +70,30 @@ #size-cells = <2>; ranges; + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + + aop_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x20000>; + no-map; + }; + aop_cmd_db_mem: memory@80820000 { reg = <0x0 0x80820000 0x0 0x20000>; compatible = "qcom,cmd-db"; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; }; smem_mem: memory@80900000 { @@ -79,9 +101,18 @@ no-map; }; - venus_mem: memory@8f600000 { - reg = <0 0x8f600000 0 0x500000>; + tz_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x3900000>; + no-map; + }; + + rmtfs_mem: memory@84400000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x84400000 0x0 0x200000>; no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; }; }; @@ -91,9 +122,12 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; @@ -110,9 +144,12 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; @@ -126,9 +163,12 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; @@ -142,9 +182,12 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; @@ -158,9 +201,12 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; @@ -174,9 +220,12 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; @@ -190,9 +239,12 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; @@ -206,9 +258,12 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; @@ -255,6 +310,60 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + local-timer-stop; + }; + }; }; memory@80000000 { @@ -352,6 +461,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; psci { @@ -898,11 +1018,56 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sc7180-ipa"; + + iommus = <&apps_smmu 0x440 0x3>; + reg = <0 0x1e40000 0 0x7000>, + <0 0x1e47000 0 0x2000>, + <0 0x1e04000 0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, + <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + modem-remoteproc = <&remoteproc_mpss>; + + status = "disabled"; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0 0x01f40000 0 0x40000>; }; + tcsr_regs: syscon@1fc0000 { + compatible = "syscon"; + reg = <0 0x01fc0000 0 0x40000>; + }; + tlmm: pinctrl@3500000 { compatible = "qcom,sc7180-pinctrl"; reg = <0 0x03500000 0 0x300000>, @@ -1294,22 +1459,106 @@ }; }; - sdhc_2: sdhci@8804000 { - compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; - iommus = <&apps_smmu 0x80 0>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; - bus-width = <4>; + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; - status = "disabled"; + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; }; gpucc: clock-controller@5090000 { @@ -1326,6 +1575,554 @@ #power-domain-cells = <1>; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&swao_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&swao_replicator_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06b04000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + swao_funnel_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etf@6b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b05000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&swao_replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&swao_funnel_out>; + }; + }; + }; + }; + + replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b06000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_replicator_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + port { + swao_replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc7180-mpss-pas"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", + "mnoc_axi", "xo"; + + power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, + <&rpmhpd SC7180_CX>, + <&rpmhpd SC7180_MX>, + <&rpmhpd SC7180_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,spare-regs = <&tcsr_regs 0xb3e4>; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x80 0>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + + status = "disabled"; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1339,7 +2136,7 @@ }; usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sc7180-qusb2-phy"; + compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -1447,6 +2244,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; @@ -1475,6 +2276,9 @@ "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; memory-region = <&venus_mem>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; + interconnect-names = "video-mem", "cpu-cfg"; video-decoder { compatible = "venus-decoder"; @@ -1544,8 +2348,12 @@ clock-names = "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, <19200000>; interrupt-parent = <&mdss>; @@ -1657,8 +2465,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 15>, <17 497 98>, - <119 634 4>, <124 639 1>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; @@ -2011,8 +2818,8 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -2059,8 +2866,8 @@ }; cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -2107,8 +2914,8 @@ }; cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -2155,8 +2962,8 @@ }; cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -2203,8 +3010,8 @@ }; cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -2251,8 +3058,8 @@ }; cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -2299,8 +3106,8 @@ }; cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -2339,8 +3146,8 @@ }; cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -2379,8 +3186,8 @@ }; cpu8-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -2419,8 +3226,8 @@ }; cpu9-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -2459,8 +3266,8 @@ }; aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -2480,8 +3287,8 @@ }; cpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -2500,8 +3307,8 @@ }; cpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -2520,8 +3327,8 @@ }; gpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -2541,8 +3348,8 @@ }; gpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -2562,8 +3369,8 @@ }; aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -2583,8 +3390,8 @@ }; cwlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -2604,8 +3411,8 @@ }; audio-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -2625,8 +3432,8 @@ }; ddr-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -2646,8 +3453,8 @@ }; q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -2667,8 +3474,8 @@ }; camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -2688,8 +3495,8 @@ }; mdm-core-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -2709,8 +3516,8 @@ }; mdm-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -2730,8 +3537,8 @@ }; npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -2751,8 +3558,8 @@ }; video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 9>; diff --git a/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts b/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts new file mode 100644 index 0000000000..76533e8b20 --- /dev/null +++ b/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> + */ + +/dts-v1/; + +#include "sdm660.dtsi" + +/ { + model = "Xiaomi Redmi Note 7"; + compatible = "xiaomi,lavender", "qcom,sdm660"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@a0000000 { + compatible = "ramoops"; + reg = <0x0 0xa0000000 0x0 0x400000>; + console-size = <0x20000>; + record-size = <0x20000>; + ftrace-size = <0x0>; + pmsg-size = <0x20000>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; +}; diff --git a/dts/src/arm64/qcom/sdm660.dtsi b/dts/src/arm64/qcom/sdm660.dtsi new file mode 100644 index 0000000000..4abbdd03d1 --- /dev/null +++ b/dts/src/arm64/qcom/sdm660.dtsi @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, Craig Tatlor. + * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "cache"; + }; + L1_D_100: l1-dcache { + compatible = "cache"; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_101: l1-icache { + compatible = "cache"; + }; + L1_D_101: l1-dcache { + compatible = "cache"; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_102: l1-icache { + compatible = "cache"; + }; + L1_D_102: l1-dcache { + compatible = "cache"; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_103: l1-icache { + compatible = "cache"; + }; + L1_D_103: l1-dcache { + compatible = "cache"; + }; + }; + + CPU4: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + L1_I_0: l1-icache { + compatible = "cache"; + }; + L1_D_0: l1-dcache { + compatible = "cache"; + }; + }; + + CPU5: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_1: l1-icache { + compatible = "cache"; + }; + L1_D_1: l1-dcache { + compatible = "cache"; + }; + }; + + CPU6: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_2: l1-icache { + compatible = "cache"; + }; + L1_D_2: l1-dcache { + compatible = "cache"; + }; + }; + + CPU7: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_3: l1-icache { + compatible = "cache"; + }; + L1_D_3: l1-dcache { + compatible = "cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm"; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm660"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00100000 0x94000>; + }; + + tlmm: pinctrl@3100000 { + compatible = "qcom,sdm660-pinctrl"; + reg = <0x03100000 0x400000>, + <0x03500000 0x400000>, + <0x03900000 0x400000>; + reg-names = "south", "center", "north"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 114>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + pinmux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + spmi_bus: spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + blsp1_uart2: serial@c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x0c170000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, + <0x17b00000 0x100000>; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/dts/src/arm64/qcom/sdm845-cheza.dtsi b/dts/src/arm64/qcom/sdm845-cheza.dtsi index 9070be43a3..70466cc4b4 100644 --- a/dts/src/arm64/qcom/sdm845-cheza.dtsi +++ b/dts/src/arm64/qcom/sdm845-cheza.dtsi @@ -548,6 +548,8 @@ edp_brij_i2c: &i2c3 { clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; @@ -631,6 +633,11 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +&mss_pil { + iommus = <&apps_smmu 0x780 0x1>, + <&apps_smmu 0x724 0x3>; +}; + &pm8998_pwrkey { status = "disabled"; }; diff --git a/dts/src/arm64/qcom/sdm845-db845c.dts b/dts/src/arm64/qcom/sdm845-db845c.dts index 21fd6f8d57..c00797bd3b 100644 --- a/dts/src/arm64/qcom/sdm845-db845c.dts +++ b/dts/src/arm64/qcom/sdm845-db845c.dts @@ -112,6 +112,40 @@ // enable-active-high; }; + cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: reg_cam0_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: reg_cam3_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + pcie0_3p3v_dual: vldo-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VLDO_3V3"; @@ -412,6 +446,52 @@ }; &pm8998_gpio { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; + + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; @@ -570,6 +650,42 @@ }; &tlmm { + cam0_default: cam0_default { + rst { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3_default { + rst { + function = "gpio"; + pins = "gpio21"; + + drive-strength = <16>; + bias-disable; + }; + + mclk3 { + function = "cam_mclk"; + pins = "gpio16"; + + drive-strength = <16>; + bias-disable; + }; + }; + pcie0_default_state: pcie0-default { clkreq { pins = "gpio36"; @@ -863,3 +979,97 @@ bias-pull-up; }; }; + +&pm8998_gpio { + +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + // CAM0_RST_N + reset-gpios = <&tlmm 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + gpios = <&tlmm 13 0>, + <&tlmm 9 0>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + /* The &vreg_s4a_1p8 trace is powered on as a, + * so it is represented by a fixed regulator. + * + * The 2.8V vdda-supply and 1.2V vddd-supply regulators + * both have to be enabled through the power management + * gpios. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + status = "disable"; + + port { + ov8856_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 + <360000000 180000000>; + data-lanes = <1 2 3 4>; +// remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + +&cci_i2c1 { + camera@60 { + compatible = "ovti,ov7251"; + + // I2C address as per ov7251.txt linux documentation + reg = <0x60>; + + // CAM3_RST_N + enable-gpios = <&tlmm 21 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + gpios = <&tlmm 16 0>, + <&tlmm 21 0>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + /* The &vreg_s4a_1p8 trace always powered on. + * + * The 2.8V vdda-supply regulator is enabled when the + * vreg_s4a_1p8 trace is pulled high. + * It too is represented by a fixed regulator. + * + * No 1.2V vddd-supply regulator is used. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + + status = "disable"; + + port { + ov7251_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; +// remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; diff --git a/dts/src/arm64/qcom/sdm845-mtp.dts b/dts/src/arm64/qcom/sdm845-mtp.dts index 023e8b04c7..1372fe8601 100644 --- a/dts/src/arm64/qcom/sdm845-mtp.dts +++ b/dts/src/arm64/qcom/sdm845-mtp.dts @@ -13,7 +13,7 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; - compatible = "qcom,sdm845-mtp"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845"; aliases { serial0 = &uart9; diff --git a/dts/src/arm64/qcom/sdm845.dtsi b/dts/src/arm64/qcom/sdm845.dtsi index 8f926b5234..8eb5a31346 100644 --- a/dts/src/arm64/qcom/sdm845.dtsi +++ b/dts/src/arm64/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,camcc-sdm845.h> #include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,gpucc-sdm845.h> @@ -1761,6 +1762,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; + + iommus = <&apps_smmu 0x720 0x3>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; @@ -1813,6 +1816,42 @@ gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0-default { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -2970,7 +3009,7 @@ }; usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sdm845-qusb2-phy"; + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -2985,7 +3024,7 @@ }; usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sdm845-qusb2-phy"; + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -3097,6 +3136,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>, + <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3141,6 +3184,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>, + <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: dwc3@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; @@ -3194,6 +3241,61 @@ #reset-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; diff --git a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts index 51a670ad15..d03ca31907 100644 --- a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts +++ b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts @@ -480,6 +480,8 @@ &ufs_mem_hc { status = "okay"; + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; vcc-max-microamp = <600000>; }; @@ -577,3 +579,14 @@ }; }; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; diff --git a/dts/src/arm64/qcom/sm8250-mtp.dts b/dts/src/arm64/qcom/sm8250-mtp.dts index 224d0f1ea6..cff7a85890 100644 --- a/dts/src/arm64/qcom/sm8250-mtp.dts +++ b/dts/src/arm64/qcom/sm8250-mtp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8250.dtsi" / { @@ -18,6 +19,336 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p875: ldo5 { + regulator-name = "vreg_l5a_0p875"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p7: ldo7 { + regulator-name = "vreg_l7a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_0p75: ldo11 { + regulator-name = "vreg_l11a_0p75"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_ts_3p0: ldo13 { + regulator-name = "vreg_l13a_ts_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_11ad_io_1p8: ldo15 { + regulator-name = "vreg_l15a_11ad_io_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + vreg_s8c_1p3: smps8 { + regulator-name = "vreg_s8c_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_1p2: ldo2 { + regulator-name = "vreg_l2c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_0p92: ldo3 { + regulator-name = "vreg_l3c_0p92"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c_1p7: ldo4 { + regulator-name = "vreg_l4c_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_cam_vcm0_2p85: ldo7 { + regulator-name = "vreg_l7c_cam_vcm0_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_3p0: ldo10 { + regulator-name = "vreg_l10c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_l1f_cam_dvdd1_1p1: ldo1 { + regulator-name = "vreg_l1f_cam_dvdd1_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_cam_dvdd0_1p2: ldo2 { + regulator-name = "vreg_l2f_cam_dvdd0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_cam_dvdd2_1p05: ldo3 { + regulator-name = "vreg_l3f_cam_dvdd2_1p05"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5f_cam_avdd0_2p85: ldo5 { + regulator-name = "vreg_l5f_cam_avdd0_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f_cam_avdd1_2p85: ldo6 { + regulator-name = "vreg_l6f_cam_avdd1_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; }; &qupv3_id_1 { @@ -27,3 +358,23 @@ &uart2 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p875>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l9a_1p2>; + vdda-pll-max-microamp = <19000>; +}; diff --git a/dts/src/arm64/qcom/sm8250.dtsi b/dts/src/arm64/qcom/sm8250.dtsi index 891d83b2af..7050adba79 100644 --- a/dts/src/arm64/qcom/sm8250.dtsi +++ b/dts/src/arm64/qcom/sm8250.dtsi @@ -4,7 +4,9 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -304,6 +306,76 @@ }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8250-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8250-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -314,8 +386,8 @@ }; pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8250-pdc"; - reg = <0x0b220000 0x30000>, <0x17c000f0 0x60>; + compatible = "qcom,sm8250-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; @@ -362,6 +434,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8250-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; }; tcsr_mutex_regs: syscon@1f40000 { |