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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:30 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
| commit | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch) | |
| tree | dd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/src/arm64/renesas/r8a7795.dtsi | |
| parent | 625eea2765d94aee016cf25d9cabecde8eae0775 (diff) | |
| download | barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz | |
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/renesas/r8a7795.dtsi')
| -rw-r--r-- | dts/src/arm64/renesas/r8a7795.dtsi | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/dts/src/arm64/renesas/r8a7795.dtsi b/dts/src/arm64/renesas/r8a7795.dtsi index d842940b2f..fb9d08ad76 100644 --- a/dts/src/arm64/renesas/r8a7795.dtsi +++ b/dts/src/arm64/renesas/r8a7795.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7795 SoC * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7795-cpg-mssr.h> @@ -291,7 +288,7 @@ #size-cells = <2>; ranges; - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; @@ -528,6 +525,15 @@ status = "disabled"; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + i2c3: i2c@e66d0000 { #address-cells = <1>; #size-cells = <0>; @@ -2530,7 +2536,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2541,7 +2547,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2552,7 +2558,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; + reg = <0 0xfea30000 0 0x5000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |