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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:30 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
commit | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch) | |
tree | dd2cf14c56430d21079c794fa6e03d7f5d91070e /dts/src/arm64/renesas/r8a77995-draak.dts | |
parent | 625eea2765d94aee016cf25d9cabecde8eae0775 (diff) | |
download | barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz barebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.xz |
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/renesas/r8a77995-draak.dts')
-rw-r--r-- | dts/src/arm64/renesas/r8a77995-draak.dts | 133 |
1 files changed, 129 insertions, 4 deletions
diff --git a/dts/src/arm64/renesas/r8a77995-draak.dts b/dts/src/arm64/renesas/r8a77995-draak.dts index 9d73de8bc9..a8e8f2669d 100644 --- a/dts/src/arm64/renesas/r8a77995-draak.dts +++ b/dts/src/arm64/renesas/r8a77995-draak.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Draak board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Glider bvba - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; @@ -59,6 +56,27 @@ }; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -82,6 +100,12 @@ regulator-boot-on; regulator-always-on; }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -142,6 +166,11 @@ groups = "usb0"; function = "usb0"; }; + + vin4_pins_cvbs: vin4 { + groups = "vin4_data8", "vin4_sync", "vin4_clk"; + function = "vin4"; + }; }; &i2c0 { @@ -154,6 +183,77 @@ reg = <0x50>; pagesize = <8>; }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, link it to + * VIN4 here. + */ + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, leave HDMI + * not connected here. + */ + adv7612_out: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; + }; }; &i2c1 { @@ -167,6 +267,11 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x12_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + ports { port@0 { endpoint { @@ -246,3 +351,23 @@ timeout-sec = <60>; status = "okay"; }; + +&vin4 { + pinctrl-0 = <&vin4_pins_cvbs>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin4_in: endpoint { + remote-endpoint = <&adv7180_out>; + }; + }; + }; +}; |