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authorSascha Hauer <s.hauer@pengutronix.de>2020-08-17 08:16:38 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-08-17 09:51:44 +0200
commit0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb (patch)
tree21cddf4b49891b7df21cbe5e5dd358d4e44e031d /dts/src/arm64
parent8ef08db9ad225acbf7326493cc586bb14fd917f5 (diff)
downloadbarebox-0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb.tar.gz
barebox-0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb.tar.xz
dts: update to v5.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64')
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts19
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone-1.2.dts40
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi54
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts1
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-cpu-opp.dtsi79
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts1
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts38
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5.dtsi38
-rw-r--r--dts/src/arm64/altera/socfpga_stratix10.dtsi2
-rw-r--r--dts/src/arm64/amazon/alpine-v2-evp.dts (renamed from dts/src/arm64/al/alpine-v2-evp.dts)0
-rw-r--r--dts/src/arm64/amazon/alpine-v2.dtsi (renamed from dts/src/arm64/al/alpine-v2.dtsi)0
-rw-r--r--dts/src/arm64/amazon/alpine-v3-evp.dts24
-rw-r--r--dts/src/arm64/amazon/alpine-v3.dtsi408
-rw-r--r--dts/src/arm64/amlogic/meson-axg.dtsi6
-rw-r--r--dts/src/arm64/amlogic/meson-g12-common.dtsi55
-rw-r--r--dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts136
-rw-r--r--dts/src/arm64/amlogic/meson-g12b-w400.dtsi6
-rw-r--r--dts/src/arm64/amlogic/meson-gx-mali450.dtsi61
-rw-r--r--dts/src/arm64/amlogic/meson-gx.dtsi18
-rw-r--r--dts/src/arm64/amlogic/meson-gxbb.dtsi63
-rw-r--r--dts/src/arm64/amlogic/meson-gxl-mali.dtsi46
-rw-r--r--dts/src/arm64/amlogic/meson-gxl-s805x.dtsi17
-rw-r--r--dts/src/arm64/amlogic/meson-gxl.dtsi12
-rw-r--r--dts/src/arm64/amlogic/meson-gxm-wetek-core2.dts87
-rw-r--r--dts/src/arm64/amlogic/meson-gxm.dtsi45
-rw-r--r--dts/src/arm64/amlogic/meson-khadas-vim3.dtsi26
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts92
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts88
-rw-r--r--dts/src/arm64/exynos/exynos5433.dtsi53
-rw-r--r--dts/src/arm64/exynos/exynos7-espresso.dts6
-rw-r--r--dts/src/arm64/exynos/exynos7.dtsi111
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a.dtsi15
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-qds.dts85
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a.dtsi39
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a-qds.dts4
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a-rdb.dts8
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a.dtsi105
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a.dtsi103
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a.dtsi14
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi14
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a-qds.dts36
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a-rdb.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a.dtsi71
-rw-r--r--dts/src/arm64/freescale/imx8mm.dtsi26
-rw-r--r--dts/src/arm64/freescale/imx8mn-evk.dts96
-rw-r--r--dts/src/arm64/freescale/imx8mn-evk.dtsi6
-rw-r--r--dts/src/arm64/freescale/imx8mn.dtsi10
-rw-r--r--dts/src/arm64/freescale/imx8mp.dtsi24
-rw-r--r--dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi2
-rw-r--r--dts/src/arm64/freescale/imx8mq.dtsi40
-rw-r--r--dts/src/arm64/freescale/imx8qxp.dtsi10
-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts83
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi34
-rw-r--r--dts/src/arm64/hisilicon/hi6220-hikey.dts428
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi10
-rw-r--r--dts/src/arm64/intel/keembay-evm.dts37
-rw-r--r--dts/src/arm64/intel/keembay-soc.dtsi123
-rw-r--r--dts/src/arm64/intel/socfpga_agilex.dtsi79
-rw-r--r--dts/src/arm64/intel/socfpga_agilex_socdk.dts8
-rw-r--r--dts/src/arm64/marvell/armada-7040.dtsi28
-rw-r--r--dts/src/arm64/marvell/armada-8040.dtsi40
-rw-r--r--dts/src/arm64/marvell/armada-ap80x.dtsi18
-rw-r--r--dts/src/arm64/mediatek/mt6358.dtsi2
-rw-r--r--dts/src/arm64/mediatek/mt8173.dtsi4
-rw-r--r--dts/src/arm64/mediatek/mt8183-evb.dts4
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-krane-sku176.dts18
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi343
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui.dtsi788
-rw-r--r--dts/src/arm64/mediatek/mt8183.dtsi68
-rw-r--r--dts/src/arm64/microchip/sparx5.dtsi213
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb125.dts21
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb134.dts17
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb134_board.dtsi252
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb134_emmc.dts17
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb135.dts17
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb135_board.dtsi92
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb135_emmc.dts17
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb_common.dtsi19
-rw-r--r--dts/src/arm64/nvidia/tegra132-norrin.dts399
-rw-r--r--dts/src/arm64/nvidia/tegra132.dtsi205
-rw-r--r--dts/src/arm64/nvidia/tegra186-p2771-0000.dts111
-rw-r--r--dts/src/arm64/nvidia/tegra186-p3310.dtsi80
-rw-r--r--dts/src/arm64/nvidia/tegra186.dtsi124
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2888.dtsi125
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2972-0000.dts16
-rw-r--r--dts/src/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts331
-rw-r--r--dts/src/arm64/nvidia/tegra194-p3668-0000.dtsi290
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi280
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2180.dtsi46
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2371-2180.dts6
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2530.dtsi19
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2597.dtsi330
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2894.dtsi414
-rw-r--r--dts/src/arm64/nvidia/tegra210-p3450-0000.dts277
-rw-r--r--dts/src/arm64/nvidia/tegra210-smaug.dts171
-rw-r--r--dts/src/arm64/nvidia/tegra210.dtsi72
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi262
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk01.dts28
-rw-r--r--dts/src/arm64/qcom/ipq8074.dtsi189
-rw-r--r--dts/src/arm64/qcom/msm8916-longcheer-l8150.dts42
-rw-r--r--dts/src/arm64/qcom/msm8916-pins.dtsi861
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi150
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts20
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts20
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi31
-rw-r--r--dts/src/arm64/qcom/msm8992-bullhead-rev-101.dts245
-rw-r--r--dts/src/arm64/qcom/msm8992-msft-lumia-talkman.dts39
-rw-r--r--dts/src/arm64/qcom/msm8992-pins.dtsi90
-rw-r--r--dts/src/arm64/qcom/msm8992-xiaomi-libra.dts364
-rw-r--r--dts/src/arm64/qcom/msm8992.dtsi566
-rw-r--r--dts/src/arm64/qcom/msm8994-angler-rev-101.dts2
-rw-r--r--dts/src/arm64/qcom/msm8994-pins.dtsi30
-rw-r--r--dts/src/arm64/qcom/msm8994-smd-rpm.dtsi268
-rw-r--r--dts/src/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts13
-rw-r--r--dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi235
-rw-r--r--dts/src/arm64/qcom/msm8994.dtsi642
-rw-r--r--dts/src/arm64/qcom/msm8998-clamshell.dtsi2
-rw-r--r--dts/src/arm64/qcom/msm8998-lenovo-miix-630.dts5
-rw-r--r--dts/src/arm64/qcom/msm8998-mtp.dtsi2
-rw-r--r--dts/src/arm64/qcom/pm660.dtsi50
-rw-r--r--dts/src/arm64/qcom/pm660l.dtsi36
-rw-r--r--dts/src/arm64/qcom/pm8009.dtsi37
-rw-r--r--dts/src/arm64/qcom/pm8150.dtsi42
-rw-r--r--dts/src/arm64/qcom/pm8150b.dtsi44
-rw-r--r--dts/src/arm64/qcom/pm8150l.dtsi44
-rw-r--r--dts/src/arm64/qcom/pmi8998.dtsi12
-rw-r--r--dts/src/arm64/qcom/qcs404.dtsi15
-rw-r--r--dts/src/arm64/qcom/sc7180-idp.dts19
-rw-r--r--dts/src/arm64/qcom/sc7180.dtsi604
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts13
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-ganges.dtsi40
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts13
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts13
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts20
-rw-r--r--dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi136
-rw-r--r--dts/src/arm64/qcom/sdm630.dtsi1174
-rw-r--r--dts/src/arm64/qcom/sdm636-sony-xperia-ganges-mermaid.dts20
-rw-r--r--dts/src/arm64/qcom/sdm845-cheza.dtsi2
-rw-r--r--dts/src/arm64/qcom/sdm845-db845c.dts118
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi525
-rw-r--r--dts/src/arm64/qcom/sm8150-mtp.dts21
-rw-r--r--dts/src/arm64/qcom/sm8150.dtsi1038
-rw-r--r--dts/src/arm64/qcom/sm8250-mtp.dts30
-rw-r--r--dts/src/arm64/qcom/sm8250.dtsi1667
-rw-r--r--dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi758
-rw-r--r--dts/src/arm64/renesas/beacon-renesom-som.dtsi312
-rw-r--r--dts/src/arm64/renesas/cat875.dtsi1
-rw-r--r--dts/src/arm64/renesas/hihope-common.dtsi71
-rw-r--r--dts/src/arm64/renesas/hihope-rev2.dtsi86
-rw-r--r--dts/src/arm64/renesas/hihope-rev4.dtsi124
-rw-r--r--dts/src/arm64/renesas/hihope-rzg2-ex-lvds.dtsi52
-rw-r--r--dts/src/arm64/renesas/hihope-rzg2-ex.dtsi39
-rw-r--r--dts/src/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts29
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts43
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts6
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts15
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts20
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-rev2.dts37
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m.dts6
-rw-r--r--dts/src/arm64/renesas/r8a774a1.dtsi10
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts15
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts5
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts15
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts15
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n-rev2.dts41
-rw-r--r--dts/src/arm64/renesas/r8a774b1-hihope-rzg2n.dts6
-rw-r--r--dts/src/arm64/renesas/r8a774b1.dtsi10
-rw-r--r--dts/src/arm64/renesas/r8a774c0.dtsi6
-rw-r--r--dts/src/arm64/renesas/r8a774e1-hihope-rzg2h-ex.dts15
-rw-r--r--dts/src/arm64/renesas/r8a774e1-hihope-rzg2h.dts26
-rw-r--r--dts/src/arm64/renesas/r8a774e1.dtsi1664
-rw-r--r--dts/src/arm64/renesas/r8a77951.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a77960.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a77961.dtsi97
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a77970-eagle.dts67
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts67
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi17
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts67
-rw-r--r--dts/src/arm64/renesas/r8a77980-v3hsk.dts67
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi17
-rw-r--r--dts/src/arm64/renesas/r8a77990-ebisu.dts1
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-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi2
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi1
-rw-r--r--dts/src/arm64/rockchip/px30-evb.dts3
-rw-r--r--dts/src/arm64/rockchip/px30.dtsi7
-rw-r--r--dts/src/arm64/rockchip/rk3308.dtsi8
-rw-r--r--dts/src/arm64/rockchip/rk3326-odroid-go2.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3328-evb.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3328-roc-cc.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi25
-rw-r--r--dts/src/arm64/rockchip/rk3368-lion-haikou.dts8
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-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi8
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts4
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi2
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-hugsun-x99.dts8
-rw-r--r--dts/src/arm64/rockchip/rk3399-khadas-edge.dtsi10
-rw-r--r--dts/src/arm64/rockchip/rk3399-leez-p710.dts8
-rw-r--r--dts/src/arm64/rockchip/rk3399-nanopi4.dtsi6
-rw-r--r--dts/src/arm64/rockchip/rk3399-pinebook-pro.dts99
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts6
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi10
-rw-r--r--dts/src/arm64/rockchip/rk3399-roc-pc.dtsi22
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock-pi-4.dts8
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock960.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-rockpro64.dtsi20
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi4
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-rw-r--r--dts/src/arm64/rockchip/rk3399pro-rock-pi-n10.dts6
-rw-r--r--dts/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi206
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts2
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-ref.dts8
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-akebi96.dts2
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts2
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts8
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi2
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts10
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi38
-rw-r--r--dts/src/arm64/ti/k3-am65-mcu.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am65-wakeup.dtsi7
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts27
-rw-r--r--dts/src/arm64/ti/k3-am654.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-j721e-common-proc-board.dts171
-rw-r--r--dts/src/arm64/ti/k3-j721e-main.dtsi281
-rw-r--r--dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi7
-rw-r--r--dts/src/arm64/ti/k3-j721e-som-p0.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-j721e.dtsi2
233 files changed, 19603 insertions, 3613 deletions
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts b/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts
index 06a775c416..3e99a87e9c 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts
@@ -9,3 +9,22 @@
model = "Pine64 PinePhone Braveheart (1.1)";
compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
};
+
+&backlight {
+ power-supply = <&reg_ldo_io0>;
+ /*
+ * PWM backlight circuit on this PinePhone revision was changed since
+ * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
+ * being off is around 20%. Duty cycle for the lowest brightness level
+ * also varries quite a bit between individual boards, so the lowest
+ * value here was chosen as a safe default.
+ */
+ brightness-levels = <
+ 774 793 814 842
+ 882 935 1003 1088
+ 1192 1316 1462 1633
+ 1830 2054 2309 2596
+ 2916 3271 3664 4096>;
+ num-interpolated-steps = <50>;
+ default-brightness-level = <400>;
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.2.dts b/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.2.dts
new file mode 100644
index 0000000000..a9f5b670c9
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-pinephone-1.2.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+ model = "Pine64 PinePhone (1.2)";
+ compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64";
+};
+
+&backlight {
+ power-supply = <&reg_ldo_io0>;
+ /*
+ * PWM backlight circuit on this PinePhone revision was changed since 1.0,
+ * and the lowest PWM duty cycle that doesn't lead to backlight being off
+ * is around 10%. Duty cycle for the lowest brightness level also varries
+ * quite a bit between individual boards, so the lowest value here was
+ * chosen as a safe default.
+ */
+ brightness-levels = <
+ 5000 5248 5506 5858 6345
+ 6987 7805 8823 10062 11543
+ 13287 15317 17654 20319 23336
+ 26724 30505 34702 39335 44427
+ 50000
+ >;
+ num-interpolated-steps = <50>;
+ default-brightness-level = <500>;
+};
+
+&lis3mdl {
+ /*
+ * Board revision 1.2 fixed routing of the interrupt to DRDY pin,
+ * enable interrupts.
+ */
+ interrupt-parent = <&pio>;
+ interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi b/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
index cefda145c3..25150aba74 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
@@ -16,6 +16,13 @@
serial0 = &uart0;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
+ enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ /* Backlight configuration differs per PinePhone revision. */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -84,6 +91,28 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
+&dphy {
+ status = "okay";
+};
+
+&dsi {
+ vcc-dsi-supply = <&reg_dldo1>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "xingbangda,xbd599";
+ reg = <0>;
+ reset-gpios = <&pio 3 23 GPIO_ACTIVE_LOW>; /* PD23 */
+ iovcc-supply = <&reg_dldo2>;
+ vcc-supply = <&reg_ldo_io0>;
+ backlight = <&backlight>;
+ };
+};
+
&ehci0 {
status = "okay";
};
@@ -92,11 +121,28 @@
status = "okay";
};
+&i2c0 {
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt917s";
+ reg = <0x5d>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */
+ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ AVDD28-supply = <&reg_ldo_io0>;
+ VDDIO-supply = <&reg_ldo_io0>;
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1440>;
+ };
+};
+
&i2c1 {
status = "okay";
/* Magnetometer */
- lis3mdl@1e {
+ lis3mdl: lis3mdl@1e {
compatible = "st,lis3mdl-magn";
reg = <0x1e>;
vdd-supply = <&reg_dldo1>;
@@ -188,6 +234,10 @@
*/
};
+&r_pwm {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -279,7 +329,7 @@
&reg_dldo4 {
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
+ regulator-max-microvolt = <1800000>;
regulator-name = "vcc-wifi-io";
};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts
index 2e2b14c0ae..8857a37915 100644
--- a/dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts
+++ b/dts/src/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
/ {
diff --git a/dts/src/arm64/allwinner/sun50i-h5-cpu-opp.dtsi b/dts/src/arm64/allwinner/sun50i-h5-cpu-opp.dtsi
new file mode 100644
index 0000000000..b265720195
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-h5-cpu-opp.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1000000 1000000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1080000 1080000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1120000 1120000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1160000 1160000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1240000 1240000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1260000 1260000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1300000 1300000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/dts/src/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts
index 64d35daf20..d811df3328 100644
--- a/dts/src/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts
+++ b/dts/src/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
#include <arm/sunxi-libretech-all-h3-cc.dtsi>
/ {
diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts
index c95a685413..de19e68eb8 100644
--- a/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -30,6 +30,21 @@
};
};
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -48,6 +63,10 @@
status = "okay";
};
+&ehci0 {
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
@@ -92,6 +111,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pa_pins>;
@@ -103,3 +126,18 @@
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
+
+&usb_otg {
+ /*
+ * According to schematics CN1 MicroUSB port can be used to take
+ * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
+ * port cannot provide power externally even if the board is powered
+ * via GPIO pins. It thus makes sense to force peripheral mode.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-h5.dtsi b/dts/src/arm64/allwinner/sun50i-h5.dtsi
index 4462a68c06..6735e316a3 100644
--- a/dts/src/arm64/allwinner/sun50i-h5.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-h5.dtsi
@@ -3,6 +3,8 @@
#include <arm/sunxi-h3-h5.dtsi>
+#include <dt-bindings/thermal/thermal.h>
+
/ {
cpus {
#address-cells = <1>;
@@ -13,6 +15,9 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -20,6 +25,9 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -27,6 +35,9 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -34,6 +45,9 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ #cooling-cells = <2>;
};
};
@@ -165,6 +179,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpu_thermal {
diff --git a/dts/src/arm64/altera/socfpga_stratix10.dtsi b/dts/src/arm64/altera/socfpga_stratix10.dtsi
index 9498d1de73..a6fb01c7ab 100644
--- a/dts/src/arm64/altera/socfpga_stratix10.dtsi
+++ b/dts/src/arm64/altera/socfpga_stratix10.dtsi
@@ -380,6 +380,7 @@
reg = <0xffda4000 0x1000>;
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
@@ -393,6 +394,7 @@
reg = <0xffda5000 0x1000>;
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
diff --git a/dts/src/arm64/al/alpine-v2-evp.dts b/dts/src/arm64/amazon/alpine-v2-evp.dts
index a079d7b306..a079d7b306 100644
--- a/dts/src/arm64/al/alpine-v2-evp.dts
+++ b/dts/src/arm64/amazon/alpine-v2-evp.dts
diff --git a/dts/src/arm64/al/alpine-v2.dtsi b/dts/src/arm64/amazon/alpine-v2.dtsi
index d5e7e2bb4e..d5e7e2bb4e 100644
--- a/dts/src/arm64/al/alpine-v2.dtsi
+++ b/dts/src/arm64/amazon/alpine-v2.dtsi
diff --git a/dts/src/arm64/amazon/alpine-v3-evp.dts b/dts/src/arm64/amazon/alpine-v3-evp.dts
new file mode 100644
index 0000000000..48078f5ea5
--- /dev/null
+++ b/dts/src/arm64/amazon/alpine-v3-evp.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ */
+
+#include "alpine-v3.dtsi"
+
+/ {
+ model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)";
+ compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 { status = "okay"; };
diff --git a/dts/src/arm64/amazon/alpine-v3.dtsi b/dts/src/arm64/amazon/alpine-v3.dtsi
new file mode 100644
index 0000000000..73a352ea8f
--- /dev/null
+++ b/dts/src/arm64/amazon/alpine-v3.dtsi
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Amazon's Annapurna Labs Alpine v3";
+ compatible = "amazon,al-alpine-v3";
+
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x2>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x3>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x200>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x201>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x202>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x203>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x300>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x301>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x302>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x303>;
+ enable-method = "psci";
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cluster0_l2: cache@0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-level = <2>;
+ };
+
+ cluster1_l2: cache@100 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-level = <2>;
+ };
+
+ cluster2_l2: cache@200 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-level = <2>;
+ };
+
+ cluster3_l2: cache@300 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-level = <2>;
+ };
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secmon@0 {
+ reg = <0x0 0x0 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f0000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0xf0800000 0 0x10000>, /* GICD */
+ <0x0 0xf0a00000 0 0x200000>, /* GICR */
+ <0x0 0xf0000000 0 0x2000>, /* GICC */
+ <0x0 0xf0010000 0 0x1000>, /* GICH */
+ <0x0 0xf0020000 0 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie@fbd00000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0xfbd00000 0x0 0x100000>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ /* 8 x legacy interrupts for SATA only */
+ interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
+ <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
+ <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
+ <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
+ <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
+ <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
+ <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
+ ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
+ bus-range = <0x00 0x00>;
+ msi-parent = <&msix>;
+ };
+
+ msix: msix@fbe00000 {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <336>;
+ al,msi-num-spis = <959>;
+ interrupt-parent = <&gic>;
+ };
+
+ io-fabric {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xfc000000 0x2000000>;
+
+ uart0: serial@1883000 {
+ compatible = "ns16550a";
+ reg = <0x1883000 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* Filled by firmware */
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@1884000 {
+ compatible = "ns16550a";
+ reg = <0x1884000 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* Filled by firmware */
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@1885000 {
+ compatible = "ns16550a";
+ reg = <0x1885000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* Filled by firmware */
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@1886000 {
+ compatible = "ns16550a";
+ reg = <0x1886000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>; /* Filled by firmware */
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/amlogic/meson-axg.dtsi b/dts/src/arm64/amlogic/meson-axg.dtsi
index 8e6281c685..b9efc84692 100644
--- a/dts/src/arm64/amlogic/meson-axg.dtsi
+++ b/dts/src/arm64/amlogic/meson-axg.dtsi
@@ -181,8 +181,10 @@
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1",
+ "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
diff --git a/dts/src/arm64/amlogic/meson-g12-common.dtsi b/dts/src/arm64/amlogic/meson-g12-common.dtsi
index 593a006f4b..1e83ec5b8c 100644
--- a/dts/src/arm64/amlogic/meson-g12-common.dtsi
+++ b/dts/src/arm64/amlogic/meson-g12-common.dtsi
@@ -52,6 +52,39 @@
secure-monitor = <&sm>;
};
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-124999998 {
+ opp-hz = /bits/ 64 <124999998>;
+ opp-microvolt = <800000>;
+ };
+ opp-249999996 {
+ opp-hz = /bits/ 64 <249999996>;
+ opp-microvolt = <800000>;
+ };
+ opp-285714281 {
+ opp-hz = /bits/ 64 <285714281>;
+ opp-microvolt = <800000>;
+ };
+ opp-399999994 {
+ opp-hz = /bits/ 64 <399999994>;
+ opp-microvolt = <800000>;
+ };
+ opp-499999992 {
+ opp-hz = /bits/ 64 <499999992>;
+ opp-microvolt = <800000>;
+ };
+ opp-666666656 {
+ opp-hz = /bits/ 64 <666666656>;
+ opp-microvolt = <800000>;
+ };
+ opp-799999987 {
+ opp-hz = /bits/ 64 <799999987>;
+ opp-microvolt = <800000>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -185,8 +218,10 @@
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1",
+ "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
@@ -2360,21 +2395,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&clkc CLKID_MALI>;
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <800000000>,
- <0>; /* Do Nothing */
+ operating-points-v2 = <&gpu_opp_table>;
#cooling-cells = <2>;
};
};
diff --git a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts
index 169ea283d4..34fffa6d85 100644
--- a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts
+++ b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts
@@ -9,6 +9,7 @@
#include "meson-g12b-s922x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
@@ -20,6 +21,14 @@
ethernet0 = &ethmac;
};
+ dioo2133: audio-amplifier-0 {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ VCC-supply = <&vcc_5v>;
+ sound-name-prefix = "U19";
+ status = "okay";
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -209,11 +218,42 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12B-ODROID-N2";
- audio-aux-devs = <&tdmout_b>;
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
+ <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
+ <&dioo2133>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_LB IN 1", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TDMIN_LB IN 2", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 6", "TDMIN_LB OUT",
+ "TODDR_B IN 6", "TDMIN_LB OUT",
+ "TODDR_C IN 6", "TDMIN_LB OUT",
+ "U19 INL", "ACODEC LOLP",
+ "U19 INR", "ACODEC LORP",
+ "Lineout", "U19 OUTL",
+ "Lineout", "U19 OUTR";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
@@ -236,8 +276,20 @@
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
@@ -246,22 +298,56 @@
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
- codec {
+ codec-0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-8 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
};
};
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
&arb {
status = "okay";
};
@@ -476,14 +562,54 @@
status = "okay";
};
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmin_lb {
+ status = "okay";
+};
+
&tdmout_b {
status = "okay";
};
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/dts/src/arm64/amlogic/meson-g12b-w400.dtsi b/dts/src/arm64/amlogic/meson-g12b-w400.dtsi
index 98b70d216a..2802ddbb83 100644
--- a/dts/src/arm64/amlogic/meson-g12b-w400.dtsi
+++ b/dts/src/arm64/amlogic/meson-g12b-w400.dtsi
@@ -336,9 +336,11 @@
bus-width = <4>;
cap-sd-highspeed;
- sd-uhs-sdr50;
max-frequency = <100000000>;
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
non-removable;
disable-wp;
@@ -398,7 +400,7 @@
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
- clock-names = "lpo";
+ clock-names = "lpo";
};
};
diff --git a/dts/src/arm64/amlogic/meson-gx-mali450.dtsi b/dts/src/arm64/amlogic/meson-gx-mali450.dtsi
new file mode 100644
index 0000000000..f9771b51c8
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-gx-mali450.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/ {
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-285714285 {
+ opp-hz = /bits/ 64 <285714285>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-666666666 {
+ opp-hz = /bits/ 64 <666666666>;
+ opp-microvolt = <950000>;
+ };
+ opp-744000000 {
+ opp-hz = /bits/ 64 <744000000>;
+ opp-microvolt = <950000>;
+ };
+ };
+};
+
+&apb {
+ mali: gpu@c0000 {
+ compatible = "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+};
diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi
index ba63c36b22..0edd137151 100644
--- a/dts/src/arm64/amlogic/meson-gx.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/meson-gxbb-power.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -60,7 +61,7 @@
compatible = "amlogic,simple-framebuffer",
"simple-framebuffer";
amlogic,pipeline = "vpu-cvbs";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
status = "disabled";
};
@@ -68,7 +69,7 @@
compatible = "amlogic,simple-framebuffer",
"simple-framebuffer";
amlogic,pipeline = "vpu-hdmi";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
status = "disabled";
};
};
@@ -438,12 +439,6 @@
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
- pwrc_vpu: power-controller-vpu {
- compatible = "amlogic,meson-gx-pwrc-vpu";
- #power-domain-cells = <0>;
- amlogic,hhi-sysctrl = <&sysctrl>;
- };
-
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
@@ -552,6 +547,12 @@
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0 0 0x400>;
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-gxbb-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&sysctrl_AO>;
+ };
};
mailbox: mailbox@404 {
@@ -574,6 +575,7 @@
interrupt-names = "macirq";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
+ power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>;
status = "disabled";
};
diff --git a/dts/src/arm64/amlogic/meson-gxbb.dtsi b/dts/src/arm64/amlogic/meson-gxbb.dtsi
index 234490d3ee..7c029f552a 100644
--- a/dts/src/arm64/amlogic/meson-gxbb.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb.dtsi
@@ -4,6 +4,7 @@
*/
#include "meson-gx.dtsi"
+#include "meson-gx-mali450.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
@@ -264,46 +265,6 @@
};
};
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_GP0_PLL>,
- <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <0>, /* Do Nothing */
- <&clkc CLKID_GP0_PLL>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <744000000>,
- <0>, /* Do Nothing */
- <744000000>,
- <0>; /* Do Nothing */
- };
-};
-
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
@@ -333,8 +294,9 @@
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
};
&gpio_intc {
@@ -385,6 +347,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&mali {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ assigned-clocks = <&clkc CLKID_GP0_PLL>;
+ assigned-clock-rates = <744000000>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
@@ -747,7 +719,7 @@
};
};
-&pwrc_vpu {
+&pwrc {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
@@ -760,6 +732,9 @@
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus", "bt656",
+ "dvin", "rdma", "venci", "vencp",
+ "vdac", "vdi6", "vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
@@ -866,7 +841,7 @@
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
};
&vdec {
diff --git a/dts/src/arm64/amlogic/meson-gxl-mali.dtsi b/dts/src/arm64/amlogic/meson-gxl-mali.dtsi
index 6aaafff674..478e755cc8 100644
--- a/dts/src/arm64/amlogic/meson-gxl-mali.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl-mali.dtsi
@@ -4,42 +4,14 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
+#include "meson-gx-mali450.dtsi"
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_GP0_PLL>,
- <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <0>, /* Do Nothing */
- <&clkc CLKID_GP0_PLL>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <744000000>,
- <0>, /* Do Nothing */
- <744000000>,
- <0>; /* Do Nothing */
- };
+&mali {
+ compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
+
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ assigned-clocks = <&clkc CLKID_GP0_PLL>;
+ assigned-clock-rates = <744000000>;
};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s805x.dtsi b/dts/src/arm64/amlogic/meson-gxl-s805x.dtsi
index f9d7056484..2997584982 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s805x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl-s805x.dtsi
@@ -11,14 +11,13 @@
};
/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */
+&gpu_opp_table {
+ opp-744000000 {
+ status = "disabled";
+ };
+};
+
&mali {
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>; /* Do Nothing */
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
};
diff --git a/dts/src/arm64/amlogic/meson-gxl.dtsi b/dts/src/arm64/amlogic/meson-gxl.dtsi
index 6c8b189884..c3ac531c4f 100644
--- a/dts/src/arm64/amlogic/meson-gxl.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl.dtsi
@@ -131,8 +131,9 @@
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
mdio0: mdio {
#address-cells = <1>;
@@ -787,7 +788,7 @@
};
};
-&pwrc_vpu {
+&pwrc {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
@@ -800,6 +801,9 @@
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus", "bt656",
+ "dvin", "rdma", "venci", "vencp",
+ "vdac", "vdi6", "vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
@@ -906,7 +910,7 @@
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
};
&vdec {
diff --git a/dts/src/arm64/amlogic/meson-gxm-wetek-core2.dts b/dts/src/arm64/amlogic/meson-gxm-wetek-core2.dts
new file mode 100644
index 0000000000..ec794c134c
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-gxm-wetek-core2.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm";
+ model = "WeTek Core 2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-update {
+ label = "update";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ button-power {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* Disabled as Realtek RTL8152 USB provides Ethernet */
+&ethmac {
+ status = "disabled";
+};
+
+&internal_phy {
+ status = "disabled";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-play2";
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
diff --git a/dts/src/arm64/amlogic/meson-gxm.dtsi b/dts/src/arm64/amlogic/meson-gxm.dtsi
index 40e3e123e0..fe41451122 100644
--- a/dts/src/arm64/amlogic/meson-gxm.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxm.dtsi
@@ -82,6 +82,35 @@
#cooling-cells = <2>;
};
};
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-285714285 {
+ opp-hz = /bits/ 64 <285714285>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-666666666 {
+ opp-hz = /bits/ 64 <666666666>;
+ opp-microvolt = <950000>;
+ };
+ };
};
&apb {
@@ -106,21 +135,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&clkc CLKID_MALI>;
resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>; /* Do Nothing */
+ operating-points-v2 = <&gpu_opp_table>;
};
};
diff --git a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
index 1ef1e3672b..94f75b4465 100644
--- a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
+++ b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
@@ -183,6 +183,23 @@
hdmi-phandle = <&hdmi_tx>;
};
+&cpu_thermal {
+ trips {
+ cpu_active: cpu-active {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_active>;
+ cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
@@ -222,6 +239,12 @@
pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
pinctrl-names = "default";
+ khadas_mcu: system-controller@18 {
+ compatible = "khadas,mcu";
+ reg = <0x18>;
+ #cooling-cells = <2>;
+ };
+
gpio_expander: gpio-controller@20 {
compatible = "ti,tca6408";
reg = <0x20>;
@@ -270,7 +293,6 @@
bus-width = <4>;
cap-sd-highspeed;
- sd-uhs-sdr50;
max-frequency = <100000000>;
non-removable;
@@ -337,7 +359,7 @@
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
- w25q32: spi-flash@0 {
+ w25q128: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128fw", "jedec,spi-nor";
diff --git a/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
index dbbf29a0db..0da56c051a 100644
--- a/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
+++ b/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
@@ -8,6 +8,7 @@
#include "meson-sm1.dtsi"
#include "meson-khadas-vim3.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "khadas,vim3l", "amlogic,sm1";
@@ -31,6 +32,69 @@
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "SM1-KHADAS-VIM3L";
+ audio-aux-devs = <&tdmout_a>;
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_a>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
};
&cpu0 {
@@ -61,6 +125,18 @@
clock-latency = <50000>;
};
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
@@ -88,8 +164,24 @@
status = "okay";
};
+&sd_emmc_a {
+ sd-uhs-sdr50;
+};
+
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/
+
+&tdmif_a {
+ status = "okay";
+};
+
+&tdmout_a {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts b/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
index 00d90b30f8..cf5a98f0e4 100644
--- a/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
+++ b/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
@@ -8,6 +8,7 @@
#include "meson-sm1.dtsi"
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "hardkernel,odroid-c4", "amlogic,sm1";
@@ -186,6 +187,69 @@
};
};
};
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "SM1-ODROID-C4";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
};
&cpu0 {
@@ -237,6 +301,18 @@
amlogic,tx-delay-ns = <2>;
};
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
&gpio {
gpio-line-names =
/* GPIOZ */
@@ -381,6 +457,18 @@
vqmmc-supply = <&flash_1v8>;
};
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/dts/src/arm64/exynos/exynos5433.dtsi b/dts/src/arm64/exynos/exynos5433.dtsi
index 6721966140..74ac4ac758 100644
--- a/dts/src/arm64/exynos/exynos5433.dtsi
+++ b/dts/src/arm64/exynos/exynos5433.dtsi
@@ -24,7 +24,7 @@
interrupt-parent = <&gic>;
arm_a53_pmu {
- compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -33,7 +33,7 @@
};
arm_a57_pmu {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -256,7 +256,7 @@
cpu_on = <0xC4000003>;
};
- soc: soc {
+ soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -1756,33 +1756,26 @@
status = "disabled";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma0: pdma@15610000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x15610000 0x1000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_fsys CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@15600000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x15600000 0x1000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_fsys CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma0: pdma@15610000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x15610000 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@15600000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x15600000 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
};
audio-subsystem@11400000 {
diff --git a/dts/src/arm64/exynos/exynos7-espresso.dts b/dts/src/arm64/exynos/exynos7-espresso.dts
index 7af288fa94..92fecc539c 100644
--- a/dts/src/arm64/exynos/exynos7-espresso.dts
+++ b/dts/src/arm64/exynos/exynos7-espresso.dts
@@ -157,6 +157,7 @@
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1150000>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo8_reg: LDO8 {
@@ -193,6 +194,7 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo13_reg: LDO13 {
@@ -406,6 +408,10 @@
};
};
+&ufs {
+ status = "okay";
+};
+
&usbdrd_phy {
vbus-supply = <&usb30_vbus_reg>;
vbus-boost-supply = <&usb3drd_boost_5v>;
diff --git a/dts/src/arm64/exynos/exynos7.dtsi b/dts/src/arm64/exynos/exynos7.dtsi
index 5558045637..b9ed6a33e2 100644
--- a/dts/src/arm64/exynos/exynos7.dtsi
+++ b/dts/src/arm64/exynos/exynos7.dtsi
@@ -29,7 +29,7 @@
};
arm-pmu {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
@@ -83,7 +83,7 @@
method = "smc";
};
- soc: soc {
+ soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -105,33 +105,26 @@
<0x11006000 0x2000>;
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma0: pdma@10e10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x10E10000 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock_fsys0 ACLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma0: pdma@10e10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10E10000 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys0 ACLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma1: pdma@10eb0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x10EB0000 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock_fsys0 ACLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma1: pdma@10eb0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10EB0000 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys0 ACLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
};
clock_topc: clock-controller@10570000 {
@@ -220,9 +213,14 @@
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
<&clock_top1 DOUT_SCLK_MMC0>,
- <&clock_top1 DOUT_SCLK_MMC1>;
+ <&clock_top1 DOUT_SCLK_MMC1>,
+ <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
+ <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
+ <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
clock-names = "fin_pll", "dout_aclk_fsys1_200",
- "dout_sclk_mmc0", "dout_sclk_mmc1";
+ "dout_sclk_mmc0", "dout_sclk_mmc1",
+ "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
+ "dout_sclk_phy_fsys1_26m";
};
serial_0: serial@13630000 {
@@ -576,6 +574,11 @@
pwm: pwm@136c0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x136c0000 0x100>;
+ interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
clocks = <&clock_peric0 PCLK_PWM>;
@@ -592,13 +595,38 @@
#thermal-sensor-cells = <0>;
};
- thermal-zones {
- atlas_thermal: cluster0-thermal {
- polling-delay-passive = <0>; /* milliseconds */
- polling-delay = <0>; /* milliseconds */
- thermal-sensors = <&tmuctrl_0>;
- #include "exynos7-trip-points.dtsi"
- };
+ ufs: ufs@15570000 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x15570000 0x100>, /* 0: HCI standard */
+ <0x15570100 0x100>, /* 1: Vendor specificed */
+ <0x15571000 0x200>, /* 2: UNIPRO */
+ <0x15572000 0x300>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
+ <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_phy>;
+ phy-names = "ufs-phy";
+ status = "disabled";
+ };
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk",
+ "tx0_symbol_clk";
};
usbdrd_phy: phy@15500000 {
@@ -636,6 +664,15 @@
};
};
+ thermal-zones {
+ atlas_thermal: cluster0-thermal {
+ polling-delay-passive = <0>; /* milliseconds */
+ polling-delay = <0>; /* milliseconds */
+ thermal-sensors = <&tmuctrl_0>;
+ #include "exynos7-trip-points.dtsi"
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
diff --git a/dts/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
index 006e544d1f..ff19ec415b 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -17,6 +17,7 @@
aliases {
crypto = &crypto;
+ rtc1 = &ftm_alarm0;
rtic-a = &rtic_a;
rtic-b = &rtic_b;
rtic-c = &rtic_c;
@@ -512,6 +513,20 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ rcpm: power-controller@1ee2140 {
+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1012a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
firmware {
diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds.dts
index dd69c5b821..e4f00c2b66 100644
--- a/dts/src/arm64/freescale/fsl-ls1028a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1028a-qds.dts
@@ -107,6 +107,91 @@
};
};
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&dspi1 {
+ bus-num = <1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&dspi2 {
+ bus-num = <2>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
&duart0 {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi
index 055f114cf8..0efeb8fa77 100644
--- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi
@@ -17,6 +17,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -129,12 +133,32 @@
};
thermal-zones {
- core-cluster {
+ ddr-controller {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
+ ddr-ctrler-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ddr-ctrler-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
@@ -983,6 +1007,19 @@
};
};
};
+
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
malidp0: display@f080000 {
diff --git a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
index 1aac81da7e..fea167d222 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
@@ -148,4 +148,8 @@
};
};
+&usb0 {
+ status = "okay";
+};
+
#include "fsl-ls1043-post.dtsi"
diff --git a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
index bfa9d957e5..3516af4726 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
@@ -209,3 +209,11 @@
fsl,tdm-interface;
};
};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
index 3b641bd432..5c2e370f63 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -27,6 +27,7 @@
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -149,19 +150,79 @@
};
thermal-zones {
- cpu_thermal: cpu-thermal {
+ ddr-controller {
polling-delay-passive = <1000>;
polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+ trips {
+ ddr-ctrler-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ddr-ctrler-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ serdes {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ serdes-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ serdes-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ fman {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ fman-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ fman-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
- cpu_alert: cpu-alert {
+ core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit: cpu-crit {
+
+ core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -170,7 +231,7 @@
cooling-maps {
map0 {
- trip = <&cpu_alert>;
+ trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
@@ -179,6 +240,26 @@
};
};
};
+
+ sec {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 4>;
+
+ trips {
+ sec-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ sec-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
};
timer {
@@ -677,6 +758,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
};
usb1: usb3@3000000 {
@@ -687,6 +769,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
};
usb2: usb3@3100000 {
@@ -697,6 +780,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ status = "disabled";
};
sata: sata@3200000 {
@@ -829,6 +913,19 @@
big-endian;
};
+ rcpm: power-controller@1ee2140 {
+ compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1043a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
firmware {
diff --git a/dts/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
index d4c1da3d4b..0246d975a2 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -28,6 +28,7 @@
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -117,19 +118,79 @@
};
thermal-zones {
- cpu_thermal: cpu-thermal {
+ ddr-controller {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ ddr-ctrler-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ddr-ctrler-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ serdes {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ serdes-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ serdes-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ fman {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ fman-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ fman-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
- cpu_alert: cpu-alert {
+ core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit: cpu-crit {
+ core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -138,7 +199,7 @@
cooling-maps {
map0 {
- trip = <&cpu_alert>;
+ trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
@@ -147,6 +208,26 @@
};
};
};
+
+ sec {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 4>;
+
+ trips {
+ sec-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ sec-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
};
timer {
@@ -765,6 +846,20 @@
queue-sizes = <64 64>;
big-endian;
};
+
+ rcpm: power-controller@1ee2140 {
+ compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1046a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
reserved-memory {
diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
index 36a7995546..169f4742ae 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -18,6 +18,7 @@
aliases {
crypto = &crypto;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -781,6 +782,19 @@
};
};
};
+
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1088a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
firmware {
diff --git a/dts/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
index 3944ef16ec..41102dacc2 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -20,6 +20,7 @@
aliases {
crypto = &crypto;
+ rtc1 = &ftm_alarm0;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
@@ -763,6 +764,19 @@
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
+
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls208xa-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
ddr1: memory-controller@1080000 {
diff --git a/dts/src/arm64/freescale/fsl-lx2160a-qds.dts b/dts/src/arm64/freescale/fsl-lx2160a-qds.dts
index 3b88e1efe4..2d1fe6c379 100644
--- a/dts/src/arm64/freescale/fsl-lx2160a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-lx2160a-qds.dts
@@ -35,6 +35,42 @@
status = "okay";
};
+&dspi0 {
+ status = "okay";
+
+ dflash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&dspi1 {
+ status = "okay";
+
+ dflash1: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&dspi2 {
+ status = "okay";
+
+ dflash2: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&esdhc0 {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts b/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts
index 22d0308eb1..54fe8cd3a7 100644
--- a/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts
@@ -121,7 +121,7 @@
power-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
- shunt-resistor = <1000>;
+ shunt-resistor = <500>;
};
};
diff --git a/dts/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
index abaeb587de..d247e4228d 100644
--- a/dts/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
//
// Device Tree Include file for Layerscape-LX2160A family SoC.
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -16,6 +16,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -777,6 +781,45 @@
status = "disabled";
};
+ dspi0: spi@2100000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ dspi1: spi@2110000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ status = "disabled";
+ };
+
+ dspi2: spi@2120000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
@@ -888,6 +931,20 @@
timeout-sec = <30>;
};
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,lx2160a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
@@ -957,7 +1014,7 @@
pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -985,7 +1042,7 @@
pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1013,7 +1070,7 @@
pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1041,7 +1098,7 @@
pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1069,7 +1126,7 @@
pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1097,7 +1154,7 @@
pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
diff --git a/dts/src/arm64/freescale/imx8mm.dtsi b/dts/src/arm64/freescale/imx8mm.dtsi
index aaf6e71101..76f040e4be 100644
--- a/dts/src/arm64/freescale/imx8mm.dtsi
+++ b/dts/src/arm64/freescale/imx8mm.dtsi
@@ -18,10 +18,18 @@
aliases {
ethernet0 = &fec1;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@@ -29,14 +37,6 @@
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
- mmc0 = &usdhc1;
- mmc1 = &usdhc2;
- mmc2 = &usdhc3;
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
};
cpus {
@@ -467,7 +467,7 @@
reg = <0x30340000 0x10000>;
};
- ocotp: ocotp-ctrl@30350000 {
+ ocotp: efuse@30350000 {
compatible = "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
@@ -775,6 +775,14 @@
status = "disabled";
};
+ mu: mailbox@30aa0000 {
+ compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+ #mbox-cells = <2>;
+ };
+
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
diff --git a/dts/src/arm64/freescale/imx8mn-evk.dts b/dts/src/arm64/freescale/imx8mn-evk.dts
index 61f3519586..b846526a8d 100644
--- a/dts/src/arm64/freescale/imx8mn-evk.dts
+++ b/dts/src/arm64/freescale/imx8mn-evk.dts
@@ -13,6 +13,102 @@
compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
};
+&i2c1 {
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450b";
+ reg = <0x25>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ buck1: BUCK1{
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
&A53_0 {
/delete-property/operating-points-v2;
};
diff --git a/dts/src/arm64/freescale/imx8mn-evk.dtsi b/dts/src/arm64/freescale/imx8mn-evk.dtsi
index 85fc0aa38c..98f5324b1d 100644
--- a/dts/src/arm64/freescale/imx8mn-evk.dtsi
+++ b/dts/src/arm64/freescale/imx8mn-evk.dtsi
@@ -223,6 +223,12 @@
>;
};
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi
index 9a4b65a267..9385dd7d1a 100644
--- a/dts/src/arm64/freescale/imx8mn.dtsi
+++ b/dts/src/arm64/freescale/imx8mn.dtsi
@@ -374,7 +374,7 @@
reg = <0x30340000 0x10000>;
};
- ocotp: ocotp-ctrl@30350000 {
+ ocotp: efuse@30350000 {
compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
@@ -675,6 +675,14 @@
status = "disabled";
};
+ mu: mailbox@30aa0000 {
+ compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+ #mbox-cells = <2>;
+ };
+
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi
index 45e2c0a4e8..9de2aa1c57 100644
--- a/dts/src/arm64/freescale/imx8mp.dtsi
+++ b/dts/src/arm64/freescale/imx8mp.dtsi
@@ -23,6 +23,12 @@
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ i2c5 = &i2c6;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
@@ -307,8 +313,8 @@
reg = <0x30340000 0x10000>;
};
- ocotp: ocotp-ctrl@30350000 {
- compatible = "fsl,imx8mp-ocotp", "syscon";
+ ocotp: efuse@30350000 {
+ compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
@@ -621,6 +627,14 @@
status = "disabled";
};
+ mu: mailbox@30aa0000 {
+ compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MU_ROOT>;
+ #mbox-cells = <2>;
+ };
+
i2c5: i2c@30ad0000 {
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
@@ -730,5 +744,11 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
};
+
+ ddr-pmu@3d800000 {
+ compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
+ reg = <0x3d800000 0x400000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
diff --git a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
index 6a55165bd7..0d1088dcaa 100644
--- a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
+++ b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
@@ -131,6 +131,8 @@
mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch: switch@0 {
diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi
index 978f8122c0..f70435cf9a 100644
--- a/dts/src/arm64/freescale/imx8mq.dtsi
+++ b/dts/src/arm64/freescale/imx8mq.dtsi
@@ -20,6 +20,7 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &fec1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -29,6 +30,8 @@
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@@ -539,7 +542,7 @@
};
};
- ocotp: ocotp-ctrl@30350000 {
+ ocotp: efuse@30350000 {
compatible = "fsl,imx8mq-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
@@ -675,6 +678,7 @@
pgc_vpu: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8M_POWER_DOMAIN_VPU>;
+ clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
};
pgc_disp: power-domain@7 {
@@ -959,6 +963,14 @@
status = "disabled";
};
+ mu: mailbox@30aa0000 {
+ compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
+ #mbox-cells = <2>;
+ };
+
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mq-usdhc",
"fsl,imx7d-usdhc";
@@ -1142,6 +1154,32 @@
status = "disabled";
};
+ vpu: video-codec@38300000 {
+ compatible = "nxp,imx8mq-vpu";
+ reg = <0x38300000 0x10000>,
+ <0x38310000 0x10000>,
+ <0x38320000 0x10000>;
+ reg-names = "g1", "g2", "ctrl";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1", "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <600000000>, <600000000>,
+ <800000000>, <0>;
+ power-domains = <&pgc_vpu>;
+ };
+
pcie0: pcie@33800000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33800000 0x400000>,
diff --git a/dts/src/arm64/freescale/imx8qxp.dtsi b/dts/src/arm64/freescale/imx8qxp.dtsi
index d1c3c98e4b..e46faac1fe 100644
--- a/dts/src/arm64/freescale/imx8qxp.dtsi
+++ b/dts/src/arm64/freescale/imx8qxp.dtsi
@@ -19,6 +19,8 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
gpio0 = &lsio_gpio0;
gpio1 = &lsio_gpio1;
gpio2 = &lsio_gpio2;
@@ -27,10 +29,18 @@
gpio5 = &lsio_gpio5;
gpio6 = &lsio_gpio6;
gpio7 = &lsio_gpio7;
+ i2c0 = &adma_i2c0;
+ i2c1 = &adma_i2c1;
+ i2c2 = &adma_i2c2;
+ i2c3 = &adma_i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
+ mu0 = &lsio_mu0;
mu1 = &lsio_mu1;
+ mu2 = &lsio_mu2;
+ mu3 = &lsio_mu3;
+ mu4 = &lsio_mu4;
serial0 = &adma_lpuart0;
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
diff --git a/dts/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
index e035cf195b..c1b614dabb 100644
--- a/dts/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -13,6 +13,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/usb/pd.h>
/ {
model = "HiKey960";
@@ -526,10 +527,63 @@
&i2c1 {
status = "okay";
+ rt1711h: rt1711h@4e {
+ compatible = "richtek,rt1711h";
+ reg = <0x4e>;
+ status = "ok";
+ interrupt-parent = <&gpio27>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_cfg_func>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 5000, 1000)>;
+ op-sink-microwatt = <10000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&dwc3_ss>;
+ };
+ };
+ };
+ };
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt1711h_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dwc3_role_switch>;
+ };
+ };
+ };
+
adv7533: adv7533@39 {
status = "ok";
compatible = "adi,adv7533";
reg = <0x39>;
+ adi,dsi-lanes = <4>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
};
};
@@ -612,3 +666,32 @@
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
};
+
+&dwc3 { /* USB */
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phy_type = "utmi";
+ snps,dis-del-phy-power-chg-quirk;
+ snps,lfps_filter_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,tx_de_emphasis_quirk;
+ snps,tx_de_emphasis = <1>;
+ snps,dis_enblslpm_quirk;
+ snps,gctl-reset-quirk;
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&rt1711h_ep>;
+ };
+
+ dwc3_ss: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usb_con_ss>;
+ };
+ };
+};
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index c39b78989f..d25aac5e0b 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -1152,6 +1152,40 @@
};
};
};
+
+ usb3_otg_bc: usb3_otg_bc@ff200000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+
+ usb_phy: usb-phy {
+ compatible = "hisilicon,hi3660-usb-phy";
+ #phy-cells = <0>;
+ hisilicon,pericrg-syscon = <&crg_ctrl>;
+ hisilicon,pctrl-syscon = <&pctrl>;
+ hisilicon,eye-diagram-param = <0x22466e4>;
+ };
+ };
+
+ dwc3: dwc3@ff100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff100000 0x0 0x100000>;
+
+ clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
+ <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
+ clock-names = "ref", "bus_early";
+
+ assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
+ assigned-clock-rates = <229000000>;
+
+ resets = <&crg_rst 0x90 8>,
+ <&crg_rst 0x90 7>,
+ <&crg_rst 0x90 6>,
+ <&crg_rst 0x90 5>;
+
+ interrupts = <0 159 4>, <0 161 4>;
+ phys = <&usb_phy>;
+ phy-names = "usb3-phy";
+ };
};
};
diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts
index c14205cd6b..533ed52388 100644
--- a/dts/src/arm64/hisilicon/hi6220-hikey.dts
+++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts
@@ -122,222 +122,6 @@
power-off-delay-us = <10>;
};
- soc {
- spi0: spi@f7106000 {
- status = "ok";
- };
-
- i2c0: i2c@f7100000 {
- status = "ok";
- };
-
- i2c1: i2c@f7101000 {
- status = "ok";
- };
-
- uart1: uart@f7111000 {
- assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
- assigned-clock-rates = <150000000>;
- status = "ok";
-
- bluetooth {
- compatible = "ti,wl1835-st";
- enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- clocks = <&pmic>;
- clock-names = "ext_clock";
- };
- };
-
- uart2: uart@f7112000 {
- status = "ok";
- };
-
- uart3: uart@f7113000 {
- status = "ok";
- };
-
- /*
- * Legend: proper name = the GPIO line is used as GPIO
- * NC = not connected (not routed from the SoC)
- * "[PER]" = pin is muxed for peripheral (not GPIO)
- * "" = no idea, schematic doesn't say, could be
- * unrouted (not connected to any external pin)
- * LSEC = Low Speed External Connector
- * HSEC = High Speed External Connector
- *
- * Pin assignments taken from LeMaker and CircuitCo Schematics
- * Rev A1.
- *
- * For the lines routed to the external connectors the
- * lines are named after the 96Boards CE Specification 1.0,
- * Appendix "Expansion Connector Signal Description".
- *
- * When the 96Board naming of a line and the schematic name of
- * the same line are in conflict, the 96Board specification
- * takes precedence, which means that the external UART on the
- * LSEC is named UART0 while the schematic and SoC names this
- * UART2. This is only for the informational lines i.e. "[FOO]",
- * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
- * ones actually used for GPIO.
- */
- gpio0: gpio@f8011000 {
- gpio-line-names = "PWR_HOLD", "DSI_SEL",
- "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",
- "PWRON_DET", "5V_HUB_EN";
- };
-
- gpio1: gpio@f8012000 {
- gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",
- "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";
- };
-
- gpio2: gpio@f8013000 {
- gpio-line-names =
- "GPIO-A", /* LSEC Pin 23: GPIO2_0 */
- "GPIO-B", /* LSEC Pin 24: GPIO2_1 */
- "GPIO-C", /* LSEC Pin 25: GPIO2_2 */
- "GPIO-D", /* LSEC Pin 26: GPIO2_3 */
- "GPIO-E", /* LSEC Pin 27: GPIO2_4 */
- "USB_ID_DET", "USB_VBUS_DET",
- "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
- };
-
- gpio3: gpio@f8014000 {
- gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",
- "WLAN_ACTIVE", "NC", "NC";
- };
-
- gpio4: gpio@f7020000 {
- gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",
- "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";
- };
-
- gpio5: gpio@f7021000 {
- gpio-line-names = "NC", "NC",
- "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
- "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
- "[AUX_SSI1]", "NC",
- "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
- "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */
- };
-
- gpio6: gpio@f7022000 {
- gpio-line-names =
- "[SPI0_DIN]", /* Pin 10: SPI0_DI */
- "[SPI0_DOUT]", /* Pin 14: SPI0_DO */
- "[SPI0_CS]", /* Pin 12: SPI0_CS_N */
- "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
- "NC", "NC", "NC",
- "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */
- };
-
- gpio7: gpio@f7023000 {
- gpio-line-names = "NC", "NC", "NC", "NC",
- "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */
- "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */
- "NC", "NC";
- };
-
- gpio8: gpio@f7024000 {
- gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",
- "", "", "", "", "", "";
- };
-
- gpio9: gpio@f7025000 {
- gpio-line-names = "",
- "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */
- "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */
- "NC", "NC", "NC", "NC", "[ISP_CCLK0]";
- };
-
- gpio10: gpio@f7026000 {
- gpio-line-names = "BOOT_SEL",
- "[ISP_CCLK1]",
- "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */
- "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */
- "NC", "NC",
- "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */
- "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */
- };
-
- gpio11: gpio@f7027000 {
- gpio-line-names =
- "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */
- "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */
- "", "NC", "NC", "NC", "", "";
- };
-
- gpio12: gpio@f7028000 {
- gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",
- "[BT_PCM_DO]",
- "NC", "NC", "NC", "NC",
- "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */
- };
-
- gpio13: gpio@f7029000 {
- gpio-line-names = "[UART0_RX]", "[UART0_TX]",
- "[BT_UART1_CTS]", "[BT_UART1_RTS]",
- "[BT_UART1_RX]", "[BT_UART1_TX]",
- "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */
- "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */
- };
-
- gpio14: gpio@f702a000 {
- gpio-line-names =
- "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */
- "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */
- "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */
- "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */
- "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */
- "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */
- "[I2C2_SCL]", "[I2C2_SDA]";
- };
-
- gpio15: gpio@f702b000 {
- gpio-line-names = "", "", "", "", "", "", "NC", "";
- };
-
- /* GPIO blocks 16 thru 19 do not appear to be routed to pins */
-
- dwmmc_0: dwmmc0@f723d000 {
- cap-mmc-highspeed;
- non-removable;
- bus-width = <0x8>;
- vmmc-supply = <&ldo19>;
- };
-
- dwmmc_1: dwmmc1@f723e000 {
- card-detect-delay = <200>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- vqmmc-supply = <&ldo7>;
- vmmc-supply = <&ldo10>;
- bus-width = <0x4>;
- disable-wp;
- cd-gpios = <&gpio1 0 1>;
- };
-
- dwmmc_2: dwmmc2@f723f000 {
- bus-width = <0x4>;
- non-removable;
- cap-power-off-card;
- vmmc-supply = <&reg_vdd_3v3>;
- mmc-pwrseq = <&wl1835_pwrseq>;
-
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1835";
- reg = <2>; /* sdio func num */
- /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- };
- };
-
leds {
compatible = "gpio-leds";
@@ -480,10 +264,26 @@
};
};
+&uart1 {
+ assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
+ assigned-clock-rates = <150000000>;
+ status = "ok";
+
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ clocks = <&pmic>;
+ clock-names = "ext_clock";
+ };
+};
+
&uart2 {
+ status = "ok";
label = "LS-UART0";
};
+
&uart3 {
+ status = "ok";
label = "LS-UART1";
};
@@ -506,6 +306,196 @@
};
};
+&dwmmc_0 {
+ cap-mmc-highspeed;
+ non-removable;
+ bus-width = <0x8>;
+ vmmc-supply = <&ldo19>;
+};
+
+&dwmmc_1 {
+ card-detect-delay = <200>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ vqmmc-supply = <&ldo7>;
+ vmmc-supply = <&ldo10>;
+ bus-width = <0x4>;
+ disable-wp;
+ cd-gpios = <&gpio1 0 1>;
+};
+
+&dwmmc_2 {
+ bus-width = <0x4>;
+ non-removable;
+ cap-power-off-card;
+ vmmc-supply = <&reg_vdd_3v3>;
+ mmc-pwrseq = <&wl1835_pwrseq>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1835";
+ reg = <2>; /* sdio func num */
+ /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+/*
+ * Legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (not routed from the SoC)
+ * "[PER]" = pin is muxed for peripheral (not GPIO)
+ * "" = no idea, schematic doesn't say, could be
+ * unrouted (not connected to any external pin)
+ * LSEC = Low Speed External Connector
+ * HSEC = High Speed External Connector
+ *
+ * Pin assignments taken from LeMaker and CircuitCo Schematics
+ * Rev A1.
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART2. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+&gpio0 {
+ gpio-line-names = "PWR_HOLD", "DSI_SEL",
+ "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",
+ "PWRON_DET", "5V_HUB_EN";
+};
+
+&gpio1 {
+ gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",
+ "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPIO-A", /* LSEC Pin 23: GPIO2_0 */
+ "GPIO-B", /* LSEC Pin 24: GPIO2_1 */
+ "GPIO-C", /* LSEC Pin 25: GPIO2_2 */
+ "GPIO-D", /* LSEC Pin 26: GPIO2_3 */
+ "GPIO-E", /* LSEC Pin 27: GPIO2_4 */
+ "USB_ID_DET", "USB_VBUS_DET",
+ "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
+};
+
+&gpio3 {
+ gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",
+ "WLAN_ACTIVE", "NC", "NC";
+};
+
+&gpio4 {
+ gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",
+ "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";
+};
+
+&gpio5 {
+ gpio-line-names = "NC", "NC",
+ "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
+ "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
+ "[AUX_SSI1]", "NC",
+ "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
+ "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */
+};
+
+&gpio6 {
+ gpio-line-names =
+ "[SPI0_DIN]", /* Pin 10: SPI0_DI */
+ "[SPI0_DOUT]", /* Pin 14: SPI0_DO */
+ "[SPI0_CS]", /* Pin 12: SPI0_CS_N */
+ "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
+ "NC", "NC", "NC",
+ "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */
+};
+
+&gpio7 {
+ gpio-line-names = "NC", "NC", "NC", "NC",
+ "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */
+ "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */
+ "NC", "NC";
+};
+
+&gpio8 {
+ gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",
+ "", "", "", "", "", "";
+};
+
+&gpio9 {
+ gpio-line-names = "",
+ "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */
+ "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */
+ "NC", "NC", "NC", "NC", "[ISP_CCLK0]";
+};
+
+&gpio10 {
+ gpio-line-names = "BOOT_SEL",
+ "[ISP_CCLK1]",
+ "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */
+ "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */
+ "NC", "NC",
+ "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */
+ "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */
+};
+
+&gpio11 {
+ gpio-line-names =
+ "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */
+ "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */
+ "", "NC", "NC", "NC", "", "";
+};
+
+&gpio12 {
+ gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",
+ "[BT_PCM_DO]",
+ "NC", "NC", "NC", "NC",
+ "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */
+};
+
+&gpio13 {
+ gpio-line-names = "[UART0_RX]", "[UART0_TX]",
+ "[BT_UART1_CTS]", "[BT_UART1_RTS]",
+ "[BT_UART1_RX]", "[BT_UART1_TX]",
+ "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */
+ "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */
+};
+
+&gpio14 {
+ gpio-line-names =
+ "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */
+ "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */
+ "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */
+ "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */
+ "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */
+ "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */
+ "[I2C2_SCL]", "[I2C2_SDA]";
+};
+
+&gpio15 {
+ gpio-line-names = "", "", "", "", "", "", "NC", "";
+};
+
+/* GPIO blocks 16 thru 19 do not appear to be routed to pins */
+
+
+&i2c0 {
+ status = "ok";
+};
+
+&i2c1 {
+ status = "ok";
+};
+
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -516,7 +506,7 @@
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <1 2>;
- pd-gpio = <&gpio0 4 0>;
+ pd-gpios = <&gpio0 4 0>;
adi,dsi-lanes = <4>;
#sound-dai-cells = <0>;
@@ -549,3 +539,7 @@
};
};
};
+
+&spi0 {
+ status = "ok";
+};
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi
index 2072b637b5..3d189d9f0d 100644
--- a/dts/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220.dtsi
@@ -302,7 +302,7 @@
mboxes = <&mailbox 1 0 11>;
};
- uart0: uart@f8015000 { /* console */
+ uart0: serial@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -311,7 +311,7 @@
clock-names = "uartclk", "apb_pclk";
};
- uart1: uart@f7111000 {
+ uart1: serial@f7111000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7111000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -325,7 +325,7 @@
status = "disabled";
};
- uart2: uart@f7112000 {
+ uart2: serial@f7112000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7112000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -337,7 +337,7 @@
status = "disabled";
};
- uart3: uart@f7113000 {
+ uart3: serial@f7113000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7113000 0x0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
@@ -349,7 +349,7 @@
status = "disabled";
};
- uart4: uart@f7114000 {
+ uart4: serial@f7114000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7114000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/intel/keembay-evm.dts b/dts/src/arm64/intel/keembay-evm.dts
new file mode 100644
index 0000000000..466c85363a
--- /dev/null
+++ b/dts/src/arm64/intel/keembay-evm.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020, Intel Corporation
+ *
+ * Device tree describing Keem Bay EVM board.
+ */
+
+/dts-v1/;
+
+#include "keembay-soc.dtsi"
+
+/ {
+ model = "Keem Bay EVM";
+ compatible = "intel,keembay-evm", "intel,keembay";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2GB of DDR memory. */
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/intel/keembay-soc.dtsi b/dts/src/arm64/intel/keembay-soc.dtsi
new file mode 100644
index 0000000000..781761d294
--- /dev/null
+++ b/dts/src/arm64/intel/keembay-soc.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020, Intel Corporation.
+ *
+ * Device tree describing Keem Bay SoC.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ gic: interrupt-controller@20500000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
+ <0x0 0x20580000 0x0 0x80000>; /* GICR */
+ /* VGIC maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Secure, non-secure, virtual, and hypervisor */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart0: serial@20150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20150000 0x0 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@20160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20160000 0x0 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@20170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20170000 0x0 0x100>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@20180000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20180000 0x0 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/src/arm64/intel/socfpga_agilex.dtsi b/dts/src/arm64/intel/socfpga_agilex.dtsi
index f52de8f780..9d7f19e97d 100644
--- a/dts/src/arm64/intel/socfpga_agilex.dtsi
+++ b/dts/src/arm64/intel/socfpga_agilex.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/agilex-clock.h>
/ {
compatible = "intel,socfpga-agilex";
@@ -101,6 +102,40 @@
fpga-mgr = <&fpga_mgr>;
};
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,agilex-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
@@ -114,6 +149,8 @@
snps,multicast-filter-bins = <256>;
iommus = <&smmu 1>;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ clocks = <&clkmgr AGILEX_EMAC0_CLK>;
+ clock-names = "stmmaceth";
status = "disabled";
};
@@ -130,6 +167,8 @@
snps,multicast-filter-bins = <256>;
iommus = <&smmu 2>;
altr,sysmgr-syscon = <&sysmgr 0x48 8>;
+ clocks = <&clkmgr AGILEX_EMAC1_CLK>;
+ clock-names = "stmmaceth";
status = "disabled";
};
@@ -146,6 +185,8 @@
snps,multicast-filter-bins = <256>;
iommus = <&smmu 3>;
altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
+ clocks = <&clkmgr AGILEX_EMAC2_CLK>;
+ clock-names = "stmmaceth";
status = "disabled";
};
@@ -196,6 +237,7 @@
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -206,6 +248,7 @@
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -216,6 +259,7 @@
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -226,6 +270,7 @@
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -236,6 +281,7 @@
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -248,6 +294,9 @@
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
+ clocks = <&clkmgr AGILEX_L4_MP_CLK>,
+ <&clkmgr AGILEX_SDMMC_CLK>;
+ clock-names = "biu", "ciu";
iommus = <&smmu 5>;
status = "disabled";
};
@@ -260,6 +309,10 @@
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
+ clocks = <&clkmgr AGILEX_NAND_CLK>,
+ <&clkmgr AGILEX_NAND_X_CLK>,
+ <&clkmgr AGILEX_NAND_ECC_CLK>;
+ clock-names = "nand", "nand_x", "ecc";
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
@@ -286,6 +339,8 @@
#dma-requests = <32>;
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
+ clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
+ clock-names = "apb_pclk";
};
rst: rstmgr@ffd11000 {
@@ -312,6 +367,9 @@
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
stream-match-mask = <0x7ff0>;
+ clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
+ <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
+ <&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled";
};
@@ -322,8 +380,10 @@
reg = <0xffda4000 0x1000>;
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
+ clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled";
};
@@ -334,8 +394,10 @@
reg = <0xffda5000 0x1000>;
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
+ clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled";
};
@@ -357,24 +419,32 @@
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;
reg = <0xffc03000 0x100>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+ clock-names = "timer";
};
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>;
reg = <0xffc03100 0x100>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+ clock-names = "timer";
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>;
reg = <0xffd00000 0x100>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+ clock-names = "timer";
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>;
reg = <0xffd00100 0x100>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+ clock-names = "timer";
};
uart0: serial0@ffc02000 {
@@ -385,6 +455,7 @@
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
status = "disabled";
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
};
uart1: serial1@ffc02100 {
@@ -394,6 +465,7 @@
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled";
};
@@ -411,6 +483,7 @@
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
+ clocks = <&clkmgr AGILEX_USB_CLK>;
iommus = <&smmu 6>;
status = "disabled";
};
@@ -424,6 +497,7 @@
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
iommus = <&smmu 7>;
+ clocks = <&clkmgr AGILEX_USB_CLK>;
status = "disabled";
};
@@ -432,6 +506,7 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled";
};
@@ -440,6 +515,7 @@
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled";
};
@@ -448,6 +524,7 @@
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled";
};
@@ -456,6 +533,7 @@
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled";
};
@@ -533,6 +611,7 @@
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
diff --git a/dts/src/arm64/intel/socfpga_agilex_socdk.dts b/dts/src/arm64/intel/socfpga_agilex_socdk.dts
index 92f478def7..96c50d4828 100644
--- a/dts/src/arm64/intel/socfpga_agilex_socdk.dts
+++ b/dts/src/arm64/intel/socfpga_agilex_socdk.dts
@@ -41,6 +41,14 @@
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
};
&gpio1 {
diff --git a/dts/src/arm64/marvell/armada-7040.dtsi b/dts/src/arm64/marvell/armada-7040.dtsi
index 4724721577..7a3198cd7a 100644
--- a/dts/src/arm64/marvell/armada-7040.dtsi
+++ b/dts/src/arm64/marvell/armada-7040.dtsi
@@ -14,3 +14,31 @@
compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
+
+&smmu {
+ status = "okay";
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
diff --git a/dts/src/arm64/marvell/armada-8040.dtsi b/dts/src/arm64/marvell/armada-8040.dtsi
index 7699b19224..79e8ce59ba 100644
--- a/dts/src/arm64/marvell/armada-8040.dtsi
+++ b/dts/src/arm64/marvell/armada-8040.dtsi
@@ -15,6 +15,18 @@
"marvell,armada-ap806";
};
+&smmu {
+ status = "okay";
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
* in CP master is not connected (by package) to the oscillator. So
* disable it. However, the RTC clock in CP slave is connected to the
@@ -23,3 +35,31 @@
&cp0_rtc {
status = "disabled";
};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
+
+&cp1_sata0 {
+ iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+ iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+ iommus = <&smmu 0x451>;
+};
diff --git a/dts/src/arm64/marvell/armada-ap80x.dtsi b/dts/src/arm64/marvell/armada-ap80x.dtsi
index 7f9b9a6477..12e477f1ae 100644
--- a/dts/src/arm64/marvell/armada-ap80x.dtsi
+++ b/dts/src/arm64/marvell/armada-ap80x.dtsi
@@ -56,6 +56,24 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@5000000 {
+ compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
diff --git a/dts/src/arm64/mediatek/mt6358.dtsi b/dts/src/arm64/mediatek/mt6358.dtsi
index 9361ada0c4..fa159b2037 100644
--- a/dts/src/arm64/mediatek/mt6358.dtsi
+++ b/dts/src/arm64/mediatek/mt6358.dtsi
@@ -16,6 +16,8 @@
};
mt6358regulator: mt6358regulator {
+ compatible = "mediatek,mt6358-regulator";
+
mt6358_vdram1_reg: buck_vdram1 {
regulator-name = "vdram1";
regulator-min-microvolt = <500000>;
diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi
index 70b1ffcab7..5e046f9d48 100644
--- a/dts/src/arm64/mediatek/mt8173.dtsi
+++ b/dts/src/arm64/mediatek/mt8173.dtsi
@@ -167,7 +167,7 @@
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <526>;
+ capacity-dmips-mhz = <740>;
};
cpu1: cpu@1 {
@@ -182,7 +182,7 @@
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <526>;
+ capacity-dmips-mhz = <740>;
};
cpu2: cpu@100 {
diff --git a/dts/src/arm64/mediatek/mt8183-evb.dts b/dts/src/arm64/mediatek/mt8183-evb.dts
index afd6ddbcbd..ae405bd8f0 100644
--- a/dts/src/arm64/mediatek/mt8183-evb.dts
+++ b/dts/src/arm64/mediatek/mt8183-evb.dts
@@ -205,7 +205,7 @@
};
};
- mmc0_pins_uhs: mmc0@0{
+ mmc0_pins_uhs: mmc0 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
@@ -264,7 +264,7 @@
};
};
- mmc1_pins_uhs: mmc1@0{
+ mmc1_pins_uhs: mmc1 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-krane-sku176.dts b/dts/src/arm64/mediatek/mt8183-kukui-krane-sku176.dts
new file mode 100644
index 0000000000..47113e275c
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-krane-sku176.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Device-tree for Krane sku176.
+ *
+ * SKU is a 8-bit value (0xb0 == 176):
+ * - Bits 7..4: Panel ID: 0xb (BOE)
+ * - Bits 3..0: SKU ID: 0x0 (default)
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-krane.dtsi"
+
+/ {
+ model = "MediaTek krane sku176 board";
+ compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi
new file mode 100644
index 0000000000..fbc471ccf8
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include "mt8183-kukui.dtsi"
+
+/ {
+ ppvarn_lcd: ppvarn-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvarn_lcd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ppvarn_lcd_en>;
+
+ enable-active-high;
+
+ gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
+ };
+
+ ppvarp_lcd: ppvarp-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvarp_lcd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ppvarp_lcd_en>;
+
+ enable-active-high;
+
+ gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
+ };
+
+ pp1800_lcd: pp1800-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1800_lcd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pp1800_lcd_en>;
+
+ enable-active-high;
+
+ gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&bluetooth {
+ firmware-name = "nvm_00440302_i2s_eu.bin";
+};
+
+&i2c0 {
+ status = "okay";
+
+ touchscreen4: touchscreen@5d {
+ compatible = "hid-over-i2c";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&open_touch>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_EDGE_FALLING>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+ };
+};
+
+&mt6358_vcama2_reg {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom@58 {
+ compatible = "atmel,24c32";
+ reg = <0x58>;
+ pagesize = <32>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom@54 {
+ compatible = "atmel,24c32";
+ reg = <0x54>;
+ pagesize = <32>;
+ };
+};
+
+&pio {
+ /* 192 lines */
+ gpio-line-names =
+ "SPI_AP_EC_CS_L",
+ "SPI_AP_EC_MOSI",
+ "SPI_AP_EC_CLK",
+ "I2S3_DO",
+ "USB_PD_INT_ODL",
+ "",
+ "",
+ "",
+ "",
+ "IT6505_HPD_L",
+ "I2S3_TDM_D3",
+ "SOC_I2C6_1V8_SCL",
+ "SOC_I2C6_1V8_SDA",
+ "DPI_D0",
+ "DPI_D1",
+ "DPI_D2",
+ "DPI_D3",
+ "DPI_D4",
+ "DPI_D5",
+ "DPI_D6",
+ "DPI_D7",
+ "DPI_D8",
+ "DPI_D9",
+ "DPI_D10",
+ "DPI_D11",
+ "DPI_HSYNC",
+ "DPI_VSYNC",
+ "DPI_DE",
+ "DPI_CK",
+ "AP_MSDC1_CLK",
+ "AP_MSDC1_DAT3",
+ "AP_MSDC1_CMD",
+ "AP_MSDC1_DAT0",
+ "AP_MSDC1_DAT2",
+ "AP_MSDC1_DAT1",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "OTG_EN",
+ "DRVBUS",
+ "DISP_PWM",
+ "DSI_TE",
+ "LCM_RST_1V8",
+ "AP_CTS_WIFI_RTS",
+ "AP_RTS_WIFI_CTS",
+ "SOC_I2C5_1V8_SCL",
+ "SOC_I2C5_1V8_SDA",
+ "SOC_I2C3_1V8_SCL",
+ "SOC_I2C3_1V8_SDA",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SOC_I2C1_1V8_SDA",
+ "SOC_I2C0_1V8_SDA",
+ "SOC_I2C0_1V8_SCL",
+ "SOC_I2C1_1V8_SCL",
+ "AP_SPI_H1_MISO",
+ "AP_SPI_H1_CS_L",
+ "AP_SPI_H1_MOSI",
+ "AP_SPI_H1_CLK",
+ "I2S5_BCK",
+ "I2S5_LRCK",
+ "I2S5_DO",
+ "BOOTBLOCK_EN_L",
+ "MT8183_KPCOL0",
+ "SPI_AP_EC_MISO",
+ "UART_DBG_TX_AP_RX",
+ "UART_AP_TX_DBG_RX",
+ "I2S2_MCK",
+ "I2S2_BCK",
+ "CLK_5M_WCAM",
+ "CLK_2M_UCAM",
+ "I2S2_LRCK",
+ "I2S2_DI",
+ "SOC_I2C2_1V8_SCL",
+ "SOC_I2C2_1V8_SDA",
+ "SOC_I2C4_1V8_SCL",
+ "SOC_I2C4_1V8_SDA",
+ "",
+ "SCL8",
+ "SDA8",
+ "FCAM_PWDN_L",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "I2S_PMIC",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ /*
+ * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
+ * call it BIOS_FLASH_WP_R_L.
+ */
+ "AP_FLASH_WP_L",
+ "EC_AP_INT_ODL",
+ "IT6505_INT_ODL",
+ "H1_INT_OD_L",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AP_SPI_FLASH_MISO",
+ "AP_SPI_FLASH_CS_L",
+ "AP_SPI_FLASH_MOSI",
+ "AP_SPI_FLASH_CLK",
+ "DA7219_IRQ",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+
+ ppvarp_lcd_en: ppvarp-lcd-en {
+ pins1 {
+ pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
+ output-low;
+ };
+ };
+
+ ppvarn_lcd_en: ppvarn-lcd-en {
+ pins1 {
+ pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
+ output-low;
+ };
+ };
+
+ pp1800_lcd_en: pp1800-lcd-en {
+ pins1 {
+ pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
+ output-low;
+ };
+ };
+
+ open_touch: open_touch {
+ irq_pin {
+ pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ rst_pin {
+ pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
+
+ /*
+ * The pen driver doesn't currently support driving
+ * this reset line. By specifying output-high here
+ * we're relying on the fact that this pin has a default
+ * pulldown at boot (which makes sure the pen was in
+ * reset if it was powered) and then we set it high here
+ * to take it out of reset. Better would be if the pen
+ * driver could control this and we could remove
+ * "output-high" here.
+ */
+ output-high;
+ };
+ };
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "LE_Krane";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/src/arm64/mediatek/mt8183-kukui.dtsi
new file mode 100644
index 0000000000..f0a070535b
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -0,0 +1,788 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "mt8183.dtsi"
+#include "mt6358.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ clk32k: oscillator1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ it6505_pp18_reg: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "it6505_pp18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 178 0>;
+ enable-active-high;
+ };
+
+ lcd_pp3300: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_pp3300";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ bl_pp5000: regulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "bl_pp5000";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mmc1_fixed_power: regulator3 {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc1_power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ mmc1_fixed_io: regulator4 {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc1_io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pp1800_alw: regulator5 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1800_alw";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pp3300_alw: regulator6 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_alw";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max98357a: codec0 {
+ compatible = "maxim,max98357a";
+ sdmode-gpios = <&pio 175 0>;
+ };
+
+ btsco: codec1 {
+ compatible = "linux,bt-sco";
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pins_pwrseq>;
+
+ /* Toggle WIFI_ENABLE to reset the chip. */
+ reset-gpios = <&pio 119 1>;
+ };
+
+ wifi_wakeup: wifi-wakeup {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pins_wakeup>;
+
+ wowlan {
+ label = "Wake on WiFi";
+ gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ tboard_thermistor1: thermal-sensor1 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 0>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = < (-5000) 4241
+ 0 4063
+ 5000 3856
+ 10000 3621
+ 15000 3364
+ 20000 3091
+ 25000 2810
+ 30000 2526
+ 35000 2247
+ 40000 1982
+ 45000 1734
+ 50000 1507
+ 55000 1305
+ 60000 1122
+ 65000 964
+ 70000 827
+ 75000 710
+ 80000 606
+ 85000 519
+ 90000 445
+ 95000 382
+ 100000 330
+ 105000 284
+ 110000 245
+ 115000 213
+ 120000 183
+ 125000 161>;
+ };
+
+ tboard_thermistor2: thermal-sensor2 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 1>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = < (-5000) 4241
+ 0 4063
+ 5000 3856
+ 10000 3621
+ 15000 3364
+ 20000 3091
+ 25000 2810
+ 30000 2526
+ 35000 2247
+ 40000 1982
+ 45000 1734
+ 50000 1507
+ 55000 1305
+ 60000 1122
+ 65000 964
+ 70000 827
+ 75000 710
+ 80000 606
+ 85000 519
+ 90000 445
+ 95000 382
+ 100000 330
+ 105000 284
+ 110000 245
+ 115000 213
+ 120000 183
+ 125000 161>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <&mt6358_vemc_reg>;
+ vqmmc-supply = <&mt6358_vio18_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
+ non-removable;
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_uhs>;
+ vmmc-supply = <&mmc1_fixed_power>;
+ vqmmc-supply = <&mmc1_fixed_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ drv-type = <2>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ cap-sdio-irq;
+ non-removable;
+ no-mmc;
+ no-sd;
+ assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qca_wifi: qca-wifi@1 {
+ compatible = "qcom,ath10k";
+ reg = <1>;
+ };
+};
+
+&mt6358_vdram2_reg {
+ regulator-always-on;
+};
+
+&mt6358codec {
+ Avdd-supply = <&mt6358_vaud28_reg>;
+};
+
+&mt6358_vsim1_reg {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+};
+
+&mt6358_vsim2_reg {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+};
+
+&pio {
+ bt_pins: bt-pins {
+ pins_bt_en {
+ pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
+ output-low;
+ };
+ };
+
+ ec_ap_int_odl: ec_ap_int_odl {
+ pins1 {
+ pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ h1_int_od_l: h1_int_od_l {
+ pins1 {
+ pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
+ input-enable;
+ };
+ };
+
+ i2c0_pins: i2c0 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
+ <PINMUX_GPIO83__FUNC_SCL0>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c1_pins: i2c1 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
+ <PINMUX_GPIO84__FUNC_SCL1>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c2_pins: i2c2 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
+ <PINMUX_GPIO104__FUNC_SDA2>;
+ bias-disable;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c3_pins: i2c3 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
+ <PINMUX_GPIO51__FUNC_SDA3>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c4_pins: i2c4 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
+ <PINMUX_GPIO106__FUNC_SDA4>;
+ bias-disable;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c5_pins: i2c5 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
+ <PINMUX_GPIO49__FUNC_SDA5>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ };
+ };
+
+ i2c6_pins: i2c6 {
+ pins_bus {
+ pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
+ <PINMUX_GPIO12__FUNC_SDA6>;
+ bias-disable;
+ };
+ };
+
+ mmc0_pins_default: mmc0-pins-default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-up-adv = <01>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-down-adv = <10>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-down-adv = <01>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-pins-uhs {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-up-adv = <01>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-down-adv = <10>;
+ };
+
+ pins_ds {
+ pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-down-adv = <10>;
+ };
+
+ pins_rst {
+ pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_14mA>;
+ mediatek,pull-up-adv = <01>;
+ };
+ };
+
+ mmc1_pins_default: mmc1-pins-default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
+ input-enable;
+ mediatek,pull-up-adv = <10>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
+ input-enable;
+ mediatek,pull-down-adv = <10>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-pins-uhs {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
+ drive-strength = <MTK_DRIVE_6mA>;
+ input-enable;
+ mediatek,pull-up-adv = <10>;
+ };
+
+ pins_clk {
+ pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ mediatek,pull-down-adv = <10>;
+ input-enable;
+ };
+ };
+
+ spi0_pins: spi0 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
+ <PINMUX_GPIO86__FUNC_GPIO86>,
+ <PINMUX_GPIO87__FUNC_SPI0_MO>,
+ <PINMUX_GPIO88__FUNC_SPI0_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi1_pins: spi1 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
+ <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
+ <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
+ <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi2_pins: spi2 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
+ <PINMUX_GPIO1__FUNC_SPI2_MO>,
+ <PINMUX_GPIO2__FUNC_SPI2_CLK>;
+ bias-disable;
+ };
+ pins_spi_mi {
+ pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
+ mediatek,pull-down-adv = <00>;
+ };
+ };
+
+ spi3_pins: spi3 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
+ <PINMUX_GPIO22__FUNC_SPI3_CSB>,
+ <PINMUX_GPIO23__FUNC_SPI3_MO>,
+ <PINMUX_GPIO24__FUNC_SPI3_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi4_pins: spi4 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
+ <PINMUX_GPIO18__FUNC_SPI4_CSB>,
+ <PINMUX_GPIO19__FUNC_SPI4_MO>,
+ <PINMUX_GPIO20__FUNC_SPI4_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi5_pins: spi5 {
+ pins_spi{
+ pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
+ <PINMUX_GPIO14__FUNC_SPI5_CSB>,
+ <PINMUX_GPIO15__FUNC_SPI5_MO>,
+ <PINMUX_GPIO16__FUNC_SPI5_CLK>;
+ bias-disable;
+ };
+ };
+
+ uart0_pins_default: uart0-pins-default {
+ pins_rx {
+ pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
+ input-enable;
+ bias-pull-up;
+ };
+ pins_tx {
+ pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins_default: uart1-pins-default {
+ pins_rx {
+ pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
+ input-enable;
+ bias-pull-up;
+ };
+ pins_tx {
+ pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
+ };
+ pins_rts {
+ pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
+ output-enable;
+ };
+ pins_cts {
+ pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
+ input-enable;
+ };
+ };
+
+ uart1_pins_sleep: uart1-pins-sleep {
+ pins_rx {
+ pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
+ input-enable;
+ bias-pull-up;
+ };
+ pins_tx {
+ pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
+ };
+ pins_rts {
+ pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
+ output-enable;
+ };
+ pins_cts {
+ pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
+ input-enable;
+ };
+ };
+
+ wifi_pins_pwrseq: wifi-pins-pwrseq {
+ pins_wifi_enable {
+ pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
+ output-low;
+ };
+ };
+
+ wifi_pins_wakeup: wifi-pins-wakeup {
+ pins_wifi_wakeup {
+ pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
+ input-enable;
+ };
+ };
+};
+
+&soc_data {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+ cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
+
+ cr50@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&h1_int_od_l>;
+ interrupt-parent = <&pio>;
+ interrupts = <153 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+ w25q64dw: spi-flash@0 {
+ compatible = "winbond,w25q64dw", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+ cros_ec: cros-ec@0 {
+ compatible = "google,cros-ec-spi";
+ reg = <0>;
+ spi-max-frequency = <3000000>;
+ interrupt-parent = <&pio>;
+ interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ec_ap_int_odl>;
+
+ i2c_tunnel: i2c-tunnel {
+ compatible = "google,cros-ec-i2c-tunnel";
+ google,remote-bus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbc_extcon: extcon0 {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <0>;
+ };
+ };
+};
+
+&spi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins>;
+ mediatek,pad-select = <0>;
+ status = "disabled";
+};
+
+&spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4_pins>;
+ mediatek,pad-select = <0>;
+ status = "disabled";
+};
+
+&spi5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi5_pins>;
+ mediatek,pad-select = <0>;
+ status = "disabled";
+};
+
+&ssusb {
+ dr_mode = "host";
+ wakeup-source;
+ vusb33-supply = <&mt6358_vusb_reg>;
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_default>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&uart1_pins_default>;
+ pinctrl-1 = <&uart1_pins_sleep>;
+ status = "okay";
+ interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
+ <&pio 121 IRQ_TYPE_EDGE_FALLING>;
+
+ bluetooth: bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pins>;
+ status = "okay";
+ compatible = "qcom,qca6174-bt";
+ enable-gpios = <&pio 120 0>;
+ clocks = <&clk32k>;
+ firmware-name = "nvm_00440302_i2s.bin";
+ };
+};
+
+&usb_host {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vusb33-supply = <&mt6358_vusb_reg>;
+ status = "okay";
+
+ hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ };
+};
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
diff --git a/dts/src/arm64/mediatek/mt8183.dtsi b/dts/src/arm64/mediatek/mt8183.dtsi
index 1e03c849dc..102105871d 100644
--- a/dts/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/src/arm64/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
+#include <dt-bindings/phy/phy.h>
#include "mt8183-pinfunc.h"
/ {
@@ -168,7 +169,7 @@
min-residency-us = <800>;
};
- CLUSTER_SLEEP0: cluster-sleep@0 {
+ CLUSTER_SLEEP0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010001>;
@@ -176,7 +177,7 @@
exit-latency-us = <400>;
min-residency-us = <1000>;
};
- CLUSTER_SLEEP1: cluster-sleep@1 {
+ CLUSTER_SLEEP1: cluster-sleep-1 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010001>;
@@ -285,6 +286,12 @@
#reset-cells = <1>;
};
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8183-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -642,6 +649,36 @@
status = "disabled";
};
+ ssusb: usb@11201000 {
+ compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci@11200000 {
+ compatible = "mediatek,mt8183-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ status = "disabled";
+ };
+ };
+
audiosys: syscon@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
@@ -678,6 +715,33 @@
reg = <0 0x11f10000 0 0x1000>;
};
+ u3phy: usb-phy@11f40000 {
+ compatible = "mediatek,mt8183-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #phy-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11f40000 0x1000>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <15>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@0700 {
+ reg = <0x0700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
diff --git a/dts/src/arm64/microchip/sparx5.dtsi b/dts/src/arm64/microchip/sparx5.dtsi
new file mode 100644
index 0000000000..cf712e8061
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "microchip,sparx5";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ lcpll_clk: lcpll-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500000000>;
+ };
+
+ clks: clock-controller@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ clocks = <&lcpll_clk>;
+ reg = <0x6 0x1110000c 0x24>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <625000000>;
+ };
+
+ axi: axi@600000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@600300000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
+ <0x6 0x00340000 0xc0000>, /* GICR */
+ <0x6 0x00200000 0x2000>, /* GICC */
+ <0x6 0x00210000 0x2000>, /* GICV */
+ <0x6 0x00220000 0x2000>; /* GICH */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@600100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x6 0x00100000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@600102000 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x6 0x00102000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ timer1: timer@600105000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x6 0x00105000 0x1000>;
+ clocks = <&ahb_clk>;
+ clock-names = "timer";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio: pinctrl@6110101e0 {
+ compatible = "microchip,sparx5-pinctrl";
+ reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 64>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_10", "GPIO_11";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart2";
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "twi";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "GPIO_28", "GPIO_29";
+ function = "twi2";
+ };
+ };
+
+ i2c0: i2c@600101000 {
+ compatible = "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x00101000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+
+ i2c1: i2c@600103000 {
+ compatible = "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x00103000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb125.dts b/dts/src/arm64/microchip/sparx5_pcb125.dts
new file mode 100644
index 0000000000..91ee5b6cfc
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb125.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/ {
+ model = "Sparx5 PCB125 Reference Board";
+ compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb134.dts b/dts/src/arm64/microchip/sparx5_pcb134.dts
new file mode 100644
index 0000000000..feee4e99ff
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb134.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi b/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi
new file mode 100644
index 0000000000..18a535a043
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c100 = &i2c100;
+ i2c101 = &i2c101;
+ i2c102 = &i2c102;
+ i2c103 = &i2c103;
+ i2c104 = &i2c104;
+ i2c105 = &i2c105;
+ i2c106 = &i2c106;
+ i2c107 = &i2c107;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ i2c110 = &i2c110;
+ i2c111 = &i2c111;
+ i2c112 = &i2c112;
+ i2c113 = &i2c113;
+ i2c114 = &i2c114;
+ i2c115 = &i2c115;
+ i2c116 = &i2c116;
+ i2c117 = &i2c117;
+ i2c118 = &i2c118;
+ i2c119 = &i2c119;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
+ "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
+ "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_16";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_19";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_4: i2cmux-4 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_5: i2cmux-5 {
+ pins = "GPIO_22";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_6: i2cmux-6 {
+ pins = "GPIO_36";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_7: i2cmux-7 {
+ pins = "GPIO_35";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_8: i2cmux-8 {
+ pins = "GPIO_50";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_9: i2cmux-9 {
+ pins = "GPIO_51";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_10: i2cmux-10 {
+ pins = "GPIO_56";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_11: i2cmux-11 {
+ pins = "GPIO_57";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&axi {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+ i2c0_emux: i2c0-emux@0 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+};
+
+&i2c0_imux {
+ pinctrl-names =
+ "i2c100", "i2c101", "i2c102", "i2c103",
+ "i2c104", "i2c105", "i2c106", "i2c107",
+ "i2c108", "i2c109", "i2c110", "i2c111", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_4>;
+ pinctrl-5 = <&i2cmux_5>;
+ pinctrl-6 = <&i2cmux_6>;
+ pinctrl-7 = <&i2cmux_7>;
+ pinctrl-8 = <&i2cmux_8>;
+ pinctrl-9 = <&i2cmux_9>;
+ pinctrl-10 = <&i2cmux_10>;
+ pinctrl-11 = <&i2cmux_11>;
+ pinctrl-12 = <&i2cmux_pins_i>;
+ i2c100: i2c_sfp1 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c101: i2c_sfp2 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c102: i2c_sfp3 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c103: i2c_sfp4 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c104: i2c_sfp5 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c105: i2c_sfp6 {
+ reg = <0x5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c106: i2c_sfp7 {
+ reg = <0x6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c107: i2c_sfp8 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c108: i2c_sfp9 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c_sfp10 {
+ reg = <0x9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c110: i2c_sfp11 {
+ reg = <0xa>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c111: i2c_sfp12 {
+ reg = <0xb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&i2c0_emux {
+ mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH
+ &gpio 60 GPIO_ACTIVE_HIGH
+ &gpio 61 GPIO_ACTIVE_HIGH
+ &gpio 54 GPIO_ACTIVE_HIGH>;
+ idle-state = <0x8>;
+ i2c112: i2c_sfp13 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c113: i2c_sfp14 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c114: i2c_sfp15 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c115: i2c_sfp16 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c116: i2c_sfp17 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c117: i2c_sfp18 {
+ reg = <0x5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c118: i2c_sfp19 {
+ reg = <0x6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c119: i2c_sfp20 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb134_emmc.dts b/dts/src/arm64/microchip/sparx5_pcb134_emmc.dts
new file mode 100644
index 0000000000..10081a6696
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb134_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb135.dts b/dts/src/arm64/microchip/sparx5_pcb135.dts
new file mode 100644
index 0000000000..20e409a9be
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb135.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi b/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi
new file mode 100644
index 0000000000..d71f11a10b
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c152 = &i2c152;
+ i2c153 = &i2c153;
+ i2c154 = &i2c154;
+ i2c155 = &i2c155;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_35", "GPIO_36",
+ "GPIO_50", "GPIO_51";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_s29: i2cmux-0 {
+ pins = "GPIO_35";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s30: i2cmux-1 {
+ pins = "GPIO_36";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s31: i2cmux-2 {
+ pins = "GPIO_50";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s32: i2cmux-3 {
+ pins = "GPIO_51";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&axi {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+};
+
+&i2c0_imux {
+ pinctrl-names =
+ "i2c152", "i2c153", "i2c154", "i2c155",
+ "idle";
+ pinctrl-0 = <&i2cmux_s29>;
+ pinctrl-1 = <&i2cmux_s30>;
+ pinctrl-2 = <&i2cmux_s31>;
+ pinctrl-3 = <&i2cmux_s32>;
+ pinctrl-4 = <&i2cmux_pins_i>;
+ i2c152: i2c_sfp1 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c153: i2c_sfp2 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c154: i2c_sfp3 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c155: i2c_sfp4 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb135_emmc.dts b/dts/src/arm64/microchip/sparx5_pcb135_emmc.dts
new file mode 100644
index 0000000000..741f0e1226
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb135_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb_common.dtsi b/dts/src/arm64/microchip/sparx5_pcb_common.dtsi
new file mode 100644
index 0000000000..9d1a082de3
--- /dev/null
+++ b/dts/src/arm64/microchip/sparx5_pcb_common.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5.dtsi"
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/nvidia/tegra132-norrin.dts b/dts/src/arm64/nvidia/tegra132-norrin.dts
index 9f3206c639..6e5f846566 100644
--- a/dts/src/arm64/nvidia/tegra132-norrin.dts
+++ b/dts/src/arm64/nvidia/tegra132-norrin.dts
@@ -18,7 +18,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
@@ -39,6 +39,9 @@
sor@54540000 {
status = "okay";
+ avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
+ vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>;
+
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
@@ -671,7 +674,7 @@
regulator-boot-on;
};
- ldo0 {
+ avdd_1v05_run: ldo0 {
regulator-name = "+1.05_RUN_AVDD";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
@@ -781,7 +784,6 @@
battery: smart-battery {
compatible = "sbs,sbs-battery";
reg = <0xb>;
- battery-name = "battery";
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <10>;
/* power-supplies = <&charger>; */
@@ -893,13 +895,108 @@
nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
};
+ usb@70090000 {
+ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
+ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
+
+ avddio-pex-supply = <&vdd_1v05_run>;
+ dvddio-pex-supply = <&vdd_1v05_run>;
+ avdd-usb-supply = <&vdd_3v3_lp0>;
+ hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
+
+ status = "okay";
+ };
+
+ padctl@7009f000 {
+ avdd-pll-utmip-supply = <&vddio_1v8>;
+ avdd-pll-erefe-supply = <&avdd_1v05_run>;
+ avdd-pex-pll-supply = <&vdd_1v05_run>;
+ hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+
+ pads {
+ usb2 {
+ status = "okay";
+
+ lanes {
+ usb2-0 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-1 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-2 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+ };
+ };
+
+ pcie {
+ status = "okay";
+
+ lanes {
+ pcie-0 {
+ nvidia,function = "usb3-ss";
+ status = "okay";
+ };
+
+ pcie-1 {
+ nvidia,function = "usb3-ss";
+ status = "okay";
+ };
+ };
+ };
+ };
+
+ ports {
+ usb2-0 {
+ status = "okay";
+ mode = "otg";
+
+ vbus-supply = <&vdd_usb1_vbus>;
+ };
+
+ usb2-1 {
+ status = "okay";
+ mode = "host";
+
+ vbus-supply = <&vdd_run_cam>;
+ };
+
+ usb2-2 {
+ status = "okay";
+ mode = "host";
+
+ vbus-supply = <&vdd_usb3_vbus>;
+ };
+
+ usb3-0 {
+ nvidia,usb2-companion = <0>;
+ status = "okay";
+ };
+
+ usb3-1 {
+ nvidia,usb2-companion = <2>;
+ status = "okay";
+ };
+ };
+ };
+
/* WIFI/BT module */
- sdhci@700b0000 {
+ mmc@700b0000 {
status = "disabled";
};
/* external SD/MMC */
- sdhci@700b0400 {
+ mmc@700b0400 {
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
@@ -909,39 +1006,12 @@
};
/* EMMC 4.51 */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
- usb@7d000000 {
- status = "okay";
- };
-
- usb-phy@7d000000 {
- status = "okay";
- vbus-supply = <&vdd_usb1_vbus>;
- };
-
- usb@7d004000 {
- status = "okay";
- };
-
- usb-phy@7d004000 {
- status = "okay";
- vbus-supply = <&vdd_run_cam>;
- };
-
- usb@7d008000 {
- status = "okay";
- };
-
- usb-phy@7d008000 {
- status = "okay";
- vbus-supply = <&vdd_usb3_vbus>;
- };
-
backlight: backlight {
compatible = "pwm-backlight";
@@ -955,17 +1025,10 @@
backlight-boot-off;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg=<0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -991,146 +1054,144 @@
panel: panel {
compatible = "innolux,n116bge";
+ power-supply = <&vdd_3v3_panel>;
backlight = <&backlight>;
ddc-i2c-bus = <&dpaux>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <19000000>;
+ regulator-max-microvolt = <19000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vdd_mux: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+VDD_MUX";
- regulator-min-microvolt = <19000000>;
- regulator-max-microvolt = <19000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "+5V_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_3v3_sys: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "+3.3V_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_run: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "+3.3V_RUN";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_3v3_hdmi: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_led: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_LED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_led: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "+VDD_LED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_mux>;
- };
+ vdd_usb1_vbus: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb1_vbus: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "+5V_USB_HS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_usb3_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_SS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb3_vbus: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "+5V_USB_SS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_3v3_panel: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_PANEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_panel: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "+3.3V_PANEL";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_hdmi_pll: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
- vdd_hdmi_pll: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
- vin-supply = <&vdd_1v05_run>;
- };
+ vdd_5v0_hdmi: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_5v0_hdmi: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "+5V_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_5v0_ts: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_VDD_TS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_5v0_ts: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "+5V_VDD_TS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_3v3_lp0: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /*
+ * TODO: find a way to wire this up with the USB EHCI
+ * controllers so that it can be enabled on demand.
+ */
+ regulator-always-on;
+ gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra132.dtsi b/dts/src/arm64/nvidia/tegra132.dtsi
index 11a1bb4285..e40281510c 100644
--- a/dts/src/arm64/nvidia/tegra132.dtsi
+++ b/dts/src/arm64/nvidia/tegra132.dtsi
@@ -17,9 +17,9 @@
pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+ reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
+ <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
+ <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -33,11 +33,11 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+ ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
clocks = <&tegra_car TEGRA124_CLK_PCIE>,
<&tegra_car TEGRA124_CLK_AFI>,
@@ -50,9 +50,6 @@
reset-names = "pex", "afi", "pcie_x";
status = "disabled";
- phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
- phy-names = "pcie";
-
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
@@ -83,10 +80,12 @@
};
host1x@50000000 {
- compatible = "nvidia,tegra124-host1x", "simple-bus";
+ compatible = "nvidia,tegra132-host1x",
+ "nvidia,tegra124-host1x";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
@@ -101,9 +100,8 @@
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP1>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA124_CLK_DISP1>;
+ clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
@@ -116,9 +114,8 @@
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP2>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA124_CLK_DISP2>;
+ clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
@@ -144,10 +141,11 @@
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SOR0>,
+ <&tegra_car TEGRA124_CLK_SOR0_OUT>,
<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA124_CLK_PLL_DP>,
<&tegra_car TEGRA124_CLK_CLK_M>;
- clock-names = "sor", "parent", "dp", "safe";
+ clock-names = "sor", "out", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
status = "disabled";
@@ -163,6 +161,11 @@
resets = <&tegra_car 181>;
reset-names = "dpaux";
status = "disabled";
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
@@ -607,7 +610,7 @@
};
emc: external-memory-controller@7001b000 {
- compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
+ compatible = "nvidia,tegra132-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_EMC>;
clock-names = "emc";
@@ -629,8 +632,6 @@
<&tegra_car 123>,
<&tegra_car 129>;
reset-names = "sata", "sata-oob", "sata-cold";
- phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
- phy-names = "sata-phy";
status = "disabled";
};
@@ -650,6 +651,41 @@
status = "disabled";
};
+ usb@70090000 {
+ compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
+ reg = <0x0 0x70090000 0x0 0x8000>,
+ <0x0 0x70098000 0x0 0x1000>,
+ <0x0 0x70099000 0x0 0x1000>;
+ reg-names = "hcd", "fpci", "ipfs";
+
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
+ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
+ <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
+ <&tegra_car TEGRA124_CLK_PLL_U_480M>,
+ <&tegra_car TEGRA124_CLK_CLK_M>,
+ <&tegra_car TEGRA124_CLK_PLL_E>;
+ clock-names = "xusb_host", "xusb_host_src",
+ "xusb_falcon_src", "xusb_ss",
+ "xusb_ss_src", "xusb_ss_div2",
+ "xusb_hs_src", "xusb_fs_src",
+ "pll_u_480m", "clk_m", "pll_e";
+ resets = <&tegra_car 89>, <&tegra_car 156>,
+ <&tegra_car 143>;
+ reset-names = "xusb_host", "xusb_ss", "xusb_src";
+
+ nvidia,xusb-padctl = <&padctl>;
+
+ status = "disabled";
+ };
+
padctl: padctl@7009f000 {
compatible = "nvidia,tegra132-xusb-padctl",
"nvidia,tegra124-xusb-padctl";
@@ -657,40 +693,130 @@
resets = <&tegra_car 142>;
reset-names = "padctl";
- #phy-cells = <1>;
+ pads {
+ usb2 {
+ status = "disabled";
+
+ lanes {
+ usb2-0 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb2-1 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb2-2 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
+ };
- phys {
- pcie-0 {
+ ulpi {
status = "disabled";
+
+ lanes {
+ ulpi-0 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
};
- sata-0 {
+ hsic {
status = "disabled";
+
+ lanes {
+ hsic-0 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ hsic-1 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
};
- usb3-0 {
+ pcie {
status = "disabled";
+
+ lanes {
+ pcie-0 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ pcie-1 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ pcie-2 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ pcie-3 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ pcie-4 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
};
- usb3-1 {
+ sata {
+ status = "disabled";
+
+ lanes {
+ sata-0 {
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
+ };
+ };
+
+ ports {
+ usb2-0 {
status = "disabled";
};
- utmi-0 {
+ usb2-1 {
status = "disabled";
};
- utmi-1 {
+ usb2-2 {
status = "disabled";
};
- utmi-2 {
+ hsic-0 {
+ status = "disabled";
+ };
+
+ hsic-1 {
+ status = "disabled";
+ };
+
+ usb3-0 {
+ status = "disabled";
+ };
+
+ usb3-1 {
status = "disabled";
};
};
};
- sdhci@700b0000 {
+ mmc@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -701,7 +827,7 @@
status = "disabled";
};
- sdhci@700b0200 {
+ mmc@700b0200 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -712,7 +838,7 @@
status = "disabled";
};
- sdhci@700b0400 {
+ mmc@700b0400 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -723,7 +849,7 @@
status = "disabled";
};
- sdhci@700b0600 {
+ mmc@700b0600 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -736,12 +862,12 @@
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra132-soctherm";
- reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
- 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
+ reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
+ <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
reg-names = "soctherm-reg", "ccroc-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
- <&tegra_car TEGRA124_CLK_SOC_THERM>;
+ <&tegra_car TEGRA124_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
@@ -992,6 +1118,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -1030,6 +1157,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -1067,6 +1195,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
diff --git a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
index 1af7f9ffb7..802b8c5248 100644
--- a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
+++ b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
@@ -103,7 +103,7 @@
};
/* SDMMC1 (SD/MMC) */
- sdhci@3400000 {
+ mmc@3400000 {
status = "okay";
vmmc-supply = <&vdd_sd>;
@@ -119,10 +119,6 @@
avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
avdd-usb-supply = <&vdd_3v3_sys>;
- dvdd-pex-supply = <&vdd_pex>;
- dvdd-pex-pll-supply = <&vdd_pex>;
- hvdd-pex-supply = <&vdd_1v8>;
- hvdd-pex-pll-supply = <&vdd_1v8>;
vclamp-usb-supply = <&vdd_1v8>;
vddio-hsic-supply = <&gnd>;
@@ -175,19 +171,18 @@
status = "okay";
mode = "otg";
vbus-supply = <&vdd_usb0>;
-
usb-role-switch;
+
connector {
- compatible = "usb-b-connector",
- "gpio-usb-b-connector";
+ compatible = "gpio-usb-b-connector",
+ "usb-b-connector";
label = "micro-USB";
type = "micro";
- vbus-gpio = <&gpio
- TEGRA186_MAIN_GPIO(X, 7)
- GPIO_ACTIVE_LOW>;
- id-gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&gpio
+ TEGRA186_MAIN_GPIO(X, 7)
+ GPIO_ACTIVE_LOW>;
+ id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
-
};
usb2-1 {
@@ -199,6 +194,7 @@
usb3-0 {
nvidia,usb2-companion = <1>;
+ vbus-supply = <&vdd_usb1>;
status = "okay";
};
};
@@ -227,8 +223,8 @@
reg = <0x57>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -286,8 +282,8 @@
sor@15580000 {
status = "okay";
- avdd-io-supply = <&vdd_hdmi_1v05>;
- vdd-pll-supply = <&vdd_1v8_ap>;
+ avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&ddc>;
@@ -333,62 +329,51 @@
};
};
- regulators {
- vdd_sd: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
-
- regulator-name = "SD_CARD_SW_PWR";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ vdd_sd: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "SD_CARD_SW_PWR";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
- gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6)
- GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
-
- vdd_hdmi: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
-
- regulator-name = "VDD_HDMI_5V0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_hdmi: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_HDMI_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
- vdd_usb0: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
+ gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- regulator-name = "VDD_USB0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ vdd_usb0: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_USB0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_5v0_sys>;
- };
+ gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- vdd_usb1: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- regulator-name = "VDD_USB1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vdd_usb1: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_USB1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vin-supply = <&vdd_5v0_sys>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra186-p3310.dtsi b/dts/src/arm64/nvidia/tegra186-p3310.dtsi
index 2fcaa2e643..53d92fdd7f 100644
--- a/dts/src/arm64/nvidia/tegra186-p3310.dtsi
+++ b/dts/src/arm64/nvidia/tegra186-p3310.dtsi
@@ -9,9 +9,6 @@
aliases {
ethernet0 = "/ethernet@2490000";
- sdhci0 = "/sdhci@3460000";
- sdhci1 = "/sdhci@3400000";
- serial0 = &uarta;
i2c0 = "/bpmp/i2c";
i2c1 = "/i2c@3160000";
i2c2 = "/i2c@c240000";
@@ -20,6 +17,9 @@
i2c5 = "/i2c@31c0000";
i2c6 = "/i2c@c250000";
i2c7 = "/i2c@31e0000";
+ mmc0 = "/mmc@3460000";
+ mmc1 = "/mmc@3400000";
+ serial0 = &uarta;
};
chosen {
@@ -27,7 +27,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
@@ -50,6 +50,8 @@
interrupt-parent = <&gpio>;
interrupts = <TEGRA186_MAIN_GPIO(M, 5)
IRQ_TYPE_LEVEL_LOW>;
+
+ #phy-cells = <0>;
};
};
};
@@ -133,7 +135,7 @@
};
/* SDMMC1 (SD/MMC) */
- sdhci@3400000 {
+ mmc@3400000 {
cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
@@ -141,12 +143,12 @@
};
/* SDMMC3 (SDIO) */
- sdhci@3440000 {
+ mmc@3440000 {
status = "okay";
};
/* SDMMC4 (eMMC) */
- sdhci@3460000 {
+ mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -172,8 +174,8 @@
reg = <0x50>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -390,45 +392,33 @@
method = "smc";
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gnd: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
-
- regulator-name = "GND";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
-
- regulator-name = "VDD_5V0_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ gnd: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "GND";
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vdd_1v8_ap: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- regulator-name = "VDD_1V8_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ vdd_1v8_ap: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- vin-supply = <&vdd_1v8>;
- };
+ vin-supply = <&vdd_1v8>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi
index 58100fb9cd..34d249d85d 100644
--- a/dts/src/arm64/nvidia/tegra186.dtsi
+++ b/dts/src/arm64/nvidia/tegra186.dtsi
@@ -60,6 +60,9 @@
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA186_RESET_EQOS>;
reset-names = "eqos";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_EQOS>;
status = "disabled";
@@ -139,12 +142,13 @@
};
};
- memory-controller@2c00000 {
+ mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ #interconnect-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
@@ -163,6 +167,8 @@
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
+ #interconnect-cells = <0>;
+
nvidia,bpmp = <&bpmp>;
};
};
@@ -327,7 +333,7 @@
status = "disabled";
};
- sdmmc1: sdhci@3400000 {
+ sdmmc1: mmc@3400000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -335,6 +341,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC1>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
@@ -353,7 +362,7 @@
status = "disabled";
};
- sdmmc2: sdhci@3420000 {
+ sdmmc2: mmc@3420000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03420000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -361,6 +370,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC2>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc2_3v3>;
@@ -374,7 +386,7 @@
status = "disabled";
};
- sdmmc3: sdhci@3440000 {
+ sdmmc3: mmc@3440000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03440000 0x0 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
@@ -382,6 +394,9 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC3>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
@@ -397,7 +412,7 @@
status = "disabled";
};
- sdmmc4: sdhci@3460000 {
+ sdmmc4: mmc@3460000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
@@ -408,6 +423,9 @@
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
@@ -436,6 +454,9 @@
<&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_HDA>;
status = "disabled";
};
@@ -547,8 +568,7 @@
<0x0 0x03538000 0x0 0x1000>;
reg-names = "hcd", "fpci";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
<&bpmp TEGRA186_CLK_XUSB_FALCON>,
<&bpmp TEGRA186_CLK_XUSB_SS>,
@@ -564,6 +584,9 @@
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
power-domain-names = "xusb_host", "xusb_ss";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
#address-cells = <1>;
#size-cells = <0>;
@@ -752,9 +775,9 @@
compatible = "nvidia,tegra186-pcie";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
device_type = "pci";
- reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
+ reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
+ <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
+ <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
@@ -769,22 +792,26 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
- 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
- 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
- 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+ ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
+ <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
+ <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
+ <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
- clocks = <&bpmp TEGRA186_CLK_AFI>,
- <&bpmp TEGRA186_CLK_PCIE>,
+ clocks = <&bpmp TEGRA186_CLK_PCIE>,
+ <&bpmp TEGRA186_CLK_AFI>,
<&bpmp TEGRA186_CLK_PLLE>;
- clock-names = "afi", "pex", "pll_e";
+ clock-names = "pex", "afi", "pll_e";
- resets = <&bpmp TEGRA186_RESET_AFI>,
- <&bpmp TEGRA186_RESET_PCIE>,
+ resets = <&bpmp TEGRA186_RESET_PCIE>,
+ <&bpmp TEGRA186_RESET_AFI>,
<&bpmp TEGRA186_RESET_PCIEXCLK>;
- reset-names = "afi", "pex", "pcie_x";
+ reset-names = "pex", "afi", "pcie_x";
+
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_AFI>;
iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
@@ -906,12 +933,13 @@
};
host1x@13e00000 {
- compatible = "nvidia,tegra186-host1x", "simple-bus";
+ compatible = "nvidia,tegra186-host1x";
reg = <0x0 0x13e00000 0x0 0x10000>,
<0x0 0x13e10000 0x0 0x10000>;
reg-names = "hypervisor", "vm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "syncpt", "host1x";
clocks = <&bpmp TEGRA186_CLK_HOST1X>;
clock-names = "host1x";
resets = <&bpmp TEGRA186_RESET_HOST1X>;
@@ -921,6 +949,10 @@
#size-cells = <1>;
ranges = <0x15000000 0x0 0x15000000 0x01000000>;
+
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
+ interconnect-names = "dma-mem";
+
iommus = <&smmu TEGRA186_SID_HOST1X>;
dpaux1: dpaux@15040000 {
@@ -958,7 +990,7 @@
};
display-hub@15200000 {
- compatible = "nvidia,tegra186-display", "simple-bus";
+ compatible = "nvidia,tegra186-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
@@ -992,6 +1024,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
@@ -1008,6 +1043,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
@@ -1024,6 +1062,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1>;
@@ -1056,6 +1097,9 @@
reset-names = "vic";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_VIC>;
};
@@ -1199,8 +1243,8 @@
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
<0x0 0x18000000 0x0 0x1000000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
@@ -1211,25 +1255,28 @@
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
+ interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
};
- sysram@30000000 {
+ sram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x30000000 0x50000>;
- cpu_bpmp_tx: shmem@4e000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4e000 0x0 0x1000>;
+ cpu_bpmp_tx: sram@4e000 {
+ reg = <0x4e000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
- cpu_bpmp_rx: shmem@4f000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4f000 0x0 0x1000>;
+ cpu_bpmp_rx: sram@4f000 {
+ reg = <0x4f000 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
@@ -1237,6 +1284,11 @@
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
diff --git a/dts/src/arm64/nvidia/tegra194-p2888.dtsi b/dts/src/arm64/nvidia/tegra194-p2888.dtsi
index b96eb4e145..4c005b8112 100644
--- a/dts/src/arm64/nvidia/tegra194-p2888.dtsi
+++ b/dts/src/arm64/nvidia/tegra194-p2888.dtsi
@@ -8,18 +8,18 @@
compatible = "nvidia,p2888", "nvidia,tegra194";
aliases {
- ethernet0 = "/cbb@0/ethernet@2490000";
- sdhci0 = "/cbb@0/sdhci@3460000";
- sdhci1 = "/cbb@0/sdhci@3400000";
- serial0 = &tcu;
+ ethernet0 = "/bus@0/ethernet@2490000";
i2c0 = "/bpmp/i2c";
- i2c1 = "/cbb@0/i2c@3160000";
- i2c2 = "/cbb@0/i2c@c240000";
- i2c3 = "/cbb@0/i2c@3180000";
- i2c4 = "/cbb@0/i2c@3190000";
- i2c5 = "/cbb@0/i2c@31c0000";
- i2c6 = "/cbb@0/i2c@c250000";
- i2c7 = "/cbb@0/i2c@31e0000";
+ i2c1 = "/bus@0/i2c@3160000";
+ i2c2 = "/bus@0/i2c@c240000";
+ i2c3 = "/bus@0/i2c@3180000";
+ i2c4 = "/bus@0/i2c@3190000";
+ i2c5 = "/bus@0/i2c@31c0000";
+ i2c6 = "/bus@0/i2c@c250000";
+ i2c7 = "/bus@0/i2c@31e0000";
+ mmc0 = "/bus@0/mmc@3460000";
+ mmc1 = "/bus@0/mmc@3400000";
+ serial0 = &tcu;
};
chosen {
@@ -27,7 +27,7 @@
stdout-path = "serial0:115200n8";
};
- cbb@0 {
+ bus@0 {
ethernet@2490000 {
status = "okay";
@@ -44,6 +44,7 @@
reg = <0x0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
+ #phy-cells = <0>;
};
};
};
@@ -57,12 +58,12 @@
};
/* SDMMC1 (SD/MMC) */
- sdhci@3400000 {
+ mmc@3400000 {
cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
};
/* SDMMC4 (eMMC) */
- sdhci@3460000 {
+ mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -292,65 +293,49 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_5v0_sys: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
-
- regulator-name = "VIN_SYS_5V0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_hdmi: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
-
- regulator-name = "VDD_5V0_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vdd_3v3_pcie: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
-
- regulator-name = "PEX_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- enable-active-high;
- };
+ vdd_5v0_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN_SYS_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vdd_12v_pcie: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
+ vdd_hdmi: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- regulator-name = "VDD_12V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- };
+ vdd_3v3_pcie: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "PEX_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
- vdd_5v_sata: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
+ vdd_12v_pcie: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_12V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ };
- regulator-name = "VDD_5V_SATA";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_5v_sata: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V_SATA";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
diff --git a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
index e15d1eac05..90b6ea5467 100644
--- a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
+++ b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
@@ -10,7 +10,7 @@
model = "NVIDIA Jetson AGX Xavier Developer Kit";
compatible = "nvidia,p2972-0000", "nvidia,tegra194";
- cbb@0 {
+ bus@0 {
aconnect@2900000 {
status = "okay";
@@ -28,7 +28,7 @@
};
/* SDMMC1 (SD/MMC) */
- sdhci@3400000 {
+ mmc@3400000 {
status = "okay";
};
@@ -93,10 +93,10 @@
usb@3610000 {
status = "okay";
- phys = <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
- <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
- <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
- <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
+ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+ <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3";
};
@@ -145,8 +145,8 @@
sor@15b80000 {
status = "okay";
- avdd-io-supply = <&vdd_1v0>;
- vdd-pll-supply = <&vdd_1v8hs>;
+ avdd-io-hdmi-dp-supply = <&vdd_1v0>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&ddc>;
diff --git a/dts/src/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts b/dts/src/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts
new file mode 100644
index 0000000000..c1c589805d
--- /dev/null
+++ b/dts/src/arm64/nvidia/tegra194-p3509-0000+p3668-0000.dts
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+#include "tegra194-p3668-0000.dtsi"
+
+/ {
+ model = "NVIDIA Jetson Xavier NX Developer Kit";
+ compatible = "nvidia,p3509-0000+p3668-0000", "nvidia,tegra194";
+
+ bus@0 {
+ aconnect@2900000 {
+ status = "okay";
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a40000 {
+ status = "okay";
+ };
+ };
+
+ ddc: i2c@3190000 {
+ status = "okay";
+ };
+
+ hda@3510000 {
+ nvidia,model = "jetson-xavier-nx-hda";
+ status = "okay";
+ };
+
+ padctl@3520000 {
+ status = "okay";
+
+ pads {
+ usb2 {
+ lanes {
+ usb2-1 {
+ status = "okay";
+ };
+
+ usb2-2 {
+ status = "okay";
+ };
+ };
+ };
+
+ usb3 {
+ lanes {
+ usb3-2 {
+ status = "okay";
+ };
+ };
+ };
+ };
+
+ ports {
+ usb2-1 {
+ mode = "host";
+ status = "okay";
+ };
+
+ usb2-2 {
+ mode = "host";
+ vbus-supply = <&vdd_5v0_sys>;
+ status = "okay";
+ };
+
+ usb3-2 {
+ nvidia,usb2-companion = <1>;
+ vbus-supply = <&vdd_5v0_sys>;
+ status = "okay";
+ };
+ };
+ };
+
+ usb@3610000 {
+ status = "okay";
+
+ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+ <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+ phy-names = "usb2-1", "usb2-2", "usb3-2";
+ };
+
+ pwm@32d0000 {
+ status = "okay";
+ };
+
+ host1x@13e00000 {
+ display-hub@15200000 {
+ status = "okay";
+ };
+
+ dpaux@155c0000 {
+ status = "okay";
+ };
+
+ dpaux@155d0000 {
+ status = "okay";
+ };
+
+ /* DP0 */
+ sor@15b00000 {
+ status = "okay";
+
+ avdd-io-hdmi-dp-supply = <&vdd_1v0>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
+
+ nvidia,dpaux = <&dpaux0>;
+ };
+
+ /* HDMI */
+ sor@15b40000 {
+ status = "okay";
+
+ avdd-io-hdmi-dp-supply = <&vdd_1v0>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
+ hdmi-supply = <&vdd_hdmi>;
+
+ nvidia,ddc-i2c-bus = <&ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 1)
+ GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+
+ pcie@14160000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_hsio_11>;
+ phy-names = "p2u-0";
+ };
+
+ pcie@141a0000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+
+ pcie_ep@141a0000 {
+ status = "disabled";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
+ GPIO_ACTIVE_HIGH>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+
+ fan: fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm6 0 45334>;
+
+ cooling-levels = <0 64 128 255>;
+ #cooling-cells = <2>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ force-recovery {
+ label = "Force Recovery";
+ gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0)
+ GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_SLEEP>;
+ debounce-interval = <10>;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4)
+ GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ vdd_5v0_sys: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_sys: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_ao: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_AO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_hdmi: regulator@104 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ thermal-zones {
+ cpu {
+ polling-delay = <0>;
+ polling-delay-passive = <500>;
+ status = "okay";
+
+ trips {
+ cpu_trip_critical: critical {
+ temperature = <96500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_trip_hot: hot {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active: active {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_passive: passive {
+ temperature = <30000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu-critical {
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_critical>;
+ };
+
+ cpu-hot {
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_hot>;
+ };
+
+ cpu-active {
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active>;
+ };
+
+ cpu-passive {
+ cooling-device = <&fan 0 0>;
+ trip = <&cpu_trip_passive>;
+ };
+ };
+ };
+
+ gpu {
+ polling-delay = <0>;
+ polling-delay-passive = <500>;
+ status = "okay";
+
+ trips {
+ gpu_alert0: critical {
+ temperature = <99000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aux {
+ polling-delay = <0>;
+ polling-delay-passive = <500>;
+ status = "okay";
+
+ trips {
+ aux_alert0: critical {
+ temperature = <90000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/nvidia/tegra194-p3668-0000.dtsi b/dts/src/arm64/nvidia/tegra194-p3668-0000.dtsi
new file mode 100644
index 0000000000..10cb836aea
--- /dev/null
+++ b/dts/src/arm64/nvidia/tegra194-p3668-0000.dtsi
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "tegra194.dtsi"
+
+#include <dt-bindings/mfd/max77620.h>
+
+/ {
+ model = "NVIDIA Jetson Xavier NX";
+ compatible = "nvidia,p3668-0000", "nvidia,tegra194";
+
+ aliases {
+ ethernet0 = "/bus@0/ethernet@2490000";
+ i2c0 = "/bpmp/i2c";
+ i2c1 = "/bus@0/i2c@3160000";
+ i2c2 = "/bus@0/i2c@c240000";
+ i2c3 = "/bus@0/i2c@3180000";
+ i2c4 = "/bus@0/i2c@3190000";
+ i2c5 = "/bus@0/i2c@31c0000";
+ i2c6 = "/bus@0/i2c@c250000";
+ i2c7 = "/bus@0/i2c@31e0000";
+ mmc0 = "/bus@0/mmc@3460000";
+ rtc0 = "/bpmp/i2c/pmic@3c";
+ rtc1 = "/bus@0/rtc@c2a0000";
+ serial0 = &tcu;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ bus@0 {
+ ethernet@2490000 {
+ status = "okay";
+
+ phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ phy-mode = "rgmii-id";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ memory-controller@2c00000 {
+ status = "okay";
+ };
+
+ serial@c280000 {
+ status = "okay";
+ };
+
+ /* SDMMC1 (SD/MMC) */
+ mmc@3400000 {
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
+ disable-wp;
+ vmmc-supply = <&vdd_3v3_sd>;
+ };
+
+ padctl@3520000 {
+ avdd-usb-supply = <&vdd_usb_3v3>;
+ vclamp-usb-supply = <&vdd_1v8ao>;
+
+ ports {
+ usb2-1 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb2-3 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb3-0 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb3-3 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+ };
+ };
+
+ rtc@c2a0000 {
+ status = "okay";
+ };
+
+ pmc@c360000 {
+ nvidia,invert-interrupt;
+ };
+ };
+
+ bpmp {
+ i2c {
+ status = "okay";
+
+ pmic: pmic@3c {
+ compatible = "maxim,max20024";
+ reg = <0x3c>;
+
+ interrupt-parent = <&pmc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&max20024_default>;
+
+ max20024_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ gpio1 {
+ pins = "gpio1";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio2 {
+ pins = "gpio2";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio3 {
+ pins = "gpio3";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio4 {
+ pins = "gpio4";
+ function = "32k-out1";
+ drive-push-pull = <1>;
+ };
+
+ gpio6 {
+ pins = "gpio6";
+ function = "gpio";
+ drive-push-pull = <1>;
+ };
+
+ gpio7 {
+ pins = "gpio7";
+ function = "gpio";
+ drive-push-pull = <0>;
+ };
+ };
+
+ fps {
+ fps0 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ };
+
+ fps1 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
+ };
+
+ fps2 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ };
+ };
+
+ regulators {
+ in-sd0-supply = <&vdd_5v0_sys>;
+ in-sd1-supply = <&vdd_5v0_sys>;
+ in-sd2-supply = <&vdd_5v0_sys>;
+ in-sd3-supply = <&vdd_5v0_sys>;
+ in-sd4-supply = <&vdd_5v0_sys>;
+
+ in-ldo0-1-supply = <&vdd_5v0_sys>;
+ in-ldo2-supply = <&vdd_5v0_sys>;
+ in-ldo3-5-supply = <&vdd_5v0_sys>;
+ in-ldo4-6-supply = <&vdd_5v0_sys>;
+ in-ldo7-8-supply = <&vdd_1v8ls>;
+
+ vdd_1v0: sd0 {
+ regulator-name = "VDDIO_SYS_1V0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8hs: sd1 {
+ regulator-name = "VDDIO_SYS_1V8HS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8ls: sd2 {
+ regulator-name = "VDDIO_SYS_1V8LS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8ao: sd3 {
+ regulator-name = "VDDIO_AO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd4 {
+ regulator-name = "VDD_DDR_1V1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo0 {
+ regulator-name = "VDD_RTC";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2 {
+ regulator-name = "VDDIO_AO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3 {
+ regulator-name = "VDD_EMMC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_usb_3v3: ldo5 {
+ regulator-name = "VDD_USB_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6 {
+ regulator-name = "VDD_SDIO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7 {
+ regulator-name = "AVDD_CSI_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
+ };
+ };
+
+ vdd_3v3_sd: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
+};
diff --git a/dts/src/arm64/nvidia/tegra194.dtsi b/dts/src/arm64/nvidia/tegra194.dtsi
index 4bc187a4ea..48160f4800 100644
--- a/dts/src/arm64/nvidia/tegra194.dtsi
+++ b/dts/src/arm64/nvidia/tegra194.dtsi
@@ -16,7 +16,7 @@
#size-cells = <2>;
/* control backbone */
- cbb@0 {
+ bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -59,6 +59,9 @@
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA194_RESET_EQOS>;
reset-names = "eqos";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
+ interconnect-names = "dma-mem", "write";
status = "disabled";
snps,write-requests = <1>;
@@ -141,8 +144,8 @@
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000
- 0xc300000 0x4000>;
+ reg = <0x2430000 0x17000>,
+ <0xc300000 0x4000>;
status = "okay";
@@ -176,6 +179,8 @@
reg = <0x02c00000 0x100000>,
<0x02b80000 0x040000>,
<0x01700000 0x100000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ #interconnect-cells = <1>;
status = "disabled";
#address-cells = <2>;
@@ -209,6 +214,8 @@
clocks = <&bpmp TEGRA194_CLK_EMC>;
clock-names = "emc";
+ #interconnect-cells = <0>;
+
nvidia,bpmp = <&bpmp>;
};
};
@@ -449,14 +456,17 @@
#pwm-cells = <2>;
};
- sdmmc1: sdhci@3400000 {
- compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ sdmmc1: mmc@3400000 {
+ compatible = "nvidia,tegra194-sdhci";
reg = <0x03400000 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
+ interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -471,14 +481,17 @@
status = "disabled";
};
- sdmmc3: sdhci@3440000 {
- compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ sdmmc3: mmc@3440000 {
+ compatible = "nvidia,tegra194-sdhci";
reg = <0x03440000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
+ interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -494,8 +507,8 @@
status = "disabled";
};
- sdmmc4: sdhci@3460000 {
- compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ sdmmc4: mmc@3460000 {
+ compatible = "nvidia,tegra194-sdhci";
reg = <0x03460000 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
@@ -506,6 +519,9 @@
<&bpmp TEGRA194_CLK_PLLC4>;
resets = <&bpmp TEGRA194_RESET_SDMMC4>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
+ interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -534,6 +550,9 @@
<&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
reset-names = "hda", "hda2codec_2x", "hda2hdmi";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
+ interconnect-names = "dma-mem", "write";
status = "disabled";
};
@@ -669,8 +688,7 @@
reg-names = "hcd", "fpci";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
<&bpmp TEGRA194_CLK_XUSB_FALCON>,
@@ -981,10 +999,7 @@
reg-names = "security", "gpio";
reg = <0xc2f0000 0x1000>,
<0xc2f1000 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1017,12 +1032,13 @@
};
host1x@13e00000 {
- compatible = "nvidia,tegra194-host1x", "simple-bus";
+ compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
<0x13e10000 0x10000>;
reg-names = "hypervisor", "vm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "syncpt", "host1x";
clocks = <&bpmp TEGRA194_CLK_HOST1X>;
clock-names = "host1x";
resets = <&bpmp TEGRA194_RESET_HOST1X>;
@@ -1032,9 +1048,11 @@
#size-cells = <1>;
ranges = <0x15000000 0x15000000 0x01000000>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
+ interconnect-names = "dma-mem";
display-hub@15200000 {
- compatible = "nvidia,tegra194-display", "simple-bus";
+ compatible = "nvidia,tegra194-display";
reg = <0x15200000 0x00040000>;
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
@@ -1067,6 +1085,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <0>;
@@ -1082,6 +1103,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <1>;
@@ -1097,6 +1121,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <2>;
@@ -1112,6 +1139,9 @@
reset-names = "dc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+ interconnect-names = "dma-mem", "read-1";
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <3>;
@@ -1128,6 +1158,9 @@
reset-names = "vic";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
+ interconnect-names = "dma-mem", "write";
};
dpaux0: dpaux@155c0000 {
@@ -1362,15 +1395,49 @@
nvidia,interface = <3>;
};
};
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>,
+ <&bpmp TEGRA194_CLK_FUSE>;
+ clock-names = "gpu", "pwr", "fuse";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ dma-coherent;
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
+ interconnect-names = "dma-mem", "read-0-hp", "write-0",
+ "read-1", "read-1-hp", "write-1",
+ "read-2", "read-2-hp", "write-2",
+ "read-3", "read-3-hp", "write-3";
+ };
};
pcie@14100000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
- reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1389,8 +1456,8 @@
<&bpmp TEGRA194_RESET_PEX0_CORE_1>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -1404,18 +1471,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+
+ ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
+ <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
+ interconnect-names = "read", "write";
};
pcie@14120000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
- reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1434,8 +1506,8 @@
<&bpmp TEGRA194_RESET_PEX0_CORE_2>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -1449,18 +1521,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+
+ ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
+ <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
+ interconnect-names = "read", "write";
};
pcie@14140000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
- reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1479,8 +1556,8 @@
<&bpmp TEGRA194_RESET_PEX0_CORE_3>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -1494,18 +1571,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+
+ ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
+ <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
+ interconnect-names = "read", "write";
};
pcie@14160000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
- reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1524,8 +1606,8 @@
<&bpmp TEGRA194_RESET_PEX0_CORE_4>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -1539,18 +1621,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+
+ ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
+ <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
+ interconnect-names = "read", "write";
};
pcie@14180000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
- reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1569,8 +1656,8 @@
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -1584,18 +1671,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+
+ ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
+ <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
+ interconnect-names = "read", "write";
};
pcie@141a0000 {
compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
- reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
status = "disabled";
@@ -1611,15 +1703,15 @@
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
- <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
+ <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
clock-names = "core", "core_m";
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
reset-names = "apb", "core";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
nvidia,bpmp = <&bpmp 5>;
@@ -1633,18 +1725,23 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+
+ ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
+ <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
+ <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
+
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
+ interconnect-names = "read", "write";
};
pcie_ep@14160000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
- reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
- 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
status = "disabled";
@@ -1673,10 +1770,10 @@
pcie_ep@14180000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
- reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
- 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
status = "disabled";
@@ -1705,10 +1802,10 @@
pcie_ep@141a0000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
- reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
- 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
status = "disabled";
@@ -1737,22 +1834,20 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
};
- sysram@40000000 {
+ sram@40000000 {
compatible = "nvidia,tegra194-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x50000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x50000>;
- cpu_bpmp_tx: shmem@4e000 {
- compatible = "nvidia,tegra194-bpmp-shmem";
+ cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
- cpu_bpmp_rx: shmem@4f000 {
- compatible = "nvidia,tegra194-bpmp-shmem";
+ cpu_bpmp_rx: sram@4f000 {
reg = <0x4f000 0x1000>;
label = "cpu-bpmp-rx";
pool;
@@ -1767,6 +1862,11 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@@ -1782,6 +1882,8 @@
};
cpus {
+ compatible = "nvidia,tegra194-ccplex";
+ nvidia,bpmp = <&bpmp>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm64/nvidia/tegra210-p2180.dtsi b/dts/src/arm64/nvidia/tegra210-p2180.dtsi
index cc6ed45a2b..6a4b50aaa2 100644
--- a/dts/src/arm64/nvidia/tegra210-p2180.dtsi
+++ b/dts/src/arm64/nvidia/tegra210-p2180.dtsi
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
};
@@ -274,8 +274,8 @@
reg = <0x50>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -293,24 +293,17 @@
};
/* eMMC */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
vqmmc-supply = <&vdd_1v8>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
@@ -342,18 +335,15 @@
method = "smc";
};
- regulators {
- vdd_gpu: regulator@100 {
- compatible = "pwm-regulator";
- reg = <100>;
- pwms = <&pwm 1 4880>;
- regulator-name = "VDD_GPU";
- regulator-min-microvolt = <710000>;
- regulator-max-microvolt = <1320000>;
- enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
- regulator-ramp-delay = <80>;
- regulator-enable-ramp-delay = <2000>;
- regulator-settling-time-us = <160>;
- };
+ vdd_gpu: regulator@100 {
+ compatible = "pwm-regulator";
+ pwms = <&pwm 1 4880>;
+ regulator-name = "VDD_GPU";
+ regulator-min-microvolt = <710000>;
+ regulator-max-microvolt = <1320000>;
+ enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ regulator-ramp-delay = <80>;
+ regulator-enable-ramp-delay = <2000>;
+ regulator-settling-time-us = <160>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
index ea0e1efa69..56adf287a8 100644
--- a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
+++ b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
@@ -87,8 +87,8 @@
reg = <0x57>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -122,7 +122,7 @@
status = "okay";
};
- agic@702f9000 {
+ interrupt-controller@702f9000 {
status = "okay";
};
};
diff --git a/dts/src/arm64/nvidia/tegra210-p2530.dtsi b/dts/src/arm64/nvidia/tegra210-p2530.dtsi
index d0dc039237..58aa051896 100644
--- a/dts/src/arm64/nvidia/tegra210-p2530.dtsi
+++ b/dts/src/arm64/nvidia/tegra210-p2530.dtsi
@@ -14,7 +14,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
@@ -34,23 +34,16 @@
};
/* eMMC */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
diff --git a/dts/src/arm64/nvidia/tegra210-p2597.dtsi b/dts/src/arm64/nvidia/tegra210-p2597.dtsi
index b57d837d5f..e18e1a9a30 100644
--- a/dts/src/arm64/nvidia/tegra210-p2597.dtsi
+++ b/dts/src/arm64/nvidia/tegra210-p2597.dtsi
@@ -27,8 +27,8 @@
sor@54580000 {
status = "okay";
- avdd-io-supply = <&avdd_1v05>;
- vdd-pll-supply = <&vdd_1v8>;
+ avdd-io-hdmi-dp-supply = <&avdd_1v05>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
@@ -1323,6 +1323,14 @@
#gpio-cells = <2>;
gpio-controller;
};
+
+ exp2: gpio@77 {
+ compatible = "ti,tca9539";
+ reg = <0x77>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
};
/* HDMI DDC */
@@ -1461,17 +1469,17 @@
usb2-0 {
status = "okay";
vbus-supply = <&vdd_usb_vbus_otg>;
+ usb-role-switch;
mode = "otg";
- usb-role-switch;
connector {
- compatible = "usb-b-connector",
- "gpio-usb-b-connector";
+ compatible = "gpio-usb-b-connector",
+ "usb-b-connector";
label = "micro-USB";
type = "micro";
- vbus-gpio = <&gpio TEGRA_GPIO(Z, 0)
- GPIO_ACTIVE_LOW>;
- id-gpio = <&pmic 0 0>;
+ vbus-gpios = <&gpio TEGRA_GPIO(Z, 0)
+ GPIO_ACTIVE_LOW>;
+ id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
};
@@ -1505,7 +1513,7 @@
};
/* MMC/SD */
- sdhci@700b0000 {
+ mmc@700b0000 {
status = "okay";
bus-width = <4>;
@@ -1523,152 +1531,6 @@
hvdd-usb-supply = <&vdd_1v8>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_sys_mux: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "VDD_SYS_MUX";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "VDD_5V0_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_sys_mux>;
- };
-
- vdd_3v3_sys: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "VDD_3V3_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_sys_mux>;
-
- regulator-enable-ramp-delay = <160>;
- regulator-disable-ramp-delay = <10000>;
- };
-
- vdd_5v0_io: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "VDD_5V0_IO_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_3v3_sd: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "VDD_3V3_SD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
-
- regulator-enable-ramp-delay = <472>;
- regulator-disable-ramp-delay = <4880>;
- };
-
- vdd_dsi_csi: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "AVDD_DSI_CSI_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- vin-supply = <&vdd_sys_1v2>;
- };
-
- vdd_3v3_dis: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "VDD_DIS_3V3_LCD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
-
- vdd_1v8_dis: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "VDD_LCD_1V8_DIS";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_1v8>;
- };
-
- vdd_5v0_rtl: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "RTL_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_usb_vbus: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "USB_VBUS_EN1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_usb_vbus_otg: regulator@11 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "USB_VBUS_EN0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_hdmi: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "VDD_HDMI_5V0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -1692,4 +1554,162 @@
linux,code = <KEY_VOLUMEUP>;
};
};
+
+ vdd_sys_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SYS_MUX";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_sys_mux>;
+ };
+
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_sys_mux>;
+
+ regulator-enable-ramp-delay = <160>;
+ regulator-disable-ramp-delay = <10000>;
+ };
+
+ vdd_5v0_io: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_IO_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_sd: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+
+ regulator-enable-ramp-delay = <472>;
+ regulator-disable-ramp-delay = <4880>;
+ };
+
+ vdd_dsi_csi: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "AVDD_DSI_CSI_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vdd_sys_1v2>;
+ };
+
+ vdd_3v3_dis: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_DIS_3V3_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_1v8_dis: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_LCD_1V8_DIS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_1v8>;
+ };
+
+ vdd_5v0_rtl: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "RTL_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_usb_vbus: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_VBUS_EN1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_usb_vbus_otg: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_VBUS_EN0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_hdmi: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_HDMI_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_cam_1v2: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cam-1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&exp2 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_cam_2v8: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cam-2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&exp1 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vdd_cam_1v8: regulator@13 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cam-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&exp2 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
};
diff --git a/dts/src/arm64/nvidia/tegra210-p2894.dtsi b/dts/src/arm64/nvidia/tegra210-p2894.dtsi
index 88a4b9333d..41beab626d 100644
--- a/dts/src/arm64/nvidia/tegra210-p2894.dtsi
+++ b/dts/src/arm64/nvidia/tegra210-p2894.dtsi
@@ -16,7 +16,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
@@ -1328,7 +1328,7 @@
status = "okay";
clock-frequency = <400000>;
- max77620: max77620@3c {
+ pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -1343,12 +1343,12 @@
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux@0 {
- pin_gpio0 {
+ gpio0 {
pins = "gpio0";
function = "gpio";
};
- pin_gpio1 {
+ gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull = <1>;
@@ -1357,37 +1357,37 @@
maxim,active-fps-power-down-slot = <0>;
};
- pin_gpio2_3 {
- pins = "gpio2", "gpio3";
+ gpio2 {
+ pins = "gpio2";
function = "fps-out";
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
- pin_gpio4 {
+ gpio3 {
+ pins = "gpio3";
+ function = "fps-out";
+ drive-open-drain = <1>;
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ gpio4 {
pins = "gpio4";
function = "32k-out1";
};
- pin_gpio5_6_7 {
+ gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull = <1>;
};
-
- pin_gpio2 {
- maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
- };
-
- pin_gpio3 {
- maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
- };
};
- spmic-default-output-high {
+ gpio@0 {
gpio-hog;
output-high;
- gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>;
+ gpios = <2 GPIO_ACTIVE_HIGH>,
+ <7 GPIO_ACTIVE_HIGH>;
};
fps {
@@ -1580,23 +1580,16 @@
status = "okay";
};
- sdhci@700b0600 {
+ mmc@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -1642,223 +1635,198 @@
method = "smc";
};
- regulators {
- compatible = "simple-bus";
- device_type = "fixed-regulators";
- #address-cells = <1>;
- #size-cells = <0>;
-
- battery_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd-ac-bat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ battery_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-ac-bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_3v3: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd-3v3";
- regulator-enable-ramp-delay = <160>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
-
- gpio = <&max77620 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_3v3: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-3v3";
+ regulator-enable-ramp-delay = <160>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
- max77620_gpio7: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "max77620-gpio7";
- regulator-enable-ramp-delay = <240>;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- vin-supply = <&max77620_ldo0>;
- regulator-always-on;
- regulator-boot-on;
-
- gpio = <&max77620 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- lcd_bl_en: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "lcd-bl-en";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
+ max77620_gpio7: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "max77620-gpio7";
+ regulator-enable-ramp-delay = <240>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&max77620_ldo0>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ lcd_bl_en: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-bl-en";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
- en_vdd_sd: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "en-vdd-sd";
- regulator-enable-ramp-delay = <472>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3>;
-
- gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- en_vdd_cam: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "en-vdd-cam";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ en_vdd_sd: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "en-vdd-sd";
+ regulator-enable-ramp-delay = <472>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3>;
- gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_sys_boost: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "vdd-sys-boost";
- regulator-enable-ramp-delay = <3090>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
-
- gpio = <&max77620 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ en_vdd_cam: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "en-vdd-cam";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
- vdd_hdmi: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "vdd-hdmi";
- regulator-enable-ramp-delay = <468>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_sys_boost>;
- regulator-boot-on;
-
- gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- en_vdd_cpu_fixed: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "vdd-cpu-fixed";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
+ vdd_sys_boost: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-sys-boost";
+ regulator-enable-ramp-delay = <3090>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
- vdd_aux_3v3: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "aux-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_snsr_pm: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "snsr_pm";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ vdd_hdmi: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-hdmi";
+ regulator-enable-ramp-delay = <468>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_sys_boost>;
+ regulator-boot-on;
+
+ gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- enable-active-high;
- };
+ en_vdd_cpu_fixed: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-fixed";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
- vdd_usb_5v0: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- status = "disabled";
- regulator-name = "vdd-usb-5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_3v3>;
+ vdd_aux_3v3: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "aux-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
- enable-active-high;
- };
+ vdd_snsr_pm: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "snsr_pm";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
- vdd_cdc_1v2_aud: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- status = "disabled";
- regulator-name = "vdd_cdc_1v2_aud";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- startup-delay-us = <250000>;
+ enable-active-high;
+ };
- enable-active-high;
- };
+ vdd_usb_5v0: regulator@11 {
+ compatible = "regulator-fixed";
+ status = "disabled";
+ regulator-name = "vdd-usb-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_3v3>;
- vdd_disp_3v0: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "vdd-disp-3v0";
- regulator-enable-ramp-delay = <232>;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
-
- gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ enable-active-high;
+ };
- vdd_fan: regulator@13 {
- compatible = "regulator-fixed";
- reg = <13>;
- regulator-name = "vdd-fan";
- regulator-enable-ramp-delay = <284>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vdd_cdc_1v2_aud: regulator@101 {
+ compatible = "regulator-fixed";
+ status = "disabled";
+ regulator-name = "vdd_cdc_1v2_aud";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ startup-delay-us = <250000>;
- gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ enable-active-high;
+ };
- usb_vbus1: regulator@14 {
- compatible = "regulator-fixed";
- reg = <14>;
- regulator-name = "usb-vbus1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vdd_disp_3v0: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-disp-3v0";
+ regulator-enable-ramp-delay = <232>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
- gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- };
+ gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- usb_vbus2: regulator@15 {
- compatible = "regulator-fixed";
- reg = <15>;
- regulator-name = "usb-vbus2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vdd_fan: regulator@13 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-fan";
+ regulator-enable-ramp-delay = <284>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- };
+ gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_3v3_eth: regulator@16 {
- compatible = "regulator-fixed";
- reg = <16>;
- regulator-name = "vdd-3v3-eth-a02";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- };
+ usb_vbus1: regulator@14 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ };
+
+ usb_vbus2: regulator@15 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ };
+
+ vdd_3v3_eth: regulator@16 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-3v3-eth-a02";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
};
};
diff --git a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
index 9bc52fdb39..2282ea1c62 100644
--- a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
+++ b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
@@ -22,7 +22,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
};
@@ -64,6 +64,16 @@
status = "okay";
};
+ vi@54080000 {
+ status = "okay";
+
+ avdd-dsi-csi-supply = <&vdd_sys_1v2>;
+
+ csi@838 {
+ status = "okay";
+ };
+ };
+
sor@54540000 {
status = "okay";
@@ -77,8 +87,8 @@
sor@54580000 {
status = "okay";
- avdd-io-supply = <&avdd_1v05>;
- vdd-pll-supply = <&vdd_1v8>;
+ avdd-io-hdmi-dp-supply = <&avdd_1v05>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
@@ -101,6 +111,22 @@
status = "okay";
};
+ pinmux@700008d4 {
+ dvfs_pwm_active_state: dvfs_pwm_active {
+ dvfs_pwm_pbb1 {
+ nvidia,pins = "dvfs_pwm_pbb1";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+ dvfs_pwm_pbb1 {
+ nvidia,pins = "dvfs_pwm_pbb1";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
/* debug port */
serial@70006000 {
status = "okay";
@@ -119,8 +145,8 @@
reg = <0x50>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -130,8 +156,8 @@
reg = <0x57>;
vcc-supply = <&vdd_1v8>;
- address-bits = <8>;
- page-size = <8>;
+ address-width = <8>;
+ pagesize = <8>;
size = <256>;
read-only;
};
@@ -513,15 +539,15 @@
usb2-0 {
status = "okay";
mode = "peripheral";
-
usb-role-switch;
+
connector {
- compatible = "usb-b-connector",
- "gpio-usb-b-connector";
+ compatible = "gpio-usb-b-connector",
+ "usb-b-connector";
label = "micro-USB";
type = "micro";
- vbus-gpio = <&gpio TEGRA_GPIO(CC, 4)
- GPIO_ACTIVE_LOW>;
+ vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
+ GPIO_ACTIVE_LOW>;
};
};
@@ -543,7 +569,7 @@
};
};
- sdhci@700b0000 {
+ mmc@700b0000 {
status = "okay";
bus-width = <4>;
@@ -553,15 +579,7 @@
vmmc-supply = <&vdd_3v3_sd>;
};
- usb@700d0000 {
- status = "okay";
- phys = <&micro_b>;
- phy-names = "usb2-0";
- avddio-usb-supply = <&vdd_3v3_sys>;
- hvdd-usb-supply = <&vdd_1v8>;
- };
-
- sdhci@700b0400 {
+ mmc@700b0400 {
status = "okay";
bus-width = <4>;
@@ -574,17 +592,39 @@
wakeup-source;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ usb@700d0000 {
+ status = "okay";
+ phys = <&micro_b>;
+ phy-names = "usb2-0";
+ avddio-usb-supply = <&vdd_3v3_sys>;
+ hvdd-usb-supply = <&vdd_1v8>;
+ };
+
+ clock@70110000 {
+ status = "okay";
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,sample-rate = <25000>;
+
+ nvidia,pwm-min-microvolts = <708000>;
+ nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+ nvidia,pwm-to-pmic;
+ nvidia,pwm-tristate-microvolts = <1000000>;
+ nvidia,pwm-voltage-step-microvolts = <19200>;
+
+ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+ pinctrl-0 = <&dvfs_pwm_active_state>;
+ pinctrl-1 = <&dvfs_pwm_inactive_state>;
+ };
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
@@ -698,120 +738,109 @@
method = "smc";
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v0_sys: regulator@0 {
+ compatible = "regulator-fixed";
- vdd_5v0_sys: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
+ regulator-name = "VDD_5V0_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- regulator-name = "VDD_5V0_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_3v3_sys: regulator@1 {
+ compatible = "regulator-fixed";
- vdd_3v3_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "VDD_3V3_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-enable-ramp-delay = <240>;
- regulator-disable-ramp-delay = <11340>;
- regulator-always-on;
- regulator-boot-on;
-
- gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- vin-supply = <&vdd_5v0_sys>;
- };
+ regulator-name = "VDD_3V3_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-disable-ramp-delay = <11340>;
+ regulator-always-on;
+ regulator-boot-on;
- vdd_3v3_sd: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
+ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- regulator-name = "VDD_3V3_SD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ vdd_3v3_sd: regulator@2 {
+ compatible = "regulator-fixed";
- vin-supply = <&vdd_3v3_sys>;
- };
+ regulator-name = "VDD_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
- vdd_hdmi: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
+ gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- regulator-name = "VDD_HDMI_5V0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_hdmi: regulator@3 {
+ compatible = "regulator-fixed";
- vdd_hub_3v3: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
+ regulator-name = "VDD_HDMI_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
- regulator-name = "VDD_HUB_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ vdd_hub_3v3: regulator@4 {
+ compatible = "regulator-fixed";
- vin-supply = <&vdd_5v0_sys>;
- };
+ regulator-name = "VDD_HUB_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
- vdd_cpu: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
+ gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- regulator-name = "VDD_CPU";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ vdd_cpu: regulator@5 {
+ compatible = "regulator-fixed";
- vin-supply = <&vdd_5v0_sys>;
- };
+ regulator-name = "VDD_CPU";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
- vdd_gpu: regulator@6 {
- compatible = "pwm-regulator";
- reg = <6>;
- pwms = <&pwm 1 4880>;
- regulator-name = "VDD_GPU";
- regulator-min-microvolt = <710000>;
- regulator-max-microvolt = <1320000>;
- regulator-ramp-delay = <80>;
- regulator-enable-ramp-delay = <2000>;
- regulator-settling-time-us = <160>;
- enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vdd_5v0_sys>;
- };
+ gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
- avdd_io_edp_1v05: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- regulator-name = "AVDD_IO_EDP_1V05";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
+ vdd_gpu: regulator@6 {
+ compatible = "pwm-regulator";
+ pwms = <&pwm 1 4880>;
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ regulator-name = "VDD_GPU";
+ regulator-min-microvolt = <710000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-ramp-delay = <80>;
+ regulator-enable-ramp-delay = <2000>;
+ regulator-settling-time-us = <160>;
- vin-supply = <&avdd_1v05_pll>;
- };
+ enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ avdd_io_edp_1v05: regulator@7 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "AVDD_IO_EDP_1V05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&avdd_1v05_pll>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra210-smaug.dts b/dts/src/arm64/nvidia/tegra210-smaug.dts
index 2faab63905..bd78378248 100644
--- a/dts/src/arm64/nvidia/tegra210-smaug.dts
+++ b/dts/src/arm64/nvidia/tegra210-smaug.dts
@@ -1330,7 +1330,6 @@
battery: bq27742@55 {
compatible = "ti,bq27742";
reg = <0x55>;
- battery-name = "battery";
};
};
};
@@ -1355,11 +1354,11 @@
maxim,enable-active-discharge;
maxim,enable-bias-control;
maxim,enable-etr;
- maxim,enable-gpio = <&max77620 5 0>;
+ maxim,enable-gpio = <&pmic 5 0>;
maxim,externally-enable;
};
- max77620: max77620@3c {
+ pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -1373,8 +1372,8 @@
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
- max77620_default: pinmux@0 {
- pin_gpio {
+ max77620_default: pinmux {
+ gpio0_1_2_7 {
pins = "gpio0", "gpio1", "gpio2", "gpio7";
function = "gpio";
};
@@ -1384,7 +1383,7 @@
* sequence, So it must be sequenced up (automatically
* set by OTP) and down properly.
*/
- pin_gpio3 {
+ gpio3 {
pins = "gpio3";
function = "fps-out";
drive-open-drain = <1>;
@@ -1393,13 +1392,13 @@
maxim,active-fps-power-down-slot = <2>;
};
- pin_gpio5_6 {
+ gpio5_6 {
pins = "gpio5", "gpio6";
function = "gpio";
drive-push-pull = <1>;
};
- pin_32k {
+ gpio4 {
pins = "gpio4";
function = "32k-out1";
};
@@ -1697,7 +1696,7 @@
};
};
- sdhci@700b0600 {
+ mmc@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
@@ -1722,22 +1721,15 @@
status = "okay";
};
- agic@702f9000 {
+ interrupt-controller@702f9000 {
status = "okay";
};
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
@@ -1815,88 +1807,73 @@
method = "smc";
};
- regulators {
- compatible = "simple-bus";
- device_type = "fixed-regulators";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ppvar_sys: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "PPVAR_SYS";
- regulator-min-microvolt = <4400000>;
- regulator-max-microvolt = <4400000>;
- regulator-always-on;
- };
+ ppvar_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "PPVAR_SYS";
+ regulator-min-microvolt = <4400000>;
+ regulator-max-microvolt = <4400000>;
+ regulator-always-on;
+ };
- pplcd_vdd: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "PPLCD_VDD";
- regulator-min-microvolt = <4400000>;
- regulator-max-microvolt = <4400000>;
- gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
- enable-active-high;
- regulator-boot-on;
- };
+ pplcd_vdd: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "PPLCD_VDD";
+ regulator-min-microvolt = <4400000>;
+ regulator-max-microvolt = <4400000>;
+ gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
+ enable-active-high;
+ regulator-boot-on;
+ };
- pp3000_always: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "PP3000_ALWAYS";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
+ pp3000_always: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "PP3000_ALWAYS";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
- pp3300: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "PP3300";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- };
+ pp3300: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PP3300";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ };
- pp5000: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "PP5000";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ pp5000: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "PP5000";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- pp1800_lcdio: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "PP1800_LCDIO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
- enable-active-high;
- regulator-boot-on;
- };
+ pp1800_lcdio: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "PP1800_LCDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
+ enable-active-high;
+ regulator-boot-on;
+ };
- pp1800_cam: regulator@6 {
- compatible = "regulator-fixed";
- reg= <6>;
- regulator-name = "PP1800_CAM";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
- enable-active-high;
- };
+ pp1800_cam: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "PP1800_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
+ enable-active-high;
+ };
- usbc_vbus: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "USBC_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
+ usbc_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "USBC_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
};
diff --git a/dts/src/arm64/nvidia/tegra210.dtsi b/dts/src/arm64/nvidia/tegra210.dtsi
index 08655081f7..829f786af1 100644
--- a/dts/src/arm64/nvidia/tegra210.dtsi
+++ b/dts/src/arm64/nvidia/tegra210.dtsi
@@ -18,9 +18,9 @@
pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+ reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
+ <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
+ <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -34,11 +34,11 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+ ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
clocks = <&tegra_car TEGRA210_CLK_PCIE>,
<&tegra_car TEGRA210_CLK_AFI>,
@@ -86,10 +86,11 @@
};
host1x@50000000 {
- compatible = "nvidia,tegra210-host1x", "simple-bus";
+ compatible = "nvidia,tegra210-host1x";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
@@ -186,9 +187,8 @@
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_DISP1>,
- <&tegra_car TEGRA210_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA210_CLK_DISP1>;
+ clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
@@ -201,9 +201,8 @@
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_DISP2>,
- <&tegra_car TEGRA210_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA210_CLK_DISP2>;
+ clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
@@ -326,7 +325,7 @@
};
dpaux: dpaux@545c0000 {
- compatible = "nvidia,tegra124-dpaux";
+ compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
@@ -362,6 +361,9 @@
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_ISPA>;
+ resets = <&tegra_car 23>;
+ reset-names = "isp";
status = "disabled";
};
@@ -369,6 +371,9 @@
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_ISPB>;
+ resets = <&tegra_car 3>;
+ reset-names = "isp";
status = "disabled";
};
@@ -376,7 +381,16 @@
compatible = "nvidia,tegra210-i2c-vi";
reg = <0x0 0x546c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
+ <&tegra_car TEGRA210_CLK_I2CSLOW>;
+ clock-names = "div-clk", "slow";
+ resets = <&tegra_car 208>;
+ reset-names = "i2c";
+ power-domains = <&pd_venc>;
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
@@ -998,8 +1012,8 @@
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
- <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
+ <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
@@ -1007,7 +1021,7 @@
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
- "xusb_ss_div2", "xusb_ss_src",
+ "xusb_ss_src", "xusb_ss_div2",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
@@ -1176,8 +1190,8 @@
};
};
- sdhci@700b0000 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0000 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
@@ -1204,8 +1218,8 @@
status = "disabled";
};
- sdhci@700b0200 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0200 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
@@ -1221,8 +1235,8 @@
status = "disabled";
};
- sdhci@700b0400 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0400 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
@@ -1244,8 +1258,8 @@
status = "disabled";
};
- sdhci@700b0600 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0600 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
@@ -1356,7 +1370,7 @@
status = "disabled";
};
- agic: agic@702f9000 {
+ agic: interrupt-controller@702f9000 {
compatible = "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -1547,8 +1561,8 @@
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra210-soctherm";
- reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
- 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
+ reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
+ <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi
index 8a4b790aa7..194343510d 100644
--- a/dts/src/arm64/qcom/apq8016-sbc.dtsi
+++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi
@@ -453,22 +453,23 @@
*/
- sound: sound {
- compatible = "qcom,apq8016-sbc-sndcard";
- reg = <0x07702000 0x4>, <0x07702004 0x4>;
- reg-names = "mic-iomux", "spkr-iomux";
-
- status = "okay";
- pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
- pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
- pinctrl-names = "default", "sleep";
- qcom,model = "DB410c";
- qcom,audio-routing =
- "AMIC2", "MIC BIAS Internal2",
- "AMIC3", "MIC BIAS External1";
+ sound: sound {
+ compatible = "qcom,apq8016-sbc-sndcard";
+ reg = <0x07702000 0x4>, <0x07702004 0x4>;
+ reg-names = "mic-iomux", "spkr-iomux";
+
+ status = "okay";
+ pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
+ pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
+ pinctrl-names = "default", "sleep";
+ qcom,model = "DB410c";
+ qcom,audio-routing =
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
external-dai-link@0 {
link-name = "ADV7533";
- cpu { /* QUAT */
+ cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
@@ -476,26 +477,26 @@
};
};
- internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
- link-name = "WCD";
- cpu { /* PRIMARY */
- sound-dai = <&lpass MI2S_PRIMARY>;
- };
- codec {
- sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
- };
- };
-
- internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
- link-name = "WCD-Capture";
- cpu { /* PRIMARY */
- sound-dai = <&lpass MI2S_TERTIARY>;
- };
- codec {
- sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
- };
- };
- };
+ internal-codec-playback-dai-link@0 {
+ link-name = "WCD";
+ cpu {
+ sound-dai = <&lpass MI2S_PRIMARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
+ };
+ };
+
+ internal-codec-capture-dai-link@0 {
+ link-name = "WCD-Capture";
+ cpu {
+ sound-dai = <&lpass MI2S_TERTIARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
+ };
+ };
+ };
spmi@200f000 {
pm8916@0 {
@@ -650,9 +651,9 @@
};
&wcd_codec {
- status = "okay";
- clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
- clock-names = "mclk";
+ status = "okay";
+ clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
+ clock-names = "mclk";
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
@@ -778,135 +779,120 @@
};
};
+/*
+ * 2mA drive strength is not enough when connecting multiple
+ * I2C devices with different pull up resistors.
+ */
+&i2c2_default {
+ drive-strength = <16>;
+};
+
+&i2c4_default {
+ drive-strength = <16>;
+};
+
+&i2c6_default {
+ drive-strength = <16>;
+};
+
&msmgpio {
msmgpio_leds: msmgpio-leds {
- pinconf {
- pins = "gpio21", "gpio120";
- function = "gpio";
- output-low;
- };
+ pins = "gpio21", "gpio120";
+ function = "gpio";
+
+ output-low;
};
usb_id_default: usb-id-default {
- pinmux {
- function = "gpio";
- pins = "gpio121";
- };
+ pins = "gpio121";
+ function = "gpio";
- pinconf {
- pins = "gpio121";
- drive-strength = <8>;
- input-enable;
- bias-pull-up;
- };
+ drive-strength = <8>;
+ input-enable;
+ bias-pull-up;
};
adv7533_int_active: adv533-int-active {
- pinmux {
- function = "gpio";
- pins = "gpio31";
- };
- pinconf {
- pins = "gpio31";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio31";
+ function = "gpio";
+
+ drive-strength = <16>;
+ bias-disable;
};
adv7533_int_suspend: adv7533-int-suspend {
- pinmux {
- function = "gpio";
- pins = "gpio31";
- };
- pinconf {
- pins = "gpio31";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio31";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
adv7533_switch_active: adv7533-switch-active {
- pinmux {
- function = "gpio";
- pins = "gpio32";
- };
- pinconf {
- pins = "gpio32";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio32";
+ function = "gpio";
+
+ drive-strength = <16>;
+ bias-disable;
};
adv7533_switch_suspend: adv7533-switch-suspend {
- pinmux {
- function = "gpio";
- pins = "gpio32";
- };
- pinconf {
- pins = "gpio32";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio32";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
msm_key_volp_n_default: msm-key-volp-n-default {
- pinmux {
- function = "gpio";
- pins = "gpio107";
- };
- pinconf {
- pins = "gpio107";
- drive-strength = <8>;
- input-enable;
- bias-pull-up;
- };
+ pins = "gpio107";
+ function = "gpio";
+
+ drive-strength = <8>;
+ input-enable;
+ bias-pull-up;
};
};
&pm8916_gpios {
usb_hub_reset_pm: usb-hub-reset-pm {
- pinconf {
- pins = "gpio3";
- function = PMIC_GPIO_FUNC_NORMAL;
- input-disable;
- output-high;
- };
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+
+ input-disable;
+ output-high;
};
usb_hub_reset_pm_device: usb-hub-reset-pm-device {
- pinconf {
- pins = "gpio3";
- function = PMIC_GPIO_FUNC_NORMAL;
- output-low;
- };
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+
+ output-low;
};
usb_sw_sel_pm: usb-sw-sel-pm {
- pinconf {
- pins = "gpio4";
- function = PMIC_GPIO_FUNC_NORMAL;
- power-source = <PM8916_GPIO_VPH>;
- input-disable;
- output-high;
- };
+ pins = "gpio4";
+ function = PMIC_GPIO_FUNC_NORMAL;
+
+ power-source = <PM8916_GPIO_VPH>;
+ input-disable;
+ output-high;
};
usb_sw_sel_pm_device: usb-sw-sel-pm-device {
- pinconf {
- pins = "gpio4";
- function = PMIC_GPIO_FUNC_NORMAL;
- power-source = <PM8916_GPIO_VPH>;
- input-disable;
- output-low;
- };
+ pins = "gpio4";
+ function = PMIC_GPIO_FUNC_NORMAL;
+
+ power-source = <PM8916_GPIO_VPH>;
+ input-disable;
+ output-low;
};
pm8916_gpios_leds: pm8916-gpios-leds {
- pinconf {
- pins = "gpio1", "gpio2";
- function = PMIC_GPIO_FUNC_NORMAL;
- output-low;
- };
+ pins = "gpio1", "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+
+ output-low;
};
};
@@ -915,19 +901,17 @@
pinctrl-0 = <&ls_exp_gpio_f>;
ls_exp_gpio_f: pm8916-mpp4 {
- pinconf {
- pins = "mpp4";
- function = "digital";
- output-low;
- power-source = <PM8916_MPP_L5>; // 1.8V
- };
+ pins = "mpp4";
+ function = "digital";
+
+ output-low;
+ power-source = <PM8916_MPP_L5>; // 1.8V
};
pm8916_mpps_leds: pm8916-mpps-leds {
- pinconf {
- pins = "mpp2", "mpp3";
- function = "digital";
- output-low;
- };
+ pins = "mpp2", "mpp3";
+ function = "digital";
+
+ output-low;
};
};
diff --git a/dts/src/arm64/qcom/ipq8074-hk01.dts b/dts/src/arm64/qcom/ipq8074-hk01.dts
index 6754cb0638..f4a76162ab 100644
--- a/dts/src/arm64/qcom/ipq8074-hk01.dts
+++ b/dts/src/arm64/qcom/ipq8074-hk01.dts
@@ -82,3 +82,31 @@
nand-bus-width = <8>;
};
};
+
+&sdhc_1 {
+ status = "ok";
+};
+
+&qusb_phy_0 {
+ status = "ok";
+};
+
+&qusb_phy_1 {
+ status = "ok";
+};
+
+&ssphy_0 {
+ status = "ok";
+};
+
+&ssphy_1 {
+ status = "ok";
+};
+
+&usb_0 {
+ status = "ok";
+};
+
+&usb_1 {
+ status = "ok";
+};
diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi
index 5303821300..96a5ec89b5 100644
--- a/dts/src/arm64/qcom/ipq8074.dtsi
+++ b/dts/src/arm64/qcom/ipq8074.dtsi
@@ -82,6 +82,91 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
+ ssphy_1: phy@58000 {
+ compatible = "qcom,ipq8074-qmp-usb3-phy";
+ reg = <0x00058000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB1_AUX_CLK>,
+ <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB1_PHY_BCR>,
+ <&gcc GCC_USB3PHY_1_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb1_ssphy: lane@58200 {
+ reg = <0x00058200 0x130>, /* Tx */
+ <0x00058400 0x200>, /* Rx */
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc*/
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB1_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb1_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_1: phy@59000 {
+ compatible = "qcom,ipq8074-qusb2-phy";
+ reg = <0x00059000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@78000 {
+ compatible = "qcom,ipq8074-qmp-usb3-phy";
+ reg = <0x00078000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: lane@78200 {
+ reg = <0x00078200 0x130>, /* Tx */
+ <0x00078400 0x200>, /* Rx */
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc*/
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: phy@79000 {
+ compatible = "qcom,ipq8074-qusb2-phy";
+ reg = <0x00079000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ };
+
pcie_phy0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>;
@@ -169,6 +254,28 @@
#reset-cells = <0x1>;
};
+ sdhc_1: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x500>, <0x7824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&xo>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>;
+ clock-names = "xo", "iface", "core";
+ max-frequency = <384000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+
+ status = "disabled";
+ };
+
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
@@ -294,6 +401,88 @@
status = "disabled";
};
+ usb_0: usb@8af8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "sys_noc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <19200000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
+ usb_1: usb@8cf8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x08cf8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
+ <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_SLEEP_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ clock-names = "sys_noc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
+ <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <19200000>;
+
+ resets = <&gcc GCC_USB1_BCR>;
+ status = "disabled";
+
+ dwc_1: dwc3@8c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8c00000 0xcd00>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_1>, <&usb1_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
diff --git a/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts b/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts
index d5230cb76e..9f2c8e94fd 100644
--- a/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts
+++ b/dts/src/arm64/qcom/msm8916-longcheer-l8150.dts
@@ -108,31 +108,6 @@
};
};
-&msmgpio {
- gpio_keys_default: gpio-keys-default {
- pinmux {
- function = "gpio";
- pins = "gpio107";
- };
- pinconf {
- pins = "gpio107";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- usb_vbus_default: usb-vbus-default {
- pinmux {
- function = "gpio";
- pins = "gpio62";
- };
- pinconf {
- pins = "gpio62";
- bias-pull-up;
- };
- };
-};
-
&spmi_bus {
pm8916@0 {
pon@800 {
@@ -258,3 +233,20 @@
regulator-max-microvolt = <2700000>;
};
};
+
+&msmgpio {
+ gpio_keys_default: gpio-keys-default {
+ pins = "gpio107";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ usb_vbus_default: usb-vbus-default {
+ pins = "gpio62";
+ function = "gpio";
+
+ bias-pull-up;
+ };
+};
diff --git a/dts/src/arm64/qcom/msm8916-pins.dtsi b/dts/src/arm64/qcom/msm8916-pins.dtsi
index e9c00367f7..4dc437f13f 100644
--- a/dts/src/arm64/qcom/msm8916-pins.dtsi
+++ b/dts/src/arm64/qcom/msm8916-pins.dtsi
@@ -6,74 +6,49 @@
&msmgpio {
blsp1_uart1_default: blsp1-uart1-default {
- pinmux {
- function = "blsp_uart1";
- // TX, RX, CTS_N, RTS_N
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- drive-strength = <16>;
- bias-disable;
- };
+ // TX, RX, CTS_N, RTS_N
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
+
+ drive-strength = <16>;
+ bias-disable;
};
blsp1_uart1_sleep: blsp1-uart1-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
blsp1_uart2_default: blsp1-uart2-default {
- pinmux {
- function = "blsp_uart2";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+
+ drive-strength = <16>;
+ bias-disable;
};
blsp1_uart2_sleep: blsp1-uart2-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi1_default: spi1-default {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio0", "gpio1", "gpio3";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio2";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio3";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio2";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -81,33 +56,24 @@
};
spi1_sleep: spi1-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi2_default: spi2-default {
- pinmux {
- function = "blsp_spi2";
- pins = "gpio4", "gpio5", "gpio7";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio6";
- };
- pinconf {
- pins = "gpio4", "gpio5", "gpio7";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio4", "gpio5", "gpio7";
+ function = "blsp_spi2";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio6";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -115,33 +81,24 @@
};
spi2_sleep: spi2-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi3_default: spi3-default {
- pinmux {
- function = "blsp_spi3";
- pins = "gpio8", "gpio9", "gpio11";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio10";
- };
- pinconf {
- pins = "gpio8", "gpio9", "gpio11";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio10";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -149,33 +106,24 @@
};
spi3_sleep: spi3-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- };
- pinconf {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi4_default: spi4-default {
- pinmux {
- function = "blsp_spi4";
- pins = "gpio12", "gpio13", "gpio15";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio14";
- };
- pinconf {
- pins = "gpio12", "gpio13", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio12", "gpio13", "gpio15";
+ function = "blsp_spi4";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio14";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -183,33 +131,24 @@
};
spi4_sleep: spi4-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio12", "gpio13", "gpio14", "gpio15";
- };
- pinconf {
- pins = "gpio12", "gpio13", "gpio14", "gpio15";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi5_default: spi5-default {
- pinmux {
- function = "blsp_spi5";
- pins = "gpio16", "gpio17", "gpio19";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio18";
- };
- pinconf {
- pins = "gpio16", "gpio17", "gpio19";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio18";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -217,33 +156,24 @@
};
spi5_sleep: spi5-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio16", "gpio17", "gpio18", "gpio19";
- };
- pinconf {
- pins = "gpio16", "gpio17", "gpio18", "gpio19";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
spi6_default: spi6-default {
- pinmux {
- function = "blsp_spi6";
- pins = "gpio20", "gpio21", "gpio23";
- };
- pinmux-cs {
- function = "gpio";
- pins = "gpio22";
- };
- pinconf {
- pins = "gpio20", "gpio21", "gpio23";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf-cs {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+
+ drive-strength = <12>;
+ bias-disable;
+
+ cs {
pins = "gpio22";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
output-high;
@@ -251,466 +181,315 @@
};
spi6_sleep: spi6-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio20", "gpio21", "gpio22", "gpio23";
- };
- pinconf {
- pins = "gpio20", "gpio21", "gpio22", "gpio23";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
i2c1_default: i2c1-default {
- pinmux {
- function = "blsp_i2c1";
- pins = "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio2", "gpio3";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c1_sleep: i2c1-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio2", "gpio3";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio2", "gpio3";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c2_default: i2c2-default {
- pinmux {
- function = "blsp_i2c2";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c2_sleep: i2c2-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c4_default: i2c4-default {
- pinmux {
- function = "blsp_i2c4";
- pins = "gpio14", "gpio15";
- };
- pinconf {
- pins = "gpio14", "gpio15";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c4_sleep: i2c4-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio14", "gpio15";
- };
- pinconf {
- pins = "gpio14", "gpio15";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c5_default: i2c5-default {
- pinmux {
- function = "blsp_i2c5";
- pins = "gpio18", "gpio19";
- };
- pinconf {
- pins = "gpio18", "gpio19";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c5_sleep: i2c5-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio18", "gpio19";
- };
- pinconf {
- pins = "gpio18", "gpio19";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c6_default: i2c6-default {
- pinmux {
- function = "blsp_i2c6";
- pins = "gpio22", "gpio23";
- };
- pinconf {
- pins = "gpio22", "gpio23";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+
+ drive-strength = <2>;
+ bias-disable;
};
i2c6_sleep: i2c6-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio22", "gpio23";
- };
- pinconf {
- pins = "gpio22", "gpio23";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
pmx-sdc1-clk {
sdc1_clk_on: clk-on {
- pinmux {
- pins = "sdc1_clk";
- };
- pinconf {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
+ pins = "sdc1_clk";
+
+ bias-disable;
+ drive-strength = <16>;
};
sdc1_clk_off: clk-off {
- pinmux {
- pins = "sdc1_clk";
- };
- pinconf {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
+ pins = "sdc1_clk";
+
+ bias-disable;
+ drive-strength = <2>;
};
};
pmx-sdc1-cmd {
sdc1_cmd_on: cmd-on {
- pinmux {
- pins = "sdc1_cmd";
- };
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
+ pins = "sdc1_cmd";
+
+ bias-pull-up;
+ drive-strength = <10>;
};
sdc1_cmd_off: cmd-off {
- pinmux {
- pins = "sdc1_cmd";
- };
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
+ pins = "sdc1_cmd";
+
+ bias-pull-up;
+ drive-strength = <2>;
};
};
pmx-sdc1-data {
sdc1_data_on: data-on {
- pinmux {
- pins = "sdc1_data";
- };
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
+ pins = "sdc1_data";
+
+ bias-pull-up;
+ drive-strength = <10>;
};
sdc1_data_off: data-off {
- pinmux {
- pins = "sdc1_data";
- };
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
+ pins = "sdc1_data";
+
+ bias-pull-up;
+ drive-strength = <2>;
};
};
pmx-sdc2-clk {
sdc2_clk_on: clk-on {
- pinmux {
- pins = "sdc2_clk";
- };
- pinconf {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
+ pins = "sdc2_clk";
+
+ bias-disable;
+ drive-strength = <16>;
};
sdc2_clk_off: clk-off {
- pinmux {
- pins = "sdc2_clk";
- };
- pinconf {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
+ pins = "sdc2_clk";
+
+ bias-disable;
+ drive-strength = <2>;
};
};
pmx-sdc2-cmd {
sdc2_cmd_on: cmd-on {
- pinmux {
- pins = "sdc2_cmd";
- };
- pinconf {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
+ pins = "sdc2_cmd";
+
+ bias-pull-up;
+ drive-strength = <10>;
};
sdc2_cmd_off: cmd-off {
- pinmux {
- pins = "sdc2_cmd";
- };
- pinconf {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
+ pins = "sdc2_cmd";
+
+ bias-pull-up;
+ drive-strength = <2>;
};
};
pmx-sdc2-data {
sdc2_data_on: data-on {
- pinmux {
- pins = "sdc2_data";
- };
- pinconf {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
+ pins = "sdc2_data";
+
+ bias-pull-up;
+ drive-strength = <10>;
};
sdc2_data_off: data-off {
- pinmux {
- pins = "sdc2_data";
- };
- pinconf {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
+ pins = "sdc2_data";
+
+ bias-pull-up;
+ drive-strength = <2>;
};
};
pmx-sdc2-cd-pin {
sdc2_cd_on: cd-on {
- pinmux {
- function = "gpio";
- pins = "gpio38";
- };
- pinconf {
- pins = "gpio38";
- drive-strength = <2>;
- bias-pull-up;
- };
+ pins = "gpio38";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
};
sdc2_cd_off: cd-off {
- pinmux {
- function = "gpio";
- pins = "gpio38";
- };
- pinconf {
- pins = "gpio38";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio38";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
cdc-pdm-lines {
cdc_pdm_lines_act: pdm-lines-on {
- pinmux {
- function = "cdc_pdm0";
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- };
- pinconf {
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- drive-strength = <8>;
- bias-pull-none;
- };
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+
+ drive-strength = <8>;
+ bias-disable;
};
cdc_pdm_lines_sus: pdm-lines-off {
- pinmux {
- function = "cdc_pdm0";
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- };
- pinconf {
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
};
ext-pri-tlmm-lines {
ext_pri_tlmm_lines_act: ext-pa-on {
- pinmux {
- function = "pri_mi2s";
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- };
- pinconf {
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- drive-strength = <8>;
- bias-pull-none;
- };
- };
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
ext_pri_tlmm_lines_sus: ext-pa-off {
- pinmux {
- function = "pri_mi2s";
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- };
- pinconf {
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
ext-pri-ws-line {
ext_pri_ws_act: ext-pa-on {
- pinmux {
- function = "pri_mi2s_ws";
- pins = "gpio110";
- };
- pinconf {
- pins = "gpio110";
- drive-strength = <8>;
- bias-pull-none;
- };
- };
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <8>;
+ bias-disable;
+ };
ext_pri_ws_sus: ext-pa-off {
- pinmux {
- function = "pri_mi2s_ws";
- pins = "gpio110";
- };
- pinconf {
- pins = "gpio110";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
ext-mclk-tlmm-lines {
ext_mclk_tlmm_lines_act: mclk-lines-on {
- pinmux {
- function = "pri_mi2s";
- pins = "gpio116";
- };
- pinconf {
- pins = "gpio116";
- drive-strength = <8>;
- bias-pull-none;
- };
+ pins = "gpio116";
+ function = "pri_mi2s";
+
+ drive-strength = <8>;
+ bias-disable;
};
ext_mclk_tlmm_lines_sus: mclk-lines-off {
- pinmux {
- function = "pri_mi2s";
- pins = "gpio116";
- };
- pinconf {
- pins = "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio116";
+ function = "pri_mi2s";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
/* secondary Mi2S */
ext-sec-tlmm-lines {
ext_sec_tlmm_lines_act: tlmm-lines-on {
- pinmux {
- function = "sec_mi2s";
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- };
- pinconf {
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- drive-strength = <8>;
- bias-pull-none;
- };
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+
+ drive-strength = <8>;
+ bias-disable;
};
ext_sec_tlmm_lines_sus: tlmm-lines-off {
- pinmux {
- function = "sec_mi2s";
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- };
- pinconf {
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
cdc-dmic-lines {
cdc_dmic_lines_act: dmic-lines-on {
- pinmux-dmic0-clk {
- function = "dmic0_clk";
+ clk {
pins = "gpio0";
+ function = "dmic0_clk";
+
+ drive-strength = <8>;
};
- pinmux-dmic0-data {
- function = "dmic0_data";
+ data {
pins = "gpio1";
- };
- pinconf {
- pins = "gpio0", "gpio1";
+ function = "dmic0_data";
+
drive-strength = <8>;
};
};
cdc_dmic_lines_sus: dmic-lines-off {
- pinmux-dmic0-clk {
- function = "dmic0_clk";
+ clk {
pins = "gpio0";
+ function = "dmic0_clk";
+
+ drive-strength = <2>;
+ bias-disable;
};
- pinmux-dmic0-data {
- function = "dmic0_data";
+ data {
pins = "gpio1";
- };
- pinconf {
- pins = "gpio0", "gpio1";
+ function = "dmic0_data";
+
drive-strength = <2>;
bias-disable;
};
@@ -718,88 +497,64 @@
};
wcnss_pin_a: wcnss-active {
- pinmux {
- pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
- function = "wcss_wlan";
- };
- pinconf {
- pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <6>;
- bias-pull-up;
- };
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "wcss_wlan";
+
+ drive-strength = <6>;
+ bias-pull-up;
};
cci0_default: cci0-default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio29", "gpio30";
- };
- pinconf {
- pins = "gpio29", "gpio30";
- drive-strength = <16>;
- bias-disable;
- };
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+
+ drive-strength = <16>;
+ bias-disable;
};
camera_front_default: camera-front-default {
- pinmux-pwdn {
- function = "gpio";
- pins = "gpio33";
- };
- pinconf-pwdn {
+ pwdn {
pins = "gpio33";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
};
-
- pinmux-rst {
- function = "gpio";
- pins = "gpio28";
- };
- pinconf-rst {
+ rst {
pins = "gpio28";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
};
-
- pinmux-mclk1 {
- function = "cam_mclk1";
- pins = "gpio27";
- };
- pinconf-mclk1 {
+ mclk1 {
pins = "gpio27";
+ function = "cam_mclk1";
+
drive-strength = <16>;
bias-disable;
};
};
camera_rear_default: camera-rear-default {
- pinmux-pwdn {
- function = "gpio";
- pins = "gpio34";
- };
- pinconf-pwdn {
+ pwdn {
pins = "gpio34";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
};
-
- pinmux-rst {
- function = "gpio";
- pins = "gpio35";
- };
- pinconf-rst {
+ rst {
pins = "gpio35";
+ function = "gpio";
+
drive-strength = <16>;
bias-disable;
};
-
- pinmux-mclk0 {
- function = "cam_mclk0";
- pins = "gpio26";
- };
- pinconf-mclk0 {
+ mclk0 {
pins = "gpio26";
+ function = "cam_mclk0";
+
drive-strength = <16>;
bias-disable;
};
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
index ea52adf07a..a0c00d9d62 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
@@ -167,77 +167,33 @@
};
};
-&msmgpio {
- gpio_keys_default: gpio-keys-default {
- pinmux {
- function = "gpio";
- pins = "gpio107", "gpio109";
- };
- pinconf {
- pins = "gpio107", "gpio109";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
+&blsp_i2c2 {
+ status = "okay";
- gpio_hall_sensor_default: gpio-hall-sensor-default {
- pinmux {
- function = "gpio";
- pins = "gpio52";
- };
- pinconf {
- pins = "gpio52";
- drive-strength = <2>;
- bias-disable;
- };
- };
+ accelerometer: accelerometer@10 {
+ compatible = "bosch,bmc150_accel";
+ reg = <0x10>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <115 IRQ_TYPE_EDGE_RISING>;
- muic_int_default: muic-int-default {
- pinmux {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- };
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_int_default>;
};
- tsp_en_default: tsp-en-default {
- pinmux {
- function = "gpio";
- pins = "gpio73";
- };
- pinconf {
- pins = "gpio73";
- drive-strength = <2>;
- bias-disable;
- };
+ magnetometer@12 {
+ compatible = "bosch,bmc150_magn";
+ reg = <0x12>;
};
+};
- pmx-mdss {
- mdss_default: mdss-default {
- pinmux {
- function = "gpio";
- pins = "gpio25";
- };
- pinconf {
- pins = "gpio25";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
- mdss_sleep: mdss-sleep {
- pinmux {
- function = "gpio";
- pins = "gpio25";
- };
- pinconf {
- pins = "gpio25";
- drive-strength = <2>;
- bias-pull-down;
+&spmi_bus {
+ pm8916@0 {
+ pon@800 {
+ volume-down {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
};
};
};
@@ -356,15 +312,61 @@
};
};
-&spmi_bus {
- pm8916@0 {
- pon@800 {
- volume-down {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&msmgpio {
+ accel_int_default: accel-int-default {
+ pins = "gpio115";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default {
+ pins = "gpio107", "gpio109";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ gpio_hall_sensor_default: gpio-hall-sensor-default {
+ pins = "gpio52";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mdss {
+ mdss_default: mdss-default {
+ pins = "gpio25";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-disable;
+ };
+ mdss_sleep: mdss-sleep {
+ pins = "gpio25";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
};
};
+
+ muic_int_default: muic-int-default {
+ pins = "gpio12";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en_default: tsp-en-default {
+ pins = "gpio73";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
};
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
index b46c872890..410c7d199f 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
+++ b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
@@ -22,6 +22,12 @@
};
};
+&accelerometer {
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+};
+
&dsi0 {
panel@0 {
reg = <0>;
@@ -51,14 +57,10 @@
&msmgpio {
panel_vdd3_default: panel-vdd3-default {
- pinmux {
- function = "gpio";
- pins = "gpio9";
- };
- pinconf {
- pins = "gpio9";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio9";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
index a555db8f6b..e39c04d977 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
+++ b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
@@ -9,6 +9,12 @@
compatible = "samsung,a5u-eur", "qcom,msm8916";
};
+&accelerometer {
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+};
+
&blsp_i2c5 {
status = "okay";
@@ -38,14 +44,10 @@
&msmgpio {
ts_int_default: ts-int-default {
- pinmux {
- function = "gpio";
- pins = "gpio13";
- };
- pinconf {
- pins = "gpio13";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio13";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi
index 32bd140ac9..67cae5f9e4 100644
--- a/dts/src/arm64/qcom/msm8916.dtsi
+++ b/dts/src/arm64/qcom/msm8916.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/arm/coresight-cti-dt.h>
+#include <dt-bindings/interconnect/qcom,msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
@@ -406,11 +407,38 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
+ bimc: interconnect@400000 {
+ compatible = "qcom,msm8916-bimc";
+ reg = <0x00400000 0x62000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
+ pcnoc: interconnect@500000 {
+ compatible = "qcom,msm8916-pcnoc";
+ reg = <0x00500000 0x11000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
+ <&rpmcc RPM_SMD_PCNOC_A_CLK>;
+ };
+
+ snoc: interconnect@580000 {
+ compatible = "qcom,msm8916-snoc";
+ reg = <0x00580000 0x14000>;
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+
msmgpio: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x300000>;
@@ -700,6 +728,9 @@
interrupt-names = "lpass-irq-lpaif";
reg = <0x07708000 0x10000>;
reg-names = "lpass-lpaif";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
lpass_codec: codec{
diff --git a/dts/src/arm64/qcom/msm8992-bullhead-rev-101.dts b/dts/src/arm64/qcom/msm8992-bullhead-rev-101.dts
index 32670d5afd..5969b5cfdc 100644
--- a/dts/src/arm64/qcom/msm8992-bullhead-rev-101.dts
+++ b/dts/src/arm64/qcom/msm8992-bullhead-rev-101.dts
@@ -11,6 +11,7 @@
model = "LG Nexus 5X";
compatible = "lg,bullhead", "qcom,msm8992";
/* required for bootloader to select correct board */
+ qcom,msm-id = <251 0>, <252 0>;
qcom,board-id = <0xb64 0>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
@@ -22,15 +23,6 @@
stdout-path = "serial0:115200n8";
};
- soc {
- serial@f991e000 {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart2_default>;
- pinctrl-1 = <&blsp1_uart2_sleep>;
- };
- };
-
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -47,4 +39,237 @@
};
};
-#include "msm8994-smd-rpm.dtsi"
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_l1-supply = <&pm8994_s1>;
+ vdd_l2_26_28-supply = <&pm8994_s3>;
+ vdd_l3_11-supply = <&pm8994_s3>;
+ vdd_l4_27_31-supply = <&pm8994_s3>;
+ vdd_l5_7-supply = <&pm8994_s3>;
+ vdd_l6_12_32-supply = <&pm8994_s5>;
+ vdd_l8_16_30-supply = <&vreg_vph_pwr>;
+ vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
+ vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
+ vdd_l14_15-supply = <&pm8994_s5>;
+ vdd_l17_29-supply = <&vreg_vph_pwr>;
+ vdd_l20_21-supply = <&vreg_vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+ vdd_lvs1_2 = <&pm8994_s4>;
+
+ pm8994_s1: s1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ pm8994_s2: s2 {
+ /* TODO */
+ };
+
+ pm8994_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8994_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-system-load = <325000>;
+ };
+
+ pm8994_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pm8994_s7: s7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l1: l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l2: l2 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+
+ pm8994_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8994_l5: l5 {
+ /* TODO */
+ };
+
+ pm8994_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l7: l7 {
+ /* TODO */
+ };
+
+ pm8994_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l11: l11 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8994_l14: l14 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l18: l18 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8994_l19: l19 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+ regulator-system-load = <570000>;
+ };
+
+ pm8994_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8994_l22: l22 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ pm8994_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3150000>;
+ };
+
+ pm8994_l25: l25 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l26: l26 {
+ /* TODO: value from downstream
+ regulator-min-microvolt = <987500>;
+ fails to apply */
+ };
+
+ pm8994_l27: l27 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8994_l28: l28 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l29: l29 {
+ /* TODO: Unsupported voltage range.
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <2800000>;
+ */
+ };
+
+ pm8994_l30: l30 {
+ /* TODO: get this verified
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ */
+ };
+
+ pm8994_l31: l31 {
+ regulator-min-microvolt = <1262500>;
+ regulator-max-microvolt = <1262500>;
+ };
+
+ pm8994_l32: l32 {
+ /* TODO: get this verified
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ */
+ };
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs400-1_8v;
+};
diff --git a/dts/src/arm64/qcom/msm8992-msft-lumia-talkman.dts b/dts/src/arm64/qcom/msm8992-msft-lumia-talkman.dts
new file mode 100644
index 0000000000..3cc01f0221
--- /dev/null
+++ b/dts/src/arm64/qcom/msm8992-msft-lumia-talkman.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "msm8992.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ model = "Microsoft Lumia 950";
+ compatible = "microsoft,talkman", "qcom,msm8992";
+
+ /* Most Lumia 950 users use GRUB to load their kernels,
+ * hence there is no need for msm-id and friends.
+ */
+
+ /* This enables graphical output via bootloader-enabled display.
+ * acpi=no is required due to WP platforms having ACPI support, but
+ * only for Windows-based OSes.
+ */
+ chosen {
+ bootargs = "earlycon=efifb console=efifb acpi=no";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs200-1_8v;
+};
diff --git a/dts/src/arm64/qcom/msm8992-pins.dtsi b/dts/src/arm64/qcom/msm8992-pins.dtsi
deleted file mode 100644
index c543c718c2..0000000000
--- a/dts/src/arm64/qcom/msm8992-pins.dtsi
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
- blsp1_uart2_default: blsp1_uart2_default {
- pinmux {
- function = "blsp_uart2";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp1_uart2_sleep: blsp1_uart2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- /* 0-3 for sdc1 4-6 for sdc2 */
- /* Order of pins */
- /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
- /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */
- sdc1_clk_on: clk-on {
- pinconf {
- pins = "sdc1_clk";
- bias-disable = <0>; /* No pull */
- drive-strength = <16>; /* 16mA */
- };
- };
-
- sdc1_clk_off: clk-off {
- pinconf {
- pins = "sdc1_clk";
- bias-disable = <0>; /* No pull */
- drive-strength = <2>; /* 2mA */
- };
- };
-
- sdc1_cmd_on: cmd-on {
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <8>;
- };
- };
-
- sdc1_cmd_off: cmd-off {
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up = <0x3>; /* same as 3.10 ?? */
- drive-strength = <2>; /* 2mA */
- };
- };
-
- sdc1_data_on: data-on {
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <8>; /* 8mA */
- };
- };
-
- sdc1_data_off: data-off {
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- sdc1_rclk_on: rclk-on {
- bias-pull-down; /* pull down */
- };
-
- sdc1_rclk_off: rclk-off {
- bias-pull-down; /* pull down */
- };
-};
diff --git a/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts b/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts
new file mode 100644
index 0000000000..4f64ca3ea1
--- /dev/null
+++ b/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "msm8992.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ model = "Xiaomi Mi 4C";
+ compatible = "xiaomi,libra", "qcom,msm8992";
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <251 0 252 0>;
+ qcom,pmic-id = <65545 65546 0 0>;
+ qcom,board-id = <12 0>;
+
+ /* This enables graphical output via bootloader-enabled display */
+ chosen {
+ bootargs = "earlycon=tty0 console=tty0";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer0: framebuffer@3404000 {
+ status= "okay";
+ compatible = "simple-framebuffer";
+ reg = <0 0x3404000 0 (1080 * 1920 * 3)>;
+ width = <1080>;
+ height = <1920>;
+ stride = <(1080 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ button@0 {
+ label = "Volume Up";
+ gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* This is for getting crash logs using Android downstream kernels */
+ ramoops@dfc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xdfc00000 0x0 0x40000>;
+ console-size = <0x10000>;
+ record-size = <0x10000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ };
+
+ continuous_splash: framebuffer@3401000{
+ reg = <0x0 0x3401000 0x0 0x2200000>;
+ no-map;
+ };
+
+ dfps_data_mem: dfps_data_mem@3400000 {
+ reg = <0x0 0x3400000 0x0 0x1000>;
+ no-map;
+ };
+
+ peripheral_region: peripheral_region@7400000 {
+ reg = <0x0 0x7400000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ modem_region: modem_region@9000000 {
+ reg = <0x0 0x9000000 0x0 0x5a00000>;
+ no-map;
+ };
+
+ tzapp: modem_region@ea00000 {
+ reg = <0x0 0xea00000 0x0 0x1900000>;
+ no-map;
+ };
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ /* Atmel or Synaptics touchscreen */
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ /* Silabs si4705 FM transmitter */
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ /* NCI NFC,
+ * TI USB320 Type-C controller,
+ * Pericom 30216a USB (de)mux switch
+ */
+};
+
+&blsp_i2c7 {
+ status = "okay";
+
+ /* cm36686 proximity and ambient light sensor */
+};
+
+&blsp_i2c13 {
+ status = "okay";
+
+ /* ST lsm6db0 gyro/accelerometer */
+};
+
+&blsp2_uart2 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_l1-supply = <&pm8994_s7>;
+ vdd_l2_26_28-supply = <&pm8994_s3>;
+ vdd_l3_11-supply = <&pm8994_s3>;
+ vdd_l4_27_31-supply = <&pm8994_s3>;
+ vdd_l5_7-supply = <&pm8994_s3>;
+ vdd_l6_12_32-supply = <&pm8994_s5>;
+ vdd_l8_16_30-supply = <&vreg_vph_pwr>;
+ vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
+ vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
+ vdd_l14_15-supply = <&pm8994_s5>;
+ vdd_l17_29-supply = <&vreg_vph_pwr>;
+ vdd_l20_21-supply = <&vreg_vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+ vdd_lvs1_2 = <&pm8994_s4>;
+
+ pm8994_s1: s1 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_s2: s2 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8994_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ regulator-system-load = <325000>;
+ };
+
+ pm8994_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pm8994_s7: s7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l1: l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l2: l2 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+
+ pm8994_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8994_l5: l5 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l7: l7 {
+ /* unused */
+ status = "disabled";
+ };
+
+ pm8994_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l11: l11 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8994_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8994_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8994_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ pm8994_l19: l19 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+ regulator-system-load = <570000>;
+ };
+
+ pm8994_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ };
+
+ pm8994_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8994_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3150000>;
+ };
+
+ pm8994_l25: l25 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l26: l26 {
+ regulator-min-microvolt = <987500>;
+ regulator-max-microvolt = <987500>;
+
+ };
+
+ pm8994_l27: l27 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8994_l28: l28 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8994_l29: l29 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8994_l30: l30 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8994_l31: l31 {
+ regulator-min-microvolt = <1262500>;
+ regulator-max-microvolt = <1262500>;
+ };
+
+ pm8994_l32: l32 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ mmc-hs400-1_8v;
+ vmmc-supply = <&pm8994_l20>;
+ vqmmc-supply = <&pm8994_s4>;
+};
diff --git a/dts/src/arm64/qcom/msm8992.dtsi b/dts/src/arm64/qcom/msm8992.dtsi
index 2021795c99..188fff2095 100644
--- a/dts/src/arm64/qcom/msm8992.dtsi
+++ b/dts/src/arm64/qcom/msm8992.dtsi
@@ -6,10 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
- model = "Qualcomm Technologies, Inc. MSM 8992";
- compatible = "qcom,msm8992";
- // msm-id needed by bootloader for selecting correct blob
- qcom,msm-id = <251 0>, <252 0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
@@ -20,55 +16,139 @@
cpus {
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- };
- };
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
+ enable-method = "psci";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ next-level-cache = <&L2_1>;
+ enable-method = "psci";
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ next-level-cache = <&L2_1>;
+ enable-method = "psci";
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+ };
+ };
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8994", "qcom,scm";
+ };
};
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
};
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
};
- vreg_vph_pwr: vreg-vph-pwr {
- compatible = "regulator-fixed";
- status = "okay";
- regulator-name = "vph-pwr";
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "hvc";
+ };
- regulator-min-microvolt = <3600000>;
- regulator-max-microvolt = <3600000>;
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- regulator-always-on;
+ smem_region: smem@6a00000 {
+ reg = <0x0 0x6a00000 0x0 0x200000>;
+ no-map;
+ };
};
sfpb_mutex: hwmutex {
@@ -98,9 +178,10 @@
<0xf9002000 0x1000>;
};
- apcs: syscon@f900d000 {
- compatible = "syscon";
+ apcs: mailbox@f900d000 {
+ compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0xf900d000 0x2000>;
+ #mbox-cells = <1>;
};
timer@f9020000 {
@@ -161,63 +242,147 @@
};
};
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
- };
+ sdhc_1: sdhci@f9824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
- msmgpio: pinctrl@fd510000 {
- compatible = "qcom,msm8994-pinctrl";
- reg = <0xfd510000 0x4000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&msmgpio 0 0 146>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ regulator-always-on;
+ bus-width = <8>;
+ non-removable;
+
+ status = "disabled";
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
- status = "disabled";
clock-names = "core", "iface";
- clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ status = "disabled";
};
- clock_gcc: clock-controller@fc400000 {
- compatible = "qcom,gcc-msm8994";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0xfc400000 0x2000>;
+ blsp_i2c2: i2c@f9924000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9924000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_default>;
+ pinctrl-1 = <&i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- sdhci1: mmc@f9824900 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ /* Somebody was very creative with their numbering scheme downstream... */
- interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
- <GIC_SPI 138 IRQ_TYPE_NONE>;
- interrupt-names = "hc_irq", "pwr_irq";
+ blsp_i2c13: i2c@f9927000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9927000 0x500>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c13_default>;
+ pinctrl-1 = <&i2c13_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c6: i2c@f9928000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9928000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c6_default>;
+ pinctrl-1 = <&i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
- <&clock_gcc GCC_SDCC1_AHB_CLK>;
+ blsp2_uart2: serial@f995e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf995e000 0x1000>;
+ interrupt = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_default>;
+ pinctrl-1 = <&blsp2_uart2_sleep>;
+ status = "disabled";
+ };
+ blsp_i2c7: i2c@f9963000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9963000 0x500>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
- &sdc1_rclk_on>;
- pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
- &sdc1_rclk_off>;
+ pinctrl-0 = <&i2c7_default>;
+ pinctrl-1 = <&i2c7_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- regulator-always-on;
- bus-width = <8>;
- mmc-hs400-1_8v;
- status = "okay";
+ blsp_i2c5: i2c@f9967000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9967000 0x500>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gcc: clock-controller@fc400000 {
+ compatible = "qcom,gcc-msm8994";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x2000>;
};
rpm_msg_ram: memory@fc428000 {
@@ -225,27 +390,189 @@
reg = <0xfc428000 0x4000>;
};
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
+ spmi_bus: spmi@fc4c0000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ reg-names = "core", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
sfpb_mutex_regs: syscon@fd484000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "syscon";
reg = <0xfd484000 0x400>;
};
- };
- memory {
- device_type = "memory";
- reg = <0 0 0 0>; // bootloader will update
- };
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,msm8994-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 146>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ blsp1_uart2_default: blsp1-uart2-default {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
- smem_region: smem@6a00000 {
- reg = <0x0 0x6a00000 0x0 0x200000>;
- no-map;
+ blsp1_uart2_sleep: blsp1-uart2-sleep {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart2_default: blsp2-uart2-default {
+ function = "blsp_uart8";
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart2_sleep: blsp2-uart2-sleep {
+ function = "gpio";
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sdc1_clk_on: clk-on {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ sdc1_clk_off: clk-off {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ sdc1_cmd_on: cmd-on {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ sdc1_cmd_off: cmd-off {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_data_on: data-on {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ sdc1_data_off: data-off {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_rclk_on: rclk-on {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ sdc1_rclk_off: rclk-off {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ i2c2_default: i2c2-default {
+ function = "blsp_i2c2";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_sleep: i2c2-sleep {
+ function = "gpio";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_default: i2c5-default {
+ /* Don't be fooled! Nobody knows the reason why though... */
+ function = "blsp_i2c11";
+ pins = "gpio83", "gpio84";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_sleep: i2c5-sleep {
+ function = "gpio";
+ pins = "gpio83", "gpio84";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_default: i2c6-default {
+ function = "blsp_i2c6";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_sleep: i2c6-sleep {
+ function = "gpio";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c7_default: i2c7-default {
+ function = "blsp_i2c7";
+ pins = "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c7_sleep: i2c7-sleep {
+ function = "gpio";
+ pins = "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c13_default: i2c13-default {
+ /* Not a typo either. */
+ function = "blsp_i2c5";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c13_sleep: i2c13-sleep {
+ function = "gpio";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
};
@@ -258,58 +585,35 @@
qcom,local-pid = <0>;
qcom,remote-pid = <6>;
- rpm-requests {
+ rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
- pm8994-regulators {
- compatible = "qcom,rpm-pm8994-regulators";
-
- pm8994_s1: s1 {};
- pm8994_s2: s2 {};
- pm8994_s3: s3 {};
- pm8994_s4: s4 {};
- pm8994_s5: s5 {};
- pm8994_s6: s6 {};
- pm8994_s7: s7 {};
-
- pm8994_l1: l1 {};
- pm8994_l2: l2 {};
- pm8994_l3: l3 {};
- pm8994_l4: l4 {};
- pm8994_l6: l6 {};
- pm8994_l8: l8 {};
- pm8994_l9: l9 {};
- pm8994_l10: l10 {};
- pm8994_l11: l11 {};
- pm8994_l12: l12 {};
- pm8994_l13: l13 {};
- pm8994_l14: l14 {};
- pm8994_l15: l15 {};
- pm8994_l16: l16 {};
- pm8994_l17: l17 {};
- pm8994_l18: l18 {};
- pm8994_l19: l19 {};
- pm8994_l20: l20 {};
- pm8994_l21: l21 {};
- pm8994_l22: l22 {};
- pm8994_l23: l23 {};
- pm8994_l24: l24 {};
- pm8994_l25: l25 {};
- pm8994_l26: l26 {};
- pm8994_l27: l27 {};
- pm8994_l28: l28 {};
- pm8994_l29: l29 {};
- pm8994_l30: l30 {};
- pm8994_l31: l31 {};
- pm8994_l32: l32 {};
-
- pm8994_lvs1: lvs1 {};
- pm8994_lvs2: lvs2 {};
+ rpmcc: rpmcc {
+ compatible = "qcom,rpmcc-msm8992";
+ #clock-cells = <1>;
};
};
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ status = "okay";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
-#include "msm8992-pins.dtsi"
diff --git a/dts/src/arm64/qcom/msm8994-angler-rev-101.dts b/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
index a5f9a6ab51..baa55643b4 100644
--- a/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
+++ b/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
@@ -11,6 +11,8 @@
model = "Huawei Nexus 6P";
compatible = "huawei,angler", "qcom,msm8994";
/* required for bootloader to select correct board */
+ qcom,msm-id = <207 0x20000>;
+ qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
qcom,board-id = <8026 0>;
aliases {
diff --git a/dts/src/arm64/qcom/msm8994-pins.dtsi b/dts/src/arm64/qcom/msm8994-pins.dtsi
deleted file mode 100644
index 2e118d967f..0000000000
--- a/dts/src/arm64/qcom/msm8994-pins.dtsi
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
- blsp1_uart2_default: blsp1_uart2_default {
- pinmux {
- function = "blsp_uart2";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp1_uart2_sleep: blsp1_uart2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-};
diff --git a/dts/src/arm64/qcom/msm8994-smd-rpm.dtsi b/dts/src/arm64/qcom/msm8994-smd-rpm.dtsi
deleted file mode 100644
index 31e3eb6ab5..0000000000
--- a/dts/src/arm64/qcom/msm8994-smd-rpm.dtsi
+++ /dev/null
@@ -1,268 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015, LGE Inc. All rights reserved.
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
- */
-
-&smd_rpm {
- rpm {
- rpm_requests {
- pm8994-regulators {
-
- vdd_l1-supply = <&pm8994_s1>;
- vdd_l2_26_28-supply = <&pm8994_s3>;
- vdd_l3_11-supply = <&pm8994_s3>;
- vdd_l4_27_31-supply = <&pm8994_s3>;
- vdd_l5_7-supply = <&pm8994_s3>;
- vdd_l6_12_32-supply = <&pm8994_s5>;
- vdd_l8_16_30-supply = <&vreg_vph_pwr>;
- vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
- vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
- vdd_l14_15-supply = <&pm8994_s5>;
- vdd_l17_29-supply = <&vreg_vph_pwr>;
- vdd_l20_21-supply = <&vreg_vph_pwr>;
- vdd_l25-supply = <&pm8994_s5>;
- vdd_lvs1_2 = <&pm8994_s4>;
-
- s1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- };
-
- s2 {
- /* TODO */
- };
-
- s3 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-allow-set-load;
- regulator-system-load = <325000>;
- };
-
- s5 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- };
-
- s7 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- l1 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- l2 {
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- };
-
- l3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- /* TODO */
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l7 {
- /* TODO */
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- };
-
- l11 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- qcom,init-voltage = <1200000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- proxy-supply = <&pm8994_l12>;
- qcom,proxy-consumer-enable;
- qcom,proxy-consumer-current = <10000>;
- status = "okay";
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- qcom,init-voltage = <2950000>;
- status = "okay";
- };
-
- l14 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- qcom,init-voltage = <1200000>;
- proxy-supply = <&pm8994_l14>;
- qcom,proxy-consumer-enable;
- qcom,proxy-consumer-current = <10000>;
- status = "okay";
- };
-
- l15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- status = "okay";
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- qcom,init-voltage = <2700000>;
- status = "okay";
- };
-
- l17 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- qcom,init-voltage = <2700000>;
- status = "okay";
- };
-
- l18 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- qcom,init-voltage = <3000000>;
- qcom,init-ldo-mode = <1>;
- };
-
- l19 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- status = "okay";
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-allow-set-load;
- regulator-system-load = <570000>;
- };
-
- l21 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- qcom,init-voltage = <1800000>;
- };
-
- l22 {
- regulator-min-microvolt = <3100000>;
- regulator-max-microvolt = <3100000>;
- qcom,init-voltage = <3100000>;
- };
-
- l23 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- qcom,init-voltage = <2800000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3150000>;
- qcom,init-voltage = <3075000>;
- };
-
- l25 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- };
-
- l26 {
- /* TODO: value from downstream
- regulator-min-microvolt = <987500>;
- fails to apply */
- };
-
- l27 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- qcom,init-voltage = <1050000>;
- };
-
- l28 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- qcom,init-voltage = <1000000>;
- proxy-supply = <&pm8994_l28>;
- qcom,proxy-consumer-enable;
- qcom,proxy-consumer-current = <10000>;
- };
-
- l29 {
- /* TODO: Unsupported voltage range.
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- qcom,init-voltage = <2800000>;
- */
- };
-
- l30 {
- /* TODO: get this verified
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- */
- };
-
- l31 {
- regulator-min-microvolt = <1262500>;
- regulator-max-microvolt = <1262500>;
- qcom,init-voltage = <1262500>;
- };
-
- l32 {
- /* TODO: get this verified
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- */
- };
- };
- };
- };
-};
diff --git a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts
new file mode 100644
index 0000000000..5d6bbbf6c1
--- /dev/null
+++ b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami-sumire.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "msm8994-sony-xperia-kitakami.dtsi"
+
+/ {
+ model = "Sony Xperia Z5";
+ compatible = "sony,sumire-row", "qcom,msm8994";
+};
diff --git a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi
new file mode 100644
index 0000000000..4032b7478f
--- /dev/null
+++ b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+#include "msm8994.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <0xcf 0x20001>;
+ qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
+ qcom,board-id = <8 0>;
+
+ /* Kitakami firmware doesn't support PSCI */
+ /delete-node/ psci;
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ button@0 {
+ label = "Volume Down";
+ gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ button@1 {
+ label = "Volume Up";
+ gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ button@2 {
+ label = "Camera Snapshot";
+ gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ button@3 {
+ label = "Camera Focus";
+ gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* This is for getting crash logs using Android downstream kernels */
+ ramoops@1fe00000 {
+ compatible = "ramoops";
+ reg = <0x0 0x1fe00000 0x0 0x200000>;
+ console-size = <0x100000>;
+ record-size = <0x10000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x80000>;
+ };
+
+ continuous_splash: framebuffer@3401000{
+ reg = <0x0 0x3401000 0x0 0x2200000>;
+ no-map;
+ };
+
+ dfps_data_mem: dfps_data_mem@3400000 {
+ reg = <0x0 0x3400000 0x0 0x1000>;
+ no-map;
+ };
+
+ peripheral_region: peripheral_region@7400000 {
+ reg = <0x0 0x7400000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ modem_region: modem_region@9000000 {
+ reg = <0x0 0x9000000 0x0 0x5a00000>;
+ no-map;
+ };
+
+ tzapp: modem_region@ea00000 {
+ reg = <0x0 0xea00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ fb_region: fb_region@40000000 {
+ reg = <0x00 0x40000000 0x00 0x1000000>;
+ no-map;
+ };
+ };
+};
+
+&blsp_spi0 {
+ status = "okay";
+
+ /* FPC fingerprint reader */
+};
+
+/* I2C1 is disabled on this board */
+
+&blsp_i2c2 {
+ status = "okay";
+
+ /* NXP NFC */
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ /* Empty but active */
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ /* SMB1357 charger and sii8620 HDMI/MHL bridge */
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ /* Synaptics touchscreen */
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&blsp2_uart2 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8994_regulators: pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+ vdd_l1-supply = <&pm8994_s1>;
+ vdd_l2_26_28-supply = <&pm8994_s3>;
+ vdd_l3_11-supply = <&pm8994_s3>;
+ vdd_l4_27_31-supply = <&pm8994_s3>;
+ vdd_l5_7-supply = <&pm8994_s3>;
+ vdd_l6_12_32-supply = <&pm8994_s5>;
+ vdd_l8_16_30-supply = <&vreg_vph_pwr>;
+ vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
+ vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
+ vdd_l14_15-supply = <&pm8994_s5>;
+ vdd_l17_29-supply = <&vreg_vph_pwr>;
+ vdd_l20_21-supply = <&vreg_vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+ vdd_lvs1_2 = <&pm8994_s4>;
+
+ pm8994_s1: s1 {};
+ pm8994_s2: s2 {};
+ pm8994_s3: s3 {};
+ pm8994_s4: s4 {};
+ pm8994_s5: s5 {};
+ pm8994_s6: s6 {};
+ pm8994_s7: s7 {};
+
+ pm8994_l1: l1 {};
+ pm8994_l2: l2 {};
+ pm8994_l3: l3 {};
+ pm8994_l4: l4 {};
+ pm8994_l6: l6 {};
+ pm8994_l8: l8 {};
+ pm8994_l9: l9 {};
+ pm8994_l10: l10 {};
+ pm8994_l11: l11 {};
+ pm8994_l12: l12 {};
+ pm8994_l13: l13 {};
+ pm8994_l14: l14 {};
+ pm8994_l15: l15 {};
+ pm8994_l16: l16 {};
+ pm8994_l17: l17 {};
+ pm8994_l18: l18 {};
+ pm8994_l19: l19 {};
+ pm8994_l20: l20 {};
+ pm8994_l21: l21 {};
+ pm8994_l22: l22 {};
+ pm8994_l23: l23 {};
+ pm8994_l24: l24 {};
+ pm8994_l25: l25 {};
+ pm8994_l26: l26 {};
+ pm8994_l27: l27 {};
+ pm8994_l28: l28 {};
+ pm8994_l29: l29 {};
+ pm8994_l30: l30 {};
+ pm8994_l31: l31 {};
+ pm8994_l32: l32 {};
+
+ pm8994_lvs1: lvs1 {};
+ pm8994_lvs2: lvs2 {};
+ };
+
+ pmi8994_regulators: pmi8994-regulators {
+ compatible = "qcom,rpm-pmi8994-regulators";
+
+ pmi8994_s1: s1 {};
+ pmi8994_s2: s2 {};
+ pmi8994_s3: s3 {};
+ pmi8994_bby: boost-bypass {};
+ };
+};
+
+&sdhc1 {
+ status = "okay";
+
+ /* Downstream pushes 2.95V to the sdhci device,
+ * but upstream driver REALLY wants to make vmmc 1.8v
+ * cause of the hs400-1_8v mode. MMC works fine without
+ * that regulator, so let's not use it for now.
+ * vqmmc is also disabled cause driver stll complains.
+ *
+ * vmmc-supply = <&pm8994_l20>;
+ * vqmmc-supply = <&pm8994_s4>;
+ */
+};
diff --git a/dts/src/arm64/qcom/msm8994.dtsi b/dts/src/arm64/qcom/msm8994.dtsi
index b1c2d7d6a0..6707f89860 100644
--- a/dts/src/arm64/qcom/msm8994.dtsi
+++ b/dts/src/arm64/qcom/msm8994.dtsi
@@ -6,12 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
- model = "Qualcomm Technologies, Inc. MSM 8994";
- compatible = "qcom,msm8994";
- // msm-id and pmic-id are required by bootloader for
- // proper selection of dt blob
- qcom,msm-id = <207 0x20000>;
- qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
@@ -19,35 +13,194 @@
chosen { };
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
cpus {
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
};
};
+ };
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- next-level-cache = <&L2_0>;
- L2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8994", "qcom,scm";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "hvc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_mem: smem_region@6a00000 {
+ reg = <0x0 0x6a00000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <6>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8994";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: rpmcc {
+ compatible = "qcom,rpmcc-msm8994";
+ #clock-cells = <1>;
+ };
};
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 2 0xff08>,
- <1 3 0xff08>,
- <1 4 0xff08>,
- <1 1 0xff08>;
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
@@ -62,7 +215,13 @@
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
- <0xf9002000 0x1000>;
+ <0xf9002000 0x1000>;
+ };
+
+ apcs: mailbox@f900d000 {
+ compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
+ reg = <0xf900d000 0x2000>;
+ #mbox-cells = <1>;
};
timer@f9020000 {
@@ -123,72 +282,407 @@
};
};
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
+ sdhc1: sdhci@f9824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
};
- msmgpio: pinctrl@fd510000 {
- compatible = "qcom,msm8994-pinctrl";
- reg = <0xfd510000 0x4000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&msmgpio 0 0 146>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ blsp1_dma: dma@f9904000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0xf9904000 0x19000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <18>;
+ qcom,num-ees = <4>;
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
status = "disabled";
+ };
+
+ blsp_i2c1: i2c@f9923000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9923000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi0: spi@f9923000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0xf9923000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ spi-max-frequency = <19200000>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_spi0_default>;
+ pinctrl-1 = <&blsp1_spi0_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- tcsr_mutex_regs: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
+ blsp_i2c2: i2c@f9924000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9924000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_default>;
+ pinctrl-1 = <&i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* I2C3 doesn't exist */
+
+ blsp_i2c4: i2c@f9926000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9926000 0x500>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_default>;
+ pinctrl-1 = <&i2c4_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_dma: dma@f9944000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0xf9944000 0x19000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <18>;
+ qcom,num-ees = <4>;
+ };
+
+ /* According to downstream kernels, i2c6
+ * comes before i2c5 address-wise...
+ */
+
+ blsp_i2c6: i2c@f9928000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9928000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c6_default>;
+ pinctrl-1 = <&i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_uart2: serial@f995e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf995e000 0x1000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_default>;
+ pinctrl-1 = <&blsp2_uart2_sleep>;
+ status = "disabled";
};
- clock_gcc: clock-controller@fc400000 {
+ blsp_i2c5: i2c@f9967000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9967000 0x500>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
- };
- memory {
- device_type = "memory";
- // We expect the bootloader to fill in the reg
- reg = <0 0 0 0>;
- };
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- };
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ spmi_bus: spmi@fc4c0000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ reg-names = "core", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ tcsr_mutex_regs: syscon@fd484000 {
+ compatible = "syscon";
+ reg = <0xfd484000 0x2000>;
+ };
- smem_mem: smem_region@6a00000 {
- reg = <0x0 0x6a00000 0x0 0x200000>;
- no-map;
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,msm8994-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 146>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ blsp1_uart2_default: blsp1-uart2-default {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_uart2_sleep: blsp1-uart2-sleep {
+ function = "gpio";
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart2_default: blsp2-uart2-default {
+ function = "blsp_uart8";
+ pins = "gpio45", "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_uart2_sleep: blsp2-uart2-sleep {
+ function = "gpio";
+ pins = "gpio45", "gpio46";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ i2c1_default: i2c1-default {
+ function = "blsp_i2c1";
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c1_sleep: i2c1-sleep {
+ function = "gpio";
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_default: i2c2-default {
+ function = "blsp_i2c2";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_sleep: i2c2-sleep {
+ function = "gpio";
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c4_default: i2c4-default {
+ function = "blsp_i2c4";
+ pins = "gpio19", "gpio20";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c4_sleep: i2c4-sleep {
+ function = "gpio";
+ pins = "gpio19", "gpio20";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ i2c5_default: i2c5-default {
+ function = "blsp_i2c5";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_sleep: i2c5-sleep {
+ function = "gpio";
+ pins = "gpio23", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_default: i2c6-default {
+ function = "blsp_i2c6";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_sleep: i2c6-sleep {
+ function = "gpio";
+ pins = "gpio28", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_spi0_default: blsp1-spi0-default {
+ default {
+ function = "blsp_spi1";
+ pins = "gpio0", "gpio1", "gpio3";
+ drive-strength = <10>;
+ bias-pull-down;
+ };
+ cs {
+ function = "gpio";
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_spi0_sleep: blsp1-spi0-sleep {
+ pins = "gpio0", "gpio1", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc1_clk_on: clk-on {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ sdc1_clk_off: clk-off {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ sdc1_cmd_on: cmd-on {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ sdc1_cmd_off: cmd-off {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_data_on: data-on {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ sdc1_data_off: data-off {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_rclk_on: rclk-on {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ sdc1_rclk_off: rclk-off {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
};
};
@@ -198,12 +692,22 @@
#hwlock-cells = <1>;
};
- qcom,smem@6a00000 {
- compatible = "qcom,smem";
- memory-region = <&smem_mem>;
- hwlocks = <&tcsr_mutex 3>;
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 0xff08>,
+ <GIC_PPI 3 0xff08>,
+ <GIC_PPI 4 0xff08>,
+ <GIC_PPI 1 0xff08>;
};
-};
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
+};
-#include "msm8994-pins.dtsi"
diff --git a/dts/src/arm64/qcom/msm8998-clamshell.dtsi b/dts/src/arm64/qcom/msm8998-clamshell.dtsi
index 6ab830d018..00d84fb217 100644
--- a/dts/src/arm64/qcom/msm8998-clamshell.dtsi
+++ b/dts/src/arm64/qcom/msm8998-clamshell.dtsi
@@ -202,7 +202,7 @@
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
- vreg_15a_1p8: l15 {
+ vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
diff --git a/dts/src/arm64/qcom/msm8998-lenovo-miix-630.dts b/dts/src/arm64/qcom/msm8998-lenovo-miix-630.dts
index 407c6a3291..89492ed519 100644
--- a/dts/src/arm64/qcom/msm8998-lenovo-miix-630.dts
+++ b/dts/src/arm64/qcom/msm8998-lenovo-miix-630.dts
@@ -25,6 +25,11 @@
};
};
+&remoteproc_mss {
+ firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn",
+ "qcom/LENOVO/81F1/qcdsp28998.mbn";
+};
+
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/src/arm64/qcom/msm8998-mtp.dtsi b/dts/src/arm64/qcom/msm8998-mtp.dtsi
index 8a14b2bf7b..cec42437b3 100644
--- a/dts/src/arm64/qcom/msm8998-mtp.dtsi
+++ b/dts/src/arm64/qcom/msm8998-mtp.dtsi
@@ -235,7 +235,7 @@
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
- vreg_15a_1p8: l15 {
+ vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
diff --git a/dts/src/arm64/qcom/pm660.dtsi b/dts/src/arm64/qcom/pm660.dtsi
new file mode 100644
index 0000000000..ea0e9558d0
--- /dev/null
+++ b/dts/src/arm64/qcom/pm660.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+ pmic@0 {
+ compatible = "qcom,pm660", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+
+ reg = <0x800>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+ };
+
+ };
+
+ pm660_gpios: gpios@c000 {
+ compatible = "qcom,pm660-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm660_gpios 0 0 13>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-cells =<2>;
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/pm660l.dtsi b/dts/src/arm64/qcom/pm660l.dtsi
new file mode 100644
index 0000000000..edba6de020
--- /dev/null
+++ b/dts/src/arm64/qcom/pm660l.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+ pmic@2 {
+ compatible = "qcom,pm660l", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm660l_gpios: gpios@c000 {
+ compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm660l_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@3 {
+ compatible = "qcom,pm660l", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
diff --git a/dts/src/arm64/qcom/pm8009.dtsi b/dts/src/arm64/qcom/pm8009.dtsi
new file mode 100644
index 0000000000..b126d7e7e4
--- /dev/null
+++ b/dts/src/arm64/qcom/pm8009.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@a {
+ compatible = "qcom,pm8009", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8009_pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ };
+
+ pm8009_gpios: gpio@c000 {
+ compatible = "qcom,pm8005-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@b {
+ compatible = "qcom,pm8009", "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm64/qcom/pm8150.dtsi b/dts/src/arm64/qcom/pm8150.dtsi
index c0b1974586..1b64069275 100644
--- a/dts/src/arm64/qcom/pm8150.dtsi
+++ b/dts/src/arm64/qcom/pm8150.dtsi
@@ -9,6 +9,37 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
+/ {
+ thermal-zones {
+ pm8150 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pm8150_0: pmic@0 {
compatible = "qcom,pm8150", "qcom,spmi-pmic";
@@ -30,6 +61,15 @@
};
};
+ pm8150_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
pm8150_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
@@ -38,8 +78,6 @@
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
diff --git a/dts/src/arm64/qcom/pm8150b.dtsi b/dts/src/arm64/qcom/pm8150b.dtsi
index 40b5d75a4a..e112e8876d 100644
--- a/dts/src/arm64/qcom/pm8150b.dtsi
+++ b/dts/src/arm64/qcom/pm8150b.dtsi
@@ -8,6 +8,37 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+/ {
+ thermal-zones {
+ pm8150b {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150b_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pmic@2 {
compatible = "qcom,pm8150b", "qcom,spmi-pmic";
@@ -22,7 +53,16 @@
status = "disabled";
};
- adc@3100 {
+ pm8150b_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150b_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8150b_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
@@ -30,8 +70,6 @@
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
diff --git a/dts/src/arm64/qcom/pm8150l.dtsi b/dts/src/arm64/qcom/pm8150l.dtsi
index cf05e0685d..62139538b7 100644
--- a/dts/src/arm64/qcom/pm8150l.dtsi
+++ b/dts/src/arm64/qcom/pm8150l.dtsi
@@ -8,6 +8,37 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+/ {
+ thermal-zones {
+ pm8150l {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8150l_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pmic@4 {
compatible = "qcom,pm8150l", "qcom,spmi-pmic";
@@ -22,7 +53,16 @@
status = "disabled";
};
- adc@3100 {
+ pm8150l_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150l_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8150l_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
@@ -30,8 +70,6 @@
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
-
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
diff --git a/dts/src/arm64/qcom/pmi8998.dtsi b/dts/src/arm64/qcom/pmi8998.dtsi
index 23f9146a16..d016b12967 100644
--- a/dts/src/arm64/qcom/pmi8998.dtsi
+++ b/dts/src/arm64/qcom/pmi8998.dtsi
@@ -25,5 +25,17 @@
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ labibb {
+ compatible = "qcom,pmi8998-lab-ibb";
+
+ ibb: ibb {
+ interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ lab: lab {
+ interrupts = <0x3 0xde 0x0 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
};
};
diff --git a/dts/src/arm64/qcom/qcs404.dtsi b/dts/src/arm64/qcom/qcs404.dtsi
index c685a16648..b654b802e9 100644
--- a/dts/src/arm64/qcom/qcs404.dtsi
+++ b/dts/src/arm64/qcom/qcs404.dtsi
@@ -1097,6 +1097,21 @@
status = "disabled";
};
+ imem@8600000 {
+ compatible = "simple-mfd";
+ reg = <0x08600000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0x08600000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
diff --git a/dts/src/arm64/qcom/sc7180-idp.dts b/dts/src/arm64/qcom/sc7180-idp.dts
index 4e9149d82d..d8b550723b 100644
--- a/dts/src/arm64/qcom/sc7180-idp.dts
+++ b/dts/src/arm64/qcom/sc7180-idp.dts
@@ -21,6 +21,7 @@
bluetooth0 = &bluetooth;
hsuart0 = &uart3;
serial0 = &uart8;
+ wifi0 = &wifi;
};
chosen {
@@ -287,6 +288,10 @@
};
};
+&qfprom {
+ vcc-supply = <&vreg_l11a_1p8>;
+};
+
&qspi {
status = "okay";
pinctrl-names = "default";
@@ -312,7 +317,7 @@
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7180-mss-pil";
- iommus = <&apps_smmu 0x460 0x1>, <&apps_smmu 0x444 0x3>;
+ iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
memory-region = <&mba_mem &mpss_mem>;
};
@@ -389,6 +394,18 @@
};
};
+&wifi {
+ status = "okay";
+ vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>;
+ vdd-1.8-xo-supply = <&vreg_l1c_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l2c_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l10c_3p3>;
+ vdd-3.3-ch1-supply = <&vreg_l11c_3p3>;
+ wifi-firmware {
+ iommus = <&apps_smmu 0xc2 0x1>;
+ };
+};
+
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk {
diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi
index 31b9217bb5..d46b3833e5 100644
--- a/dts/src/arm64/qcom/sc7180.dtsi
+++ b/dts/src/arm64/qcom/sc7180.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
@@ -130,6 +131,9 @@
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -153,6 +157,9 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
@@ -172,6 +179,9 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
@@ -191,6 +201,9 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
@@ -210,6 +223,9 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
@@ -229,6 +245,9 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
@@ -248,6 +267,9 @@
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_600>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
@@ -267,6 +289,9 @@
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_700>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
@@ -366,6 +391,141 @@
};
};
+ cpu0_opp_table: cpu0_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu0_opp2: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu0_opp3: opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu0_opp4: opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <1804000 8908800>;
+ };
+
+ cpu0_opp5: opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <2188000 12902400>;
+ };
+
+ cpu0_opp6: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <2188000 12902400>;
+ };
+
+ cpu0_opp7: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <3072000 15052800>;
+ };
+
+ cpu0_opp8: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <3072000 15052800>;
+ };
+
+ cpu0_opp9: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <3072000 15052800>;
+ };
+
+ cpu0_opp10: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <4068000 22425600>;
+ };
+ };
+
+ cpu6_opp_table: cpu6_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu6_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp2: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp3: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp4: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp5: opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp6: opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <4068000 12902400>;
+ };
+
+ cpu6_opp7: opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu6_opp8: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu6_opp9: opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu6_opp10: opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <6220000 22425600>;
+ };
+
+ cpu6_opp11: opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <6220000 22425600>;
+ };
+
+ cpu6_opp12: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6220000 22425600>;
+ };
+
+ cpu6_opp13: opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu6_opp14: opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu6_opp15: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <8532000 23347200>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -498,9 +658,15 @@
#power-domain-cells = <1>;
};
- qfprom@784000 {
+ qfprom: efuse@784000 {
compatible = "qcom,qfprom";
- reg = <0 0x00784000 0 0x8ff>;
+ reg = <0 0x00784000 0 0x8ff>,
+ <0 0x00780000 0 0x7a0>,
+ <0 0x00782000 0 0x100>,
+ <0 0x00786000 0 0x1fff>;
+
+ clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
+ clock-names = "core";
#address-cells = <1>;
#size-cells = <1>;
@@ -524,6 +690,8 @@
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
bus-width = <8>;
non-removable;
@@ -535,6 +703,39 @@
mmc-hs400-enhanced-strobe;
status = "disabled";
+
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
qupv3_id_0: geniqup@8c0000 {
@@ -547,6 +748,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -559,6 +762,11 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -572,6 +780,11 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -583,6 +796,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -596,6 +814,11 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -609,6 +832,11 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -620,6 +848,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -633,6 +866,11 @@
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -644,6 +882,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -657,6 +900,11 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -670,6 +918,11 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -681,6 +934,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -694,6 +952,11 @@
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -705,6 +968,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -718,6 +986,11 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -731,6 +1004,11 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -742,6 +1020,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -756,6 +1039,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -768,6 +1053,11 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -781,6 +1071,11 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -792,6 +1087,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -805,6 +1105,11 @@
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -816,6 +1121,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -829,6 +1139,11 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -842,6 +1157,11 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -853,6 +1173,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -866,6 +1191,11 @@
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -877,6 +1207,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -890,6 +1225,11 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -903,6 +1243,11 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -914,6 +1259,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -927,6 +1277,11 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -940,6 +1295,11 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -951,6 +1311,11 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -1459,6 +1824,57 @@
};
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sc7180-mpss-pas";
+ reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <&gcc GCC_MSS_NAV_AXI_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&gcc GCC_MSS_MFAB_AXIS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bus", "nav", "snoc_axi",
+ "mnoc_axi", "xo";
+
+ power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
+ <&rpmhpd SC7180_CX>,
+ <&rpmhpd SC7180_MX>,
+ <&rpmhpd SC7180_MSS>;
+ power-domain-names = "load_state", "cx", "mx", "mss";
+
+ memory-region = <&mpss_mem>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
+ reset-names = "mss_restart", "pdc_reset";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
+ qcom,spare-regs = <&tcsr_regs 0xb3e4>;
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ mboxes = <&apss_shared 12>;
+ };
+ };
+
gpu: gpu@5000000 {
compatible = "qcom,adreno-618.0", "qcom,adreno";
#stream-id-cells = <16>;
@@ -1470,42 +1886,52 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+ interconnect-names = "gfx-mem";
+
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <8532000>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <7216000>;
};
opp-565000000 {
opp-hz = /bits/ 64 <565000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <5412000>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5412000>;
};
opp-355000000 {
opp-hz = /bits/ 64 <355000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <3072000>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <3072000>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ opp-peak-kBps = <1804000>;
};
};
};
@@ -1711,6 +2137,7 @@
etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06048000 0 0x1000>;
+ iommus = <&apps_smmu 0x04a0 0x20>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -1783,6 +2210,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ qcom,replicator-loses-context;
out-ports {
port {
@@ -1810,6 +2238,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1829,6 +2258,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1848,6 +2278,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1867,6 +2298,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1886,6 +2318,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1905,6 +2338,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1924,6 +2358,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -1943,6 +2378,7 @@
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
out-ports {
port {
@@ -2054,57 +2490,6 @@
};
};
- remoteproc_mpss: remoteproc@4080000 {
- compatible = "qcom,sc7180-mpss-pas";
- reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
- reg-names = "qdsp6", "rmb";
-
- interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready", "handover",
- "stop-ack", "shutdown-ack";
-
- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
- <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
- <&gcc GCC_MSS_NAV_AXI_CLK>,
- <&gcc GCC_MSS_SNOC_AXI_CLK>,
- <&gcc GCC_MSS_MFAB_AXIS_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "bus", "nav", "snoc_axi",
- "mnoc_axi", "xo";
-
- power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
- <&rpmhpd SC7180_CX>,
- <&rpmhpd SC7180_MX>,
- <&rpmhpd SC7180_MSS>;
- power-domain-names = "load_state", "cx", "mx", "mss";
-
- memory-region = <&mpss_mem>;
-
- qcom,smem-states = <&modem_smp2p_out 0>;
- qcom,smem-state-names = "stop";
-
- resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
- <&pdc_reset PDC_MODEM_SYNC_RESET>;
- reset-names = "mss_restart", "pdc_reset";
-
- qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- qcom,spare-regs = <&tcsr_regs 0xb3e4>;
-
- status = "disabled";
-
- glink-edge {
- interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
- label = "modem";
- qcom,remote-pid = <1>;
- mboxes = <&apss_shared 12>;
- };
- };
-
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2117,10 +2502,45 @@
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
qspi: spi@88dc000 {
@@ -2132,6 +2552,11 @@
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC
+ &config_noc SLAVE_QSPI_0>;
+ interconnect-names = "qspi-config";
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
status = "disabled";
};
@@ -2257,6 +2682,7 @@
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
};
};
@@ -2355,6 +2781,8 @@
<19200000>,
<19200000>,
<19200000>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SC7180_CX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
@@ -2372,6 +2800,31 @@
};
};
};
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
};
dsi0: dsi@ae94000 {
@@ -2395,6 +2848,9 @@
"iface",
"bus";
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SC7180_CX>;
+
phys = <&dsi_phy>;
phy-names = "dsi";
@@ -2420,6 +2876,25 @@
};
};
};
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
};
dsi_phy: dsi-phy@ae94400 {
@@ -2814,6 +3289,29 @@
#freq-domain-cells = <1>;
};
+
+ wifi: wifi@18800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0 0x18800000 0 0x800000>;
+ reg-names = "membase";
+ iommus = <&apps_smmu 0xc0 0x1>;
+ interrupts =
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
+ memory-region = <&wlan_mem>;
+ qcom,msa-fixed-perm;
+ status = "disabled";
+ };
};
thermal-zones {
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts b/dts/src/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts
new file mode 100644
index 0000000000..46a7f2b26e
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-ganges-kirin.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Martin Botka
+ */
+
+/dts-v1/;
+
+#include "sdm630-sony-xperia-ganges.dtsi"
+
+/ {
+ model = "Sony Xperia 10";
+ compatible = "sony,kirin-row", "qcom,sdm630";
+};
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-ganges.dtsi b/dts/src/arm64/qcom/sdm630-sony-xperia-ganges.dtsi
new file mode 100644
index 0000000000..cf2e8b5d60
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-ganges.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Martin Botka
+ */
+
+/dts-v1/;
+
+/* Ganges is very similar to Nile, but
+ * there are some differences that will need
+ * to be addresed when more peripherals are
+ * enabled upstream. Hence the separate DTSI.
+ */
+#include "sdm630-sony-xperia-nile.dtsi"
+
+/ {
+ chosen {
+ framebuffer@9d400000 {
+ reg = <0 0x9d400000 0 (2520 * 1080 * 4)>;
+ height = <2520>;
+ };
+ };
+
+ /* Yes, this is intentional.
+ * Ganges devices only use gpio-keys for
+ * Volume Down, but currently there's an
+ * issue with it that has to be resolved.
+ * Until then, let's not make the kernel panic
+ */
+ /delete-node/ gpio-keys;
+
+ soc {
+
+ i2c@c175000 {
+ status = "okay";
+
+ /* Novatek touchscreen */
+ };
+ };
+
+};
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts
new file mode 100644
index 0000000000..8fca0b69fa
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-discovery.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "sdm630-sony-xperia-nile.dtsi"
+
+/ {
+ model = "Sony Xperia XA2 Ultra";
+ compatible = "sony,discovery-row", "qcom,sdm630";
+};
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts
new file mode 100644
index 0000000000..90dcd4ebaa
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-pioneer.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "sdm630-sony-xperia-nile.dtsi"
+
+/ {
+ model = "Sony Xperia XA2";
+ compatible = "sony,pioneer-row", "qcom,sdm630";
+};
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts
new file mode 100644
index 0000000000..fae5f1bb68
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-nile-voyager.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "sdm630-sony-xperia-nile.dtsi"
+
+/ {
+ model = "Sony Xperia XA2 Plus";
+ compatible = "sony,voyager-row", "qcom,sdm630";
+
+ chosen {
+ framebuffer@9d400000 {
+ reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
+ height = <2160>;
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi b/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi
new file mode 100644
index 0000000000..9ba359c848
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+/dts-v1/;
+
+#include "sdm630.dtsi"
+#include "pm660.dtsi"
+#include "pm660l.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+/ {
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <318 0>;
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00>;
+
+ /* This part enables graphical output via bootloader-enabled display */
+ chosen {
+ bootargs = "earlycon=tty0 console=tty0";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "framebuffer0";
+
+ framebuffer0: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9d400000 0 (1920 * 1080 * 4)>;
+ width = <1080>;
+ height = <1920>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ status= "okay";
+ };
+ };
+
+ gpio_keys {
+ status = "okay";
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ camera_focus {
+ label = "Camera Focus";
+ gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ debounce-interval = <15>;
+ };
+
+ camera_snapshot {
+ label = "Camera Snapshot";
+ gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA>;
+ debounce-interval = <15>;
+ };
+
+ vol_down {
+ label = "Volume Down";
+ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x10000>;
+ console-size = <0x60000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ ecc-size = <16>;
+ status = "okay";
+ };
+
+ debug_region@ffb00000 {
+ reg = <0x00 0xffb00000 0x00 0x100000>;
+ no-map;
+ };
+
+ removed_region@85800000 {
+ reg = <0x00 0x85800000 0x00 0x3700000>;
+ no-map;
+ };
+ };
+
+ soc {
+ sdhci@c0c4000 {
+ status = "okay";
+
+ mmc-ddr-1_8v;
+ /* SoMC Nile platform's eMMC doesn't support HS200 mode */
+ mmc-hs400-1_8v;
+ };
+
+ i2c@c175000 {
+ status = "okay";
+
+ /* Synaptics touchscreen */
+ };
+
+ i2c@c176000 {
+ status = "okay";
+
+ /* SMB1351 charger */
+ };
+
+ serial@c1af000 {
+ status = "okay";
+ };
+
+ /* I2C3, 4, 5, 7 and 8 are disabled on this board. */
+
+ i2c@c1b6000 {
+ status = "okay";
+
+ /* NXP NFC */
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/sdm630.dtsi b/dts/src/arm64/qcom/sdm630.dtsi
new file mode 100644
index 0000000000..88efe8200c
--- /dev/null
+++ b/dts/src/arm64/qcom/sdm630.dtsi
@@ -0,0 +1,1174 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2020, Konrad Dybcio
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&PERF_CPU_SLEEP_0
+ &PERF_CPU_SLEEP_1
+ &PERF_CLUSTER_SLEEP_0
+ &PERF_CLUSTER_SLEEP_1
+ &PERF_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1126>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&PERF_CPU_SLEEP_0
+ &PERF_CPU_SLEEP_1
+ &PERF_CLUSTER_SLEEP_0
+ &PERF_CLUSTER_SLEEP_1
+ &PERF_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1126>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ cpu-idle-states = <&PERF_CPU_SLEEP_0
+ &PERF_CPU_SLEEP_1
+ &PERF_CLUSTER_SLEEP_0
+ &PERF_CLUSTER_SLEEP_1
+ &PERF_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1126>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ cpu-idle-states = <&PERF_CPU_SLEEP_0
+ &PERF_CPU_SLEEP_1
+ &PERF_CLUSTER_SLEEP_0
+ &PERF_CLUSTER_SLEEP_1
+ &PERF_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1126>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU4: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&PWR_CPU_SLEEP_0
+ &PWR_CPU_SLEEP_1
+ &PWR_CLUSTER_SLEEP_0
+ &PWR_CLUSTER_SLEEP_1
+ &PWR_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&PWR_CPU_SLEEP_0
+ &PWR_CPU_SLEEP_1
+ &PWR_CLUSTER_SLEEP_0
+ &PWR_CLUSTER_SLEEP_1
+ &PWR_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU6: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ cpu-idle-states = <&PWR_CPU_SLEEP_0
+ &PWR_CPU_SLEEP_1
+ &PWR_CLUSTER_SLEEP_0
+ &PWR_CLUSTER_SLEEP_1
+ &PWR_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU7: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ cpu-idle-states = <&PWR_CPU_SLEEP_0
+ &PWR_CPU_SLEEP_1
+ &PWR_CLUSTER_SLEEP_0
+ &PWR_CLUSTER_SLEEP_1
+ &PWR_CLUSTER_SLEEP_2>;
+ capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "pwr-retention";
+ arm,psci-suspend-param = <0x40000002>;
+ entry-latency-us = <338>;
+ exit-latency-us = <423>;
+ min-residency-us = <200>;
+ };
+
+ PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "pwr-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <515>;
+ exit-latency-us = <1821>;
+ min-residency-us = &