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authorSascha Hauer <s.hauer@pengutronix.de>2021-08-09 21:17:51 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2021-08-09 21:17:51 +0200
commit6187b17da4b277417f34fe0b0b90bbaddcbc599e (patch)
tree51cbbaa0fa325c592d084eb7d197a5df0e7a43bb /dts/src/arm64
parentc53e1fc545e686e1f48c8efb9057fc72e158f183 (diff)
downloadbarebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.gz
barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.xz
dts: update to v5.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64')
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi25
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts2
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64.dtsi62
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts195
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6.dtsi9
-rw-r--r--dts/src/arm64/amlogic/meson-axg.dtsi1
-rw-r--r--dts/src/arm64/amlogic/meson-g12-common.dtsi1
-rw-r--r--dts/src/arm64/amlogic/meson-gx.dtsi1
-rw-r--r--dts/src/arm64/amlogic/meson-khadas-vim3.dtsi41
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts646
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts13
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts17
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts48
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-odroid.dtsi9
-rw-r--r--dts/src/arm64/amlogic/meson-sm1.dtsi10
-rw-r--r--dts/src/arm64/arm/juno-base.dtsi6
-rw-r--r--dts/src/arm64/arm/vexpress-v2m-rs1.dtsi2
-rw-r--r--dts/src/arm64/broadcom/bcm2711-rpi-400.dts2
-rw-r--r--dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi2
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi8
-rw-r--r--dts/src/arm64/exynos/exynos5433-tm2-common.dtsi1
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a-frwy.dts4
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a.dtsi14
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-rdb.dts4
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a.dtsi24
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a.dtsi12
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a.dtsi24
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a.dtsi24
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a.dtsi16
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a.dtsi16
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi1
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a.dtsi24
-rw-r--r--dts/src/arm64/freescale/imx8-ss-conn.dtsi50
-rw-r--r--dts/src/arm64/freescale/imx8mm-evk.dtsi1
-rw-r--r--dts/src/arm64/freescale/imx8mm-venice-gw7901.dts1019
-rw-r--r--dts/src/arm64/freescale/imx8mm.dtsi363
-rw-r--r--dts/src/arm64/freescale/imx8mn-beacon-som.dtsi3
-rw-r--r--dts/src/arm64/freescale/imx8mn-evk.dtsi1
-rw-r--r--dts/src/arm64/freescale/imx8mn.dtsi147
-rw-r--r--dts/src/arm64/freescale/imx8mp-evk.dts139
-rw-r--r--dts/src/arm64/freescale/imx8mp-phycore-som.dtsi25
-rw-r--r--dts/src/arm64/freescale/imx8mp.dtsi18
-rw-r--r--dts/src/arm64/freescale/imx8mq-evk.dts1
-rw-r--r--dts/src/arm64/freescale/imx8mq-nitrogen.dts182
-rw-r--r--dts/src/arm64/freescale/imx8mq.dtsi16
-rw-r--r--dts/src/arm64/hisilicon/hi3660-coresight.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts2
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi3670-hikey970.dts2
-rw-r--r--dts/src/arm64/hisilicon/hi3670.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi6220-coresight.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi6220-hikey.dts2
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hip05-d02.dts2
-rw-r--r--dts/src/arm64/hisilicon/hip05.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hip06-d03.dts2
-rw-r--r--dts/src/arm64/hisilicon/hip06.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hip07-d05.dts2
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi2
-rw-r--r--dts/src/arm64/marvell/armada-3720-turris-mox.dts6
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi10
-rw-r--r--dts/src/arm64/marvell/armada-ap807.dtsi3
-rw-r--r--dts/src/arm64/marvell/cn9130-db.dts2
-rw-r--r--dts/src/arm64/mediatek/mt8167.dtsi121
-rw-r--r--dts/src/arm64/mediatek/mt8173.dtsi60
-rw-r--r--dts/src/arm64/mediatek/mt8183-evb.dts5
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts30
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts44
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts32
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi27
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts16
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts16
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts12
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts13
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts12
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi26
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi8
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi4
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi4
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi4
-rw-r--r--dts/src/arm64/mediatek/mt8183-kukui.dtsi23
-rw-r--r--dts/src/arm64/mediatek/mt8183-pumpkin.dts5
-rw-r--r--dts/src/arm64/mediatek/mt8183.dtsi110
-rw-r--r--dts/src/arm64/microchip/sparx5.dtsi94
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb134_board.dtsi481
-rw-r--r--dts/src/arm64/microchip/sparx5_pcb135_board.dtsi621
-rw-r--r--dts/src/arm64/nvidia/tegra186-p2771-0000.dts4
-rw-r--r--dts/src/arm64/nvidia/tegra186.dtsi4
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2972-0000.dts4
-rw-r--r--dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi595
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi100
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2371-2180.dts2
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2597.dtsi2
-rw-r--r--dts/src/arm64/nvidia/tegra210-p3450-0000.dts4
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi93
-rw-r--r--dts/src/arm64/qcom/apq8096-ifc6640.dts24
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk10-c1.dts11
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk10-c2.dts10
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk10.dtsi76
-rw-r--r--dts/src/arm64/qcom/ipq8074.dtsi20
-rw-r--r--dts/src/arm64/qcom/msm8916-alcatel-idol347.dts26
-rw-r--r--dts/src/arm64/qcom/msm8916-huawei-g7.dts454
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi131
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts47
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts26
-rw-r--r--dts/src/arm64/qcom/msm8994-angler-rev-101.dts4
-rw-r--r--dts/src/arm64/qcom/msm8996-mtp.dtsi2
-rw-r--r--dts/src/arm64/qcom/msm8996-pins.dtsi653
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi1001
-rw-r--r--dts/src/arm64/qcom/msm8998.dtsi2
-rw-r--r--dts/src/arm64/qcom/pm6150.dtsi24
-rw-r--r--dts/src/arm64/qcom/pm7325.dtsi53
-rw-r--r--dts/src/arm64/qcom/pm8150.dtsi12
-rw-r--r--dts/src/arm64/qcom/pm8350c.dtsi32
-rw-r--r--dts/src/arm64/qcom/pm8994.dtsi8
-rw-r--r--dts/src/arm64/qcom/pmi8994.dtsi13
-rw-r--r--dts/src/arm64/qcom/pmk8350.dtsi51
-rw-r--r--dts/src/arm64/qcom/pmm8155au_1.dtsi135
-rw-r--r--dts/src/arm64/qcom/pmm8155au_2.dtsi108
-rw-r--r--dts/src/arm64/qcom/pmr735a.dtsi32
-rw-r--r--dts/src/arm64/qcom/qcs404-evb.dtsi2
-rw-r--r--dts/src/arm64/qcom/qcs404.dtsi4
-rw-r--r--dts/src/arm64/qcom/qrb5165-rb5.dts98
-rw-r--r--dts/src/arm64/qcom/sa8155p-adp.dts360
-rw-r--r--dts/src/arm64/qcom/sc7180-idp.dts169
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts4
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts22
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts (renamed from dts/src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts)6
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-coachz-r3.dts (renamed from dts/src/arm64/qcom/sc7180-trogdor-coachz-r2.dts)4
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-coachz.dtsi64
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts9
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts9
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts9
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi9
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts12
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts4
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts38
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts14
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts15
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor-pompom.dtsi29
-rw-r--r--dts/src/arm64/qcom/sc7180-trogdor.dtsi121
-rw-r--r--dts/src/arm64/qcom/sc7180.dtsi142
-rw-r--r--dts/src/arm64/qcom/sc7280-idp.dts36
-rw-r--r--dts/src/arm64/qcom/sc7280.dtsi1171
-rw-r--r--dts/src/arm64/qcom/sdm845-cheza.dtsi4
-rw-r--r--dts/src/arm64/qcom/sdm845-mtp.dts5
-rw-r--r--dts/src/arm64/qcom/sdm845-oneplus-common.dtsi18
-rw-r--r--dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts114
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi4
-rw-r--r--dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts2
-rw-r--r--dts/src/arm64/qcom/sm8150-hdk.dts28
-rw-r--r--dts/src/arm64/qcom/sm8150-microsoft-surface-duo.dts543
-rw-r--r--dts/src/arm64/qcom/sm8150-mtp.dts28
-rw-r--r--dts/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts19
-rw-r--r--dts/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts13
-rw-r--r--dts/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi452
-rw-r--r--dts/src/arm64/qcom/sm8150.dtsi78
-rw-r--r--dts/src/arm64/qcom/sm8250-hdk.dts33
-rw-r--r--dts/src/arm64/qcom/sm8250-mtp.dts10
-rw-r--r--dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts15
-rw-r--r--dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts35
-rw-r--r--dts/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi636
-rw-r--r--dts/src/arm64/qcom/sm8250.dtsi192
-rw-r--r--dts/src/arm64/qcom/sm8350-mtp.dts6
-rw-r--r--dts/src/arm64/qcom/sm8350.dtsi64
-rw-r--r--dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi4
-rw-r--r--dts/src/arm64/renesas/beacon-renesom-som.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a774a1.dtsi2
-rw-r--r--dts/src/arm64/renesas/r8a774b1.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a774c0.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a774e1.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77951.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77960.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a77961.dtsi19
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77970-eagle.dts8
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts2
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts8
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi21
-rw-r--r--dts/src/arm64/renesas/r8a779a0.dtsi7
-rw-r--r--dts/src/arm64/renesas/r9a07g044.dtsi132
-rw-r--r--dts/src/arm64/renesas/r9a07g044l1.dtsi25
-rw-r--r--dts/src/arm64/renesas/r9a07g044l2-smarc.dts21
-rw-r--r--dts/src/arm64/renesas/r9a07g044l2.dtsi13
-rw-r--r--dts/src/arm64/renesas/rzg2l-smarc.dtsi27
-rw-r--r--dts/src/arm64/rockchip/px30.dtsi28
-rw-r--r--dts/src/arm64/rockchip/rk3308-roc-cc.dts4
-rw-r--r--dts/src/arm64/rockchip/rk3308.dtsi96
-rw-r--r--dts/src/arm64/rockchip/rk3326-odroid-go2.dts37
-rw-r--r--dts/src/arm64/rockchip/rk3328-nanopi-r2s.dts36
-rw-r--r--dts/src/arm64/rockchip/rk3328-roc-cc.dts9
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock-pi-e.dts7
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts5
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi13
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi2
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts162
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi2
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-kobol-helios64.dts121
-rw-r--r--dts/src/arm64/rockchip/rk3399-nanopi-r4s.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399-nanopi4.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3399-roc-pc.dtsi16
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock-pi-4.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi68
-rw-r--r--dts/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3568-evb1-v10.dts79
-rw-r--r--dts/src/arm64/rockchip/rk3568-pinctrl.dtsi3111
-rw-r--r--dts/src/arm64/rockchip/rk3568.dtsi593
-rw-r--r--dts/src/arm64/rockchip/rockchip-pinconf.dtsi344
-rw-r--r--dts/src/arm64/ti/k3-am64-main.dtsi222
-rw-r--r--dts/src/arm64/ti/k3-am64-mcu.dtsi6
-rw-r--r--dts/src/arm64/ti/k3-am642-evm.dts110
-rw-r--r--dts/src/arm64/ti/k3-am642-sk.dts121
-rw-r--r--dts/src/arm64/ti/k3-am65-iot2050-common.dtsi63
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi37
-rw-r--r--dts/src/arm64/ti/k3-am65-mcu.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am65-wakeup.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am6528-iot2050-basic.dts5
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts49
-rw-r--r--dts/src/arm64/ti/k3-j7200-common-proc-board.dts2
-rw-r--r--dts/src/arm64/ti/k3-j7200-main.dtsi25
-rw-r--r--dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi6
-rw-r--r--dts/src/arm64/ti/k3-j721e-common-proc-board.dts62
-rw-r--r--dts/src/arm64/ti/k3-j721e-main.dtsi126
-rw-r--r--dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi4
-rw-r--r--dts/src/arm64/toshiba/tmpv7708-rm-mbrc.dts8
-rw-r--r--dts/src/arm64/toshiba/tmpv7708.dtsi9
-rw-r--r--dts/src/arm64/toshiba/tmpv7708_pins.dtsi5
232 files changed, 17493 insertions, 1886 deletions
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi b/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
index 79adea3f8c..5b44a979f2 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
@@ -25,6 +25,11 @@
/* Backlight configuration differs per PinePhone revision. */
};
+ bt_sco_codec: bt-sco-codec {
+ #sound-dai-cells = <1>;
+ compatible = "linux,bt-sco";
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -91,6 +96,8 @@
};
&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&aif3_pins>;
status = "okay";
};
@@ -426,6 +433,7 @@
&sound {
status = "okay";
+ simple-audio-card,name = "PinePhone";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
simple-audio-card,widgets = "Microphone", "Headset Microphone",
"Microphone", "Internal Microphone",
@@ -447,6 +455,23 @@
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
"MIC2", "Headset Microphone";
+
+ simple-audio-card,dai-link@2 {
+ format = "dsp_a";
+ frame-master = <&link2_codec>;
+ bitclock-master = <&link2_codec>;
+ bitclock-inversion;
+
+ link2_cpu: cpu {
+ sound-dai = <&bt_sco_codec 0>;
+ };
+
+ link2_codec: codec {
+ sound-dai = <&codec 2>;
+ dai-tdm-slot-num = <1>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
};
&uart0 {
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
index e22b94c836..5e66ce1a33 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dc1sw>;
status = "okay";
diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi
index 5b30e6c1fa..6ddb717f2f 100644
--- a/dts/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi
@@ -131,12 +131,10 @@
};
sound: sound {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-a64-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "DACL",
@@ -145,12 +143,19 @@
"ADCR", "Right ADC";
status = "disabled";
- cpudai: simple-audio-card,cpu {
- sound-dai = <&dai>;
- };
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+ mclk-fs = <128>;
+
+ link0_cpu: cpu {
+ sound-dai = <&dai>;
+ };
- link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ link0_codec: codec {
+ sound-dai = <&codec 0>;
+ };
};
};
@@ -659,6 +664,18 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ aif2_pins: aif2-pins {
+ pins = "PB4", "PB5", "PB6", "PB7";
+ function = "aif2";
+ };
+
+ /omit-if-no-ref/
+ aif3_pins: aif3-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "aif3";
+ };
+
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
@@ -799,6 +816,23 @@
};
};
+ timer@1c20c00 {
+ compatible = "allwinner,sun50i-a64-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun50i-a64-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
@@ -880,7 +914,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
@@ -1325,13 +1359,5 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- wdt0: watchdog@1c20ca0 {
- compatible = "allwinner,sun50i-a64-wdt",
- "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
};
};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/dts/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts
new file mode 100644
index 0000000000..55bcdf8d1a
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-h6.dtsi b/dts/src/arm64/allwinner/sun50i-h6.dtsi
index 50815867ce..30d396e8c7 100644
--- a/dts/src/arm64/allwinner/sun50i-h6.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-h6.dtsi
@@ -271,6 +271,15 @@
};
};
+ timer@3009000 {
+ compatible = "allwinner,sun50i-h6-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x03009000 0xa0>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h6-wdt",
"allwinner,sun6i-a31-wdt";
diff --git a/dts/src/arm64/amlogic/meson-axg.dtsi b/dts/src/arm64/amlogic/meson-axg.dtsi
index 895c43c7af..3f5254eeb4 100644
--- a/dts/src/arm64/amlogic/meson-axg.dtsi
+++ b/dts/src/arm64/amlogic/meson-axg.dtsi
@@ -1871,6 +1871,7 @@
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
diff --git a/dts/src/arm64/amlogic/meson-g12-common.dtsi b/dts/src/arm64/amlogic/meson-g12-common.dtsi
index 793d48f723..00c6f53290 100644
--- a/dts/src/arm64/amlogic/meson-g12-common.dtsi
+++ b/dts/src/arm64/amlogic/meson-g12-common.dtsi
@@ -2317,6 +2317,7 @@
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi
index 3d00404aae..6b457b2c30 100644
--- a/dts/src/arm64/amlogic/meson-gx.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx.dtsi
@@ -301,6 +301,7 @@
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
diff --git a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
index 66d67524b0..3cf4ecb6d5 100644
--- a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
+++ b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi
@@ -171,11 +171,16 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
+ audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
@@ -198,8 +203,20 @@
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
@@ -214,7 +231,7 @@
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
@@ -454,10 +471,26 @@
status = "okay";
};
+&tdmin_a {
+ status = "okay";
+};
+
&tdmout_a {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
diff --git a/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts
new file mode 100644
index 0000000000..effaa138b5
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m5", "amlogic,sm1";
+ model = "Banana Pi BPI-M5";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ key {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = &ethmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* TOFIX: handle CVBS_DET on SARADC channel 0 */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M5";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
+ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "Lineout", "ACODEC LOLP",
+ "Lineout", "ACODEC LORP";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ethmac {
+ pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub on the BPI-M5 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
diff --git a/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
index 06de0b1ce7..f2c0981435 100644
--- a/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
+++ b/dts/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
@@ -32,6 +32,19 @@
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ model = "G12B-KHADAS-VIM3L";
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 13", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
+ };
};
&cpu0 {
diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts b/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
index 8c327c03d8..8c30ce6368 100644
--- a/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
+++ b/dts/src/arm64/amlogic/meson-sm1-odroid-c4.dts
@@ -23,18 +23,6 @@
};
};
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
model = "ODROID-C4";
};
@@ -58,8 +46,3 @@
&ir {
linux,rc-map-name = "rc-odroid";
};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts b/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
index bf15700c4b..f3f953225b 100644
--- a/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
+++ b/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
@@ -44,6 +44,32 @@
};
};
+ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
+ p12v_0: regulator-p12v_0 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
+ p12v_1: regulator-p12v_1 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
sound {
model = "ODROID-HC4";
};
@@ -90,7 +116,25 @@
status = "disabled";
};
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+};
+
+&usb2_phy0 {
+ status = "disabled";
};
diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi
index d14716b3d0..fd0ad85c16 100644
--- a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi
+++ b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi
@@ -46,8 +46,13 @@
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
gpios-states = <0>;
states = <3300000 0>,
@@ -78,6 +83,8 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
diff --git a/dts/src/arm64/amlogic/meson-sm1.dtsi b/dts/src/arm64/amlogic/meson-sm1.dtsi
index c309517aba..3d8b1f4f20 100644
--- a/dts/src/arm64/amlogic/meson-sm1.dtsi
+++ b/dts/src/arm64/amlogic/meson-sm1.dtsi
@@ -401,6 +401,16 @@
status = "disabled";
};
+ toacodec: audio-controller@740 {
+ compatible = "amlogic,sm1-toacodec",
+ "amlogic,g12a-toacodec";
+ reg = <0x0 0x740 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOACODEC";
+ resets = <&clkc_audio AUD_RESET_TOACODEC>;
+ status = "disabled";
+ };
+
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";
diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi
index 1cc7fdcec5..8e7a66943b 100644
--- a/dts/src/arm64/arm/juno-base.dtsi
+++ b/dts/src/arm64/arm/juno-base.dtsi
@@ -568,13 +568,13 @@
clocks {
compatible = "arm,scpi-clocks";
- scpi_dvfs: scpi-dvfs {
+ scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
};
- scpi_clk: scpi-clk {
+ scpi_clk: clocks-1 {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>;
@@ -582,7 +582,7 @@
};
};
- scpi_devpd: scpi-power-domains {
+ scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
diff --git a/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi b/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi
index 4f7220b11f..2ad9fd7c94 100644
--- a/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi
+++ b/dts/src/arm64/arm/vexpress-v2m-rs1.dtsi
@@ -144,7 +144,7 @@
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
- port1-otg;
+ dr_mode = "peripheral";
};
iofpga-bus@300000000 {
diff --git a/dts/src/arm64/broadcom/bcm2711-rpi-400.dts b/dts/src/arm64/broadcom/bcm2711-rpi-400.dts
new file mode 100644
index 0000000000..b9000f58be
--- /dev/null
+++ b/dts/src/arm64/broadcom/bcm2711-rpi-400.dts
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "arm/bcm2711-rpi-400.dts"
diff --git a/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi b/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi
index 8060178b36..a5a64d17d9 100644
--- a/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi
+++ b/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi
@@ -306,7 +306,7 @@
interrupt-names = "nand";
status = "okay";
- nandcs: nandcs@0 {
+ nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
};
diff --git a/dts/src/arm64/broadcom/stingray/stingray.dtsi b/dts/src/arm64/broadcom/stingray/stingray.dtsi
index 2ffb2c9218..7b04dfe67b 100644
--- a/dts/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/dts/src/arm64/broadcom/stingray/stingray.dtsi
@@ -470,7 +470,7 @@
status = "disabled";
};
- uart0: uart@100000 {
+ uart0: serial@100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
@@ -481,7 +481,7 @@
status = "disabled";
};
- uart1: uart@110000 {
+ uart1: serial@110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
@@ -492,7 +492,7 @@
status = "disabled";
};
- uart2: uart@120000 {
+ uart2: serial@120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
@@ -503,7 +503,7 @@
status = "disabled";
};
- uart3: uart@130000 {
+ uart3: serial@130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
diff --git a/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi b/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
index 773d9abe3a..cbcc01a66a 100644
--- a/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
+++ b/dts/src/arm64/exynos/exynos5433-tm2-common.dtsi
@@ -391,6 +391,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
reg = <0x66>;
samsung,s2mps11-wrstbi-ground;
+ wakeup-source;
s2mps13_osc: clocks {
compatible = "samsung,s2mps13-clk";
diff --git a/dts/src/arm64/freescale/fsl-ls1012a-frwy.dts b/dts/src/arm64/freescale/fsl-ls1012a-frwy.dts
index 6290e2f9de..e8562585d4 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a-frwy.dts
+++ b/dts/src/arm64/freescale/fsl-ls1012a-frwy.dts
@@ -24,6 +24,10 @@
status = "okay";
};
+&pcie1 {
+ status = "okay";
+};
+
&qspi {
status = "okay";
diff --git a/dts/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
index 9058cfa498..50a72cda47 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -238,35 +238,35 @@
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x60000 0x100 0x60e00 0x18>;
+ reg = <0x60000 0x100>, <0x60e00 0x18>;
ranges = <0x0 0x60100 0x500>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x00 0x20 0x100 0x100>;
+ reg = <0x00 0x20>, <0x100 0x100>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x20 0x20 0x200 0x100>;
+ reg = <0x20 0x20>, <0x200 0x100>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x40 0x20 0x300 0x100>;
+ reg = <0x40 0x20>, <0x300 0x100>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x60 0x20 0x400 0x100>;
+ reg = <0x60 0x20>, <0x400 0x100>;
};
};
};
@@ -522,8 +522,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1012a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
diff --git a/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts
index 9322c6ad8e..d7b5272725 100644
--- a/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts
@@ -275,6 +275,10 @@
status = "okay";
};
+&optee {
+ status = "okay";
+};
+
&sai4 {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi
index a30249ebff..b2e3e5d2a1 100644
--- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi
@@ -88,7 +88,7 @@
};
firmware {
- optee {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
@@ -617,8 +617,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
@@ -644,8 +644,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,19 +990,19 @@
msi-map = <0 &its 0x17 0xe>;
iommu-map = <0 &smmu 0x17 0xe>;
/* PF0-6 BAR0 - non-prefetchable memory */
- ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
+ ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
/* PF0-6 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
+ 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
/* PF0: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
+ 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
/* PF0: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
+ 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
+ 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
/* PF1: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
+ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
+ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
index 28c51e521c..01b01e3204 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -869,8 +869,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
@@ -895,8 +895,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 128 0x4>,
<0 127 0x4>;
@@ -921,8 +921,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 162 0x4>,
<0 161 0x4>;
diff --git a/dts/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
index 39458305e3..687fea6d8a 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -773,8 +773,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -799,8 +799,8 @@
pcie_ep1: pcie_ep@3400000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x40 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -809,8 +809,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -835,8 +835,8 @@
pcie_ep2: pcie_ep@3500000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x48 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -845,8 +845,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -871,8 +871,8 @@
pcie_ep3: pcie_ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x50 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
index 8ffbc9fde0..2fa6cfbef0 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -536,8 +536,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -562,8 +562,8 @@
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x20 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <24>;
num-ob-windows = <256>;
@@ -573,8 +573,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -599,8 +599,8 @@
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x28 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
@@ -609,8 +609,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -635,8 +635,8 @@
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x30 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
diff --git a/dts/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
index 76ab68d2de..6f6667b700 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
@@ -120,32 +120,32 @@
};
&pcie1 {
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie2 {
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie3 {
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie4 {
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/dts/src/arm64/freescale/fsl-ls2088a.dtsi b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
index da24dc1276..c3dc38188c 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
@@ -121,8 +121,8 @@
&pcie1 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
@@ -130,8 +130,8 @@
&pcie2 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
@@ -139,8 +139,8 @@
&pcie3 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
@@ -148,8 +148,8 @@
&pcie4 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x38 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
diff --git a/dts/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
index 135ac82108..801ba9612d 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -929,7 +929,6 @@
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "dspi";
spi-num-chipselects = <5>;
- bus-num = <0>;
};
esdhc: esdhc@2140000 {
diff --git a/dts/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
index 0551f6f4c3..c4b1a59ba4 100644
--- a/dts/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -1089,8 +1089,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1117,8 +1117,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1145,8 +1145,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1173,8 +1173,8 @@
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1201,8 +1201,8 @@
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
+ <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1229,8 +1229,8 @@
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
+ <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
diff --git a/dts/src/arm64/freescale/imx8-ss-conn.dtsi b/dts/src/arm64/freescale/imx8-ss-conn.dtsi
index e1e81ca0ca..a79f42a961 100644
--- a/dts/src/arm64/freescale/imx8-ss-conn.dtsi
+++ b/dts/src/arm64/freescale/imx8-ss-conn.dtsi
@@ -77,9 +77,12 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&enet0_lpcg IMX_LPCG_CLK_2>,
- <&enet0_lpcg IMX_LPCG_CLK_1>,
+ <&enet0_lpcg IMX_LPCG_CLK_3>,
<&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
@@ -94,9 +97,12 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&enet1_lpcg IMX_LPCG_CLK_2>,
- <&enet1_lpcg IMX_LPCG_CLK_1>,
+ <&enet1_lpcg IMX_LPCG_CLK_3>,
<&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
@@ -152,15 +158,19 @@ conn_subsys: bus@5b000000 {
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet0_ipg_root_clk",
- "enet0_tx_clk",
- "enet0_ahb_clk",
- "enet0_ipg_clk",
- "enet0_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet0_lpcg_timer_clk",
+ "enet0_lpcg_txc_sampling_clk",
+ "enet0_lpcg_ahb_clk",
+ "enet0_lpcg_rgmii_txc_clk",
+ "enet0_lpcg_ipg_clk",
+ "enet0_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_0>;
};
@@ -170,15 +180,19 @@ conn_subsys: bus@5b000000 {
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet1_ipg_root_clk",
- "enet1_tx_clk",
- "enet1_ahb_clk",
- "enet1_ipg_clk",
- "enet1_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet1_lpcg_timer_clk",
+ "enet1_lpcg_txc_sampling_clk",
+ "enet1_lpcg_ahb_clk",
+ "enet1_lpcg_rgmii_txc_clk",
+ "enet1_lpcg_ipg_clk",
+ "enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
};
diff --git a/dts/src/arm64/freescale/imx8mm-evk.dtsi b/dts/src/arm64/freescale/imx8mm-evk.dtsi
index 6518f088b2..e033d0257b 100644
--- a/dts/src/arm64/freescale/imx8mm-evk.dtsi
+++ b/dts/src/arm64/freescale/imx8mm-evk.dtsi
@@ -314,6 +314,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts
new file mode 100644
index 0000000000..5a1e9df39b
--- /dev/null
+++ b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts
@@ -0,0 +1,1019 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7901 i.MX8MM board";
+ compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
+ ethernet3 = &lan3;
+ ethernet4 = &lan4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led01_red";
+ gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led02_red";
+ gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led03_red";
+ gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led04_red";
+ gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led05_red";
+ gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-a {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator-ioexp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_ioexp>;
+ compatible = "regulator-fixed";
+ regulator-name = "ioexp";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator-isouart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_isouart>;
+ compatible = "regulator-fixed";
+ regulator-name = "iso_uart";
+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_usb2_vbus";
+ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ status = "okay";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin_aux1";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vin_aux2";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_0p95";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_soc";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_arm";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p8";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p2";
+ };
+
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ leds_gpio: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ switch: switch@5f {
+ compatible = "microchip,ksz9897";
+ reg = <0x5f>;
+ pinctrl-0 = <&pinctrl_ksz>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ phy-mode = "rgmii-id";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1: port@0 {
+ reg = <0>;
+ label = "lan1";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan2: port@1 {
+ reg = <1>;
+ label = "lan2";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan3: port@2 {
+ reg = <2>;
+ label = "lan3";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan4: port@3 {
+ reg = <3>;
+ label = "lan4";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ crypto@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
+ cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <&reg_wifi>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_ksz: kszgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
+ >;
+ };
+
+ pinctrl_reg_isouart: regisouartgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
+ >;
+ };
+
+ pinctrl_reg_ioexp: regioexpgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
+ >;
+ };
+
+ pinctrl_reg_usb2: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41
+ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
+ >;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
+ >;
+ };
+
+ pinctrl_uart4_gpio: uart4gpiogrp {
+ fsl,pins = <
+
+ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+};
diff --git a/dts/src/arm64/freescale/imx8mm.dtsi b/dts/src/arm64/freescale/imx8mm.dtsi
index a27e02bee6..e7648c3b83 100644
--- a/dts/src/arm64/freescale/imx8mm.dtsi
+++ b/dts/src/arm64/freescale/imx8mm.dtsi
@@ -261,6 +261,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mm_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -271,117 +272,125 @@
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
- sai1: sai@30010000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30010000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
- <&clk IMX8MM_CLK_SAI1_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ spba2: spba-bus@30000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x100000>;
+ ranges;
+
+ sai1: sai@30010000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30010000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
+ <&clk IMX8MM_CLK_SAI1_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai2: sai@30020000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30020000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
- <&clk IMX8MM_CLK_SAI2_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai2: sai@30020000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30020000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
+ <&clk IMX8MM_CLK_SAI2_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai3: sai@30030000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30030000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
- <&clk IMX8MM_CLK_SAI3_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai3: sai@30030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30030000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
+ <&clk IMX8MM_CLK_SAI3_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai5: sai@30050000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30050000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
- <&clk IMX8MM_CLK_SAI5_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai5: sai@30050000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30050000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+ <&clk IMX8MM_CLK_SAI5_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai6: sai@30060000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30060000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
- <&clk IMX8MM_CLK_SAI6_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai6: sai@30060000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30060000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
+ <&clk IMX8MM_CLK_SAI6_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- micfil: audio-controller@30080000 {
- compatible = "fsl,imx8mm-micfil";
- reg = <0x30080000 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_PDM_IPG>,
- <&clk IMX8MM_CLK_PDM_ROOT>,
- <&clk IMX8MM_AUDIO_PLL1_OUT>,
- <&clk IMX8MM_AUDIO_PLL2_OUT>,
- <&clk IMX8MM_CLK_EXT3>;
- clock-names = "ipg_clk", "ipg_clk_app",
- "pll8k", "pll11k", "clkext3";
- dmas = <&sdma2 24 25 0x80000000>;
- dma-names = "rx";
- status = "disabled";
- };
+ micfil: audio-controller@30080000 {
+ compatible = "fsl,imx8mm-micfil";
+ reg = <0x30080000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PDM_IPG>,
+ <&clk IMX8MM_CLK_PDM_ROOT>,
+ <&clk IMX8MM_AUDIO_PLL1_OUT>,
+ <&clk IMX8MM_AUDIO_PLL2_OUT>,
+ <&clk IMX8MM_CLK_EXT3>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "pll11k", "clkext3";
+ dmas = <&sdma2 24 25 0x80000000>;
+ dma-names = "rx";
+ status = "disabled";
+ };
- spdif1: spdif@30090000 {
- compatible = "fsl,imx35-spdif";
- reg = <0x30090000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
- <&clk IMX8MM_CLK_24M>, /* rxtx0 */
- <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
- <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
- <&clk IMX8MM_CLK_DUMMY>; /* spba */
- clock-names = "core", "rxtx0",
- "rxtx1", "rxtx2",
- "rxtx3", "rxtx4",
- "rxtx5", "rxtx6",
- "rxtx7", "spba";
- dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
- dma-names = "rx", "tx";
- status = "disabled";
+ spdif1: spdif@30090000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x30090000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */
+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MM_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
};
gpio1: gpio@30200000 {
@@ -670,80 +679,88 @@
ranges = <0x30800000 0x30800000 0x400000>,
<0x8000000 0x8000000 0x10000000>;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
- <&clk IMX8MM_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
+
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
- <&clk IMX8MM_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
- <&clk IMX8MM_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
- <&clk IMX8MM_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+ <&clk IMX8MM_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
- <&clk IMX8MM_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+ <&clk IMX8MM_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
- <&clk IMX8MM_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+ <&clk IMX8MM_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi b/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi
index c35eeaff95..54eaf3d605 100644
--- a/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi
+++ b/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi
@@ -120,6 +120,9 @@
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
diff --git a/dts/src/arm64/freescale/imx8mn-evk.dtsi b/dts/src/arm64/freescale/imx8mn-evk.dtsi
index a0dddba2e5..85e65f8719 100644
--- a/dts/src/arm64/freescale/imx8mn-evk.dtsi
+++ b/dts/src/arm64/freescale/imx8mn-evk.dtsi
@@ -193,6 +193,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi
index 4dac4da38f..d4231e0614 100644
--- a/dts/src/arm64/freescale/imx8mn.dtsi
+++ b/dts/src/arm64/freescale/imx8mn.dtsi
@@ -245,6 +245,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -255,7 +256,7 @@
#size-cells = <1>;
ranges;
- spba: spba-bus@30000000 {
+ spba2: spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -681,80 +682,88 @@
#size-cells = <1>;
ranges;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
- <&clk IMX8MN_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
- <&clk IMX8MN_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
- <&clk IMX8MN_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
- <&clk IMX8MN_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
- <&clk IMX8MN_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+ <&clk IMX8MN_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
- <&clk IMX8MN_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+ <&clk IMX8MN_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+ <&clk IMX8MN_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/dts/src/arm64/freescale/imx8mp-evk.dts b/dts/src/arm64/freescale/imx8mp-evk.dts
index 2c28e58967..7b99fad6e4 100644
--- a/dts/src/arm64/freescale/imx8mp-evk.dts
+++ b/dts/src/arm64/freescale/imx8mp-evk.dts
@@ -81,6 +81,26 @@
status = "disabled";/* can2 pin conflict with pdm */
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
@@ -104,6 +124,92 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1045000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -177,6 +283,26 @@
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
@@ -229,6 +355,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
@@ -236,6 +369,12 @@
>;
};
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
diff --git a/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi b/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi
index f3965ec5b3..aa78e0d8c7 100644
--- a/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi
+++ b/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi
@@ -65,6 +65,20 @@
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ som_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -217,6 +231,17 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi
index c2d51a46cb..9f7c7f587d 100644
--- a/dts/src/arm64/freescale/imx8mp.dtsi
+++ b/dts/src/arm64/freescale/imx8mp.dtsi
@@ -37,6 +37,7 @@
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
+ spi0 = &flexspi;
};
cpus {
@@ -407,7 +408,6 @@
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
- <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
@@ -423,7 +423,6 @@
<500000000>,
<400000000>,
<800000000>,
- <400000000>,
<393216000>,
<361267200>;
};
@@ -761,6 +760,21 @@
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ compatible = "nxp,imx8mp-fspi";
+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+ <&clk IMX8MP_CLK_QSPI_ROOT>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
diff --git a/dts/src/arm64/freescale/imx8mq-evk.dts b/dts/src/arm64/freescale/imx8mq-evk.dts
index 85b045253a..4d2035e3dd 100644
--- a/dts/src/arm64/freescale/imx8mq-evk.dts
+++ b/dts/src/arm64/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ vph-supply = <&vgen5_reg>;
status = "okay";
};
diff --git a/dts/src/arm64/freescale/imx8mq-nitrogen.dts b/dts/src/arm64/freescale/imx8mq-nitrogen.dts
index 81d2692966..f70fb32b96 100644
--- a/dts/src/arm64/freescale/imx8mq-nitrogen.dts
+++ b/dts/src/arm64/freescale/imx8mq-nitrogen.dts
@@ -34,6 +34,30 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ ddc-i2c-bus = <&ddc_i2c_bus>;
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&lt8912_out>;
+ };
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
@@ -70,6 +94,9 @@
};
};
+&dphy {
+ status = "okay";
+};
&fec1 {
pinctrl-names = "default";
@@ -91,6 +118,15 @@
};
};
+/* Release reset of the USB Host HUB */
+&gpio1 {
+ usb-host-reset-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -174,6 +210,98 @@
};
};
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pca9546: i2cmux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c4@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+ };
+
+ ddc_i2c_bus: i2c4@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ max7323: gpio-expander@68 {
+ compatible = "maxim,max7323";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7323>;
+ gpio-controller;
+ reg = <0x68>;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&hdmi_out_in>;
+ };
+ };
+ };
+};
+
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -190,6 +318,29 @@
status = "okay";
};
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_0>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+ status = "okay";
+};
+
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
@@ -321,6 +472,19 @@
>;
};
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_max7323: max7323grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
+ >;
+ };
+
pinctrl_reg_arm_dram: reg-arm-dramgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
@@ -339,6 +503,12 @@
>;
};
+ pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
@@ -353,6 +523,18 @@
>;
};
+ pinctrl_usb3_0: usb3-0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
+ >;
+ };
+
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi
index 17c449e12c..91df9c5350 100644
--- a/dts/src/arm64/freescale/imx8mq.dtsi
+++ b/dts/src/arm64/freescale/imx8mq.dtsi
@@ -1383,6 +1383,14 @@
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
@@ -1413,6 +1421,14 @@
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
diff --git a/dts/src/arm64/hisilicon/hi3660-coresight.dtsi b/dts/src/arm64/hisilicon/hi3660-coresight.dtsi
index d607f2f669..79a55a0fa2 100644
--- a/dts/src/arm64/hisilicon/hi3660-coresight.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660-coresight.dtsi
@@ -3,7 +3,7 @@
/*
* dtsi for Hisilicon Hi3660 Coresight
*
- * Copyright (C) 2016-2018 Hisilicon Ltd.
+ * Copyright (C) 2016-2018 HiSilicon Ltd.
*
* Author: Wanglai Shi <shiwanglai@hisilicon.com>
*
diff --git a/dts/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
index 963300eede..f68580dc87 100644
--- a/dts/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey960 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*
*/
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index cab89dc6f5..f1ec87c058 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3660 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/src/arm64/hisilicon/hi3670-hikey970.dts b/dts/src/arm64/hisilicon/hi3670-hikey970.dts
index 7f9f9886c3..d8abf442ee 100644
--- a/dts/src/arm64/hisilicon/hi3670-hikey970.dts
+++ b/dts/src/arm64/hisilicon/hi3670-hikey970.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey970 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*
*/
diff --git a/dts/src/arm64/hisilicon/hi3670.dtsi b/dts/src/arm64/hisilicon/hi3670.dtsi
index 8830795c8e..20698cfd06 100644
--- a/dts/src/arm64/hisilicon/hi3670.dtsi
+++ b/dts/src/arm64/hisilicon/hi3670.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3670 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*/
diff --git a/dts/src/arm64/hisilicon/hi6220-coresight.dtsi b/dts/src/arm64/hisilicon/hi6220-coresight.dtsi
index 7b3010f448..3f387f4cf5 100644
--- a/dts/src/arm64/hisilicon/hi6220-coresight.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220-coresight.dtsi
@@ -2,7 +2,7 @@
/*
* dtsi file for Hisilicon Hi6220 coresight
*
- * Copyright (C) 2017 Hisilicon Ltd.
+ * Copyright (C) 2017 HiSilicon Ltd.
*
* Author: Pengcheng Li <lipengcheng8@huawei.com>
* Leo Yan <leo.yan@linaro.org>
diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts
index 91d08673c0..3df2afb2f6 100644
--- a/dts/src/arm64/hisilicon/hi6220-hikey.dts
+++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey Development Board
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*
*/
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi
index d426c6c872..dde9371dc5 100644
--- a/dts/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi6220 SoC
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/src/arm64/hisilicon/hip05-d02.dts b/dts/src/arm64/hisilicon/hip05-d02.dts
index 369b69b17b..40f3e00ac8 100644
--- a/dts/src/arm64/hisilicon/hip05-d02.dts
+++ b/dts/src/arm64/hisilicon/hip05-d02.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/dts/src/arm64/hisilicon/hip05.dtsi b/dts/src/arm64/hisilicon/hip05.dtsi
index 4aed8d440b..7b2abd10d3 100644
--- a/dts/src/arm64/hisilicon/hip05.dtsi
+++ b/dts/src/arm64/hisilicon/hip05.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/src/arm64/hisilicon/hip06-d03.dts b/dts/src/arm64/hisilicon/hip06-d03.dts
index 9f4a930e73..35af5d3821 100644
--- a/dts/src/arm64/hisilicon/hip06-d03.dts
+++ b/dts/src/arm64/hisilicon/hip06-d03.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/dts/src/arm64/hisilicon/hip06.dtsi b/dts/src/arm64/hisilicon/hip06.dtsi
index 7deca5f763..70d7732dd3 100644
--- a/dts/src/arm64/hisilicon/hip06.dtsi
+++ b/dts/src/arm64/hisilicon/hip06.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/src/arm64/hisilicon/hip07-d05.dts b/dts/src/arm64/hisilicon/hip07-d05.dts
index 81a2312c8a..c3df67845f 100644
--- a/dts/src/arm64/hisilicon/hip07-d05.dts
+++ b/dts/src/arm64/hisilicon/hip07-d05.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/dts/src/arm64/hisilicon/hip07.dtsi b/dts/src/arm64/hisilicon/hip07.dtsi
index 2172d80711..6baf6a6864 100644
--- a/dts/src/arm64/hisilicon/hip07.dtsi
+++ b/dts/src/arm64/hisilicon/hip07.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/src/arm64/marvell/armada-3720-turris-mox.dts b/dts/src/arm64/marvell/armada-3720-turris-mox.dts
index 53e817c5f6..ce2bcddf39 100644
--- a/dts/src/arm64/marvell/armada-3720-turris-mox.dts
+++ b/dts/src/arm64/marvell/armada-3720-turris-mox.dts
@@ -109,10 +109,8 @@
};
firmware {
- turris-mox-rwtm {
- compatible = "cznic,turris-mox-rwtm";
- mboxes = <&rwtm 0>;
- status = "okay";
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
};
};
};
diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi
index 456dcd4a77..5db81a416c 100644
--- a/dts/src/arm64/marvell/armada-37xx.dtsi
+++ b/dts/src/arm64/marvell/armada-37xx.dtsi
@@ -134,7 +134,7 @@
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
- reg = <0x12000 0x200>;
+ reg = <0x12000 0x18>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -504,4 +504,12 @@
};
};
};
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware";
+ mboxes = <&rwtm 0>;
+ status = "okay";
+ };
+ };
};
diff --git a/dts/src/arm64/marvell/armada-ap807.dtsi b/dts/src/arm64/marvell/armada-ap807.dtsi
index d9bbbfa4b4..4a23f65d47 100644
--- a/dts/src/arm64/marvell/armada-ap807.dtsi
+++ b/dts/src/arm64/marvell/armada-ap807.dtsi
@@ -29,6 +29,7 @@
};
&ap_sdhci0 {
- compatible = "marvell,armada-ap807-sdhci";
+ compatible = "marvell,armada-ap807-sdhci",
+ "marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
diff --git a/dts/src/arm64/marvell/cn9130-db.dts b/dts/src/arm64/marvell/cn9130-db.dts
index 2c2af00161..9758609541 100644
--- a/dts/src/arm64/marvell/cn9130-db.dts
+++ b/dts/src/arm64/marvell/cn9130-db.dts
@@ -260,7 +260,7 @@
};
partition@200000 {
label = "Linux";
- reg = <0x200000 0xd00000>;
+ reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
diff --git a/dts/src/arm64/mediatek/mt8167.dtsi b/dts/src/arm64/mediatek/mt8167.dtsi
index 1c5639ead6..9029051624 100644
--- a/dts/src/arm64/mediatek/mt8167.dtsi
+++ b/dts/src/arm64/mediatek/mt8167.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
+#include <dt-bindings/power/mt8167-power.h>
#include "mt8167-pinfunc.h"
@@ -34,6 +35,73 @@
#clock-cells = <1>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8167-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT8167_POWER_DOMAIN_MM {
+ reg = <MT8167_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_VDEC {
+ reg = <MT8167_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>,
+ <&topckgen CLK_TOP_RG_VDEC>;
+ clock-names = "mm", "vdec";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_ISP {
+ reg = <MT8167_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
+ <&topckgen CLK_TOP_RG_SLOW_MFG>;
+ clock-names = "axi_mfg", "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,infracfg = <&infracfg>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_2D {
+ reg = <MT8167_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG {
+ reg = <MT8167_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_CONN {
+ reg = <MT8167_POWER_DOMAIN_CONN>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -57,5 +125,58 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ mmsys: mmsys@14000000 {
+ compatible = "mediatek,mt8167-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi@14017000 {
+ compatible = "mediatek,mt8167-smi-common";
+ reg = <0 0x14017000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb0: larb@14016000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x14016000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb1: larb@15001000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB1_SMI>,
+ <&imgsys CLK_IMG_LARB1_SMI>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
+ };
+
+ larb2: larb@16010000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
+ };
+
+ iommu: m4u@10203000 {
+ compatible = "mediatek,mt8167-m4u";
+ reg = <0 0x10203000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+ #iommu-cells = <1>;
+ };
};
};
diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi
index 003a5653c5..22f271b1f5 100644
--- a/dts/src/arm64/mediatek/mt8173.dtsi
+++ b/dts/src/arm64/mediatek/mt8173.dtsi
@@ -1459,14 +1459,11 @@
clock-names = "apb", "smi";
};
- vcodec_enc: vcodec@18002000 {
+ vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+ reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1477,29 +1474,12 @@
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
- <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
jpegdec: jpegdec@18004000 {
@@ -1531,5 +1511,27 @@
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";
};
+
+ vcodec_enc_vp8: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-enc-vp8";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents =
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ };
};
};
diff --git a/dts/src/arm64/mediatek/mt8183-evb.dts b/dts/src/arm64/mediatek/mt8183-evb.dts
index edff1e03e6..7bc0a6a7fa 100644
--- a/dts/src/arm64/mediatek/mt8183-evb.dts
+++ b/dts/src/arm64/mediatek/mt8183-evb.dts
@@ -42,6 +42,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts
new file mode 100644
index 0000000000..a8d6f32ade
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google burnet board";
+ compatible = "google,burnet", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c0 {
+ touchscreen@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+ post-power-on-delay-ms = <200>;
+ hid-descr-addr = <0x0020>;
+ };
+};
+
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
new file mode 100644
index 0000000000..ef6257c9a2
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku1 board";
+ compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
+
+ pwmleds {
+ compatible = "pwm-leds";
+ keyboard_backlight: keyboard-backlight {
+ label = "cros_ec::kbd_backlight";
+ pwms = <&cros_ec_pwm 0>;
+ max-brightness = <1023>;
+ };
+ };
+};
+
+&cros_ec_pwm {
+ status = "okay";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
new file mode 100644
index 0000000000..899c2e4238
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku6 board";
+ compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
new file mode 100644
index 0000000000..bbe6c338f4
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
new file mode 100644
index 0000000000..e8c41f6b4b
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel14 sku0 board";
+ compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
new file mode 100644
index 0000000000..b3f46c16e5
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google kappa board";
+ compatible = "google,kappa", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
new file mode 100644
index 0000000000..6f1aa69275
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-juniper.dtsi"
+
+/ {
+ model = "Google kenzo sku17 board";
+ compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
new file mode 100644
index 0000000000..281265f082
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku0";
+ compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
+};
+
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
new file mode 100644
index 0000000000..22e56bdc1e
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku1";
+ compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
new file mode 100644
index 0000000000..76d3354016
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_JUNIPER";
+};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 4049dff846..d8826c82bc 100644
--- a/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/dts/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -92,6 +92,14 @@
};
};
+&cros_ec {
+ cros_ec_pwm: ec-pwm {
+ compatible = "google,cros-ec-pwm";
+ #pwm-cells = <1>;
+ status = "disabled";
+ };
+};
+
&dsi0 {
status = "okay";
/delete-node/panel@0;
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
index b442e38a31..28966a6539 100644
--- a/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
@@ -88,11 +88,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -101,11 +103,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
index 2f5234a16e..3aa79403c0 100644
--- a/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
+++ b/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
@@ -62,11 +62,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c64";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcamio_reg>;
};
};
@@ -75,11 +77,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi
index fbc471ccf8..30c183c96a 100644
--- a/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi
+++ b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi
@@ -71,11 +71,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -84,11 +86,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/dts/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/src/arm64/mediatek/mt8183-kukui.dtsi
index ff56bcfa33..ae549d55a9 100644
--- a/dts/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/dts/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -279,6 +279,11 @@
};
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -816,6 +821,10 @@
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
};
+
+ cbas {
+ compatible = "google,cros-cbas";
+ };
};
};
@@ -847,6 +856,20 @@
status = "okay";
};
+&thermal_zones {
+ tboard1 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor1>;
+ };
+
+ tboard2 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor2>;
+ };
+};
+
&u3phy {
status = "okay";
};
diff --git a/dts/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/src/arm64/mediatek/mt8183-pumpkin.dts
index 0aff5eb52e..ee912825cf 100644
--- a/dts/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/dts/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -68,6 +68,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/dts/src/arm64/mediatek/mt8183.dtsi b/dts/src/arm64/mediatek/mt8183.dtsi
index c5e822b6b7..f90df6439c 100644
--- a/dts/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/src/arm64/mediatek/mt8183.dtsi
@@ -197,6 +197,91 @@
};
};
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <625000>, <850000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <631250>, <850000>;
+ };
+
+ opp-340000000 {
+ opp-hz = /bits/ 64 <340000000>;
+ opp-microvolt = <637500>, <850000>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <643750>, <850000>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-microvolt = <650000>, <850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <656250>, <850000>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <662500>, <850000>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ opp-microvolt = <675000>, <850000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <687500>, <850000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <700000>, <850000>;
+ };
+
+ opp-580000000 {
+ opp-hz = /bits/ 64 <580000000>;
+ opp-microvolt = <712500>, <850000>;
+ };
+
+ opp-620000000 {
+ opp-hz = /bits/ 64 <620000000>;
+ opp-microvolt = <725000>, <850000>;
+ };
+
+ opp-653000000 {
+ opp-hz = /bits/ 64 <653000000>;
+ opp-microvolt = <743750>, <850000>;
+ };
+
+ opp-698000000 {
+ opp-hz = /bits/ 64 <698000000>;
+ opp-microvolt = <768750>, <868750>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <793750>, <893750>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <825000>, <925000>;
+ };
+ };
+
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
@@ -673,7 +758,7 @@
nvmem-cell-names = "calibration-data";
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
@@ -1118,6 +1203,26 @@
#clock-cells = <1>;
};
+ gpu: gpu@13040000 {
+ compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+ interrupts =
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+
+ power-domains =
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
+ <&spm MT8183_POWER_DOMAIN_MFG_2D>;
+ power-domain-names = "core0", "core1", "core2";
+
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
@@ -1263,13 +1368,14 @@
};
smi_common: smi@14019000 {
- compatible = "mediatek,mt8183-smi-common", "syscon";
+ compatible = "mediatek,mt8183-smi-common";
reg = <0 0x14019000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
imgsys: syscon@15020000 {
diff --git a/dts/src/arm64/microchip/sparx5.dtsi b/dts/src/arm64/microchip/sparx5.dtsi
index d64621d121..ad07fff405 100644
--- a/dts/src/arm64/microchip/sparx5.dtsi
+++ b/dts/src/arm64/microchip/sparx5.dtsi
@@ -135,9 +135,12 @@
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@600100000 {
@@ -275,6 +278,21 @@
"GPIO_46", "GPIO_47";
function = "emmc";
};
+
+ miim1_pins: miim1-pins {
+ pins = "GPIO_56", "GPIO_57";
+ function = "miim";
+ };
+
+ miim2_pins: miim2-pins {
+ pins = "GPIO_58", "GPIO_59";
+ function = "miim";
+ };
+
+ miim3_pins: miim3-pins {
+ pins = "GPIO_52", "GPIO_53";
+ function = "miim";
+ };
};
sgpio0: gpio@61101036c {
@@ -285,6 +303,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio0_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x1101036c 0x100>;
sgpio_in0: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -292,6 +312,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out0: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -310,6 +333,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio1_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x11010484 0x100>;
sgpio_in1: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -317,6 +342,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out1: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -335,6 +363,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio2_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x1101059c 0x100>;
sgpio_in2: gpio@0 {
reg = <0>;
@@ -342,6 +372,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out2: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -386,5 +419,62 @@
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ mdio0: mdio@6110102b0 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102b0 0x24>;
+ };
+
+ mdio1: mdio@6110102d4 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim1_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102d4 0x24>;
+ };
+
+ mdio2: mdio@6110102f8 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim2_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102d4 0x24>;
+ };
+
+ mdio3: mdio@61101031c {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim3_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x1101031c 0x24>;
+ };
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d0000>;
+ };
+
+ switch: switch@0x600000000 {
+ compatible = "microchip,sparx5-switch";
+ reg = <0x6 0 0x401000>,
+ <0x6 0x10004000 0x7fc000>,
+ <0x6 0x11010000 0xaf0000>;
+ reg-names = "cpu", "dev", "gcb";
+ interrupt-names = "xtr";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ };
};
};
diff --git a/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi b/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi
index f0c9151609..33faf1f326 100644
--- a/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi
+++ b/dts/src/arm64/microchip/sparx5_pcb134_board.dtsi
@@ -7,30 +7,6 @@
#include "sparx5_pcb_common.dtsi"
/{
- aliases {
- i2c0 = &i2c0;
- i2c100 = &i2c100;
- i2c101 = &i2c101;
- i2c102 = &i2c102;
- i2c103 = &i2c103;
- i2c104 = &i2c104;
- i2c105 = &i2c105;
- i2c106 = &i2c106;
- i2c107 = &i2c107;
- i2c108 = &i2c108;
- i2c109 = &i2c109;
- i2c110 = &i2c110;
- i2c111 = &i2c111;
- i2c112 = &i2c112;
- i2c113 = &i2c113;
- i2c114 = &i2c114;
- i2c115 = &i2c115;
- i2c116 = &i2c116;
- i2c117 = &i2c117;
- i2c118 = &i2c118;
- i2c119 = &i2c119;
- };
-
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
@@ -298,17 +274,10 @@
&spi0 {
status = "okay";
- spi@0 {
- compatible = "spi-mux";
- mux-controls = <&mux>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>; /* CS0 */
- spi-flash@9 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <8000000>;
- reg = <0x9>; /* SPI */
- };
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
};
};
@@ -328,6 +297,33 @@
};
};
+&sgpio0 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <8 15>;
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&sgpio1 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <24 31>;
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&sgpio2 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <0 0>, <11 31>;
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
@@ -415,9 +411,9 @@
&i2c0_imux {
pinctrl-names =
- "i2c100", "i2c101", "i2c102", "i2c103",
- "i2c104", "i2c105", "i2c106", "i2c107",
- "i2c108", "i2c109", "i2c110", "i2c111", "idle";
+ "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
+ "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8",
+ "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
@@ -431,62 +427,62 @@
pinctrl-10 = <&i2cmux_10>;
pinctrl-11 = <&i2cmux_11>;
pinctrl-12 = <&i2cmux_pins_i>;
- i2c100: i2c_sfp1 {
+ i2c_sfp1: i2c_sfp1 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c101: i2c_sfp2 {
+ i2c_sfp2: i2c_sfp2 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c102: i2c_sfp3 {
+ i2c_sfp3: i2c_sfp3 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c103: i2c_sfp4 {
+ i2c_sfp4: i2c_sfp4 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c104: i2c_sfp5 {
+ i2c_sfp5: i2c_sfp5 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c105: i2c_sfp6 {
+ i2c_sfp6: i2c_sfp6 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c106: i2c_sfp7 {
+ i2c_sfp7: i2c_sfp7 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c107: i2c_sfp8 {
+ i2c_sfp8: i2c_sfp8 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c108: i2c_sfp9 {
+ i2c_sfp9: i2c_sfp9 {
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c109: i2c_sfp10 {
+ i2c_sfp10: i2c_sfp10 {
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c110: i2c_sfp11 {
+ i2c_sfp11: i2c_sfp11 {
reg = <0xa>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c111: i2c_sfp12 {
+ i2c_sfp12: i2c_sfp12 {
reg = <0xb>;
#address-cells = <1>;
#size-cells = <0>;
@@ -499,44 +495,413 @@
&gpio 61 GPIO_ACTIVE_HIGH
&gpio 54 GPIO_ACTIVE_HIGH>;
idle-state = <0x8>;
- i2c112: i2c_sfp13 {
+ i2c_sfp13: i2c_sfp13 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c113: i2c_sfp14 {
+ i2c_sfp14: i2c_sfp14 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c114: i2c_sfp15 {
+ i2c_sfp15: i2c_sfp15 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c115: i2c_sfp16 {
+ i2c_sfp16: i2c_sfp16 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c116: i2c_sfp17 {
+ i2c_sfp17: i2c_sfp17 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c117: i2c_sfp18 {
+ i2c_sfp18: i2c_sfp18 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c118: i2c_sfp19 {
+ i2c_sfp19: i2c_sfp19 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c119: i2c_sfp20 {
+ i2c_sfp20: i2c_sfp20 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+&mdio3 {
+ status = "ok";
+ phy64: ethernet-phy@64 {
+ reg = <28>;
+ };
+};
+
+&axi {
+ sfp_eth12: sfp-eth12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth13: sfp-eth13 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth14: sfp-eth14 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth15: sfp-eth15 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth48: sfp-eth48 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp5>;
+ tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth49: sfp-eth49 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp6>;
+ tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth50: sfp-eth50 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp7>;
+ tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth51: sfp-eth51 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp8>;
+ tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth52: sfp-eth52 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp9>;
+ tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth53: sfp-eth53 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp10>;
+ tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth54: sfp-eth54 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp11>;
+ tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth55: sfp-eth55 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp12>;
+ tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth56: sfp-eth56 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp13>;
+ tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth57: sfp-eth57 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp14>;
+ tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth58: sfp-eth58 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp15>;
+ tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth59: sfp-eth59 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp16>;
+ tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp17>;
+ tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp18>;
+ tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp19>;
+ tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp20>;
+ tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 10G SFPs */
+ port12: port@12 {
+ reg = <12>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 13>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth12>;
+ microchip,sd-sgpio = <301>;
+ managed = "in-band-status";
+ };
+ port13: port@13 {
+ reg = <13>;
+ /* Example: CU SFP, 1G speed */
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 14>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth13>;
+ microchip,sd-sgpio = <305>;
+ managed = "in-band-status";
+ };
+ port14: port@14 {
+ reg = <14>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 15>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth14>;
+ microchip,sd-sgpio = <309>;
+ managed = "in-band-status";
+ };
+ port15: port@15 {
+ reg = <15>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 16>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth15>;
+ microchip,sd-sgpio = <313>;
+ managed = "in-band-status";
+ };
+ port48: port@48 {
+ reg = <48>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 17>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth48>;
+ microchip,sd-sgpio = <317>;
+ managed = "in-band-status";
+ };
+ port49: port@49 {
+ reg = <49>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 18>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth49>;
+ microchip,sd-sgpio = <321>;
+ managed = "in-band-status";
+ };
+ port50: port@50 {
+ reg = <50>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 19>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth50>;
+ microchip,sd-sgpio = <325>;
+ managed = "in-band-status";
+ };
+ port51: port@51 {
+ reg = <51>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 20>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth51>;
+ microchip,sd-sgpio = <329>;
+ managed = "in-band-status";
+ };
+ port52: port@52 {
+ reg = <52>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 21>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth52>;
+ microchip,sd-sgpio = <333>;
+ managed = "in-band-status";
+ };
+ port53: port@53 {
+ reg = <53>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 22>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth53>;
+ microchip,sd-sgpio = <337>;
+ managed = "in-band-status";
+ };
+ port54: port@54 {
+ reg = <54>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 23>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth54>;
+ microchip,sd-sgpio = <341>;
+ managed = "in-band-status";
+ };
+ port55: port@55 {
+ reg = <55>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 24>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth55>;
+ microchip,sd-sgpio = <345>;
+ managed = "in-band-status";
+ };
+ /* 25G SFPs */
+ port56: port@56 {
+ reg = <56>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 25>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth56>;
+ microchip,sd-sgpio = <349>;
+ managed = "in-band-status";
+ };
+ port57: port@57 {
+ reg = <57>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 26>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth57>;
+ microchip,sd-sgpio = <353>;
+ managed = "in-band-status";
+ };
+ port58: port@58 {
+ reg = <58>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 27>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth58>;
+ microchip,sd-sgpio = <357>;
+ managed = "in-band-status";
+ };
+ port59: port@59 {
+ reg = <59>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 28>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth59>;
+ microchip,sd-sgpio = <361>;
+ managed = "in-band-status";
+ };
+ port60: port@60 {
+ reg = <60>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 29>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth60>;
+ microchip,sd-sgpio = <365>;
+ managed = "in-band-status";
+ };
+ port61: port@61 {
+ reg = <61>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 30>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth61>;
+ microchip,sd-sgpio = <369>;
+ managed = "in-band-status";
+ };
+ port62: port@62 {
+ reg = <62>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 31>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth62>;
+ microchip,sd-sgpio = <373>;
+ managed = "in-band-status";
+ };
+ port63: port@63 {
+ reg = <63>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 32>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth63>;
+ microchip,sd-sgpio = <377>;
+ managed = "in-band-status";
+ };
+ /* Finally the Management interface */
+ port64: port@64 {
+ reg = <64>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 0>;
+ phy-handle = <&phy64>;
+ phy-mode = "sgmii";
+ };
+ };
+};
diff --git a/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi b/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi
index e28c6dd163..ef96e6d8c6 100644
--- a/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi
+++ b/dts/src/arm64/microchip/sparx5_pcb135_board.dtsi
@@ -7,14 +7,6 @@
#include "sparx5_pcb_common.dtsi"
/{
- aliases {
- i2c0 = &i2c0;
- i2c152 = &i2c152;
- i2c153 = &i2c153;
- i2c154 = &i2c154;
- i2c155 = &i2c155;
- };
-
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
@@ -97,17 +89,10 @@
&spi0 {
status = "okay";
- spi@0 {
- compatible = "spi-mux";
- mux-controls = <&mux>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>; /* CS0 */
- spi-flash@9 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <8000000>;
- reg = <0x9>; /* SPI */
- };
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
};
};
@@ -138,6 +123,11 @@
};
};
+&sgpio2 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
+};
+
&axi {
i2c0_imux: i2c0-imux@0 {
compatible = "i2c-mux-pinctrl";
@@ -149,31 +139,614 @@
&i2c0_imux {
pinctrl-names =
- "i2c152", "i2c153", "i2c154", "i2c155",
+ "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
"idle";
pinctrl-0 = <&i2cmux_s29>;
pinctrl-1 = <&i2cmux_s30>;
pinctrl-2 = <&i2cmux_s31>;
pinctrl-3 = <&i2cmux_s32>;
pinctrl-4 = <&i2cmux_pins_i>;
- i2c152: i2c_sfp1 {
+ i2c_sfp1: i2c_sfp1 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c153: i2c_sfp2 {
+ i2c_sfp2: i2c_sfp2 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c154: i2c_sfp3 {
+ i2c_sfp3: i2c_sfp3 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c155: i2c_sfp4 {
+ i2c_sfp4: i2c_sfp4 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+&axi {
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mdio0 {
+ status = "ok";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <15>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <20>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <21>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <22>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <23>;
+ };
+};
+
+&mdio1 {
+ status = "ok";
+ phy24: ethernet-phy@24 {
+ reg = <0>;
+ };
+ phy25: ethernet-phy@25 {
+ reg = <1>;
+ };
+ phy26: ethernet-phy@26 {
+ reg = <2>;
+ };
+ phy27: ethernet-phy@27 {
+ reg = <3>;
+ };
+ phy28: ethernet-phy@28 {
+ reg = <4>;
+ };
+ phy29: ethernet-phy@29 {
+ reg = <5>;
+ };
+ phy30: ethernet-phy@30 {
+ reg = <6>;
+ };
+ phy31: ethernet-phy@31 {
+ reg = <7>;
+ };
+ phy32: ethernet-phy@32 {
+ reg = <8>;
+ };
+ phy33: ethernet-phy@33 {
+ reg = <9>;
+ };
+ phy34: ethernet-phy@34 {
+ reg = <10>;
+ };
+ phy35: ethernet-phy@35 {
+ reg = <11>;
+ };
+ phy36: ethernet-phy@36 {
+ reg = <12>;
+ };
+ phy37: ethernet-phy@37 {
+ reg = <13>;
+ };
+ phy38: ethernet-phy@38 {
+ reg = <14>;
+ };
+ phy39: ethernet-phy@39 {
+ reg = <15>;
+ };
+ phy40: ethernet-phy@40 {
+ reg = <16>;
+ };
+ phy41: ethernet-phy@41 {
+ reg = <17>;
+ };
+ phy42: ethernet-phy@42 {
+ reg = <18>;
+ };
+ phy43: ethernet-phy@43 {
+ reg = <19>;
+ };
+ phy44: ethernet-phy@44 {
+ reg = <20>;
+ };
+ phy45: ethernet-phy@45 {
+ reg = <21>;
+ };
+ phy46: ethernet-phy@46 {
+ reg = <22>;
+ };
+ phy47: ethernet-phy@47 {
+ reg = <23>;
+ };
+};
+
+&mdio3 {
+ status = "ok";
+ phy64: ethernet-phy@64 {
+ reg = <28>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy0>;
+ phy-mode = "qsgmii";
+ };
+ port1: port@1 {
+ reg = <1>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy1>;
+ phy-mode = "qsgmii";
+ };
+ port2: port@2 {
+ reg = <2>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy2>;
+ phy-mode = "qsgmii";
+ };
+ port3: port@3 {
+ reg = <3>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy3>;
+ phy-mode = "qsgmii";
+ };
+ port4: port@4 {
+ reg = <4>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy4>;
+ phy-mode = "qsgmii";
+ };
+ port5: port@5 {
+ reg = <5>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy5>;
+ phy-mode = "qsgmii";
+ };
+ port6: port@6 {
+ reg = <6>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy6>;
+ phy-mode = "qsgmii";
+ };
+ port7: port@7 {
+ reg = <7>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy7>;
+ phy-mode = "qsgmii";
+ };
+ port8: port@8 {
+ reg = <8>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy8>;
+ phy-mode = "qsgmii";
+ };
+ port9: port@9 {
+ reg = <9>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy9>;
+ phy-mode = "qsgmii";
+ };
+ port10: port@10 {
+ reg = <10>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy10>;
+ phy-mode = "qsgmii";
+ };
+ port11: port@11 {
+ reg = <11>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy11>;
+ phy-mode = "qsgmii";
+ };
+ port12: port@12 {
+ reg = <12>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy12>;
+ phy-mode = "qsgmii";
+ };
+ port13: port@13 {
+ reg = <13>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy13>;
+ phy-mode = "qsgmii";
+ };
+ port14: port@14 {
+ reg = <14>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy14>;
+ phy-mode = "qsgmii";
+ };
+ port15: port@15 {
+ reg = <15>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy15>;
+ phy-mode = "qsgmii";
+ };
+ port16: port@16 {
+ reg = <16>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy16>;
+ phy-mode = "qsgmii";
+ };
+ port17: port@17 {
+ reg = <17>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy17>;
+ phy-mode = "qsgmii";
+ };
+ port18: port@18 {
+ reg = <18>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy18>;
+ phy-mode = "qsgmii";
+ };
+ port19: port@19 {
+ reg = <19>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy19>;
+ phy-mode = "qsgmii";
+ };
+ port20: port@20 {
+ reg = <20>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy20>;
+ phy-mode = "qsgmii";
+ };
+ port21: port@21 {
+ reg = <21>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy21>;
+ phy-mode = "qsgmii";
+ };
+ port22: port@22 {
+ reg = <22>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy22>;
+ phy-mode = "qsgmii";
+ };
+ port23: port@23 {
+ reg = <23>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy23>;
+ phy-mode = "qsgmii";
+ };
+ port24: port@24 {
+ reg = <24>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ };
+ port25: port@25 {
+ reg = <25>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy25>;
+ phy-mode = "qsgmii";
+ };
+ port26: port@26 {
+ reg = <26>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy26>;
+ phy-mode = "qsgmii";
+ };
+ port27: port@27 {
+ reg = <27>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy27>;
+ phy-mode = "qsgmii";
+ };
+ port28: port@28 {
+ reg = <28>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy28>;
+ phy-mode = "qsgmii";
+ };
+ port29: port@29 {
+ reg = <29>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy29>;
+ phy-mode = "qsgmii";
+ };
+ port30: port@30 {
+ reg = <30>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy30>;
+ phy-mode = "qsgmii";
+ };
+ port31: port@31 {
+ reg = <31>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy31>;
+ phy-mode = "qsgmii";
+ };
+ port32: port@32 {
+ reg = <32>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy32>;
+ phy-mode = "qsgmii";
+ };
+ port33: port@33 {
+ reg = <33>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy33>;
+ phy-mode = "qsgmii";
+ };
+ port34: port@34 {
+ reg = <34>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy34>;
+ phy-mode = "qsgmii";
+ };
+ port35: port@35 {
+ reg = <35>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy35>;
+ phy-mode = "qsgmii";
+ };
+ port36: port@36 {
+ reg = <36>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy36>;
+ phy-mode = "qsgmii";
+ };
+ port37: port@37 {
+ reg = <37>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy37>;
+ phy-mode = "qsgmii";
+ };
+ port38: port@38 {
+ reg = <38>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy38>;
+ phy-mode = "qsgmii";
+ };
+ port39: port@39 {
+ reg = <39>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy39>;
+ phy-mode = "qsgmii";
+ };
+ port40: port@40 {
+ reg = <40>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy40>;
+ phy-mode = "qsgmii";
+ };
+ port41: port@41 {
+ reg = <41>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy41>;
+ phy-mode = "qsgmii";
+ };
+ port42: port@42 {
+ reg = <42>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy42>;
+ phy-mode = "qsgmii";
+ };
+ port43: port@43 {
+ reg = <43>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy43>;
+ phy-mode = "qsgmii";
+ };
+ port44: port@44 {
+ reg = <44>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy44>;
+ phy-mode = "qsgmii";
+ };
+ port45: port@45 {
+ reg = <45>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy45>;
+ phy-mode = "qsgmii";
+ };
+ port46: port@46 {
+ reg = <46>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy46>;
+ phy-mode = "qsgmii";
+ };
+ port47: port@47 {
+ reg = <47>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy47>;
+ phy-mode = "qsgmii";
+ };
+ /* Then the 25G interfaces */
+ port60: port@60 {
+ reg = <60>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 29>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth60>;
+ managed = "in-band-status";
+ };
+ port61: port@61 {
+ reg = <61>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 30>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth61>;
+ managed = "in-band-status";
+ };
+ port62: port@62 {
+ reg = <62>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 31>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth62>;
+ managed = "in-band-status";
+ };
+ port63: port@63 {
+ reg = <63>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 32>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth63>;
+ managed = "in-band-status";
+ };
+ /* Finally the Management interface */
+ port64: port@64 {
+ reg = <64>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 0>;
+ phy-handle = <&phy64>;
+ phy-mode = "sgmii";
+ };
+ };
+};
diff --git a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
index 683743f818..74c1a5df3f 100644
--- a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
+++ b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts
@@ -817,7 +817,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-tx2-hda";
+ nvidia,model = "NVIDIA Jetson TX2 HDA";
status = "okay";
};
@@ -1109,6 +1109,6 @@
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
<&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
- label = "jetson-tx2-ape";
+ label = "NVIDIA Jetson TX2 APE";
};
};
diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi
index 9f75bbf00c..d02f6bf3e2 100644
--- a/dts/src/arm64/nvidia/tegra186.dtsi
+++ b/dts/src/arm64/nvidia/tegra186.dtsi
@@ -1082,7 +1082,7 @@
};
smmu: iommu@12000000 {
- compatible = "arm,mmu-500";
+ compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
reg = <0 0x12000000 0 0x800000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -1152,6 +1152,8 @@
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
};
host1x@13e00000 {
diff --git a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
index d618f197a1..96bd01cadb 100644
--- a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
+++ b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts
@@ -554,7 +554,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-hda";
+ nvidia,model = "NVIDIA Jetson AGX Xavier HDA";
status = "okay";
};
@@ -831,7 +831,7 @@
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
- label = "jetson-xavier-ape";
+ label = "NVIDIA Jetson AGX Xavier APE";
widgets =
"Microphone", "CVB-RT MIC Jack",
diff --git a/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi b/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi
index d1d7722015..836a7e0a42 100644
--- a/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi
+++ b/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi
@@ -15,6 +15,577 @@
interrupt-controller@2a40000 {
status = "okay";
};
+
+ ahub@2900800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0_ep: endpoint {
+ remote-endpoint = <&admaif0_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1_ep: endpoint {
+ remote-endpoint = <&admaif1_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2_ep: endpoint {
+ remote-endpoint = <&admaif2_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3_ep: endpoint {
+ remote-endpoint = <&admaif3_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4_ep: endpoint {
+ remote-endpoint = <&admaif4_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5_ep: endpoint {
+ remote-endpoint = <&admaif5_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6_ep: endpoint {
+ remote-endpoint = <&admaif6_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7_ep: endpoint {
+ remote-endpoint = <&admaif7_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8_ep: endpoint {
+ remote-endpoint = <&admaif8_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9_ep: endpoint {
+ remote-endpoint = <&admaif9_ep>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10_ep: endpoint {
+ remote-endpoint = <&admaif10_ep>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11_ep: endpoint {
+ remote-endpoint = <&admaif11_ep>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12_ep: endpoint {
+ remote-endpoint = <&admaif12_ep>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13_ep: endpoint {
+ remote-endpoint = <&admaif13_ep>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14_ep: endpoint {
+ remote-endpoint = <&admaif14_ep>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15_ep: endpoint {
+ remote-endpoint = <&admaif15_ep>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16_ep: endpoint {
+ remote-endpoint = <&admaif16_ep>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17_ep: endpoint {
+ remote-endpoint = <&admaif17_ep>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18_ep: endpoint {
+ remote-endpoint = <&admaif18_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19_ep: endpoint {
+ remote-endpoint = <&admaif19_ep>;
+ };
+ };
+
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+
+ xbar_i2s5_port: port@18 {
+ reg = <0x18>;
+
+ xbar_i2s5_ep: endpoint {
+ remote-endpoint = <&i2s5_cif_ep>;
+ };
+ };
+
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+
+ xbar_dmic4_port: port@1d {
+ reg = <0x1d>;
+
+ xbar_dmic4_ep: endpoint {
+ remote-endpoint = <&dmic4_cif_ep>;
+ };
+ };
+
+ xbar_dspk1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_dspk1_ep: endpoint {
+ remote-endpoint = <&dspk1_cif_ep>;
+ };
+ };
+
+ xbar_dspk2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_dspk2_ep: endpoint {
+ remote-endpoint = <&dspk2_cif_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap_ep: endpoint@0 {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic4_ep>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk1_ep>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk2_ep>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+ };
};
ddc: i2c@3190000 {
@@ -36,7 +607,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-nx-hda";
+ nvidia,model = "NVIDIA Jetson Xavier NX HDA";
status = "okay";
};
@@ -265,6 +836,28 @@
regulator-boot-on;
};
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s3_port>, <&xbar_i2s5_port>,
+ <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,
+ <&xbar_dspk1_port>, <&xbar_dspk2_port>,
+ /* BE I/O Ports */
+ <&i2s3_port>, <&i2s5_port>,
+ <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
+ <&dspk1_port>, <&dspk2_port>;
+
+ label = "NVIDIA Jetson Xavier NX APE";
+ };
+
thermal-zones {
cpu {
polling-delay = <0>;
diff --git a/dts/src/arm64/nvidia/tegra194.dtsi b/dts/src/arm64/nvidia/tegra194.dtsi
index 9449156fae..b7d5328413 100644
--- a/dts/src/arm64/nvidia/tegra194.dtsi
+++ b/dts/src/arm64/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
@@ -733,6 +734,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC1>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC3>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_HDA>;
status = "disabled";
};
@@ -1300,6 +1305,84 @@
interrupt-controller;
};
+ smmu: iommu@12000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x12000000 0x800000>,
+ <0x11000000 0x800000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@
ranges = <0x15000000 0x15000000 0x01000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
+ iommus = <&smmu TEGRA194_SID_HOST1X>;
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_VIC>;
};
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA194_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@@ -2345,6 +2431,20 @@
};
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
+ &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
status = "okay";
diff --git a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
index 497635af7f..7d3e363474 100644
--- a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
+++ b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
@@ -424,6 +424,6 @@
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
- label = "jetson-tx1-ape";
+ label = "NVIDIA Jetson TX1 APE";
};
};
diff --git a/dts/src/arm64/nvidia/tegra210-p2597.dtsi b/dts/src/arm64/nvidia/tegra210-p2597.dtsi
index a9caaf7c0d..d8409c1b43 100644
--- a/dts/src/arm64/nvidia/tegra210-p2597.dtsi
+++ b/dts/src/arm64/nvidia/tegra210-p2597.dtsi
@@ -1345,7 +1345,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-tx1-hda";
+ nvidia,model = "NVIDIA Jetson TX1 HDA";
status = "okay";
};
diff --git a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
index 14c128a5e2..7dbb13f20d 100644
--- a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
+++ b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts
@@ -441,7 +441,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-nano-hda";
+ nvidia,model = "NVIDIA Jetson Nano HDA";
status = "okay";
};
@@ -1043,6 +1043,6 @@
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
- label = "jetson-nano-ape";
+ label = "NVIDIA Jetson Nano APE";
};
};
diff --git a/dts/src/arm64/qcom/apq8096-db820c.dtsi b/dts/src/arm64/qcom/apq8096-db820c.dtsi
index defcbd15ed..068692350e 100644
--- a/dts/src/arm64/qcom/apq8096-db820c.dtsi
+++ b/dts/src/arm64/qcom/apq8096-db820c.dtsi
@@ -41,14 +41,14 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
- serial1 = &blsp2_uart2;
- serial2 = &blsp1_uart1;
- i2c0 = &blsp1_i2c2;
+ serial0 = &blsp2_uart2;
+ serial1 = &blsp2_uart3;
+ serial2 = &blsp1_uart2;
+ i2c0 = &blsp1_i2c3;
i2c1 = &blsp2_i2c1;
- i2c2 = &blsp2_i2c0;
- spi0 = &blsp1_spi0;
- spi1 = &blsp2_spi5;
+ i2c2 = &blsp2_i2c1;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp2_spi6;
};
chosen {
@@ -133,24 +133,24 @@
};
};
-&blsp1_i2c2 {
+&blsp1_i2c3 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
-&blsp1_spi0 {
+&blsp1_spi1 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
-&blsp1_uart1 {
+&blsp1_uart2 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
@@ -162,7 +162,11 @@
};
};
-&blsp2_i2c0 {
+&adsp_pil {
+ status = "okay";
+};
+
+&blsp2_i2c1 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
@@ -174,32 +178,36 @@
status = "okay";
};
-&blsp2_spi5 {
+&blsp2_spi6 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
-&blsp2_uart1 {
+&blsp2_uart2 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&blsp2_uart2 {
+&blsp2_uart3 {
label = "LS-UART0";
status = "disabled";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart2_4pins_default>;
- pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+ pinctrl-0 = <&blsp2_uart3_4pins_default>;
+ pinctrl-1 = <&blsp2_uart3_4pins_sleep>;
};
&camss {
vdda-supply = <&vreg_l2a_1p25>;
};
+&gpu {
+ status = "okay";
+};
+
&hdmi {
status = "okay";
@@ -245,7 +253,12 @@
vdd-gfx-supply = <&vdd_gfx>;
};
-&msmgpio {
+&pm8994_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&tlmm {
gpio-line-names =
"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
@@ -424,7 +437,7 @@
};
};
- blsp1_uart1_default: blsp1_uart1_default {
+ blsp1_uart2_default: blsp1_uart2_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
@@ -437,7 +450,7 @@
};
};
- blsp1_uart1_sleep: blsp1_uart1_sleep {
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
@@ -505,20 +518,20 @@
&pcie0 {
status = "okay";
- perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie2 {
status = "okay";
- perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
@@ -929,9 +942,9 @@
&sdhc2 {
/* External SD card */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- cd-gpios = <&msmgpio 38 0x1>;
+ pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
status = "okay";
@@ -1026,20 +1039,6 @@
};
};
-&spmi_bus {
- pmic@0 {
- pon@800 {
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
- };
- };
-};
-
&ufsphy {
status = "okay";
@@ -1064,7 +1063,7 @@
status = "okay";
extcon = <&usb2_id>;
- dwc3@7600000 {
+ usb@7600000 {
extcon = <&usb2_id>;
dr_mode = "otg";
maximum-speed = "high-speed";
@@ -1075,7 +1074,7 @@
status = "okay";
extcon = <&usb3_id>;
- dwc3@6a00000 {
+ usb@6a00000 {
extcon = <&usb3_id>;
dr_mode = "otg";
};
@@ -1089,6 +1088,10 @@
};
+&venus {
+ status = "okay";
+};
+
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
diff --git a/dts/src/arm64/qcom/apq8096-ifc6640.dts b/dts/src/arm64/qcom/apq8096-ifc6640.dts
index f6ddf17ada..8c7a27e972 100644
--- a/dts/src/arm64/qcom/apq8096-ifc6640.dts
+++ b/dts/src/arm64/qcom/apq8096-ifc6640.dts
@@ -17,7 +17,7 @@
qcom,board-id = <0x00010018 0>;
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
@@ -81,14 +81,22 @@
};
};
-&blsp2_uart1 {
+&blsp2_uart2 {
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&msmgpio {
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&tlmm {
sdc2_pins_default: sdc2-pins-default {
clk {
pins = "sdc2_clk";
@@ -352,7 +360,7 @@
bus-width = <4>;
- cd-gpios = <&msmgpio 38 0x1>;
+ cd-gpios = <&tlmm 38 0x1>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
@@ -383,3 +391,7 @@
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/dts/src/arm64/qcom/ipq8074-hk10-c1.dts b/dts/src/arm64/qcom/ipq8074-hk10-c1.dts
new file mode 100644
index 0000000000..2bfcf42aea
--- /dev/null
+++ b/dts/src/arm64/qcom/ipq8074-hk10-c1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1";
+ compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074";
+};
diff --git a/dts/src/arm64/qcom/ipq8074-hk10-c2.dts b/dts/src/arm64/qcom/ipq8074-hk10-c2.dts
new file mode 100644
index 0000000000..7da39f1d97
--- /dev/null
+++ b/dts/src/arm64/qcom/ipq8074-hk10-c2.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2";
+ compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";
+};
diff --git a/dts/src/arm64/qcom/ipq8074-hk10.dtsi b/dts/src/arm64/qcom/ipq8074-hk10.dtsi
new file mode 100644
index 0000000000..07e6708296
--- /dev/null
+++ b/dts/src/arm64/qcom/ipq8074-hk10.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+};
+
+&blsp1_spi1 {
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart5 {
+ status = "ok";
+};
+
+&pcie0 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+};
+
+&pcie1 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+};
+
+&pcie_phy0 {
+ status = "ok";
+};
+
+&pcie_phy1 {
+ status = "ok";
+};
+
+&qpic_bam {
+ status = "ok";
+};
+
+&qpic_nand {
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+};
diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi
index a32e5e79ab..95d6cb8cd4 100644
--- a/dts/src/arm64/qcom/ipq8074.dtsi
+++ b/dts/src/arm64/qcom/ipq8074.dtsi
@@ -165,6 +165,7 @@
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
};
pcie_phy0: phy@86000 {
@@ -372,6 +373,21 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x078ba000 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 23>, <&blsp_dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07984000 0x1a000>;
@@ -427,7 +443,7 @@
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
- dwc_0: dwc3@8a00000 {
+ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +484,7 @@
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
- dwc_1: dwc3@8c00000 {
+ dwc_1: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/msm8916-alcatel-idol347.dts b/dts/src/arm64/qcom/msm8916-alcatel-idol347.dts
index 540b1fa4b2..670bd1bebd 100644
--- a/dts/src/arm64/qcom/msm8916-alcatel-idol347.dts
+++ b/dts/src/arm64/qcom/msm8916-alcatel-idol347.dts
@@ -45,6 +45,24 @@
status = "okay";
};
+&blsp_i2c4 {
+ status = "okay";
+
+ touchscreen@26 {
+ compatible = "mstar,msg2638";
+ reg = <0x26>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_reset_default>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+ touchscreen-size-x = <2048>;
+ touchscreen-size-y = <2048>;
+ };
+};
+
&blsp_i2c5 {
status = "okay";
@@ -281,6 +299,14 @@
bias-pull-up;
};
+ ts_int_reset_default: ts-int-reset-default {
+ pins = "gpio13", "gpio100";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
usb_id_default: usb-id-default {
pins = "gpio69";
function = "gpio";
diff --git a/dts/src/arm64/qcom/msm8916-huawei-g7.dts b/dts/src/arm64/qcom/msm8916-huawei-g7.dts
new file mode 100644
index 0000000000..e0075b5741
--- /dev/null
+++ b/dts/src/arm64/qcom/msm8916-huawei-g7.dts
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2021 Stephan Gerhold
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+
+/*
+ * Note: The original firmware from Huawei can only boot 32-bit kernels.
+ * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
+ * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
+ * forgot to set up (firmware) secure boot for some reason.
+ *
+ * Also note that Huawei no longer provides bootloader unlock codes.
+ * This can be bypassed by patching the bootloader from a custom HYP firmware,
+ * making it think the bootloader is unlocked.
+ *
+ * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)
+ */
+
+/ {
+ model = "Huawei Ascend G7";
+ compatible = "huawei,g7", "qcom,msm8916";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ label = "GPIO Buttons";
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds_default>;
+
+ led-0 {
+ gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-1 {
+ gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-2 {
+ gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_default>;
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak09911";
+ reg = <0x0c>;
+
+ vdd-supply = <&pm8916_l17>;
+ vid-supply = <&pm8916_l6>;
+
+ reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mag_reset_default>;
+ };
+
+ accelerometer@1e {
+ compatible = "kionix,kx023-1025";
+ reg = <0x1e>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <115 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_irq_default>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+
+ proximity@39 {
+ compatible = "avago,apds9930";
+ reg = <0x39>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <113 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ led-max-microamp = <100000>;
+ amstaos,proximity-diodes = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&prox_irq_default>;
+ };
+
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&reg_lcd_en_default>;
+
+ reg_lcd_pos: outp {
+ regulator-name = "outp";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+
+ reg_lcd_neg: outn {
+ regulator-name = "outn";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ rmi4@70 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l16>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_irq_default>;
+
+ syna,startup-delay-ms = <100>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>; /* Allow sleeping */
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>; /* Touchscreen */
+ };
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&pm8916_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&pronto {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>;
+
+ /*
+ * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>.
+ * However, gpio38 does not change its state when inserting/removing the
+ * SD card, it's just low all the time. The Huawei kernel seems to use
+ * polling for SD card detection instead.
+ *
+ * However, looking closer at the GPIO debug output it turns out that
+ * gpio56 switches its state when inserting/removing the SD card.
+ * It behaves just like gpio38 normally does. Usually GPIO56 is used as
+ * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted.
+ * Maybe Huawei decided to replace the second SIM card slot with the
+ * SD card slot and forgot to re-route to gpio38.
+ */
+ cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>;
+};
+
+&usb {
+ status = "okay";
+ extcon = <&usb_id>, <&usb_id>;
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&smd_rpm_regulators {
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ l4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l8 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l10 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ l11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+
+ l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+};
+
+&msmgpio {
+ accel_irq_default: accel-irq-default {
+ pins = "gpio115";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default {
+ pins = "gpio107";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ gpio_leds_default: gpio-leds-default {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ nfc_default: nfc-default {
+ pins = "gpio2", "gpio20", "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mag_reset_default: mag-reset-default {
+ pins = "gpio36";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ prox_irq_default: prox-irq-default {
+ pins = "gpio113";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ reg_lcd_en_default: reg-lcd-en-default {
+ pins = "gpio32", "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdhc2_cd_default: sdhc2-cd-default {
+ pins = "gpio56";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_irq_default: ts-irq-default {
+ pins = "gpio13";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ usb_id_default: usb-id-default {
+ pins = "gpio117";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
index 230ba3ce32..9b4b7de7ce 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
@@ -95,6 +96,63 @@
pinctrl-0 = <&muic_int_default>;
};
};
+
+ i2c-tkey {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey: touchkey@20 {
+ /* Note: Actually an ABOV MCU that implements same interface */
+ compatible = "coreriver,tc360-touchkey";
+ reg = <0x20>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <98 IRQ_TYPE_EDGE_FALLING>;
+
+ /* vcc/vdd-supply are board-specific */
+ vddio-supply = <&pm8916_l6>;
+
+ linux,keycodes = <KEY_APPSELECT KEY_BACK>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_default>;
+ };
+ };
+
+ i2c-nfc {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+ reg = <0x27>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default &nfc_clk_req>;
+ };
+ };
};
&blsp_i2c2 {
@@ -122,6 +180,20 @@
};
};
+&blsp_i2c4 {
+ status = "okay";
+
+ battery@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <121 IRQ_TYPE_EDGE_BOTH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fg_alert_default>;
+ };
+};
+
&blsp1_uart2 {
status = "okay";
};
@@ -284,6 +356,14 @@
bias-disable;
};
+ fg_alert_default: fg-alert-default {
+ pins = "gpio121";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
gpio_keys_default: gpio-keys-default {
pins = "gpio107", "gpio109";
function = "gpio";
@@ -333,6 +413,46 @@
bias-disable;
};
+ nfc_default: nfc-default {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+
+ irq {
+ pins = "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ nfc_i2c_default: nfc-i2c-default {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_default: tkey-default {
+ pins = "gpio98";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_i2c_default: tkey-i2c-default {
+ pins = "gpio16", "gpio17";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
tsp_en_default: tsp-en-default {
pins = "gpio73";
function = "gpio";
@@ -341,3 +461,14 @@
bias-disable;
};
};
+
+&pm8916_gpios {
+ nfc_clk_req: nfc-clk-req {
+ pins = "gpio2";
+ function = "func1";
+
+ input-enable;
+ bias-disable;
+ power-source = <PM8916_GPIO_L2>;
+ };
+};
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
index 661f41ad97..6cc2eaeb1d 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
+++ b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
@@ -20,6 +20,37 @@
pinctrl-names = "default";
pinctrl-0 = <&panel_vdd3_default>;
};
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
+
+ reg_key_led: regulator-key-led {
+ compatible = "regulator-fixed";
+ regulator-name = "key_led";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_led_en_default>;
+ };
+};
+
+&touchkey {
+ vcc-supply = <&reg_touch_key>;
+ vdd-supply = <&reg_key_led>;
};
&accelerometer {
@@ -81,6 +112,22 @@
bias-disable;
};
+ tkey_en_default: tkey-en-default {
+ pins = "gpio86";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_led_en_default: tkey-led-en-default {
+ pins = "gpio60";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
index dd35c33443..c2eff5aebf 100644
--- a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
+++ b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
@@ -7,6 +7,19 @@
/ {
model = "Samsung Galaxy A5U (EUR)";
compatible = "samsung,a5u-eur", "qcom,msm8916";
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
};
&accelerometer {
@@ -42,7 +55,20 @@
};
};
+&touchkey {
+ vcc-supply = <&reg_touch_key>;
+ vdd-supply = <&reg_touch_key>;
+};
+
&msmgpio {
+ tkey_en_default: tkey-en-default {
+ pins = "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/dts/src/arm64/qcom/msm8994-angler-rev-101.dts b/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
index baa55643b4..ffe1a9bd8f 100644
--- a/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
+++ b/dts/src/arm64/qcom/msm8994-angler-rev-101.dts
@@ -32,3 +32,7 @@
};
};
};
+
+&tlmm {
+ gpio-reserved-ranges = <85 4>;
+};
diff --git a/dts/src/arm64/qcom/msm8996-mtp.dtsi b/dts/src/arm64/qcom/msm8996-mtp.dtsi
index 5f46a1427f..1e1514e915 100644
--- a/dts/src/arm64/qcom/msm8996-mtp.dtsi
+++ b/dts/src/arm64/qcom/msm8996-mtp.dtsi
@@ -7,7 +7,7 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
diff --git a/dts/src/arm64/qcom/msm8996-pins.dtsi b/dts/src/arm64/qcom/msm8996-pins.dtsi
deleted file mode 100644
index ac1ede5793..0000000000
--- a/dts/src/arm64/qcom/msm8996-pins.dtsi
+++ /dev/null
@@ -1,653 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
-
- wcd9xxx_intr {
- wcd_intr_default: wcd_intr_default{
- mux {
- pins = "gpio54";
- function = "gpio";
- };
-
- config {
- pins = "gpio54";
- drive-strength = <2>; /* 2 mA */
- bias-pull-down; /* pull down */
- input-enable;
- };
- };
- };
-
- cdc_reset_ctrl {
- cdc_reset_sleep: cdc_reset_sleep {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
- };
- cdc_reset_active:cdc_reset_active {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-pull-down;
- output-high;
- };
- };
- };
-
- blsp1_spi0_default: blsp1_spi0_default {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio0", "gpio1", "gpio3";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio2";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio3";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio2";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp1_spi0_sleep: blsp1_spi0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- blsp1_i2c2_default: blsp1_i2c2_default {
- pinmux {
- function = "blsp_i2c3";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <16>;
- bias-disable = <0>;
- };
- };
-
- blsp1_i2c2_sleep: blsp1_i2c2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <2>;
- bias-disable = <0>;
- };
- };
-
- blsp2_i2c0_default: blsp2_i2c0 {
- pinmux {
- function = "blsp_i2c7";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c0_sleep: blsp2_i2c0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_default: blsp2_uart1_2pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_default: blsp2_uart1_4pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_default: blsp2_i2c1 {
- pinmux {
- function = "blsp_i2c8";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_sleep: blsp2_i2c1_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_default: blsp2_uart2_2pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_default: blsp2_uart2_4pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_spi5_default: blsp2_spi5_default {
- pinmux {
- function = "blsp_spi12";
- pins = "gpio85", "gpio86", "gpio88";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio87";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio88";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio87";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp2_spi5_sleep: blsp2_spi5_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- sdc2_clk_on: sdc2_clk_on {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <16>; /* 16 MA */
- };
- };
-
- sdc2_clk_off: sdc2_clk_off {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_cmd_on: sdc2_cmd_on {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_cmd_off: sdc2_cmd_off {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_data_on: sdc2_data_on {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_data_off: sdc2_data_off {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- pcie0_clkreq_default: pcie0_clkreq_default {
- mux {
- pins = "gpio36";
- function = "pci_e0";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_perst_default: pcie0_perst_default {
- mux {
- pins = "gpio35";
- function = "gpio";
- };
-
- config {
- pins = "gpio35";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie0_wake_default: pcie0_wake_default {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_clkreq_sleep: pcie0_clkreq_sleep {
- mux {
- pins = "gpio36";
- function = "gpio";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie0_wake_sleep: pcie0_wake_sleep {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_clkreq_default: pcie1_clkreq_default {
- mux {
- pins = "gpio131";
- function = "pci_e1";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_perst_default: pcie1_perst_default {
- mux {
- pins = "gpio130";
- function = "gpio";
- };
-
- config {
- pins = "gpio130";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_wake_default: pcie1_wake_default {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_clkreq_sleep: pcie1_clkreq_sleep {
- mux {
- pins = "gpio131";
- function = "gpio";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_wake_sleep: pcie1_wake_sleep {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_clkreq_default: pcie2_clkreq_default {
- mux {
- pins = "gpio115";
- function = "pci_e2";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_perst_default: pcie2_perst_default {
- mux {
- pins = "gpio114";
- function = "gpio";
- };
-
- config {
- pins = "gpio114";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_wake_default: pcie2_wake_default {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_clkreq_sleep: pcie2_clkreq_sleep {
- mux {
- pins = "gpio115";
- function = "gpio";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_wake_sleep: pcie2_wake_sleep {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- cci0_default: cci0_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio17", "gpio18";
- };
- pinconf {
- pins = "gpio17", "gpio18";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- cci1_default: cci1_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio19", "gpio20";
- };
- pinconf {
- pins = "gpio19", "gpio20";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_board_default: camera_board_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio98";
- };
- config_pwdn {
- pins = "gpio98";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio104";
- };
- config_rst {
- pins = "gpio104";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk1 {
- function = "cam_mclk";
- pins = "gpio14";
- };
- config_mclk1 {
- pins = "gpio14";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_front_default: camera_front_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio133";
- };
- config_pwdn {
- pins = "gpio133";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio23";
- };
- config_rst {
- pins = "gpio23";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk2 {
- function = "cam_mclk";
- pins = "gpio15";
- };
- config_mclk2 {
- pins = "gpio15";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_rear_default: camera_rear_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio26";
- };
- config_pwdn {
- pins = "gpio26";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio25";
- };
- config_rst {
- pins = "gpio25";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk0 {
- function = "cam_mclk";
- pins = "gpio13";
- };
- config_mclk0 {
- pins = "gpio13";
- drive-strength = <16>;
- bias-disable;
- };
- };
-};
diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi
index ce430ba9c1..0e1bc4669d 100644
--- a/dts/src/arm64/qcom/msm8996.dtsi
+++ b/dts/src/arm64/qcom/msm8996.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -43,6 +45,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -57,6 +62,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -67,6 +75,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -81,6 +92,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -120,6 +134,227 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-msm8996";
@@ -424,7 +659,7 @@
bits = <1 4>;
};
- gpu_speed_bin: gpu_speed_bin@133 {
+ speedbin_efuse: speedbin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
@@ -472,7 +707,7 @@
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
- reg = <0x00740000 0x20000>;
+ reg = <0x00740000 0x40000>;
};
tcsr: syscon@7a0000 {
@@ -521,6 +756,8 @@
#size-cells = <1>;
ranges;
+ status = "disabled";
+
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x00901000 0x90000>;
@@ -542,6 +779,11 @@
iommus = <&mdp_smmu 0>;
+ assigned-clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -552,9 +794,82 @@
remote-endpoint = <&hdmi_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@994000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x00994000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "byte",
+ "iface",
+ "bus",
+ "core_mmss",
+ "pixel",
+ "core";
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
};
};
+ dsi0_phy: dsi-phy@994400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0x00994400 0x100>,
+ <0x00994500 0x300>,
+ <0x00994800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+ status = "disabled";
+ };
+
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
@@ -618,7 +933,8 @@
"ref";
};
};
- gpu@b00000 {
+
+ gpu: gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
@@ -642,7 +958,7 @@
power-domains = <&mmcc GPU_GX_GDSC>;
iommus = <&adreno_smmu 0>;
- nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cells = <&speedbin_efuse>;
nvmem-cell-names = "speed_bin";
qcom,gpu-quirk-two-pass-use-wfi;
@@ -650,6 +966,8 @@
operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
@@ -693,15 +1011,482 @@
};
};
- msmgpio: pinctrl@1010000 {
+ tlmm: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&msmgpio 0 0 150>;
+ gpio-ranges = <&tlmm 0 0 150>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ blsp1_spi1_default: blsp1-spi1-default {
+ spi {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp1_spi1_sleep: blsp1-spi1-sleep {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_default: blsp2-i2c2 {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci0_default: cci0-default {
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera0_state_on:
+ camera_rear_default: camera-rear-default {
+ mclk0 {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci1_default: cci1-default {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera1_state_on:
+ camera_board_default: camera-board-default {
+ mclk1 {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio98";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera2_state_on:
+ camera_front_default: camera-front-default {
+ mclk2 {
+ pins = "gpio15";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ pcie0_state_on: pcie0-state-on {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_state_off: pcie0-state-off {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_i2c3_default: blsp1-i2c2-default {
+ pins = "gpio47", "gpio48";
+ function = "blsp_i2c3";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+
+ blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ pins = "gpio47", "gpio48";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+
+ blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcd_intr_default: wcd-intr-default{
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ blsp2_i2c1_default: blsp2-i2c1 {
+ pins = "gpio55", "gpio56";
+ function = "blsp_i2c7";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c5_default: blsp2-i2c5 {
+ pins = "gpio60", "gpio61";
+ function = "blsp_i2c11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /* Sleep state for BLSP2_I2C5 is missing.. */
+
+ cdc_reset_active: cdc-reset-active {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ output-high;
+ };
+
+ cdc_reset_sleep: cdc-reset-sleep {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ blsp2_spi6_default: blsp2-spi5-default {
+ spi {
+ pins = "gpio85", "gpio86", "gpio88";
+ function = "blsp_spi12";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp2_spi6_sleep: blsp2-spi5-sleep {
+ pins = "gpio85", "gpio86", "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_i2c6_default: blsp2-i2c6 {
+ pins = "gpio87", "gpio88";
+ function = "blsp_i2c12";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ pins = "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_state_on: pcie1-state-on {
+ perst {
+ pins = "gpio130";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio131";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_state_off: pcie1-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio131";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie2_state_on: pcie2-state-on {
+ perst {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio115";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_state_off: pcie2-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sdc1_state_on: sdc1-state-on {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-state-off {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-clk-on {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-clk-off {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
spmi_bus: qcom,spmi@400f000 {
@@ -762,8 +1547,8 @@
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
- pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
+ pinctrl-0 = <&pcie0_state_on>;
+ pinctrl-1 = <&pcie0_state_off>;
linux,pci-domain = <0>;
@@ -816,8 +1601,8 @@
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
- pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+ pinctrl-0 = <&pcie1_state_on>;
+ pinctrl-1 = <&pcie1_state_off>;
linux,pci-domain = <1>;
@@ -867,8 +1652,8 @@
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+ pinctrl-0 = <&pcie2_state_on>;
+ pinctrl-1 = <&pcie2_state_off>;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
@@ -1136,7 +1921,7 @@
};
adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
@@ -1152,7 +1937,7 @@
power-domains = <&mmcc GPU_GDSC>;
};
- video-codec@c00000 {
+ venus: video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
@@ -1183,7 +1968,7 @@
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
- status = "okay";
+ status = "disabled";
video-decoder {
compatible = "venus-decoder";
@@ -1745,9 +2530,14 @@
};
};
};
+
kryocc: clock-controller@6400000 {
- compatible = "qcom,apcc-msm8996";
+ compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
+
+ clock-names = "xo";
+ clocks = <&xo_board>;
+
#clock-cells = <1>;
};
@@ -1758,6 +2548,10 @@
#size-cells = <1>;
ranges;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
@@ -1772,7 +2566,7 @@
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
- dwc3@6a00000 {
+ usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
@@ -1841,34 +2635,75 @@
status = "disabled";
};
+ sdhc1: sdhci@7464900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x07464900 0x11c>, <0x07464000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+ };
+
sdhc2: sdhci@74a4900 {
- status = "disabled";
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
-
- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
-
- clock-names = "iface", "core", "xo";
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
- bus-width = <4>;
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+
+ bus-width = <4>;
+ status = "disabled";
};
- blsp1_uart1: serial@7570000 {
+ blsp1_dma: dma@7544000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07544000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart2: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
- blsp1_spi0: spi@7575000 {
+ blsp1_spi1: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -1876,14 +2711,16 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_spi0_default>;
- pinctrl-1 = <&blsp1_spi0_sleep>;
+ pinctrl-0 = <&blsp1_spi1_default>;
+ pinctrl-1 = <&blsp1_spi1_sleep>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp1_i2c2: i2c@7577000 {
+ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -1891,14 +2728,27 @@
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_i2c2_default>;
- pinctrl-1 = <&blsp1_i2c2_sleep>;
+ pinctrl-0 = <&blsp1_i2c3_default>;
+ pinctrl-1 = <&blsp1_i2c3_sleep>;
+ dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_uart1: serial@75b0000 {
+ blsp2_dma: dma@7584000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07584000 0x2b000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -1908,7 +2758,7 @@
status = "disabled";
};
- blsp2_uart2: serial@75b1000 {
+ blsp2_uart3: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
@@ -1918,7 +2768,7 @@
status = "disabled";
};
- blsp2_i2c0: i2c@75b5000 {
+ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -1926,14 +2776,16 @@
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c0_default>;
- pinctrl-1 = <&blsp2_i2c0_sleep>;
+ pinctrl-0 = <&blsp2_i2c1_default>;
+ pinctrl-1 = <&blsp2_i2c1_sleep>;
+ dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_i2c1: i2c@75b6000 {
+ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@@ -1941,14 +2793,49 @@
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c1_default>;
- pinctrl-1 = <&blsp2_i2c1_sleep>;
+ pinctrl-0 = <&blsp2_i2c2_default>;
+ pinctrl-1 = <&blsp2_i2c2_sleep>;
+ dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_spi5: spi@75ba000{
+ blsp2_i2c5: i2c@75b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75b9000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp2_i2c5_default>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_i2c6: i2c@75ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75ba000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c6_default>;
+ pinctrl-1 = <&blsp2_i2c6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_spi6: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -1956,8 +2843,10 @@
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_spi5_default>;
- pinctrl-1 = <&blsp2_spi5_sleep>;
+ pinctrl-0 = <&blsp2_spi6_default>;
+ pinctrl-1 = <&blsp2_spi6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1981,14 +2870,16 @@
assigned-clock-rates = <19200000>, <60000000>;
power-domains = <&gcc USB30_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
status = "disabled";
- dwc3@7600000 {
+ usb@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
@@ -2032,13 +2923,13 @@
compatible = "slim217,1a0";
reg = <1 0>;
- interrupt-parent = <&msmgpio>;
+ interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
- reset-gpios = <&msmgpio 64 0>;
+ reset-gpios = <&tlmm 64 0>;
slim-ifc-dev = <&tasha_ifd>;
@@ -2067,6 +2958,11 @@
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
+ power-domains = <&rpmpd MSM8996_VDDCX>;
+ power-domain-names = "cx";
+
+ status = "disabled";
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
@@ -2458,4 +3354,3 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
-#include "msm8996-pins.dtsi"
diff --git a/dts/src/arm64/qcom/msm8998.dtsi b/dts/src/arm64/qcom/msm8998.dtsi
index e9d3ce2993..6f294f9c0c 100644
--- a/dts/src/arm64/qcom/msm8998.dtsi
+++ b/dts/src/arm64/qcom/msm8998.dtsi
@@ -1964,7 +1964,7 @@
resets = <&gcc GCC_USB_30_BCR>;
- usb3_dwc3: dwc3@a800000 {
+ usb3_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/pm6150.dtsi b/dts/src/arm64/qcom/pm6150.dtsi
index 8ab4f1f78b..8a4972e6a2 100644
--- a/dts/src/arm64/qcom/pm6150.dtsi
+++ b/dts/src/arm64/qcom/pm6150.dtsi
@@ -7,6 +7,30 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
+/ {
+ thermal-zones {
+ pm6150_thermal: pm6150-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6150_temp>;
+
+ trips {
+ pm6150_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6150_crit: crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pm6150_lsid0: pmic@0 {
compatible = "qcom,pm6150", "qcom,spmi-pmic";
diff --git a/dts/src/arm64/qcom/pm7325.dtsi b/dts/src/arm64/qcom/pm7325.dtsi
new file mode 100644
index 0000000000..e7f64a9ddc
--- /dev/null
+++ b/dts/src/arm64/qcom/pm7325.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2021, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm7325: pmic@1 {
+ compatible = "qcom,pm7325", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm7325_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm7325_gpios: gpios@8800 {
+ compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm7325_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm7325_thermal: pm7325-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7325_temp_alarm>;
+
+ trips {
+ pm7325_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm7325_crit: pm7325-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/pm8150.dtsi b/dts/src/arm64/qcom/pm8150.dtsi
index fa4ea7ded0..c566a64b13 100644
--- a/dts/src/arm64/qcom/pm8150.dtsi
+++ b/dts/src/arm64/qcom/pm8150.dtsi
@@ -50,7 +50,8 @@
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
- pwrkey {
+
+ pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
@@ -59,6 +60,15 @@
status = "disabled";
};
+
+ pon_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+
+ status = "disabled";
+ };
};
pm8150_temp: temp-alarm@2400 {
diff --git a/dts/src/arm64/qcom/pm8350c.dtsi b/dts/src/arm64/qcom/pm8350c.dtsi
index 2b9b75ecec..e1b75ae0a8 100644
--- a/dts/src/arm64/qcom/pm8350c.dtsi
+++ b/dts/src/arm64/qcom/pm8350c.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8350c_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pm8350c_gpios: gpio@8800 {
- compatible = "qcom,pm8350c-gpio";
+ compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pm8350c_gpios 0 0 9>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pm8350c_thermal: pm8350c-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8350c_temp_alarm>;
+
+ trips {
+ pm8350c_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8350c_crit: pm8350c-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/pm8994.dtsi b/dts/src/arm64/qcom/pm8994.dtsi
index c3876c82c8..ad19016df0 100644
--- a/dts/src/arm64/qcom/pm8994.dtsi
+++ b/dts/src/arm64/qcom/pm8994.dtsi
@@ -45,7 +45,6 @@
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
-
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
@@ -58,6 +57,13 @@
linux,code = <KEY_POWER>;
};
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm8994_temp: temp-alarm@2400 {
diff --git a/dts/src/arm64/qcom/pmi8994.dtsi b/dts/src/arm64/qcom/pmi8994.dtsi
index e5ed28ab9b..b4ac900ab1 100644
--- a/dts/src/arm64/qcom/pmi8994.dtsi
+++ b/dts/src/arm64/qcom/pmi8994.dtsi
@@ -32,5 +32,18 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ pmi8994_wled: wled@d800 {
+ compatible = "qcom,pmi8994-wled";
+ reg = <0xd800 0xd900>;
+ interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "short";
+ qcom,num-strings = <3>;
+ /* Yes, all four strings *have to* be defined or things won't work. */
+ qcom,enabled-strings = <0 1 2 3>;
+ qcom,cabc;
+ qcom,eternal-pfet;
+ status = "disabled";
+ };
};
};
diff --git a/dts/src/arm64/qcom/pmk8350.dtsi b/dts/src/arm64/qcom/pmk8350.dtsi
index 1530b8ff27..04fc2632a0 100644
--- a/dts/src/arm64/qcom/pmk8350.dtsi
+++ b/dts/src/arm64/qcom/pmk8350.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2021, Linaro Limited
*/
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@@ -13,10 +15,57 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmk8350_pon: pon@1300 {
+ compatible = "qcom,pm8998-pon";
+ reg = <0x1300>;
+
+ pwrkey {
+ compatible = "qcom,pmk8350-pwrkey";
+ interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ };
+
+ resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pmk8350_vadc: adc@3100 {
+ compatible = "qcom,spmi-adc7";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ };
+
+ pmk8350_adc_tm: adc-tm@3400 {
+ compatible = "qcom,adc-tm7";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "threshold";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ pmk8350_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
pmk8350_gpios: gpio@b000 {
- compatible = "qcom,pmk8350-gpio";
+ compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
reg = <0xb000>;
gpio-controller;
+ gpio-ranges = <&pmk8350_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/dts/src/arm64/qcom/pmm8155au_1.dtsi b/dts/src/arm64/qcom/pmm8155au_1.dtsi
new file mode 100644
index 0000000000..7072e5a2e7
--- /dev/null
+++ b/dts/src/arm64/qcom/pmm8155au_1.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-1-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_1_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon: power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+
+ status = "disabled";
+ };
+ };
+
+ pmm8155au_1_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_1_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_1_adc_tm: adc-tm@3500 {
+ compatible = "qcom,spmi-adc-tm5";
+ reg = <0x3500>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pmm8155au_1_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_1_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_1_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm64/qcom/pmm8155au_2.dtsi b/dts/src/arm64/qcom/pmm8155au_2.dtsi
new file mode 100644
index 0000000000..72075964fb
--- /dev/null
+++ b/dts/src/arm64/qcom/pmm8155au_2.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_2_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@4 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_2_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_2_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_2_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_2_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@5 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm64/qcom/pmr735a.dtsi b/dts/src/arm64/qcom/pmr735a.dtsi
index 1c675af13c..b4b6ba24f8 100644
--- a/dts/src/arm64/qcom/pmr735a.dtsi
+++ b/dts/src/arm64/qcom/pmr735a.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmr735a_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pmr735a_gpios: gpio@8800 {
- compatible = "qcom,pmr735a-gpio";
+ compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pmr735a_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pmr735a_thermal: pmr735a-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmr735a_temp_alarm>;
+
+ trips {
+ pmr735a_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmr735a_crit: pmr735a-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/dts/src/arm64/qcom/qcs404-evb.dtsi b/dts/src/arm64/qcom/qcs404-evb.dtsi
index a80c578484..f8a55307b8 100644
--- a/dts/src/arm64/qcom/qcs404-evb.dtsi
+++ b/dts/src/arm64/qcom/qcs404-evb.dtsi
@@ -337,7 +337,7 @@
&usb3 {
status = "okay";
- dwc3@7580000 {
+ usb@7580000 {
dr_mode = "host";
};
};
diff --git a/dts/src/arm64/qcom/qcs404.dtsi b/dts/src/arm64/qcom/qcs404.dtsi
index 339790ba58..9c4be020d5 100644
--- a/dts/src/arm64/qcom/qcs404.dtsi
+++ b/dts/src/arm64/qcom/qcs404.dtsi
@@ -544,7 +544,7 @@
assigned-clock-rates = <19200000>, <200000000>;
status = "disabled";
- dwc3@7580000 {
+ usb@7580000 {
compatible = "snps,dwc3";
reg = <0x07580000 0xcd00>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -573,7 +573,7 @@
assigned-clock-rates = <19200000>, <133333333>;
status = "disabled";
- dwc3@78c0000 {
+ usb@78c0000 {
compatible = "snps,dwc3";
reg = <0x078c0000 0xcc00>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/qrb5165-rb5.dts b/dts/src/arm64/qcom/qrb5165-rb5.dts
index 5f41de20aa..8ac96f8e79 100644
--- a/dts/src/arm64/qcom/qrb5165-rb5.dts
+++ b/dts/src/arm64/qcom/qrb5165-rb5.dts
@@ -5,7 +5,6 @@
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -552,7 +551,13 @@
vdds-supply = <&vreg_l5a_0p88>;
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -664,10 +669,6 @@
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_default_state>;
};
&pcie0_phy {
@@ -678,10 +679,6 @@
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_default_state>;
};
&pcie1_phy {
@@ -692,10 +689,6 @@
&pcie2 {
status = "okay";
- perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_default_state>;
};
&pcie2_phy {
@@ -1173,81 +1166,6 @@
bias-disable;
};
- pcie0_default_state: pcie0-default {
- clkreq {
- pins = "gpio80";
- function = "pci_e0";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio79";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio81";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_default_state: pcie1-default {
- clkreq {
- pins = "gpio83";
- function = "pci_e1";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio82";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio84";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_default_state: pcie2-default {
- clkreq {
- pins = "gpio86";
- function = "pci_e2";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio85";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio87";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
@@ -1352,6 +1270,10 @@
qcom,dmic-sample-rate = <600000>;
};
+&venus {
+ status = "okay";
+};
+
/* PINCTRL - additions to nodes defined in sm8250.dtsi */
&qup_spi0_cs_gpio {
drive-strength = <6>;
diff --git a/dts/src/arm64/qcom/sa8155p-adp.dts b/dts/src/arm64/qcom/sa8155p-adp.dts
new file mode 100644
index 0000000000..0da7a3b8d1
--- /dev/null
+++ b/dts/src/arm64/qcom/sa8155p-adp.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pmm8155au_1.dtsi"
+#include "pmm8155au_2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA8155P ADP";
+ compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vreg_3p3: vreg_3p3_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /*
+ * S4A is always on and not controllable through RPMh.
+ * So model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: smps4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+
+ vin-supply = <&vreg_3p3>;
+ };
+};
+
+&apps_rsc {
+ pmm8155au-1-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p92>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s5a_2p04: smps5 {
+ regulator-name = "vreg_s5a_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p92: smps6 {
+ regulator-name = "vreg_s6a_0p92";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1a_0p752: ldo1 {
+ regulator-name = "vreg_l1a_0p752";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p072: ldo2 {
+ regulator-name = "vreg_l2a_3p072";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-name = "vreg_l3a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_usb_ss_dp_core_1:
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p96: ldo10 {
+ regulator-name = "vreg_l10a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-name = "vreg_l11a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_1p8:
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-name = "vreg_l13a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-name = "vreg_l15a_1p7";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_2p96: ldo17 {
+ regulator-name = "vreg_l17a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pmm8155au-2-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>;
+ vdd-l6-l9-supply = <&vreg_s6c_1p128>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s4c_1p352: smps4 {
+ regulator-name = "vreg_s4c_1p352";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5c_2p04: smps5 {
+ regulator-name = "vreg_s5c_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6c_1p128: smps6 {
+ regulator-name = "vreg_s6c_1p128";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1c_1p304: ldo1 {
+ regulator-name = "vreg_l1c_1p304";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p808: ldo2 {
+ regulator-name = "vreg_l2c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p2: ldo5 {
+ regulator-name = "vreg_l5c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_1p8: ldo7 {
+ regulator-name = "vreg_l7c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p2: ldo8 {
+ regulator-name = "vreg_l8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_0p8: ldo11 {
+ regulator-name = "vreg_l11c_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p808: ldo12 {
+ regulator-name = "vreg_l12c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p96: ldo13 {
+ regulator-name = "vreg_l13c_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15c_1p9: ldo15 {
+ regulator-name = "vreg_l15c_1p9";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16c_3p008: ldo16 {
+ regulator-name = "vreg_l16c_3p008";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18c_0p88: ldo18 {
+ regulator-name = "vreg_l18c_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p96>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l5c_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-max-microamp = <87100>;
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda-pll-max-microamp = <18300>;
+};
+
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
diff --git a/dts/src/arm64/qcom/sc7180-idp.dts b/dts/src/arm64/qcom/sc7180-idp.dts
index e77a792603..acdb36f447 100644
--- a/dts/src/arm64/qcom/sc7180-idp.dts
+++ b/dts/src/arm64/qcom/sc7180-idp.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sc7180.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
@@ -45,7 +46,7 @@
/* Increase the size from 2MB to 8MB */
&rmtfs_mem {
- reg = <0x0 0x84400000 0x0 0x800000>;
+ reg = <0x0 0x94600000 0x0 0x800000>;
};
/ {
@@ -288,6 +289,57 @@
};
};
+&dsi0 {
+ status = "okay";
+
+ vdda-supply = <&vreg_l3c_1p2>;
+
+ panel@0 {
+ compatible = "visionox,rm69299-1080p-display";
+ reg = <0>;
+
+ vdda-supply = <&vreg_l8c_1p8>;
+ vdd3p3-supply = <&vreg_l18a_2p8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pins>;
+
+ reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dsi_phy {
+ status = "okay";
+};
+
+&mdp {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
&qfprom {
vcc-supply = <&vreg_l11a_1p8>;
};
@@ -414,6 +466,19 @@
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+&pm6150l_gpio {
+ disp_pins: disp-pins {
+ pinconf {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_FUNC1;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
&qspi_clk {
pinconf {
pins = "gpio63";
@@ -598,4 +663,106 @@
bias-pull-up;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
index 533c048903..82dc00cc7f 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
@@ -9,8 +9,8 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev1) with LTE";
- compatible = "google,coachz-rev1-sku0", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2) with LTE";
+ compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180";
};
&cros_ec_proximity {
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
index 1b1dbdb2a8..21b516e069 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
@@ -10,8 +10,26 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev1)";
- compatible = "google,coachz-rev1", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2)";
+ compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature,
+ * which currently is not supported by the PM6150 ADC driver. Disable the
+ * skin temperature thermal zone to avoid using bogus temperature values.
+ */
+&skin_temp_thermal {
+ status = "disabled";
};
&tlmm {
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts
index 6e7745801f..d23409034e 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts
@@ -2,14 +2,14 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
-#include "sc7180-trogdor-coachz-r2.dts"
+#include "sc7180-trogdor-coachz-r3.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev2+) with LTE";
+ model = "Google CoachZ (rev3+) with LTE";
compatible = "google,coachz-sku0", "qcom,sc7180";
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r2.dts b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r3.dts
index 4f69b6ba29..a02d2d57c7 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r2.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r3.dts
@@ -2,7 +2,7 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
/dts-v1/;
@@ -10,6 +10,6 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev2+)";
+ model = "Google CoachZ (rev3+)";
compatible = "google,coachz", "qcom,sc7180";
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz.dtsi b/dts/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
index 4c6e433c82..6f9c071475 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
+++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
@@ -23,8 +23,53 @@ ap_h1_spi: &spi0 {};
adau7002: audio-codec-1 {
compatible = "adi,adau7002";
IOVDD-supply = <&pp1800_l15a>;
+ wakeup-delay-ms = <15>;
#sound-dai-cells = <0>;
};
+
+ thermal-zones {
+ skin_temp_thermal: skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150_adc_tm 1>;
+ sustainable-power = <814>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <42000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <45000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <60000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
&ap_spi_fp {
@@ -77,6 +122,25 @@ ap_ts_pen_1v8: &i2c4 {
compatible = "boe,nv110wtm-n61";
};
+&pm6150_adc {
+ skin-temp-thermistor@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ skin-temp-thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
index 5c997cd900..30e3e769d2 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev0", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
index d9fbcc7bc5..c2ef06367b 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
index ea8c2ee097..b474df47cd 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
@@ -14,12 +14,3 @@
model = "Google Lazor (rev3+)";
compatible = "google,lazor", "qcom,sc7180";
};
-
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi b/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
index 6b10b96173..00535aaa43 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
+++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
@@ -21,6 +21,15 @@ ap_h1_spi: &spi0 {};
semtech,avg-pos-strength = <64>;
};
+/*
+ * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
+ * not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
index e720e7bd0d..e122a6b481 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
@@ -9,11 +9,23 @@
#include "sc7180-trogdor-pompom.dtsi"
+/delete-node/ &keyboard_controller;
+#include <arm/cros-ec-keyboard.dtsi>
+
/ {
model = "Google Pompom (rev1)";
compatible = "google,pompom-rev1", "qcom,sc7180";
};
+/*
+ * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
index 791d496ad0..00e187c08e 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
@@ -9,6 +9,6 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google Pompom (rev2+) with LTE";
- compatible = "google,pompom-sku0", "qcom,sc7180";
+ model = "Google Pompom (rev2) with LTE";
+ compatible = "google,pompom-rev2-sku0", "qcom,sc7180";
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
index 984d7337da..4f32e6733f 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
@@ -10,35 +10,15 @@
#include "sc7180-trogdor-pompom.dtsi"
/ {
- model = "Google Pompom (rev2+)";
- compatible = "google,pompom", "qcom,sc7180";
+ model = "Google Pompom (rev2)";
+ compatible = "google,pompom-rev2", "qcom,sc7180";
};
-&keyboard_controller {
- function-row-physmap = <
- MATRIX_KEY(0x00, 0x02, 0) /* T1 */
- MATRIX_KEY(0x03, 0x02, 0) /* T2 */
- MATRIX_KEY(0x02, 0x02, 0) /* T3 */
- MATRIX_KEY(0x01, 0x02, 0) /* T4 */
- MATRIX_KEY(0x03, 0x04, 0) /* T5 */
- MATRIX_KEY(0x02, 0x04, 0) /* T6 */
- MATRIX_KEY(0x01, 0x04, 0) /* T7 */
- MATRIX_KEY(0x02, 0x09, 0) /* T8 */
- MATRIX_KEY(0x01, 0x09, 0) /* T9 */
- MATRIX_KEY(0x00, 0x04, 0) /* T10 */
- >;
- linux,keymap = <
- MATRIX_KEY(0x00, 0x02, KEY_BACK)
- MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
- MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
- MATRIX_KEY(0x01, 0x02, KEY_SCALE)
- MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
- MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
- MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
- MATRIX_KEY(0x02, 0x09, KEY_MUTE)
- MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
- MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
- CROS_STD_MAIN_KEYMAP
- >;
+/*
+ * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts
new file mode 100644
index 0000000000..e90b73c353
--- /dev/null
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "sc7180-trogdor-pompom-r3.dts"
+#include "sc7180-trogdor-lte-sku.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+) with LTE";
+ compatible = "google,pompom-sku0", "qcom,sc7180";
+};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts
new file mode 100644
index 0000000000..f8aac63a53
--- /dev/null
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-pompom.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+)";
+ compatible = "google,pompom", "qcom,sc7180";
+};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/dts/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index 622b5f1b88..a246dbd74c 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -107,6 +107,35 @@ ap_ts_pen_1v8: &i2c4 {
};
};
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
&panel {
compatible = "kingdisplay,kd116n21-30nv-a010";
};
diff --git a/dts/src/arm64/qcom/sc7180-trogdor.dtsi b/dts/src/arm64/qcom/sc7180-trogdor.dtsi
index 24d293ef56..77ae7561d4 100644
--- a/dts/src/arm64/qcom/sc7180-trogdor.dtsi
+++ b/dts/src/arm64/qcom/sc7180-trogdor.dtsi
@@ -64,11 +64,6 @@
no-map;
};
- camera_mem: memory@8ec00000 {
- reg = <0x0 0x8ec00000 0x0 0x500000>;
- no-map;
- };
-
venus_mem: memory@8f600000 {
reg = <0 0x8f600000 0 0x500000>;
no-map;
@@ -335,8 +330,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
- /* TODO: Increase frequency after testing */
- spi-max-frequency = <25000000>;
+ spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
@@ -564,10 +558,6 @@
#size-cells = <0>;
};
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
-
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
@@ -655,6 +645,8 @@ edp_brij_i2c: &i2c2 {
clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -772,7 +764,7 @@ hp_i2c: &i2c9 {
qcom,capture-sd-lines = <0>;
};
- mi2s@1 {
+ secondary_mi2s: mi2s@1 {
reg = <MI2S_SECONDARY>;
qcom,playback-sd-lines = <0>;
};
@@ -805,7 +797,7 @@ hp_i2c: &i2c9 {
};
};
-&pm6150_pwrkey {
+&pm6150_pon {
status = "disabled";
};
@@ -981,6 +973,7 @@ ap_spi_fp: &spi10 {
&qspi_clk {
pinconf {
pins = "gpio63";
+ drive-strength = <8>;
bias-disable;
};
};
@@ -1494,4 +1487,106 @@ ap_spi_fp: &spi10 {
drive-strength = <2>;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi
index 6228ba2d85..a5d58eb928 100644
--- a/dts/src/arm64/qcom/sc7180.dtsi
+++ b/dts/src/arm64/qcom/sc7180.dtsi
@@ -701,8 +701,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -726,15 +727,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <100000 100000>;
- opp-avg-kBps = <100000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <600000 900000>;
- opp-avg-kBps = <261438 300000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <390000 0>;
};
};
};
@@ -768,8 +769,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -1059,8 +1058,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -1871,108 +1868,6 @@
function = "lpass_ext";
};
};
-
- sdc1_on: sdc1-on {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc1_off: sdc1-off {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc2_on: sdc2-on {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- sdc2_off: sdc2-off {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-disable;
- drive-strength = <2>;
- };
- };
};
remoteproc_mpss: remoteproc@4080000 {
@@ -2670,8 +2565,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
@@ -2689,15 +2585,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <160000 100000>;
- opp-avg-kBps = <80000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <200000 120000>;
- opp-avg-kBps = <100000 60000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <200000 0>;
};
};
};
@@ -2754,8 +2650,8 @@
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
+ <0 0x088e8000 0 0x3c>,
+ <0 0x088ea000 0 0x18c>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -2860,7 +2756,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/sc7280-idp.dts b/dts/src/arm64/qcom/sc7280-idp.dts
index 54d2cb365b..3900cfc095 100644
--- a/dts/src/arm64/qcom/sc7280-idp.dts
+++ b/dts/src/arm64/qcom/sc7280-idp.dts
@@ -7,11 +7,19 @@
/dts-v1/;
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include "sc7280.dtsi"
+#include "pm7325.dtsi"
+#include "pmr735a.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
- compatible = "qcom,sc7280-idp", "qcom,sc7280";
+ compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280";
aliases {
serial0 = &uart5;
@@ -234,6 +242,32 @@
};
};
+&pmk8350_vadc {
+ pm8350_die_temp {
+ reg = <PM8350_ADC7_DIE_TEMP>;
+ label = "pm8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmk8350_die_temp {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735a_die_temp {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ label = "pmr735a_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735b_die_temp {
+ reg = <PMR735B_ADC7_DIE_TEMP>;
+ label = "pmr735b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/dts/src/arm64/qcom/sc7280.dtsi b/dts/src/arm64/qcom/sc7280.dtsi
index 2cc4785539..a8c274ad74 100644
--- a/dts/src/arm64/qcom/sc7280.dtsi
+++ b/dts/src/arm64/qcom/sc7280.dtsi
@@ -11,7 +11,10 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -51,6 +54,11 @@
no-map;
};
+ smem_mem: memory@80900000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ no-map;
+ };
+
cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -70,6 +78,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -88,6 +98,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -103,6 +115,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +132,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +149,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -148,6 +166,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -163,6 +183,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -178,6 +200,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -251,6 +275,125 @@
};
};
+ clk_virt: interconnect {
+ compatible = "qcom,sc7280-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ wpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -316,6 +459,93 @@
};
};
+ cnoc2: interconnect@1500000 {
+ reg = <0 0x01500000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc2";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc3: interconnect@1502000 {
+ reg = <0 0x01502000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc3";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@1580000 {
+ reg = <0 0x01580000 0 0x4>;
+ compatible = "qcom,sc7280-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ reg = <0 0x01680000 0 0x15480>;
+ compatible = "qcom,sc7280-system-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sc7280-aggre1-noc";
+ reg = <0 0x016e0000 0 0x1c080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ reg = <0 0x01700000 0 0x2b080>;
+ compatible = "qcom,sc7280-aggre2-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1740000 {
+ reg = <0 0x01740000 0 0x1e080>;
+ compatible = "qcom,sc7280-mmss-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex", "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+ <0 0x03c04000 0 0x4>,
+ <0 0x03389000 0 0x24>;
+ reg-names = "qdsp6ss", "top_cc", "cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ reg = <0 0x03c40000 0 0xf080>;
+ compatible = "qcom,sc7280-lpass-ag-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc7280-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
@@ -805,6 +1035,20 @@
};
};
+ dc_noc: interconnect@90e0000 {
+ reg = <0 0x090e0000 0 0x5080>;
+ compatible = "qcom,sc7280-dc-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ reg = <0 0x9100000 0 0xe2200>;
+ compatible = "qcom,sc7280-gem-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
@@ -812,6 +1056,42 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ nsp_noc: interconnect@a0c0000 {
+ reg = <0 0x0a0c0000 0 0x10000>;
+ compatible = "qcom,sc7280-nsp-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sc7280-videocc";
+ reg = <0 0xaaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sc7280-dispcc";
+ reg = <0 0xaf00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
@@ -825,6 +1105,40 @@
interrupt-controller;
};
+ pdc_reset: reset-controller@b5e0000 {
+ compatible = "qcom,sc7280-pdc-global";
+ reg = <0 0x0b5e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <12>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
@@ -1063,6 +1377,10 @@
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
rpmhpd: power-controller {
compatible = "qcom,sc7280-rpmhpd";
#power-domain-cells = <1>;
@@ -1116,6 +1434,859 @@
#clock-cells = <1>;
};
};
+
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu0_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu1_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu2_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu3_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu4_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu5_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu6_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu7_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu8-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu8_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu8_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu8_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu9-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu9_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu9_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu9_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu10-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu10_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu10_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu10_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu11-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu11_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu11_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu11_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0_crit: aoss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss1_crit: aoss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss0_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss1_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss0_crit: gpuss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss1_crit: gpuss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ nspss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss0_crit: nspss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ nspss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss1_crit: nspss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ video_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video_crit: video-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ ddr_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ ddr_crit: ddr-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ mdmss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss0_crit: mdmss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ mdmss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss1_crit: mdmss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ mdmss2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss2_crit: mdmss2-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ mdmss3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss3_crit: mdmss3-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ camera0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0_crit: camera0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
};
timer {
diff --git a/dts/src/arm64/qcom/sdm845-cheza.dtsi b/dts/src/arm64/qcom/sdm845-cheza.dtsi
index 216a74f005..dfd1b42c07 100644
--- a/dts/src/arm64/qcom/sdm845-cheza.dtsi
+++ b/dts/src/arm64/qcom/sdm845-cheza.dtsi
@@ -714,10 +714,6 @@ ap_ts_i2c: &i2c14 {
#address-cells = <1>;
#size-cells = <0>;
};
-
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
};
};
diff --git a/dts/src/arm64/qcom/sdm845-mtp.dts b/dts/src/arm64/qcom/sdm845-mtp.dts
index 1372fe8601..91ede9296a 100644
--- a/dts/src/arm64/qcom/sdm845-mtp.dts
+++ b/dts/src/arm64/qcom/sdm845-mtp.dts
@@ -448,6 +448,11 @@
clock-frequency = <400000>;
};
+&ipa {
+ status = "okay";
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi b/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi
index 8f617f7b6d..4d052e39b3 100644
--- a/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi
+++ b/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi
@@ -46,6 +46,14 @@
};
reserved-memory {
+ /* The rmtfs_mem needs to be guarded due to "XPU limitations"
+ * it is otherwise possible for an allocation adjacent to the
+ * rmtfs_mem region to trigger an XPU violation, causing a crash.
+ */
+ rmtfs_lower_guard: memory@f5b00000 {
+ no-map;
+ reg = <0 0xf5b00000 0 0x1000>;
+ };
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
* but given the same address every time. Hard code it as this address is
@@ -59,6 +67,10 @@
qcom,client-id = <1>;
qcom,vmid = <15>;
};
+ rmtfs_upper_guard: memory@f5d01000 {
+ no-map;
+ reg = <0 0xf5d01000 0 0x2000>;
+ };
/*
* It seems like reserving the old rmtfs_mem region is also needed to prevent
@@ -387,6 +399,12 @@
};
};
+&ipa {
+ status = "okay";
+
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts b/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
index 7d02942533..c60c8c640e 100644
--- a/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
+++ b/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
@@ -5,6 +5,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
@@ -311,6 +313,28 @@
};
};
+/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */
+&q6afedai {
+ qi2s@22 {
+ reg = <22>;
+ qcom,sd-lines = <0>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -328,6 +352,70 @@
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
};
+&sound {
+ compatible = "qcom,db845c-sndcard";
+ pinctrl-0 = <&quat_mi2s_active
+ &quat_mi2s_sd0_active>;
+ pinctrl-names = "default";
+ model = "Xiaomi Poco F1";
+ audio-routing =
+ "RX_BIAS", "MCLK",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 0>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 1>;
+ };
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
@@ -356,6 +444,15 @@
function = "gpio";
bias-pull-up;
};
+
+ wcd_intr_default: wcd_intr_default {
+ pins = <54>;
+ function = "gpio";
+
+ input-enable;
+ bias-pull-down;
+ drive-strength = <2>;
+ };
};
&uart6 {
@@ -416,6 +513,23 @@
vdda-pll-supply = <&vreg_l1a_0p875>;
};
+&wcd9340{
+ pinctrl-0 = <&wcd_intr_default>;
+ pinctrl-names = "default";
+ clock-names = "extclk";
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ reset-gpios = <&tlmm 64 0>;
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
+ qcom,micbias1-microvolt = <2700000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <2700000>;
+ qcom,micbias4-microvolt = <2700000>;
+};
+
&wifi {
status = "okay";
diff --git a/dts/src/arm64/qcom/sdm845.dtsi b/dts/src/arm64/qcom/sdm845.dtsi
index 0a86fe71a6..1796ae8372 100644
--- a/dts/src/arm64/qcom/sdm845.dtsi
+++ b/dts/src/arm64/qcom/sdm845.dtsi
@@ -3781,7 +3781,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -3829,7 +3829,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_2_dwc3: dwc3@a800000 {
+ usb_2_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
index 140db2d5ba..c2a709a384 100644
--- a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
@@ -376,6 +376,8 @@
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm64/qcom/sm8150-hdk.dts b/dts/src/arm64/qcom/sm8150-hdk.dts
index fb2cf3d987..335aa0753f 100644
--- a/dts/src/arm64/qcom/sm8150-hdk.dts
+++ b/dts/src/arm64/qcom/sm8150-hdk.dts
@@ -354,22 +354,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/dts/src/arm64/qcom/sm8150-microsoft-surface-duo.dts b/dts/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
new file mode 100644
index 0000000000..736da9af44
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (C) 2021, Microsoft Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/ {
+ model = "Microsoft Surface Duo";
+ compatible = "microsoft,surface-duo", "qcom,sm8150";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ vol_up {
+ label = "Volume Up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s5a_2p0: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vdda_wcss_pll:
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_pdphy:
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_csi_0_0p9:
+ vdda_csi_1_0p9:
+ vdda_csi_2_0p9:
+ vdda_csi_3_0p9:
+ vdda_dsi_0_0p9:
+ vdda_dsi_1_0p9:
+ vdda_dsi_0_pll_0p9:
+ vdda_dsi_1_pll_0p9:
+ vdda_pcie_1ln_core:
+ vdda_pcie_2ln_core:
+ vdda_pll_hv_cc_ebi01:
+ vdda_pll_hv_cc_ebi23:
+ vdda_qrefs_0p875_5:
+ vdda_sp_sensor:
+ vdda_ufs_2ln_core_1:
+ vdda_ufs_2ln_core_2:
+ vdda_usb_ss_dp_core_1:
+ vdda_usb_ss_dp_core_2:
+ vdda_qlink_lv:
+ vdda_qlink_lv_ck:
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_10:
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_qfprom:
+ vdd_qfprom_sp:
+ vdda_apc_cs_1p8:
+ vdda_gfx_cs_1p8:
+ vdda_usb_hs_1p8:
+ vdda_qrefs_vref_1p8:
+ vddpx_10_a:
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_wcss_adcdac_1:
+ vdda_wcss_adcdac_22:
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_hv_ebi0:
+ vdda_hv_ebi1:
+ vdda_hv_ebi2:
+ vdda_hv_ebi3:
+ vdda_hv_refgen0:
+ vdda_qlink_hv_ck:
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_5:
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_6:
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_2:
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+
+ vdd-l2-supply = <&vreg_s8c_1p3>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f_2p85: ldo5 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p85: ldo6 {
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <2856000>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+
+ da7280@4a {
+ compatible = "dlg,da7280";
+ reg = <0x4a>;
+ interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "da7280_default";
+ pinctrl-0 = <&da7280_intr_default>;
+
+ dlg,actuator-type = "LRA";
+ dlg,dlg,const-op-mode = <1>;
+ dlg,dlg,periodic-op-mode = <1>;
+ dlg,nom-microvolt = <2000000>;
+ dlg,abs-max-microvolt = <2000000>;
+ dlg,imax-microamp = <129000>;
+ dlg,resonant-freq-hz = <180>;
+ dlg,impd-micro-ohms = <14300000>;
+ dlg,freq-track-enable;
+ dlg,bemf-sens-enable;
+ dlg,mem-array = <
+ 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a
+ 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29
+ 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01
+ 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06
+ 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08
+ 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84
+ 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e
+ 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ >;
+ };
+
+ /* SMB1381 @ 0x44 */
+ /* MAX34417 @ 0x1c */
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* SMB1355 @ 0x0c */
+ /* SMB1390 @ 0x10 */
+};
+
+&i2c17 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+};
+
+&i2c19 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* MAX34417 @ 0x12 */
+ /* MAX34417 @ 0x1a */
+ /* MAX34417 @ 0x1e */
+};
+
+&pon {
+ pwrkey {
+ status = "okay";
+ };
+
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/adsp.mdt";
+};
+
+&remoteproc_cdsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/cdsp.mdt";
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/modem.mdt";
+};
+
+&remoteproc_slpi {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/slpi.mdt";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+
+ da7280_intr_default: da7280-intr-default {
+ pins = "gpio42";
+ function = "gpio";
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p5>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l9a_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
+ vdda-max-microamp = <90200>;
+ vdda-pll-supply = <&vreg_l3c_1p2>;
+ vdda-pll-max-microamp = <19000>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&wifi {
+ status = "okay";
+
+ vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>;
+ vdd-3.3-ch0-supply = <&vreg_l11c_3p3>;
+};
diff --git a/dts/src/arm64/qcom/sm8150-mtp.dts b/dts/src/arm64/qcom/sm8150-mtp.dts
index 3774f8e634..53edf75411 100644
--- a/dts/src/arm64/qcom/sm8150-mtp.dts
+++ b/dts/src/arm64/qcom/sm8150-mtp.dts
@@ -349,22 +349,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts
new file mode 100644
index 0000000000..3b55fdda76
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 5";
+ compatible = "sony,bahamut-generic", "qcom,sm8150";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
diff --git a/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts
new file mode 100644
index 0000000000..6f490ec284
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 1";
+ compatible = "sony,griffin-generic", "qcom,sm8150";
+};
diff --git a/dts/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
new file mode 100644
index 0000000000..014fe3a315
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &venus_mem;
+
+/ {
+ qcom,msm-id = <339 0x20000>; /* SM8150 v2 */
+ qcom,board-id = <8 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's (going to be) a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet (& no dispcc either)..
+ */
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ mpss_mem: memory@8dc00000 {
+ reg = <0x0 0x8dc00000 0x0 0x9600000>;
+ no-map;
+ };
+
+ venus_mem: memory@97200000 {
+ reg = <0x0 0x97200000 0x0 0x500000>;
+ no-map;
+ };
+
+ slpi_mem: memory@97700000 {
+ reg = <0x0 0x97700000 0x0 0x1400000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@98b00000 {
+ reg = <0x0 0x98b00000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@98b10000 {
+ reg = <0x0 0x98b10000 0x0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: memory@98b15000 {
+ reg = <0x0 0x98b15000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: memory@98c00000 {
+ reg = <0x0 0x98c00000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: memory@98d00000 {
+ reg = <0x0 0x98d00000 0x0 0x1400000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2400000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@a4c00000 {
+ reg = <0x0 0xa4c00000 0x0 0x3c00000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp_mem {
+ reg = <0x0 0x8be00000 0x0 0x1e00000>;
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s2a_0p6: smps2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p8: ldo18 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s1c_1p1: smps1 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /* PM8009 is not present on these boards, even if downstream sources suggest so. */
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Qcom SMB1355 @ c */
+ /* Qcom SMB1390 @ 10 */
+ /* NXP PN553 NFC @ 28 */
+ /* Qcom FSA4480 USB-C audio switch @ 43 */
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c10 {
+ status = "okay";
+
+ /* Samsung touchscreen @ 48 */
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l5a_0p875>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p8>;
+};
diff --git a/dts/src/arm64/qcom/sm8150.dtsi b/dts/src/arm64/qcom/sm8150.dtsi
index 51235a9521..612dda0fef 100644
--- a/dts/src/arm64/qcom/sm8150.dtsi
+++ b/dts/src/arm64/qcom/sm8150.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -577,6 +578,29 @@
<&sleep_clk>;
};
+ gpi_dma0: dma-controller@800000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0x800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x00d6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -695,6 +719,29 @@
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xa00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x0616 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -795,6 +842,29 @@
};
};
+ gpi_dma2: dma-controller@c00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xc00000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x07b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@cc0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00cc0000 0x0 0x6000>;
@@ -1082,6 +1152,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1149,6 +1221,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1496,6 +1570,8 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ status = "disabled";
+
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
@@ -2268,7 +2344,7 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/qcom/sm8250-hdk.dts b/dts/src/arm64/qcom/sm8250-hdk.dts
index c3a2c5aa6f..47742816ac 100644
--- a/dts/src/arm64/qcom/sm8250-hdk.dts
+++ b/dts/src/arm64/qcom/sm8250-hdk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include <dt-bindings/gpio/gpio.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -365,22 +364,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&tlmm {
@@ -452,3 +455,7 @@
&usb_2_dwc3 {
dr_mode = "host";
};
+
+&venus {
+ status = "okay";
+};
diff --git a/dts/src/arm64/qcom/sm8250-mtp.dts b/dts/src/arm64/qcom/sm8250-mtp.dts
index cfc4d1febe..062b944be9 100644
--- a/dts/src/arm64/qcom/sm8250-mtp.dts
+++ b/dts/src/arm64/qcom/sm8250-mtp.dts
@@ -465,7 +465,13 @@
firmware-name = "qcom/sm8250/cdsp.mbn";
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -691,3 +697,7 @@
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p9>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts b/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts
new file mode 100644
index 0000000000..79afeb07f4
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 1 II";
+ compatible = "sony,pdx203-generic", "qcom,sm8250";
+};
+
+/delete-node/ &vreg_l7f_1p8;
diff --git a/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts b/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts
new file mode 100644
index 0000000000..16c96e8385
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 5 II";
+ compatible = "sony,pdx206-generic", "qcom,sm8250";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
+
+&gpio_keys {
+ g-assist-key {
+ label = "Google Assistant Key";
+ linux,code = <KEY_LEFTMETA>;
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+};
+
+&vreg_l2f_1p3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+};
diff --git a/dts/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/dts/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
new file mode 100644
index 0000000000..d63f7a9bc4
--- /dev/null
+++ b/dts/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8250.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+/delete-node/ &adsp_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &cdsp_secure_heap;
+
+/ {
+ qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */
+ qcom,board-id = <0x10008 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet..
+ */
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ power-domains = <&dispcc MDSS_GDSC>;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ /*
+ * Camera focus (light press) and camera snapshot (full press)
+ * seem not to work properly.. Adding the former one stalls the CPU
+ * and the latter kills the volume down key for whatever reason. In any
+ * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1).
+ */
+
+ vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S6c is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s6c_0p88: smpc6-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s6c_0p88";
+
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ adsp_mem: memory@8a100000 {
+ reg = <0x0 0x8a100000 0x0 0x2500000>;
+ no-map;
+ };
+
+ spss_mem: memory@8c600000 {
+ reg = <0x0 0x8c600000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap: memory@8c700000 {
+ reg = <0x0 0x8c700000 0x0 0x4600000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2300000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p2>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ /* (S1+S2+S3) - cx.lvl (ARC) */
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-name = "vreg_s5a_1p9";
+ regulator-min-microvolt = <1824000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p6: smps6 {
+ regulator-name = "vreg_s6a_0p6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-name = "vreg_l2a_3p1";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p9: ldo3 {
+ regulator-name = "vreg_l3a_0p9";
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L4 - lmx.lvl (ARC) */
+
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L7 is unused. */
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-name = "vreg_l9a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L10 is unused, L11 - lcx.lvl (ARC) */
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L15 & L16 are unused. */
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-name = "vreg_l17a_3p0";
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p9: ldo18 {
+ regulator-name = "vreg_l18a_0p9";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /*
+ * Remaining regulators that are not yet supported:
+ * OLEDB: 4925000-8100000
+ * ab: 4600000-6100000
+ * ibb: 800000-5400000
+ */
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p2>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ /*
+ * S1-S6 are ARCs:
+ * (S1+S2) - gfx.lvl,
+ * S3 - mx.lvl,
+ * (S4+S5) - mmcx.lvl,
+ * S6 - ebi.lvl
+ */
+
+ vreg_s7c_0p35: smps7 {
+ regulator-name = "vreg_s7c_0p35";
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p2: smps8 {
+ regulator-name = "vreg_s8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L2-4 are unused. */
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-name = "vreg_l5c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-name = "vreg_l6c_2p9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_2p85: ldo7 {
+ regulator-name = "vreg_l7c_2p85";
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-name = "vreg_l9c_2p9";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3296000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p0: ldo11 {
+ regulator-name = "vreg_l11c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+ vdd-l2-supply = <&vreg_s8c_1p2>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_s4a_1p8>;
+
+ vreg_s1f_1p2: smps1 {
+ regulator-name = "vreg_s1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2f_0p5: smps2 {
+ regulator-name = "vreg_s2f_0p5";
+ regulator-min-microvolt = <512000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L1 is unused. */
+
+ vreg_l2f_1p3: ldo2 {
+ regulator-name = "vreg_l2f_1p3";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L3 & L4 are unused. */
+
+ vreg_l5f_2p8: ldo5 {
+ regulator-name = "vreg_l5f_2p85";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p8: ldo6 {
+ regulator-name = "vreg_l6f_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f_1p8: ldo7 {
+ regulator-name = "vreg_l7f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&cdsp {
+ status = "okay";
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* NXP PN553 NFC @ 28 */
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Dialog SLG51000 CMIC @ 75 */
+};
+
+&i2c9 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c13 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ /* It's "vddio" downstream but it works anyway! */
+ vdd-supply = <&vreg_l1c_1p8>;
+ avdd-supply = <&vreg_l10c_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_default>;
+ };
+};
+
+&i2c15 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Qcom SMB1390 @ 10 */
+ /* Silicon Labs SI4704 FM Radio Receiver @ 11 */
+ /* Qcom SMB1390_slave @ 18 */
+ /* HALO HL6111R Qi charger @ 25 */
+ /* Richwave RTC6226 FM Radio Receiver @ 64 */
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pcie2 {
+ status = "okay";
+
+ pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>;
+};
+
+&pcie2_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEUP>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9c_2p9>;
+ vqmmc-supply = <&vreg_l6c_2p9>;
+ bus-width = <4>;
+ no-sdio;
+ no-emmc;
+};
+
+&slpi {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <40 4>, <52 4>;
+
+ sdc2_default_state: sdc2-default {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ mdm2ap_default: mdm2ap-default {
+ pins = "gpio1", "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default {
+ pins = "gpio39";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disabled;
+ input-enable;
+ };
+
+ ap2mdm_default: ap2mdm-default {
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sdc2_card_det_n: sd-card-det-n {
+ pins = "gpio77";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&uart12 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l9a_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p9>;
+};
diff --git a/dts/src/arm64/qcom/sm8250.dtsi b/dts/src/arm64/qcom/sm8250.dtsi
index 4c0de12aab..4798368b02 100644
--- a/dts/src/arm64/qcom/sm8250.dtsi
+++ b/dts/src/arm64/qcom/sm8250.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -519,6 +521,26 @@
};
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00800000 0 0x70000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x76 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -714,6 +736,29 @@
};
};
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00900000 0 0x70000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <15>;
+ dma-channel-mask = <0x7ff>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -961,6 +1006,26 @@
};
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00a00000 0 0x70000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -1249,6 +1314,12 @@
phys = <&pcie0_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
status = "disabled";
};
@@ -1347,6 +1418,12 @@
phys = <&pcie1_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
status = "disabled";
};
@@ -1447,6 +1524,12 @@
phys = <&pcie2_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_default_state>;
+
status = "disabled";
};
@@ -1470,7 +1553,7 @@
status = "disabled";
- pcie2_lane: lanes@1c0e200 {
+ pcie2_lane: lanes@1c16200 {
reg = <0 0x1c16200 0 0x170>, /* tx0 */
<0 0x1c16400 0 0x200>, /* rx0 */
<0 0x1c16a00 0 0x1f0>, /* pcs */
@@ -1746,6 +1829,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1819,6 +1904,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2323,6 +2410,8 @@
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "bus", "core";
+ status = "disabled";
+
video-decoder {
compatible = "venus-decoder";
};
@@ -2370,7 +2459,7 @@
};
mdss: mdss@ae00000 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
@@ -2402,7 +2491,7 @@
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2424,8 +2513,6 @@
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2499,6 +2586,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2566,6 +2656,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -3395,6 +3488,95 @@
output-high;
};
};
+
+ sdc2_sleep_state: sdc2-sleep {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_default_state: pcie0-default {
+ perst {
+ pins = "gpio79";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio80";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default {
+ perst {
+ pins = "gpio82";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio83";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio84";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_default_state: pcie2-default {
+ perst {
+ pins = "gpio85";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio86";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
apps_smmu: iommu@15000000 {
diff --git a/dts/src/arm64/qcom/sm8350-mtp.dts b/dts/src/arm64/qcom/sm8350-mtp.dts
index 6ca638b4e3..93740444dd 100644
--- a/dts/src/arm64/qcom/sm8350-mtp.dts
+++ b/dts/src/arm64/qcom/sm8350-mtp.dts
@@ -364,3 +364,9 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l5b_0p88>;
};
+
+&ipa {
+ status = "okay";
+
+ memory-region = <&pil_ipa_fw_mem>;
+};
diff --git a/dts/src/arm64/qcom/sm8350.dtsi b/dts/src/arm64/qcom/sm8350.dtsi
index ed0b51bc03..0d16392bb9 100644
--- a/dts/src/arm64/qcom/sm8350.dtsi
+++ b/dts/src/arm64/qcom/sm8350.dtsi
@@ -6,11 +6,13 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
/ {
interrupt-parent = <&intc>;
@@ -391,6 +393,17 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
smp2p-slpi {
@@ -629,6 +642,45 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ipa: ipa@1e40000 {
+ compatible = "qcom,sm8350-ipa";
+
+ iommus = <&apps_smmu 0x5c0 0x0>,
+ <&apps_smmu 0x5c2 0x0>;
+ reg = <0 0x1e40000 0 0x8000>,
+ <0 0x1e50000 0 0x4b20>,
+ <0 0x1e04000 0 0x23000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
+ <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+ interconnect-names = "ipa_to_llcc",
+ "llcc_to_ebi1",
+ "appss_to_ipa";
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -656,7 +708,7 @@
<&rpmhpd 12>;
power-domain-names = "load_state", "cx", "mss";
- interconnects = <&mc_virt 0 &mc_virt 1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
@@ -689,7 +741,7 @@
interrupt-controller;
};
- tsens0: thermal-sensor@c222000 {
+ tsens0: thermal-sensor@c263000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
@@ -700,7 +752,7 @@
#thermal-sensor-cells = <1>;
};
- tsens1: thermal-sensor@c223000 {
+ tsens1: thermal-sensor@c265000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
@@ -1063,7 +1115,7 @@
<&rpmhpd 10>;
power-domain-names = "load_state", "cx", "mxc";
- interconnects = <&compute_noc 1 &mc_virt 1>;
+ interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
@@ -1176,7 +1228,7 @@
};
};
- dc_noc: interconnect@90e0000 {
+ dc_noc: interconnect@90c0000 {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c0000 0 0x4200>;
#interconnect-cells = <1>;
@@ -1317,7 +1369,7 @@
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
diff --git a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi
index d8046fedf9..e3c8b2fe14 100644
--- a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi
+++ b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi
@@ -271,12 +271,12 @@
&ehci0 {
dr_mode = "otg";
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&hdmi0 {
diff --git a/dts/src/arm64/renesas/beacon-renesom-som.dtsi b/dts/src/arm64/renesas/beacon-renesom-som.dtsi
index 8d3a4d6ee8..090dc9c4f5 100644
--- a/dts/src/arm64/renesas/beacon-renesom-som.dtsi
+++ b/dts/src/arm64/renesas/beacon-renesom-som.dtsi
@@ -53,6 +53,8 @@
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
+ clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+ clock-names = "fck", "refclk";
status = "okay";
phy0: ethernet-phy@0 {
@@ -319,8 +321,10 @@
status = "okay";
};
-&usb_extal_clk {
- clock-frequency = <50000000>;
+&usb2_clksel {
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&versaclock5 3>, <&usb3s0_clk>;
+ status = "okay";
};
&usb3s0_clk {
diff --git a/dts/src/arm64/renesas/r8a774a1.dtsi b/dts/src/arm64/renesas/r8a774a1.dtsi
index 46f8dbf689..78c121a89f 100644
--- a/dts/src/arm64/renesas/r8a774a1.dtsi
+++ b/dts/src/arm64/renesas/r8a774a1.dtsi
@@ -76,6 +76,7 @@
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
};
@@ -1127,6 +1128,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a774b1.dtsi b/dts/src/arm64/renesas/r8a774b1.dtsi
index d16a4be5ef..28c612ce49 100644
--- a/dts/src/arm64/renesas/r8a774b1.dtsi
+++ b/dts/src/arm64/renesas/r8a774b1.dtsi
@@ -1001,6 +1001,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi
index 1aef34447a..a5d4dce847 100644
--- a/dts/src/arm64/renesas/r8a774c0.dtsi
+++ b/dts/src/arm64/renesas/r8a774c0.dtsi
@@ -957,6 +957,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a774e1.dtsi b/dts/src/arm64/renesas/r8a774e1.dtsi
index 1f51237ab0..379a130027 100644
--- a/dts/src/arm64/renesas/r8a774e1.dtsi
+++ b/dts/src/arm64/renesas/r8a774e1.dtsi
@@ -1230,6 +1230,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77951.dtsi b/dts/src/arm64/renesas/r8a77951.dtsi
index 85d66d1546..2e4c18b8ee 100644
--- a/dts/src/arm64/renesas/r8a77951.dtsi
+++ b/dts/src/arm64/renesas/r8a77951.dtsi
@@ -1312,6 +1312,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi
index 12476e354d..2bd8169735 100644
--- a/dts/src/arm64/renesas/r8a77960.dtsi
+++ b/dts/src/arm64/renesas/r8a77960.dtsi
@@ -63,18 +63,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -1188,6 +1189,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi
index d980476842..91b501e012 100644
--- a/dts/src/arm64/renesas/r8a77961.dtsi
+++ b/dts/src/arm64/renesas/r8a77961.dtsi
@@ -52,18 +52,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -559,10 +560,19 @@
};
intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77961", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
- /* placeholder */
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
@@ -1144,6 +1154,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77965.dtsi b/dts/src/arm64/renesas/r8a77965.dtsi
index dcb9df861d..ad69da362a 100644
--- a/dts/src/arm64/renesas/r8a77965.dtsi
+++ b/dts/src/arm64/renesas/r8a77965.dtsi
@@ -1050,6 +1050,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77970-eagle.dts b/dts/src/arm64/renesas/r8a77970-eagle.dts
index 874a7fc273..5c84681703 100644
--- a/dts/src/arm64/renesas/r8a77970-eagle.dts
+++ b/dts/src/arm64/renesas/r8a77970-eagle.dts
@@ -73,6 +73,12 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ x1_clk: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
};
&avb {
@@ -104,6 +110,8 @@
};
&du {
+ clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
+ clock-names = "du.0", "dclkin.0";
status = "okay";
};
diff --git a/dts/src/arm64/renesas/r8a77970-v3msk.dts b/dts/src/arm64/renesas/r8a77970-v3msk.dts
index 7417cf5fea..2426e53312 100644
--- a/dts/src/arm64/renesas/r8a77970-v3msk.dts
+++ b/dts/src/arm64/renesas/r8a77970-v3msk.dts
@@ -59,7 +59,7 @@
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
+ reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc5_clk: osc5-clock {
diff --git a/dts/src/arm64/renesas/r8a77970.dtsi b/dts/src/arm64/renesas/r8a77970.dtsi
index e8f6352c36..517892cf62 100644
--- a/dts/src/arm64/renesas/r8a77970.dtsi
+++ b/dts/src/arm64/renesas/r8a77970.dtsi
@@ -612,6 +612,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77980-condor.dts b/dts/src/arm64/renesas/r8a77980-condor.dts
index 04d47c0c9b..7bde0a549c 100644
--- a/dts/src/arm64/renesas/r8a77980-condor.dts
+++ b/dts/src/arm64/renesas/r8a77980-condor.dts
@@ -210,7 +210,7 @@
&mmc0 {
pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins_uhs>;
+ pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
@@ -255,12 +255,6 @@
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
- power-source = <3300>;
- };
-
- mmc_pins_uhs: mmc_uhs {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
power-source = <1800>;
};
diff --git a/dts/src/arm64/renesas/r8a77980.dtsi b/dts/src/arm64/renesas/r8a77980.dtsi
index 7b51d464de..6347d15e66 100644
--- a/dts/src/arm64/renesas/r8a77980.dtsi
+++ b/dts/src/arm64/renesas/r8a77980.dtsi
@@ -664,6 +664,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi
index 0eaea58f42..4d0304bc97 100644
--- a/dts/src/arm64/renesas/r8a77990.dtsi
+++ b/dts/src/arm64/renesas/r8a77990.dtsi
@@ -1000,6 +1000,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a77995.dtsi b/dts/src/arm64/renesas/r8a77995.dtsi
index 2319271c88..84dba37193 100644
--- a/dts/src/arm64/renesas/r8a77995.dtsi
+++ b/dts/src/arm64/renesas/r8a77995.dtsi
@@ -760,6 +760,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
index 14d3db5d6c..f791c76f1b 100644
--- a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
+++ b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
@@ -6,6 +6,27 @@
*/
&i2c0 {
+ pca9654_a: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_b: gpio@22 {
+ compatible = "onnn,pca9654";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_c: gpio@23 {
+ compatible = "onnn,pca9654";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
diff --git a/dts/src/arm64/renesas/r8a779a0.dtsi b/dts/src/arm64/renesas/r8a779a0.dtsi
index 70b3604e56..78ca75f619 100644
--- a/dts/src/arm64/renesas/r8a779a0.dtsi
+++ b/dts/src/arm64/renesas/r8a779a0.dtsi
@@ -618,6 +618,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 211>;
phy-mode = "rgmii";
@@ -665,6 +666,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 212>;
phy-mode = "rgmii";
@@ -712,6 +714,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 213>;
phy-mode = "rgmii";
@@ -759,6 +762,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 214>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 214>;
phy-mode = "rgmii";
@@ -806,6 +810,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 215>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 215>;
phy-mode = "rgmii";
@@ -853,6 +858,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 216>;
phy-mode = "rgmii";
@@ -1096,7 +1102,6 @@
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
fcpvd0: fcp@fea10000 {
diff --git a/dts/src/arm64/renesas/r9a07g044.dtsi b/dts/src/arm64/renesas/r9a07g044.dtsi
new file mode 100644
index 0000000000..734c8adece
--- /dev/null
+++ b/dts/src/arm64/renesas/r9a07g044.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g044-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g044";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_CLK_SCIF0>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g044-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/dts/src/arm64/renesas/r9a07g044l1.dtsi b/dts/src/arm64/renesas/r9a07g044l1.dtsi
new file mode 100644
index 0000000000..9d89d45903
--- /dev/null
+++ b/dts/src/arm64/renesas/r9a07g044l1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/dts/src/arm64/renesas/r9a07g044l2-smarc.dts b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts
new file mode 100644
index 0000000000..d3f72ec62f
--- /dev/null
+++ b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
diff --git a/dts/src/arm64/renesas/r9a07g044l2.dtsi b/dts/src/arm64/renesas/r9a07g044l2.dtsi
new file mode 100644
index 0000000000..91dc10b2cd
--- /dev/null
+++ b/dts/src/arm64/renesas/r9a07g044l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
+};
diff --git a/dts/src/arm64/renesas/rzg2l-smarc.dtsi b/dts/src/arm64/renesas/rzg2l-smarc.dtsi
new file mode 100644
index 0000000000..adcd4f5051
--- /dev/null
+++ b/dts/src/arm64/renesas/rzg2l-smarc.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/px30.dtsi b/dts/src/arm64/rockchip/px30.dtsi
index 09baa8a167..248ebb61aa 100644
--- a/dts/src/arm64/rockchip/px30.dtsi
+++ b/dts/src/arm64/rockchip/px30.dtsi
@@ -244,28 +244,31 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -277,15 +280,17 @@
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -300,8 +305,9 @@
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -311,11 +317,13 @@
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -814,7 +822,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -1087,7 +1095,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1128,7 +1135,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
diff --git a/dts/src/arm64/rockchip/rk3308-roc-cc.dts b/dts/src/arm64/rockchip/rk3308-roc-cc.dts
index 3dddd4742c..665b2e6945 100644
--- a/dts/src/arm64/rockchip/rk3308-roc-cc.dts
+++ b/dts/src/arm64/rockchip/rk3308-roc-cc.dts
@@ -84,8 +84,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
vin-supply = <&vcc5v0_sys>;
};
diff --git a/dts/src/arm64/rockchip/rk3308.dtsi b/dts/src/arm64/rockchip/rk3308.dtsi
index 0c5fa9801e..a185901aba 100644
--- a/dts/src/arm64/rockchip/rk3308.dtsi
+++ b/dts/src/arm64/rockchip/rk3308.dtsi
@@ -164,7 +164,7 @@
grf: grf@ff000000 {
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x10000>;
+ reg = <0x0 0xff000000 0x0 0x08000>;
reboot-mode {
compatible = "syscon-reboot-mode";
@@ -177,6 +177,42 @@
};
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
detect_grf: syscon@ff00b000 {
compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
@@ -579,6 +615,42 @@
status = "disabled";
};
+ usb20_otg: usb@ff400000 {
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
@@ -637,6 +709,28 @@
status = "disabled";
};
+ gmac: ethernet@ff4e0000 {
+ compatible = "rockchip,rk3308-gmac";
+ reg = <0x0 0xff4e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
+ <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC>, <&cru ACLK_MAC>,
+ <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac", "clk_mac_speed";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+ resets = <&cru SRST_MAC_A>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
diff --git a/dts/src/arm64/rockchip/rk3326-odroid-go2.dts b/dts/src/arm64/rockchip/rk3326-odroid-go2.dts
index 49c97f76df..7fc674a99a 100644
--- a/dts/src/arm64/rockchip/rk3326-odroid-go2.dts
+++ b/dts/src/arm64/rockchip/rk3326-odroid-go2.dts
@@ -165,6 +165,31 @@
};
};
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+ };
+
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
@@ -239,6 +264,7 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
port {
@@ -269,11 +295,14 @@
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "xin32k";
+ #sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
@@ -432,6 +461,10 @@
};
};
};
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
};
};
diff --git a/dts/src/arm64/rockchip/rk3328-nanopi-r2s.dts b/dts/src/arm64/rockchip/rk3328-nanopi-r2s.dts
index f807bc066c..3857d487ab 100644
--- a/dts/src/arm64/rockchip/rk3328-nanopi-r2s.dts
+++ b/dts/src/arm64/rockchip/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
@@ -76,8 +77,8 @@
regulator-settling-time-us = <5000>;
regulator-type = "voltage";
startup-delay-us = <2000>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
vin-supply = <&vcc_io_33>;
};
@@ -101,6 +102,18 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vdd_5v_lan: vdd-5v-lan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&lan_vdd_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_5v_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
};
&cpu0 {
@@ -309,6 +322,12 @@
};
};
+ lan {
+ lan_vdd_pin: lan-vdd-pin {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -368,6 +387,19 @@
dr_mode = "host";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Second port is for USB 3.0 */
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
+ };
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/dts/src/arm64/rockchip/rk3328-roc-cc.dts b/dts/src/arm64/rockchip/rk3328-roc-cc.dts
index a05732b59f..aa22a0c222 100644
--- a/dts/src/arm64/rockchip/rk3328-roc-cc.dts
+++ b/dts/src/arm64/rockchip/rk3328-roc-cc.dts
@@ -50,8 +50,8 @@
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
@@ -363,6 +363,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts
index c7e31efdd2..018a3a5075 100644
--- a/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -177,8 +177,6 @@
};
&gmac2phy {
- pinctrl-names = "default";
- pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>;
status = "okay";
};
@@ -382,6 +380,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/dts/src/arm64/rockchip/rk3328-rock64.dts b/dts/src/arm64/rockchip/rk3328-rock64.dts
index 3bef1f39bc..1b0f7e4551 100644
--- a/dts/src/arm64/rockchip/rk3328-rock64.dts
+++ b/dts/src/arm64/rockchip/rk3328-rock64.dts
@@ -381,6 +381,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi
index 3ed69ecbcf..8c821acb21 100644
--- a/dts/src/arm64/rockchip/rk3328.dtsi
+++ b/