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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-03 09:12:13 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-03 09:12:13 +0100 |
commit | 09584e8845c38ebc45347b4fa7607f5949afd37c (patch) | |
tree | 6e8eb34b67d3e9844f796a1824f655ca88f33bff /dts/src/arm | |
parent | 3dd4b2040a3a4011859d92d1cd7818837c02104d (diff) | |
download | barebox-09584e8845c38ebc45347b4fa7607f5949afd37c.tar.gz barebox-09584e8845c38ebc45347b4fa7607f5949afd37c.tar.xz |
dts: update to v5.16-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm')
-rw-r--r-- | dts/src/arm/imx6qp-prtwd3.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/imx6ull-pinfunc.h | 2 | ||||
-rw-r--r-- | dts/src/arm/ls1021a-tsn.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_arria10_socdk_qspi.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_arria5_socdk.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_cyclone5_socdk.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_cyclone5_sockit.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_cyclone5_socrates.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_cyclone5_sodia.dts | 2 | ||||
-rw-r--r-- | dts/src/arm/socfpga_cyclone5_vining_fpga.dts | 4 |
10 files changed, 13 insertions, 9 deletions
diff --git a/dts/src/arm/imx6qp-prtwd3.dts b/dts/src/arm/imx6qp-prtwd3.dts index 7648e8a020..cf6571cc46 100644 --- a/dts/src/arm/imx6qp-prtwd3.dts +++ b/dts/src/arm/imx6qp-prtwd3.dts @@ -178,6 +178,8 @@ label = "cpu"; ethernet = <&fec>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; fixed-link { speed = <100>; diff --git a/dts/src/arm/imx6ull-pinfunc.h b/dts/src/arm/imx6ull-pinfunc.h index eb025a9d47..7328d4ef85 100644 --- a/dts/src/arm/imx6ull-pinfunc.h +++ b/dts/src/arm/imx6ull-pinfunc.h @@ -82,6 +82,6 @@ #define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 #define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 #define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0 #endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/dts/src/arm/ls1021a-tsn.dts b/dts/src/arm/ls1021a-tsn.dts index ff0ffb2276..1ea32fff41 100644 --- a/dts/src/arm/ls1021a-tsn.dts +++ b/dts/src/arm/ls1021a-tsn.dts @@ -91,6 +91,8 @@ /* Internal port connected to eth2 */ ethernet = <&enet2>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <4>; fixed-link { diff --git a/dts/src/arm/socfpga_arria10_socdk_qspi.dts b/dts/src/arm/socfpga_arria10_socdk_qspi.dts index 2b645642b9..2a74552240 100644 --- a/dts/src/arm/socfpga_arria10_socdk_qspi.dts +++ b/dts/src/arm/socfpga_arria10_socdk_qspi.dts @@ -12,7 +12,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00aa"; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; diff --git a/dts/src/arm/socfpga_arria5_socdk.dts b/dts/src/arm/socfpga_arria5_socdk.dts index 90e676e701..1b02d46496 100644 --- a/dts/src/arm/socfpga_arria5_socdk.dts +++ b/dts/src/arm/socfpga_arria5_socdk.dts @@ -119,7 +119,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q256a"; + compatible = "micron,n25q256a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; diff --git a/dts/src/arm/socfpga_cyclone5_socdk.dts b/dts/src/arm/socfpga_cyclone5_socdk.dts index 6f138b2b26..51bb436784 100644 --- a/dts/src/arm/socfpga_cyclone5_socdk.dts +++ b/dts/src/arm/socfpga_cyclone5_socdk.dts @@ -124,7 +124,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; diff --git a/dts/src/arm/socfpga_cyclone5_sockit.dts b/dts/src/arm/socfpga_cyclone5_sockit.dts index c155ff02eb..cae9ddd5ed 100644 --- a/dts/src/arm/socfpga_cyclone5_sockit.dts +++ b/dts/src/arm/socfpga_cyclone5_sockit.dts @@ -169,7 +169,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; diff --git a/dts/src/arm/socfpga_cyclone5_socrates.dts b/dts/src/arm/socfpga_cyclone5_socrates.dts index 8d5d3996f6..ca18b959e6 100644 --- a/dts/src/arm/socfpga_cyclone5_socrates.dts +++ b/dts/src/arm/socfpga_cyclone5_socrates.dts @@ -80,7 +80,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q256a"; + compatible = "micron,n25q256a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/dts/src/arm/socfpga_cyclone5_sodia.dts b/dts/src/arm/socfpga_cyclone5_sodia.dts index 99a71757cd..3f7aa7bf08 100644 --- a/dts/src/arm/socfpga_cyclone5_sodia.dts +++ b/dts/src/arm/socfpga_cyclone5_sodia.dts @@ -116,7 +116,7 @@ flash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q512a"; + compatible = "micron,n25q512a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; diff --git a/dts/src/arm/socfpga_cyclone5_vining_fpga.dts b/dts/src/arm/socfpga_cyclone5_vining_fpga.dts index a060718758..25874e1b9c 100644 --- a/dts/src/arm/socfpga_cyclone5_vining_fpga.dts +++ b/dts/src/arm/socfpga_cyclone5_vining_fpga.dts @@ -224,7 +224,7 @@ n25q128@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128"; + compatible = "micron,n25q128", "jedec,spi-nor"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; @@ -241,7 +241,7 @@ n25q00@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <1>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; |