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authorSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:46:54 +0100
commit574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (patch)
tree3fbe9ed379bc0d6c536860845e85a4ede4b36bbc /dts/src/arm
parent179dedbc6d85d7ea7c8013513b364a75f32943e8 (diff)
downloadbarebox-574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d.tar.gz
dts: update to v5.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm')
-rw-r--r--dts/src/arm/am335x-baltos.dtsi12
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi22
-rw-r--r--dts/src/arm/am335x-boneblue.dts22
-rw-r--r--dts/src/arm/am335x-chiliboard.dts18
-rw-r--r--dts/src/arm/am335x-cm-t335.dts20
-rw-r--r--dts/src/arm/am335x-evm.dts25
-rw-r--r--dts/src/arm/am335x-evmsk.dts25
-rw-r--r--dts/src/arm/am335x-guardian.dts22
-rw-r--r--dts/src/arm/am335x-igep0033.dtsi25
-rw-r--r--dts/src/arm/am335x-lxm.dts22
-rw-r--r--dts/src/arm/am335x-moxa-uc-2100-common.dtsi17
-rw-r--r--dts/src/arm/am335x-moxa-uc-8100-me-t.dts22
-rw-r--r--dts/src/arm/am335x-netcan-plus-1xx.dts87
-rw-r--r--dts/src/arm/am335x-netcom-plus-2xx.dts95
-rw-r--r--dts/src/arm/am335x-netcom-plus-8xx.dts115
-rw-r--r--dts/src/arm/am335x-osd3358-sm-red.dts22
-rw-r--r--dts/src/arm/am335x-pcm-953.dtsi25
-rw-r--r--dts/src/arm/am335x-pdu001.dts28
-rw-r--r--dts/src/arm/am335x-pepper.dts20
-rw-r--r--dts/src/arm/am335x-pocketbeagle.dts22
-rw-r--r--dts/src/arm/am335x-regor.dtsi21
-rw-r--r--dts/src/arm/am335x-shc.dts17
-rw-r--r--dts/src/arm/am335x-sl50.dts22
-rw-r--r--dts/src/arm/am335x-wega.dtsi26
-rw-r--r--dts/src/arm/am33xx-l4.dtsi27
-rw-r--r--dts/src/arm/am33xx.dtsi99
-rw-r--r--dts/src/arm/am3517.dtsi37
-rw-r--r--dts/src/arm/am3517_mt_ventoux.dts2
-rw-r--r--dts/src/arm/am4372.dtsi33
-rw-r--r--dts/src/arm/am437x-l4.dtsi23
-rw-r--r--dts/src/arm/am571x-idk.dts27
-rw-r--r--dts/src/arm/am572x-idk.dts5
-rw-r--r--dts/src/arm/am574x-idk.dts5
-rw-r--r--dts/src/arm/am57xx-beagle-x15-revb1.dts2
-rw-r--r--dts/src/arm/am57xx-beagle-x15-revc.dts2
-rw-r--r--dts/src/arm/am57xx-idk-common.dtsi5
-rw-r--r--dts/src/arm/armada-38x.dtsi5
-rw-r--r--dts/src/arm/armada-xp-98dx3236.dtsi2
-rw-r--r--dts/src/arm/armada-xp-db-xc3-24g4xg.dts5
-rw-r--r--dts/src/arm/armada-xp.dtsi2
-rw-r--r--dts/src/arm/aspeed-ast2500-evb.dts2
-rw-r--r--dts/src/arm/aspeed-ast2600-evb.dts137
-rw-r--r--dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-cmm.dts66
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-minipack.dts59
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-tiogapass.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-yamp.dts65
-rw-r--r--dts/src/arm/aspeed-bmc-ibm-rainier.dts972
-rw-r--r--dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts58
-rw-r--r--dts/src/arm/aspeed-bmc-inspur-on5263m5.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-intel-s2600wf.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-lenovo-hr630.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-lenovo-hr855xg2.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-opp-lanyang.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-opp-mihawk.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-opp-palmetto.dts2
-rw-r--r--dts/src/arm/aspeed-bmc-opp-romulus.dts5
-rw-r--r--dts/src/arm/aspeed-bmc-opp-swift.dts3
-rw-r--r--dts/src/arm/aspeed-bmc-opp-tacoma.dts1195
-rw-r--r--dts/src/arm/aspeed-bmc-opp-vesnin.dts4
-rw-r--r--dts/src/arm/aspeed-bmc-opp-witherspoon.dts7
-rw-r--r--dts/src/arm/aspeed-bmc-opp-zaius.dts5
-rw-r--r--dts/src/arm/aspeed-bmc-portwell-neptune.dts6
-rw-r--r--dts/src/arm/aspeed-g4.dtsi4
-rw-r--r--dts/src/arm/aspeed-g5.dtsi27
-rw-r--r--dts/src/arm/aspeed-g6-pinctrl.dtsi9
-rw-r--r--dts/src/arm/aspeed-g6.dtsi587
-rw-r--r--dts/src/arm/ast2500-facebook-netbmc-common.dtsi96
-rw-r--r--dts/src/arm/at91-kizbox2-2.dts26
-rw-r--r--dts/src/arm/at91-kizbox2-common.dtsi258
-rw-r--r--dts/src/arm/at91-kizbox2.dts244
-rw-r--r--dts/src/arm/at91-kizbox3-hs.dts309
-rw-r--r--dts/src/arm/at91-kizbox3_common.dtsi412
-rw-r--r--dts/src/arm/at91-sama5d27_som1_ek.dts1
-rw-r--r--dts/src/arm/at91-sama5d2_xplained.dts6
-rw-r--r--dts/src/arm/at91-sama5d4_xplained.dts1
-rw-r--r--dts/src/arm/atlas7-evb.dts2
-rw-r--r--dts/src/arm/bcm-hr2.dtsi2
-rw-r--r--dts/src/arm/bcm2711-rpi-4-b.dts140
-rw-r--r--dts/src/arm/bcm2711.dtsi890
-rw-r--r--dts/src/arm/bcm2835-common.dtsi194
-rw-r--r--dts/src/arm/bcm2835-rpi.dtsi4
-rw-r--r--dts/src/arm/bcm2835.dtsi1
-rw-r--r--dts/src/arm/bcm2836.dtsi1
-rw-r--r--dts/src/arm/bcm2837.dtsi1
-rw-r--r--dts/src/arm/bcm283x-rpi-usb-peripheral.dtsi7
-rw-r--r--dts/src/arm/bcm283x.dtsi190
-rw-r--r--dts/src/arm/bcm47094-luxul-xwc-2000.dts53
-rw-r--r--dts/src/arm/dove.dtsi2
-rw-r--r--dts/src/arm/dra7-l4.dtsi70
-rw-r--r--dts/src/arm/dra7.dtsi51
-rw-r--r--dts/src/arm/e60k02.dtsi306
-rw-r--r--dts/src/arm/emev2.dtsi4
-rw-r--r--dts/src/arm/exynos3250.dtsi13
-rw-r--r--dts/src/arm/exynos4.dtsi14
-rw-r--r--dts/src/arm/exynos4210.dtsi27
-rw-r--r--dts/src/arm/exynos4412.dtsi25
-rw-r--r--dts/src/arm/exynos5.dtsi4
-rw-r--r--dts/src/arm/exynos5250-arndale.dts27
-rw-r--r--dts/src/arm/exynos5250.dtsi41
-rw-r--r--dts/src/arm/exynos5260.dtsi2
-rw-r--r--dts/src/arm/exynos5410.dtsi6
-rw-r--r--dts/src/arm/exynos5420-peach-pit.dts4
-rw-r--r--dts/src/arm/exynos5420.dtsi90
-rw-r--r--dts/src/arm/exynos5422-odroid-core.dtsi117
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-lite.dts4
-rw-r--r--dts/src/arm/exynos54xx.dtsi46
-rw-r--r--dts/src/arm/exynos5800-peach-pi.dts4
-rw-r--r--dts/src/arm/exynos5800.dtsi2
-rw-r--r--dts/src/arm/imx27.dtsi2
-rw-r--r--dts/src/arm/imx31.dtsi2
-rw-r--r--dts/src/arm/imx51.dtsi2
-rw-r--r--dts/src/arm/imx53-qsb-common.dtsi44
-rw-r--r--dts/src/arm/imx53-usbarmory.dts2
-rw-r--r--dts/src/arm/imx6dl-apf6dev.dts49
-rw-r--r--dts/src/arm/imx6dl-colibri-eval-v3.dts39
-rw-r--r--dts/src/arm/imx6dl-yapp4-common.dtsi28
-rw-r--r--dts/src/arm/imx6dl-yapp4-hydra.dts8
-rw-r--r--dts/src/arm/imx6dl.dtsi1
-rw-r--r--dts/src/arm/imx6q-apalis-eval.dts13
-rw-r--r--dts/src/arm/imx6q-apalis-ixora-v1.1.dts13
-rw-r--r--dts/src/arm/imx6q-apalis-ixora.dts13
-rw-r--r--dts/src/arm/imx6q-apf6dev.dts49
-rw-r--r--dts/src/arm/imx6q-dhcom-pdk2.dts8
-rw-r--r--dts/src/arm/imx6q-dhcom-som.dtsi2
-rw-r--r--dts/src/arm/imx6q-gw54xx.dts19
-rw-r--r--dts/src/arm/imx6q.dtsi3
-rw-r--r--dts/src/arm/imx6qdl-apalis.dtsi57
-rw-r--r--dts/src/arm/imx6qdl-apf6.dtsi200
-rw-r--r--dts/src/arm/imx6qdl-apf6dev.dtsi424
-rw-r--r--dts/src/arm/imx6qdl-colibri.dtsi35
-rw-r--r--dts/src/arm/imx6qdl-gw551x.dtsi19
-rw-r--r--dts/src/arm/imx6qdl-rex.dtsi19
-rw-r--r--dts/src/arm/imx6qdl-udoo.dtsi14
-rw-r--r--dts/src/arm/imx6qdl-wandboard.dtsi10
-rw-r--r--dts/src/arm/imx6qdl-zii-rdu2.dtsi7
-rw-r--r--dts/src/arm/imx6sl.dtsi2
-rw-r--r--dts/src/arm/imx6sll-kobo-clarahd.dts324
-rw-r--r--dts/src/arm/imx6sll.dtsi2
-rw-r--r--dts/src/arm/imx6sx.dtsi2
-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dtsi28
-rw-r--r--dts/src/arm/imx6ul-imx6ull-opos6ul.dtsi148
-rw-r--r--dts/src/arm/imx6ul-imx6ull-opos6uldev.dtsi338
-rw-r--r--dts/src/arm/imx6ul-kontron-n6310-s.dts405
-rw-r--r--dts/src/arm/imx6ul-kontron-n6310-som.dtsi95
-rw-r--r--dts/src/arm/imx6ul-kontron-n6311-s.dts16
-rw-r--r--dts/src/arm/imx6ul-kontron-n6311-som.dtsi40
-rw-r--r--dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi418
-rw-r--r--dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi109
-rw-r--r--dts/src/arm/imx6ul-opos6ul.dtsi195
-rw-r--r--dts/src/arm/imx6ul-opos6uldev.dts382
-rw-r--r--dts/src/arm/imx6ul-phytec-phycore-som.dtsi2
-rw-r--r--dts/src/arm/imx6ul.dtsi3
-rw-r--r--dts/src/arm/imx6ull-colibri-eval-v3.dtsi14
-rw-r--r--dts/src/arm/imx6ull-colibri-nonwifi.dtsi2
-rw-r--r--dts/src/arm/imx6ull-colibri-wifi.dtsi2
-rw-r--r--dts/src/arm/imx6ull-colibri.dtsi64
-rw-r--r--dts/src/arm/imx6ull-kontron-n6411-s.dts16
-rw-r--r--dts/src/arm/imx6ull-kontron-n6411-som.dtsi40
-rw-r--r--dts/src/arm/imx6ull-opos6ul.dtsi6
-rw-r--r--dts/src/arm/imx6ull-opos6uldev.dts42
-rw-r--r--dts/src/arm/imx7-colibri-eval-v3.dtsi38
-rw-r--r--dts/src/arm/imx7-colibri.dtsi30
-rw-r--r--dts/src/arm/imx7d.dtsi6
-rw-r--r--dts/src/arm/imx7s.dtsi2
-rw-r--r--dts/src/arm/imx7ulp-evk.dts2
-rw-r--r--dts/src/arm/imx7ulp.dtsi31
-rw-r--r--dts/src/arm/keystone-clocks.dtsi27
-rw-r--r--dts/src/arm/keystone-k2e-clocks.dtsi20
-rw-r--r--dts/src/arm/keystone-k2e-netcp.dtsi21
-rw-r--r--dts/src/arm/keystone-k2hk-netcp.dtsi20
-rw-r--r--dts/src/arm/keystone-k2l-netcp.dtsi20
-rw-r--r--dts/src/arm/kirkwood-synology.dtsi2
-rw-r--r--dts/src/arm/logicpd-som-lv-35xx-devkit.dts2
-rw-r--r--dts/src/arm/logicpd-torpedo-35xx-devkit.dts2
-rw-r--r--dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts19
-rw-r--r--dts/src/arm/logicpd-torpedo-37xx-devkit.dts14
-rw-r--r--dts/src/arm/logicpd-torpedo-baseboard.dtsi14
-rw-r--r--dts/src/arm/logicpd-torpedo-som.dtsi5
-rw-r--r--dts/src/arm/mmp3-dell-ariel.dts94
-rw-r--r--dts/src/arm/mmp3.dtsi527
-rw-r--r--dts/src/arm/motorola-cpcap-mapphone.dtsi10
-rw-r--r--dts/src/arm/motorola-mapphone-common.dtsi786
-rw-r--r--dts/src/arm/mt6323.dtsi27
-rw-r--r--dts/src/arm/omap3-beagle-xm.dts2
-rw-r--r--dts/src/arm/omap3-beagle.dts2
-rw-r--r--dts/src/arm/omap3-cm-t3530.dts2
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-rw-r--r--dts/src/arm/stm32mp157a-dk1.dts77
-rw-r--r--dts/src/arm/stm32mp157c-dk2.dts21
-rw-r--r--dts/src/arm/stm32mp157c-ed1.dts41
-rw-r--r--dts/src/arm/stm32mp157c-ev1.dts3
-rw-r--r--dts/src/arm/stm32mp157c.dtsi23
-rw-r--r--dts/src/arm/sun5i-a10s-olinuxino-micro.dts2
-rw-r--r--dts/src/arm/sun6i-a31.dtsi1
-rw-r--r--dts/src/arm/sun8i-a83t-tbs-a711.dts16
-rw-r--r--dts/src/arm/sun8i-a83t.dtsi9
-rw-r--r--dts/src/arm/sun8i-h3-nanopi-duo2.dts174
-rw-r--r--dts/src/arm/sun8i-h3.dtsi22
-rw-r--r--dts/src/arm/sun8i-r40.dtsi9
-rw-r--r--dts/src/arm/sun9i-a80.dtsi11
-rw-r--r--dts/src/arm/sunxi-h3-h5.dtsi14
-rw-r--r--dts/src/arm/tegra124-nyan-big-emc.dtsi7869
-rw-r--r--dts/src/arm/tegra124-venice2.dts3
-rw-r--r--dts/src/arm/tegra124.dtsi3
-rw-r--r--dts/src/arm/tegra20-cpu-opp-microvolt.dtsi201
-rw-r--r--dts/src/arm/tegra20-cpu-opp.dtsi302
-rw-r--r--dts/src/arm/tegra20-paz00.dts41
-rw-r--r--dts/src/arm/tegra20-trimslice.dts11
-rw-r--r--dts/src/arm/tegra20.dtsi2
-rw-r--r--dts/src/arm/tegra30-apalis-v1.1.dtsi22
-rw-r--r--dts/src/arm/tegra30-apalis.dtsi22
-rw-r--r--dts/src/arm/tegra30-cardhu-a04.dts48
-rw-r--r--dts/src/arm/tegra30-colibri.dtsi22
-rw-r--r--dts/src/arm/tegra30-cpu-opp-microvolt.dtsi801
-rw-r--r--dts/src/arm/tegra30-cpu-opp.dtsi1202
-rw-r--r--dts/src/arm/tegra30.dtsi14
-rw-r--r--dts/src/arm/vf-colibri.dtsi12
-rw-r--r--dts/src/arm/vf500-colibri.dtsi2
-rw-r--r--dts/src/arm/vf610-bk4.dts4
-rw-r--r--dts/src/arm/vf610-zii-scu4-aib.dts12
302 files changed, 20530 insertions, 5746 deletions
diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi
index ed235f2..05e7b5d 100644
--- a/dts/src/arm/am335x-baltos.dtsi
+++ b/dts/src/arm/am335x-baltos.dtsi
@@ -258,18 +258,6 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
#include "tps65910.dtsi"
&tps {
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index 89b4cf2..6c9187b 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -191,38 +191,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
diff --git a/dts/src/arm/am335x-boneblue.dts b/dts/src/arm/am335x-boneblue.dts
index 2f6652e..5811fb8 100644
--- a/dts/src/arm/am335x-boneblue.dts
+++ b/dts/src/arm/am335x-boneblue.dts
@@ -278,38 +278,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c0 {
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256";
diff --git a/dts/src/arm/am335x-chiliboard.dts b/dts/src/arm/am335x-chiliboard.dts
index 8cd81dc..b14a275 100644
--- a/dts/src/arm/am335x-chiliboard.dts
+++ b/dts/src/arm/am335x-chiliboard.dts
@@ -153,30 +153,12 @@
};
/* USB */
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_drvvbus>;
-
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
/* microSD */
&mmc1 {
pinctrl-names = "default";
diff --git a/dts/src/arm/am335x-cm-t335.dts b/dts/src/arm/am335x-cm-t335.dts
index 1fe3b56..c6fe9db 100644
--- a/dts/src/arm/am335x-cm-t335.dts
+++ b/dts/src/arm/am335x-cm-t335.dts
@@ -330,26 +330,6 @@ status = "okay";
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
&epwmss0 {
status = "okay";
diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts
index a001457..6f0a6be 100644
--- a/dts/src/arm/am335x-evm.dts
+++ b/dts/src/arm/am335x-evm.dts
@@ -433,35 +433,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts
index e28a5b8..a97f9df 100644
--- a/dts/src/arm/am335x-evmsk.dts
+++ b/dts/src/arm/am335x-evmsk.dts
@@ -523,35 +523,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&epwmss2 {
status = "okay";
diff --git a/dts/src/arm/am335x-guardian.dts b/dts/src/arm/am335x-guardian.dts
index c9611ea..81e0f63 100644
--- a/dts/src/arm/am335x-guardian.dts
+++ b/dts/src/arm/am335x-guardian.dts
@@ -115,10 +115,6 @@
};
};
-&cppi41dma {
- status = "okay";
-};
-
&elm {
status = "okay";
};
@@ -328,30 +324,12 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
&usb0 {
dr_mode = "peripheral";
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
};
&usb1 {
dr_mode = "host";
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
};
&am33xx_pinmux {
diff --git a/dts/src/arm/am335x-igep0033.dtsi b/dts/src/arm/am335x-igep0033.dtsi
index eabcc8b..c9f354f 100644
--- a/dts/src/arm/am335x-igep0033.dtsi
+++ b/dts/src/arm/am335x-igep0033.dtsi
@@ -217,35 +217,10 @@
pinctrl-0 = <&uart0_pins>;
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
#include "tps65910.dtsi"
&tps {
diff --git a/dts/src/arm/am335x-lxm.dts b/dts/src/arm/am335x-lxm.dts
index a8005e9..fef5828 100644
--- a/dts/src/arm/am335x-lxm.dts
+++ b/dts/src/arm/am335x-lxm.dts
@@ -283,36 +283,14 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rmii";
diff --git a/dts/src/arm/am335x-moxa-uc-2100-common.dtsi b/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
index 671d4a5..6495a12 100644
--- a/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
+++ b/dts/src/arm/am335x-moxa-uc-2100-common.dtsi
@@ -111,27 +111,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
/* Power */
&vbat {
regulator-name = "vbat";
diff --git a/dts/src/arm/am335x-moxa-uc-8100-me-t.dts b/dts/src/arm/am335x-moxa-uc-8100-me-t.dts
index 783d411..244df9c 100644
--- a/dts/src/arm/am335x-moxa-uc-8100-me-t.dts
+++ b/dts/src/arm/am335x-moxa-uc-8100-me-t.dts
@@ -290,36 +290,14 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
#include "tps65910.dtsi"
&tps {
diff --git a/dts/src/arm/am335x-netcan-plus-1xx.dts b/dts/src/arm/am335x-netcan-plus-1xx.dts
new file mode 100644
index 0000000..1e4dbc8
--- /dev/null
+++ b/dts/src/arm/am335x-netcan-plus-1xx.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
+
+/ {
+ model = "NetCAN";
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "can_data";
+ linux,default-trigger = "netdev";
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@2 {
+ label = "can_error";
+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&am33xx_pinmux {
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */
+ >;
+ };
+
+ dcan1_pins: pinmux_dcan1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */
+ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
+
+&dcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins>;
+
+ status = "okay";
+};
diff --git a/dts/src/arm/am335x-netcom-plus-2xx.dts b/dts/src/arm/am335x-netcom-plus-2xx.dts
new file mode 100644
index 0000000..9a6cd8e
--- /dev/null
+++ b/dts/src/arm/am335x-netcom-plus-2xx.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
+
+/ {
+ model = "NetCom Plus";
+};
+
+&am33xx_pinmux {
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */
+ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */
+ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
diff --git a/dts/src/arm/am335x-netcom-plus-8xx.dts b/dts/src/arm/am335x-netcom-plus-8xx.dts
new file mode 100644
index 0000000..2298563
--- /dev/null
+++ b/dts/src/arm/am335x-netcom-plus-8xx.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+
+/ {
+ model = "NetCom Plus";
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dip_switches>;
+
+ dip_switches: pinmux_dip_switches {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ >;
+ };
+
+ tca6416_pins: pinmux_tca6416_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3)
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3)
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&i2c1 {
+ tca6416a: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <20 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tca6416_pins>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416b: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ tca6416c: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
diff --git a/dts/src/arm/am335x-osd3358-sm-red.dts b/dts/src/arm/am335x-osd3358-sm-red.dts
index f47cc9f..1d29020 100644
--- a/dts/src/arm/am335x-osd3358-sm-red.dts
+++ b/dts/src/arm/am335x-osd3358-sm-red.dts
@@ -384,38 +384,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
diff --git a/dts/src/arm/am335x-pcm-953.dtsi b/dts/src/arm/am335x-pcm-953.dtsi
index 9bfa032..6c547c8 100644
--- a/dts/src/arm/am335x-pcm-953.dtsi
+++ b/dts/src/arm/am335x-pcm-953.dtsi
@@ -237,31 +237,6 @@
};
/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-
-&usb1_phy {
- status = "okay";
-};
diff --git a/dts/src/arm/am335x-pdu001.dts b/dts/src/arm/am335x-pdu001.dts
index 3141255..e4dcfa0 100644
--- a/dts/src/arm/am335x-pdu001.dts
+++ b/dts/src/arm/am335x-pdu001.dts
@@ -384,34 +384,6 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
/*
* Disable soc's rtc as we have no VBAT for it. This makes the board
* rtc (Microchip MCP79400) the default rtc device 'rtc0'.
diff --git a/dts/src/arm/am335x-pepper.dts b/dts/src/arm/am335x-pepper.dts
index e7764ec..6d7608d 100644
--- a/dts/src/arm/am335x-pepper.dts
+++ b/dts/src/arm/am335x-pepper.dts
@@ -552,38 +552,18 @@
/* USB */
&usb {
- status = "okay";
-
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
};
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&am33xx_pinmux {
usb_pins: pinmux_usb {
pinctrl-single,pins = <
diff --git a/dts/src/arm/am335x-pocketbeagle.dts b/dts/src/arm/am335x-pocketbeagle.dts
index ff4f919..4da7190 100644
--- a/dts/src/arm/am335x-pocketbeagle.dts
+++ b/dts/src/arm/am335x-pocketbeagle.dts
@@ -206,32 +206,10 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "otg";
};
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-
-&cppi41dma {
- status = "okay";
-};
diff --git a/dts/src/arm/am335x-regor.dtsi b/dts/src/arm/am335x-regor.dtsi
index 5aff02a..6fbf4ac 100644
--- a/dts/src/arm/am335x-regor.dtsi
+++ b/dts/src/arm/am335x-regor.dtsi
@@ -200,24 +200,3 @@
status = "okay";
linux,rs485-enabled-at-boot-time;
};
-
-/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
diff --git a/dts/src/arm/am335x-shc.dts b/dts/src/arm/am335x-shc.dts
index 5b03685..1eaa265 100644
--- a/dts/src/arm/am335x-shc.dts
+++ b/dts/src/arm/am335x-shc.dts
@@ -117,10 +117,6 @@
status = "okay";
};
-&cppi41dma {
- status = "okay";
-};
-
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
@@ -358,20 +354,7 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
diff --git a/dts/src/arm/am335x-sl50.dts b/dts/src/arm/am335x-sl50.dts
index 2f82095..f4684c8 100644
--- a/dts/src/arm/am335x-sl50.dts
+++ b/dts/src/arm/am335x-sl50.dts
@@ -512,36 +512,14 @@
status = "disabled";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "otg";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&mmc1 {
status = "okay";
pinctrl-names = "default";
diff --git a/dts/src/arm/am335x-wega.dtsi b/dts/src/arm/am335x-wega.dtsi
index 61fc4cd..1359bf8 100644
--- a/dts/src/arm/am335x-wega.dtsi
+++ b/dts/src/arm/am335x-wega.dtsi
@@ -191,32 +191,6 @@
status = "okay";
};
-/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb1 {
dr_mode = "host";
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
};
diff --git a/dts/src/arm/am33xx-l4.dtsi b/dts/src/arm/am33xx-l4.dtsi
index 7a9eb2b..3a8a205 100644
--- a/dts/src/arm/am33xx-l4.dtsi
+++ b/dts/src/arm/am33xx-l4.dtsi
@@ -129,7 +129,6 @@
gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
@@ -163,7 +162,6 @@
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
@@ -195,7 +193,6 @@
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
@@ -306,6 +303,13 @@
};
};
+ usb_ctrl_mod: control@620 {
+ compatible = "ti,am335x-usb-ctrl-module";
+ reg = <0x620 0x10>,
+ <0x648 0x4>;
+ reg-names = "phy_ctrl", "wakeup";
+ };
+
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
@@ -368,7 +372,6 @@
target-module@35000 { /* 0x44e35000, ap 29 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
@@ -912,7 +915,6 @@
target-module@22000 { /* 0x48022000, ap 10 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
@@ -944,7 +946,6 @@
target-module@24000 { /* 0x48024000, ap 12 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
@@ -976,7 +977,6 @@
target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
@@ -1046,7 +1046,6 @@
target-module@38000 { /* 0x48038000, ap 16 02.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
@@ -1077,7 +1076,6 @@
target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
@@ -1270,7 +1268,6 @@
target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
@@ -1312,7 +1309,6 @@
target-module@60000 { /* 0x48060000, ap 36 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
@@ -1385,7 +1381,6 @@
target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
@@ -1506,7 +1501,6 @@
target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
@@ -1592,7 +1586,6 @@
target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
@@ -1622,7 +1615,6 @@
target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
@@ -1652,7 +1644,6 @@
target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
@@ -1682,7 +1673,6 @@
target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
@@ -1716,7 +1706,6 @@
target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
@@ -1806,7 +1795,6 @@
target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
@@ -2061,7 +2049,6 @@
target-module@10000 { /* 0x48310000, ap 76 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index fb6b8aa..646f114 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -236,7 +236,6 @@
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
@@ -263,37 +262,38 @@
};
};
- usb: usb@47400000 {
- compatible = "ti,am33xx-usb";
- reg = <0x47400000 0x1000>;
- ranges;
+ usb: target-module@47400000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x47400000 0x4>,
+ <0x47400010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
- ti,hwmods = "usb_otg_hs";
- status = "disabled";
-
- usb_ctrl_mod: control@44e10620 {
- compatible = "ti,am335x-usb-ctrl-module";
- reg = <0x44e10620 0x10
- 0x44e10648 0x4>;
- reg-names = "phy_ctrl", "wakeup";
- status = "disabled";
- };
+ ranges = <0x0 0x47400000 0x5000>;
- usb0_phy: usb-phy@47401300 {
+ usb0_phy: usb-phy@1300 {
compatible = "ti,am335x-usb-phy";
- reg = <0x47401300 0x100>;
+ reg = <0x1300 0x100>;
reg-names = "phy";
- status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
- usb0: usb@47401000 {
+ usb0: usb@1400 {
compatible = "ti,musb-am33xx";
- status = "disabled";
- reg = <0x47401400 0x400
- 0x47401000 0x200>;
+ reg = <0x1400 0x400>,
+ <0x1000 0x200>;
reg-names = "mc", "control";
interrupts = <18>;
@@ -329,20 +329,18 @@
"tx14", "tx15";
};
- usb1_phy: usb-phy@47401b00 {
+ usb1_phy: usb-phy@1b00 {
compatible = "ti,am335x-usb-phy";
- reg = <0x47401b00 0x100>;
+ reg = <0x1b00 0x100>;
reg-names = "phy";
- status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
- usb1: usb@47401800 {
+ usb1: usb@1800 {
compatible = "ti,musb-am33xx";
- status = "disabled";
- reg = <0x47401c00 0x400
- 0x47401800 0x200>;
+ reg = <0x1c00 0x400>,
+ <0x1800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
@@ -377,36 +375,35 @@
"tx14", "tx15";
};
- cppi41dma: dma-controller@47402000 {
+ cppi41dma: dma-controller@2000 {
compatible = "ti,am3359-cppi41";
- reg = <0x47400000 0x1000
- 0x47402000 0x1000
- 0x47403000 0x1000
- 0x47404000 0x4000>;
+ reg = <0x0000 0x1000>,
+ <0x2000 0x1000>,
+ <0x3000 0x1000>,
+ <0x4000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
- status = "disabled";
};
};
- ocmcram: ocmcram@40300000 {
+ ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
ranges = <0x0 0x40300000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
- pm_sram_code: pm-sram-code@0 {
+ pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
- pm_sram_data: pm-sram-data@1000 {
+ pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
@@ -465,3 +462,29 @@
#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"
+
+&prcm {
+ prm_per: prm@c00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xc00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_wkup: prm@d00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xd00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@f00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_gfx: prm@1100 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1100 0x100>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/dts/src/arm/am3517.dtsi b/dts/src/arm/am3517.dtsi
index bf30020..125379e 100644
--- a/dts/src/arm/am3517.dtsi
+++ b/dts/src/arm/am3517.dtsi
@@ -16,6 +16,37 @@
can = &hecc;
};
+ cpus {
+ cpu: cpu@0 {
+ /* Based on OMAP3630 variants OPP50 and OPP100 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
+
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+ /*
+ * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
+ * appear to operate at 300MHz as well. Since AM3517 only
+ * lists one operating voltage, it will remain fixed at 1.2V
+ */
+ opp50-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0xffffffff 0xffffffff>;
+ opp-suspend;
+ };
+
+ opp100-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0xffffffff 0xffffffff>;
+ };
+ };
+
ocp@68000000 {
am35x_otg_hs: am35x_otg_hs@5c040000 {
compatible = "ti,omap3-musb";
@@ -115,6 +146,12 @@
};
};
+/* Not currently working, probably needs at least different clocks */
+&rng_target {
+ status = "disabled";
+ /delete-property/ clocks;
+};
+
/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
&usb_otg_hs {
status = "disabled";
diff --git a/dts/src/arm/am3517_mt_ventoux.dts b/dts/src/arm/am3517_mt_ventoux.dts
index e507e4a..e7d7124 100644
--- a/dts/src/arm/am3517_mt_ventoux.dts
+++ b/dts/src/arm/am3517_mt_ventoux.dts
@@ -8,7 +8,7 @@
/ {
model = "TeeJet Mt.Ventoux";
- compatible = "teejet,mt_ventoux", "ti,omap3";
+ compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi
index 14bbc43..ca0aa3f 100644
--- a/dts/src/arm/am4372.dtsi
+++ b/dts/src/arm/am4372.dtsi
@@ -230,7 +230,6 @@
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
@@ -351,20 +350,20 @@
};
};
- ocmcram: ocmcram@40300000 {
+ ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */
ranges = <0x0 0x40300000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
- pm_sram_code: pm-sram-code@0 {
+ pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
- pm_sram_data: pm-sram-data@1000 {
+ pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
@@ -375,3 +374,29 @@
#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"
+
+&prcm {
+ prm_gfx: prm@400 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_per: prm@800 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x800 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_wkup: prm@2000 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x2000 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@4000 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x4000 0x100>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/dts/src/arm/am437x-l4.dtsi b/dts/src/arm/am437x-l4.dtsi
index 59770dd..0dd59ee 100644
--- a/dts/src/arm/am437x-l4.dtsi
+++ b/dts/src/arm/am437x-l4.dtsi
@@ -132,7 +132,6 @@
target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
@@ -167,7 +166,6 @@
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
@@ -195,7 +193,6 @@
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
@@ -373,7 +370,6 @@
target-module@35000 { /* 0x44e35000, ap 28 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
@@ -679,7 +675,6 @@
target-module@22000 { /* 0x48022000, ap 8 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
@@ -708,7 +703,6 @@
target-module@24000 { /* 0x48024000, ap 10 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
@@ -737,7 +731,6 @@
target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
@@ -817,7 +810,6 @@
target-module@38000 { /* 0x48038000, ap 14 04.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
@@ -849,7 +841,6 @@
target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
@@ -1048,7 +1039,6 @@
target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
@@ -1083,7 +1073,6 @@
target-module@60000 { /* 0x48060000, ap 30 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
@@ -1149,7 +1138,6 @@
target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
@@ -1262,7 +1250,6 @@
target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
@@ -1388,7 +1375,6 @@
target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
@@ -1417,7 +1403,6 @@
target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
@@ -1446,7 +1431,6 @@
target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
@@ -1475,7 +1459,6 @@
target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
@@ -1510,7 +1493,6 @@
target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
@@ -1614,7 +1596,6 @@
target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
@@ -1999,7 +1980,6 @@
target-module@10000 { /* 0x48310000, ap 64 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
@@ -2038,7 +2018,6 @@
target-module@20000 { /* 0x48320000, ap 82 34.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio5";
reg = <0x20000 0x4>,
<0x20010 0x4>,
<0x20114 0x4>;
@@ -2073,7 +2052,6 @@
target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio6";
reg = <0x22000 0x4>,
<0x22010 0x4>,
<0x22114 0x4>;
@@ -2296,7 +2274,6 @@
target-module@47000 { /* 0x48347000, ap 110 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hdq1w";
reg = <0x47000 0x4>,
<0x47014 0x4>,
<0x47018 0x4>;
diff --git a/dts/src/arm/am571x-idk.dts b/dts/src/arm/am571x-idk.dts
index 0aaacea..820ce3b 100644
--- a/dts/src/arm/am571x-idk.dts
+++ b/dts/src/arm/am571x-idk.dts
@@ -186,3 +186,30 @@
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};
+
+&mac_sw {
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+};
+
+&cpsw_port1 {
+ phy-handle = <&ethphy0_sw>;
+ phy-mode = "rgmii";
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ phy-handle = <&ethphy1_sw>;
+ phy-mode = "rgmii";
+ ti,dual-emac-pvid = <2>;
+};
+
+&davinci_mdio_sw {
+ ethphy0_sw: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1_sw: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
diff --git a/dts/src/arm/am572x-idk.dts b/dts/src/arm/am572x-idk.dts
index ea1c119..c3d9669 100644
--- a/dts/src/arm/am572x-idk.dts
+++ b/dts/src/arm/am572x-idk.dts
@@ -27,3 +27,8 @@
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
};
+
+&mac {
+ status = "okay";
+ dual_emac;
+};
diff --git a/dts/src/arm/am574x-idk.dts b/dts/src/arm/am574x-idk.dts
index 7935d70..fa00880 100644
--- a/dts/src/arm/am574x-idk.dts
+++ b/dts/src/arm/am574x-idk.dts
@@ -35,3 +35,8 @@
pinctrl-1 = <&mmc2_pins_default>;
pinctrl-2 = <&mmc2_pins_default>;
};
+
+&mac {
+ status = "okay";
+ dual_emac;
+};
diff --git a/dts/src/arm/am57xx-beagle-x15-revb1.dts b/dts/src/arm/am57xx-beagle-x15-revb1.dts
index 7b113b5..39d1c4f 100644
--- a/dts/src/arm/am57xx-beagle-x15-revb1.dts
+++ b/dts/src/arm/am57xx-beagle-x15-revb1.dts
@@ -24,7 +24,7 @@
};
&mmc2 {
- pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
diff --git a/dts/src/arm/am57xx-beagle-x15-revc.dts b/dts/src/arm/am57xx-beagle-x15-revc.dts
index 30c500b..4187a97 100644
--- a/dts/src/arm/am57xx-beagle-x15-revc.dts
+++ b/dts/src/arm/am57xx-beagle-x15-revc.dts
@@ -24,7 +24,7 @@
};
&mmc2 {
- pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
diff --git a/dts/src/arm/am57xx-idk-common.dtsi b/dts/src/arm/am57xx-idk-common.dtsi
index 423855a..398721c 100644
--- a/dts/src/arm/am57xx-idk-common.dtsi
+++ b/dts/src/arm/am57xx-idk-common.dtsi
@@ -363,11 +363,6 @@
ext-clk-src;
};
-&mac {
- status = "okay";
- dual_emac;
-};
-
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi
index 3f4bb44..e038abc 100644
--- a/dts/src/arm/armada-38x.dtsi
+++ b/dts/src/arm/armada-38x.dtsi
@@ -103,6 +103,11 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ sdramc: sdramc@1400 {
+ compatible = "marvell,armada-xp-sdram-controller";
+ reg = <0x1400 0x500>;
+ };
+
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
diff --git a/dts/src/arm/armada-xp-98dx3236.dtsi b/dts/src/arm/armada-xp-98dx3236.dtsi
index 267d0c1..654648b 100644
--- a/dts/src/arm/armada-xp-98dx3236.dtsi
+++ b/dts/src/arm/armada-xp-98dx3236.dtsi
@@ -90,7 +90,7 @@
};
internal-regs {
- sdramc@1400 {
+ sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
diff --git a/dts/src/arm/armada-xp-db-xc3-24g4xg.dts b/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
index df04805..4ec0ae0 100644
--- a/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
+++ b/dts/src/arm/armada-xp-db-xc3-24g4xg.dts
@@ -33,6 +33,11 @@
};
};
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
&devbus_bootcs {
status = "okay";
diff --git a/dts/src/arm/armada-xp.dtsi b/dts/src/arm/armada-xp.dtsi
index ee15c77..6c19984 100644
--- a/dts/src/arm/armada-xp.dtsi
+++ b/dts/src/arm/armada-xp.dtsi
@@ -36,7 +36,7 @@
};
internal-regs {
- sdramc@1400 {
+ sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
diff --git a/dts/src/arm/aspeed-ast2500-evb.dts b/dts/src/arm/aspeed-ast2500-evb.dts
index c9d88c9..8bec21e 100644
--- a/dts/src/arm/aspeed-ast2500-evb.dts
+++ b/dts/src/arm/aspeed-ast2500-evb.dts
@@ -40,6 +40,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -50,6 +51,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
+ spi-max-frequency = <100000000>;
};
};
diff --git a/dts/src/arm/aspeed-ast2600-evb.dts b/dts/src/arm/aspeed-ast2600-evb.dts
index 9870553..4afa866 100644
--- a/dts/src/arm/aspeed-ast2600-evb.dts
+++ b/dts/src/arm/aspeed-ast2600-evb.dts
@@ -55,6 +55,9 @@
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default>;
};
&mac2 {
@@ -62,6 +65,9 @@
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii3_default>;
};
&mac3 {
@@ -69,12 +75,141 @@
phy-mode = "rgmii";
phy-handle = <&ethphy3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii4_default>;
};
-&emmc {
+&emmc_controller {
status = "okay";
};
+&emmc {
+ non-removable;
+ bus-width = <4>;
+ max-frequency = <52000000>;
+};
+
&rtc {
status = "okay";
};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0xe0000>; // 896KB
+ label = "u-boot";
+ };
+
+ u-boot-env@e0000 {
+ reg = <0xe0000 0x20000>; // 128KB
+ label = "u-boot-env";
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x900000>; // 9MB
+ label = "kernel";
+ };
+
+ rofs@a00000 {
+ reg = <0xa00000 0x2000000>; // 32MB
+ label = "rofs";
+ };
+
+ rwfs@6000000 {
+ reg = <0x2a00000 0x1600000>; // 22MB
+ label = "rwfs";
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&uart5 {
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temp@2e {
+ compatible = "adi,adt7490";
+ reg = <0x2e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts b/dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
index 521afbe..2c29ac0 100644
--- a/dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
+++ b/dts/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -92,6 +92,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>,
+ <&syscon ASPEED_CLK_MAC2RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-facebook-cmm.dts b/dts/src/arm/aspeed-bmc-facebook-cmm.dts
index d519d30..016bbcb 100644
--- a/dts/src/arm/aspeed-bmc-facebook-cmm.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-cmm.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Backpack CMM BMC";
@@ -53,10 +53,6 @@
bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
};
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
@@ -64,39 +60,7 @@
};
};
-&pinctrl {
- aspeed,external-nodes = <&gfx &lhc>;
-};
-
-/*
- * Update reset type to "system" (full chip) to fix warm reboot hang issue
- * when reset type is set to default ("soc", gated by reset mask registers).
- */
-&wdt1 {
- status = "okay";
- aspeed,reset-type = "system";
-};
-
-/*
- * wdt2 is not used by Backpack CMM.
- */
-&wdt2 {
- status = "disabled";
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
- };
-};
-
&uart1 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
@@ -107,8 +71,6 @@
};
&uart3 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default
&pinctrl_ncts3_default
@@ -123,17 +85,6 @@
&pinctrl_rxd4_default>;
};
-&uart5 {
- status = "okay";
-};
-
-&mac1 {
- status = "okay";
- no-hw-checksum;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
-};
-
/*
* I2C bus reserved for communication with COM-E.
*/
@@ -380,3 +331,18 @@
&ehci1 {
status = "okay";
};
+
+&vhub {
+ status = "disabled";
+};
+
+&sdhci0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_default>;
+};
+
+&sdhci1 {
+ status = "disabled";
+};
diff --git a/dts/src/arm/aspeed-bmc-facebook-minipack.dts b/dts/src/arm/aspeed-bmc-facebook-minipack.dts
index c054782..88ce4ff 100644
--- a/dts/src/arm/aspeed-bmc-facebook-minipack.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-minipack.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Minipack 100 BMC";
@@ -76,35 +76,36 @@
stdout-path = &uart1;
bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw";
};
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
};
-&wdt1 {
+&wdt2 {
status = "okay";
aspeed,reset-type = "system";
};
-&wdt2 {
- status = "okay";
- aspeed,reset-type = "system";
+/*
+ * Both firmware flashes are 64MB on Minipack BMC.
+ */
+&fmc_flash0 {
+ partitions {
+ data0@1c00000 {
+ reg = <0x1c00000 0x2400000>;
+ };
+ flash0@0 {
+ reg = <0x0 0x4000000>;
+ };
+ };
};
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
+&fmc_flash1 {
+ partitions {
+ flash1@0 {
+ reg = <0x0 0x4000000>;
+ };
};
};
&uart1 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
@@ -120,13 +121,6 @@
&pinctrl_rxd2_default>;
};
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd3_default
- &pinctrl_rxd3_default>;
-};
-
&uart4 {
status = "okay";
pinctrl-names = "default";
@@ -134,17 +128,6 @@
&pinctrl_rxd4_default>;
};
-&uart5 {
- status = "okay";
-};
-
-&mac1 {
- status = "okay";
- no-hw-checksum;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
-};
-
&i2c0 {
status = "okay";
bus-frequency = <400000>;
@@ -423,7 +406,3 @@
&i2c13 {
status = "okay";
};
-
-&vhub {
- status = "okay";
-};
diff --git a/dts/src/arm/aspeed-bmc-facebook-tiogapass.dts b/dts/src/arm/aspeed-bmc-facebook-tiogapass.dts
index 682f729..5d7cbd9 100644
--- a/dts/src/arm/aspeed-bmc-facebook-tiogapass.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-tiogapass.dts
@@ -126,6 +126,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-facebook-yamp.dts b/dts/src/arm/aspeed-bmc-facebook-yamp.dts
index 4e09a9c..5293359 100644
--- a/dts/src/arm/aspeed-bmc-facebook-yamp.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-yamp.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook YAMP 100 BMC";
@@ -23,47 +23,6 @@
stdout-path = &uart5;
bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
};
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-};
-
-&pinctrl {
- aspeed,external-nodes = <&gfx &lhc>;
-};
-
-/*
- * Update reset type to "system" (full chip) to fix warm reboot hang issue
- * when reset type is set to default ("soc", gated by reset mask registers).
- */
-&wdt1 {
- status = "okay";
- aspeed,reset-type = "system";
-};
-
-/*
- * wdt2 is not used by Yamp.
- */
-&wdt2 {
- status = "disabled";
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
- };
-};
-
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd1_default
- &pinctrl_rxd1_default>;
};
&uart2 {
@@ -73,23 +32,19 @@
&pinctrl_rxd2_default>;
};
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd3_default
- &pinctrl_rxd3_default>;
-};
-
-&uart5 {
- status = "okay";
-};
-
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+};
+
+&mac1 {
+ status = "disabled";
};
&i2c0 {
@@ -154,7 +109,3 @@
&i2c13 {
status = "okay";
};
-
-&vhub {
- status = "okay";
-};
diff --git a/dts/src/arm/aspeed-bmc-ibm-rainier.dts b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
new file mode 100644
index 0000000..c1c9cd3
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
@@ -0,0 +1,972 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Rainier";
+ compatible = "ibm,rainier-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@B8000000 {
+ no-map;
+ reg = <0xB8000000 0x04000000>; /* 64M */
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 0)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 1)>;
+ };
+
+ ps2-presence {
+ label = "ps2-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 2)>;
+ };
+
+ ps3-presence {
+ label = "ps3-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 3)>;
+ };
+ };
+
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ power-supply@68 {
+ compatible = "ibm,cffps2";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps2";
+ reg = <0x69>;
+ };
+
+ power-supply@6a {
+ compatible = "ibm,cffps2";
+ reg = <0x6a>;
+ };
+
+ power-supply@6b {
+ compatible = "ibm,cffps2";
+ reg = <0x6b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ tmp275@4b {
+ compatible = "ti,tmp275";
+ reg = <0x4b>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ si7021-a20@20 {
+ compatible = "silabs,si7020";
+ reg = <0x20>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ };
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ ucd90320@b {
+ compatible = "ti,ucd90160";
+ reg = <0x0b>;
+ };
+
+ ucd90320@c {
+ compatible = "ti,ucd90160";
+ reg = <0x0c>;
+ };
+
+ ucd90320@11 {
+ compatible = "ti,ucd90160";
+ reg = <0x11>;
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ ir35221@42 {
+ compatible = "infineon,ir35221";
+ reg = <0x42>;
+ };
+
+ ir35221@43 {
+ compatible = "infineon,ir35221";
+ reg = <0x43>;
+ };
+
+ ir35221@44 {
+ compatible = "infineon,ir35221";
+ reg = <0x44>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ ir35221@73 {
+ compatible = "infineon,ir35221";
+ reg = <0x73>;
+ };
+
+ ir35221@74 {
+ compatible = "infineon,ir35221";
+ reg = <0x74>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+
+ ir35221@42 {
+ compatible = "infineon,ir35221";
+ reg = <0x42>;
+ };
+
+ ir35221@43 {
+ compatible = "infineon,ir35221";
+ reg = <0x43>;
+ };
+
+ ir35221@44 {
+ compatible = "infineon,ir35221";
+ reg = <0x44>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ ir35221@73 {
+ compatible = "infineon,ir35221";
+ reg = <0x73>;
+ };
+
+ ir35221@74 {
+ compatible = "infineon,ir35221";
+ reg = <0x74>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+};
+
+&i2c11 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ power-supply@68 {
+ compatible = "ibm,cffps2";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps2";
+ reg = <0x69>;
+ };
+
+ power-supply@6a {
+ compatible = "ibm,cffps2";
+ reg = <0x6a>;
+ };
+
+ power-supply@6b {
+ compatible = "ibm,cffps2";
+ reg = <0x6b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ tmp275@4b {
+ compatible = "ti,tmp275";
+ reg = <0x4b>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ si7021-a20@20 {
+ compatible = "silabs,si7020";
+ reg = <0x20>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ };
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ ucd90320@b {
+ compatible = "ti,ucd90160";
+ reg = <0x0b>;
+ };
+
+ ucd90320@c {
+ compatible = "ti,ucd90160";
+ reg = <0x0c>;
+ };
+
+ ucd90320@11 {
+ compatible = "ti,ucd90160";
+ reg = <0x11>;
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ ir35221@42 {
+ compatible = "infineon,ir35221";
+ reg = <0x42>;
+ };
+
+ ir35221@43 {
+ compatible = "infineon,ir35221";
+ reg = <0x43>;
+ };
+
+ ir35221@44 {
+ compatible = "infineon,ir35221";
+ reg = <0x44>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ ir35221@73 {
+ compatible = "infineon,ir35221";
+ reg = <0x73>;
+ };
+
+ ir35221@74 {
+ compatible = "infineon,ir35221";
+ reg = <0x74>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+
+ ir35221@42 {
+ compatible = "infineon,ir35221";
+ reg = <0x42>;
+ };
+
+ ir35221@43 {
+ compatible = "infineon,ir35221";
+ reg = <0x43>;
+ };
+
+ ir35221@44 {
+ compatible = "infineon,ir35221";
+ reg = <0x44>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ ir35221@73 {
+ compatible = "infineon,ir35221";
+ reg = <0x73>;
+ };
+
+ ir35221@74 {
+ compatible = "infineon,ir35221";
+ reg = <0x74>;
+ };
+};
+
+&i2c11 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c14 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c15 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&vuart1 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&mac3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>,
+ <&syscon ASPEED_CLK_MAC4RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
diff --git a/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
index e9d714a..c17bb7f 100644
--- a/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
+++ b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
@@ -148,14 +148,48 @@
};
leds {
- compatible = "gpio-leds";
+ compatible = "gpio-leds";
- power {
- label = "power";
- /* TODO: dummy gpio */
- gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>;
- };
+ power {
+ label = "power";
+ /* TODO: dummy gpio */
+ gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ init-ok {
+ label = "init-ok";
+ gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ front-memory {
+ label = "front-memory";
+ gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ front-syshot {
+ label = "front-syshot";
+ gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ front-syshealth {
+ label = "front-syshealth";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ };
+ front-fan {
+ label = "front-fan";
+ gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ front-psu {
+ label = "front-psu";
+ gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ label = "identify";
+ gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>;
+ };
};
iio-hwmon-battery {
@@ -239,6 +273,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -749,15 +786,6 @@
aspeed,external-nodes = <&gfx &lhc>;
};
-&gpio {
- pin_gpio_b7 {
- gpio-hog;
- gpios = <ASPEED_GPIO(B,7) GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "BMC_INIT_OK";
- };
-};
-
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
diff --git a/dts/src/arm/aspeed-bmc-inspur-on5263m5.dts b/dts/src/arm/aspeed-bmc-inspur-on5263m5.dts
index 2337ee2..80c92e0 100644
--- a/dts/src/arm/aspeed-bmc-inspur-on5263m5.dts
+++ b/dts/src/arm/aspeed-bmc-inspur-on5263m5.dts
@@ -77,6 +77,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-intel-s2600wf.dts b/dts/src/arm/aspeed-bmc-intel-s2600wf.dts
index 22dade6..1deb30e 100644
--- a/dts/src/arm/aspeed-bmc-intel-s2600wf.dts
+++ b/dts/src/arm/aspeed-bmc-intel-s2600wf.dts
@@ -69,6 +69,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-lenovo-hr630.dts b/dts/src/arm/aspeed-bmc-lenovo-hr630.dts
index d3695a3..c29e5f4 100644
--- a/dts/src/arm/aspeed-bmc-lenovo-hr630.dts
+++ b/dts/src/arm/aspeed-bmc-lenovo-hr630.dts
@@ -133,6 +133,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-lenovo-hr855xg2.dts b/dts/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
index 118eb8b..084c455 100644
--- a/dts/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
+++ b/dts/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
@@ -139,6 +139,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-opp-lanyang.dts b/dts/src/arm/aspeed-bmc-opp-lanyang.dts
index de95112..42b37a2 100644
--- a/dts/src/arm/aspeed-bmc-opp-lanyang.dts
+++ b/dts/src/arm/aspeed-bmc-opp-lanyang.dts
@@ -178,6 +178,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-opp-mihawk.dts b/dts/src/arm/aspeed-bmc-opp-mihawk.dts
index e55cc45..f7e935e 100644
--- a/dts/src/arm/aspeed-bmc-opp-mihawk.dts
+++ b/dts/src/arm/aspeed-bmc-opp-mihawk.dts
@@ -449,6 +449,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-opp-palmetto.dts b/dts/src/arm/aspeed-bmc-opp-palmetto.dts
index b0cb34c..eb4e93a 100644
--- a/dts/src/arm/aspeed-bmc-opp-palmetto.dts
+++ b/dts/src/arm/aspeed-bmc-opp-palmetto.dts
@@ -87,6 +87,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -99,6 +100,7 @@
flash@0 {
status = "okay";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
label = "pnor";
};
};
diff --git a/dts/src/arm/aspeed-bmc-opp-romulus.dts b/dts/src/arm/aspeed-bmc-opp-romulus.dts
index 9628ecb..edfa44f 100644
--- a/dts/src/arm/aspeed-bmc-opp-romulus.dts
+++ b/dts/src/arm/aspeed-bmc-opp-romulus.dts
@@ -112,6 +112,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -125,6 +126,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
+ spi-max-frequency = <100000000>;
};
};
@@ -160,6 +162,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&i2c1 {
diff --git a/dts/src/arm/aspeed-bmc-opp-swift.dts b/dts/src/arm/aspeed-bmc-opp-swift.dts
index f67fef1..b8fdd2a 100644
--- a/dts/src/arm/aspeed-bmc-opp-swift.dts
+++ b/dts/src/arm/aspeed-bmc-opp-swift.dts
@@ -322,6 +322,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&i2c2 {
diff --git a/dts/src/arm/aspeed-bmc-opp-tacoma.dts b/dts/src/arm/aspeed-bmc-opp-tacoma.dts
new file mode 100644
index 0000000..f02de4a
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-opp-tacoma.dts
@@ -0,0 +1,1195 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Tacoma";
+ compatible = "ibm,tacoma-bmc", "aspeed,ast2600";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@ba000000 {
+ no-map;
+ reg = <0xb8000000 0x4000000>; /* 64M */
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ air-water {
+ label = "air-water";
+ gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(Q, 7)>;
+ };
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(E, 3)>;
+ };
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 3)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(E, 5)>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&emmc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam0_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam0_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam0_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam0_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam0_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam0_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam0_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam0_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam0_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam0_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam0_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam0_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam0_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ0: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+&fsi_hub0 {
+ cfam@1,0 {
+ reg = <1 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <1>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam1_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam1_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam1_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam1_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam1_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam1_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam1_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam1_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam1_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam1_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam1_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam1_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam1_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ1: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub1: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+/* Legacy OCC numbering (to get rid of when userspace is fixed) */
+&fsi_occ0 {
+ reg = <1>;
+};
+
+&fsi_occ1 {
+ reg = <2>;
+};
+
+/ {
+ aliases {
+ i2c100 = &cfam0_i2c0;
+ i2c101 = &cfam0_i2c1;
+ i2c102 = &cfam0_i2c2;
+ i2c103 = &cfam0_i2c3;
+ i2c104 = &cfam0_i2c4;
+ i2c105 = &cfam0_i2c5;
+ i2c106 = &cfam0_i2c6;
+ i2c107 = &cfam0_i2c7;
+ i2c108 = &cfam0_i2c8;
+ i2c109 = &cfam0_i2c9;
+ i2c110 = &cfam0_i2c10;
+ i2c111 = &cfam0_i2c11;
+ i2c112 = &cfam0_i2c12;
+ i2c113 = &cfam0_i2c13;
+ i2c114 = &cfam0_i2c14;
+ i2c200 = &cfam1_i2c0;
+ i2c201 = &cfam1_i2c1;
+ i2c202 = &cfam1_i2c2;
+ i2c203 = &cfam1_i2c3;
+ i2c204 = &cfam1_i2c4;
+ i2c205 = &cfam1_i2c5;
+ i2c206 = &cfam1_i2c6;
+ i2c207 = &cfam1_i2c7;
+ i2c208 = &cfam1_i2c8;
+ i2c209 = &cfam1_i2c9;
+ i2c210 = &cfam1_i2c10;
+ i2c211 = &cfam1_i2c11;
+ i2c212 = &cfam1_i2c12;
+ i2c213 = &cfam1_i2c13;
+ i2c214 = &cfam1_i2c14;
+ };
+
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&uart5 {
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&vuart1 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&pinctrl {
+ /* Hog these as no driver is probed for the entire LPC block */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpc_default>,
+ <&pinctrl_lsirq_default>;
+};
diff --git a/dts/src/arm/aspeed-bmc-opp-vesnin.dts b/dts/src/arm/aspeed-bmc-opp-vesnin.dts
index a27c88d..affd2c8 100644
--- a/dts/src/arm/aspeed-bmc-opp-vesnin.dts
+++ b/dts/src/arm/aspeed-bmc-opp-vesnin.dts
@@ -43,6 +43,10 @@
gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>;
};
+ power_green {
+ gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ };
+
id_blue {
gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>;
};
diff --git a/dts/src/arm/aspeed-bmc-opp-witherspoon.dts b/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
index 31ea34e..569dad9 100644
--- a/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
+++ b/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
@@ -200,6 +200,7 @@
status = "okay";
label = "bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
@@ -224,6 +225,7 @@
status = "okay";
label = "alt-bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
@@ -242,7 +244,6 @@
label = "alt-obmc-ubi";
};
};
-
};
};
@@ -255,6 +256,7 @@
status = "okay";
label = "pnor";
m25p,fast-read;
+ spi-max-frequency = <100000000>;
};
};
@@ -293,6 +295,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-opp-zaius.dts b/dts/src/arm/aspeed-bmc-opp-zaius.dts
index 3062437..bc60ec2 100644
--- a/dts/src/arm/aspeed-bmc-opp-zaius.dts
+++ b/dts/src/arm/aspeed-bmc-opp-zaius.dts
@@ -130,6 +130,7 @@
status = "okay";
label = "bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -143,6 +144,7 @@
status = "okay";
label = "pnor";
m25p,fast-read;
+ spi-max-frequency = <100000000>;
};
};
@@ -187,6 +189,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-bmc-portwell-neptune.dts b/dts/src/arm/aspeed-bmc-portwell-neptune.dts
index 33d7045..4a1ca8f 100644
--- a/dts/src/arm/aspeed-bmc-portwell-neptune.dts
+++ b/dts/src/arm/aspeed-bmc-portwell-neptune.dts
@@ -80,12 +80,18 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default
&pinctrl_mdio1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>,
+ <&syscon ASPEED_CLK_MAC2RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index dffb595..46c0891 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -65,6 +65,7 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
@@ -100,6 +101,7 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -182,7 +184,7 @@
#reset-cells = <1>;
pinctrl: pinctrl {
- compatible = "aspeed,g4-pinctrl";
+ compatible = "aspeed,ast2400-pinctrl";
};
p2a: p2a-control {
diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi
index e8feb8b..a259c63 100644
--- a/dts/src/arm/aspeed-g5.dtsi
+++ b/dts/src/arm/aspeed-g5.dtsi
@@ -72,16 +72,19 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -97,11 +100,13 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -117,11 +122,13 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -215,7 +222,7 @@
#reset-cells = <1>;
pinctrl: pinctrl {
- compatible = "aspeed,g5-pinctrl";
+ compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
@@ -299,7 +306,7 @@
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2500-gpio";
- reg = <0x1e780000 0x1000>;
+ reg = <0x1e780000 0x200>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 232>;
clocks = <&syscon ASPEED_CLK_APB>;
@@ -307,6 +314,21 @@
#interrupt-cells = <2>;
};
+ sgpio: sgpio@1e780200 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2500-sgpio";
+ gpio-controller;
+ interrupts = <40>;
+ reg = <0x1e780200 0x0100>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ interrupt-controller;
+ ngpios = <8>;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm_default>;
+ status = "disabled";
+ };
+
rtc: rtc@1e781000 {
compatible = "aspeed,ast2500-rtc";
reg = <0x1e781000 0x18>;
@@ -379,6 +401,7 @@
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
+ aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
status = "disabled";
};
diff --git a/dts/src/arm/aspeed-g6-pinctrl.dtsi b/dts/src/arm/aspeed-g6-pinctrl.dtsi
index 5b8bf58..045ce66 100644
--- a/dts/src/arm/aspeed-g6-pinctrl.dtsi
+++ b/dts/src/arm/aspeed-g6-pinctrl.dtsi
@@ -852,14 +852,9 @@
groups = "SD2";
};
- pinctrl_sd3_default: sd3_default {
- function = "SD3";
- groups = "SD3";
- };
-
pinctrl_emmc_default: emmc_default {
- function = "SD3";
- groups = "EMMC";
+ function = "EMMC";
+ groups = "EMMCG4";
};
pinctrl_sgpm1_default: sgpm1_default {
diff --git a/dts/src/arm/aspeed-g6.dtsi b/dts/src/arm/aspeed-g6.dtsi
index 3a1422f..5f6142d 100644
--- a/dts/src/arm/aspeed-g6.dtsi
+++ b/dts/src/arm/aspeed-g6.dtsi
@@ -12,7 +12,29 @@
interrupt-parent = <&gic>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
serial4 = &uart5;
+ serial5 = &vuart1;
+ serial6 = &vuart2;
};
@@ -64,12 +86,113 @@
<0x40466000 0x2000>;
};
+ fmc: spi@1e620000 {
+ reg = < 0x1e620000 0xc4
+ 0x20000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ };
+
+ spi1: spi@1e630000 {
+ reg = < 0x1e630000 0xc4
+ 0x30000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ };
+
+ spi2: spi@1e631000 {
+ reg = < 0x1e631000 0xc4
+ 0x50000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+
+ fsim0: fsi@1e79b000 {
+ compatible = "aspeed,ast2600-fsi-master", "fsi-master";
+ reg = <0x1e79b000 0x94>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+ status = "disabled";
+ };
+
+ fsim1: fsi@1e79b100 {
+ compatible = "aspeed,ast2600-fsi-master", "fsi-master";
+ reg = <0x1e79b100 0x94>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+ status = "disabled";
+ };
+ };
+
mdio0: mdio@1e650000 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650000 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio1_default>;
};
mdio1: mdio@1e650008 {
@@ -78,6 +201,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio2_default>;
};
mdio2: mdio@1e650010 {
@@ -86,6 +211,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio3_default>;
};
mdio3: mdio@1e650018 {
@@ -94,6 +221,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio4_default>;
};
mac0: ftgmac@1e660000 {
@@ -168,6 +297,32 @@
quality = <100>;
};
+ gpio0: gpio@1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780000 0x800>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 208>;
+ ngpios = <208>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1e780800 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780800 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 208 36>;
+ ngpios = <36>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
rtc: rtc@1e781000 {
compatible = "aspeed,ast2600-rtc";
reg = <0x1e781000 0x18>;
@@ -175,6 +330,35 @@
status = "disabled";
};
+ timer: timer@1e782000 {
+ compatible = "aspeed,ast2600-timer";
+ reg = <0x1e782000 0x90>;
+ interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ clock-names = "PCLK";
+ };
+
+ uart1: serial@1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+ resets = <&lpc_reset 4>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
+ status = "disabled";
+ };
+
uart5: serial@1e784000 {
compatible = "ns16550a";
reg = <0x1e784000 0x1000>;
@@ -207,6 +391,93 @@
status = "disabled";
};
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
+ reg = <0x0 0x80>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x80>;
+
+ kcs1: kcs1@0 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+ kcs2: kcs2@0 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <2>;
+ status = "disabled";
+ };
+ kcs3: kcs3@0 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <3>;
+ status = "disabled";
+ };
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ kcs4: kcs4@0 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <4>;
+ status = "disabled";
+ };
+
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2600-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+
+ lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@c0 {
+ compatible = "aspeed,ast2600-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+ };
+
sdc: sdc@1e740000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e740000 0x100>;
@@ -235,7 +506,7 @@
};
};
- emmc: sdc@1e750000 {
+ emmc_controller: sdc@1e750000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e750000 0x100>;
#address-cells = <1>;
@@ -244,7 +515,7 @@
clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
status = "disabled";
- sdhci@1e750100 {
+ emmc: sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
sdhci,auto-cmd12;
@@ -254,8 +525,320 @@
pinctrl-0 = <&pinctrl_emmc_default>;
};
};
+
+ vuart1: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ vuart2: serial@1e788000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e788000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart2: serial@1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+ resets = <&lpc_reset 5>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+ status = "disabled";
+ };
+
+ uart3: serial@1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+ resets = <&lpc_reset 6>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+ status = "disabled";
+ };
+
+ uart4: serial@1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+ resets = <&lpc_reset 7>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
+ status = "disabled";
+ };
+
+ i2c: bus@1e78a000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e78a000 0x1000>;
+ };
+
};
};
};
#include "aspeed-g6-pinctrl.dtsi"
+
+&i2c {
+ i2c0: i2c-bus@80 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "disabled";
+ };
+
+ i2c1: i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x100 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+ status = "disabled";
+ };
+
+ i2c2: i2c-bus@180 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x180 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ status = "disabled";
+ };
+
+ i2c3: i2c-bus@200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x200 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ status = "disabled";
+ };
+
+ i2c4: i2c-bus@280 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x280 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ status = "disabled";
+ };
+
+ i2c5: i2c-bus@300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x300 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6_default>;
+ status = "disabled";
+ };
+
+ i2c6: i2c-bus@380 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x380 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_default>;
+ status = "disabled";
+ };
+
+ i2c7: i2c-bus@400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x400 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c8_default>;
+ status = "disabled";
+ };
+
+ i2c8: i2c-bus@480 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x480 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c9_default>;
+ status = "disabled";
+ };
+
+ i2c9: i2c-bus@500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x500 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ status = "disabled";
+ };
+
+ i2c10: i2c-bus@580 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x580 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ status = "disabled";
+ };
+
+ i2c11: i2c-bus@600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x600 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c12_default>;
+ status = "disabled";
+ };
+
+ i2c12: i2c-bus@680 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x680 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c13_default>;
+ status = "disabled";
+ };
+
+ i2c13: i2c-bus@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x700 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c14_default>;
+ status = "disabled";
+ };
+
+ i2c14: i2c-bus@780 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x780 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c15_default>;
+ status = "disabled";
+ };
+
+ i2c15: i2c-bus@800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x800 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c16_default>;
+ status = "disabled";
+ };
+};
diff --git a/dts/src/arm/ast2500-facebook-netbmc-common.dtsi b/dts/src/arm/ast2500-facebook-netbmc-common.dtsi
new file mode 100644
index 0000000..7a395ba
--- /dev/null
+++ b/dts/src/arm/ast2500-facebook-netbmc-common.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2019 Facebook Inc.
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+/*
+ * Update reset type to "system" (full chip) to fix warm reboot hang issue
+ * when reset type is set to default ("soc", gated by reset mask registers).
+ */
+&wdt1 {
+ status = "okay";
+ aspeed,reset-type = "system";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ fmc_flash0: flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "spi0.0";
+
+#include "facebook-bmc-flash-layout.dtsi"
+ };
+
+ fmc_flash1: flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "spi0.1";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1@0 {
+ reg = <0x0 0x2000000>;
+ label = "flash1";
+ };
+ };
+ };
+};
+
+&mac1 {
+ status = "okay";
+ no-hw-checksum;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&sdmmc {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd2_default>;
+};
diff --git a/dts/src/arm/at91-kizbox2-2.dts b/dts/src/arm/at91-kizbox2-2.dts
new file mode 100644
index 0000000..cab8b35
--- /dev/null
+++ b/dts/src/arm/at91-kizbox2-2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with
+ * two head board
+ *
+ * Copyright (C) 2015 Overkiz SAS
+ *
+ * Authors: Antoine Aubert <a.aubert@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizbox2-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox 2 with two heads";
+ compatible = "overkiz,kizbox2-2", "atmel,sama5d31",
+ "atmel,sama5d3", "atmel,sama5";
+};
+
+&usart1 {
+ status = "okay";
+};
+
+&usart2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/at91-kizbox2-common.dtsi b/dts/src/arm/at91-kizbox2-common.dtsi
new file mode 100644
index 0000000..af38253
--- /dev/null
+++ b/dts/src/arm/at91-kizbox2-common.dtsi
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox2_common.dtsi - Device Tree Include file for
+ * Overkiz Kizbox 2 family SoC
+ *
+ * Copyright (C) 2014-2018 Overkiz SAS
+ *
+ * Authors: Antoine Aubert <a.aubert@overkiz.com>
+ * Gaël Portay <g.portay@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+#include "sama5d31.dtsi"
+
+/ {
+ chosen {
+ bootargs = "ubi.mtd=ubi";
+ stdout-path = &dbgu;
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ prog {
+ label = "PB_PROG";
+ gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
+ linux,code = <0x102>;
+ wakeup-source;
+ };
+
+ reset {
+ label = "PB_RST";
+ gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x100>;
+ wakeup-source;
+ };
+
+ user {
+ label = "PB_USER";
+ gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x101>;
+ wakeup-source;
+ };
+ };
+
+ pwm_leds {
+ compatible = "pwm-leds";
+
+ blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+
+ green {
+ label = "pwm:green:user";
+ pwms = <&pwm0 1 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+
+ red {
+ label = "pwm:red:user";
+ pwms = <&pwm0 0 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ pmic: act8865@5b {
+ compatible = "active-semi,act8865";
+ reg = <0x5b>;
+ status = "okay";
+
+ regulators {
+ vcc_1v8_reg: DCDC_REG1 {
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_1v2_reg: DCDC_REG2 {
+ regulator-name = "VCC_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vcc_3v3_reg: DCDC_REG3 {
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vddfuse_reg: LDO_REG1 {
+ regulator-name = "FUSE_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vddana_reg: LDO_REG2 {
+ regulator-name = "VDDANA";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vled_reg: LDO_REG3 {
+ regulator-name = "VLED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ v3v8_rf_reg: LDO_REG4 {
+ regulator-name = "V3V8_RF";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&usart0 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&usart1 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&usart2 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwmh0_1
+ &pinctrl_pwm0_pwmh1_1
+ &pinctrl_pwm0_pwmh2_0>;
+ status = "okay";
+};
+
+&adc0 {
+ atmel,adc-vref = <3333>;
+ status = "okay";
+};
+
+&macb1 {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* WMBUS (inverted with IO in the latest schematic) */
+&pinctrl_usart0 {
+ atmel,pins =
+ <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
+
+/* RTS */
+&pinctrl_usart1 {
+ atmel,pins =
+ <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOE 7 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
+
+/* IO (inverted with WMBUS in the latest schematic) */
+&pinctrl_usart2 {
+ atmel,pins =
+ <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP
+ AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
diff --git a/dts/src/arm/at91-kizbox2.dts b/dts/src/arm/at91-kizbox2.dts
deleted file mode 100644
index 86d8218..0000000
--- a/dts/src/arm/at91-kizbox2.dts
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board
- *
- * Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
- */
-/dts-v1/;
-#include "sama5d31.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- model = "Overkiz Kizbox 2";
- compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
-
- chosen {
- bootargs = "ubi.mtd=ubi";
- stdout-path = &dbgu;
- };
-
- memory {
- reg = <0x20000000 0x10000000>;
- };
-
- clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
- main_xtal {
- clock-frequency = <12000000>;
- };
- };
-
- ahb {
- apb {
- i2c1: i2c@f0018000 {
- status = "okay";
-
- pmic: act8865@5b {
- compatible = "active-semi,act8865";
- reg = <0x5b>;
- status = "okay";
-
- regulators {
- vcc_1v8_reg: DCDC_REG1 {
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- vcc_1v2_reg: DCDC_REG2 {
- regulator-name = "VCC_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vcc_3v3_reg: DCDC_REG3 {
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vddfuse_reg: LDO_REG1 {
- regulator-name = "FUSE_2V5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- };
-
- vddana_reg: LDO_REG2 {
- regulator-name = "VDDANA";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vled_reg: LDO_REG3 {
- regulator-name = "VLED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v3v8_rf_reg: LDO_REG4 {
- regulator-name = "V3V8_RF";
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- regulator-always-on;
- };
- };
- };
- };
-
- tcb0: timer@f0010000 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>;
- };
-
- timer@1 {
- compatible = "atmel,tcb-timer";
- reg = <1>;
- };
- };
-
- usart0: serial@f001c000 {
- status = "okay";
- };
-
- usart1: serial@f0020000 {
- status = "okay";
- };
-
- pwm0: pwm@f002c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_pwmh0_1
- &pinctrl_pwm0_pwmh1_1
- &pinctrl_pwm0_pwmh2_0>;
- status = "okay";
- };
-
- adc0: adc@f8018000 {
- atmel,adc-vref = <3333>;
- status = "okay";
- };
-
- usart2: serial@f8020000 {
- status = "okay";
- };
-
- macb1: ethernet@f802c000 {
- phy-mode = "rmii";
- status = "okay";
- };
-
- dbgu: serial@ffffee00 {
- status = "okay";
- };
-
- watchdog@fffffe40 {
- status = "okay";
- };
- };
-
- usb1: ohci@600000 {
- status = "okay";
- };
-
- usb2: ehci@700000 {
- status = "okay";
- };
-
- ebi: ebi@10000000 {
- pinctrl-0 = <&pinctrl_ebi_nand_addr>;
- pinctrl-names = "default";
- status = "okay";
-
- nand_controller: nand-controller {
- status = "okay";
-
- nand@3 {
- reg = <0x3 0x0 0x2>;
- atmel,rb = <0>;
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- prog {
- label = "PB_PROG";
- gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
- linux,code = <0x102>;
- wakeup-source;
- };
-
- reset {
- label = "PB_RST";
- gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
- linux,code = <0x100>;
- wakeup-source;
- };
-
- user {
- label = "PB_USER";
- gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
- linux,code = <0x101>;
- wakeup-source;
- };
- };
-
- pwm_leds {
- compatible = "pwm-leds";
-
- blue {
- label = "pwm:blue:user";
- pwms = <&pwm0 2 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
-
- green {
- label = "pwm:green:user";
- pwms = <&pwm0 1 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
-
- red {
- label = "pwm:red:user";
- pwms = <&pwm0 0 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
- };
-};
diff --git a/dts/src/arm/at91-kizbox3-hs.dts b/dts/src/arm/at91-kizbox3-hs.dts
new file mode 100644
index 0000000..8734e7f
--- /dev/null
+++ b/dts/src/arm/at91-kizbox3-hs.dts
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
+ *
+ * Copyright (C) 2018 Overkiz SAS
+ *
+ * Authors: Dorian Rocipon <d.rocipon@overkiz.com>
+ * Kevin Carli <k.carli@overkiz.com>
+ * Mickael Gardet <m.gardet@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizbox3_common.dtsi"
+
+/ {
+ model = "Overkiz KIZBOX3-HS";
+ compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
+
+ pwm_leds {
+ status = "okay";
+
+ red {
+ status = "okay";
+ };
+
+ green {
+ status = "okay";
+ };
+
+ blue {
+ status = "okay";
+ };
+
+ white {
+ status = "okay";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_red
+ &pinctrl_led_white>;
+ status = "okay";
+
+ red {
+ label = "pio:red:user";
+ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ white {
+ label = "pio:white:user";
+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default" , "default", "default",
+ "default", "default" ;
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>;
+ pinctrl-2 = <&pinctrl_pio_io_boot
+ &pinctrl_pio_io_reset
+ &pinctrl_pio_io_test_radio>;
+ pinctrl-3 = <&pinctrl_pio_zbe_test_radio
+ &pinctrl_pio_zbe_rst>;
+ pinctrl-4 = <&pinctrl_pio_input>;
+
+ SW1 {
+ label = "SW1";
+ gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x101>;
+ wakeup-source;
+ };
+
+ SW2 {
+ label = "SW2";
+ gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>;
+ linux,code = <0x102>;
+ wakeup-source;
+ };
+
+ SW3 {
+ label = "SW3";
+ gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>;
+ linux,code = <0x103>;
+ wakeup-source;
+ };
+
+ SW7 {
+ label = "SW7";
+ gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>;
+ linux,code = <0x107>;
+ wakeup-source;
+ };
+
+ SW8 {
+ label = "SW8";
+ gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>;
+ linux,code = <0x108>;
+ wakeup-source;
+ };
+ };
+
+ gpios {
+ compatible = "gpio";
+ status = "okay";
+
+ rf_on {
+ label = "rf on";
+ gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ wifi_on {
+ label = "wifi on";
+ gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ zbe_test_radio {
+ label = "zbe test radio";
+ gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ zbe_rst {
+ label = "zbe rst";
+ gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_reset {
+ label = "io reset";
+ gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_test_radio {
+ label = "io test radio";
+ gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_boot_0 {
+ label = "io boot 0";
+ gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_boot_1 {
+ label = "io boot 1";
+ gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ verbose_bootloader {
+ label = "verbose bootloader";
+ gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ nail_bed_detection {
+ label = "nail bed detection";
+ gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ id_usba {
+ label = "id usba";
+ gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>;
+ input;
+ };
+ };
+};
+
+&pioA {
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux= <PIN_PA22__GPIO>,
+ <PIN_PA24__GPIO>,
+ <PIN_PA26__GPIO>,
+ <PIN_PA29__GPIO>,
+ <PIN_PA18__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_gpio {
+ pinctrl_pio_rf: gpio_rf {
+ pinmux = <PIN_PC19__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_wifi: gpio_wifi {
+ pinmux = <PIN_PC20__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_io_boot: gpio_io_boot {
+ pinmux =
+ <PIN_PC11__GPIO>,
+ <PIN_PC17__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_io_test_radio: gpio_io_test_radio {
+ pinmux = <PIN_PC9__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio {
+ pinmux = <PIN_PB21__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_zbe_rst: gpio_zbe_rst {
+ pinmux = <PIN_PB25__GPIO>;
+ bias-disable;
+ };
+ /* stm32 reset must be open drain (internal pull up) */
+ pinctrl_pio_io_reset: gpio_io_reset {
+ pinmux = <PIN_PB30__GPIO>;
+ bias-disable;
+ drive-open-drain = <1>;
+ output-low;
+ };
+ pinctrl_pio_input: gpio_input {
+ pinmux =
+ <PIN_PB11__GPIO>,
+ <PIN_PB12__GPIO>,
+ <PIN_PC0__GPIO>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_leds {
+ pinctrl_led_red: led_red {
+ pinmux = <PIN_PB1__GPIO>;
+ bias-disable;
+ };
+ pinctrl_led_white: led_white {
+ pinmux = <PIN_PB8__GPIO>;
+ bias-disable;
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&flx0 {
+ status = "okay";
+
+ uart5: serial@200 {
+ status = "okay";
+ };
+};
+
+&flx3 {
+ status = "okay";
+ uart6: serial@200 {
+ status = "okay";
+ };
+};
+
+&flx4 {
+ status = "okay";
+
+ i2c2: i2c@600 {
+ status = "okay";
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/at91-kizbox3_common.dtsi b/dts/src/arm/at91-kizbox3_common.dtsi
new file mode 100644
index 0000000..299e74d
--- /dev/null
+++ b/dts/src/arm/at91-kizbox3_common.dtsi
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
+ * family SoC boards
+ *
+ * Copyright (C) 2018 Overkiz SAS
+ *
+ * Authors: Dorian Rocipon <d.rocipon@overkiz.com>
+ * Kevin Carli <k.carli@overkiz.com>
+ * Mickael Gardet <m.gardet@overkiz.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Overkiz Kizbox3";
+ compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ };
+
+ chosen {
+ bootargs = "ubi.mtd=ubi";
+ stdout-path = "serial1:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ vdd_adc_vddana: supply_3v3_ana {
+ compatible = "regulator-fixed";
+ regulator-name = "adc-vddana";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_adc_vref: supply_3v3_ref {
+ compatible = "regulator-fixed";
+ regulator-name = "adc-vref";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ pwm_leds {
+ compatible = "pwm-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwm_h0
+ &pinctrl_pwm0_pwm_h1
+ &pinctrl_pwm0_pwm_h2
+ &pinctrl_pwm0_pwm_h3>;
+ status = "disabled";
+
+ red {
+ label = "pwm:red:user";
+ pwms = <&pwm0 0 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ status = "disabled";
+ };
+
+ green {
+ label = "pwm:green:user";
+ pwms = <&pwm0 1 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ status = "disabled";
+ };
+
+ blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ status = "disabled";
+ };
+
+ white {
+ label = "pwm:white:user";
+ pwms = <&pwm0 3 10000000 0>;
+ max-brightness = <255>;
+ status = "disabled";
+ };
+ };
+};
+
+&ebi {
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+
+ nand@3 {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ reg = <0x3 0x0 0x800000>;
+
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ u-boot@20000 {
+ label = "u-boot";
+ reg = <0x20000 0x140000>;
+ };
+
+ u-boot-factory@160000 {
+ label = "u-boot-factory";
+ reg = <0x160000 0x140000>;
+ };
+
+ ubi@2A0000 {
+ label = "ubi";
+ reg = <0x2A0000 0x7D60000>;
+ };
+ };
+
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&pioA {
+ pinctrl_ebi_nand_addr: ebi-addr-1 {
+ pinmux = <PIN_PA0__D0>,
+ <PIN_PA1__D1>,
+ <PIN_PA2__D2>,
+ <PIN_PA3__D3>,
+ <PIN_PA4__D4>,
+ <PIN_PA5__D5>,
+ <PIN_PA6__D6>,
+ <PIN_PA7__D7>,
+ <PIN_PA8__NWE_NANDWE>,
+ <PIN_PA9__NCS3>,
+ <PIN_PA10__A21_NANDALE>,
+ <PIN_PA11__A22_NANDCLE>,
+ <PIN_PA21__NANDRDY>;
+ bias-disable;
+ };
+
+ pinctrl_usart {
+ pinctrl_usart_0: usart0-0 {
+ pinmux = < PIN_PB26__URXD0>, <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+ pinctrl_usart_1: usart1-0 {
+ pinmux = < PIN_PD2__URXD1>, <PIN_PD3__UTXD1>;
+ bias-disable;
+ };
+ pinctrl_usart_2: usart2-0 {
+ pinmux = < PIN_PD4__URXD2>, <PIN_PD5__UTXD2>;
+ bias-disable;
+ };
+ pinctrl_usart_3: usart3-0 {
+ pinmux = < PIN_PC12__URXD3>, <PIN_PC13__UTXD3>;
+ bias-disable;
+ };
+ pinctrl_usart_4: usart4-0 {
+ pinmux = < PIN_PB3__URXD4>, <PIN_PB4__UTXD4>;
+ bias-disable;
+ };
+ pinctrl_flx0_default: flx0_usart_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>, //TX
+ <PIN_PB29__FLEXCOM0_IO1>; //RX
+ bias-disable;
+ };
+ pinctrl_flx3_default: flx3_usart_default {
+ pinmux = <PIN_PB22__FLEXCOM3_IO1>, //RX
+ <PIN_PB23__FLEXCOM3_IO0>; //TX
+ bias-disable;
+ };
+ };
+
+ pinctrl_flx4_default: flx4_i2c2_default {
+ pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA
+ <PIN_PD13__FLEXCOM4_IO1>; //CLK
+ bias-disable;
+ drive-open-drain = <1>;
+ };
+
+ pinctrl_pwm0 {
+ pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 {
+ pinmux = <PIN_PA30__PWMH0>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h1: pwm0_pwmh1 {
+ pinmux = <PIN_PB0__PWMH1>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 {
+ pinmux = <PIN_PB5__PWMH2>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 {
+ pinmux = <PIN_PB7__PWMH3>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_adc {
+ pinctrl_adc2: adc2 {
+ pinmux = <PIN_PD21__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc3: adc3 {
+ pinmux = <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc4: adc4 {
+ pinmux = <PIN_PD23__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc5: adc5 {
+ pinmux = <PIN_PD24__GPIO>;
+ bias-disable;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_0>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+/* debug uart */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_1>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_2>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_3>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_4>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "disabled";
+
+ uart5: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x400>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "usart";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,fifo-size = <32>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+ };
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "disabled";
+
+ uart6: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x400>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(17))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(18))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "usart";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ atmel,fifo-size = <32>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "disabled";
+
+ i2c2: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(19))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(20))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&shutdown_controller {
+ atmel,shdwc-debouncer = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc2
+ &pinctrl_adc3
+ &pinctrl_adc4
+ &pinctrl_adc5>;
+
+ vddana-supply = <&vdd_adc_vddana>;
+ vref-supply = <&vdd_adc_vref>;
+ status = "disabled";
+};
+
+&securam {
+ export;
+
+ /* export overkiz u-boot mode/version and factory */
+ uboot@1400 {
+ reg = <0x1400 0x20>;
+ export;
+ };
+};
diff --git a/dts/src/arm/at91-sama5d27_som1_ek.dts b/dts/src/arm/at91-sama5d27_som1_ek.dts
index 89f0c99..fca5716 100644
--- a/dts/src/arm/at91-sama5d27_som1_ek.dts
+++ b/dts/src/arm/at91-sama5d27_som1_ek.dts
@@ -53,6 +53,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
+ mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts
index 808e399..9d0a7fb 100644
--- a/dts/src/arm/at91-sama5d2_xplained.dts
+++ b/dts/src/arm/at91-sama5d2_xplained.dts
@@ -334,6 +334,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
status = "okay";
};
};
@@ -342,6 +345,9 @@
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
status = "okay";
at24@54 {
diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts
index fdfc37d..924d949 100644
--- a/dts/src/arm/at91-sama5d4_xplained.dts
+++ b/dts/src/arm/at91-sama5d4_xplained.dts
@@ -49,6 +49,7 @@
};
i2c0: i2c@f8014000 {
+ i2c-digital-filter;
status = "okay";
};
diff --git a/dts/src/arm/atlas7-evb.dts b/dts/src/arm/atlas7-evb.dts
index e0c0291..e051504 100644
--- a/dts/src/arm/atlas7-evb.dts
+++ b/dts/src/arm/atlas7-evb.dts
@@ -119,7 +119,7 @@
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
- debounce_interval = <100>;
+ debounce-interval = <100>;
};
};
diff --git a/dts/src/arm/bcm-hr2.dtsi b/dts/src/arm/bcm-hr2.dtsi
index e4d4973..6142c67 100644
--- a/dts/src/arm/bcm-hr2.dtsi
+++ b/dts/src/arm/bcm-hr2.dtsi
@@ -268,7 +268,7 @@
clock-frequency = <100000>;
};
- watchdog@39000 {
+ watchdog: watchdog@39000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x39000 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/bcm2711-rpi-4-b.dts b/dts/src/arm/bcm2711-rpi-4-b.dts
new file mode 100644
index 0000000..1b5a835
--- /dev/null
+++ b/dts/src/arm/bcm2711-rpi-4-b.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-usb-peripheral.dtsi"
+
+/ {
+ compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
+ model = "Raspberry Pi 4 Model B";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0>;
+ };
+
+ aliases {
+ ethernet0 = &genet;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ sd_io_1v8_reg: sd_io_1v8_reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ status = "okay";
+ };
+};
+
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "",
+ "";
+ status = "okay";
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* EMMC2 is used to drive the SD card */
+&emmc2 {
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ broken-cd;
+ status = "okay";
+};
+
+&genet {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+&genet_mdio {
+ phy1: ethernet-phy@1 {
+ /* No PHY interrupt */
+ reg = <0x1>;
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&vchiq {
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/src/arm/bcm2711.dtsi b/dts/src/arm/bcm2711.dtsi
new file mode 100644
index 0000000..961bed8
--- /dev/null
+++ b/dts/src/arm/bcm2711.dtsi
@@ -0,0 +1,890 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm283x.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
+
+/ {
+ compatible = "brcm,bcm2711";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gicv2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
+ * that's not good enough for the BCM2711 as some devices can
+ * only address the lower 1G of memory (ZONE_DMA).
+ */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x2000000>; /* 32MB */
+ alloc-ranges = <0x0 0x00000000 0x40000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+
+ soc {
+ /*
+ * Defined ranges:
+ * Common BCM283x peripherals
+ * BCM2711-specific peripherals
+ * ARM-local peripherals
+ */
+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
+ <0x7c000000 0x0 0xfc000000 0x02000000>,
+ <0x40000000 0x0 0xff800000 0x00800000>;
+ /* Emulate a contiguous 30-bit address range for DMA */
+ dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
+
+ /*
+ * This node is the provider for the enable-method for
+ * bringing up secondary cores.
+ */
+ local_intc: local_intc@40000000 {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ };
+
+ gicv2: interrupt-controller@40041000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ reg = <0x40041000 0x1000>,
+ <0x40042000 0x2000>,
+ <0x40044000 0x2000>,
+ <0x40046000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xb00>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ /* DMA lite 7 - 10 */
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x07f5>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>,
+ <0x7ec11000 0x20>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ rng@7e104000 {
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* RNG is incompatible with brcm,bcm2835-rng */
+ status = "disabled";
+ };
+
+ uart2: serial@7e201400 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201400 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart3: serial@7e201600 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201600 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart4: serial@7e201800 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201800 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart5: serial@7e201a00 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201a00 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ spi3: spi@7e204600 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204600 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@7e204800 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204800 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@7e204a00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204a00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@7e204c00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204c00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@7e205600 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205600 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@7e205800 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205800 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@7e205a00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205a00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@7e205c00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205c00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@7e20c800 {
+ compatible = "brcm,bcm2835-pwm";
+ reg = <0x7e20c800 0x28>;
+ clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clock-rates = <10000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ emmc2: emmc2@7e340000 {
+ compatible = "brcm,bcm2711-emmc2";
+ reg = <0x7e340000 0x100>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2711_CLOCK_EMMC2>;
+ status = "disabled";
+ };
+
+ hvs@7e400000 {
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ /* This only applies to the ARMv7 stub */
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000d8>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e8>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000f0>;
+ };
+ };
+
+ scb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
+
+ genet: ethernet@7d580000 {
+ compatible = "brcm,bcm2711-genet-v5";
+ reg = <0x0 0x7d580000 0x10000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ genet_mdio: mdio@e14 {
+ compatible = "brcm,genet-mdio-v5";
+ reg = <0xe14 0x8>;
+ reg-names = "mdio";
+ #address-cells = <0x0>;
+ #size-cells = <0x1>;
+ };
+ };
+ };
+};
+
+&clk_osc {
+ clock-frequency = <54000000>;
+};
+
+&clocks {
+ compatible = "brcm,bcm2711-cprman";
+};
+
+&cpu_thermal {
+ coefficients = <(-487) 410040>;
+};
+
+&dsi0 {
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dsi1 {
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio {
+ compatible = "brcm,bcm2711-gpio";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpclk0_gpio49: gpclk0_gpio49 {
+ pin-gpclk {
+ pins = "gpio49";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk1_gpio50: gpclk1_gpio50 {
+ pin-gpclk {
+ pins = "gpio50";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk2_gpio51: gpclk2_gpio51 {
+ pin-gpclk {
+ pins = "gpio51";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ i2c0_gpio46: i2c0_gpio46 {
+ pin-sda {
+ function = "alt0";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt0";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c1_gpio46: i2c1_gpio46 {
+ pin-sda {
+ function = "alt1";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt1";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c3_gpio2: i2c3_gpio2 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio2";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio3";
+ bias-disable;
+ };
+ };
+ i2c3_gpio4: i2c3_gpio4 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio4";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio5";
+ bias-disable;
+ };
+ };
+ i2c4_gpio6: i2c4_gpio6 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio6";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio7";
+ bias-disable;
+ };
+ };
+ i2c4_gpio8: i2c4_gpio8 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio8";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio9";
+ bias-disable;
+ };
+ };
+ i2c5_gpio10: i2c5_gpio10 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio10";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio11";
+ bias-disable;
+ };
+ };
+ i2c5_gpio12: i2c5_gpio12 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio12";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio13";
+ bias-disable;
+ };
+ };
+ i2c6_gpio0: i2c6_gpio0 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio0";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio1";
+ bias-disable;
+ };
+ };
+ i2c6_gpio22: i2c6_gpio22 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio22";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio23";
+ bias-disable;
+ };
+ };
+ i2c_slave_gpio8: i2c_slave_gpio8 {
+ pins-i2c-slave {
+ pins = "gpio8",
+ "gpio9",
+ "gpio10",
+ "gpio11";
+ function = "alt3";
+ };
+ };
+
+ jtag_gpio48: jtag_gpio48 {
+ pins-jtag {
+ pins = "gpio48",
+ "gpio49",
+ "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt4";
+ };
+ };
+
+ mii_gpio28: mii_gpio28 {
+ pins-mii {
+ pins = "gpio28",
+ "gpio29",
+ "gpio30",
+ "gpio31";
+ function = "alt4";
+ };
+ };
+ mii_gpio36: mii_gpio36 {
+ pins-mii {
+ pins = "gpio36",
+ "gpio37",
+ "gpio38",
+ "gpio39";
+ function = "alt5";
+ };
+ };
+
+ pcm_gpio50: pcm_gpio50 {
+ pins-pcm {
+ pins = "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt2";
+ };
+ };
+
+ pwm0_0_gpio12: pwm0_0_gpio12 {
+ pin-pwm {
+ pins = "gpio12";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio18: pwm0_0_gpio18 {
+ pin-pwm {
+ pins = "gpio18";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_0_gpio40: pwm1_0_gpio40 {
+ pin-pwm {
+ pins = "gpio40";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio13: pwm0_1_gpio13 {
+ pin-pwm {
+ pins = "gpio13";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio19: pwm0_1_gpio19 {
+ pin-pwm {
+ pins = "gpio19";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_1_gpio41: pwm1_1_gpio41 {
+ pin-pwm {
+ pins = "gpio41";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio45: pwm0_1_gpio45 {
+ pin-pwm {
+ pins = "gpio45";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio52: pwm0_0_gpio52 {
+ pin-pwm {
+ pins = "gpio52";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio53: pwm0_1_gpio53 {
+ pin-pwm {
+ pins = "gpio53";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ rgmii_gpio35: rgmii_gpio35 {
+ pin-start-stop {
+ pins = "gpio35";
+ function = "alt4";
+ };
+ pin-rx-ok {
+ pins = "gpio36";
+ function = "alt4";
+ };
+ };
+ rgmii_irq_gpio34: rgmii_irq_gpio34 {
+ pin-irq {
+ pins = "gpio34";
+ function = "alt5";
+ };
+ };
+ rgmii_irq_gpio39: rgmii_irq_gpio39 {
+ pin-irq {
+ pins = "gpio39";
+ function = "alt4";
+ };
+ };
+ rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
+ pins-mdio {
+ pins = "gpio28",
+ "gpio29";
+ function = "alt5";
+ };
+ };
+ rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
+ pins-mdio {
+ pins = "gpio37",
+ "gpio38";
+ function = "alt4";
+ };
+ };
+
+ spi0_gpio46: spi0_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49";
+ function = "alt2";
+ };
+ };
+ spi2_gpio46: spi2_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49",
+ "gpio50";
+ function = "alt5";
+ };
+ };
+ spi3_gpio0: spi3_gpio0 {
+ pins-spi {
+ pins = "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3";
+ function = "alt3";
+ };
+ };
+ spi4_gpio4: spi4_gpio4 {
+ pins-spi {
+ pins = "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7";
+ function = "alt3";
+ };
+ };
+ spi5_gpio12: spi5_gpio12 {
+ pins-spi {
+ pins = "gpio12",
+ "gpio13",
+ "gpio14",
+ "gpio15";
+ function = "alt3";
+ };
+ };
+ spi6_gpio18: spi6_gpio18 {
+ pins-spi {
+ pins = "gpio18",
+ "gpio19",
+ "gpio20",
+ "gpio21";
+ function = "alt3";
+ };
+ };
+
+ uart2_gpio0: uart2_gpio0 {
+ pin-tx {
+ pins = "gpio0";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio1";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
+ pin-cts {
+ pins = "gpio2";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio3";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart3_gpio4: uart3_gpio4 {
+ pin-tx {
+ pins = "gpio4";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio5";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
+ pin-cts {
+ pins = "gpio6";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio7";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart4_gpio8: uart4_gpio8 {
+ pin-tx {
+ pins = "gpio8";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio9";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
+ pin-cts {
+ pins = "gpio10";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio11";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart5_gpio12: uart5_gpio12 {
+ pin-tx {
+ pins = "gpio12";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio13";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
+ pin-cts {
+ pins = "gpio14";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio15";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+};
+
+&i2c0 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mailbox {
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhci {
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhost {
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi {
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi2 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&system_timer {
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&txp {
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&vec {
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/src/arm/bcm2835-common.dtsi b/dts/src/arm/bcm2835-common.dtsi
new file mode 100644
index 0000000..fe1ab40
--- /dev/null
+++ b/dts/src/arm/bcm2835-common.dtsi
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This include file covers the common peripherals and configuration between
+ * bcm2835, bcm2836 and bcm2837 implementations.
+ */
+
+/ {
+ interrupt-parent = <&intc>;
+
+ soc {
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16>,
+ <1 17>,
+ <1 18>,
+ <1 19>,
+ <1 20>,
+ <1 21>,
+ <1 22>,
+ <1 23>,
+ <1 24>,
+ <1 25>,
+ <1 26>,
+ /* dma channel 11-14 share one irq */
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ /* unused shared irq for all channels */
+ <1 28>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11",
+ "dma12",
+ "dma13",
+ "dma14",
+ "dma-shared-all";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x7f35>;
+ };
+
+ intc: interrupt-controller@7e00b200 {
+ compatible = "brcm,bcm2835-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ pixelvalve@7e206000 {
+ compatible = "brcm,bcm2835-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <2 13>; /* pwa0 */
+ };
+
+ pixelvalve@7e207000 {
+ compatible = "brcm,bcm2835-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <2 14>; /* pwa1 */
+ };
+
+ thermal: thermal@7e212000 {
+ compatible = "brcm,bcm2835-thermal";
+ reg = <0x7e212000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@7e805000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e805000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+ };
+
+ hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+ dmas = <&dma 17>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
+ };
+
+ vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+ };
+ };
+};
+
+&cpu_thermal {
+ thermal-sensors = <&thermal>;
+};
+
+&gpio {
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&i2s {
+ dmas = <&dma 2>, <&dma 3>;
+ dma-names = "tx", "rx";
+};
+
+&sdhost {
+ dmas = <&dma 13>;
+ dma-names = "rx-tx";
+};
+
+&spi {
+ dmas = <&dma 6>, <&dma 7>;
+ dma-names = "tx", "rx";
+};
diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi
index 6c6a7f6..394c8a7 100644
--- a/dts/src/arm/bcm2835-rpi.dtsi
+++ b/dts/src/arm/bcm2835-rpi.dtsi
@@ -59,10 +59,6 @@
clock-frequency = <100000>;
};
-&i2c2 {
- status = "okay";
-};
-
&usb {
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
diff --git a/dts/src/arm/bcm2835.dtsi b/dts/src/arm/bcm2835.dtsi
index a5c3824..53bf457 100644
--- a/dts/src/arm/bcm2835.dtsi
+++ b/dts/src/arm/bcm2835.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
/ {
compatible = "brcm,bcm2835";
diff --git a/dts/src/arm/bcm2836.dtsi b/dts/src/arm/bcm2836.dtsi
index c933e84..82d6c46 100644
--- a/dts/src/arm/bcm2836.dtsi
+++ b/dts/src/arm/bcm2836.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
/ {
compatible = "brcm,bcm2836";
diff --git a/dts/src/arm/bcm2837.dtsi b/dts/src/arm/bcm2837.dtsi
index beb6c50..9e95fee 100644
--- a/dts/src/arm/bcm2837.dtsi
+++ b/dts/src/arm/bcm2837.dtsi
@@ -1,4 +1,5 @@
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
/ {
compatible = "brcm,bcm2837";
diff --git a/dts/src/arm/bcm283x-rpi-usb-peripheral.dtsi b/dts/src/arm/bcm283x-rpi-usb-peripheral.dtsi
new file mode 100644
index 0000000..0ff0e9e
--- /dev/null
+++ b/dts/src/arm/bcm283x-rpi-usb-peripheral.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+&usb {
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 256 512 512 512 768 768>;
+};
diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi
index 2d191fc..3caaa57 100644
--- a/dts/src/arm/bcm283x.dtsi
+++ b/dts/src/arm/bcm283x.dtsi
@@ -18,7 +18,6 @@
/ {
compatible = "brcm,bcm2835";
model = "BCM2835";
- interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
@@ -36,8 +35,6 @@
polling-delay-passive = <0>;
polling-delay = <1000>;
- thermal-sensors = <&thermal>;
-
trips {
cpu-crit {
temperature = <80000>;
@@ -56,7 +53,7 @@
#address-cells = <1>;
#size-cells = <1>;
- timer@7e003000 {
+ system_timer: timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
@@ -67,74 +64,12 @@
clock-frequency = <1000000>;
};
- txp@7e004000 {
+ txp: txp@7e004000 {
compatible = "brcm,bcm2835-txp";
reg = <0x7e004000 0x20>;
interrupts = <1 11>;
};
- dma: dma@7e007000 {
- compatible = "brcm,bcm2835-dma";
- reg = <0x7e007000 0xf00>;
- interrupts = <1 16>,
- <1 17>,
- <1 18>,
- <1 19>,
- <1 20>,
- <1 21>,
- <1 22>,
- <1 23>,
- <1 24>,
- <1 25>,
- <1 26>,
- /* dma channel 11-14 share one irq */
- <1 27>,
- <1 27>,
- <1 27>,
- <1 27>,
- /* unused shared irq for all channels */
- <1 28>;
- interrupt-names = "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "dma8",
- "dma9",
- "dma10",
- "dma11",
- "dma12",
- "dma13",
- "dma14",
- "dma-shared-all";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x7f35>;
- };
-
- intc: interrupt-controller@7e00b200 {
- compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x7e00b200 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pm: watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
- #power-domain-cells = <1>;
- #reset-cells = <1>;
- reg = <0x7e100000 0x114>,
- <0x7e00a000 0x24>;
- clocks = <&clocks BCM2835_CLOCK_V3D>,
- <&clocks BCM2835_CLOCK_PERI_IMAGE>,
- <&clocks BCM2835_CLOCK_H264>,
- <&clocks BCM2835_CLOCK_ISP>;
- clock-names = "v3d", "peri_image", "h264", "isp";
- system-power-controller;
- };
-
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
@@ -184,8 +119,7 @@
interrupt-controller;
#interrupt-cells = <2>;
- /* Defines pin muxing groups according to
- * BCM2835-ARM-Peripherals.pdf page 102.
+ /* Defines common pin muxing groups
*
* While each pin can have its mux selected
* for various functions individually, some
@@ -263,15 +197,7 @@
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- i2c_slave_gpio18: i2c_slave_gpio18 {
- brcm,pins = <18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- jtag_gpio4: jtag_gpio4 {
- brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
@@ -286,35 +212,6 @@
brcm,function = <BCM2835_FSEL_ALT2>;
};
- pwm0_gpio12: pwm0_gpio12 {
- brcm,pins = <12>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm0_gpio18: pwm0_gpio18 {
- brcm,pins = <18>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm0_gpio40: pwm0_gpio40 {
- brcm,pins = <40>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio13: pwm1_gpio13 {
- brcm,pins = <13>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio19: pwm1_gpio19 {
- brcm,pins = <19>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm1_gpio41: pwm1_gpio41 {
- brcm,pins = <41>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio45: pwm1_gpio45 {
- brcm,pins = <45>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
@@ -396,7 +293,7 @@
};
uart0: serial@7e201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ compatible = "arm,pl011", "arm,primecell";
reg = <0x7e201000 0x200>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
@@ -410,8 +307,6 @@
reg = <0x7e202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 13>;
- dma-names = "rx-tx";
status = "disabled";
};
@@ -419,10 +314,6 @@
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
-
- dmas = <&dma 2>,
- <&dma 3>;
- dma-names = "tx", "rx";
status = "disabled";
};
@@ -431,8 +322,6 @@
reg = <0x7e204000 0x200>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 6>, <&dma 7>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -448,18 +337,6 @@
status = "disabled";
};
- pixelvalve@7e206000 {
- compatible = "brcm,bcm2835-pixelvalve0";
- reg = <0x7e206000 0x100>;
- interrupts = <2 13>; /* pwa0 */
- };
-
- pixelvalve@7e207000 {
- compatible = "brcm,bcm2835-pixelvalve1";
- reg = <0x7e207000 0x100>;
- interrupts = <2 14>; /* pwa1 */
- };
-
dpi: dpi@7e208000 {
compatible = "brcm,bcm2835-dpi";
reg = <0x7e208000 0x8c>;
@@ -490,14 +367,6 @@
};
- thermal: thermal@7e212000 {
- compatible = "brcm,bcm2835-thermal";
- reg = <0x7e212000 0x8>;
- clocks = <&clocks BCM2835_CLOCK_TSENS>;
- #thermal-sensor-cells = <0>;
- status = "disabled";
- };
-
aux: aux@7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
@@ -587,16 +456,6 @@
status = "disabled";
};
- i2c2: i2c@7e805000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e805000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
vec: vec@7e806000 {
compatible = "brcm,bcm2835-vec";
reg = <0x7e806000 0x1000>;
@@ -605,26 +464,6 @@
status = "disabled";
};
- pixelvalve@7e807000 {
- compatible = "brcm,bcm2835-pixelvalve2";
- reg = <0x7e807000 0x100>;
- interrupts = <2 10>; /* pixelvalve */
- };
-
- hdmi: hdmi@7e902000 {
- compatible = "brcm,bcm2835-hdmi";
- reg = <0x7e902000 0x600>,
- <0x7e808000 0x100>;
- interrupts = <2 8>, <2 9>;
- ddc = <&i2c2>;
- clocks = <&clocks BCM2835_PLLH_PIX>,
- <&clocks BCM2835_CLOCK_HSM>;
- clock-names = "pixel", "hdmi";
- dmas = <&dma 17>;
- dma-names = "audio-rx";
- status = "disabled";
- };
-
usb: usb@7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
@@ -636,36 +475,19 @@
phys = <&usbphy>;
phy-names = "usb2-phy";
};
-
- v3d: v3d@7ec00000 {
- compatible = "brcm,bcm2835-v3d";
- reg = <0x7ec00000 0x1000>;
- interrupts = <1 10>;
- power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
- };
-
- vc4: gpu {
- compatible = "brcm,bcm2835-vc4";
- };
};
clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
/* The oscillator is the root of the clock tree. */
- clk_osc: clock@3 {
+ clk_osc: clk-osc {
compatible = "fixed-clock";
- reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
- clk_usb: clock@4 {
+ clk_usb: clk-usb {
compatible = "fixed-clock";
- reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
diff --git a/dts/src/arm/bcm47094-luxul-xwc-2000.dts b/dts/src/arm/bcm47094-luxul-xwc-2000.dts
new file mode 100644
index 0000000..3343253
--- /dev/null
+++ b/dts/src/arm/bcm47094-luxul-xwc-2000.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2019 Legrand AV Inc.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Luxul XWC-2000 V1";
+
+ chosen {
+ bootargs = "earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000
+ 0x88000000 0x18000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&spi_nor {
+ status = "okay";
+};
diff --git a/dts/src/arm/dove.dtsi b/dts/src/arm/dove.dtsi
index 2e8a397..3081b04 100644
--- a/dts/src/arm/dove.dtsi
+++ b/dts/src/arm/dove.dtsi
@@ -784,7 +784,7 @@
status = "disabled";
};
- crypto_sram: sa-sram@ffffe000 {
+ crypto_sram: sram@ffffe000 {
compatible = "mmio-sram";
reg = <0xffffe000 0x800>;
clocks = <&gate_clk 15>;
diff --git a/dts/src/arm/dra7-l4.dtsi b/dts/src/arm/dra7-l4.dtsi
index 5cac2dd..7e7aa10 100644
--- a/dts/src/arm/dra7-l4.dtsi
+++ b/dts/src/arm/dra7-l4.dtsi
@@ -442,7 +442,6 @@
target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox1";
reg = <0xf4000 0x4>,
<0xf4010 0x4>;
reg-names = "rev", "sysc";
@@ -1899,7 +1898,6 @@
target-module@90000 { /* 0x48090000, ap 55 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
@@ -2090,7 +2088,6 @@
target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hdq1w";
reg = <0xb2000 0x4>,
<0xb2014 0x4>,
<0xb2018 0x4>;
@@ -3059,7 +3056,7 @@
davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
+ clocks = <&gmac_main_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
@@ -3079,6 +3076,58 @@
phys = <&phy_gmii_sel 2>;
};
};
+
+ mac_sw: switch@0 {
+ compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
+ reg = <0x0 0x4000>;
+ ranges = <0 0 0x4000>;
+ clocks = <&gmac_main_clk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscon = <&scm_conf>;
+ status = "disabled";
+
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx_thresh", "rx", "tx", "misc";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 1>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 2>;
+ };
+ };
+
+ davinci_mdio_sw: mdio@1000 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ clocks = <&gmac_main_clk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ reg = <0x1000 0x100>;
+ };
+
+ cpts {
+ clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
+ clock-names = "cpts";
+ };
+ };
};
};
};
@@ -3199,7 +3248,6 @@
target-module@2000 { /* 0x48802000, ap 95 7c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox13";
reg = <0x2000 0x4>,
<0x2010 0x4>;
reg-names = "rev", "sysc";
@@ -3528,7 +3576,6 @@
target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox2";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -3559,7 +3606,6 @@
target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox3";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -3590,7 +3636,6 @@
target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox4";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -3621,7 +3666,6 @@
target-module@40000 { /* 0x48840000, ap 39 64.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox5";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
@@ -3652,7 +3696,6 @@
target-module@42000 { /* 0x48842000, ap 41 4e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox6";
reg = <0x42000 0x4>,
<0x42010 0x4>;
reg-names = "rev", "sysc";
@@ -3683,7 +3726,6 @@
target-module@44000 { /* 0x48844000, ap 43 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox7";
reg = <0x44000 0x4>,
<0x44010 0x4>;
reg-names = "rev", "sysc";
@@ -3714,7 +3756,6 @@
target-module@46000 { /* 0x48846000, ap 45 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox8";
reg = <0x46000 0x4>,
<0x46010 0x4>;
reg-names = "rev", "sysc";
@@ -3833,7 +3874,6 @@
target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox9";
reg = <0x5e000 0x4>,
<0x5e010 0x4>;
reg-names = "rev", "sysc";
@@ -3864,7 +3904,6 @@
target-module@60000 { /* 0x48860000, ap 71 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox10";
reg = <0x60000 0x4>,
<0x60010 0x4>;
reg-names = "rev", "sysc";
@@ -3895,7 +3934,6 @@
target-module@62000 { /* 0x48862000, ap 73 74.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox11";
reg = <0x62000 0x4>,
<0x62010 0x4>;
reg-names = "rev", "sysc";
@@ -3926,7 +3964,6 @@
target-module@64000 { /* 0x48864000, ap 67 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox12";
reg = <0x64000 0x4>,
<0x64010 0x4>;
reg-names = "rev", "sysc";
@@ -4301,7 +4338,6 @@
target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index 953f0ff..73e5011 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -763,3 +763,54 @@
#include "dra7-l4.dtsi"
#include "dra7xx-clocks.dtsi"
+
+&prm {
+ prm_dsp1: prm@400 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_ipu: prm@500 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x500 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_iva: prm@f00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ };
+
+ prm_dsp2: prm@1b00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+
+ prm_eve1: prm@1b40 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b40 0x40>;
+ };
+
+ prm_eve2: prm@1b80 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b80 0x40>;
+ };
+
+ prm_eve3: prm@1bc0 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1bc0 0x40>;
+ };
+
+ prm_eve4: prm@1c00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1c00 0x60>;
+ };
+};
diff --git a/dts/src/arm/e60k02.dtsi b/dts/src/arm/e60k02.dtsi
new file mode 100644
index 0000000..6472b05
--- /dev/null
+++ b/dts/src/arm/e60k02.dtsi
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * and
+ * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
+ *
+ * Netronix E60K02 board common.
+ * This board is equipped with different SoCs and
+ * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
+ * the Tolino Shine 3 (with i.MX6SL)
+ */
+#include <dt-bindings/input/input.h>
+
+/ {
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ cover {
+ label = "Cover";
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ on {
+ label = "e60k02:white:on";
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lm3630a: backlight@36 {
+ reg = <0x36>;
+ compatible = "ti,lm3630a";
+ enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0>;
+ label = "backlight_warm";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ label = "backlight_cold";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ /* TODO: CYTTSP5 touch controller at 0x24 */
+
+ /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ ricoh619: pmic@32 {
+ compatible = "ricoh,rc5t619";
+ reg = <0x32>;
+ system-power-controller;
+
+ regulators {
+ dcdc1_reg: DCDC1 {
+ regulator-name = "DCDC1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <900000>;
+ regulator-suspend-min-microvolt = <900000>;
+ };
+ };
+
+ /* Core3_3V3 */
+ dcdc2_reg: DCDC2 {
+ regulator-name = "DCDC2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3300000>;
+ regulator-suspend-min-microvolt = <3300000>;
+ };
+ };
+
+ dcdc3_reg: DCDC3 {
+ regulator-name = "DCDC3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V2 */
+ dcdc4_reg: DCDC4 {
+ regulator-name = "DCDC4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V8 */
+ dcdc5_reg: DCDC5 {
+ regulator-name = "DCDC5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1700000>;
+ regulator-suspend-min-microvolt = <1700000>;
+ };
+ };
+
+ /* IR_3V3 */
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-boot-on;
+ };
+
+ /* Core1_3V3 */
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3000000>;
+ regulator-suspend-min-microvolt = <3000000>;
+ };
+ };
+
+ /* Core5_1V2 */
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-boot-on;
+ };
+
+ /* SPD_3V3 */
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* DDR_0V6 */
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* VDD_PWM */
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* ldo_1v8 */
+ ldo8_reg: LDO8 {
+ regulator-name = "LDO8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "LDO9";
+ regulator-boot-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "LDO10";
+ regulator-boot-on;
+ };
+
+ ldortc1_reg: LDORTC1 {
+ regulator-name = "LDORTC1";
+ regulator-boot-on;
+ };
+
+ ldortc2_reg: LDORTC2 {
+ regulator-name = "LDORTC2";
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&snvs_rtc {
+ /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ vmmc-supply = <&reg_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
diff --git a/dts/src/arm/emev2.dtsi b/dts/src/arm/emev2.dtsi
index 67d8601..96678dd 100644
--- a/dts/src/arm/emev2.dtsi
+++ b/dts/src/arm/emev2.dtsi
@@ -212,6 +212,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio1: gpio@e0050080 {
compatible = "renesas,em-gio";
reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
@@ -224,6 +225,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio2: gpio@e0050100 {
compatible = "renesas,em-gio";
reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
@@ -236,6 +238,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio3: gpio@e0050180 {
compatible = "renesas,em-gio";
reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
@@ -248,6 +251,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio4: gpio@e0050200 {
compatible = "renesas,em-gio";
reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi
index 7848184..b016b0b 100644
--- a/dts/src/arm/exynos3250.dtsi
+++ b/dts/src/arm/exynos3250.dtsi
@@ -138,7 +138,7 @@
#size-cells = <1>;
ranges;
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
@@ -265,7 +265,7 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- mct@10050000 {
+ timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
@@ -314,8 +314,7 @@
sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -355,8 +354,7 @@
sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -507,8 +505,7 @@
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi
index 433f109..d2779a7 100644
--- a/dts/src/arm/exynos4.dtsi
+++ b/dts/src/arm/exynos4.dtsi
@@ -111,28 +111,28 @@
syscon = <&pmu_system_controller>;
};
- pd_mfc: mfc-power-domain@10023c40 {
+ pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
- pd_g3d: g3d-power-domain@10023c60 {
+ pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
- pd_lcd0: lcd0-power-domain@10023c80 {
+ pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
- pd_tv: tv-power-domain@10023c20 {
+ pd_tv: power-domain@10023c20 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C20 0x20>;
#power-domain-cells = <0>;
@@ -140,21 +140,21 @@
label = "TV";
};
- pd_cam: cam-power-domain@10023c00 {
+ pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
- pd_gps: gps-power-domain@10023ce0 {
+ pd_gps: power-domain@10023ce0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CE0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
- pd_gps_alive: gps-alive-power-domain@10023d00 {
+ pd_gps_alive: power-domain@10023d00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
#power-domain-cells = <0>;
diff --git a/dts/src/arm/exynos4210.dtsi b/dts/src/arm/exynos4210.dtsi
index f220716..554819a 100644
--- a/dts/src/arm/exynos4210.dtsi
+++ b/dts/src/arm/exynos4210.dtsi
@@ -72,7 +72,7 @@
};
soc: soc {
- sysram: sysram@2020000 {
+ sysram: sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x20000>;
#address-cells = <1>;
@@ -90,7 +90,7 @@
};
};
- pd_lcd1: lcd1-power-domain@10023ca0 {
+ pd_lcd1: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@@ -106,26 +106,17 @@
arm,data-latency = <2 2 1>;
};
- mct: mct@10050000 {
+ mct: timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map =
- <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
- <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&combiner 12 6>,
+ <&combiner 12 7>,
+ <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {
diff --git a/dts/src/arm/exynos4412.dtsi b/dts/src/arm/exynos4412.dtsi
index d20db2d..5022aa5 100644
--- a/dts/src/arm/exynos4412.dtsi
+++ b/dts/src/arm/exynos4412.dtsi
@@ -188,7 +188,7 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
@@ -206,7 +206,7 @@
};
};
- pd_isp: isp-power-domain@10023ca0 {
+ pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@@ -243,25 +243,16 @@
clock-names = "aclk200", "aclk400_mcuisp";
};
- mct@10050000 {
+ timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map =
- <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &combiner 12 5>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <&combiner 12 5>,
+ <&combiner 12 6>,
+ <&combiner 12 7>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {
diff --git a/dts/src/arm/exynos5.dtsi b/dts/src/arm/exynos5.dtsi
index 67f9b45..4801ca7 100644
--- a/dts/src/arm/exynos5.dtsi
+++ b/dts/src/arm/exynos5.dtsi
@@ -35,8 +35,8 @@
#size-cells = <1>;
ranges;
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
+ chipid: chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid", "syscon";
reg = <0x10000000 0x100>;
};
diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts
index 6fcb78a..d6c85ef 100644
--- a/dts/src/arm/exynos5250-arndale.dts
+++ b/dts/src/arm/exynos5250-arndale.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5250.dtsi"
/ {
@@ -135,6 +136,12 @@
};
};
+ sound {
+ compatible = "samsung,arndale-wm1811";
+ samsung,audio-cpu = <&i2s0>;
+ samsung,audio-codec = <&wm1811>;
+ };
+
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
@@ -151,6 +158,16 @@
};
};
+&clock {
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <49152000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -502,9 +519,11 @@
&i2c_3 {
status = "okay";
- wm1811a@1a {
+ wm1811: codec@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ clock-names = "MCLK1";
AVDD2-supply = <&main_dc_reg>;
CPVDD-supply = <&main_dc_reg>;
@@ -540,9 +559,15 @@
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
+&i2s0_bus {
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+};
+
&mali {
mali-supply = <&buck4_reg>;
status = "okay";
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index fc966c1..e1f0215 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -164,7 +164,7 @@
};
soc: soc {
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x30000>;
#address-cells = <1>;
@@ -233,28 +233,17 @@
power-domains = <&pd_mau>;
};
- mct@101c0000 {
+ timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &combiner 23 3>,
- <0x1 0 &combiner 23 4>,
- <0x2 0 &combiner 25 2>,
- <0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
- <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&combiner 23 3>,
+ <&combiner 23 4>,
+ <&combiner 25 2>,
+ <&combiner 25 3>,
+ <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_0: pinctrl@11400000 {
@@ -586,9 +575,9 @@
compatible = "samsung,s5pv210-i2s";
status = "disabled";
reg = <0x03830000 0x100>;
- dmas = <&pdma0 10
- &pdma0 9
- &pdma0 8>;
+ dmas = <&pdma0 10>,
+ <&pdma0 9>,
+ <&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -606,8 +595,8 @@
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D60000 0x100>;
- dmas = <&pdma1 12
- &pdma1 11>;
+ dmas = <&pdma1 12>,
+ <&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
clock-names = "iis", "i2s_opclk0";
@@ -621,8 +610,8 @@
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D70000 0x100>;
- dmas = <&pdma0 12
- &pdma0 11>;
+ dmas = <&pdma0 12>,
+ <&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
clock-names = "iis", "i2s_opclk0";
diff --git a/dts/src/arm/exynos5260.dtsi b/dts/src/arm/exynos5260.dtsi
index 3581b57..b0811db 100644
--- a/dts/src/arm/exynos5260.dtsi
+++ b/dts/src/arm/exynos5260.dtsi
@@ -180,7 +180,7 @@
reg = <0x10000000 0x100>;
};
- mct: mct@100b0000 {
+ mct: timer@100b0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
diff --git a/dts/src/arm/exynos5410.dtsi b/dts/src/arm/exynos5410.dtsi
index e6f78b1..a4b03d4 100644
--- a/dts/src/arm/exynos5410.dtsi
+++ b/dts/src/arm/exynos5410.dtsi
@@ -222,9 +222,9 @@
audi2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
- dmas = <&pdma0 10
- &pdma0 9
- &pdma0 8>;
+ dmas = <&pdma0 10>,
+ <&pdma0 9>,
+ <&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index 9eb48ca..2bcbdf8 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -1065,6 +1065,10 @@
status = "okay";
};
+&timer {
+ arm,cpu-registers-not-fw-configured;
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 7d51e0f..d39907a 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -175,7 +175,7 @@
};
clock: clock-controller@10010000 {
- compatible = "samsung,exynos5420-clock";
+ compatible = "samsung,exynos5420-clock", "syscon";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
@@ -237,6 +237,32 @@
status = "disabled";
};
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ samsung,syscon-clk = <&clock>;
+ status = "disabled";
+ };
+
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -273,6 +299,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d60000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -434,9 +508,9 @@
i2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
- dmas = <&adma 0
- &adma 2
- &adma 1>;
+ dmas = <&adma 0>,
+ <&adma 2>,
+ <&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -455,8 +529,8 @@
i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
- dmas = <&pdma1 12
- &pdma1 11>;
+ dmas = <&pdma1 12>,
+ <&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
clock-names = "iis", "i2s_opclk0";
@@ -471,8 +545,8 @@
i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
- dmas = <&pdma0 12
- &pdma0 11>;
+ dmas = <&pdma0 12>,
+ <&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
clock-names = "iis", "i2s_opclk0";
diff --git a/dts/src/arm/exynos5422-odroid-core.dtsi b/dts/src/arm/exynos5422-odroid-core.dtsi
index 829147e..059fa32 100644
--- a/dts/src/arm/exynos5422-odroid-core.dtsi
+++ b/dts/src/arm/exynos5422-odroid-core.dtsi
@@ -34,6 +34,98 @@
clock-frequency = <24000000>;
};
};
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <165000000>;
+ opp-microvolt = <875000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <206000000>;
+ opp-microvolt = <875000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <875000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <413000000>;
+ opp-microvolt = <887500>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <937500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <633000000>;
+ opp-microvolt = <1012500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <728000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ samsung_K3QF2F20DB: lpddr3 {
+ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
+ density = <16384>;
+ io-width = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tRFC-min-tck = <17>;
+ tRRD-min-tck = <2>;
+ tRPab-min-tck = <2>;
+ tRPpb-min-tck = <2>;
+ tRCD-min-tck = <3>;
+ tRC-min-tck = <6>;
+ tRAS-min-tck = <5>;
+ tWTR-min-tck = <2>;
+ tWR-min-tck = <7>;
+ tRTP-min-tck = <2>;
+ tW2W-C2C-min-tck = <0>;
+ tR2R-C2C-min-tck = <0>;
+ tWL-min-tck = <8>;
+ tDQSCK-min-tck = <5>;
+ tRL-min-tck = <14>;
+ tFAW-min-tck = <5>;
+ tXSR-min-tck = <12>;
+ tXP-min-tck = <2>;
+ tCKE-min-tck = <2>;
+ tCKESR-min-tck = <2>;
+ tMRD-min-tck = <5>;
+
+ timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ /* workaround: 'reg' shows max-freq */
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tRFC = <65000>;
+ tRRD = <6000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRCD = <10000>;
+ tRC = <33750>;
+ tRAS = <23000>;
+ tWTR = <3750>;
+ tWR = <7500>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tR2R-C2C = <0>;
+ tFAW = <25000>;
+ tXSR = <70000>;
+ tXP = <3750>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tMRD = <7000>;
+ };
+ };
};
&adc {
@@ -132,6 +224,15 @@
cpu-supply = <&buck2_reg>;
};
+&dmc {
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ operating-points-v2 = <&dmc_opp_table>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
@@ -634,6 +735,22 @@
};
};
+&ppmu_dmc0_0 {
+ status = "okay";
+};
+
+&ppmu_dmc0_1 {
+ status = "okay";
+};
+
+&ppmu_dmc1_0 {
+ status = "okay";
+};
+
+&ppmu_dmc1_1 {
+ status = "okay";
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo7_reg>;
};
diff --git a/dts/src/arm/exynos5422-odroidxu3-lite.dts b/dts/src/arm/exynos5422-odroidxu3-lite.dts
index c19b5a5..a31ca2e 100644
--- a/dts/src/arm/exynos5422-odroidxu3-lite.dts
+++ b/dts/src/arm/exynos5422-odroidxu3-lite.dts
@@ -26,6 +26,10 @@
status = "disabled";
};
+&chipid {
+ samsung,asv-bin = <2>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/dts/src/arm/exynos54xx.dtsi b/dts/src/arm/exynos54xx.dtsi
index 9c3b63b..f78dee8 100644
--- a/dts/src/arm/exynos54xx.dtsi
+++ b/dts/src/arm/exynos54xx.dtsi
@@ -45,8 +45,17 @@
status = "disabled";
};
+ timer: timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ };
+
soc: soc {
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
@@ -64,30 +73,21 @@
};
};
- mct: mct@101c0000 {
+ mct: timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
- <8>, <9>, <10>, <11>;
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &combiner 23 3>,
- <1 &combiner 23 4>,
- <2 &combiner 25 2>,
- <3 &combiner 25 3>,
- <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
- <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
- <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
- <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
- <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
- <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
- <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
- <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&combiner 23 3>,
+ <&combiner 23 4>,
+ <&combiner 25 2>,
+ <&combiner 25 3>,
+ <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@101d0000 {
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index 4398f2d..60ca3d6 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -1034,6 +1034,10 @@
status = "okay";
};
+&timer {
+ arm,cpu-registers-not-fw-configured;
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};
diff --git a/dts/src/arm/exynos5800.dtsi b/dts/src/arm/exynos5800.dtsi
index de639ee..16177d8 100644
--- a/dts/src/arm/exynos5800.dtsi
+++ b/dts/src/arm/exynos5800.dtsi
@@ -17,7 +17,7 @@
};
&clock {
- compatible = "samsung,exynos5800-clock";
+ compatible = "samsung,exynos5800-clock", "syscon";
};
&cluster_a15_opp_table {
diff --git a/dts/src/arm/imx27.dtsi b/dts/src/arm/imx27.dtsi
index 3652f55..f3464cf 100644
--- a/dts/src/arm/imx27.dtsi
+++ b/dts/src/arm/imx27.dtsi
@@ -585,7 +585,7 @@
status = "disabled";
};
- iram: iram@ffff4c00 {
+ iram: sram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
diff --git a/dts/src/arm/imx31.dtsi b/dts/src/arm/imx31.dtsi
index d7f6fb7..6b62f07 100644
--- a/dts/src/arm/imx31.dtsi
+++ b/dts/src/arm/imx31.dtsi
@@ -55,7 +55,7 @@
interrupt-parent = <&avic>;
ranges;
- iram: iram@1fffc000 {
+ iram: sram@1fffc000 {
compatible = "mmio-sram";
reg = <0x1fffc000 0x4000>;
#address-cells = <1>;
diff --git a/dts/src/arm/imx51.dtsi b/dts/src/arm/imx51.dtsi
index 0a4b9a5..dea86b9 100644
--- a/dts/src/arm/imx51.dtsi
+++ b/dts/src/arm/imx51.dtsi
@@ -116,7 +116,7 @@
interrupt-parent = <&tzic>;
ranges;
- iram: iram@1ffe0000 {
+ iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
};
diff --git a/dts/src/arm/imx53-qsb-common.dtsi b/dts/src/arm/imx53-qsb-common.dtsi
index f00dda3..9b4efcd 100644
--- a/dts/src/arm/imx53-qsb-common.dtsi
+++ b/dts/src/arm/imx53-qsb-common.dtsi
@@ -18,34 +18,28 @@
display0: disp0 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
- display-timings {
- claawvga {
- native-mode;
- clock-frequency = <27000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <40>;
- hfront-porch = <60>;
- vback-porch = <10>;
- vfront-porch = <10>;
- hsync-len = <20>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- port {
+ port@0 {
+ reg = <0>;
+
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
gpio-keys {
@@ -84,6 +78,16 @@
};
};
+ panel {
+ compatible = "sii,43wvf1g";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/dts/src/arm/imx53-usbarmory.dts b/dts/src/arm/imx53-usbarmory.dts
index ee6263d..f34993a 100644
--- a/dts/src/arm/imx53-usbarmory.dts
+++ b/dts/src/arm/imx53-usbarmory.dts
@@ -120,7 +120,7 @@
};
/*
- * UART mode pin header configration
+ * UART mode pin header configuration
* 3 - GPIO5[26], pull-down 100K
* 4 - GPIO5[27], pull-down 100K
* 5 - TX, pull-up 100K
diff --git a/dts/src/arm/imx6dl-apf6dev.dts b/dts/src/arm/imx6dl-apf6dev.dts
index 6632e99..3dcce34 100644
--- a/dts/src/arm/imx6dl-apf6dev.dts
+++ b/dts/src/arm/imx6dl-apf6dev.dts
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6dl.dtsi"
diff --git a/dts/src/arm/imx6dl-colibri-eval-v3.dts b/dts/src/arm/imx6dl-colibri-eval-v3.dts
index 9a5d6c9..cd07562 100644
--- a/dts/src/arm/imx6dl-colibri-eval-v3.dts
+++ b/dts/src/arm/imx6dl-colibri-eval-v3.dts
@@ -168,6 +168,21 @@
&i2c3 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@@ -175,6 +190,30 @@
};
};
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
+ &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+ >;
+
+ pinctrl_pcap_1: pcap1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_mxt_ts: mxttsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
+ >;
+ };
+};
+
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
diff --git a/dts/src/arm/imx6dl-yapp4-common.dtsi b/dts/src/arm/imx6dl-yapp4-common.dtsi
index e8d800f..80ed5f1 100644
--- a/dts/src/arm/imx6dl-yapp4-common.dtsi
+++ b/dts/src/arm/imx6dl-yapp4-common.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
@@ -308,7 +309,7 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
- status = "disabled";
+ status = "okay";
oled: oled@3d {
compatible = "solomon,ssd1305fb-i2c";
@@ -330,6 +331,18 @@
vcc-supply = <&sw2_reg>;
status = "disabled";
};
+
+ touchkeys: keys@5a {
+ compatible = "fsl,mpr121-touchkey";
+ reg = <0x5a>;
+ vdd-supply = <&sw2_reg>;
+ autorepeat;
+ linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
+ <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
+ <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
+ poll-interval = <50>;
+ status = "disabled";
+ };
};
&iomuxc {
@@ -447,6 +460,13 @@
>;
};
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
+ >;
+ };
+
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
@@ -532,6 +552,12 @@
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
diff --git a/dts/src/arm/imx6dl-yapp4-hydra.dts b/dts/src/arm/imx6dl-yapp4-hydra.dts
index f979270..6010d3d 100644
--- a/dts/src/arm/imx6dl-yapp4-hydra.dts
+++ b/dts/src/arm/imx6dl-yapp4-hydra.dts
@@ -25,10 +25,6 @@
status = "okay";
};
-&i2c3 {
- status = "okay";
-};
-
&leds {
status = "okay";
};
@@ -45,6 +41,10 @@
status = "okay";
};
+&touchkeys {
+ status = "okay";
+};
+
&usdhc3 {
status = "okay";
};
diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi
index 2ed1031..008312e 100644
--- a/dts/src/arm/imx6dl.dtsi
+++ b/dts/src/arm/imx6dl.dtsi
@@ -64,6 +64,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
diff --git a/dts/src/arm/imx6q-apalis-eval.dts b/dts/src/arm/imx6q-apalis-eval.dts
index 0edd304..4665e15 100644
--- a/dts/src/arm/imx6q-apalis-eval.dts
+++ b/dts/src/arm/imx6q-apalis-eval.dts
@@ -167,6 +167,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
diff --git a/dts/src/arm/imx6q-apalis-ixora-v1.1.dts b/dts/src/arm/imx6q-apalis-ixora-v1.1.dts
index b94bb68..a3fa04a 100644
--- a/dts/src/arm/imx6q-apalis-ixora-v1.1.dts
+++ b/dts/src/arm/imx6q-apalis-ixora-v1.1.dts
@@ -172,6 +172,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
diff --git a/dts/src/arm/imx6q-apalis-ixora.dts b/dts/src/arm/imx6q-apalis-ixora.dts
index 302fd6a..5ba49d0 100644
--- a/dts/src/arm/imx6q-apalis-ixora.dts
+++ b/dts/src/arm/imx6q-apalis-ixora.dts
@@ -171,6 +171,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
diff --git a/dts/src/arm/imx6q-apf6dev.dts b/dts/src/arm/imx6q-apf6dev.dts
index 07a36bb..664b0af 100644
--- a/dts/src/arm/imx6q-apf6dev.dts
+++ b/dts/src/arm/imx6q-apf6dev.dts
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6q.dtsi"
diff --git a/dts/src/arm/imx6q-dhcom-pdk2.dts b/dts/src/arm/imx6q-dhcom-pdk2.dts
index 9c61e3b..5219553 100644
--- a/dts/src/arm/imx6q-dhcom-pdk2.dts
+++ b/dts/src/arm/imx6q-dhcom-pdk2.dts
@@ -43,6 +43,14 @@
status = "okay";
};
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6q-dhcom-som.dtsi b/dts/src/arm/imx6q-dhcom-som.dtsi
index 387801d..845cfad 100644
--- a/dts/src/arm/imx6q-dhcom-som.dtsi
+++ b/dts/src/arm/imx6q-dhcom-som.dtsi
@@ -51,13 +51,11 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
};
&ecspi1 {
diff --git a/dts/src/arm/imx6q-gw54xx.dts b/dts/src/arm/imx6q-gw54xx.dts
index ecc3989..d5d4690 100644
--- a/dts/src/arm/imx6q-gw54xx.dts
+++ b/dts/src/arm/imx6q-gw54xx.dts
@@ -15,19 +15,16 @@
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_codec>;
+ simple-audio-card,frame-master = <&sound_codec>;
- simple-audio-card,dai-link@0 {
- format = "i2s";
-
- cpu {
- sound-dai = <&ssi2>;
- };
+ sound_cpu: simple-audio-card,cpu {
+ sound-dai = <&ssi2>;
+ };
- codec {
- bitclock-master;
- frame-master;
- sound-dai = <&hdmi_receiver>;
- };
+ sound_codec: simple-audio-card,codec {
+ sound-dai = <&hdmi_receiver>;
};
};
};
diff --git a/dts/src/arm/imx6q.dtsi b/dts/src/arm/imx6q.dtsi
index d038f41..9d3be1c 100644
--- a/dts/src/arm/imx6q.dtsi
+++ b/dts/src/arm/imx6q.dtsi
@@ -73,6 +73,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -107,6 +108,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -141,6 +143,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi
index 7c4ad54..ff1287e 100644
--- a/dts/src/arm/imx6qdl-apalis.dtsi
+++ b/dts/src/arm/imx6qdl-apalis.dtsi
@@ -148,14 +148,16 @@
};
&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan1_default>;
+ pinctrl-1 = <&pinctrl_flexcan1_sleep>;
status = "disabled";
};
&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan2_default>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
status = "disabled";
};
@@ -205,8 +207,11 @@
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -216,8 +221,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@@ -372,9 +380,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default", "recovery";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@@ -599,19 +607,32 @@
>;
};
- pinctrl_flexcan1: flexcan1grp {
+ pinctrl_flexcan1_default: flexcan1defgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
- pinctrl_flexcan2: flexcan2grp {
+ pinctrl_flexcan1_sleep: flexcan1slpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
+ >;
+ };
+
+ pinctrl_flexcan2_default: flexcan2defgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
+ pinctrl_flexcan2_sleep: flexcan2slpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
+ >;
+ };
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
@@ -646,6 +667,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -653,6 +681,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
@@ -660,7 +695,7 @@
>;
};
- pinctrl_i2c3_recovery: i2c3recoverygrp {
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
diff --git a/dts/src/arm/imx6qdl-apf6.dtsi b/dts/src/arm/imx6qdl-apf6.dtsi
index 4738c3c..b78ed79 100644
--- a/dts/src/arm/imx6qdl-apf6.dtsi
+++ b/dts/src/arm/imx6qdl-apf6.dtsi
@@ -1,66 +1,56 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&reg_3p3v>;
+ };
+
+ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <15>;
+ power-off-delay-us = <70>;
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ phy-handle = <&ethphy1>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
status = "okay";
};
@@ -68,6 +58,12 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ cap-power-off-card;
+ keep-power-in-suspend;
non-removable;
status = "okay";
@@ -94,65 +90,63 @@
};
&iomuxc {
- apf6 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
- >;
- };
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ >;
+ };
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
- >;
- };
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
+ >;
+ };
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
- >;
- };
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
+ >;
+ };
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
};
};
diff --git a/dts/src/arm/imx6qdl-apf6dev.dtsi b/dts/src/arm/imx6qdl-apf6dev.dtsi
index 9fc1fa4..b8e74ab 100644
--- a/dts/src/arm/imx6qdl-apf6dev.dtsi
+++ b/dts/src/arm/imx6qdl-apf6dev.dtsi
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -54,35 +11,37 @@
stdout-path = &uart4;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <0>;
+ power-supply = <&reg_5v>;
+ };
+
disp0 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "bgr666";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_disp1>;
-
- display-timings {
- lw700 {
- clock-frequency = <33000033>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <96>;
- hfront-porch = <96>;
- vback-porch = <20>;
- vfront-porch = <21>;
- hsync-len = <64>;
- vsync-len = <4>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
+ pinctrl-0 = <&pinctrl_ipu1_disp0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
- port {
display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
gpio-keys {
@@ -111,17 +70,30 @@
};
};
+ panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <&reg_3p3v>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
+ vin-supply = <&reg_5v>;
};
- reg_usbh1_vbus: regulator-usb-h1-vbus {
+ reg_5v: regulator-5v {
compatible = "regulator-fixed";
- regulator-name = "usb_h1_vbus";
+ regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
@@ -166,6 +138,7 @@
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_5v>;
status = "okay";
};
@@ -212,6 +185,11 @@
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
+
+ rtc@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
};
&i2c3 {
@@ -261,7 +239,7 @@
};
&usbh1 {
- vbus-supply = <&reg_usbh1_vbus>;
+ vbus-supply = <&reg_5v>;
phy_type = "utmi";
status = "okay";
};
@@ -297,178 +275,176 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
- apf6dev {
- pinctrl_audmux: audmuxgrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
- >;
- };
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
- >;
- };
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
- >;
- };
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
- >;
- };
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
- >;
- };
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
+ >;
+ };
- pinctrl_gpios: gpiosgrp {
- fsl,pins = <
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
- >;
- };
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ >;
+ };
- pinctrl_gsm: gsmgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
- >;
- };
+ pinctrl_gsm: gsmgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
+ >;
+ };
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
- >;
- };
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- >;
- };
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ >;
+ };
- pinctrl_ipu1_disp1: ipu1disp1grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
- >;
- };
+ pinctrl_ipu1_disp0: ipu1disp0grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
+ >;
+ };
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
- >;
- };
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
+ >;
+ };
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
- >;
- };
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
+ >;
+ };
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
- >;
- };
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
+ >;
+ };
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
- >;
- };
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
+ >;
+ };
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
- >;
- };
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
+ >;
+ };
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
- pinctrl_spdif: spdifgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
- >;
- };
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
- pinctrl_touchscreen: touchscreengrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
- >;
- };
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
+ >;
};
};
diff --git a/dts/src/arm/imx6qdl-colibri.dtsi b/dts/src/arm/imx6qdl-colibri.dtsi
index 019dda6..d03dff2 100644
--- a/dts/src/arm/imx6qdl-colibri.dtsi
+++ b/dts/src/arm/imx6qdl-colibri.dtsi
@@ -166,8 +166,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-0 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@@ -312,9 +315,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default", "recovery";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@@ -426,6 +429,9 @@
};
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_oc_1>;
+
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
@@ -509,6 +515,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -516,7 +529,7 @@
>;
};
- pinctrl_i2c3_recovery: i2c3recoverygrp {
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
@@ -615,6 +628,13 @@
>;
};
+ pinctrl_usbh_oc_1: usbhoc1grp {
+ fsl,pins = <
+ /* USBH_OC */
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
@@ -681,6 +701,13 @@
>;
};
+ pinctrl_usbc_id_1: usbc_id-1 {
+ fsl,pins = <
+ /* USBC_ID */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
diff --git a/dts/src/arm/imx6qdl-gw551x.dtsi b/dts/src/arm/imx6qdl-gw551x.dtsi
index c23ba22..c38e86e 100644
--- a/dts/src/arm/imx6qdl-gw551x.dtsi
+++ b/dts/src/arm/imx6qdl-gw551x.dtsi
@@ -105,19 +105,16 @@
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_codec>;
+ simple-audio-card,frame-master = <&sound_codec>;
- simple-audio-card,dai-link@0 {
- format = "i2s";
-
- cpu {
- sound-dai = <&ssi2>;
- };
+ sound_cpu: simple-audio-card,cpu {
+ sound-dai = <&ssi2>;
+ };
- codec {
- bitclock-master;
- frame-master;
- sound-dai = <&hdmi_receiver>;
- };
+ sound_codec: simple-audio-card,codec {
+ sound-dai = <&hdmi_receiver>;
};
};
};
diff --git a/dts/src/arm/imx6qdl-rex.dtsi b/dts/src/arm/imx6qdl-rex.dtsi
index 97f1659..de514eb 100644
--- a/dts/src/arm/imx6qdl-rex.dtsi
+++ b/dts/src/arm/imx6qdl-rex.dtsi
@@ -132,6 +132,19 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ pca9535: gpio-expander@27 {
+ compatible = "nxp,pca9535";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9535>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
@@ -237,6 +250,12 @@
>;
};
+ pinctrl_pca9535: pca9535grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
diff --git a/dts/src/arm/imx6qdl-udoo.dtsi b/dts/src/arm/imx6qdl-udoo.dtsi
index 776bfc7..828dd20 100644
--- a/dts/src/arm/imx6qdl-udoo.dtsi
+++ b/dts/src/arm/imx6qdl-udoo.dtsi
@@ -210,6 +210,14 @@
>;
};
+ pinctrl_usbotg: usbotg {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059
+ MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -287,6 +295,12 @@
status = "okay";
};
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ status = "okay";
+};
+
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
diff --git a/dts/src/arm/imx6qdl-wandboard.dtsi b/dts/src/arm/imx6qdl-wandboard.dtsi
index 2cfb411..c070893 100644
--- a/dts/src/arm/imx6qdl-wandboard.dtsi
+++ b/dts/src/arm/imx6qdl-wandboard.dtsi
@@ -279,8 +279,18 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
+ phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
};
&mipi_csi {
diff --git a/dts/src/arm/imx6qdl-zii-rdu2.dtsi b/dts/src/arm/imx6qdl-zii-rdu2.dtsi
index 93be00a..a2a4f33 100644
--- a/dts/src/arm/imx6qdl-zii-rdu2.dtsi
+++ b/dts/src/arm/imx6qdl-zii-rdu2.dtsi
@@ -358,8 +358,10 @@
compatible = "fsl,mma8451";
reg = <0x1c>;
interrupt-parent = <&gpio1>;
- interrupt-names = "int1", "int2";
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT2";
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&reg_3p3v>;
+ vddio-supply = <&reg_3p3v>;
};
hpa2: amp@60 {
@@ -849,7 +851,6 @@
&iomuxc {
pinctrl_accel: accelgrp {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x4001b000
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
>;
};
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index 3a96b55..59c54e6 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -525,7 +525,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/src/arm/imx6sll-kobo-clarahd.dts b/dts/src/arm/imx6sll-kobo-clarahd.dts
new file mode 100644
index 0000000..7214d1c
--- /dev/null
+++ b/dts/src/arm/imx6sll-kobo-clarahd.dts
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Kobo Clara HD ebook reader
+ *
+ * Name on mainboard is: 37NB-E60K00+4A4
+ * Serials start with: E60K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Kobo Clara HD ebook reader it is an i.MX6SLL
+ *
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sll.dtsi"
+#include "e60k02.dtsi"
+
+/ {
+ model = "Kobo Clara HD";
+ compatible = "kobo,clarahd", "fsl,imx6sll";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+ arm-supply = <&dcdc3_reg>;
+ soc-supply = <&dcdc1_reg>;
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */
+ MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79
+ MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79
+ MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79
+ MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79
+ MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79
+ MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79
+ MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79
+ MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79
+ MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79
+ MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79
+ MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79
+ MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79
+ MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79
+ MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79
+ MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79
+ MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79
+ MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79
+ MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79
+ MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79
+ MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79
+ MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79
+ MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79
+ MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79
+ MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79
+ MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79
+ MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9
+ MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9
+ MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9
+ MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1
+ MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1
+ MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1
+ MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+&reg_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/dts/src/arm/imx6sll.dtsi b/dts/src/arm/imx6sll.dtsi
index 13c7ba7..85aa8bb 100644
--- a/dts/src/arm/imx6sll.dtsi
+++ b/dts/src/arm/imx6sll.dtsi
@@ -507,7 +507,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sll-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x4000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi
index 531a52c..59bad60 100644
--- a/dts/src/arm/imx6sx.dtsi
+++ b/dts/src/arm/imx6sx.dtsi
@@ -594,7 +594,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/src/arm/imx6ul-14x14-evk.dtsi b/dts/src/arm/imx6ul-14x14-evk.dtsi
index c2a9dd5..1506eb1 100644
--- a/dts/src/arm/imx6ul-14x14-evk.dtsi
+++ b/dts/src/arm/imx6ul-14x14-evk.dtsi
@@ -30,6 +30,16 @@
enable-active-high;
};
+ reg_sensors: regulator-sensors {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sensors_reg>;
+ regulator-name = "sensors-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ };
+
reg_can_3v3: regulator-can-3v3 {
compatible = "regulator-fixed";
regulator-name = "can-3v3";
@@ -180,9 +190,11 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- mag3110@e {
+ magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
+ vdd-supply = <&reg_sensors>;
+ vddio-supply = <&reg_sensors>;
};
};
@@ -266,6 +278,8 @@
&usbotg1 {
dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
status = "okay";
};
@@ -448,6 +462,12 @@
>;
};
+ pinctrl_sensors_reg: sensorsreggrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
@@ -499,6 +519,12 @@
>;
};
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
diff --git a/dts/src/arm/imx6ul-imx6ull-opos6ul.dtsi b/dts/src/arm/imx6ul-imx6ull-opos6ul.dtsi
new file mode 100644
index 0000000..f2386dc
--- /dev/null
+++ b/dts/src/arm/imx6ul-imx6ull-opos6ul.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-handle = <&ethphy1>;
+ phy-supply = <&reg_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
+/* Bluetooth */
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
+ /* RST# */
+ MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
+ /* BT_REG_ON */
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
+ MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
+ MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
+ MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
+ /* WL_REG_ON */
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
+ /* WL_IRQ */
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-imx6ull-opos6uldev.dtsi b/dts/src/arm/imx6ul-imx6ull-opos6uldev.dtsi
new file mode 100644
index 0000000..1896635
--- /dev/null
+++ b/dts/src/arm/imx6ul-imx6ull-opos6uldev.dtsi
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <&reg_5v>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user-button {
+ label = "User button";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user-led {
+ label = "User";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_w1>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel: panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <&reg_3v3>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbotg1_vbus: regulator-usbotg1vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg1vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg2_vbus: regulator-usbotg2vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg2vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&adc1 {
+ vref-supply = <&reg_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_5v>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_5v>;
+ status = "okay";
+};
+
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ };
+
+ spidev1: spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ vbus-supply = <&reg_usbotg1_vbus>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbotg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpios>;
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
+ MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
+ MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
+ MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
+ MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
+ MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: usbotg1vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-kontron-n6310-s.dts b/dts/src/arm/imx6ul-kontron-n6310-s.dts
index 0205fd5..5a3e06d 100644
--- a/dts/src/arm/imx6ul-kontron-n6310-s.dts
+++ b/dts/src/arm/imx6ul-kontron-n6310-s.dts
@@ -8,413 +8,10 @@
/dts-v1/;
#include "imx6ul-kontron-n6310-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N6310 S";
compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
"fsl,imx6ul";
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led1 {
- label = "debug-led1";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- label = "debug-led2";
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- label = "debug-led3";
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pwm-beeper {
- compatible = "pwm-beeper";
- pwms = <&pwm8 0 5000>;
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vref_adc: regulator-vref-adc {
- compatible = "regulator-fixed";
- regulator-name = "vref-adc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc1>;
- num-channels = <3>;
- vref-supply = <&reg_vref_adc>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- eeprom@0 {
- compatible = "anvo,anv32e61w", "atmel,at25";
- reg = <0>;
- spi-max-frequency = <20000000>;
- spi-cpha;
- spi-cpol;
- pagesize = <1>;
- size = <8192>;
- address-width = <16>;
- };
-};
-
-&fec1 {
- pinctrl-0 = <&pinctrl_enet1>;
- /delete-node/ mdio;
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
- phy-mode = "rmii";
- phy-handle = <&ethphy2>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET2_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- rtc@32 {
- compatible = "epson,rx8900";
- reg = <0x32>;
- };
-};
-
-&pwm8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm8>;
- status = "okay";
-};
-
-&snvs_poweroff {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- linux,rs485-enabled-at-boot-time;
- rs485-rx-during-tx;
- rs485-rts-active-low;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- fsl,uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- dr_mode = "otg";
- srp-disable;
- hnp-disable;
- adp-disable;
- vbus-supply = <&reg_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <&reg_3v3>;
- voltage-ranges = <3300 3300>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- non-removable;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <&reg_3v3>;
- voltage-ranges = <3300 3300>;
- no-1-8-v;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
-
- pinctrl_adc1: adc1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
- >;
- };
-
- /* FRAM */
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
- MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
- MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
- >;
- };
-
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
- >;
- };
-
- pinctrl_enet2_mdio: enet2mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp{
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
- >;
- };
-
- pinctrl_gpio: gpiogrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
- MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
- >;
- };
-
- pinctrl_pwm8: pwm8grp {
- fsl,pins = <
- MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
- MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
- /*
- * mux unused RTS to make sure it doesn't cause
- * any interrupts when it is undefined
- */
- MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1: usbotg1 {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
- >;
- };
};
diff --git a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi b/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
index a896b23..47d3ce5 100644
--- a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
+++ b/dts/src/arm/imx6ul-kontron-n6310-som.dtsi
@@ -6,7 +6,7 @@
*/
#include "imx6ul.dtsi"
-#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N6310 SOM";
@@ -18,49 +18,7 @@
};
};
-&ecspi2 {
- cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- status = "okay";
-
- spi-flash@0 {
- compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
- phy-mode = "rmii";
- phy-handle = <&ethphy1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-&fec2 {
- phy-mode = "rmii";
- status = "disabled";
-};
-
&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -81,54 +39,3 @@
};
};
};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reset_out>;
-
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
- MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
- MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
- >;
- };
-
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
- >;
- };
-
- pinctrl_enet1_mdio: enet1mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
- MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
- MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
- MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
- >;
- };
-
- pinctrl_reset_out: rstoutgrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
- >;
- };
-};
diff --git a/dts/src/arm/imx6ul-kontron-n6311-s.dts b/dts/src/arm/imx6ul-kontron-n6311-s.dts
new file mode 100644
index 0000000..239a1af
--- /dev/null
+++ b/dts/src/arm/imx6ul-kontron-n6311-s.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-n6311-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N6311 S";
+ compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som",
+ "fsl,imx6ul";
+};
diff --git a/dts/src/arm/imx6ul-kontron-n6311-som.dtsi b/dts/src/arm/imx6ul-kontron-n6311-som.dtsi
new file mode 100644
index 0000000..a095a76
--- /dev/null
+++ b/dts/src/arm/imx6ul-kontron-n6311-som.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N6311 SOM";
+ compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&qspi {
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+
+ partition@0 {
+ label = "ubi1";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ partition@8000000 {
+ label = "ubi2";
+ reg = <0x08000000 0x18000000>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi b/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi
new file mode 100644
index 0000000..f05e918
--- /dev/null
+++ b/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <&reg_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <&reg_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&reg_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&reg_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi
new file mode 100644
index 0000000..a17af4d
--- /dev/null
+++ b/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6ul-opos6ul.dtsi b/dts/src/arm/imx6ul-opos6ul.dtsi
index cf7faf4..6ce84f9 100644
--- a/dts/src/arm/imx6ul-opos6ul.dtsi
+++ b/dts/src/arm/imx6ul-opos6ul.dtsi
@@ -1,193 +1,6 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
#include "imx6ul.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0>; /* will be filled by U-Boot */
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- usdhc3_pwrseq: usdhc3-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-reset-duration = <1>;
- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- phy-handle = <&ethphy1>;
- phy-supply = <&reg_3v3>;
- status = "okay";
-
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
- };
- };
-};
-
-/* Bluetooth */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart8>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- status = "okay";
-};
-
-/* WiFi */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- no-1-8-v;
- non-removable;
- mmc-pwrseq = <&usdhc3_pwrseq>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio2>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "host-wake";
- };
-};
-
-&iomuxc {
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- /* INT# */
- MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
- /* RST# */
- MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
- >;
- };
-
- pinctrl_uart8: uart8grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
- /* BT_REG_ON */
- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
- MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
- MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
- MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
- MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
- MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
- MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
- MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
- MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
- /* WL_REG_ON */
- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
- /* WL_IRQ */
- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
- >;
- };
-};
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/dts/src/arm/imx6ul-opos6uldev.dts b/dts/src/arm/imx6ul-opos6uldev.dts
index 8ecdb9a..375b98d 100644
--- a/dts/src/arm/imx6ul-opos6uldev.dts
+++ b/dts/src/arm/imx6ul-opos6uldev.dts
@@ -1,293 +1,21 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
- model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
- compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
-
- chosen {
- stdout-path = &uart1;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm3 0 191000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
- power-supply = <&reg_5v>;
- status = "okay";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- user-button {
- label = "User button";
- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_MISC>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- user-led {
- label = "User";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_led>;
- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- onewire {
- compatible = "w1-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_w1>;
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- };
-
- panel: panel {
- compatible = "armadeus,st0700-adapt";
- power-supply = <&reg_3v3>;
- backlight = <&backlight>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbotg1_vbus: regulator-usbotg1vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg1vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_vbus>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usbotg2_vbus: regulator-usbotg2vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg2vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg2_vbus>;
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&adc1 {
- vref-supply = <&reg_3v3>;
- status = "okay";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <&reg_5v>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <&reg_5v>;
- status = "okay";
-};
-
-&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- spidev0: spi@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <5000000>;
- };
-
- spidev1: spi@1 {
- compatible = "spidev";
- reg = <1>;
- spi-max-frequency = <5000000>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif>;
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "disabled";
-};
-
-&tsc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- measure-delay-time = <0xffff>;
- pre-charge-time = <0xffff>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- vbus-supply = <&reg_usbotg1_vbus>;
- dr_mode = "otg";
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- vbus-supply = <&reg_usbotg2_vbus>;
- dr_mode = "host";
- disable-over-current;
- status = "okay";
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};
&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpios>;
+ pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
- pinctrl_ecspi4: ecspi4grp {
+ pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
- MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
- MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
- MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
- MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
- MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
- >;
- };
-
- pinctrl_gpios: gpiosgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
- MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
- MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
@@ -299,100 +27,6 @@
>;
};
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
- >;
- };
-
- pinctrl_led: ledgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
- >;
- };
-
- pinctrl_tsc: tscgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1_id: usbotg1idgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
- >;
- };
-
- pinctrl_usbotg1_vbus: usbotg1vbusgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
- >;
- };
-
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
diff --git a/dts/src/arm/imx6ul-phytec-phycore-som.dtsi b/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
index 41f3b7f..88f631c 100644
--- a/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
+++ b/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
@@ -20,7 +20,7 @@
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};
diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi
index f008036..d9fdca1 100644
--- a/dts/src/arm/imx6ul.dtsi
+++ b/dts/src/arm/imx6ul.dtsi
@@ -558,7 +558,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -711,6 +711,7 @@
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
<&clks IMX6UL_CLK_GPT2_SERIAL>;
clock-names = "ipg", "per";
+ status = "disabled";
};
sdma: sdma@20ec000 {
diff --git a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
index b6147c7..a78849f 100644
--- a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
+++ b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
@@ -8,6 +8,20 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
diff --git a/dts/src/arm/imx6ull-colibri-nonwifi.dtsi b/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
index fb213be..95a11b8 100644
--- a/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
+++ b/dts/src/arm/imx6ull-colibri-nonwifi.dtsi
@@ -15,7 +15,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+ &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
diff --git a/dts/src/arm/imx6ull-colibri-wifi.dtsi b/dts/src/arm/imx6ull-colibri-wifi.dtsi
index 038d8c9..a054543 100644
--- a/dts/src/arm/imx6ull-colibri-wifi.dtsi
+++ b/dts/src/arm/imx6ull-colibri-wifi.dtsi
@@ -26,7 +26,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5>;
+ &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
};
diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi
index d56728f..6d850d9 100644
--- a/dts/src/arm/imx6ull-colibri.dtsi
+++ b/dts/src/arm/imx6ull-colibri.dtsi
@@ -54,6 +54,18 @@
vref-supply = <&reg_module_3v3_avdd>;
};
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
/* Colibri SPI */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
@@ -62,8 +74,9 @@
};
&fec2 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
+ pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
@@ -198,6 +211,12 @@
assigned-clock-rates = <0>, <198000000>;
};
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
&iomuxc {
pinctrl_can_int: canint-grp {
fsl,pins = <
@@ -220,6 +239,21 @@
>;
};
+ pinctrl_enet2_sleep: enet2sleepgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
+ MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
+ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
+ >;
+ };
+
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
@@ -234,6 +268,13 @@
>;
};
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
+ MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
+ >;
+ };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
@@ -249,8 +290,6 @@
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
- MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
@@ -303,6 +342,13 @@
>;
};
+ pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
@@ -490,6 +536,12 @@
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
>;
};
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
};
&iomuxc_snvs {
@@ -517,19 +569,19 @@
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
diff --git a/dts/src/arm/imx6ull-kontron-n6411-s.dts b/dts/src/arm/imx6ull-kontron-n6411-s.dts
new file mode 100644
index 0000000..57588a5
--- /dev/null
+++ b/dts/src/arm/imx6ull-kontron-n6411-s.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-n6411-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N6411 S";
+ compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som",
+ "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-kontron-n6411-som.dtsi b/dts/src/arm/imx6ull-kontron-n6411-som.dtsi
new file mode 100644
index 0000000..b7e9842
--- /dev/null
+++ b/dts/src/arm/imx6ull-kontron-n6411-som.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N6411 SOM";
+ compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&qspi {
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+
+ partition@0 {
+ label = "ubi1";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ partition@8000000 {
+ label = "ubi2";
+ reg = <0x08000000 0x18000000>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx6ull-opos6ul.dtsi b/dts/src/arm/imx6ull-opos6ul.dtsi
new file mode 100644
index 0000000..155f941
--- /dev/null
+++ b/dts/src/arm/imx6ull-opos6ul.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+#include "imx6ull.dtsi"
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/dts/src/arm/imx6ull-opos6uldev.dts b/dts/src/arm/imx6ull-opos6uldev.dts
new file mode 100644
index 0000000..198fdb7
--- /dev/null
+++ b/dts/src/arm/imx6ull-opos6uldev.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/dts-v1/;
+#include "imx6ull-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
+
+/ {
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tamper_gpios>;
+
+ pinctrl_tamper_gpios: tampergpiosgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
+ >;
+ };
+
+ pinctrl_usbotg2_vbus: usbotg2vbusgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_w1: w1grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7-colibri-eval-v3.dtsi b/dts/src/arm/imx7-colibri-eval-v3.dtsi
index 3f27461..6aa123c 100644
--- a/dts/src/arm/imx7-colibri-eval-v3.dtsi
+++ b/dts/src/arm/imx7-colibri-eval-v3.dtsi
@@ -52,6 +52,20 @@
clock-frequency = <16000000>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
panel: panel {
compatible = "edt,et057090dhu";
backlight = <&bl>;
@@ -131,6 +145,21 @@
&i2c4 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
compatible = "st,m41t0";
@@ -186,3 +215,12 @@
vmmc-supply = <&reg_3v3>;
status = "okay";
};
+
+&iomuxc {
+ pinctrl_gpiotouch: touchgpios {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7-colibri.dtsi b/dts/src/arm/imx7-colibri.dtsi
index 917eb0b..d05be3f 100644
--- a/dts/src/arm/imx7-colibri.dtsi
+++ b/dts/src/arm/imx7-colibri.dtsi
@@ -322,7 +322,6 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
- no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <&reg_LDO2>;
@@ -667,6 +666,28 @@
>;
};
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
@@ -737,12 +758,17 @@
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
>;
};
+ pinctrl_gpiokeys: gpiokeysgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
+ >;
+ };
+
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi
index 9c8dd32..d8acd7c 100644
--- a/dts/src/arm/imx7d.dtsi
+++ b/dts/src/arm/imx7d.dtsi
@@ -22,6 +22,7 @@
reg = <1>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
@@ -43,7 +44,8 @@
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
- opp-supported-hw = <0xf>, <0xf>;
+ opp-supported-hw = <0xd>, <0xf>;
+ opp-suspend;
};
opp-996000000 {
@@ -51,6 +53,7 @@
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xc>, <0xf>;
+ opp-suspend;
};
opp-1200000000 {
@@ -58,6 +61,7 @@
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0x8>, <0xf>;
+ opp-suspend;
};
};
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index e2e604d..1b812f4 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -559,7 +559,7 @@
anatop: anatop@30360000 {
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/imx7ulp-evk.dts b/dts/src/arm/imx7ulp-evk.dts
index 4245b33..a863a2b 100644
--- a/dts/src/arm/imx7ulp-evk.dts
+++ b/dts/src/arm/imx7ulp-evk.dts
@@ -77,6 +77,8 @@
};
&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
diff --git a/dts/src/arm/imx7ulp.dtsi b/dts/src/arm/imx7ulp.dtsi
index 6859a3a..d37a192 100644
--- a/dts/src/arm/imx7ulp.dtsi
+++ b/dts/src/arm/imx7ulp.dtsi
@@ -87,13 +87,6 @@
#clock-cells = <0>;
};
- mpll: clock-mpll {
- compatible = "fixed-clock";
- clock-frequency = <480000000>;
- clock-output-names = "mpll";
- #clock-cells = <0>;
- };
-
ahbbridge0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -230,8 +223,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -246,8 +237,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -258,12 +247,22 @@
compatible = "fsl,imx7ulp-scg1";
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
- <&firc>, <&upll>, <&mpll>;
+ <&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
- "firc", "upll", "mpll";
+ "firc", "upll";
#clock-cells = <1>;
};
+ wdog1: watchdog@403d0000 {
+ compatible = "fsl,imx7ulp-wdt";
+ reg = <0x403d0000 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
+ timeout-sec = <40>;
+ };
+
pcc2: clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
@@ -276,13 +275,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
@@ -309,13 +307,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
};
diff --git a/dts/src/arm/keystone-clocks.dtsi b/dts/src/arm/keystone-clocks.dtsi
index 457515b..0397c34 100644
--- a/dts/src/arm/keystone-clocks.dtsi
+++ b/dts/src/arm/keystone-clocks.dtsi
@@ -408,4 +408,31 @@ clocks {
reg-names = "control", "domain";
domain-id = <0>;
};
+
+ /*
+ * Below are set of fixed, input clocks definitions,
+ * for which real frequencies have to be defined in board files.
+ * Those clocks can be used as reference clocks for some HW modules
+ * (as cpts, for example) by configuring corresponding clock muxes.
+ */
+ timi0: timi0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "timi0";
+ };
+
+ timi1: timi1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "timi1";
+ };
+
+ tsrefclk: tsrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsrefclk";
+ };
};
diff --git a/dts/src/arm/keystone-k2e-clocks.dtsi b/dts/src/arm/keystone-k2e-clocks.dtsi
index f759215..cf30e00 100644
--- a/dts/src/arm/keystone-k2e-clocks.dtsi
+++ b/dts/src/arm/keystone-k2e-clocks.dtsi
@@ -71,4 +71,24 @@ clocks {
reg-names = "control", "domain";
domain-id = <29>;
};
+
+ /*
+ * Below are set of fixed, input clocks definitions,
+ * for which real frequencies have to be defined in board files.
+ * Those clocks can be used as reference clocks for some HW modules
+ * (as cpts, for example) by configuring corresponding clock muxes.
+ */
+ tsipclka: tsipclka {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsipclka";
+ };
+
+ tsipclkb: tsipclkb {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsipclkb";
+ };
};
diff --git a/dts/src/arm/keystone-k2e-netcp.dtsi b/dts/src/arm/keystone-k2e-netcp.dtsi
index 1db17ec..ad15e77 100644
--- a/dts/src/arm/keystone-k2e-netcp.dtsi
+++ b/dts/src/arm/keystone-k2e-netcp.dtsi
@@ -135,8 +135,8 @@ netcp: netcp@24000000 {
/* NetCP address range */
ranges = <0 0x24000000 0x1000000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 0>,
@@ -156,6 +156,23 @@ netcp: netcp@24000000 {
tx-queue = <896>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsipclka>, <&tsrefclk>,
+ <&tsipclkb>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x4>, <0x8>, <0xC>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/dts/src/arm/keystone-k2hk-netcp.dtsi b/dts/src/arm/keystone-k2hk-netcp.dtsi
index e203145..d5a6c1f 100644
--- a/dts/src/arm/keystone-k2hk-netcp.dtsi
+++ b/dts/src/arm/keystone-k2hk-netcp.dtsi
@@ -152,8 +152,8 @@ netcp: netcp@2000000 {
/* NetCP address range */
ranges = <0 0x2000000 0x100000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 22>,
@@ -175,6 +175,22 @@ netcp: netcp@2000000 {
tx-queue = <648>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsrefclk>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x8>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/dts/src/arm/keystone-k2l-netcp.dtsi b/dts/src/arm/keystone-k2l-netcp.dtsi
index a2e47ba..c1f9826 100644
--- a/dts/src/arm/keystone-k2l-netcp.dtsi
+++ b/dts/src/arm/keystone-k2l-netcp.dtsi
@@ -134,8 +134,8 @@ netcp: netcp@26000000 {
/* NetCP address range */
ranges = <0 0x26000000 0x1000000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 0>,
@@ -155,6 +155,22 @@ netcp: netcp@26000000 {
tx-queue = <896>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsrefclk>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x8>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/dts/src/arm/kirkwood-synology.dtsi b/dts/src/arm/kirkwood-synology.dtsi
index c97ed29..217bd37 100644
--- a/dts/src/arm/kirkwood-synology.dtsi
+++ b/dts/src/arm/kirkwood-synology.dtsi
@@ -244,7 +244,7 @@
rs5c372: rs5c372@32 {
status = "disabled";
- compatible = "ricoh,rs5c372";
+ compatible = "ricoh,rs5c372a";
reg = <0x32>;
};
diff --git a/dts/src/arm/logicpd-som-lv-35xx-devkit.dts b/dts/src/arm/logicpd-som-lv-35xx-devkit.dts
index f7a841a..2a0a98f 100644
--- a/dts/src/arm/logicpd-som-lv-35xx-devkit.dts
+++ b/dts/src/arm/logicpd-som-lv-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/dts/src/arm/logicpd-torpedo-35xx-devkit.dts b/dts/src/arm/logicpd-torpedo-35xx-devkit.dts
index 7675bc3..57bae2a 100644
--- a/dts/src/arm/logicpd-torpedo-35xx-devkit.dts
+++ b/dts/src/arm/logicpd-torpedo-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx Torpedo Development Kit";
- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts b/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts
index 07ac99b..b553613 100644
--- a/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts
+++ b/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts
@@ -11,22 +11,5 @@
#include "logicpd-torpedo-37xx-devkit.dts"
&lcd0 {
-
- label = "28";
-
- panel-timing {
- clock-frequency = <9000000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <3>;
- hback-porch = <2>;
- hsync-len = <42>;
- vback-porch = <3>;
- vfront-porch = <2>;
- vsync-len = <11>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ compatible = "logicpd,type28";
};
diff --git a/dts/src/arm/logicpd-torpedo-37xx-devkit.dts b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
index 18c27e8..5532db0 100644
--- a/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
+++ b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts
@@ -50,6 +50,20 @@
};
};
+&uart2 {
+ /delete-property/dma-names;
+ bluetooth {
+ compatible = "ti,wl1283-st";
+ enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */
+ max-speed = <3000000>;
+ };
+};
+
+/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
+&mt9p031_out {
+ pixel-clock-frequency = <90000000>;
+};
+
&omap3_pmx_core {
mmc3_pins: pinmux_mm3_pins {
pinctrl-single,pins = <
diff --git a/dts/src/arm/logicpd-torpedo-baseboard.dtsi b/dts/src/arm/logicpd-torpedo-baseboard.dtsi
index 449cc76..f7b82ce 100644
--- a/dts/src/arm/logicpd-torpedo-baseboard.dtsi
+++ b/dts/src/arm/logicpd-torpedo-baseboard.dtsi
@@ -101,6 +101,12 @@
};
};
+&hdqw1w {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdq_pins>;
+};
+
+
&vpll2 {
regulator-always-on;
};
@@ -108,6 +114,7 @@
&dss {
status = "ok";
vdds_dsi-supply = <&vpll2>;
+ vdda_video-supply = <&vpll2>;
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins1>;
port {
@@ -125,7 +132,6 @@
lcd0: display {
/* This isn't the exact LCD, but the timings meet spec */
- /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
compatible = "newhaven,nhd-4.3-480272ef-atxl";
label = "15";
pinctrl-names = "default";
@@ -168,6 +174,12 @@
>;
};
+ hdq_pins: hdq_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
+ >;
+ };
+
pwm_pins: pinmux_pwm_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */
diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi
index 506b118..3a52285 100644
--- a/dts/src/arm/logicpd-torpedo-som.dtsi
+++ b/dts/src/arm/logicpd-torpedo-som.dtsi
@@ -35,6 +35,11 @@
};
};
+/* The Torpedo doesn't route the USB host pins */
+&usbhshost {
+ status = "disabled";
+};
+
&gpmc {
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
diff --git a/dts/src/arm/mmp3-dell-ariel.dts b/dts/src/arm/mmp3-dell-ariel.dts
new file mode 100644
index 0000000..c1947b5
--- /dev/null
+++ b/dts/src/arm/mmp3-dell-ariel.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D)
+ *
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+/dts-v1/;
+#include "mmp3.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Dell Ariel";
+ compatible = "dell,wyse-ariel", "marvell,mmp3";
+
+ aliases {
+ serial2 = &uart3;
+ };
+
+ chosen {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
+ bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200";
+ };
+
+ memory@0 {
+ linux,usable-memory = <0x0 0x7f600000>;
+ available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>;
+ reg = <0x0 0x80000000>;
+ device_type = "memory";
+ };
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb_otg0 {
+ status = "okay";
+};
+
+&usb_otg_phy0 {
+ status = "okay";
+};
+
+&mmc3 {
+ status = "okay";
+ max-frequency = <50000000>;
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+};
+
+&twsi1 {
+ status = "okay";
+
+ rtc@68 {
+ compatible = "dallas,ds1338";
+ reg = <0x68>;
+ status = "okay";
+ };
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&twsi4 {
+ status = "okay";
+};
+
+&ssp3 {
+ status = "okay";
+ cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+
+ firmware-flash@0 {
+ compatible = "st,m25p80", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ m25p,fast-read;
+ };
+};
+
+&ssp4 {
+ cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/dts/src/arm/mmp3.dtsi b/dts/src/arm/mmp3.dtsi
new file mode 100644
index 0000000..d9762de
--- /dev/null
+++ b/dts/src/arm/mmp3.dtsi
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,mmp3-smp";
+
+ cpu@0 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4200000 0x00200000>;
+ ranges;
+
+ interrupt-controller@d4282000 {
+ compatible = "marvell,mmp3-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xd4282000 0x1000>,
+ <0xd4284000 0x100>;
+ mrvl,intc-nr-irqs = <64>;
+ };
+
+ pmic_mux: interrupt-controller@d4282150 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x150 0x4>, <0x168 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <4>;
+ };
+
+ rtc_mux: interrupt-controller@d4282154 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x154 0x4>, <0x16c 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ hsi3_mux: interrupt-controller@d42821bc {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1bc 0x4>, <0x1a4 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <3>;
+ };
+
+ gpu_mux: interrupt-controller@d42821c0 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c0 0x4>, <0x1a8 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <3>;
+ };
+
+ twsi_mux: interrupt-controller@d4282158 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x158 0x4>, <0x170 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <5>;
+ };
+
+ hsi2_mux: interrupt-controller@d42821c4 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c4 0x4>, <0x1ac 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ dxo_mux: interrupt-controller@d42821c8 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c8 0x4>, <0x1b0 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ misc1_mux: interrupt-controller@d428215c {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x15c 0x4>, <0x174 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <31>;
+ };
+
+ ci_mux: interrupt-controller@d42821cc {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1cc 0x4>, <0x1b4 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ ssp_mux: interrupt-controller@d4282160 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x160 0x4>, <0x178 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ hsi1_mux: interrupt-controller@d4282184 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x184 0x4>, <0x17c 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <4>;
+ };
+
+ misc2_mux: interrupt-controller@d4282188 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x188 0x4>, <0x180 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <20>;
+ };
+
+ hsi0_mux: interrupt-controller@d42821d0 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1d0 0x4>, <0x1b8 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <5>;
+ };
+
+ usb_otg_phy0: usb-otg-phy@d4207000 {
+ compatible = "marvell,mmp3-usb-phy";
+ reg = <0xd4207000 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb_otg0: usb-otg@d4208000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xd4208000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USB>;
+ clock-names = "USBCLK";
+ phys = <&usb_otg_phy0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ mmc1: mmc@d4280000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280000 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH0>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@d4280800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280800 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH1>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@d4281000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4281000 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH2>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc4: mmc@d4281800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4281800 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH3>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ camera0: camera@d420a000 {
+ compatible = "marvell,mmp2-ccic";
+ reg = <0xd420a000 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_CCIC0>;
+ clock-names = "axi";
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ status = "disabled";
+ };
+
+ camera1: camera@d420a800 {
+ compatible = "marvell,mmp2-ccic";
+ reg = <0xd420a800 0x800>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_CCIC1>;
+ clock-names = "axi";
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ status = "disabled";
+ };
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4000000 0x00200000>;
+ ranges;
+
+ timer: timer@d4014000 {
+ compatible = "mrvl,mmp-timer";
+ reg = <0xd4014000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_TIMER>;
+ };
+
+ uart1: uart@d4030000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0xd4030000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART0>;
+ resets = <&soc_clocks MMP2_CLK_UART0>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: uart@d4017000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0xd4017000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART1>;
+ resets = <&soc_clocks MMP2_CLK_UART1>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: uart@d4018000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0xd4018000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART2>;
+ resets = <&soc_clocks MMP2_CLK_UART2>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: uart@d4016000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0xd4016000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART3>;
+ resets = <&soc_clocks MMP2_CLK_UART3>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ gpio: gpio@d4019000 {
+ compatible = "marvell,mmp2-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4019000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ clocks = <&soc_clocks MMP2_CLK_GPIO>;
+ resets = <&soc_clocks MMP2_CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ gcb0: gpio@d4019000 {
+ reg = <0xd4019000 0x4>;
+ };
+
+ gcb1: gpio@d4019004 {
+ reg = <0xd4019004 0x4>;
+ };
+
+ gcb2: gpio@d4019008 {
+ reg = <0xd4019008 0x4>;
+ };
+
+ gcb3: gpio@d4019100 {
+ reg = <0xd4019100 0x4>;
+ };
+
+ gcb4: gpio@d4019104 {
+ reg = <0xd4019104 0x4>;
+ };
+
+ gcb5: gpio@d4019108 {
+ reg = <0xd4019108 0x4>;
+ };
+ };
+
+ twsi1: i2c@d4011000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4011000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+ resets = <&soc_clocks MMP2_CLK_TWSI0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi2: i2c@d4031000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4031000 0x1000>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <0>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+ resets = <&soc_clocks MMP2_CLK_TWSI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi3: i2c@d4032000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4032000 0x1000>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <1>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI2>;
+ resets = <&soc_clocks MMP2_CLK_TWSI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi4: i2c@d4033000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4033000 0x1000>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <2>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI3>;
+ resets = <&soc_clocks MMP2_CLK_TWSI3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+
+ twsi5: i2c@d4033800 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4033800 0x1000>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <3>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI4>;
+ resets = <&soc_clocks MMP2_CLK_TWSI4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi6: i2c@d4034000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4034000 0x1000>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <4>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI5>;
+ resets = <&soc_clocks MMP2_CLK_TWSI5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rtc: rtc@d4010000 {
+ compatible = "mrvl,mmp-rtc";
+ reg = <0xd4010000 0x1000>;
+ interrupts = <1 0>;
+ interrupt-names = "rtc 1Hz", "rtc alarm";
+ interrupt-parent = <&rtc_mux>;
+ clocks = <&soc_clocks MMP2_CLK_RTC>;
+ resets = <&soc_clocks MMP2_CLK_RTC>;
+ status = "disabled";
+ };
+
+ ssp1: spi@d4035000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4035000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp2: spi@d4036000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4036000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP1>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp3: spi@d4037000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4037000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP2>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp4: spi@d4039000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4039000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP3>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ l2: l2-cache-controller@d0020000 {
+ compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+ reg = <0xd0020000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc_clocks: clocks@d4050000 {
+ compatible = "marvell,mmp2-clock";
+ reg = <0xd4050000 0x1000>,
+ <0xd4282800 0x400>,
+ <0xd4015000 0x1000>;
+ reg-names = "mpmu", "apmu", "apbc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ snoop-control-unit@e0000000 {
+ compatible = "arm,arm11mp-scu";
+ reg = <0xe0000000 0x100>;
+ };
+
+ gic: interrupt-controller@e0001000 {
+ compatible = "arm,arm11mp-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xe0001000 0x1000>,
+ <0xe0000100 0x100>;
+ };
+
+ local-timer@e0000600 {
+ compatible = "arm,arm11mp-twd-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ reg = <0xe0000600 0x20>;
+ };
+
+ watchdog@e0000620 {
+ compatible = "arm,arm11mp-twd-wdt";
+ reg = <0xe0000620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ };
+ };
+};
diff --git a/dts/src/arm/motorola-cpcap-mapphone.dtsi b/dts/src/arm/motorola-cpcap-mapphone.dtsi
index d1eae47..936ad01 100644
--- a/dts/src/arm/motorola-cpcap-mapphone.dtsi
+++ b/dts/src/arm/motorola-cpcap-mapphone.dtsi
@@ -43,11 +43,13 @@
compatible = "motorola,mapphone-cpcap-charger";
interrupts-extended = <
&cpcap 13 0 &cpcap 12 0 &cpcap 29 0 &cpcap 28 0
- &cpcap 22 0 &cpcap 20 0 &cpcap 19 0 &cpcap 54 0
+ &cpcap 22 0 &cpcap 21 0 &cpcap 20 0 &cpcap 19 0
+ &cpcap 54 0
>;
interrupt-names =
"chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn",
- "rvrs_mode", "chrgcurr1", "vbusvld", "battdetb";
+ "rvrs_mode", "chrgcurr2", "chrgcurr1", "vbusvld",
+ "battdetb";
mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW
&gpio3 23 GPIO_ACTIVE_LOW>;
io-channels = <&cpcap_adc 0 &cpcap_adc 1
@@ -160,12 +162,12 @@
regulator-enable-ramp-delay = <1000>;
};
- /* Used by DSS */
+ /* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */
vcsi: VCSI {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <1000>;
- regulator-boot-on;
+ regulator-always-on;
};
vdac: VDAC {
diff --git a/dts/src/arm/motorola-mapphone-common.dtsi b/dts/src/arm/motorola-mapphone-common.dtsi
new file mode 100644
index 0000000..da6b107
--- /dev/null
+++ b/dts/src/arm/motorola-mapphone-common.dtsi
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "omap443x.dtsi"
+#include "motorola-cpcap-mapphone.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &hdmi0;
+ };
+
+ /*
+ * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
+ * then 1023 - 1024 seems to contain mbm.
+ */
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x3fd00000>; /* 1021 MB */
+ };
+
+ /* Poweroff GPIO probably connected to CPCAP */
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&poweroff_gpio>;
+ pinctrl-names = "default";
+ gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ pinctrl-0 = <&hdmi_hpd_gpio>;
+ pinctrl-names = "default";
+ label = "hdmi";
+ type = "d";
+
+ hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+ };
+
+ /*
+ * HDMI 5V regulator probably sourced from battery. Let's keep
+ * keep this as always enabled for HDMI to work until we've
+ * figured what the encoder chip is.
+ */
+ hdmi_regulator: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* FS USB Host PHY on port 1 for mdm6600 */
+ fsusb1_phy: usb-phy@1 {
+ compatible = "motorola,mapphone-mdm6600";
+ pinctrl-0 = <&usb_mdm6600_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
+ /* mode: gpio_148 gpio_149 */
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ /* cmd: gpio_103 gpio_104 gpio_142 */
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ /* status: gpio_52 gpio_53 gpio_55 */
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB host TLL nop-phy on port 2 for w3glte */
+ hsusb2_phy: usb-phy@2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ /* LCD regulator from sw5 source */
+ lcd_regulator: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd";
+ regulator-min-microvolt = <5050000>;
+ regulator-max-microvolt = <5050000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
+ enable-active-high;
+ vin-supply = <&sw5>;
+ };
+
+ /* This is probably coming straight from the battery.. */
+ wl12xx_vmmc: regulator-wl12xx {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ volume_down {
+ label = "Volume Down";
+ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
+ linux,code = <KEY_VOLUMEDOWN>;
+ linux,can-disable;
+ /* Value above 7.95ms for no GPIO hardware debounce */
+ debounce-interval = <10>;
+ };
+
+ slider {
+ label = "Keypad Slide";
+ gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_KEYPAD_SLIDE>;
+ linux,can-disable;
+ /* Value above 7.95ms for no GPIO hardware debounce */
+ debounce-interval = <10>;
+ };
+ };
+
+ soundcard {
+ compatible = "audio-graph-card";
+ label = "Droid 4 Audio";
+
+ simple-graph-card,widgets =
+ "Speaker", "Earpiece",
+ "Speaker", "Loudspeaker",
+ "Headphone", "Headphone Jack",
+ "Microphone", "Internal Mic";
+
+ simple-graph-card,routing =
+ "Earpiece", "EP",
+ "Loudspeaker", "SPKR",
+ "Headphone Jack", "HSL",
+ "Headphone Jack", "HSR",
+ "MICR", "Internal Mic";
+
+ dais = <&mcbsp2_port>, <&mcbsp3_port>;
+ };
+
+ pwm8: dmtimer-pwm-8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm-9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <10000000>;
+ };
+};
+
+&dss {
+ status = "okay";
+};
+
+&dsi1 {
+ status = "okay";
+ vdd-supply = <&vcsi>;
+
+ port {
+ dsi1_out_ep: endpoint {
+ remote-endpoint = <&lcd0_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd0: display {
+ compatible = "panel-dsi-cm";
+ label = "lcd0";
+ vddi-supply = <&lcd_regulator>;
+ reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
+
+ width-mm = <50>;
+ height-mm = <89>;
+
+ panel-timing {
+ clock-frequency = <0>; /* Calculated by dsi */
+
+ hback-porch = <2>;
+ hactive = <540>;
+ hfront-porch = <0>;
+ hsync-len = <2>;
+
+ vback-porch = <1>;
+ vactive = <960>;
+ vfront-porch = <0>;
+ vsync-len = <1>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd0_in: endpoint {
+ remote-endpoint = <&dsi1_out_ep>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "okay";
+ pinctrl-0 = <&dss_hdmi_pins>;
+ pinctrl-names = "default";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ lanes = <1 0 3 2 5 4 7 6>;
+ };
+ };
+};
+
+&i2c1 {
+ tmp105@48 {
+ compatible = "ti,tmp105";
+ reg = <0x48>;
+ pinctrl-0 = <&tmp105_irq>;
+ pinctrl-names = "default";
+ /* kpd_row0.gpio_178 */
+ interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
+ &omap4_pmx_core 0x14e>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <
+
+ /* Row 1 */
+ MATRIX_KEY(0, 2, KEY_1)
+ MATRIX_KEY(0, 6, KEY_2)
+ MATRIX_KEY(2, 3, KEY_3)
+ MATRIX_KEY(0, 7, KEY_4)
+ MATRIX_KEY(0, 4, KEY_5)
+ MATRIX_KEY(5, 5, KEY_6)
+ MATRIX_KEY(0, 1, KEY_7)
+ MATRIX_KEY(0, 5, KEY_8)
+ MATRIX_KEY(0, 0, KEY_9)
+ MATRIX_KEY(1, 6, KEY_0)
+
+ /* Row 2 */
+ MATRIX_KEY(3, 4, KEY_APOSTROPHE)
+ MATRIX_KEY(7, 6, KEY_Q)
+ MATRIX_KEY(7, 7, KEY_W)
+ MATRIX_KEY(7, 2, KEY_E)
+ MATRIX_KEY(1, 0, KEY_R)
+ MATRIX_KEY(4, 4, KEY_T)
+ MATRIX_KEY(1, 2, KEY_Y)
+ MATRIX_KEY(6, 7, KEY_U)
+ MATRIX_KEY(2, 2, KEY_I)
+ MATRIX_KEY(5, 6, KEY_O)
+ MATRIX_KEY(3, 7, KEY_P)
+ MATRIX_KEY(6, 5, KEY_BACKSPACE)
+
+ /* Row 3 */
+ MATRIX_KEY(5, 4, KEY_TAB)
+ MATRIX_KEY(5, 7, KEY_A)
+ MATRIX_KEY(2, 7, KEY_S)
+ MATRIX_KEY(7, 0, KEY_D)
+ MATRIX_KEY(2, 6, KEY_F)
+ MATRIX_KEY(6, 2, KEY_G)
+ MATRIX_KEY(6, 6, KEY_H)
+ MATRIX_KEY(1, 4, KEY_J)
+ MATRIX_KEY(3, 1, KEY_K)
+ MATRIX_KEY(2, 1, KEY_L)
+ MATRIX_KEY(4, 6, KEY_ENTER)
+
+ /* Row 4 */
+ MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */
+ MATRIX_KEY(6, 1, KEY_Z)
+ MATRIX_KEY(7, 4, KEY_X)
+ MATRIX_KEY(5, 1, KEY_C)
+ MATRIX_KEY(1, 7, KEY_V)
+ MATRIX_KEY(2, 4, KEY_B)
+ MATRIX_KEY(4, 1, KEY_N)
+ MATRIX_KEY(1, 1, KEY_M)
+ MATRIX_KEY(3, 5, KEY_COMMA)
+ MATRIX_KEY(5, 2, KEY_DOT)
+ MATRIX_KEY(6, 3, KEY_UP)
+ MATRIX_KEY(7, 3, KEY_OK)
+
+ /* Row 5 */
+ MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */
+ MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */
+ MATRIX_KEY(6, 0, KEY_MINUS)
+ MATRIX_KEY(4, 7, KEY_EQUAL)
+ MATRIX_KEY(1, 5, KEY_SPACE)
+ MATRIX_KEY(3, 2, KEY_SLASH)
+ MATRIX_KEY(4, 3, KEY_LEFT)
+ MATRIX_KEY(5, 3, KEY_DOWN)
+ MATRIX_KEY(3, 3, KEY_RIGHT)
+
+ /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
+ MATRIX_KEY(5, 0, KEY_VOLUMEUP)
+ >;
+};
+
+&mmc1 {
+ vmmc-supply = <&vwlan2>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
+};
+
+&mmc2 {
+ vmmc-supply = <&vsdio>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ vmmc-supply = <&wl12xx_vmmc>;
+ /* uart2_tx.sdmmc3_dat1 pad as wakeirq */
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xde>;
+ interrupt-names = "irq", "wakeup";
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1285", "ti,wl1283";
+ reg = <2>;
+ /* gpio_100 with gpmc_wait2 pad as wakeirq */
+ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap4_pmx_core 0x4e>;
+ interrupt-names = "irq", "wakeup";
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&i2c1 {
+ led-controller@38 {
+ compatible = "ti,lm3532";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x38>;
+
+ enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+
+ ramp-up-us = <1024>;
+ ramp-down-us = <8193>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <2>;
+ ti,led-mode = <0>;
+ label = ":backlight";
+ linux,default-trigger = "backlight";
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ ti,led-mode = <0>;
+ label = ":kbd_backlight";
+ };
+ };
+};
+
+&i2c2 {
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
+
+ /* gpio_183 with sys_nirq2 pad as wakeup */
+ interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>,
+ <&omap4_pmx_core 0x160>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
+
+ isl29030@44 {
+ compatible = "isil,isl29030";
+ reg = <0x44>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&als_proximity_pins>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
+ };
+};
+
+&omap4_pmx_core {
+
+ /* hdmi_hpd.gpio_63 */
+ hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
+ >;
+ };
+
+ /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
+ >;
+ };
+
+ /* gpmc_ncs0.gpio_50 */
+ poweroff_gpio: pinmux_poweroff_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ /* kpd_row0.gpio_178 */
+ tmp105_irq: pinmux_tmp105_irq {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
+ /* gpio_60 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ touchscreen_pins: pinmux_touchscreen_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ als_proximity_pins: pinmux_als_proximity_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
+ pinctrl-single,pins = <
+ /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+ /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+ /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+ /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+ /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+ /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+ /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ usb_ulpi_pins: pinmux_usb_ulpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ /* usb0_otg_dp and usb0_otg_dm */
+ usb_utmi_pins: pinmux_usb_utmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ /*
+ * Note that the v3.0.8 stock userspace dynamically remuxes uart1
+ * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
+ * when not used. If needed, we can add rts pin remux later based
+ * on power measurements.
+ */
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
+ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
+ OMAP4_IOPAD(0x13e, MUX_MODE1)
+
+ /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
+ OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
+
+ /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
+ OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
+ >;
+ };
+
+ /* uart3_tx_irtx and uart3_rx_irrx */
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, MUX_MODE2)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */
+ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */
+ OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */
+ OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */
+ OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */
+ OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */
+ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */
+ >;
+ };
+
+ mcbsp3_pins: pinmux_mcbsp3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */
+ OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */
+ OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */
+ OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */
+ >;
+ };
+
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
+ /* gpio_wk0 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+};
+
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+ assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+&timer9 {
+ assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+/*
+ * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
+ * uart1 wakeirq.
+ */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xfc>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x17c>;
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+
+ bluetooth {
+ compatible = "ti,wl1285-st";
+ enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */
+ max-speed = <3686400>;
+ };
+};
+
+&usbhsohci {
+ phys = <&fsusb1_phy>;
+ phy-names = "usb";
+};
+
+&usbhsehci {
+ phys = <&hsusb2_phy>;
+};
+
+&usbhshost {
+ port1-mode = "ohci-phy-4pin-dpdm";
+ port2-mode = "ehci-tll";
+};
+
+/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+
+ /*
+ * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4.
+ * VBUS Regulator Main Characteristics". Binding uses 2 mA units.
+ */
+ power = <150>;
+};
+
+&i2c4 {
+ ak8975: magnetometer@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+
+ vdd-supply = <&vhvio>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
+
+ rotation-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+
+ };
+
+ lis3dh: accelerometer@18 {
+ compatible = "st,lis3dh-accel";
+ reg = <0x18>;
+
+ vdd-supply = <&vhvio>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */
+
+ rotation-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+ };
+};
+
+&mcbsp2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+
+ mcbsp2_port: port {
+ cpu_dai2: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&cpcap_audio_codec0>;
+ frame-master = <&cpcap_audio_codec0>;
+ bitclock-master = <&cpcap_audio_codec0>;
+ };
+ };
+};
+
+&mcbsp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp3_pins>;
+ status = "okay";
+
+ mcbsp3_port: port {
+ cpu_dai3: endpoint {
+ dai-format = "dsp_a";
+ frame-master = <&cpcap_audio_codec1>;
+ bitclock-master = <&cpcap_audio_codec1>;
+ remote-endpoint = <&cpcap_audio_codec1>;
+ };
+ };
+};
+
+&cpcap_audio_codec0 {
+ remote-endpoint = <&cpu_dai2>;
+};
+
+&cpcap_audio_codec1 {
+ remote-endpoint = <&cpu_dai3>;
+};
diff --git a/dts/src/arm/mt6323.dtsi b/dts/src/arm/mt6323.dtsi
index ba39740..7fda40a 100644
--- a/dts/src/arm/mt6323.dtsi
+++ b/dts/src/arm/mt6323.dtsi
@@ -238,5 +238,32 @@
regulator-enable-ramp-delay = <216>;
};
};
+
+ mt6323keys: mt6323keys {
+ compatible = "mediatek,mt6323-keys";
+ mediatek,long-press-mode = <1>;
+ power-off-time-sec = <0>;
+
+ power {
+ linux,keycodes = <116>;
+ wakeup-source;
+ };
+
+ home {
+ linux,keycodes = <114>;
+ };
+ };
+
+ codec: mt6397codec {
+ compatible = "mediatek,mt6397-codec";
+ };
+
+ power-controller {
+ compatible = "mediatek,mt6323-pwrc";
+ };
+
+ rtc {
+ compatible = "mediatek,mt6323-rtc";
+ };
};
};
diff --git a/dts/src/arm/omap3-beagle-xm.dts b/dts/src/arm/omap3-beagle-xm.dts
index 1aa99fc..125ed93 100644
--- a/dts/src/arm/omap3-beagle-xm.dts
+++ b/dts/src/arm/omap3-beagle-xm.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard xM";
- compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/dts/src/arm/omap3-beagle.dts b/dts/src/arm/omap3-beagle.dts
index e3df3c1..4ed3f93 100644
--- a/dts/src/arm/omap3-beagle.dts
+++ b/dts/src/arm/omap3-beagle.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard";
- compatible = "ti,omap3-beagle", "ti,omap3";
+ compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
cpus {
cpu@0 {
diff --git a/dts/src/arm/omap3-cm-t3530.dts b/dts/src/arm/omap3-cm-t3530.dts
index 76e52c7..32dbaea 100644
--- a/dts/src/arm/omap3-cm-t3530.dts
+++ b/dts/src/arm/omap3-cm-t3530.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3530";
- compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
/* Regulator to trigger the reset signal of the Wifi module */
mmc2_sdio_reset: regulator-mmc2-sdio-reset {
diff --git a/dts/src/arm/omap3-cm-t3730.dts b/dts/src/arm/omap3-cm-t3730.dts
index 6e944df..683819b 100644
--- a/dts/src/arm/omap3-cm-t3730.dts
+++ b/dts/src/arm/omap3-cm-t3730.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3730";
- compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
diff --git a/dts/src/arm/omap3-devkit8000-lcd43.dts b/dts/src/arm/omap3-devkit8000-lcd43.dts
index a80fc60..afed850 100644
--- a/dts/src/arm/omap3-devkit8000-lcd43.dts
+++ b/dts/src/arm/omap3-devkit8000-lcd43.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/dts/src/arm/omap3-devkit8000-lcd70.dts b/dts/src/arm/omap3-devkit8000-lcd70.dts
index 0753776..07c51a1 100644
--- a/dts/src/arm/omap3-devkit8000-lcd70.dts
+++ b/dts/src/arm/omap3-devkit8000-lcd70.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/dts/src/arm/omap3-devkit8000.dts b/dts/src/arm/omap3-devkit8000.dts
index faafc48..162d072 100644
--- a/dts/src/arm/omap3-devkit8000.dts
+++ b/dts/src/arm/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
#include "omap3-devkit8000-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
aliases {
display1 = &dvi0;
diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi
index b6ef1a7..409a758 100644
--- a/dts/src/arm/omap3-gta04.dtsi
+++ b/dts/src/arm/omap3-gta04.dtsi
@@ -11,7 +11,7 @@
/ {
model = "OMAP3 GTA04";
- compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/dts/src/arm/omap3-ha-lcd.dts b/dts/src/arm/omap3-ha-lcd.dts
index badb9b3..c9ecbc4 100644
--- a/dts/src/arm/omap3-ha-lcd.dts
+++ b/dts/src/arm/omap3-ha-lcd.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/dts/src/arm/omap3-ha.dts b/dts/src/arm/omap3-ha.dts
index a536525..35c4e15 100644
--- a/dts/src/arm/omap3-ha.dts
+++ b/dts/src/arm/omap3-ha.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/dts/src/arm/omap3-igep0020-rev-f.dts b/dts/src/arm/omap3-igep0020-rev-f.dts
index 03dcd05..5672325 100644
--- a/dts/src/arm/omap3-igep0020-rev-f.dts
+++ b/dts/src/arm/omap3-igep0020-rev-f.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
@@ -49,3 +49,11 @@
interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */
};
};
+
+&uart2 {
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */
+ max-speed = <300000>;
+ };
+};
diff --git a/dts/src/arm/omap3-igep0020.dts b/dts/src/arm/omap3-igep0020.dts
index 6d0519e..e341535 100644
--- a/dts/src/arm/omap3-igep0020.dts
+++ b/dts/src/arm/omap3-igep0020.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/dts/src/arm/omap3-igep0030-rev-g.dts b/dts/src/arm/omap3-igep0030-rev-g.dts
index 060acd1..df6ba12 100644
--- a/dts/src/arm/omap3-igep0030-rev-g.dts
+++ b/dts/src/arm/omap3-igep0030-rev-g.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
@@ -71,3 +71,11 @@
interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */
};
};
+
+&uart2 {
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */
+ max-speed = <300000>;
+ };
+};
diff --git a/dts/src/arm/omap3-igep0030.dts b/dts/src/arm/omap3-igep0030.dts
index 25170bd..32f3103 100644
--- a/dts/src/arm/omap3-igep0030.dts
+++ b/dts/src/arm/omap3-igep0030.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/dts/src/arm/omap3-ldp.dts b/dts/src/arm/omap3-ldp.dts
index 9a5fde2..ec9ba04 100644
--- a/dts/src/arm/omap3-ldp.dts
+++ b/dts/src/arm/omap3-ldp.dts
@@ -10,7 +10,7 @@
/ {
model = "TI OMAP3430 LDP (Zoom1 Labrador)";
- compatible = "ti,omap3-ldp", "ti,omap3";
+ compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/dts/src/arm/omap3-lilly-a83x.dtsi b/dts/src/arm/omap3-lilly-a83x.dtsi
index c22833d..73d4778 100644
--- a/dts/src/arm/omap3-lilly-a83x.dtsi
+++ b/dts/src/arm/omap3-lilly-a83x.dtsi
@@ -7,7 +7,7 @@
/ {
model = "INCOstartec LILLY-A83X module (DM3730)";
- compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
chosen {
bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
diff --git a/dts/src/arm/omap3-lilly-dbb056.dts b/dts/src/arm/omap3-lilly-dbb056.dts
index fec3354..ecb4ef7 100644
--- a/dts/src/arm/omap3-lilly-dbb056.dts
+++ b/dts/src/arm/omap3-lilly-dbb056.dts
@@ -8,7 +8,7 @@
/ {
model = "INCOstartec LILLY-DBB056 (DM3730)";
- compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&twl {
diff --git a/dts/src/arm/omap3-n9.dts b/dts/src/arm/omap3-n9.dts
index 74c0ff2..2495a69 100644
--- a/dts/src/arm/omap3-n9.dts
+++ b/dts/src/arm/omap3-n9.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N9";
- compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&i2c2 {
diff --git a/dts/src/arm/omap3-n900.dts b/dts/src/arm/omap3-n900.dts
index 84a5ade..a638e05 100644
--- a/dts/src/arm/omap3-n900.dts
+++ b/dts/src/arm/omap3-n900.dts
@@ -155,6 +155,12 @@
pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
};
+ rom_rng: rng {
+ compatible = "nokia,n900-rom-rng";
+ clocks = <&rng_ick>;
+ clock-names = "ick";
+ };
+
/* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
vctcxo: vctcxo {
compatible = "fixed-clock";
@@ -1013,6 +1019,11 @@
};
};
+/* RNG not directly accessible on n900, see omap3-rom-rng instead */
+&rng_target {
+ status = "disabled";
+};
+
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
diff --git a/dts/src/arm/omap3-n950-n9.dtsi b/dts/src/arm/omap3-n950-n9.dtsi
index 6681d45..a075b63 100644
--- a/dts/src/arm/omap3-n950-n9.dtsi
+++ b/dts/src/arm/omap3-n950-n9.dtsi
@@ -11,13 +11,6 @@
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- 1000000 1375000
- >;
};
};
diff --git a/dts/src/arm/omap3-n950.dts b/dts/src/arm/omap3-n950.dts
index 9886bf8..31d47a1 100644
--- a/dts/src/arm/omap3-n950.dts
+++ b/dts/src/arm/omap3-n950.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N950";
- compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3";
keys {
compatible = "gpio-keys";
diff --git a/dts/src/arm/omap3-overo-storm-alto35.dts b/dts/src/arm/omap3-overo-storm-alto35.dts
index 1833857..7f04dfa 100644
--- a/dts/src/arm/omap3-overo-storm-alto35.dts
+++ b/dts/src/arm/omap3-overo-storm-alto35.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/dts/src/arm/omap3-overo-storm-chestnut43.dts b/dts/src/arm/omap3-overo-storm-chestnut43.dts
index f204c8a..bc5a04e 100644
--- a/dts/src/arm/omap3-overo-storm-chestnut43.dts
+++ b/dts/src/arm/omap3-overo-storm-chestnut43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-overo-storm-gallop43.dts b/dts/src/arm/omap3-overo-storm-gallop43.dts
index c633f7c..065c31c 100644
--- a/dts/src/arm/omap3-overo-storm-gallop43.dts
+++ b/dts/src/arm/omap3-overo-storm-gallop43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-overo-storm-palo35.dts b/dts/src/arm/omap3-overo-storm-palo35.dts
index fb88ebc..e38c1c5 100644
--- a/dts/src/arm/omap3-overo-storm-palo35.dts
+++ b/dts/src/arm/omap3-overo-storm-palo35.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35";
- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-overo-storm-palo43.dts b/dts/src/arm/omap3-overo-storm-palo43.dts
index 76cca00..e6dc231 100644
--- a/dts/src/arm/omap3-overo-storm-palo43.dts
+++ b/dts/src/arm/omap3-overo-storm-palo43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-overo-storm-summit.dts b/dts/src/arm/omap3-overo-storm-summit.dts
index cc081a9..587c08c 100644
--- a/dts/src/arm/omap3-overo-storm-summit.dts
+++ b/dts/src/arm/omap3-overo-storm-summit.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-overo-storm-tobi.dts b/dts/src/arm/omap3-overo-storm-tobi.dts
index 1de41c0..f57de60 100644
--- a/dts/src/arm/omap3-overo-storm-tobi.dts
+++ b/dts/src/arm/omap3-overo-storm-tobi.dts
@@ -14,6 +14,6 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/dts/src/arm/omap3-overo-storm-tobiduo.dts b/dts/src/arm/omap3-overo-storm-tobiduo.dts
index 9ed1311..281af6c 100644
--- a/dts/src/arm/omap3-overo-storm-tobiduo.dts
+++ b/dts/src/arm/omap3-overo-storm-tobiduo.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo";
- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/dts/src/arm/omap3-pandora-1ghz.dts b/dts/src/arm/omap3-pandora-1ghz.dts
index 81b957f..ea50995 100644
--- a/dts/src/arm/omap3-pandora-1ghz.dts
+++ b/dts/src/arm/omap3-pandora-1ghz.dts
@@ -16,7 +16,7 @@
/ {
model = "Pandora Handheld Console 1GHz";
- compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3";
+ compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/dts/src/arm/omap3-pandora-common.dtsi b/dts/src/arm/omap3-pandora-common.dtsi
index ec58917..150d5be 100644
--- a/dts/src/arm/omap3-pandora-common.dtsi
+++ b/dts/src/arm/omap3-pandora-common.dtsi
@@ -226,6 +226,17 @@
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */
};
+ /* wl1251 wifi+bt module */
+ wlan_en: fixed-regulator-wg7210_en {
+ compatible = "regulator-fixed";
+ regulator-name = "vwlan";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <50000>;
+ enable-active-high;
+ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
/* wg7210 (wifi+bt module) 32k clock buffer */
wg7210_32k: fixed-regulator-wg7210_32k {
compatible = "regulator-fixed";
@@ -522,9 +533,30 @@
/*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */
};
-/* mmc3 is probed using pdata-quirks to pass wl1251 card data */
&mmc3 {
- status = "disabled";
+ vmmc-supply = <&wlan_en>;
+
+ bus-width = <4>;
+ non-removable;
+ ti,non-removable;
+ cap-power-off-card;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wlan: wifi@1 {
+ compatible = "ti,wl1251";
+
+ reg = <1>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */
+
+ ti,wl1251-has-eeprom;
+ };
};
/* bluetooth*/
diff --git a/dts/src/arm/omap3-sbc-t3530.dts b/dts/src/arm/omap3-sbc-t3530.dts
index ae96002..24bf3fd 100644
--- a/dts/src/arm/omap3-sbc-t3530.dts
+++ b/dts/src/arm/omap3-sbc-t3530.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3530 with CM-T3530";
- compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/dts/src/arm/omap3-sbc-t3730.dts b/dts/src/arm/omap3-sbc-t3730.dts
index 7de6df1..eb3893b 100644
--- a/dts/src/arm/omap3-sbc-t3730.dts
+++ b/dts/src/arm/omap3-sbc-t3730.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3730 with CM-T3730";
- compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/dts/src/arm/omap3-sniper.dts b/dts/src/arm/omap3-sniper.dts
index 40a8733..b6879cd 100644
--- a/dts/src/arm/omap3-sniper.dts
+++ b/dts/src/arm/omap3-sniper.dts
@@ -9,7 +9,7 @@
/ {
model = "LG Optimus Black";
- compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3";
+ compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/dts/src/arm/omap3-tao3530.dtsi b/dts/src/arm/omap3-tao3530.dtsi
index a7a04d7..f24e232 100644
--- a/dts/src/arm/omap3-tao3530.dtsi
+++ b/dts/src/arm/omap3-tao3530.dtsi
@@ -222,7 +222,7 @@
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vqmmc-supply = <&vsim>;
- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
bus-width = <8>;
};
diff --git a/dts/src/arm/omap3-thunder.dts b/dts/src/arm/omap3-thunder.dts
index 6276e70..64221e3 100644
--- a/dts/src/arm/omap3-thunder.dts
+++ b/dts/src/arm/omap3-thunder.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
- compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/dts/src/arm/omap3-zoom3.dts b/dts/src/arm/omap3-zoom3.dts
index db3a2fe..d240e39 100644
--- a/dts/src/arm/omap3-zoom3.dts
+++ b/dts/src/arm/omap3-zoom3.dts
@@ -9,7 +9,7 @@
/ {
model = "TI Zoom3";
- compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/dts/src/arm/omap3.dtsi b/dts/src/arm/omap3.dtsi
index 4043ecb..5698a3e 100644
--- a/dts/src/arm/omap3.dtsi
+++ b/dts/src/arm/omap3.dtsi
@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -502,6 +503,30 @@
status = "disabled";
};
+ /* Likely needs to be tagged disabled on HS devices */
+ rng_target: target-module@480a0000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480a003c 0x4>,
+ <0x480a0040 0x4>,
+ <0x480a0044 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&rng_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480a0000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap2-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <52>;
+ };
+ };
+
mcbsp2: mcbsp@49022000 {
compatible = "ti,omap3-mcbsp";
reg = <0x49022000 0xff>,
diff --git a/dts/src/arm/omap3430-sdp.dts b/dts/src/arm/omap3430-sdp.dts
index 0abd611..7bfde8a 100644
--- a/dts/src/arm/omap3430-sdp.dts
+++ b/dts/src/arm/omap3430-sdp.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3430 SDP";
- compatible = "ti,omap3430-sdp", "ti,omap3";
+ compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/dts/src/arm/omap34xx-omap36xx-clocks.dtsi b/dts/src/arm/omap34xx-omap36xx-clocks.dtsi
index 5e9d1af..21079cd 100644
--- a/dts/src/arm/omap34xx-omap36xx-clocks.dtsi
+++ b/dts/src/arm/omap34xx-omap36xx-clocks.dtsi
@@ -260,6 +260,6 @@
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
- <&mspro_fck>;
+ <&rng_ick>, <&mspro_fck>;
};
};
diff --git a/dts/src/arm/omap34xx.dtsi b/dts/src/arm/omap34xx.dtsi
index 7b09cbe..c4dd980 100644
--- a/dts/src/arm/omap34xx.dtsi
+++ b/dts/src/arm/omap34xx.dtsi
@@ -16,19 +16,67 @@
/ {
cpus {
cpu: cpu@0 {
- /* OMAP343x/OMAP35xx variants OPP1-5 */
- operating-points = <
- /* kHz uV */
- 125000 975000
- 250000 1075000
- 500000 1200000
- 550000 1270000
- 600000 1350000
- >;
+ /* OMAP343x/OMAP35xx variants OPP1-6 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
clock-latency = <300000>; /* From legacy driver */
};
};
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp1-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 3-3 of the omap3530 Data sheet (SPRS507F).
+ * Format is: <target min max>
+ */
+ opp-microvolt = <975000 975000 975000>;
+ /*
+ * first value is silicon revision bit mask
+ * second one 720MHz Device Identification bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp2-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1075000 1075000 1075000>;
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp3-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp4-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <1275000 1275000 1275000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp5-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp6-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ /* only high-speed grade omap3530 devices */
+ opp-supported-hw = <0xffffffff 2>;
+ turbo-mode;
+ };
+ };
+
ocp@68000000 {
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
diff --git a/dts/src/arm/omap36xx-clocks.dtsi b/dts/src/arm/omap36xx-clocks.dtsi
index e66fc57..4e9cc90 100644
--- a/dts/src/arm/omap36xx-clocks.dtsi
+++ b/dts/src/arm/omap36xx-clocks.dtsi
@@ -105,3 +105,7 @@
<&mcbsp4_ick>, <&uart4_fck>;
};
};
+
+&dpll4_m4_ck {
+ ti,max-div = <31>;
+};
diff --git a/dts/src/arm/omap36xx.dtsi b/dts/src/arm/omap36xx.dtsi
index 1e552f0..c618cb2 100644
--- a/dts/src/arm/omap36xx.dtsi
+++ b/dts/src/arm/omap36xx.dtsi
@@ -19,16 +19,65 @@
};
cpus {
- /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+ /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
cpu: cpu@0 {
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- >;
- clock-latency = <300000>; /* From legacy driver */
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ vbb-supply = <&abb_mpu_iva>;
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ };
+
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp50-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 4-19 of the DM3730 Data sheet (SPRS685B)
+ * Format is: cpu0-supply: <target min max>
+ * vbb-supply: <target min max>
+ */
+ opp-microvolt = <1012500 1012500 1012500>,
+ <1012500 1012500 1012500>;
+ /*
+ * first value is silicon revision bit mask
+ * second one is "speed binned" bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp100-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000 1200000 1200000>,
+ <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp130-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1325000 1325000 1325000>,
+ <1325000 1325000 1325000>;
+ opp-supported-hw = <0xffffffff 3>;
};
+
+ opp1g-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1375000 1375000 1375000>,
+ <1375000 1375000 1375000>;
+ /* only on am/dm37x with speed-binned bit set */
+ opp-supported-hw = <0xffffffff 2>;
+ turbo-mode;
+ };
+ };
+
+ opp_supply_mpu_iva: opp_supply {
+ compatible = "ti,omap-opp-supply";
+ ti,absolute-max-voltage-uv = <1375000>;
};
ocp@68000000 {
diff --git a/dts/src/arm/omap3xxx-clocks.dtsi b/dts/src/arm/omap3xxx-clocks.dtsi
index 685c82a..0656c32 100644
--- a/dts/src/arm/omap3xxx-clocks.dtsi
+++ b/dts/src/arm/omap3xxx-clocks.dtsi
@@ -416,7 +416,7 @@
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
- ti,max-div = <32>;
+ ti,max-div = <16>;
reg = <0x0e40>;
ti,index-starts-at-one;
};
diff --git a/dts/src/arm/omap4-droid-bionic-xt875.dts b/dts/src/arm/omap4-droid-bionic-xt875.dts
new file mode 100644
index 0000000..ba5c35b
--- /dev/null
+++ b/dts/src/arm/omap4-droid-bionic-xt875.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-common.dtsi"
+
+/ {
+ model = "Motorola Droid Bionic XT875";
+ compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4";
+};
diff --git a/dts/src/arm/omap4-droid4-xt894.dts b/dts/src/arm/omap4-droid4-xt894.dts
index a40fe8d..c0d2fd9 100644
--- a/dts/src/arm/omap4-droid4-xt894.dts
+++ b/dts/src/arm/omap4-droid4-xt894.dts
@@ -1,784 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include "omap443x.dtsi"
-#include "motorola-cpcap-mapphone.dtsi"
+#include "motorola-mapphone-common.dtsi"
/ {
model = "Motorola Droid 4 XT894";
compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
-
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- display0 = &lcd0;
- display1 = &hdmi0;
- };
-
- /*
- * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
- * then 1023 - 1024 seems to contain mbm.
- */
- memory {
- device_type = "memory";
- reg = <0x80000000 0x3fd00000>; /* 1021 MB */
- };
-
- /* Poweroff GPIO probably connected to CPCAP */
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&poweroff_gpio>;
- pinctrl-names = "default";
- gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- pinctrl-0 = <&hdmi_hpd_gpio>;
- pinctrl-names = "default";
- label = "hdmi";
- type = "d";
-
- hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
- };
-
- /*
- * HDMI 5V regulator probably sourced from battery. Let's keep
- * keep this as always enabled for HDMI to work until we've
- * figured what the encoder chip is.
- */
- hdmi_regulator: regulator-hdmi {
- compatible = "regulator-fixed";
- regulator-name = "hdmi";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */
- enable-active-high;
- regulator-always-on;
- };
-
- /* FS USB Host PHY on port 1 for mdm6600 */
- fsusb1_phy: usb-phy@1 {
- compatible = "motorola,mapphone-mdm6600";
- pinctrl-0 = <&usb_mdm6600_pins>;
- pinctrl-names = "default";
- enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
- power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
- reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
- /* mode: gpio_148 gpio_149 */
- motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
- <&gpio5 21 GPIO_ACTIVE_HIGH>;
- /* cmd: gpio_103 gpio_104 gpio_142 */
- motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
- <&gpio4 8 GPIO_ACTIVE_HIGH>,
- <&gpio5 14 GPIO_ACTIVE_HIGH>;
- /* status: gpio_52 gpio_53 gpio_55 */
- motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
- <&gpio2 21 GPIO_ACTIVE_HIGH>,
- <&gpio2 23 GPIO_ACTIVE_HIGH>;
- #phy-cells = <0>;
- };
-
- /* HS USB host TLL nop-phy on port 2 for w3glte */
- hsusb2_phy: usb-phy@2 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
-
- /* LCD regulator from sw5 source */
- lcd_regulator: regulator-lcd {
- compatible = "regulator-fixed";
- regulator-name = "lcd";
- regulator-min-microvolt = <5050000>;
- regulator-max-microvolt = <5050000>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
- enable-active-high;
- vin-supply = <&sw5>;
- };
-
- /* This is probably coming straight from the battery.. */
- wl12xx_vmmc: regulator-wl12xx {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1650000>;
- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- volume_down {
- label = "Volume Down";
- gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
- linux,code = <KEY_VOLUMEDOWN>;
- linux,can-disable;
- /* Value above 7.95ms for no GPIO hardware debounce */
- debounce-interval = <10>;
- };
-
- slider {
- label = "Keypad Slide";
- gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
- linux,input-type = <EV_SW>;
- linux,code = <SW_KEYPAD_SLIDE>;
- linux,can-disable;
- /* Value above 7.95ms for no GPIO hardware debounce */
- debounce-interval = <10>;
- };
- };
-
- soundcard {
- compatible = "audio-graph-card";
- label = "Droid 4 Audio";
-
- simple-graph-card,widgets =
- "Speaker", "Earpiece",
- "Speaker", "Loudspeaker",
- "Headphone", "Headphone Jack",
- "Microphone", "Internal Mic";
-
- simple-graph-card,routing =
- "Earpiece", "EP",
- "Loudspeaker", "SPKR",
- "Headphone Jack", "HSL",
- "Headphone Jack", "HSR",
- "MICR", "Internal Mic";
-
- dais = <&mcbsp2_port>, <&mcbsp3_port>;
- };
-
- pwm8: dmtimer-pwm-8 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_direction_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer8>;
- ti,clock-source = <0x01>;
- };
-
- pwm9: dmtimer-pwm-9 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_enable_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer9>;
- ti,clock-source = <0x01>;
- };
-
- vibrator {
- compatible = "pwm-vibrator";
- pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
- pwm-names = "enable", "direction";
- direction-duty-cycle-ns = <10000000>;
- };
-};
-
-&dss {
- status = "okay";
-};
-
-&dsi1 {
- status = "okay";
- vdd-supply = <&vcsi>;
-
- port {
- dsi1_out_ep: endpoint {
- remote-endpoint = <&lcd0_in>;
- lanes = <0 1 2 3 4 5>;
- };
- };
-
- lcd0: display {
- compatible = "panel-dsi-cm";
- label = "lcd0";
- vddi-supply = <&lcd_regulator>;
- reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
-
- width-mm = <50>;
- height-mm = <89>;
-
- panel-timing {
- clock-frequency = <0>; /* Calculated by dsi */
-
- hback-porch = <2>;
- hactive = <540>;
- hfront-porch = <0>;
- hsync-len = <2>;
-
- vback-porch = <1>;
- vactive = <960>;
- vfront-porch = <0>;
- vsync-len = <1>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
- port {
- lcd0_in: endpoint {
- remote-endpoint = <&dsi1_out_ep>;
- };
- };
- };
-};
-
-&hdmi {
- status = "okay";
- pinctrl-0 = <&dss_hdmi_pins>;
- pinctrl-names = "default";
- vdda-supply = <&vdac>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- lanes = <1 0 3 2 5 4 7 6>;
- };
- };
-};
-
-&i2c1 {
- tmp105@48 {
- compatible = "ti,tmp105";
- reg = <0x48>;
- pinctrl-0 = <&tmp105_irq>;
- pinctrl-names = "default";
- /* kpd_row0.gpio_178 */
- interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
- &omap4_pmx_core 0x14e>;
- interrupt-names = "irq", "wakeup";
- wakeup-source;
- };
-};
-
-&keypad {
- keypad,num-rows = <8>;
- keypad,num-columns = <8>;
- linux,keymap = <
-
- /* Row 1 */
- MATRIX_KEY(0, 2, KEY_1)
- MATRIX_KEY(0, 6, KEY_2)
- MATRIX_KEY(2, 3, KEY_3)
- MATRIX_KEY(0, 7, KEY_4)
- MATRIX_KEY(0, 4, KEY_5)
- MATRIX_KEY(5, 5, KEY_6)
- MATRIX_KEY(0, 1, KEY_7)
- MATRIX_KEY(0, 5, KEY_8)
- MATRIX_KEY(0, 0, KEY_9)
- MATRIX_KEY(1, 6, KEY_0)
-
- /* Row 2 */
- MATRIX_KEY(3, 4, KEY_APOSTROPHE)
- MATRIX_KEY(7, 6, KEY_Q)
- MATRIX_KEY(7, 7, KEY_W)
- MATRIX_KEY(7, 2, KEY_E)
- MATRIX_KEY(1, 0, KEY_R)
- MATRIX_KEY(4, 4, KEY_T)
- MATRIX_KEY(1, 2, KEY_Y)
- MATRIX_KEY(6, 7, KEY_U)
- MATRIX_KEY(2, 2, KEY_I)
- MATRIX_KEY(5, 6, KEY_O)
- MATRIX_KEY(3, 7, KEY_P)
- MATRIX_KEY(6, 5, KEY_BACKSPACE)
-
- /* Row 3 */
- MATRIX_KEY(5, 4, KEY_TAB)
- MATRIX_KEY(5, 7, KEY_A)
- MATRIX_KEY(2, 7, KEY_S)
- MATRIX_KEY(7, 0, KEY_D)
- MATRIX_KEY(2, 6, KEY_F)
- MATRIX_KEY(6, 2, KEY_G)
- MATRIX_KEY(6, 6, KEY_H)
- MATRIX_KEY(1, 4, KEY_J)
- MATRIX_KEY(3, 1, KEY_K)
- MATRIX_KEY(2, 1, KEY_L)
- MATRIX_KEY(4, 6, KEY_ENTER)
-
- /* Row 4 */
- MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */
- MATRIX_KEY(6, 1, KEY_Z)
- MATRIX_KEY(7, 4, KEY_X)
- MATRIX_KEY(5, 1, KEY_C)
- MATRIX_KEY(1, 7, KEY_V)
- MATRIX_KEY(2, 4, KEY_B)
- MATRIX_KEY(4, 1, KEY_N)
- MATRIX_KEY(1, 1, KEY_M)
- MATRIX_KEY(3, 5, KEY_COMMA)
- MATRIX_KEY(5, 2, KEY_DOT)
- MATRIX_KEY(6, 3, KEY_UP)
- MATRIX_KEY(7, 3, KEY_OK)
-
- /* Row 5 */
- MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */
- MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */
- MATRIX_KEY(6, 0, KEY_MINUS)
- MATRIX_KEY(4, 7, KEY_EQUAL)
- MATRIX_KEY(1, 5, KEY_SPACE)
- MATRIX_KEY(3, 2, KEY_SLASH)
- MATRIX_KEY(4, 3, KEY_LEFT)
- MATRIX_KEY(5, 3, KEY_DOWN)
- MATRIX_KEY(3, 3, KEY_RIGHT)
-
- /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
- MATRIX_KEY(5, 0, KEY_VOLUMEUP)
- >;
-};
-
-&mmc1 {
- vmmc-supply = <&vwlan2>;
- bus-width = <4>;
- cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
-};
-
-&mmc2 {
- vmmc-supply = <&vsdio>;
- bus-width = <8>;
- ti,non-removable;
-};
-
-&mmc3 {
- vmmc-supply = <&wl12xx_vmmc>;
- /* uart2_tx.sdmmc3_dat1 pad as wakeirq */
- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
- &omap4_pmx_core 0xde>;
- interrupt-names = "irq", "wakeup";
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
- keep-power-in-suspend;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1285", "ti,wl1283";
- reg = <2>;
- /* gpio_100 with gpmc_wait2 pad as wakeirq */
- interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
- <&omap4_pmx_core 0x4e>;
- interrupt-names = "irq", "wakeup";
- ref-clock-frequency = <26000000>;
- tcxo-clock-frequency = <26000000>;
- };
-};
-
-&i2c1 {
- led-controller@38 {
- compatible = "ti,lm3532";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x38>;
-
- enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
-
- ramp-up-us = <1024>;
- ramp-down-us = <8193>;
-
- led@0 {
- reg = <0>;
- led-sources = <2>;
- ti,led-mode = <0>;
- label = ":backlight";
- linux,default-trigger = "backlight";
- };
-
- led@1 {
- reg = <1>;
- led-sources = <1>;
- ti,led-mode = <0>;
- label = ":kbd_backlight";
- };
- };
-};
-
-&i2c2 {
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_pins>;
-
- reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
-
- /* gpio_183 with sys_nirq2 pad as wakeup */
- interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>,
- <&omap4_pmx_core 0x160>;
- interrupt-names = "irq", "wakeup";
- wakeup-source;
- };
-
- isl29030@44 {
- compatible = "isil,isl29030";
- reg = <0x44>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&als_proximity_pins>;
-
- interrupt-parent = <&gpio6>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
- };
-};
-
-&omap4_pmx_core {
-
- /* hdmi_hpd.gpio_63 */
- hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
- >;
- };
-
- /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
- dss_hdmi_pins: pinmux_dss_hdmi_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
- >;
- };
-
- /* gpmc_ncs0.gpio_50 */
- poweroff_gpio: pinmux_poweroff_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- /* kpd_row0.gpio_178 */
- tmp105_irq: pinmux_tmp105_irq {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
- /* gpio_60 */
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)