diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
commit | bfbf18d991756858337f7700e8ff0a6f0dc31afc (patch) | |
tree | cf3568de4fdff1891e277507f08f49a871682706 /dts/src/mips/brcm/bcm3368.dtsi | |
parent | 834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff) | |
download | barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz |
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/mips/brcm/bcm3368.dtsi')
-rw-r--r-- | dts/src/mips/brcm/bcm3368.dtsi | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/dts/src/mips/brcm/bcm3368.dtsi b/dts/src/mips/brcm/bcm3368.dtsi new file mode 100644 index 0000000000..bee855cb80 --- /dev/null +++ b/dts/src/mips/brcm/bcm3368.dtsi @@ -0,0 +1,101 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm3368"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <150000000>; + + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + ubus { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges; + + periph_cntl: syscon@fff8c000 { + compatible = "syscon"; + reg = <0xfff8c000 0xc>; + native-endian; + }; + + reboot: syscon-reboot@fff8c008 { + compatible = "syscon-reboot"; + regmap = <&periph_cntl>; + offset = <0x8>; + mask = <0x1>; + }; + + periph_intc: interrupt-controller@fff8c00c { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0xfff8c00c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + uart0: serial@fff8c100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfff8c100 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <2>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + uart1: serial@fff8c120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfff8c120 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <3>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + }; +}; |