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authorSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
commit3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 (patch)
treeeb5a7bfce811d20e58dd0eb1add0f6cf0e6b86e0 /dts/src/mips/ingenic/ci20.dts
parent81ceab95360295cef146e89a1cd1cd5e590aa75e (diff)
downloadbarebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.gz
barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.xz
dts: update to v5.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/mips/ingenic/ci20.dts')
-rw-r--r--dts/src/mips/ingenic/ci20.dts9
1 files changed, 6 insertions, 3 deletions
diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts
index a688809bee..b249a4f0f6 100644
--- a/dts/src/mips/ingenic/ci20.dts
+++ b/dts/src/mips/ingenic/ci20.dts
@@ -113,9 +113,12 @@
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
- assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
- assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
- assigned-clock-rates = <48000000>;
+ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
+ <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>;
+ assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
+ <&cgu JZ4780_CLK_MPLL>,
+ <&cgu JZ4780_CLK_SSIPLL>;
+ assigned-clock-rates = <48000000>, <0>, <54000000>;
};
&tcu {