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author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-12-13 07:55:33 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-12-13 07:55:33 +0100 |
commit | 0e80215da956b08bb3da8501e3e6dd60784d8ca6 (patch) | |
tree | dd43b760055536c7ab1c3a14f320b415b5af8a86 /dts/src/riscv | |
parent | bb21fa523c0a8d56e9e1d63d7e00e68fb3d79375 (diff) | |
download | barebox-0e80215da956b08bb3da8501e3e6dd60784d8ca6.tar.gz barebox-0e80215da956b08bb3da8501e3e6dd60784d8ca6.tar.xz |
dts: update to v6.7-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/riscv')
-rw-r--r-- | dts/src/riscv/microchip/mpfs-icicle-kit.dts | 7 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs-m100pfsevp.dts | 7 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs-polarberry.dts | 7 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs-sev-kit.dts | 7 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs-tysom-m.dts | 7 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs.dtsi | 1 | ||||
-rw-r--r-- | dts/src/riscv/sophgo/cv1800b.dtsi | 1 |
7 files changed, 1 insertions, 36 deletions
diff --git a/dts/src/riscv/microchip/mpfs-icicle-kit.dts b/dts/src/riscv/microchip/mpfs-icicle-kit.dts index 90b2611147..dce96f27cc 100644 --- a/dts/src/riscv/microchip/mpfs-icicle-kit.dts +++ b/dts/src/riscv/microchip/mpfs-icicle-kit.dts @@ -8,9 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> -/* Clock frequency (in Hz) of the rtcclk */ -#define RTCCLK_FREQ 1000000 - / { model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", @@ -29,10 +26,6 @@ stdout-path = "serial1:115200n8"; }; - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - leds { compatible = "gpio-leds"; diff --git a/dts/src/riscv/microchip/mpfs-m100pfsevp.dts b/dts/src/riscv/microchip/mpfs-m100pfsevp.dts index 184cb36a17..a8d623ee9f 100644 --- a/dts/src/riscv/microchip/mpfs-m100pfsevp.dts +++ b/dts/src/riscv/microchip/mpfs-m100pfsevp.dts @@ -10,9 +10,6 @@ #include "mpfs.dtsi" #include "mpfs-m100pfs-fabric.dtsi" -/* Clock frequency (in Hz) of the rtcclk */ -#define MTIMER_FREQ 1000000 - / { model = "Aries Embedded M100PFEVPS"; compatible = "aries,m100pfsevp", "microchip,mpfs"; @@ -33,10 +30,6 @@ stdout-path = "serial1:115200n8"; }; - cpus { - timebase-frequency = <MTIMER_FREQ>; - }; - ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; diff --git a/dts/src/riscv/microchip/mpfs-polarberry.dts b/dts/src/riscv/microchip/mpfs-polarberry.dts index c87cc2d8fe..ea0808ab10 100644 --- a/dts/src/riscv/microchip/mpfs-polarberry.dts +++ b/dts/src/riscv/microchip/mpfs-polarberry.dts @@ -6,9 +6,6 @@ #include "mpfs.dtsi" #include "mpfs-polarberry-fabric.dtsi" -/* Clock frequency (in Hz) of the rtcclk */ -#define MTIMER_FREQ 1000000 - / { model = "Sundance PolarBerry"; compatible = "sundance,polarberry", "microchip,mpfs"; @@ -22,10 +19,6 @@ stdout-path = "serial0:115200n8"; }; - cpus { - timebase-frequency = <MTIMER_FREQ>; - }; - ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x2e000000>; diff --git a/dts/src/riscv/microchip/mpfs-sev-kit.dts b/dts/src/riscv/microchip/mpfs-sev-kit.dts index 013cb666c7..f9a8905794 100644 --- a/dts/src/riscv/microchip/mpfs-sev-kit.dts +++ b/dts/src/riscv/microchip/mpfs-sev-kit.dts @@ -6,9 +6,6 @@ #include "mpfs.dtsi" #include "mpfs-sev-kit-fabric.dtsi" -/* Clock frequency (in Hz) of the rtcclk */ -#define MTIMER_FREQ 1000000 - / { #address-cells = <2>; #size-cells = <2>; @@ -28,10 +25,6 @@ stdout-path = "serial1:115200n8"; }; - cpus { - timebase-frequency = <MTIMER_FREQ>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/src/riscv/microchip/mpfs-tysom-m.dts b/dts/src/riscv/microchip/mpfs-tysom-m.dts index e0797c7e1b..d1120f5f2c 100644 --- a/dts/src/riscv/microchip/mpfs-tysom-m.dts +++ b/dts/src/riscv/microchip/mpfs-tysom-m.dts @@ -11,9 +11,6 @@ #include "mpfs.dtsi" #include "mpfs-tysom-m-fabric.dtsi" -/* Clock frequency (in Hz) of the rtcclk */ -#define MTIMER_FREQ 1000000 - / { model = "Aldec TySOM-M-MPFS250T-REV2"; compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; @@ -34,10 +31,6 @@ stdout-path = "serial1:115200n8"; }; - cpus { - timebase-frequency = <MTIMER_FREQ>; - }; - ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x30000000>; diff --git a/dts/src/riscv/microchip/mpfs.dtsi b/dts/src/riscv/microchip/mpfs.dtsi index a6faf24f1d..266489d439 100644 --- a/dts/src/riscv/microchip/mpfs.dtsi +++ b/dts/src/riscv/microchip/mpfs.dtsi @@ -13,6 +13,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + timebase-frequency = <1000000>; cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; diff --git a/dts/src/riscv/sophgo/cv1800b.dtsi b/dts/src/riscv/sophgo/cv1800b.dtsi index df40e87ee0..aec6401a46 100644 --- a/dts/src/riscv/sophgo/cv1800b.dtsi +++ b/dts/src/riscv/sophgo/cv1800b.dtsi @@ -34,7 +34,6 @@ cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; - #address-cells = <0>; #interrupt-cells = <1>; }; }; |