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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-09-13 10:20:12 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-09-13 10:20:12 +0200 |
| commit | 1dd61d3c9561085edf7b51c2c212b8cfeba598f4 (patch) | |
| tree | f2a774501eb132803a14fc574b7ef64401070865 /dts/src/riscv | |
| parent | 18f2d1491df374df636ffb2b1b4ceb68b2b6e597 (diff) | |
| download | barebox-1dd61d3c9561085edf7b51c2c212b8cfeba598f4.tar.gz barebox-1dd61d3c9561085edf7b51c2c212b8cfeba598f4.tar.xz | |
dts: update to v6.0-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/riscv')
| -rw-r--r-- | dts/src/riscv/microchip/mpfs.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/dts/src/riscv/microchip/mpfs.dtsi b/dts/src/riscv/microchip/mpfs.dtsi index 74493344ea..6d9d455fa1 100644 --- a/dts/src/riscv/microchip/mpfs.dtsi +++ b/dts/src/riscv/microchip/mpfs.dtsi @@ -185,7 +185,7 @@ ranges; cctrllr: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; + compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x1000>; cache-block-size = <64>; cache-level = <2>; |