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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
| commit | 2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch) | |
| tree | 468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/src/riscv | |
| parent | 785f926d4527184194b6424bc39ce367e2cea7d8 (diff) | |
| download | barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz | |
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/riscv')
| -rw-r--r-- | dts/src/riscv/sifive/fu540-c000.dtsi | 22 | ||||
| -rw-r--r-- | dts/src/riscv/sifive/hifive-unleashed-a00.dts | 8 |
2 files changed, 27 insertions, 3 deletions
diff --git a/dts/src/riscv/sifive/fu540-c000.dtsi b/dts/src/riscv/sifive/fu540-c000.dtsi index 42b5ec2231..afa43c7ea3 100644 --- a/dts/src/riscv/sifive/fu540-c000.dtsi +++ b/dts/src/riscv/sifive/fu540-c000.dtsi @@ -13,6 +13,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; + ethernet0 = ð0; }; chosen { @@ -60,7 +61,6 @@ }; }; cpu2: cpu@2 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -84,7 +84,6 @@ }; }; cpu3: cpu@3 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -108,7 +107,6 @@ }; }; cpu4: cpu@4 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -230,6 +228,24 @@ #size-cells = <0>; status = "disabled"; }; + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42 43 44 45>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46 47 48 49>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; }; }; diff --git a/dts/src/riscv/sifive/hifive-unleashed-a00.dts b/dts/src/riscv/sifive/hifive-unleashed-a00.dts index 93d68cbd64..104d334511 100644 --- a/dts/src/riscv/sifive/hifive-unleashed-a00.dts +++ b/dts/src/riscv/sifive/hifive-unleashed-a00.dts @@ -85,3 +85,11 @@ reg = <0>; }; }; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; |