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authorSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
commitbfbf18d991756858337f7700e8ff0a6f0dc31afc (patch)
treecf3568de4fdff1891e277507f08f49a871682706 /dts/src/xtensa
parent834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff)
downloadbarebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz
barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/xtensa')
-rw-r--r--dts/src/xtensa/csp.dts54
-rw-r--r--dts/src/xtensa/xtfpga.dtsi15
2 files changed, 61 insertions, 8 deletions
diff --git a/dts/src/xtensa/csp.dts b/dts/src/xtensa/csp.dts
new file mode 100644
index 0000000000..4082f26716
--- /dev/null
+++ b/dts/src/xtensa/csp.dts
@@ -0,0 +1,54 @@
+/dts-v1/;
+
+/ {
+ compatible = "cdns,xtensa-xtfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&pic>;
+
+ chosen {
+ bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "cdns,xtensa-cpu";
+ reg = <0>;
+ };
+ };
+
+ pic: pic {
+ compatible = "cdns,xtensa-pic";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ clocks {
+ osc: main-oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf0000000 0x10000000>;
+
+ uart0: serial@0d000000 {
+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+ clocks = <&osc>, <&osc>;
+ clock-names = "uart_clk", "pclk";
+ reg = <0x0d000000 0x1000>;
+ interrupts = <0 1>;
+ };
+ };
+};
diff --git a/dts/src/xtensa/xtfpga.dtsi b/dts/src/xtensa/xtfpga.dtsi
index cd45f9c2c4..91616a9d79 100644
--- a/dts/src/xtensa/xtfpga.dtsi
+++ b/dts/src/xtensa/xtfpga.dtsi
@@ -19,9 +19,7 @@
cpu@0 {
compatible = "cdns,xtensa-cpu";
reg = <0>;
- /* Filled in by platform_setup from FPGA register
- * clock-frequency = <100000000>;
- */
+ clocks = <&osc>;
};
};
@@ -36,11 +34,6 @@
};
clocks {
- osc: main-oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
clk54: clk54 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -54,6 +47,12 @@
compatible = "simple-bus";
ranges = <0x00000000 0xf0000000 0x10000000>;
+ osc: main-oscillator {
+ #clock-cells = <0>;
+ compatible = "cdns,xtfpga-clock";
+ reg = <0x0d020004 0x4>;
+ };
+
serial0: serial@0d050020 {
device_type = "serial";
compatible = "ns16550a";