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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-11-15 09:02:29 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:48:45 +0100 |
commit | 37beaba4559bf62e6f4b35abc4ded9f7e7ed6796 (patch) | |
tree | 968d658900dc8f298ca13af7262813100e7680ba /dts/src | |
parent | c580e8422c0cb6dfe963c826a9d83214e6f0aa8a (diff) | |
download | barebox-37beaba4559bf62e6f4b35abc4ded9f7e7ed6796.tar.gz barebox-37beaba4559bf62e6f4b35abc4ded9f7e7ed6796.tar.xz |
dts: update to v4.9-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src')
-rw-r--r-- | dts/src/arm/ste-snowball.dts | 15 | ||||
-rw-r--r-- | dts/src/arm/uniphier-pro5.dtsi | 4 | ||||
-rw-r--r-- | dts/src/arm/uniphier-pxs2.dtsi | 4 | ||||
-rw-r--r-- | dts/src/arm/vf500.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm64/broadcom/ns2-svk.dts | 2 | ||||
-rw-r--r-- | dts/src/arm64/freescale/fsl-ls1043a.dtsi | 1 | ||||
-rw-r--r-- | dts/src/arm64/freescale/fsl-ls2080a.dtsi | 1 | ||||
-rw-r--r-- | dts/src/arm64/marvell/armada-cp110-master.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3368-geekbox.dts | 3 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts | 4 | ||||
-rw-r--r-- | dts/src/arm64/socionext/uniphier-ld20.dtsi | 12 |
11 files changed, 29 insertions, 21 deletions
diff --git a/dts/src/arm/ste-snowball.dts b/dts/src/arm/ste-snowball.dts index b3df1c60d4..386eee6de2 100644 --- a/dts/src/arm/ste-snowball.dts +++ b/dts/src/arm/ste-snowball.dts @@ -239,14 +239,25 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; + cap-sd-highspeed; cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + /* All direction control is used */ + st,sig-dir-cmd; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-pin-fbclk; + full-pwr-cycle; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi0_default_mode>; pinctrl-1 = <&sdi0_sleep_mode>; - cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218 + /* GPIO218 MMC_CD */ + cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -549,7 +560,7 @@ /* VMMCI level-shifter enable */ snowball_cfg3 { pins = "GPIO217_AH12"; - ste,config = <&gpio_out_lo>; + ste,config = <&gpio_out_hi>; }; /* VMMCI level-shifter voltage select */ snowball_cfg4 { diff --git a/dts/src/arm/uniphier-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi index 2c49c3614b..5357ea9c14 100644 --- a/dts/src/arm/uniphier-pro5.dtsi +++ b/dts/src/arm/uniphier-pro5.dtsi @@ -184,11 +184,11 @@ }; &mio_clk { - compatible = "socionext,uniphier-pro5-mio-clock"; + compatible = "socionext,uniphier-pro5-sd-clock"; }; &mio_rst { - compatible = "socionext,uniphier-pro5-mio-reset"; + compatible = "socionext,uniphier-pro5-sd-reset"; }; &peri_clk { diff --git a/dts/src/arm/uniphier-pxs2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi index 8789cd5189..950f07ba03 100644 --- a/dts/src/arm/uniphier-pxs2.dtsi +++ b/dts/src/arm/uniphier-pxs2.dtsi @@ -197,11 +197,11 @@ }; &mio_clk { - compatible = "socionext,uniphier-pxs2-mio-clock"; + compatible = "socionext,uniphier-pxs2-sd-clock"; }; &mio_rst { - compatible = "socionext,uniphier-pxs2-mio-reset"; + compatible = "socionext,uniphier-pxs2-sd-reset"; }; &peri_clk { diff --git a/dts/src/arm/vf500.dtsi b/dts/src/arm/vf500.dtsi index a3824e61bd..d7fdb2a7d9 100644 --- a/dts/src/arm/vf500.dtsi +++ b/dts/src/arm/vf500.dtsi @@ -70,7 +70,7 @@ global_timer: timer@40002200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x40002200 0x20>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&intc>; clocks = <&clks VF610_CLK_PLATFORM_BUS>; }; diff --git a/dts/src/arm64/broadcom/ns2-svk.dts b/dts/src/arm64/broadcom/ns2-svk.dts index 2d7872a36b..b09f3bc5c6 100644 --- a/dts/src/arm64/broadcom/ns2-svk.dts +++ b/dts/src/arm64/broadcom/ns2-svk.dts @@ -164,6 +164,8 @@ nand-ecc-mode = "hw"; nand-ecc-strength = <8>; nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; #address-cells = <1>; #size-cells = <1>; }; diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi index 220ac7057d..97d331ec25 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi @@ -123,6 +123,7 @@ <1 14 0xf08>, /* Physical Non-Secure PPI */ <1 11 0xf08>, /* Virtual PPI */ <1 10 0xf08>; /* Hypervisor PPI */ + fsl,erratum-a008585; }; pmu { diff --git a/dts/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/src/arm64/freescale/fsl-ls2080a.dtsi index 337da90bd7..7f0dc13b40 100644 --- a/dts/src/arm64/freescale/fsl-ls2080a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls2080a.dtsi @@ -195,6 +195,7 @@ <1 14 4>, /* Physical Non-Secure PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */ + fsl,erratum-a008585; }; pmu { diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi index e5e3ed678b..602e2c2e9a 100644 --- a/dts/src/arm64/marvell/armada-cp110-master.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi @@ -131,7 +131,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <1>; - clocks = <&cpm_syscon0 0 3>; + clocks = <&cpm_syscon0 1 21>; status = "disabled"; }; diff --git a/dts/src/arm64/rockchip/rk3368-geekbox.dts b/dts/src/arm64/rockchip/rk3368-geekbox.dts index 46cdddfcea..e5eeca2c24 100644 --- a/dts/src/arm64/rockchip/rk3368-geekbox.dts +++ b/dts/src/arm64/rockchip/rk3368-geekbox.dts @@ -116,7 +116,6 @@ cap-mmc-highspeed; clock-frequency = <150000000>; disable-wp; - keep-power-in-suspend; non-removable; num-slots = <1>; vmmc-supply = <&vcc_io>; @@ -258,8 +257,6 @@ }; vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; regulator-name = "vcc_sd"; }; diff --git a/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts index 5797933ef8..ea0a8eceef 100644 --- a/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts +++ b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts @@ -152,8 +152,6 @@ gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; vin-supply = <&vcc_io>; }; @@ -201,7 +199,6 @@ bus-width = <8>; cap-mmc-highspeed; disable-wp; - keep-power-in-suspend; mmc-pwrseq = <&emmc_pwrseq>; mmc-hs200-1_2v; mmc-hs200-1_8v; @@ -350,7 +347,6 @@ clock-freq-min-max = <400000 50000000>; cap-sd-highspeed; card-detect-delay = <200>; - keep-power-in-suspend; num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; diff --git a/dts/src/arm64/socionext/uniphier-ld20.dtsi b/dts/src/arm64/socionext/uniphier-ld20.dtsi index 08fd7cf776..56a1b2e92c 100644 --- a/dts/src/arm64/socionext/uniphier-ld20.dtsi +++ b/dts/src/arm64/socionext/uniphier-ld20.dtsi @@ -257,18 +257,18 @@ reg = <0x59801000 0x400>; }; - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", + sdctrl@59810000 { + compatible = "socionext,uniphier-ld20-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - mio_clk: clock { - compatible = "socionext,uniphier-ld20-mio-clock"; + sd_clk: clock { + compatible = "socionext,uniphier-ld20-sd-clock"; #clock-cells = <1>; }; - mio_rst: reset { - compatible = "socionext,uniphier-ld20-mio-reset"; + sd_rst: reset { + compatible = "socionext,uniphier-ld20-sd-reset"; #reset-cells = <1>; }; }; |