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authorSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
commit3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 (patch)
treeeb5a7bfce811d20e58dd0eb1add0f6cf0e6b86e0 /dts/src
parent81ceab95360295cef146e89a1cd1cd5e590aa75e (diff)
downloadbarebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.gz
barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.xz
dts: update to v5.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src')
-rw-r--r--dts/src/arm/am335x-pocketbeagle.dts1
-rw-r--r--dts/src/arm/arm-realview-eb.dtsi42
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-rw-r--r--dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts19
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi243
-rw-r--r--dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts21
-rw-r--r--dts/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts1
-rw-r--r--dts/src/arm64/qcom/sm6125.dtsi59
-rw-r--r--dts/src/arm64/qcom/sm6350-sony-xperia-lena-pdx213.dts58
-rw-r--r--dts/src/arm64/qcom/sm6350.dtsi965
-rw-r--r--dts/src/arm64/qcom/sm7225-fairphone-fp4.dts320
-rw-r--r--dts/src/arm64/qcom/sm7225.dtsi16
-rw-r--r--dts/src/arm64/qcom/sm8150-hdk.dts2
-rw-r--r--dts/src/arm64/qcom/sm8150-microsoft-surface-duo.dts3
-rw-r--r--dts/src/arm64/qcom/sm8150-mtp.dts2
-rw-r--r--dts/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts1
-rw-r--r--dts/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts1
-rw-r--r--dts/src/arm64/qcom/sm8150.dtsi161
-rw-r--r--dts/src/arm64/qcom/sm8250-hdk.dts2
-rw-r--r--dts/src/arm64/qcom/sm8250-mtp.dts2
-rw-r--r--dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts1
-rw-r--r--dts/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts1
-rw-r--r--dts/src/arm64/qcom/sm8250.dtsi52
-rw-r--r--dts/src/arm64/qcom/sm8350-hdk.dts2
-rw-r--r--dts/src/arm64/qcom/sm8350-mtp.dts6
-rw-r--r--dts/src/arm64/qcom/sm8350.dtsi302
-rw-r--r--dts/src/arm64/renesas/beacon-renesom-som.dtsi3
-rw-r--r--dts/src/arm64/renesas/cat875.dtsi2
-rw-r--r--dts/src/arm64/renesas/draak.dtsi686
-rw-r--r--dts/src/arm64/renesas/ebisu.dtsi803
-rw-r--r--dts/src/arm64/renesas/hihope-rzg2-ex.dtsi2
-rw-r--r--dts/src/arm64/renesas/r8a77961.dtsi11
-rw-r--r--dts/src/arm64/renesas/r8a77970-eagle.dts4
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts4
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts4
-rw-r--r--dts/src/arm64/renesas/r8a77980-v3hsk.dts4
-rw-r--r--dts/src/arm64/renesas/r8a77990-ebisu.dts788
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts671
-rw-r--r--dts/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi70
-rw-r--r--dts/src/arm64/renesas/r8a779a0-falcon.dts2
-rw-r--r--dts/src/arm64/renesas/r8a779a0.dtsi1458
-rw-r--r--dts/src/arm64/renesas/r8a779m0.dtsi12
-rw-r--r--dts/src/arm64/renesas/r8a779m1.dtsi9
-rw-r--r--dts/src/arm64/renesas/r8a779m2.dtsi12
-rw-r--r--dts/src/arm64/renesas/r8a779m3.dtsi9
-rw-r--r--dts/src/arm64/renesas/r8a779m4.dtsi12
-rw-r--r--dts/src/arm64/renesas/r8a779m5-salvator-xs.dts36
-rw-r--r--dts/src/arm64/renesas/r8a779m5.dtsi21
-rw-r--r--dts/src/arm64/renesas/r8a779m6.dtsi12
-rw-r--r--dts/src/arm64/renesas/r8a779m7.dtsi12
-rw-r--r--dts/src/arm64/renesas/r8a779m8.dtsi12
-rw-r--r--dts/src/arm64/renesas/r9a07g044.dtsi337
-rw-r--r--dts/src/arm64/renesas/r9a07g044l2-smarc.dts7
-rw-r--r--dts/src/arm64/renesas/rzg2l-smarc-som.dtsi275
-rw-r--r--dts/src/arm64/renesas/rzg2l-smarc.dtsi292
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi56
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi2
-rw-r--r--dts/src/arm64/rockchip/px30-evb.dts52
-rw-r--r--dts/src/arm64/rockchip/px30.dtsi126
-rw-r--r--dts/src/arm64/rockchip/rk3308.dtsi49
-rw-r--r--dts/src/arm64/rockchip/rk3318-a95x-z2.dts3
-rw-r--r--dts/src/arm64/rockchip/rk3326-odroid-go2.dts28
-rw-r--r--dts/src/arm64/rockchip/rk3328-roc-pc.dts110
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi17
-rw-r--r--dts/src/arm64/rockchip/rk3368-lion.dtsi47
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi191
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-bob.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-chromebook.dtsi176
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-scarlet-dumo.dts41
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi182
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-kobol-helios64.dts36
-rw-r--r--dts/src/arm64/rockchip/rk3399-op1-opp.dtsi6
-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi6
-rw-r--r--dts/src/arm64/rockchip/rk3399-pinebook-pro.dts7
-rw-r--r--dts/src/arm64/rockchip/rk3399-roc-pc-plus.dts218
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock-pi-4.dtsi54
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock-pi-4a-plus.dts14
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock-pi-4b-plus.dts47
-rw-r--r--dts/src/arm64/rockchip/rk3399-rockpro64.dtsi29
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi116
-rw-r--r--dts/src/arm64/rockchip/rk3566-quartz64-a.dts548
-rw-r--r--dts/src/arm64/rockchip/rk3566.dtsi20
-rw-r--r--dts/src/arm64/rockchip/rk3568-evb1-v10.dts313
-rw-r--r--dts/src/arm64/rockchip/rk3568-pinctrl.dtsi9
-rw-r--r--dts/src/arm64/rockchip/rk3568.dtsi644
-rw-r--r--dts/src/arm64/rockchip/rk356x.dtsi1145
-rw-r--r--dts/src/arm64/ti/k3-am64-main.dtsi280
-rw-r--r--dts/src/arm64/ti/k3-am64-mcu.dtsi8
-rw-r--r--dts/src/arm64/ti/k3-am64.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am642-evm.dts8
-rw-r--r--dts/src/arm64/ti/k3-am642-sk.dts8
-rw-r--r--dts/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi46
-rw-r--r--dts/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi51
-rw-r--r--dts/src/arm64/ti/k3-am65-iot2050-common.dtsi39
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi8
-rw-r--r--dts/src/arm64/ti/k3-am65-wakeup.dtsi4
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi60
-rw-r--r--dts/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts24
-rw-r--r--dts/src/arm64/ti/k3-am6528-iot2050-basic.dts56
-rw-r--r--dts/src/arm64/ti/k3-am654.dtsi4
-rw-r--r--dts/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi56
-rw-r--r--dts/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts29
-rw-r--r--dts/src/arm64/ti/k3-am6548-iot2050-advanced.dts50
-rw-r--r--dts/src/arm64/ti/k3-j7200-common-proc-board.dts3
-rw-r--r--dts/src/arm64/ti/k3-j7200-main.dtsi7
-rw-r--r--dts/src/arm64/ti/k3-j7200.dtsi2
-rw-r--r--dts/src/arm64/ti/k3-j721e-common-proc-board.dts3
-rw-r--r--dts/src/arm64/ti/k3-j721e-main.dtsi16
-rw-r--r--dts/src/arm64/ti/k3-j721e-sk.dts1002
-rw-r--r--dts/src/arm64/ti/k3-j721e.dtsi3
-rw-r--r--dts/src/arm64/toshiba/tmpv7708-rm-mbrc.dts6
-rw-r--r--dts/src/arm64/toshiba/tmpv7708-visrobo-vrb.dts61
-rw-r--r--dts/src/arm64/toshiba/tmpv7708-visrobo-vrc.dtsi44
-rw-r--r--dts/src/arm64/toshiba/tmpv7708.dtsi59
-rw-r--r--dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi13
-rw-r--r--dts/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dts315
-rw-r--r--dts/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dts298
-rw-r--r--dts/src/arm64/xilinx/zynqmp-sm-k26-revA.dts289
-rw-r--r--dts/src/arm64/xilinx/zynqmp-smk-k26-revA.dts21
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1232-revA.dts16
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts16
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1275-revA.dts18
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts298
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts342
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts49
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts24
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts330
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts264
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-rev1.1.dts15
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts320
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revB.dts3
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts292
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu104-revC.dts250
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts340
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts274
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi93
-rw-r--r--dts/src/mips/ingenic/ci20.dts9
-rw-r--r--dts/src/mips/ingenic/jz4725b.dtsi2
-rw-r--r--dts/src/mips/ingenic/jz4740.dtsi2
-rw-r--r--dts/src/mips/ingenic/jz4770.dtsi2
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi46
-rw-r--r--dts/src/mips/ingenic/x1000.dtsi2
-rw-r--r--dts/src/mips/ingenic/x1830.dtsi2
-rw-r--r--dts/src/mips/netlogic/xlp_evp.dts131
-rw-r--r--dts/src/mips/netlogic/xlp_fvp.dts131
-rw-r--r--dts/src/mips/netlogic/xlp_gvp.dts89
-rw-r--r--dts/src/mips/netlogic/xlp_rvp.dts89
-rw-r--r--dts/src/mips/netlogic/xlp_svp.dts131
-rw-r--r--dts/src/powerpc/a4m072.dts6
-rw-r--r--dts/src/powerpc/charon.dts8
-rw-r--r--dts/src/powerpc/digsy_mtc.dts8
-rw-r--r--dts/src/powerpc/lite5200.dts8
-rw-r--r--dts/src/powerpc/lite5200b.dts8
-rw-r--r--dts/src/powerpc/media5200.dts8
-rw-r--r--dts/src/powerpc/mpc5200b.dtsi6
-rw-r--r--dts/src/powerpc/mucmc52.dts6
-rw-r--r--dts/src/powerpc/o2d.dts2
-rw-r--r--dts/src/powerpc/o2d.dtsi2
-rw-r--r--dts/src/powerpc/o2dnt2.dts2
-rw-r--r--dts/src/powerpc/o3dnt.dts2
-rw-r--r--dts/src/powerpc/pcm030.dts6
-rw-r--r--dts/src/powerpc/pcm032.dts8
-rw-r--r--dts/src/powerpc/tqm5200.dts8
-rw-r--r--dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts18
-rw-r--r--dts/src/riscv/microchip/microchip-mpfs.dtsi40
-rw-r--r--dts/src/riscv/sifive/fu540-c000.dtsi2
-rw-r--r--dts/src/riscv/sifive/hifive-unleashed-a00.dts10
-rw-r--r--dts/src/riscv/sifive/hifive-unmatched-a00.dts7
-rw-r--r--dts/src/sh/j2_mimas_v2.dts2
675 files changed, 46522 insertions, 8160 deletions
diff --git a/dts/src/arm/am335x-pocketbeagle.dts b/dts/src/arm/am335x-pocketbeagle.dts
index 209cdd17dc..5e415d8ffd 100644
--- a/dts/src/arm/am335x-pocketbeagle.dts
+++ b/dts/src/arm/am335x-pocketbeagle.dts
@@ -205,6 +205,7 @@
&am33xx_pinmux {
+ compatible = "pinconf-single";
pinctrl-names = "default";
pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
diff --git a/dts/src/arm/arm-realview-eb.dtsi b/dts/src/arm/arm-realview-eb.dtsi
index 04e8a27ba1..2dfb32bf9d 100644
--- a/dts/src/arm/arm-realview-eb.dtsi
+++ b/dts/src/arm/arm-realview-eb.dtsi
@@ -198,96 +198,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
+ ranges = <0x0 0x10000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- led@08.0 {
+ led@8,0 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8,1 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8,2 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8,3 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8,4 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8,5 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8,6 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8,7 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
+ reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
- oscclk1: osc1@10 {
+ oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
+ reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
- oscclk2: osc2@14 {
+ oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
+ reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
- oscclk3: osc3@18 {
+ oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
+ reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
- oscclk4: osc4@1c {
+ oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
diff --git a/dts/src/arm/arm-realview-pb1176.dts b/dts/src/arm/arm-realview-pb1176.dts
index 366687fb1e..06b8723b09 100644
--- a/dts/src/arm/arm-realview-pb1176.dts
+++ b/dts/src/arm/arm-realview-pb1176.dts
@@ -216,96 +216,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
+ ranges = <0x0 0x10000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- led@08.0 {
+ led@8,0 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8,1 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8,2 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8,3 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8,4 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8,5 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8,6 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8,7 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
+ reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
- oscclk1: osc1@10 {
+ oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
+ reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
- oscclk2: osc2@14 {
+ oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
+ reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
- oscclk3: osc3@18 {
+ oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
+ reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
- oscclk4: osc4@1c {
+ oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
diff --git a/dts/src/arm/arm-realview-pb11mp.dts b/dts/src/arm/arm-realview-pb11mp.dts
index 228a51a38f..295aef4481 100644
--- a/dts/src/arm/arm-realview-pb11mp.dts
+++ b/dts/src/arm/arm-realview-pb11mp.dts
@@ -303,114 +303,132 @@
pb11mp_syscon: syscon@10000000 {
compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
+ ranges = <0x0 0x10000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- led@08.0 {
+ led@8,0 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8,1 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8,2 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8,3 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
- led@08.4 {
+ led@8,4 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
- led@08.5 {
+ led@8,5 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
- led@08.6 {
+ led@8,6 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8,7 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
+ reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
- oscclk1: osc1@10 {
+ oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
+ reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
- oscclk2: osc2@14 {
+ oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
+ reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
- oscclk3: osc3@18 {
+ oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
+ reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
- oscclk4: osc4@1c {
+ oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
clocks = <&xtal24mhz>;
};
- oscclk5: osc5@d4 {
+ oscclk5: clock-controller@d4 {
compatible = "arm,syscon-icst307";
+ reg = <0xd4 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd4>;
clocks = <&xtal24mhz>;
};
- oscclk6: osc6@d8 {
+ oscclk6: clock-controller@d8 {
compatible = "arm,syscon-icst307";
+ reg = <0xd8 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd8>;
diff --git a/dts/src/arm/arm-realview-pbx.dtsi b/dts/src/arm/arm-realview-pbx.dtsi
index ccf6f756b6..6f61f968d6 100644
--- a/dts/src/arm/arm-realview-pbx.dtsi
+++ b/dts/src/arm/arm-realview-pbx.dtsi
@@ -220,96 +220,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
+ ranges = <0x0 0x10000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- led@08.0 {
+ led@8,0 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8,1 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8,2 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8,3 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8,4 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8,5 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8,6 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8,7 {
compatible = "register-bit-led";
+ reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
- oscclk0: osc0@0c {
+ oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
+ reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
- oscclk1: osc1@10 {
+ oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
+ reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
- oscclk2: osc2@14 {
+ oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
+ reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
- oscclk3: osc3@18 {
+ oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
+ reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
- oscclk4: osc4@1c {
+ oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
diff --git a/dts/src/arm/armada-381-netgear-gs110emx.dts b/dts/src/arm/armada-381-netgear-gs110emx.dts
new file mode 100644
index 0000000000..0a961116a1
--- /dev/null
+++ b/dts/src/arm/armada-381-netgear-gs110emx.dts
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Netgear GS110EMX";
+ compatible = "netgear,gs110emx", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = &eth0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&front_button_pins>;
+ pinctrl-names = "default";
+
+ factory_default {
+ label = "Factory Default";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+ };
+ };
+};
+
+&eth0 {
+ /* ethernet@70000 */
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&switch_interrupt_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+ reg = <0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: switch0phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: switch0phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: switch0phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: switch0phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: switch0phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: switch0phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: switch0phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: switch0phy8@8 {
+ reg = <0x8>;
+ };
+ };
+
+ mdio-external {
+ compatible = "marvell,mv88e6xxx-mdio-external";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@b {
+ reg = <0xb>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ phy2: ethernet-phy@c {
+ reg = <0xc>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ ethernet = <&eth0>;
+ label = "cpu";
+ reg = <0>;
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
+ port@1 {
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan2";
+ phy-handle = <&switch0phy2>;
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ reg = <4>;
+ };
+
+ port@5 {
+ label = "lan5";
+ phy-handle = <&switch0phy5>;
+ reg = <5>;
+ };
+
+ port@6 {
+ label = "lan6";
+ phy-handle = <&switch0phy6>;
+ reg = <6>;
+ };
+
+ port@7 {
+ label = "lan7";
+ phy-handle = <&switch0phy7>;
+ reg = <7>;
+ };
+
+ port@8 {
+ label = "lan8";
+ phy-handle = <&switch0phy8>;
+ reg = <8>;
+ };
+
+ port@9 {
+ /* 88X3310P external phy */
+ label = "lan9";
+ phy-handle = <&phy1>;
+ phy-mode = "xaui";
+ reg = <9>;
+ };
+
+ port@a {
+ /* 88X3310P external phy */
+ label = "lan10";
+ phy-handle = <&phy2>;
+ phy-mode = "xaui";
+ reg = <0xa>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ front_button_pins: front-button-pins {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+
+ switch_interrupt_pins: switch-interrupt-pins {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ read-only;
+ reg = <0x00000000 0x00100000>;
+ };
+
+ partition@100000 {
+ label = "env";
+ reg = <0x00100000 0x00010000>;
+ };
+
+ partition@200000 {
+ label = "rsv";
+ reg = <0x00110000 0x00010000>;
+ };
+
+ partition@300000 {
+ label = "image0";
+ reg = <0x00120000 0x00900000>;
+ };
+
+ partition@400000 {
+ label = "config";
+ reg = <0x00a20000 0x00300000>;
+ };
+
+ partition@480000 {
+ label = "debug";
+ reg = <0x00d20000 0x002e0000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-amd-ethanolx.dts b/dts/src/arm/aspeed-bmc-amd-ethanolx.dts
index 79d17841b3..6406a0f080 100644
--- a/dts/src/arm/aspeed-bmc-amd-ethanolx.dts
+++ b/dts/src/arm/aspeed-bmc-amd-ethanolx.dts
@@ -159,6 +159,11 @@
//24LC128 EEPROM
&i2c3 {
status = "okay";
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
};
//P0 Power regulators
diff --git a/dts/src/arm/aspeed-bmc-ampere-mtjade.dts b/dts/src/arm/aspeed-bmc-ampere-mtjade.dts
index 57b0c45a22..3515d55bd3 100644
--- a/dts/src/arm/aspeed-bmc-ampere-mtjade.dts
+++ b/dts/src/arm/aspeed-bmc-ampere-mtjade.dts
@@ -86,6 +86,18 @@
linux,code = <ASPEED_GPIO(J, 1)>;
};
+ S0_scp_auth_fail {
+ label = "S0_SCP_AUTH_FAIL";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
+
+ S1_scp_auth_fail {
+ label = "S1_SCP_AUTH_FAIL";
+ gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(Z, 5)>;
+ };
+
S1_overtemp {
label = "S1_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
@@ -590,7 +602,7 @@
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
/*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
"OCP_MAIN_PWREN","RESET_BUTTON","","",
- /*S0-S7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
@@ -604,4 +616,11 @@
"S1_BMC_DDR_ADR","","","","",
/*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
"BMC_OCP_PG";
+
+ i2c4_o_en {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_I2C4_O_EN";
+ };
};
diff --git a/dts/src/arm/aspeed-bmc-ibm-everest.dts b/dts/src/arm/aspeed-bmc-ibm-everest.dts
index 2efd706667..f42e2d776b 100644
--- a/dts/src/arm/aspeed-bmc-ibm-everest.dts
+++ b/dts/src/arm/aspeed-bmc-ibm-everest.dts
@@ -96,6 +96,20 @@
i2c32 = &i2c14mux1chn1;
i2c33 = &i2c14mux1chn2;
i2c34 = &i2c14mux1chn3;
+ i2c35 = &i2c15mux0chn0;
+ i2c36 = &i2c15mux0chn1;
+ i2c37 = &i2c15mux0chn2;
+ i2c38 = &i2c15mux0chn3;
+ i2c39 = &i2c15mux1chn0;
+ i2c40 = &i2c15mux1chn1;
+ i2c41 = &i2c15mux1chn2;
+ i2c42 = &i2c15mux1chn3;
+ i2c43 = &i2c15mux2chn0;
+ i2c44 = &i2c15mux2chn1;
+ i2c45 = &i2c15mux2chn2;
+ i2c46 = &i2c15mux2chn3;
+ i2c47 = &i2c8mux0chn0;
+ i2c48 = &i2c8mux0chn1;
serial4 = &uart5;
@@ -231,20 +245,36 @@
gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>;
};
};
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc1 7>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
};
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
- /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","","",
+ /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","checkstop","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "PIN_HOLE_RESET_IN_N","","",
- "PIN_HOLE_RESET_OUT_N","","","","",
+ "PIN_HOLE_RESET_OUT_N","","",
+ "factory-reset-toggle","",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","",
- /*I0-I7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","bmc-secure-boot","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
@@ -252,7 +282,7 @@
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","led-pcieslot-power","","","",
- /*Q0-Q7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
@@ -297,86 +327,6 @@
"presence-lcd-op",
"presence-base-op",
"";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -440,56 +390,6 @@
"expander-cable-card3",
"expander-cable-card4",
"expander-cable-card5";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
i2c-switch@70 {
@@ -533,36 +433,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -599,36 +469,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -665,36 +505,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
};
@@ -725,67 +535,6 @@
"expander-cable-card9",
"expander-cable-card10",
"expander-cable-card11";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
};
i2c-switch@70 {
@@ -829,36 +578,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -895,36 +614,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -961,36 +650,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1027,36 +686,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
};
@@ -1106,36 +735,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1172,36 +771,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1238,36 +807,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1304,36 +843,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
};
@@ -1347,11 +856,6 @@
gpio-controller;
#gpio-cells = <2>;
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
led@1 {
label = "pcieslot-c01";
reg = <1>;
@@ -1439,26 +943,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -2082,11 +1566,6 @@
type = <PCA955X_TYPE_LED>;
};
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
led@8 {
label = "vrm4";
reg = <8>;
@@ -2217,11 +1696,6 @@
type = <PCA955X_TYPE_LED>;
};
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
led@8 {
label = "vrm0";
reg = <8>;
@@ -2310,6 +1784,27 @@
compatible = "atmel,24c128";
reg = <0x50>;
};
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c8mux0chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&i2c9 {
@@ -2413,15 +1908,21 @@
};
&i2c14 {
+ multi-master;
status = "okay";
+ ibm-panel@62 {
+ compatible = "ibm,op-panel";
+ reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
+
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
- i2c-mux-idle-disconnect;
+ idle-state = <1>;
i2c14mux0chn0: i2c@0 {
#address-cells = <1>;
@@ -2651,16 +2152,6 @@
default-state = "keep";
type = <PCA955X_TYPE_LED>;
};
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
pca0: pca9552@61 {
@@ -2680,86 +2171,6 @@
"presence-fan2",
"presence-fan1",
"presence-fan0";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
};
@@ -2816,6 +2227,152 @@
&i2c15 {
status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c15mux0chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux0chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux0chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux0chn3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+ };
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9546";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c15mux1chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux1chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux1chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux1chn3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+ };
+
+ i2c-switch@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c15mux2chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux2chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+ };
+
+ i2c15mux2chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c15mux2chn3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
};
&ehci1 {
@@ -4050,11 +3607,6 @@
memory-region = <&flash_memory>;
};
-&kcs4 {
- compatible = "openbmc,mctp-lpc";
- status = "okay";
-};
-
&mac2 {
status = "okay";
pinctrl-names = "default";
@@ -4093,3 +3645,14 @@
status = "okay";
memory-region = <&vga_memory>;
};
+
+&kcs2 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca8 0xcac>;
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
diff --git a/dts/src/arm/aspeed-bmc-ibm-rainier.dts b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
index 6419c9762c..866f32cdcc 100644
--- a/dts/src/arm/aspeed-bmc-ibm-rainier.dts
+++ b/dts/src/arm/aspeed-bmc-ibm-rainier.dts
@@ -82,7 +82,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200n8";
+ bootargs = "console=ttyS4,115200n8 earlycon";
};
memory@80000000 {
@@ -116,34 +116,6 @@
};
};
- gpio-keys {
- compatible = "gpio-keys";
-
- ps0-presence {
- label = "ps0-presence";
- gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(S, 0)>;
- };
-
- ps1-presence {
- label = "ps1-presence";
- gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(S, 1)>;
- };
-
- ps2-presence {
- label = "ps2-presence";
- gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(S, 2)>;
- };
-
- ps3-presence {
- label = "ps3-presence";
- gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(S, 3)>;
- };
- };
-
i2c2mux: i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
@@ -246,6 +218,21 @@
linux,code = <11>;
};
};
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc1 7>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
};
&ehci1 {
@@ -259,10 +246,10 @@
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
- /*F0-F7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","factory-reset-toggle","",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","",
- /*I0-I7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","bmc-secure-boot","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
@@ -270,7 +257,7 @@
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","usb-power","","","","",
/*P0-P7*/ "","","","","pcieslot-power","","","",
- /*Q0-Q7*/ "cfam-reset","","","","","","","",
+ /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
/*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
"","","","",
@@ -282,13 +269,6 @@
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","";
- pin_mclr_vpp {
- gpio-hog;
- gpios = <ASPEED_GPIO(P, 7) GPIO_OPEN_DRAIN>;
- output-high;
- line-name = "mclr_vpp";
- };
-
i2c3_mux_oe_n {
gpio-hog;
gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_LOW>;
@@ -945,46 +925,6 @@
"DASD_BP2_PRESENT_N",
"DASD_BP1_PRESENT_N",
"DASD_BP0_PRESENT_N";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1025,86 +965,6 @@
"SLOT1_EXPANDER_PRSNT_N", "SLOT2_EXPANDER_PRSNT_N",
"SLOT3_EXPANDER_PRSNT_N", "SLOT4_EXPANDER_PRSNT_N",
"", "", "", "", "", "";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1126,6 +986,32 @@
reg = <0x4a>;
};
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard0-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard0-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -1182,6 +1068,58 @@
reg = <0x49>;
};
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard3-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard3-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard4-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard4-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -1290,6 +1228,486 @@
multi-master;
status = "okay";
+ pca9552@30 {
+ compatible = "ibm,pca9552";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "pcieslot0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "pcieslot1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "pcieslot2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "pcieslot3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "pcieslot4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "cpu1";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "cpu-vrm1";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "lcd-russel";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pca9552@31 {
+ compatible = "ibm,pca9552";
+ reg = <0x31>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm8";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm9";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm10";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm11";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm12";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm13";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm14";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm15";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pca9552@32 {
+ compatible = "ibm,pca9552";
+ reg = <0x32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm16";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm17";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm18";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm19";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm20";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm21";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm22";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm23";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm24";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm25";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm26";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm27";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm28";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm29";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm30";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm31";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pca9552@33 {
+ compatible = "ibm,pca9552";
+ reg = <0x33>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "planar";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cpu0";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "dasd-pyramid0";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "dasd-pyramid1";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "dasd-pyramid2";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "cpu0-vrm0";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "rtc-battery";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "base-blyth";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "pcieslot6";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "pcieslot7";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "pcieslot8";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "pcieslot9";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "pcieslot10";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "pcieslot11";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "tpm-wilson";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
si7021-a20@40 {
compatible = "silabs,si7020";
reg = <0x40>;
@@ -1343,93 +1761,103 @@
};
};
- pca0: pca9552@61 {
- compatible = "nxp,pca9552";
- reg = <0x61>;
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
- gpio@0 {
+ led@0 {
+ label = "front-sys-id0";
reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@1 {
+ led@1 {
+ label = "front-check-log0";
reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@2 {
+ led@2 {
+ label = "front-enc-fault1";
reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@3 {
+ led@3 {
+ label = "front-sys-pwron0";
reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
+ };
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
+ pca0: pca9552@61 {
+ compatible = "nxp,pca9552";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
+ led@0 {
+ label = "fan0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
+ led@1 {
+ label = "fan1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
+ led@2 {
+ label = "fan2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
+ led@3 {
+ label = "fan3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
+ led@4 {
+ label = "fan4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
+ led@5 {
+ label = "fan5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
};
};
@@ -1488,6 +1916,19 @@
reg = <0x51>;
};
+ pca_pres3: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "power-config-full-load", "";
+ };
+
pca_pres2: pca9552@61 {
compatible = "nxp,pca9552";
reg = <0x61>;
@@ -1504,86 +1945,6 @@
"SLOT8_EXPANDER_PRSNT_N", "SLOT9_EXPANDER_PRSNT_N",
"SLOT10_EXPANDER_PRSNT_N", "SLOT11_EXPANDER_PRSNT_N",
"", "", "", "";
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
};
};
@@ -1639,6 +2000,32 @@
reg = <0x49>;
};
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard10-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard10-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -1673,6 +2060,11 @@
&i2c12 {
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
&i2c13 {
@@ -1682,6 +2074,80 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "nvme4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "nvme5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "nvme6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "nvme7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
&i2c14 {
@@ -1691,6 +2157,80 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme8";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme9";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme10";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme11";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "nvme12";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "nvme13";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "nvme14";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "nvme15";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
&i2c15 {
@@ -1700,6 +2240,80 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme16";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme17";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme18";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme19";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "nvme20";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "nvme21";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "nvme22";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "nvme23";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
&vuart1 {
@@ -1777,3 +2391,14 @@
status = "okay";
memory-region = <&vga_memory>;
};
+
+&kcs2 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca8 0xcac>;
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
diff --git a/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
index 1752f3250e..60a39ea10a 100644
--- a/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
+++ b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
@@ -3,6 +3,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "FP5280G2 BMC";
@@ -245,7 +246,7 @@
label = "bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout.dtsi"
+#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -902,4 +903,10 @@
};
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
+
#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-inventec-transformers.dts b/dts/src/arm/aspeed-bmc-inventec-transformers.dts
new file mode 100644
index 0000000000..caf66651e5
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-inventec-transformers.dts
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2021 Inventec Corp.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include "aspeed-g6-pinctrl.dtsi"
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "TRANSFORMERS BMC";
+ compatible = "inventec,transformer-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ // UID led
+ uid {
+ label = "UID_LED";
+ gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ // Heart beat led
+ heartbeat {
+ label = "HB_LED";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mac3 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii4_default>;
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <33000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+#include "openbmc-flash-layout.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc2";
+ spi-max-frequency = <33000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bios";
+ spi-max-frequency = <33000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&wdt1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ //Set bmc' slave address;
+ bmc_slave@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ // FRU AT24C512C-SSHM-T
+ status = "okay";
+ eeprom@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp75@49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+
+ tmp75@4f {
+ compatible = "ti,tmp75";
+ reg = <0x4f>;
+ };
+
+ tmp468@48 {
+ compatible = "ti,tmp468";
+ reg = <0x48>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ adm1278@40 {
+ compatible = "adi,adm1278";
+ reg = <0x40>;
+ };
+};
+
+
+&i2c8 {
+ // FRU AT24C512C-SSHM-T
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ pagesize = <128>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c512";
+ reg = <0x53>;
+ pagesize = <128>;
+ };
+};
+
+&i2c9 {
+ // M.2
+ status = "okay";
+};
+
+&i2c10 {
+ // I2C EXPANDER
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ };
+};
+
+&i2c11 {
+ // I2C EXPANDER
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ pcie_eeprom_riser1: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@55 {
+ compatible = "atmel,24c512";
+ reg = <0x55>;
+ pagesize = <128>;
+ };
+ };
+
+ pcie_eeprom_riser2: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ eeprom@55 {
+ compatible = "atmel,24c512";
+ reg = <0x55>;
+ pagesize = <128>;
+ };
+ };
+
+ pcie_eeprom_riser3: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom@55 {
+ compatible = "atmel,24c512";
+ reg = <0x55>;
+ pagesize = <128>;
+ };
+ };
+ };
+};
+
+&i2c12 {
+ status = "okay";
+
+ psu0:psu0@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","power-chassis-control","","","",
+ /*G0-G7*/ "","","jtag-mux","","","","","",
+ /*H0-H7*/ "","","","","reset-button","power-button","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","tck-mux","","","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","nmi-button","","","","","","",
+ /*V0-V7*/ "","","","","power-config-full-load","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "","","","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+ non-removable;
+ max-frequency = <52000000>;
+ bus-width = <8>;
+};
+
+&vhub {
+ status = "okay";
+ aspeed,vhub-downstream-ports = <7>;
+ aspeed,vhub-generic-endpoints = <21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2ad_default>;
+};
+
+&rtc {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-tyan-s7106.dts b/dts/src/arm/aspeed-bmc-tyan-s7106.dts
new file mode 100644
index 0000000000..68f332ee18
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-tyan-s7106.dts
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Tyan S7106 BMC";
+ compatible = "tyan,s7106-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlycon";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ p2a_memory: region@987f0000 {
+ no-map;
+ reg = <0x987f0000 0x00010000>; /* 64KB */
+ };
+
+ vga_memory: framebuffer@9f000000 {
+ no-map;
+ reg = <0x9f000000 0x01000000>; /* 16M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>; /* 16M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 15>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ label = "bmc";
+ status = "okay";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart2 {
+ /* RS-232 connector on header */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default>;
+};
+
+&uart3 {
+ /* Alternative to vuart to internally connect (route) to uart1
+ * when vuart cannot be used due to BIOS limitations.
+ */
+ status = "okay";
+};
+
+&uart4 {
+ /* Alternative to vuart to internally connect (route) to the
+ * external port usually used by uart1 when vuart cannot be
+ * used due to BIOS limitations.
+ */
+ status = "okay";
+};
+
+&uart5 {
+ /* BMC "debug" (console) UART; connected to RS-232 connector
+ * on header; selectable via jumpers as alternative to uart2
+ */
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&p2a {
+ status = "okay";
+ memory-region = <&p2a_memory>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&adc {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default>;
+
+ /* CPU fan #0 */
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ /* CPU fan #1 */
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ /* PWM group for chassis fans #1, #2, #3 and #4 */
+ fan@2 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ /* PWM group for chassis fans #5 and #6 */
+ fan@6 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ /* Hardware monitor with temperature sensors */
+ nct7802@28 {
+ compatible = "nuvoton,nct7802";
+ reg = <0x28>;
+ };
+
+ /* Also connected to:
+ * - IPMB pin header
+ * - CPU #0 memory error LED @ 0x3A
+ * - CPU #1 memory error LED @ 0x3C
+ */
+};
+
+&i2c1 {
+ /* Directly connected to PCH SMBUS #0 */
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* BMC EEPROM, incl. mainboard FRU */
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+
+ /* Also connected to:
+ * - fan header
+ * - mini-SAS HD connector
+ * - SSATA SGPIO
+ * - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low)
+ * to PCH SMBUS #3
+ */
+};
+
+&i2c3 {
+ status = "okay";
+
+ /* PSU1 FRU @ 0xA0 */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* PSU2 FRU @ 0xA2 */
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* PSU1 @ 0xB0 */
+ power-supply@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+
+ /* PSU2 @ 0xB2 */
+ power-supply@59 {
+ compatible = "pmbus";
+ reg = <0x59>;
+ };
+
+ /* Also connected to:
+ * - PCH SMBUS #1
+ */
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Connected to:
+ * - PCH SMBUS #2
+ */
+
+ /* Connected via switch to:
+ * - CPU #0 channels ABC VDDQ @ 0x80
+ * - CPU #0 channels DEF VDDQ @ 0x81
+ * - CPU #1 channels ABC VDDQ @ 0x82
+ * - CPU #1 channels DEF VDDQ @ 0x83
+ * - CPU #0 VCCIO & VMCP @ 0x52
+ * - CPU #1 VCCIO & VMCP @ 0x53
+ * - CPU #0 VCCIN @ 0xC0
+ * - CPU #0 VSA @ 0xC2
+ * - CPU #1 VCCIN @ 0xC4
+ * - CPU #1 VSA @ 0xC6
+ * - J110
+ */
+};
+
+&i2c5 {
+ status = "okay";
+
+ /* Connected via switch (PCH_BMC_SMB_SW_P) to:
+ * - mainboard FRU @ 0xAE
+ * - XDP connector
+ * - ME debug header
+ * - clock buffer @ 0xD8
+ * - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH)
+ * - PCH SMBUS
+ */
+};
+
+&i2c6 {
+ status = "okay";
+
+ /* Connected via switch (BMC_PE_SMB_EN_1_N) to
+ * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
+ * - 0,0: PCIE slot 1, SMB #1
+ * - 0,1: PCIE slot 1, SMB #2
+ * - 1,0: PCIE slot 2, SMB #1
+ * - 1,1: PCIE slot 2, SMB #2
+ */
+
+ /* Connected via switch (BMC_PE_SMB_EN_2_N) to
+ * bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
+ * - 0,0: OCP0 (A) SMB
+ * - 0,1: OCP0 (C) SMB
+ * - 1,0: OCP1 (A) SMB
+ * - 1,1: NC
+ */
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Connected to:
+ * - PCH SMBUS #4
+ */
+};
+
+&i2c8 {
+ status = "okay";
+
+ /* Not connected */
+};
+
+&mac0 {
+ status = "okay";
+ use-ncsi;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&kcs1 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca8>;
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+};
+
+/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+/* We're following the GPIO naming as defined at
+ * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
+ *
+ * Notes on led-identify and id-button:
+ * - A physical button is connected to id-button which
+ * triggers the clock on a D flip-flop. The /Q output of the
+ * flip-flop drives its D input.
+ * - The flip-flop's Q output drives led-identify which is
+ * connected to LEDs.
+ * - With that, every button press toggles the LED between on and off.
+ *
+ * Notes on power-, reset- and nmi- button and control:
+ * - The -button signals can be used to monitor physical buttons.
+ * - The -control signals can be used to actuate the specific
+ * operation.
+ * - In hardware, the -button signals are connected to the -control
+ * signals through drivers with the -control signals being
+ * protected through diodes.
+ */
+&gpio {
+ status = "okay";
+ gpio-line-names =
+ /*A0*/ "",
+ /*A1*/ "",
+ /*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */
+ /*A3*/ "",
+ /*A4*/ "",
+ /*A5*/ "",
+ /*A6*/ "",
+ /*A7*/ "",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0*/ "",
+ /*C1*/ "",
+ /*C2*/ "",
+ /*C3*/ "",
+ /*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */
+ /*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */
+ /*C6*/ "",
+ /*C7*/ "",
+ /*D0*/ "",
+ /*D1*/ "",
+ /*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */
+ /*D3*/ "platform-reset", /* in: SYS_PLTRST_N */
+ /*D4*/ "",
+ /*D5*/ "",
+ /*D6*/ "",
+ /*D7*/ "",
+ /*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */
+ /*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */
+ /*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */
+ /*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */
+ /*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */
+ /*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */
+ /*E6*/ "",
+ /*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */
+ /*F0*/ "",
+ /*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */
+ /*F2*/ "",
+ /*F3*/ "",
+ /*F4*/ "led-fault", /* out: AST_HW_FAULT_N */
+ /*F5*/ "",
+ /*F6*/ "",
+ /*F7*/ "",
+ /*G0*/ "BMC_PE_SMB_EN_1_N", /* out */
+ /*G1*/ "BMC_PE_SMB_EN_2_N", /* out */
+ /*G2*/ "",
+ /*G3*/ "",
+ /*G4*/ "",
+ /*G5*/ "",
+ /*G6*/ "",
+ /*G7*/ "",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0*/ "",
+ /*Q1*/ "",
+ /*Q2*/ "",
+ /*Q3*/ "",
+ /*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */
+ /*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */
+ /*Q6*/ "",
+ /*Q7*/ "",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0*/ "",
+ /*AA1*/ "",
+ /*AA2*/ "",
+ /*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */
+ /*AA4*/ "",
+ /*AA5*/ "",
+ /*AA6*/ "",
+ /*AA7*/ "",
+ /*AB0-AB7*/ "","","","","","","","";
+};
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index c5aeb3cf3a..b313a1cf5f 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -383,6 +383,12 @@
interrupts = <8>;
status = "disabled";
};
+
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2400-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
};
uart2: serial@1e78d000 {
diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi
index 73ca1ec6fc..c7049454c7 100644
--- a/dts/src/arm/aspeed-g5.dtsi
+++ b/dts/src/arm/aspeed-g5.dtsi
@@ -491,6 +491,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2500-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
+
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
diff --git a/dts/src/arm/aspeed-g6.dtsi b/dts/src/arm/aspeed-g6.dtsi
index 1b47be1704..5106a424f1 100644
--- a/dts/src/arm/aspeed-g6.dtsi
+++ b/dts/src/arm/aspeed-g6.dtsi
@@ -364,6 +364,26 @@
status = "disabled";
};
+ adc0: adc@1e6e9000 {
+ compatible = "aspeed,ast2600-adc0";
+ reg = <0x1e6e9000 0x100>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ adc1: adc@1e6e9100 {
+ compatible = "aspeed,ast2600-adc1";
+ reg = <0x1e6e9100 0x100>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
gpio0: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
@@ -551,6 +571,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ status = "disabled";
+ };
+
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
diff --git a/dts/src/arm/at91-lmu5000.dts b/dts/src/arm/at91-lmu5000.dts
new file mode 100644
index 0000000000..f8863d7c07
--- /dev/null
+++ b/dts/src/arm/at91-lmu5000.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree file for CalAmp LMU5000 board
+ *
+ * Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>
+ */
+
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+ model = "CalAmp LMU5000";
+ compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ chosen {
+ bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2";
+ };
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <18432000>;
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&ebi {
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ kernel@0 {
+ label = "kernel";
+ reg = <0x0 0x400000>;
+ };
+
+ rootfs@400000 {
+ label = "rootfs";
+ reg = <0x400000 0x3C00000>;
+ };
+
+ user1@4000000 {
+ label = "user1";
+ reg = <0x4000000 0x2000000>;
+ };
+
+ user2@6000000 {
+ label = "user2";
+ reg = <0x6000000 0x2000000>;
+ };
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&pinctrl {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usb0 {
+ pinctrl_usb1_vbus_gpio: usb0_vbus_gpio {
+ atmel,pins = <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&ssc0 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usart0 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+};
+
+&usart2 {
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <2>;
+ status = "okay";
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/dts/src/arm/at91-q5xr5.dts b/dts/src/arm/at91-q5xr5.dts
new file mode 100644
index 0000000000..5827383b18
--- /dev/null
+++ b/dts/src/arm/at91-q5xr5.dts
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree file for Exegin Q5xR5 board
+ *
+ * Copyright (C) 2014 Owen Kirby <osk@exegin.com>
+ */
+
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+ model = "Exegin Q5x (rev5)";
+ compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
+ };
+
+ memory {
+ reg = <0x20000000 0x0>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <18432000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <18432000>;
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&ebi {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x1000000 0x800000>;
+ bank-width = <2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ kernel@0 {
+ label = "kernel";
+ reg = <0x0 0x200000>;
+ };
+
+ rootfs@200000 {
+ label = "rootfs";
+ reg = <0x200000 0x600000>;
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&pinctrl {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi0_npcs0: spi0_npcs0 {
+ atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi0_npcs1: spi0_npcs1 {
+ atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_npcs0: spi1_npcs0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_npcs1: spi1_npcs1 {
+ atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
+ cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91boot@0 {
+ label = "at91boot";
+ reg = <0x0 0x4000>;
+ };
+
+ uenv@4000 {
+ label = "uboot-env";
+ reg = <0x4000 0x4000>;
+ };
+
+ uboot@8000 {
+ label = "uboot";
+ reg = <0x8000 0x3E000>;
+ };
+ };
+
+ spidev@1 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <1>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
+ cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <0>;
+ };
+
+ spidev@1 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <1>;
+ };
+};
+
+&usart0 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <2>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/dts/src/arm/at91-sama5d27_som1.dtsi b/dts/src/arm/at91-sama5d27_som1.dtsi
index b48ac3b62a..a4623cc67c 100644
--- a/dts/src/arm/at91-sama5d27_som1.dtsi
+++ b/dts/src/arm/at91-sama5d27_som1.dtsi
@@ -8,6 +8,7 @@
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D27 SoM1";
@@ -95,8 +96,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@50 {
@@ -113,6 +117,12 @@
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_qspi1_default: qspi1_default {
sck_cs {
pinmux = <PIN_PB5__QSPI1_SCK>,
diff --git a/dts/src/arm/at91-sama5d27_som1_ek.dts b/dts/src/arm/at91-sama5d27_som1_ek.dts
index cd4672501a..08f0d4b995 100644
--- a/dts/src/arm/at91-sama5d27_som1_ek.dts
+++ b/dts/src/arm/at91-sama5d27_som1_ek.dts
@@ -130,8 +130,11 @@
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
};
@@ -215,8 +218,11 @@
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -252,6 +258,13 @@
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PD4__GPIO>,
+ <PIN_PD5__GPIO>;
+ bias-disable;
+ };
+
+
pinctrl_isc_base: isc_base {
pinmux = <PIN_PC21__ISC_PCK>,
<PIN_PC22__ISC_VSYNC>,
@@ -441,6 +454,12 @@
bias-disable;
};
+ pinctrl_i2c3_gpio: i2c3_gpio {
+ pinmux = <PIN_PA24__GPIO>,
+ <PIN_PA23__GPIO>;
+ bias-disable;
+ };
+
pinctrl_flx4_default: flx4_uart_default {
pinmux = <PIN_PC28__FLEXCOM4_IO0>,
<PIN_PC29__FLEXCOM4_IO1>,
diff --git a/dts/src/arm/at91-sama5d27_wlsom1.dtsi b/dts/src/arm/at91-sama5d27_wlsom1.dtsi
index 025a78310e..21c86171e4 100644
--- a/dts/src/arm/at91-sama5d27_wlsom1.dtsi
+++ b/dts/src/arm/at91-sama5d27_wlsom1.dtsi
@@ -30,6 +30,14 @@
clock-frequency = <24000000>;
};
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-wilc1000";
+ reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pinctrl_wilc_pwrseq>;
+ pinctrl-names = "default";
+ };
};
&flx1 {
@@ -310,5 +318,67 @@
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ cmd-data {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-disable;
+ };
+
+ conf-ck {
+ pinmux = <PIN_PA22__SDMMC1_CK>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_wilc_default: wilc_default {
+ conf-irq {
+ pinmux = <PIN_PB25__GPIO>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_wilc_pwrseq: wilc_pwrseq {
+ conf-ce-nrst {
+ pinmux = <PIN_PA27__GPIO>,
+ <PIN_PA29__GPIO>;
+ bias-disable;
+ };
+
+ conf-rtcclk {
+ pinmux = <PIN_PB13__PCK1>;
+ bias-disable;
+ };
+ };
+};
+
+&sdmmc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ no-1-8-v;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+
+ wilc: wifi@0 {
+ reg = <0>;
+ compatible = "microchip,wilc1000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wilc_default>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 9>;
+ clock-names = "rtc";
+ interrupts = <PIN_PB25 IRQ_TYPE_NONE>;
+ interrupt-parent = <&pioA>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
+ assigned-clock-rates = <32768>;
+ };
};
diff --git a/dts/src/arm/at91-sama5d2_icp.dts b/dts/src/arm/at91-sama5d2_icp.dts
index e06b58724c..806eb1d911 100644
--- a/dts/src/arm/at91-sama5d2_icp.dts
+++ b/dts/src/arm/at91-sama5d2_icp.dts
@@ -307,8 +307,11 @@
};
&i2c0 { /* mikrobus i2c */
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@@ -316,8 +319,11 @@
&i2c1 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@@ -402,6 +408,12 @@
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PD19__GPIO>,
+ <PIN_PD20__GPIO>;
+ bias-disable;
+ };
+
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;
bias-pull-up;
@@ -463,6 +475,12 @@
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_mikrobus1_an: mikrobus1_an {
pinmux = <PIN_PD26__GPIO>;
bias-disable;
diff --git a/dts/src/arm/at91-sama7g5ek.dts b/dts/src/arm/at91-sama7g5ek.dts
index f3d6aaa3a7..0e1975c681 100644
--- a/dts/src/arm/at91-sama7g5ek.dts
+++ b/dts/src/arm/at91-sama7g5ek.dts
@@ -122,6 +122,14 @@
};
};
+&adc {
+ vddana-supply = <&vddout25>;
+ vref-supply = <&vddout25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vddcpu>;
};
@@ -679,6 +687,18 @@
status = "okay";
};
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
&trng {
status = "okay";
};
diff --git a/dts/src/arm/at91-tse850-3.dts b/dts/src/arm/at91-tse850-3.dts
index 3ca97b47c6..7e5c598e7e 100644
--- a/dts/src/arm/at91-tse850-3.dts
+++ b/dts/src/arm/at91-tse850-3.dts
@@ -262,7 +262,7 @@
&macb1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi
index 019f1c3d4d..7368347c93 100644
--- a/dts/src/arm/at91sam9260.dtsi
+++ b/dts/src/arm/at91sam9260.dtsi
@@ -166,7 +166,7 @@
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
- pinctrl@fffff400 {
+ pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
diff --git a/dts/src/arm/axp209.dtsi b/dts/src/arm/axp209.dtsi
index 0d9ff12bdf..ca240cd6f6 100644
--- a/dts/src/arm/axp209.dtsi
+++ b/dts/src/arm/axp209.dtsi
@@ -53,7 +53,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp202-ac-power-supply";
status = "disabled";
};
@@ -69,7 +69,7 @@
#gpio-cells = <2>;
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp209-battery-power-supply";
status = "disabled";
};
@@ -112,7 +112,7 @@
};
};
- usb_power_supply: usb-power-supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};
diff --git a/dts/src/arm/axp22x.dtsi b/dts/src/arm/axp22x.dtsi
index 65a07a67ac..a020c12b28 100644
--- a/dts/src/arm/axp22x.dtsi
+++ b/dts/src/arm/axp22x.dtsi
@@ -52,7 +52,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
@@ -62,7 +62,7 @@
#io-channel-cells = <1>;
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
@@ -163,7 +163,7 @@
};
};
- usb_power_supply: usb_power_supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};
diff --git a/dts/src/arm/axp81x.dtsi b/dts/src/arm/axp81x.dtsi
index 1dfeeceabf..b93387b0c1 100644
--- a/dts/src/arm/axp81x.dtsi
+++ b/dts/src/arm/axp81x.dtsi
@@ -48,7 +48,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
@@ -63,18 +63,18 @@
gpio-controller;
#gpio-cells = <2>;
- gpio0_ldo: gpio0-ldo {
+ gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
- gpio1_ldo: gpio1-ldo {
+ gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
@@ -172,7 +172,7 @@
};
};
- usb_power_supply: usb-power-supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp813-usb-power-supply";
};
};
diff --git a/dts/src/arm/bcm-nsp-ax.dtsi b/dts/src/arm/bcm-nsp-ax.dtsi
new file mode 100644
index 0000000000..f2e941dbab
--- /dev/null
+++ b/dts/src/arm/bcm-nsp-ax.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom Northstar Plus Ax stepping-specific bindings.
+ * Notable differences from B0+ are the secondary-boot-reg and
+ * lack of DMA coherency.
+ */
+
+&cpu1 {
+ secondary-boot-reg = <0xffff042c>;
+};
+
+&dma {
+ /delete-property/ dma-coherent;
+};
+
+&sdio {
+ /delete-property/ dma-coherent;
+};
+
+&amac0 {
+ /delete-property/ dma-coherent;
+};
+
+&amac1 {
+ /delete-property/ dma-coherent;
+};
+
+&amac2 {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&mailbox {
+ /delete-property/ dma-coherent;
+};
+
+&xhci {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&ohci0 {
+ /delete-property/ dma-coherent;
+};
+
+&i2c0 {
+ /delete-property/ dma-coherent;
+};
+
+&sata {
+ /delete-property/ dma-coherent;
+};
+
+&pcie0 {
+ /delete-property/ dma-coherent;
+};
+
+&pcie1 {
+ /delete-property/ dma-coherent;
+};
+
+&pcie2 {
+ /delete-property/ dma-coherent;
+};
diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi
index 748df7955a..1c08daa188 100644
--- a/dts/src/arm/bcm-nsp.dtsi
+++ b/dts/src/arm/bcm-nsp.dtsi
@@ -77,7 +77,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- mpcore@19000000 {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -166,7 +166,7 @@
};
};
- axi@18000000 {
+ axi: axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
@@ -219,7 +219,7 @@
status = "disabled";
};
- sdio: sdhci@21000 {
+ sdio: mmc@21000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x21000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
@@ -310,6 +310,7 @@
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
xhci: usb@29000 {
@@ -362,6 +363,42 @@
status = "disabled";
};
+ mdio: mdio@32000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x32000 0x8>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+ };
+
+ mdio-mux@32000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x32000 0x4>;
+ mux-mask = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio>;
+
+ mdio_int: mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,ns-bx-usb3-phy";
+ reg = <0x10>;
+ usb3-dmp-syscon = <&usb3_dmp>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ mdio_ext: mdio@200 {
+ reg = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@@ -520,13 +557,8 @@
};
};
- usb3_phy: usb3-phy@104000 {
- compatible = "brcm,ns-bx-usb3-phy";
- reg = <0x104000 0x1000>,
- <0x032000 0x1000>;
- reg-names = "dmp", "ccb-mii";
- #phy-cells = <0>;
- status = "disabled";
+ usb3_dmp: syscon@104000 {
+ reg = <0x104000 0x1000>;
};
};
diff --git a/dts/src/arm/bcm2711-rpi-4-b.dts b/dts/src/arm/bcm2711-rpi-4-b.dts
index 72ce80fbf2..631dd5baf6 100644
--- a/dts/src/arm/bcm2711-rpi-4-b.dts
+++ b/dts/src/arm/bcm2711-rpi-4-b.dts
@@ -3,6 +3,7 @@
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
@@ -26,11 +27,6 @@
};
};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
-
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
@@ -56,6 +52,10 @@
};
};
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+};
+
&ddc0 {
status = "okay";
};
@@ -178,23 +178,6 @@
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* EMMC2 is used to drive the SD card */
&emmc2 {
vqmmc-supply = <&sd_io_1v8_reg>;
@@ -237,13 +220,6 @@
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
@@ -260,3 +236,7 @@
&vec {
status = "disabled";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/bcm2711-rpi-cm4-io.dts b/dts/src/arm/bcm2711-rpi-cm4-io.dts
new file mode 100644
index 0000000000..19600b629b
--- /dev/null
+++ b/dts/src/arm/bcm2711-rpi-cm4-io.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711-rpi-cm4.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+ model = "Raspberry Pi Compute Module 4 IO Board";
+
+ leds {
+ led-act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
+&gpio {
+ /*
+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "RGMII_MDIO",
+ "RGMIO_MDC",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ /* Shared with SPI flash */
+ "PWM0_MISO",
+ "PWM1_MOSI",
+ "STATUS_LED_G_CLK",
+ "SPIFLASH_CE_N",
+ "SDA0",
+ "SCL0",
+ "RGMII_RXCLK",
+ "RGMII_RXCTL",
+ "RGMII_RXD0",
+ "RGMII_RXD1",
+ "RGMII_RXD2",
+ "RGMII_RXD3",
+ "RGMII_TXCLK",
+ "RGMII_TXCTL",
+ "RGMII_TXD0",
+ "RGMII_TXD1",
+ "RGMII_TXD2",
+ "RGMII_TXD3";
+};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi1 {
+ status = "okay";
+};
+
+&genet {
+ status = "okay";
+};
+
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
+&pixelvalve2 {
+ status = "okay";
+};
+
+&pixelvalve4 {
+ status = "okay";
+};
+
+&vc4 {
+ status = "okay";
+};
+
+&vec {
+ status = "disabled";
+};
diff --git a/dts/src/arm/bcm2711-rpi-cm4.dtsi b/dts/src/arm/bcm2711-rpi-cm4.dtsi
new file mode 100644
index 0000000000..a2954d466a
--- /dev/null
+++ b/dts/src/arm/bcm2711-rpi-cm4.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711.dtsi"
+#include "bcm2711-rpi.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
+
+/ {
+ compatible = "raspberrypi,4-compute-module", "brcm,bcm2711";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ sd_io_1v8_reg: sd_io_1v8_reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ status = "okay";
+ };
+
+ sd_vcc_reg: sd_vcc_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+};
+
+/* EMMC2 is used to drive the eMMC */
+&emmc2 {
+ bus-width = <8>;
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ vmmc-supply = <&sd_vcc_reg>;
+ broken-cd;
+ /* Even the IP block is limited to 100 MHz
+ * this provides a throughput gain
+ */
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "ANT1",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "ANT2";
+
+ ant1: ant1-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ /* internal antenna enabled */
+ output-high;
+ line-name = "ant1";
+ };
+
+ ant2: ant2-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ /* external antenna disabled */
+ output-low;
+ line-name = "ant2";
+ };
+};
+
+&genet {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+&genet_mdio {
+ phy1: ethernet-phy@0 {
+ /* No PHY interrupt */
+ reg = <0x0>;
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+ uart-has-rtscts;
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/bcm2835-rpi-zero-w.dts b/dts/src/arm/bcm2835-rpi-zero-w.dts
index 33b2b77aa4..243236bc1e 100644
--- a/dts/src/arm/bcm2835-rpi-zero-w.dts
+++ b/dts/src/arm/bcm2835-rpi-zero-w.dts
@@ -7,6 +7,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
@@ -27,11 +28,10 @@
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
&gpio {
@@ -110,19 +110,7 @@
};
&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
- bus-width = <4>;
- mmc-pwrseq = <&wifi_pwrseq>;
- non-removable;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
};
&sdhost {
@@ -135,13 +123,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
- };
};
&uart1 {
@@ -149,3 +130,7 @@
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/bcm2837-rpi-3-a-plus.dts b/dts/src/arm/bcm2837-rpi-3-a-plus.dts
index 77099a7871..d73daf5bff 100644
--- a/dts/src/arm/bcm2837-rpi-3-a-plus.dts
+++ b/dts/src/arm/bcm2837-rpi-3-a-plus.dts
@@ -3,6 +3,7 @@
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
@@ -130,28 +131,6 @@
status = "okay";
};
-/*
- * SDHCI is used to control the SDIO for wireless
- *
- * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
- * by a single GPIO. We can't give GPIO control to one of the drivers,
- * otherwise the other part would get unexpectedly disturbed.
- */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@@ -160,16 +139,15 @@
bus-width = <4>;
};
-/* uart0 communicates with the BT module */
+/* uart0 communicates with the BT module
+ *
+ * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
+ * by a single GPIO. We can't give GPIO control to one of the drivers,
+ * otherwise the other part would get unexpectedly disturbed.
+ */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- };
};
/* uart1 is mapped to the pin header */
diff --git a/dts/src/arm/bcm2837-rpi-3-b-plus.dts b/dts/src/arm/bcm2837-rpi-3-b-plus.dts
index 61010266ca..e12938baaf 100644
--- a/dts/src/arm/bcm2837-rpi-3-b-plus.dts
+++ b/dts/src/arm/bcm2837-rpi-3-b-plus.dts
@@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
@@ -31,11 +32,10 @@
linux,default-trigger = "default-on";
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@@ -137,23 +137,6 @@
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@@ -166,13 +149,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
@@ -181,3 +157,7 @@
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/bcm2837-rpi-3-b.dts b/dts/src/arm/bcm2837-rpi-3-b.dts
index dd4a486040..42b5383b55 100644
--- a/dts/src/arm/bcm2837-rpi-3-b.dts
+++ b/dts/src/arm/bcm2837-rpi-3-b.dts
@@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@@ -24,11 +25,10 @@
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
+};
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
- };
+&bt {
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@@ -134,13 +134,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <2000000>;
- shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
- };
};
/* uart1 is mapped to the pin header */
@@ -150,23 +143,6 @@
status = "okay";
};
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_gpio34>;
- status = "okay";
- bus-width = <4>;
- non-removable;
- mmc-pwrseq = <&wifi_pwrseq>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@@ -174,3 +150,7 @@
status = "okay";
bus-width = <4>;
};
+
+&wifi_pwrseq {
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/bcm283x-rpi-wifi-bt.dtsi b/dts/src/arm/bcm283x-rpi-wifi-bt.dtsi
new file mode 100644
index 0000000000..0b64cc1994
--- /dev/null
+++ b/dts/src/arm/bcm283x-rpi-wifi-bt.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ };
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ status = "okay";
+
+ bt: bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ };
+};
diff --git a/dts/src/arm/bcm4708-netgear-r6250.dts b/dts/src/arm/bcm4708-netgear-r6250.dts
index 61c7b13760..43a5d675dd 100644
--- a/dts/src/arm/bcm4708-netgear-r6250.dts
+++ b/dts/src/arm/bcm4708-netgear-r6250.dts
@@ -20,7 +20,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
@@ -94,3 +94,40 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
index d857751ec5..d00495a8b6 100644
--- a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
@@ -117,3 +117,40 @@
};
};
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm4709-asus-rt-ac87u.dts b/dts/src/arm/bcm4709-asus-rt-ac87u.dts
index 6c6bb7b17d..7546c8d07b 100644
--- a/dts/src/arm/bcm4709-asus-rt-ac87u.dts
+++ b/dts/src/arm/bcm4709-asus-rt-ac87u.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
diff --git a/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
index d29e7f80ea..beae9eab9c 100644
--- a/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
diff --git a/dts/src/arm/bcm4709-linksys-ea9200.dts b/dts/src/arm/bcm4709-linksys-ea9200.dts
index 9b6887d477..7879f7d7d9 100644
--- a/dts/src/arm/bcm4709-linksys-ea9200.dts
+++ b/dts/src/arm/bcm4709-linksys-ea9200.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
diff --git a/dts/src/arm/bcm4709-netgear-r7000.dts b/dts/src/arm/bcm4709-netgear-r7000.dts
index 7989a53597..56d309dbc6 100644
--- a/dts/src/arm/bcm4709-netgear-r7000.dts
+++ b/dts/src/arm/bcm4709-netgear-r7000.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
diff --git a/dts/src/arm/bcm4709-netgear-r8000.dts b/dts/src/arm/bcm4709-netgear-r8000.dts
index 87b655be67..89f992af61 100644
--- a/dts/src/arm/bcm4709-netgear-r8000.dts
+++ b/dts/src/arm/bcm4709-netgear-r8000.dts
@@ -30,7 +30,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
@@ -187,3 +187,45 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&gmac2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
index f806be5da7..c2a266a439 100644
--- a/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
+++ b/dts/src/arm/bcm4709-tplink-archer-c9-v1.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/dts/src/arm/bcm47094-asus-rt-ac88u.dts b/dts/src/arm/bcm47094-asus-rt-ac88u.dts
new file mode 100644
index 0000000000..448060561c
--- /dev/null
+++ b/dts/src/arm/bcm47094-asus-rt-ac88u.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Asus RT-AC88U";
+
+ chosen {
+ bootargs = "earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
+ };
+
+ nvram@1c080000 {
+ compatible = "brcm,nvram";
+ reg = <0x1c080000 0x00180000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "white:power";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ wan-red {
+ label = "red:wan";
+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "white:lan";
+ gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2 {
+ label = "white:usb2";
+ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ehci_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ usb3 {
+ label = "white:usb3";
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ehci_port1>, <&xhci_port1>;
+ linux,default-trigger = "usbport";
+ };
+
+ wps {
+ label = "white:wps";
+ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+ };
+
+ reset {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi {
+ label = "Wi-Fi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led {
+ label = "Backlight";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
+ status = "okay";
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ sw0_p5: port@5 {
+ reg = <5>;
+ label = "extsw";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ ethernet = <&gmac1>;
+ label = "cpu";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ ethernet = <&gmac2>;
+ label = "cpu";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&nandcs {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "nvram";
+ reg = <0x00080000 0x00180000>;
+ };
+
+ partition@200000 {
+ label = "firmware";
+ reg = <0x00200000 0x07e00000>;
+ compatible = "brcm,trx";
+ };
+ };
+};
diff --git a/dts/src/arm/bcm47094-dlink-dir-885l.dts b/dts/src/arm/bcm47094-dlink-dir-885l.dts
index a6e2aeb286..60bfd52ee6 100644
--- a/dts/src/arm/bcm47094-dlink-dir-885l.dts
+++ b/dts/src/arm/bcm47094-dlink-dir-885l.dts
@@ -118,3 +118,45 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&gmac2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm47094-linksys-panamera.dts b/dts/src/arm/bcm47094-linksys-panamera.dts
index 05d4f29317..9bef6b9bfa 100644
--- a/dts/src/arm/bcm47094-linksys-panamera.dts
+++ b/dts/src/arm/bcm47094-linksys-panamera.dts
@@ -129,7 +129,7 @@
};
};
- mdio-bus-mux@18003000 {
+ mdio-mux@18003000 {
/* BIT(9) = 1 => external mdio */
mdio@200 {
diff --git a/dts/src/arm/bcm47094-luxul-abr-4500.dts b/dts/src/arm/bcm47094-luxul-abr-4500.dts
index 4b8117f32d..b51a0ee7e5 100644
--- a/dts/src/arm/bcm47094-luxul-abr-4500.dts
+++ b/dts/src/arm/bcm47094-luxul-abr-4500.dts
@@ -68,3 +68,40 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm47094-luxul-xbr-4500.dts b/dts/src/arm/bcm47094-luxul-xbr-4500.dts
index 5fecce0422..b959a9504e 100644
--- a/dts/src/arm/bcm47094-luxul-xbr-4500.dts
+++ b/dts/src/arm/bcm47094-luxul-xbr-4500.dts
@@ -68,3 +68,40 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm47094-luxul-xwc-2000.dts b/dts/src/arm/bcm47094-luxul-xwc-2000.dts
index 452b8d0ab1..b0d8a68814 100644
--- a/dts/src/arm/bcm47094-luxul-xwc-2000.dts
+++ b/dts/src/arm/bcm47094-luxul-xwc-2000.dts
@@ -16,7 +16,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
diff --git a/dts/src/arm/bcm47189-tenda-ac9.dts b/dts/src/arm/bcm47189-tenda-ac9.dts
index 049cdfd927..07eb3a8287 100644
--- a/dts/src/arm/bcm47189-tenda-ac9.dts
+++ b/dts/src/arm/bcm47189-tenda-ac9.dts
@@ -105,3 +105,40 @@
};
};
};
+
+&switch {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/dts/src/arm/bcm53016-meraki-mr32.dts b/dts/src/arm/bcm53016-meraki-mr32.dts
index 3b978dc899..64f973e1ef 100644
--- a/dts/src/arm/bcm53016-meraki-mr32.dts
+++ b/dts/src/arm/bcm53016-meraki-mr32.dts
@@ -20,7 +20,7 @@
bootargs = " console=ttyS0,115200n8 earlycon";
};
- memory {
+ memory@0 {
reg = <0x00000000 0x08000000>;
device_type = "memory";
};
@@ -110,6 +110,12 @@
reg = <0x50>;
pagesize = <32>;
read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac_address: mac-address@66 {
+ reg = <0x66 0x6>;
+ };
};
};
};
@@ -133,6 +139,11 @@
*/
};
+&gmac0 {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&mac_address>;
+};
+
&gmac1 {
status = "disabled";
};
@@ -195,3 +206,25 @@
};
};
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index f92089290c..d4f355015e 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -19,7 +19,7 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
- chipcommonA@18000000 {
+ chipcommon-a-bus@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x00001000>;
#address-cells = <1>;
@@ -44,7 +44,7 @@
};
};
- mpcore@19000000 {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -369,8 +369,8 @@
#address-cells = <1>;
};
- mdio-bus-mux@18003000 {
- compatible = "mdio-mux-mmioreg";
+ mdio-mux@18003000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
#size-cells = <0>;
@@ -415,7 +415,7 @@
status = "disabled";
};
- dmu@1800c000 {
+ dmu-bus@1800c000 {
compatible = "simple-bus";
ranges = <0 0x1800c000 0x1000>;
#address-cells = <1>;
diff --git a/dts/src/arm/bcm53573.dtsi b/dts/src/arm/bcm53573.dtsi
index 51546fccc6..3f03a381db 100644
--- a/dts/src/arm/bcm53573.dtsi
+++ b/dts/src/arm/bcm53573.dtsi
@@ -180,6 +180,24 @@
gmac0: ethernet@5000 {
reg = <0x5000 0x1000>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch: switch@1e {
+ compatible = "brcm,bcm53125";
+ reg = <0x1e>;
+
+ status = "disabled";
+
+ /* ports are defined in board DTS */
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
};
gmac1: ethernet@b000 {
diff --git a/dts/src/arm/bcm94708.dts b/dts/src/arm/bcm94708.dts
index 3d13e46c69..d9eb2040b9 100644
--- a/dts/src/arm/bcm94708.dts
+++ b/dts/src/arm/bcm94708.dts
@@ -38,7 +38,7 @@
model = "NorthStar SVK (BCM94708)";
compatible = "brcm,bcm94708", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/dts/src/arm/bcm94709.dts b/dts/src/arm/bcm94709.dts
index 5017b7b259..618c812eef 100644
--- a/dts/src/arm/bcm94709.dts
+++ b/dts/src/arm/bcm94709.dts
@@ -38,7 +38,7 @@
model = "NorthStar SVK (BCM94709)";
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/dts/src/arm/bcm958522er.dts b/dts/src/arm/bcm958522er.dts
index 1f73885ec2..60376b62cd 100644
--- a/dts/src/arm/bcm958522er.dts
+++ b/dts/src/arm/bcm958522er.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958522ER)";
- compatible = "brcm,bcm58522", "brcm,nsp";
+ compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -134,6 +134,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958525er.dts b/dts/src/arm/bcm958525er.dts
index b6b9ca8b09..8eeb319f5b 100644
--- a/dts/src/arm/bcm958525er.dts
+++ b/dts/src/arm/bcm958525er.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958525ER)";
- compatible = "brcm,bcm58525", "brcm,nsp";
+ compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -134,6 +134,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958525xmc.dts b/dts/src/arm/bcm958525xmc.dts
index ecf426f6ad..dc86d5a912 100644
--- a/dts/src/arm/bcm958525xmc.dts
+++ b/dts/src/arm/bcm958525xmc.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus XMC (BCM958525xmc)";
- compatible = "brcm,bcm58525", "brcm,nsp";
+ compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -150,6 +150,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958622hr.dts b/dts/src/arm/bcm958622hr.dts
index 8ca18da981..c457e53d88 100644
--- a/dts/src/arm/bcm958622hr.dts
+++ b/dts/src/arm/bcm958622hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958622HR)";
- compatible = "brcm,bcm58622", "brcm,nsp";
+ compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -138,6 +138,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958623hr.dts b/dts/src/arm/bcm958623hr.dts
index 9747378db5..c06871915a 100644
--- a/dts/src/arm/bcm958623hr.dts
+++ b/dts/src/arm/bcm958623hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958623HR)";
- compatible = "brcm,bcm58623", "brcm,nsp";
+ compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -142,6 +142,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958625-meraki-alamo.dtsi b/dts/src/arm/bcm958625-meraki-alamo.dtsi
new file mode 100644
index 0000000000..102acd85fa
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-alamo.dtsi
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+/ {
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ /* green:wan1-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ /* green:wan1-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ /* green:wan2-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ /* green:wan2-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ /* amber:power */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led-5 {
+ /* white:status */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&axi {
+ mdio-mux@3f1c0 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x3f1c0 0x4>;
+ mux-mask = <0x2000>;
+ mdio-parent-bus = <&mdio_ext>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port6: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port7: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port8: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port9: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port10: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ reg = <0x10>;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ethernet = <&sgmii1>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ phy-handle = <&phy_port6>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan9";
+ phy-handle = <&phy_port7>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan10";
+ phy-handle = <&phy_port8>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan11";
+ phy-handle = <&phy_port9>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan12";
+ phy-handle = <&phy_port10>;
+ };
+ };
+ };
+ };
+
+ mdio-mii@2000 {
+ reg = <0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port2: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port4: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port5: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ reg = <0x10>;
+ dsa,member = <2 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ethernet = <&sgmii0>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ phy-handle = <&phy_port1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ phy-handle = <&phy_port2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan5";
+ phy-handle = <&phy_port3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan6";
+ phy-handle = <&phy_port4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan7";
+ phy-handle = <&phy_port5>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+ dsa,member = <0 0>;
+
+ ports {
+ port@0 {
+ label = "wan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "wan2";
+ reg = <1>;
+ };
+
+ sgmii0: port@4 {
+ label = "sw0";
+ reg = <4>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ sgmii1: port@5 {
+ label = "sw1";
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm958625-meraki-kingpin.dtsi b/dts/src/arm/bcm958625-meraki-kingpin.dtsi
new file mode 100644
index 0000000000..7c487c74fd
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-kingpin.dtsi
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+/ {
+
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ /* green:lan1-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ /* green:lan1-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ /* green:lan2-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ /* green:lan2-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ /* green:lan3-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <4>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ led-5 {
+ /* green:lan3-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <5>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ led-6 {
+ /* green:lan4-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ };
+
+ led-7 {
+ /* green:lan4-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <7>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ led-8 {
+ /* green:wan-left */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <8>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
+ };
+
+ led-9 {
+ /* green:wan-right */
+ function = LED_FUNCTION_ACTIVITY;
+ function-enumerator = <9>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
+ };
+
+ led-a {
+ /* amber:power */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-b {
+ /* white:status */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+
+ ports {
+ port@0 {
+ label = "lan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "lan2";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan3";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan4";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "wan";
+ reg = <4>;
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx64-a0.dts b/dts/src/arm/bcm958625-meraki-mx64-a0.dts
new file mode 100644
index 0000000000..9944566c11
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx64-a0.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+#include "bcm-nsp-ax.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64(A0)";
+ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx64.dts b/dts/src/arm/bcm958625-meraki-mx64.dts
new file mode 100644
index 0000000000..06939438e8
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx64.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64";
+ compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx64w-a0.dts b/dts/src/arm/bcm958625-meraki-mx64w-a0.dts
new file mode 100644
index 0000000000..112fddb1ee
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx64w-a0.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+#include "bcm-nsp-ax.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64W(A0)";
+ compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx64w.dts b/dts/src/arm/bcm958625-meraki-mx64w.dts
new file mode 100644
index 0000000000..de2e367c3e
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx64w.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64W";
+ compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx65.dts b/dts/src/arm/bcm958625-meraki-mx65.dts
new file mode 100644
index 0000000000..d1b684dcdb
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx65.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65";
+ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx65w.dts b/dts/src/arm/bcm958625-meraki-mx65w.dts
new file mode 100644
index 0000000000..a2165aba36
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx65w.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65W.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65W";
+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625-meraki-mx6x-common.dtsi b/dts/src/arm/bcm958625-meraki-mx6x-common.dtsi
new file mode 100644
index 0000000000..6519b7c61a
--- /dev/null
+++ b/dts/src/arm/bcm958625-meraki-mx6x-common.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm-nsp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm 1 50000>;
+ max-brightness = <255>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm 2 50000>;
+ max-brightness = <255>;
+ };
+
+ led-3 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm 3 50000>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&amac2 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
+ };
+};
+
+&nand_controller {
+ nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "shmoo";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "bootkernel1";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@400000 {
+ label = "nvram";
+ reg = <0x400000 0x100000>;
+ };
+
+ partition@500000 {
+ label = "bootkernel2";
+ reg = <0x500000 0x300000>;
+ };
+
+ partition@800000 {
+ label = "ubi";
+ reg = <0x800000 0x3f700000>;
+ };
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_leds>;
+
+ pwm_leds: pwm_leds {
+ function = "pwm";
+ groups = "pwm1_grp", "pwm2_grp", "pwm3_grp";
+ };
+};
+
+&pwm {
+ status = "okay";
+ #pwm-cells = <2>;
+};
+
+&uart0 {
+ clock-frequency = <62500000>;
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm958625hr.dts b/dts/src/arm/bcm958625hr.dts
index 0f92b773af..b22fc6624a 100644
--- a/dts/src/arm/bcm958625hr.dts
+++ b/dts/src/arm/bcm958625hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958625HR)";
- compatible = "brcm,bcm58625", "brcm,nsp";
+ compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -149,6 +149,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts
index 9e984ca0e6..0183f8965a 100644
--- a/dts/src/arm/bcm958625k.dts
+++ b/dts/src/arm/bcm958625k.dts
@@ -36,7 +36,7 @@
/ {
model = "NorthStar Plus SVK (BCM958625K)";
- compatible = "brcm,bcm58625", "brcm,nsp";
+ compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -153,6 +153,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/bcm988312hr.dts b/dts/src/arm/bcm988312hr.dts
index 5475dab818..007e347159 100644
--- a/dts/src/arm/bcm988312hr.dts
+++ b/dts/src/arm/bcm988312hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM988312HR)";
- compatible = "brcm,bcm88312", "brcm,nsp";
+ compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@@ -58,6 +58,10 @@
/* USB 3 support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
@@ -134,6 +138,7 @@
};
&qspi {
+ status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index dfc1ef8ef6..6b485cbed8 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -965,6 +965,25 @@
};
};
+ target-module@59000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x59000020 0x4>;
+ reg-names = "rev";
+ clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000000 0x1000>;
+
+ bb2d: gpu@0 {
+ compatible = "vivante,gc";
+ reg = <0x0 0x700>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>;
+ clock-names = "core";
+ };
+ };
+
aes1_target: target-module@4b500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b500080 0x4>,
diff --git a/dts/src/arm/e60k02.dtsi b/dts/src/arm/e60k02.dtsi
index cfb239d518..1a49f15f2d 100644
--- a/dts/src/arm/e60k02.dtsi
+++ b/dts/src/arm/e60k02.dtsi
@@ -41,7 +41,7 @@
leds: leds {
compatible = "gpio-leds";
- on {
+ led {
label = "e60k02:white:on";
gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
diff --git a/dts/src/arm/e70k02.dtsi b/dts/src/arm/e70k02.dtsi
new file mode 100644
index 0000000000..156de653f2
--- /dev/null
+++ b/dts/src/arm/e70k02.dtsi
@@ -0,0 +1,320 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * and
+ * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
+ *
+ * Netronix E70K02 board common.
+ * This board is equipped with different SoCs and
+ * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
+ * the Tolino Shine 3 (with i.MX6SL)
+ */
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc3;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ cover {
+ label = "Cover";
+ gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+
+ pageup {
+ label = "PageUp";
+ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PAGEUP>;
+ };
+
+ pagedown {
+ label = "PageDown";
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PAGEDOWN>;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led {
+ label = "e70k02:white:on";
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lm3630a: backlight@36 {
+ reg = <0x36>;
+ compatible = "ti,lm3630a";
+ enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0>;
+ label = "backlight_warm";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ label = "backlight_cold";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+ };
+
+ /* TODO: KX122 acceleration sensor a 0x1e */
+
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ /* TODO: CYTTSP5 touch controller at 0x24 */
+
+ /* TODO: SY7636 PMIC for E Ink at 0x62 */
+
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ ricoh619: pmic@32 {
+ compatible = "ricoh,rc5t619";
+ reg = <0x32>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+ system-power-controller;
+
+ regulators {
+ dcdc1_reg: DCDC1 {
+ regulator-name = "DCDC1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <900000>;
+ regulator-suspend-min-microvolt = <900000>;
+ };
+ };
+
+ /* Core3_3V3 */
+ dcdc2_reg: DCDC2 {
+ regulator-name = "DCDC2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3300000>;
+ regulator-suspend-min-microvolt = <3300000>;
+ };
+ };
+
+ dcdc3_reg: DCDC3 {
+ regulator-name = "DCDC3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V2 */
+ dcdc4_reg: DCDC4 {
+ regulator-name = "DCDC4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V8 */
+ dcdc5_reg: DCDC5 {
+ regulator-name = "DCDC5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1700000>;
+ regulator-suspend-min-microvolt = <1700000>;
+ };
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-boot-on;
+ };
+
+ /* Core1_3V3 */
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3000000>;
+ regulator-suspend-min-microvolt = <3000000>;
+ };
+ };
+
+ /* Core5_1V2 */
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-boot-on;
+ };
+
+ /* SPD_3V3 */
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* DDR_0V6 */
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* VDD_PWM */
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-boot-on;
+ };
+
+ /* ldo_1v8 */
+ ldo8_reg: LDO8 {
+ regulator-name = "LDO8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "LDO9";
+ regulator-boot-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "LDO10";
+ regulator-boot-on;
+ };
+
+ ldortc1_reg: LDORTC1 {
+ regulator-name = "LDORTC1";
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&snvs_rtc {
+ /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc3 {
+ vmmc-supply = <&reg_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
diff --git a/dts/src/arm/emev2-kzm9d.dts b/dts/src/arm/emev2-kzm9d.dts
index 0a27f034dd..89495dd373 100644
--- a/dts/src/arm/emev2-kzm9d.dts
+++ b/dts/src/arm/emev2-kzm9d.dts
@@ -80,7 +80,7 @@
};
ethernet@20000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan9221", "smsc,lan9115";
reg = <0x20000000 0x10000>;
phy-mode = "mii";
interrupt-parent = <&gpio0>;
diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts
index f6ba5e4260..5f7f8fedfb 100644
--- a/dts/src/arm/exynos3250-rinato.dts
+++ b/dts/src/arm/exynos3250-rinato.dts
@@ -19,6 +19,7 @@
/ {
model = "Samsung Rinato board";
compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
+ chassis-type = "watch";
aliases {
i2c7 = &i2c_max77836;
diff --git a/dts/src/arm/exynos4210-i9100.dts b/dts/src/arm/exynos4210-i9100.dts
index 5592217680..19bb7dc98b 100644
--- a/dts/src/arm/exynos4210-i9100.dts
+++ b/dts/src/arm/exynos4210-i9100.dts
@@ -18,6 +18,7 @@
/ {
model = "Samsung Galaxy S2 (GT-I9100)";
compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4";
+ chassis-type = "handset";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos4210-origen.dts b/dts/src/arm/exynos4210-origen.dts
index 1c53941525..435fda60e8 100644
--- a/dts/src/arm/exynos4210-origen.dts
+++ b/dts/src/arm/exynos4210-origen.dts
@@ -206,74 +206,74 @@
ldo4_reg: LDO4 {
regulator-name = "VDD_RTC_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "VDD_AUD_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
ldo8_reg: LDO8 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
ldo9_reg: LDO9 {
regulator-name = "DVDD_SWB_2.8V";
regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "VDD_PLL_1.1V";
regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo11_reg: LDO11 {
regulator-name = "VDD_AUD_3V";
regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
};
ldo14_reg: LDO14 {
regulator-name = "AVDD18_SWB_1.8V";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo17_reg: LDO17 {
regulator-name = "VDD_SWB_3.3V";
regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo21_reg: LDO21 {
regulator-name = "VDD_MIF_1.2V";
regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VDD_ARM_1.2V";
regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
@@ -281,7 +281,7 @@
buck2_reg: BUCK2 {
regulator-name = "VDD_INT_1.1V";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts
index 3eb8df3192..9c4ff75213 100644
--- a/dts/src/arm/exynos4210-trats.dts
+++ b/dts/src/arm/exynos4210-trats.dts
@@ -16,6 +16,7 @@
/ {
model = "Samsung Trats based on Exynos4210";
compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
+ chassis-type = "handset";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos4210-universal_c210.dts b/dts/src/arm/exynos4210-universal_c210.dts
index f052853244..9f93e7464a 100644
--- a/dts/src/arm/exynos4210-universal_c210.dts
+++ b/dts/src/arm/exynos4210-universal_c210.dts
@@ -16,6 +16,7 @@
/ {
model = "Samsung Universal C210 based on Exynos4210 rev0";
compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
+ chassis-type = "handset";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos4412-i9300.dts b/dts/src/arm/exynos4412-i9300.dts
index 07fbcf845c..61aca5798f 100644
--- a/dts/src/arm/exynos4412-i9300.dts
+++ b/dts/src/arm/exynos4412-i9300.dts
@@ -12,6 +12,7 @@
/ {
model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412";
compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+ chassis-type = "handset";
/* bootargs are passed in by bootloader */
diff --git a/dts/src/arm/exynos4412-i9305.dts b/dts/src/arm/exynos4412-i9305.dts
index 6bc3d897f4..77083f1a82 100644
--- a/dts/src/arm/exynos4412-i9305.dts
+++ b/dts/src/arm/exynos4412-i9305.dts
@@ -5,6 +5,7 @@
/ {
model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412";
compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+ chassis-type = "handset";
/* bootargs are passed in by bootloader */
diff --git a/dts/src/arm/exynos4412-n710x.dts b/dts/src/arm/exynos4412-n710x.dts
index 2c79214260..9ae05b0d68 100644
--- a/dts/src/arm/exynos4412-n710x.dts
+++ b/dts/src/arm/exynos4412-n710x.dts
@@ -5,6 +5,7 @@
/ {
compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412";
+ chassis-type = "handset";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts
index 5479ef09f9..e6aec5faca 100644
--- a/dts/src/arm/exynos4412-origen.dts
+++ b/dts/src/arm/exynos4412-origen.dts
@@ -382,7 +382,7 @@
buck1_reg: BUCK1 {
regulator-name = "VDD_MIF";
regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -391,7 +391,7 @@
buck2_reg: BUCK2 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -400,7 +400,7 @@
buck3_reg: BUCK3 {
regulator-name = "VDD_INT";
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -409,7 +409,7 @@
buck4_reg: BUCK4 {
regulator-name = "VDD_G3D";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -418,7 +418,7 @@
buck5_reg: BUCK5 {
regulator-name = "VDD_M12";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -427,7 +427,7 @@
buck6_reg: BUCK6 {
regulator-name = "VDD12_5M";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -436,7 +436,7 @@
buck9_reg: BUCK9 {
regulator-name = "VDDF28_EMMC";
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
diff --git a/dts/src/arm/exynos4412-p4note-n8010.dts b/dts/src/arm/exynos4412-p4note-n8010.dts
index 9f559425bd..0932ec5866 100644
--- a/dts/src/arm/exynos4412-p4note-n8010.dts
+++ b/dts/src/arm/exynos4412-p4note-n8010.dts
@@ -12,6 +12,7 @@
/ {
model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412";
compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4";
+ chassis-type = "tablet";
/* this is the base variant without any kind of modem */
};
diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts
index 7b447b6300..3c2d2a7836 100644
--- a/dts/src/arm/exynos4412-trats2.dts
+++ b/dts/src/arm/exynos4412-trats2.dts
@@ -15,6 +15,7 @@
/ {
model = "Samsung Trats 2 based on Exynos4412";
compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+ chassis-type = "handset";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts
index a771542e28..3583095fbb 100644
--- a/dts/src/arm/exynos5250-arndale.dts
+++ b/dts/src/arm/exynos5250-arndale.dts
@@ -240,9 +240,6 @@
vinl8-supply = <&buck8_reg>;
vinl9-supply = <&buck8_reg>;
- s5m8767,pmic-buck2-dvs-voltage = <1300000>;
- s5m8767,pmic-buck3-dvs-voltage = <1100000>;
- s5m8767,pmic-buck4-dvs-voltage = <1200000>;
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
<&gpd1 1 GPIO_ACTIVE_HIGH>,
<&gpd1 2 GPIO_ACTIVE_HIGH>;
diff --git a/dts/src/arm/exynos5250-snow-rev5.dts b/dts/src/arm/exynos5250-snow-rev5.dts
index 0822b778c0..f8ca61df69 100644
--- a/dts/src/arm/exynos5250-snow-rev5.dts
+++ b/dts/src/arm/exynos5250-snow-rev5.dts
@@ -14,6 +14,7 @@
model = "Google Snow Rev 5+";
compatible = "google,snow-rev5", "samsung,exynos5250",
"samsung,exynos5";
+ chassis-type = "laptop";
sound {
compatible = "google,snow-audio-max98090";
diff --git a/dts/src/arm/exynos5250-snow.dts b/dts/src/arm/exynos5250-snow.dts
index 9946dce54d..a630bc654a 100644
--- a/dts/src/arm/exynos5250-snow.dts
+++ b/dts/src/arm/exynos5250-snow.dts
@@ -12,6 +12,7 @@
model = "Google Snow";
compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250",
"samsung,exynos5";
+ chassis-type = "laptop";
sound {
compatible = "google,snow-audio-max98095";
diff --git a/dts/src/arm/exynos5250-spring.dts b/dts/src/arm/exynos5250-spring.dts
index fba1462b19..e0feedcf54 100644
--- a/dts/src/arm/exynos5250-spring.dts
+++ b/dts/src/arm/exynos5250-spring.dts
@@ -16,6 +16,7 @@
/ {
model = "Google Spring";
compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
+ chassis-type = "laptop";
memory@40000000 {
device_type = "memory";
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index 4ffa9253b5..139778928b 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -386,7 +386,6 @@
sata: sata@122f0000 {
compatible = "snps,dwc-ahci";
- samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index 315b3dc9c0..e76fb104db 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -26,6 +26,7 @@
"google,pit-rev7", "google,pit-rev6",
"google,pit", "google,peach","samsung,exynos5420",
"samsung,exynos5";
+ chassis-type = "laptop";
aliases {
/* Assign 20 so we don't get confused w/ builtin ones */
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index 0ce3443d39..77013ee586 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -24,6 +24,7 @@
"google,pi-rev11", "google,pi-rev10",
"google,pi", "google,peach", "samsung,exynos5800",
"samsung,exynos5";
+ chassis-type = "laptop";
aliases {
/* Assign 20 so we don't get confused w/ builtin ones */
diff --git a/dts/src/arm/gemini-dlink-dir-685.dts b/dts/src/arm/gemini-dlink-dir-685.dts
index c79a2a02dd..3961496642 100644
--- a/dts/src/arm/gemini-dlink-dir-685.dts
+++ b/dts/src/arm/gemini-dlink-dir-685.dts
@@ -439,24 +439,6 @@
pci@50000000 {
status = "okay";
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map =
- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
- <0x4800 0 0 2 &pci_intc 1>,
- <0x4800 0 0 3 &pci_intc 2>,
- <0x4800 0 0 4 &pci_intc 3>,
- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
- <0x5000 0 0 2 &pci_intc 2>,
- <0x5000 0 0 3 &pci_intc 3>,
- <0x5000 0 0 4 &pci_intc 0>,
- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
- <0x5800 0 0 2 &pci_intc 3>,
- <0x5800 0 0 3 &pci_intc 0>,
- <0x5800 0 0 4 &pci_intc 1>,
- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
- <0x6000 0 0 2 &pci_intc 0>,
- <0x6000 0 0 3 &pci_intc 1>,
- <0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
diff --git a/dts/src/arm/gemini-ns2502.dts b/dts/src/arm/gemini-ns2502.dts
new file mode 100644
index 0000000000..704abd212d
--- /dev/null
+++ b/dts/src/arm/gemini-ns2502.dts
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
+ * Device Tree file for Edimax NS 2502
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+
+/ {
+ model = "Edimax NS-2502";
+ compatible = "edimax,ns-2502", "cortina,gemini";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+ /* 128 MB */
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ aliases {
+ mdio-gpio0 = &mdio0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,19200n8";
+ stdout-path = &uart0;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ /* We lack the knowledge of necessary GPIO to achieve
+ * Gigabit
+ */
+ max-speed = <100>;
+ };
+ };
+};
+
+&ethernet {
+ status = "okay";
+ ethernet-port@0 {
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+};
+
+&flash {
+ status = "okay";
+ /* 8MB of flash */
+ reg = <0x30000000 0x00800000>;
+
+ pinctrl-names = "enabled", "disabled";
+ pinctrl-0 = <&pflash_default_pins>;
+ pinctrl-1 = <&pflash_disabled_pins>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "RedBoot";
+ reg = <0x00000000 0x00020000>;
+ };
+ partition@20000 {
+ label = "kernel";
+ reg = <0x00020000 0x00700000>;
+ };
+ partition@720000 {
+ label = "VCTL";
+ reg = <0x00720000 0x00020000>;
+ };
+ partition@740000 {
+ label = "CurConf";
+ reg = <0x00740000 0x000a0000>;
+ };
+ partition@7e0000 {
+ label = "FIS";
+ reg = <0x007e0000 0x00010000>;
+ };
+ };
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+};
+
+&ide0 {
+ status = "okay";
+};
+
+&ide1 {
+ status = "okay";
+};
+
+&sata {
+ cortina,gemini-ata-muxmode = <3>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+};
+
+&syscon {
+ pinctrl {
+ /*
+ * gpio0agrp cover line 0-4
+ * gpio0bgrp cover line 5
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0agrp", "gpio0bgrp", "gpio0hgrp";
+ };
+ };
+ pflash_disabled_pins: pinctrl-pflash-disabled {
+ mux {
+ function = "gpio0";
+ groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
+ "gpio0kgrp";
+ };
+ };
+ pinctrl-gmii {
+ mux {
+ function = "gmii";
+ groups = "gmii_gmac0_grp";
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/gemini-sl93512r.dts b/dts/src/arm/gemini-sl93512r.dts
index c78e55fd25..91c19e8ebf 100644
--- a/dts/src/arm/gemini-sl93512r.dts
+++ b/dts/src/arm/gemini-sl93512r.dts
@@ -256,24 +256,6 @@
pci@50000000 {
status = "okay";
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map =
- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
- <0x4800 0 0 2 &pci_intc 1>,
- <0x4800 0 0 3 &pci_intc 2>,
- <0x4800 0 0 4 &pci_intc 3>,
- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
- <0x5000 0 0 2 &pci_intc 2>,
- <0x5000 0 0 3 &pci_intc 3>,
- <0x5000 0 0 4 &pci_intc 0>,
- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
- <0x5800 0 0 2 &pci_intc 3>,
- <0x5800 0 0 3 &pci_intc 0>,
- <0x5800 0 0 4 &pci_intc 1>,
- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
- <0x6000 0 0 2 &pci_intc 0>,
- <0x6000 0 0 3 &pci_intc 1>,
- <0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
diff --git a/dts/src/arm/gemini-sq201.dts b/dts/src/arm/gemini-sq201.dts
index 1b64cc80b5..d0efd76695 100644
--- a/dts/src/arm/gemini-sq201.dts
+++ b/dts/src/arm/gemini-sq201.dts
@@ -252,24 +252,6 @@
pci@50000000 {
status = "okay";
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map =
- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
- <0x4800 0 0 2 &pci_intc 1>,
- <0x4800 0 0 3 &pci_intc 2>,
- <0x4800 0 0 4 &pci_intc 3>,
- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
- <0x5000 0 0 2 &pci_intc 2>,
- <0x5000 0 0 3 &pci_intc 3>,
- <0x5000 0 0 4 &pci_intc 0>,
- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
- <0x5800 0 0 2 &pci_intc 3>,
- <0x5800 0 0 3 &pci_intc 0>,
- <0x5800 0 0 4 &pci_intc 1>,
- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
- <0x6000 0 0 2 &pci_intc 0>,
- <0x6000 0 0 3 &pci_intc 1>,
- <0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
diff --git a/dts/src/arm/gemini-ssi1328.dts b/dts/src/arm/gemini-ssi1328.dts
new file mode 100644
index 0000000000..2b3e7db84f
--- /dev/null
+++ b/dts/src/arm/gemini-ssi1328.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
+ * Device Tree file for SSI 1328
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+
+/ {
+ model = "SSI 1328";
+ compatible = "ssi,1328", "cortina,gemini";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+ /* 128 MB */
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ aliases {
+ mdio-gpio0 = &mdio0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M";
+ stdout-path = &uart0;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LAN Marvell 88E1118 */
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ /* We lack the knowledge of necessary GPIO to achieve
+ * Gigabit
+ */
+ max-speed = <100>;
+ };
+ /* WAN ICPlus IP101A */
+ phy1: ethernet-phy@2 {
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ };
+};
+
+&ethernet {
+ status = "okay";
+ ethernet-port@0 {
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+ ethernet-port@1 {
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+};
+
+&flash {
+ status = "okay";
+ /* 32MB of flash */
+ reg = <0x30000000 0x03200000>;
+
+ pinctrl-names = "enabled", "disabled";
+ pinctrl-0 = <&pflash_default_pins>;
+ pinctrl-1 = <&pflash_disabled_pins>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0xfe0000 */
+ fis-index-block = <0x7F>;
+ };
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+};
+
+&ide0 {
+ status = "okay";
+};
+
+&ide1 {
+ status = "okay";
+};
+
+&sata {
+ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+};
+
+&syscon {
+ pinctrl {
+ /*
+ * gpio0agrp cover line 0-4
+ * gpio0bgrp cover line 5
+ */
+ gpio0_default_pins: pinctrl-gpio0 {
+ mux {
+ function = "gpio0";
+ groups = "gpio0agrp", "gpio0bgrp";
+ };
+ };
+ pflash_disabled_pins: pinctrl-pflash-disabled {
+ mux {
+ function = "gpio0";
+ groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
+ "gpio0kgrp";
+ };
+ };
+ pinctrl-gmii {
+ /* This platform use both the ethernet ports */
+ mux {
+ function = "gmii";
+ groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/gemini-wbd111.dts b/dts/src/arm/gemini-wbd111.dts
index 5602ba8f30..de3c4416b0 100644
--- a/dts/src/arm/gemini-wbd111.dts
+++ b/dts/src/arm/gemini-wbd111.dts
@@ -140,24 +140,6 @@
pci@50000000 {
status = "okay";
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map =
- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
- <0x4800 0 0 2 &pci_intc 1>,
- <0x4800 0 0 3 &pci_intc 2>,
- <0x4800 0 0 4 &pci_intc 3>,
- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
- <0x5000 0 0 2 &pci_intc 2>,
- <0x5000 0 0 3 &pci_intc 3>,
- <0x5000 0 0 4 &pci_intc 0>,
- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
- <0x5800 0 0 2 &pci_intc 3>,
- <0x5800 0 0 3 &pci_intc 0>,
- <0x5800 0 0 4 &pci_intc 1>,
- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
- <0x6000 0 0 2 &pci_intc 0>,
- <0x6000 0 0 3 &pci_intc 1>,
- <0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
diff --git a/dts/src/arm/gemini-wbd222.dts b/dts/src/arm/gemini-wbd222.dts
index a4a260c36d..e5ceaadbcc 100644
--- a/dts/src/arm/gemini-wbd222.dts
+++ b/dts/src/arm/gemini-wbd222.dts
@@ -151,24 +151,6 @@
pci@50000000 {
status = "okay";
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map =
- <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
- <0x4800 0 0 2 &pci_intc 1>,
- <0x4800 0 0 3 &pci_intc 2>,
- <0x4800 0 0 4 &pci_intc 3>,
- <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
- <0x5000 0 0 2 &pci_intc 2>,
- <0x5000 0 0 3 &pci_intc 3>,
- <0x5000 0 0 4 &pci_intc 0>,
- <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
- <0x5800 0 0 2 &pci_intc 3>,
- <0x5800 0 0 3 &pci_intc 0>,
- <0x5800 0 0 4 &pci_intc 1>,
- <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
- <0x6000 0 0 2 &pci_intc 0>,
- <0x6000 0 0 3 &pci_intc 1>,
- <0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
diff --git a/dts/src/arm/gemini.dtsi b/dts/src/arm/gemini.dtsi
index cc053af3c3..e836bd0818 100644
--- a/dts/src/arm/gemini.dtsi
+++ b/dts/src/arm/gemini.dtsi
@@ -16,7 +16,7 @@
compatible = "simple-bus";
interrupt-parent = <&intcon>;
- flash@30000000 {
+ flash: flash@30000000 {
compatible = "cortina,gemini-flash", "cfi-flash";
syscon = <&syscon>;
pinctrl-names = "default";
@@ -289,9 +289,28 @@
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
status = "disabled";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
+ <0x4800 0 0 2 &pci_intc 1>,
+ <0x4800 0 0 3 &pci_intc 2>,
+ <0x4800 0 0 4 &pci_intc 3>,
+ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
+ <0x5000 0 0 2 &pci_intc 2>,
+ <0x5000 0 0 3 &pci_intc 3>,
+ <0x5000 0 0 4 &pci_intc 0>,
+ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
+ <0x5800 0 0 2 &pci_intc 3>,
+ <0x5800 0 0 3 &pci_intc 0>,
+ <0x5800 0 0 4 &pci_intc 1>,
+ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
+ <0x6000 0 0 2 &pci_intc 0>,
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+
bus-range = <0x00 0xff>;
/* PCI ranges mappings */
ranges =
@@ -322,7 +341,7 @@
};
};
- ethernet@60000000 {
+ ethernet: ethernet@60000000 {
compatible = "cortina,gemini-ethernet";
reg = <0x60000000 0x4000>, /* Global registers, queue */
<0x60004000 0x2000>, /* V-bit */
@@ -365,7 +384,7 @@
clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
};
- ide@63000000 {
+ ide0: ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
@@ -378,7 +397,7 @@
#size-cells = <0>;
};
- ide@63400000 {
+ ide1: ide@63400000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
@@ -421,7 +440,7 @@
status = "disabled";
};
- usb@68000000 {
+ usb0: usb@68000000 {
compatible = "cortina,gemini-usb", "faraday,fotg210";
reg = <0x68000000 0x1000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
@@ -442,7 +461,7 @@
status = "disabled";
};
- usb@69000000 {
+ usb1: usb@69000000 {
compatible = "cortina,gemini-usb", "faraday,fotg210";
reg = <0x69000000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/imx6dl-alti6p.dts b/dts/src/arm/imx6dl-alti6p.dts
index 4329b372d8..e8325fd680 100644
--- a/dts/src/arm/imx6dl-alti6p.dts
+++ b/dts/src/arm/imx6dl-alti6p.dts
@@ -192,7 +192,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
diff --git a/dts/src/arm/imx6dl-b1x5v2.dtsi b/dts/src/arm/imx6dl-b1x5v2.dtsi
index a326a33150..f028b6a191 100644
--- a/dts/src/arm/imx6dl-b1x5v2.dtsi
+++ b/dts/src/arm/imx6dl-b1x5v2.dtsi
@@ -47,7 +47,6 @@
mpl3115a2: pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
- vcc-supply = <&reg_3v3_acm>;
/*
* The MPL3115 interrupts are connected to pin 22 and 23
diff --git a/dts/src/arm/imx6dl-prtrvt.dts b/dts/src/arm/imx6dl-prtrvt.dts
index 5ac84445e9..56bb1ca56a 100644
--- a/dts/src/arm/imx6dl-prtrvt.dts
+++ b/dts/src/arm/imx6dl-prtrvt.dts
@@ -67,11 +67,9 @@
ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>,
<&gpio5 11 GPIO_ACTIVE_LOW>;
vin-supply = <&reg_3v3>;
- vin-voltage-override = <3100000>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
- t5t-rmb-extra-byte-quirk;
status = "okay";
};
};
diff --git a/dts/src/arm/imx6dl-skov-revc-lt2.dts b/dts/src/arm/imx6dl-skov-revc-lt2.dts
index 667b8faa18..b12b5aabe7 100644
--- a/dts/src/arm/imx6dl-skov-revc-lt2.dts
+++ b/dts/src/arm/imx6dl-skov-revc-lt2.dts
@@ -6,6 +6,7 @@
#include "imx6dl.dtsi"
#include "imx6qdl-skov-cpu.dtsi"
#include "imx6qdl-skov-cpu-revc.dtsi"
+#include "imx6qdl-skov-revc-lt2.dtsi"
/ {
model = "SKOV IMX6 CPU SoloCore";
diff --git a/dts/src/arm/imx6dl-yapp4-common.dtsi b/dts/src/arm/imx6dl-yapp4-common.dtsi
index e5c4dc65fb..674af39c88 100644
--- a/dts/src/arm/imx6dl-yapp4-common.dtsi
+++ b/dts/src/arm/imx6dl-yapp4-common.dtsi
@@ -296,14 +296,6 @@
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
-
- chan@3 {
- chan-name = "W";
- led-cur = /bits/ 8 <0x0>;
- max-cur = /bits/ 8 <0x0>;
- reg = <3>;
- color = <LED_COLOR_ID_WHITE>;
- };
};
eeprom@57 {
diff --git a/dts/src/arm/imx6q-skov-revc-lt2.dts b/dts/src/arm/imx6q-skov-revc-lt2.dts
index f00add7b30..ff97d22eb0 100644
--- a/dts/src/arm/imx6q-skov-revc-lt2.dts
+++ b/dts/src/arm/imx6q-skov-revc-lt2.dts
@@ -6,6 +6,7 @@
#include "imx6q.dtsi"
#include "imx6qdl-skov-cpu.dtsi"
#include "imx6qdl-skov-cpu-revc.dtsi"
+#include "imx6qdl-skov-revc-lt2.dtsi"
/ {
model = "SKOV IMX6 CPU QuadCore";
diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi
index 30fa349f9d..ed2739e390 100644
--- a/dts/src/arm/imx6qdl-apalis.dtsi
+++ b/dts/src/arm/imx6qdl-apalis.dtsi
@@ -310,10 +310,10 @@
st,mod-12b = <1>;
/* internal ADC reference */
st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
+ /* ADC conversion time: 80 clocks */
st,sample-time = <4>;
- stmpe_touchscreen {
+ stmpe_touchscreen: stmpe-touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
@@ -330,10 +330,11 @@
st,touch-det-delay = <5>;
};
- stmpe_adc {
+ stmpe_adc: stmpe-adc {
compatible = "st,stmpe-adc";
/* forbid to use ADC channels 3-0 (touch) */
st,norequest-mask = <0x0F>;
+ #io-channel-cells = <1>;
};
};
};
diff --git a/dts/src/arm/imx6qdl-phytec-mira.dtsi b/dts/src/arm/imx6qdl-phytec-mira.dtsi
index 019938562a..120d6e997a 100644
--- a/dts/src/arm/imx6qdl-phytec-mira.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-mira.dtsi
@@ -145,8 +145,11 @@
};
&i2c1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "disabled";
@@ -185,8 +188,11 @@
};
&i2c2 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "disabled";
};
@@ -256,6 +262,7 @@
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
no-1-8-v;
+ disable-wp;
status = "disabled";
};
@@ -299,6 +306,20 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
@@ -306,10 +327,10 @@
>;
};
- pinctrl_i2c1: i2c1grp {
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
>;
};
diff --git a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi
index a80aa08a37..94b254bfd0 100644
--- a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi
@@ -78,8 +78,11 @@
};
&i2c3 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
@@ -259,6 +262,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
diff --git a/dts/src/arm/imx6qdl-skov-revc-lt2.dtsi b/dts/src/arm/imx6qdl-skov-revc-lt2.dtsi
new file mode 100644
index 0000000000..48c9ce051f
--- /dev/null
+++ b/dts/src/arm/imx6qdl-skov-revc-lt2.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright (C) 2021 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;
+ pwms = <&pwm2 0 20000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <17>;
+ default-brightness-level = <8>;
+ power-supply = <&reg_24v0>;
+ };
+
+ display {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "fsl,imx-parallel-display";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "logictechno,lttd800480070-l2rt";
+ backlight = <&backlight>;
+ power-supply = <&reg_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
+ };
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&iomuxc {
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58
+ >;
+ };
+
+ pinctrl_ipu1: ipu1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-tqma6.dtsi b/dts/src/arm/imx6qdl-tqma6.dtsi
index b18b83ac6a..51a3a5392c 100644
--- a/dts/src/arm/imx6qdl-tqma6.dtsi
+++ b/dts/src/arm/imx6qdl-tqma6.dtsi
@@ -20,7 +20,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
m25p80: flash@0 {
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index 89c342f3a7..f5de5def87 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -264,7 +264,7 @@
};
pcie: pcie@1ffc000 {
- compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6q-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
@@ -272,10 +272,9 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
+ <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
- num-viewport = <4>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
diff --git a/dts/src/arm/imx6qp-prtwd3.dts b/dts/src/arm/imx6qp-prtwd3.dts
index b92e0f2748..7648e8a020 100644
--- a/dts/src/arm/imx6qp-prtwd3.dts
+++ b/dts/src/arm/imx6qp-prtwd3.dts
@@ -123,7 +123,7 @@
};
&ecspi2 {
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
@@ -189,7 +189,7 @@
};
&ecspi3 {
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
diff --git a/dts/src/arm/imx6qp.dtsi b/dts/src/arm/imx6qp.dtsi
index b310f13a53..0503655138 100644
--- a/dts/src/arm/imx6qp.dtsi
+++ b/dts/src/arm/imx6qp.dtsi
@@ -110,5 +110,5 @@
};
&pcie {
- compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6qp-pcie";
};
diff --git a/dts/src/arm/imx6sl-tolino-vision5.dts b/dts/src/arm/imx6sl-tolino-vision5.dts
new file mode 100644
index 0000000000..ff6118df39
--- /dev/null
+++ b/dts/src/arm/imx6sl-tolino-vision5.dts
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Tolino Vision 5 ebook reader
+ *
+ * Name on mainboard is: 37NB-E70K0M+6A3
+ * Serials start with: E70K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Tolino Vision 5 ebook reader it is a i.MX6SL
+ *
+ * Copyright 2021 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+#include "e70k02.dtsi"
+
+/ {
+ model = "Tolino Vision 5";
+ compatible = "kobo,tolino-vision5", "fsl,imx6sl";
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */
+ MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x17059 /* HALL_EN */
+ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */
+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
+ MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
+ MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
+ MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
+ MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
+ MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
+ MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
+ MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
+ MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
+ MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
+ MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
+ MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
+ MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
+ MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
+ MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
+ MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
+ MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
+ MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
+ MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
+ MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
+ MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
+ MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x79
+ MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x79
+ MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x10059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */
+ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */
+ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x17059
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x170b9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x170f9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_sleep: usdhc1-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x10059
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x10059
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x10059
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x10059
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x10059
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x10059
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x10059
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x10059
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x10059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+&reg_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+&reg_vdd1p1 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&reg_arm {
+ vin-supply = <&dcdc3_reg>;
+};
+
+&reg_soc {
+ vin-supply = <&dcdc1_reg>;
+};
+
+&reg_pu {
+ vin-supply = <&dcdc1_reg>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index 997b96c1c4..c7d907c5c3 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -55,18 +55,16 @@
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 996000 1275000
- 792000 1175000
- 396000 975000
- >;
- fsl,soc-operating-points = <
+ <996000 1275000>,
+ <792000 1175000>,
+ <396000 975000>;
+ fsl,soc-operating-points =
/* ARM kHz SOC-PU uV */
- 996000 1225000
- 792000 1175000
- 396000 1175000
- >;
+ <996000 1225000>,
+ <792000 1175000>,
+ <396000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
diff --git a/dts/src/arm/imx6sll-kobo-librah2o.dts b/dts/src/arm/imx6sll-kobo-librah2o.dts
new file mode 100644
index 0000000000..a8b0e88064
--- /dev/null
+++ b/dts/src/arm/imx6sll-kobo-librah2o.dts
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Kobo Libra H2O ebook reader
+ *
+ * Name on mainboard is: 37NB-E70K0M+6A3
+ * Serials start with: E70K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Kobo Libra H2O ebook reader it is an i.MX6SLL
+ *
+ * Copyright 2021 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sll.dtsi"
+#include "e70k02.dtsi"
+
+/ {
+ model = "Kobo Libra H2O";
+ compatible = "kobo,librah2o", "fsl,imx6sll";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+ arm-supply = <&dcdc3_reg>;
+ soc-supply = <&dcdc1_reg>;
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */
+ MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */
+ MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79
+ MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79
+ MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79
+ MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79
+ MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79
+ MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79
+ MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79
+ MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79
+ MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79
+ MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79
+ MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79
+ MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79
+ MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79
+ MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79
+ MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79
+ MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79
+ MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79
+ MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79
+ MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79
+ MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79
+ MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79
+ MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x79
+ MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x79
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */
+ MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */
+ MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+ MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x17059
+ MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x17059
+ MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x17059
+ MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+ MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9
+ MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9
+ MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9
+ MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+ MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9
+ MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9
+ MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9
+ MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_sleep: usdhc1-sleepgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x10059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x10059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x10059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x10059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x10059
+ MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x10059
+ MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x10059
+ MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x10059
+ MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x10059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1
+ MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1
+ MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1
+ MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+&reg_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/dts/src/arm/imx6sll.dtsi b/dts/src/arm/imx6sll.dtsi
index 04f8d637a5..d4a000c3dd 100644
--- a/dts/src/arm/imx6sll.dtsi
+++ b/dts/src/arm/imx6sll.dtsi
@@ -51,20 +51,18 @@
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 996000 1275000
- 792000 1175000
- 396000 1075000
- 198000 975000
- >;
- fsl,soc-operating-points = <
+ <996000 1275000>,
+ <792000 1175000>,
+ <396000 1075000>,
+ <198000 975000>;
+ fsl,soc-operating-points =
/* ARM kHz SOC-PU uV */
- 996000 1175000
- 792000 1175000
- 396000 1175000
- 198000 1175000
- >;
+ <996000 1175000>,
+ <792000 1175000>,
+ <396000 1175000>,
+ <198000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SLL_CLK_ARM>,
diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi
index 8516730778..fc6334336b 100644
--- a/dts/src/arm/imx6sx.dtsi
+++ b/dts/src/arm/imx6sx.dtsi
@@ -1395,15 +1395,15 @@
};
pcie: pcie@8ffc000 {
- compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6sx-pcie";
reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
+ <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
diff --git a/dts/src/arm/imx6ul-phytec-phycore-som.dtsi b/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
index 19a062635f..3cddc68917 100644
--- a/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
+++ b/dts/src/arm/imx6ul-phytec-phycore-som.dtsi
@@ -68,8 +68,11 @@
};
&i2c1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
@@ -147,6 +150,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2cgpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
diff --git a/dts/src/arm/imx6ul-phytec-segin.dtsi b/dts/src/arm/imx6ul-phytec-segin.dtsi
index 95e4080dd0..0d4ba9494c 100644
--- a/dts/src/arm/imx6ul-phytec-segin.dtsi
+++ b/dts/src/arm/imx6ul-phytec-segin.dtsi
@@ -191,6 +191,7 @@
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
+ disable-wp;
status = "disabled";
};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-eval-v3.dts b/dts/src/arm/imx6ull-colibri-emmc-eval-v3.dts
new file mode 100644
index 0000000000..61b93cb040
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-emmc-eval-v3.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri-imx6ull-emmc-eval",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi b/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi
new file mode 100644
index 0000000000..a099abfdfa
--- /dev/null
+++ b/dts/src/arm/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 Toradex
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &usdhc2; /* eMMC */
+ mmc1 = &usdhc1; /* MMC 4bit slot */
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "SODIMM_89",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_140",
+ "SODIMM_59",
+ "SODIMM_142",
+ "SODIMM_144",
+ "SODIMM_133",
+ "SODIMM_146",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "SODIMM_81",
+ "SODIMM_94",
+ "SODIMM_101",
+ "SODIMM_103",
+ "SODIMM_79",
+ "SODIMM_97",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "SODIMM_93",
+ "",
+ "SODIMM_138",
+ "",
+ "SODIMM_105",
+ "SODIMM_127";
+};
+
+&gpmi {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+ &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7
+ &pinctrl_gpmi_gpio>;
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2emmc>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <&reg_module_3v3>;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi
index 0cdbf7b6e7..7f35a06dff 100644
--- a/dts/src/arm/imx6ull-colibri.dtsi
+++ b/dts/src/arm/imx6ull-colibri.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2021 Toradex
*/
#include "imx6ull.dtsi"
@@ -345,6 +345,19 @@
>;
};
+ /*
+ * With an eMMC instead of a raw NAND device the following pins
+ * are available at SODIMM pins
+ */
+ pinctrl_gpmi_gpio: gpmi-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
+ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
+ MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */
+ MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
+ >;
+ };
+
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
@@ -533,6 +546,21 @@
>;
};
+ pinctrl_usdhc2emmc: usdhc2emmcgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
+
pinctrl_wdog: wdog-grp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
diff --git a/dts/src/arm/imx7-mba7.dtsi b/dts/src/arm/imx7-mba7.dtsi
index 5e6bef230d..49086c6b6a 100644
--- a/dts/src/arm/imx7-mba7.dtsi
+++ b/dts/src/arm/imx7-mba7.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Include file for TQ Systems MBa7 carrier board.
+ * Device Tree Include file for TQ-Systems MBa7 carrier board.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*
@@ -236,6 +236,44 @@
};
};
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uboot@0 {
+ label = "U-Boot";
+ reg = <0x0 0xd0000>;
+ };
+
+ env1@d0000 {
+ label = "ENV1";
+ reg = <0xd0000 0x10000>;
+ };
+
+ env2@e0000 {
+ label = "ENV2";
+ reg = <0xe0000 0x10000>;
+ };
+
+ dtb@f0000 {
+ label = "DTB";
+ reg = <0xf0000 0x10000>;
+ };
+
+ linux@100000 {
+ label = "Linux";
+ reg = <0x100000 0x700000>;
+ };
+
+ rootfs@800000 {
+ label = "RootFS";
+ reg = <0x800000 0x3800000>;
+ };
+ };
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
diff --git a/dts/src/arm/imx7-tqma7.dtsi b/dts/src/arm/imx7-tqma7.dtsi
index 8773344b54..fe42b0a468 100644
--- a/dts/src/arm/imx7-tqma7.dtsi
+++ b/dts/src/arm/imx7-tqma7.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB.
+ * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
@@ -19,6 +19,16 @@
cpu-supply = <&sw1a_reg>;
};
+&gpio2 {
+ /* Configured as pullup by QSPI pin group */
+ qspi-reset-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "qspi-reset";
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -160,6 +170,25 @@
>;
};
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
+ MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
+ MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
+ MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
+ MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
+ MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
+ MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
+ >;
+ };
+
+ pinctrl_qspi_reset: qspi_resetgrp {
+ fsl,pins = <
+ /* #QSPI_RESET */
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
@@ -217,6 +246,20 @@
};
};
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&sdma {
status = "okay";
};
diff --git a/dts/src/arm/imx7d-mba7.dts b/dts/src/arm/imx7d-mba7.dts
index 36ef6a3cdb..32bf9fa9d0 100644
--- a/dts/src/arm/imx7d-mba7.dts
+++ b/dts/src/arm/imx7d-mba7.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
+ * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
@@ -13,7 +13,7 @@
#include "imx7-mba7.dtsi"
/ {
- model = "TQ Systems TQMa7D board on MBa7 carrier board";
+ model = "TQ-Systems TQMa7D board on MBa7 carrier board";
compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
};
diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts
index 4a0d83784d..7813ef960f 100644
--- a/dts/src/arm/imx7d-sdb.dts
+++ b/dts/src/arm/imx7d-sdb.dts
@@ -45,7 +45,7 @@
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/imx7d-tqma7.dtsi b/dts/src/arm/imx7d-tqma7.dtsi
index 598aed1ffd..3ee2017c1a 100644
--- a/dts/src/arm/imx7d-tqma7.dtsi
+++ b/dts/src/arm/imx7d-tqma7.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC.
+ * Device Tree Include file for TQ-Systems TQMa7D board with NXP i.MX7Dual SoC.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi
index b0bcfa9094..b7735979b7 100644
--- a/dts/src/arm/imx7d.dtsi
+++ b/dts/src/arm/imx7d.dtsi
@@ -164,7 +164,7 @@
};
pcie: pcie@33800000 {
- compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx7d-pcie";
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
reg-names = "dbi", "config";
@@ -172,10 +172,9 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
+ <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
- num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
diff --git a/dts/src/arm/imx7s-mba7.dts b/dts/src/arm/imx7s-mba7.dts
index d7d3f530f8..8e4cf589c9 100644
--- a/dts/src/arm/imx7s-mba7.dts
+++ b/dts/src/arm/imx7s-mba7.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board.
+ * Device Tree Source for TQ-Systems TQMa7S board on MBa7 carrier board.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
@@ -13,6 +13,6 @@
#include "imx7-mba7.dtsi"
/ {
- model = "TQ Systems TQMa7S board on MBa7 carrier board";
+ model = "TQ-Systems TQMa7S board on MBa7 carrier board";
compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s";
};
diff --git a/dts/src/arm/imx7s-tqma7.dtsi b/dts/src/arm/imx7s-tqma7.dtsi
index 5f5433eb7d..7a190fdb2d 100644
--- a/dts/src/arm/imx7s-tqma7.dtsi
+++ b/dts/src/arm/imx7s-tqma7.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
- * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC.
+ * Device Tree Include file for TQ-Systems TQMa7S board with NXP i.MX7Solo SoC.
*
- * Copyright (C) 2016 TQ Systems GmbH
+ * Copyright (C) 2016 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
diff --git a/dts/src/arm/integrator.dtsi b/dts/src/arm/integrator.dtsi
index 602f74d2c7..ad868cfebc 100644
--- a/dts/src/arm/integrator.dtsi
+++ b/dts/src/arm/integrator.dtsi
@@ -15,10 +15,14 @@
core-module@10000000 {
compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
reg = <0x10000000 0x200>;
+ ranges = <0x0 0x10000000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
/* Use core module LED to indicate CPU load */
- led@c.0 {
+ led@c,0 {
compatible = "register-bit-led";
+ reg = <0x0c 0x04>;
offset = <0x0c>;
mask = <0x01>;
label = "integrator:core_module";
@@ -104,35 +108,42 @@
interrupts = <4>;
};
- syscon {
+ syscon@1a000000 {
/* Debug registers mapped as syscon */
compatible = "syscon", "simple-mfd";
reg = <0x1a000000 0x10>;
+ ranges = <0x0 0x1a000000 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- led@4.0 {
+ led@4,0 {
compatible = "register-bit-led";
+ reg = <0x04 0x04>;
offset = <0x04>;
mask = <0x01>;
label = "integrator:green0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@4.1 {
+ led@4,1 {
compatible = "register-bit-led";
+ reg = <0x04 0x04>;
offset = <0x04>;
mask = <0x02>;
label = "integrator:yellow";
default-state = "off";
};
- led@4.2 {
+ led@4,2 {
compatible = "register-bit-led";
+ reg = <0x04 0x04>;
offset = <0x04>;
mask = <0x04>;
label = "integrator:red";
default-state = "off";
};
- led@4.3 {
+ led@4,3 {
compatible = "register-bit-led";
+ reg = <0x04 0x04>;
offset = <0x04>;
mask = <0x08>;
label = "integrator:green1";
diff --git a/dts/src/arm/integratorap-im-pd1.dts b/dts/src/arm/integratorap-im-pd1.dts
index 0614f82b80..d47bfb66d0 100644
--- a/dts/src/arm/integratorap-im-pd1.dts
+++ b/dts/src/arm/integratorap-im-pd1.dts
@@ -28,9 +28,13 @@
syscon@0 {
compatible = "arm,im-pd1-syscon", "syscon";
reg = <0x00000000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
- vco1: vco1-clock {
+ vco1: clock-controller@0 {
compatible = "arm,impd1-vco1";
+ reg = <0x00 0x04>;
#clock-cells = <0>;
lock-offset = <0x08>;
vco-offset = <0x00>;
@@ -38,8 +42,9 @@
clock-output-names = "IM-PD1-VCO1";
};
- vco2: vco2-clock {
+ vco2: clock-controller@4 {
compatible = "arm,impd1-vco2";
+ reg = <0x04 0x04>;
#clock-cells = <0>;
lock-offset = <0x08>;
vco-offset = <0x04>;
diff --git a/dts/src/arm/integratorap.dts b/dts/src/arm/integratorap.dts
index 67d1f9b24a..9b652cc27b 100644
--- a/dts/src/arm/integratorap.dts
+++ b/dts/src/arm/integratorap.dts
@@ -88,8 +88,9 @@
};
/* Oscillator on the core module, clocks the CPU core */
- cmosc: cmosc@24M {
+ cmosc: clock-controller@8 {
compatible = "arm,syscon-icst525-integratorap-cm";
+ reg = <0x08 0x04>;
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x08>;
@@ -97,8 +98,9 @@
};
/* Auxilary oscillator on the core module, 32.369MHz at boot */
- auxosc: auxosc@24M {
+ auxosc: clock-controller@1c {
compatible = "arm,syscon-icst525";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x1c>;
@@ -109,13 +111,17 @@
syscon {
compatible = "arm,integrator-ap-syscon", "syscon";
reg = <0x11000000 0x100>;
+ ranges = <0x0 0x11000000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
/*
* SYSCLK clocks PCIv3 bridge, system controller and the
* logic modules.
*/
- sysclk: apsys@24M {
+ sysclk: clock-controller@4 {
compatible = "arm,syscon-icst525-integratorap-sys";
+ reg = <0x04 0x04>;
#clock-cells = <0>;
lock-offset = <0x1c>;
vco-offset = <0x04>;
@@ -123,8 +129,9 @@
};
/* One-bit control for the PCI bus clock (33 or 25 MHz) */
- pciclk: pciclk@24M {
+ pciclk: clock-controller@4,8 {
compatible = "arm,syscon-icst525-integratorap-pci";
+ reg = <0x04 0x04>;
#clock-cells = <0>;
lock-offset = <0x1c>;
vco-offset = <0x04>;
diff --git a/dts/src/arm/integratorcp.dts b/dts/src/arm/integratorcp.dts
index 01fa229e1b..38fc7e81bd 100644
--- a/dts/src/arm/integratorcp.dts
+++ b/dts/src/arm/integratorcp.dts
@@ -92,8 +92,9 @@
};
/* Oscillator on the core module, clocks the CPU core */
- cmcore: cmosc@24M {
+ cmcore: clock-controller@8 {
compatible = "arm,syscon-icst525-integratorcp-cm-core";
+ reg = <0x08 0x04>;
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x08>;
@@ -101,8 +102,9 @@
};
/* Oscillator on the core module, clocks the memory bus */
- cmmem: cmosc@24M {
+ cmmem: clock-controller@8,12 {
compatible = "arm,syscon-icst525-integratorcp-cm-mem";
+ reg = <0x08 0x04>;
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x08>;
@@ -110,8 +112,9 @@
};
/* Auxilary oscillator on the core module, clocks the CLCD */
- auxosc: auxosc@24M {
+ auxosc: clock-controller@1c {
compatible = "arm,syscon-icst525";
+ reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x1c>;
diff --git a/dts/src/arm/intel-ixp42x-adi-coyote.dts b/dts/src/arm/intel-ixp42x-adi-coyote.dts
index 44c017b780..bd4230d7da 100644
--- a/dts/src/arm/intel-ixp42x-adi-coyote.dts
+++ b/dts/src/arm/intel-ixp42x-adi-coyote.dts
@@ -63,6 +63,8 @@
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
diff --git a/dts/src/arm/intel-ixp42x-arcom-vulcan.dts b/dts/src/arm/intel-ixp42x-arcom-vulcan.dts
index 7200126cb3..92b987bc3f 100644
--- a/dts/src/arm/intel-ixp42x-arcom-vulcan.dts
+++ b/dts/src/arm/intel-ixp42x-arcom-vulcan.dts
@@ -120,6 +120,8 @@
* We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
* per slot. This interrupt is shared (OR:ed) by all four pins.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
diff --git a/dts/src/arm/intel-ixp42x-dlink-dsm-g600.dts b/dts/src/arm/intel-ixp42x-dlink-dsm-g600.dts
index 8b32e9f22d..5ab09fb10d 100644
--- a/dts/src/arm/intel-ixp42x-dlink-dsm-g600.dts
+++ b/dts/src/arm/intel-ixp42x-dlink-dsm-g600.dts
@@ -129,6 +129,8 @@
* We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
* Only slot 3 have three IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */
diff --git a/dts/src/arm/intel-ixp42x-freecom-fsg-3.dts b/dts/src/arm/intel-ixp42x-freecom-fsg-3.dts
index 77e78c6dc2..598586fc08 100644
--- a/dts/src/arm/intel-ixp42x-freecom-fsg-3.dts
+++ b/dts/src/arm/intel-ixp42x-freecom-fsg-3.dts
@@ -106,6 +106,8 @@
* Written based on the FSG-3 PCI boardfile.
* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
diff --git a/dts/src/arm/intel-ixp42x-gateworks-gw2348.dts b/dts/src/arm/intel-ixp42x-gateworks-gw2348.dts
index a20277ff04..a5943f51e8 100644
--- a/dts/src/arm/intel-ixp42x-gateworks-gw2348.dts
+++ b/dts/src/arm/intel-ixp42x-gateworks-gw2348.dts
@@ -115,6 +115,8 @@
*
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/src/arm/intel-ixp42x-iomega-nas100d.dts b/dts/src/arm/intel-ixp42x-iomega-nas100d.dts
index 8c18d802c8..cbc87b344f 100644
--- a/dts/src/arm/intel-ixp42x-iomega-nas100d.dts
+++ b/dts/src/arm/intel-ixp42x-iomega-nas100d.dts
@@ -115,6 +115,8 @@
* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
* We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/src/arm/intel-ixp42x-ixdpg425.dts b/dts/src/arm/intel-ixp42x-ixdpg425.dts
index 002a8705ab..f17cab12a6 100644
--- a/dts/src/arm/intel-ixp42x-ixdpg425.dts
+++ b/dts/src/arm/intel-ixp42x-ixdpg425.dts
@@ -68,6 +68,8 @@
* We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
* for 12 & 13 and one for 14.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
diff --git a/dts/src/arm/intel-ixp42x-linksys-nslu2.dts b/dts/src/arm/intel-ixp42x-linksys-nslu2.dts
index e3a32b08d1..0edc5928e0 100644
--- a/dts/src/arm/intel-ixp42x-linksys-nslu2.dts
+++ b/dts/src/arm/intel-ixp42x-linksys-nslu2.dts
@@ -122,6 +122,8 @@
* Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
* We have slots (IDSEL) 1, 2 and 3.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/src/arm/intel-ixp42x-linksys-wrv54g.dts b/dts/src/arm/intel-ixp42x-linksys-wrv54g.dts
index 6b28dda747..5e7e31b74b 100644
--- a/dts/src/arm/intel-ixp42x-linksys-wrv54g.dts
+++ b/dts/src/arm/intel-ixp42x-linksys-wrv54g.dts
@@ -123,6 +123,8 @@
* We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
* Derived from the GTWX5715 PCI boardfile.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 0 */
<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
diff --git a/dts/src/arm/intel-ixp42x-netgear-wg302v2.dts b/dts/src/arm/intel-ixp42x-netgear-wg302v2.dts
index 04a0f71389..a57009436e 100644
--- a/dts/src/arm/intel-ixp42x-netgear-wg302v2.dts
+++ b/dts/src/arm/intel-ixp42x-netgear-wg302v2.dts
@@ -62,6 +62,8 @@
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
diff --git a/dts/src/arm/intel-ixp43x-gateworks-gw2358.dts b/dts/src/arm/intel-ixp43x-gateworks-gw2358.dts
index 84e6aec8e6..cf4010d601 100644
--- a/dts/src/arm/intel-ixp43x-gateworks-gw2358.dts
+++ b/dts/src/arm/intel-ixp43x-gateworks-gw2358.dts
@@ -131,6 +131,8 @@
* have instead assumed that they are rotated (swizzled) like
* this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/src/arm/intel-ixp45x-ixp46x.dtsi b/dts/src/arm/intel-ixp45x-ixp46x.dtsi
index b6ff614dad..1dd4a65cb7 100644
--- a/dts/src/arm/intel-ixp45x-ixp46x.dtsi
+++ b/dts/src/arm/intel-ixp45x-ixp46x.dtsi
@@ -74,5 +74,13 @@
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
+
+ ptp-timer@c8010000 {
+ compatible = "intel,ixp46x-ptp-timer";
+ reg = <0xc8010000 0x1000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "master", "slave";
+ };
};
};
diff --git a/dts/src/arm/intel-ixp4xx-reference-design.dtsi b/dts/src/arm/intel-ixp4xx-reference-design.dtsi
index c1d9c49982..146352ba84 100644
--- a/dts/src/arm/intel-ixp4xx-reference-design.dtsi
+++ b/dts/src/arm/intel-ixp4xx-reference-design.dtsi
@@ -106,6 +106,8 @@
* PCI slots on the BIXMB425BD base card.
* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/src/arm/intel-ixp4xx.dtsi b/dts/src/arm/intel-ixp4xx.dtsi
index e5af2d4630..46fede0214 100644
--- a/dts/src/arm/intel-ixp4xx.dtsi
+++ b/dts/src/arm/intel-ixp4xx.dtsi
@@ -78,8 +78,6 @@
dma-ranges =
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xf800 0 0 7>;
/* Each unique DTS using PCI must specify the swizzling */
};
diff --git a/dts/src/arm/iwg20d-q7-common.dtsi b/dts/src/arm/iwg20d-q7-common.dtsi
index bc857676d1..849034a49a 100644
--- a/dts/src/arm/iwg20d-q7-common.dtsi
+++ b/dts/src/arm/iwg20d-q7-common.dtsi
@@ -158,6 +158,8 @@
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
diff --git a/dts/src/arm/ls1021a-qds.dts b/dts/src/arm/ls1021a-qds.dts
index 74a6760487..f1acb97aee 100644
--- a/dts/src/arm/ls1021a-qds.dts
+++ b/dts/src/arm/ls1021a-qds.dts
@@ -1,49 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -67,19 +25,12 @@
clock-frequency = <24576000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_3p3v: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ reg_3p3v: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
sound {
@@ -231,9 +182,9 @@
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
- ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000>,
+ <0x2 0x0 0x0 0x7e800000 0x00010000>,
+ <0x3 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
@@ -254,7 +205,7 @@
fpga: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "simple-bus";
+ compatible = "simple-mfd";
reg = <0x3 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
@@ -328,6 +279,20 @@
};
};
+&qspi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&sai2 {
status = "okay";
};
diff --git a/dts/src/arm/ls1021a-tsn.dts b/dts/src/arm/ls1021a-tsn.dts
index 9d8f0c2a8a..ff0ffb2276 100644
--- a/dts/src/arm/ls1021a-tsn.dts
+++ b/dts/src/arm/ls1021a-tsn.dts
@@ -8,6 +8,7 @@
/ {
model = "NXP LS1021A-TSN Board";
+ compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
sys_mclk: clock-mclk {
compatible = "fixed-clock";
@@ -136,7 +137,6 @@
/* 3 axis accelerometer */
accelerometer@1e {
compatible = "fsl,fxls8471";
- position = <0>;
reg = <0x1e>;
};
@@ -251,7 +251,7 @@
flash@0 {
/* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
- compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/ls1021a-twr.dts b/dts/src/arm/ls1021a-twr.dts
index 5edf001f61..f5c03871b2 100644
--- a/dts/src/arm/ls1021a-twr.dts
+++ b/dts/src/arm/ls1021a-twr.dts
@@ -1,49 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -65,19 +23,12 @@
clock-frequency = <24576000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_3p3v: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ reg_3p3v: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
sound {
diff --git a/dts/src/arm/ls1021a.dtsi b/dts/src/arm/ls1021a.dtsi
index 4fce814229..2e69d6eab4 100644
--- a/dts/src/arm/ls1021a.dtsi
+++ b/dts/src/arm/ls1021a.dtsi
@@ -1,48 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -51,7 +9,6 @@
/ {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "fsl,ls1021a";
interrupt-parent = <&gic>;
aliases {
@@ -90,7 +47,7 @@
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>;
};
@@ -169,6 +126,7 @@
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
dcfg: dcfg@1ee0000 {
@@ -290,78 +248,45 @@
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
- fsl,tmu-calibration = <0x00000000 0x00000020
- 0x00000001 0x00000024
- 0x00000002 0x0000002a
- 0x00000003 0x00000032
- 0x00000004 0x00000038
- 0x00000005 0x0000003e
- 0x00000006 0x00000043
- 0x00000007 0x0000004a
- 0x00000008 0x00000050
- 0x00000009 0x00000059
- 0x0000000a 0x0000005f
- 0x0000000b 0x00000066
-
- 0x00010000 0x00000023
- 0x00010001 0x0000002b
- 0x00010002 0x00000033
- 0x00010003 0x0000003a
- 0x00010004 0x00000042
- 0x00010005 0x0000004a
- 0x00010006 0x00000054
- 0x00010007 0x0000005c
- 0x00010008 0x00000065
- 0x00010009 0x0000006f
-
- 0x00020000 0x00000029
- 0x00020001 0x00000033
- 0x00020002 0x0000003d
- 0x00020003 0x00000048
- 0x00020004 0x00000054
- 0x00020005 0x00000060
- 0x00020006 0x0000006c
-
- 0x00030000 0x00000025
- 0x00030001 0x00000033
- 0x00030002 0x00000043
- 0x00030003 0x00000055>;
+ fsl,tmu-calibration = <0x00000000 0x00000020>,
+ <0x00000001 0x00000024>,
+ <0x00000002 0x0000002a>,
+ <0x00000003 0x00000032>,
+ <0x00000004 0x00000038>,
+ <0x00000005 0x0000003e>,
+ <0x00000006 0x00000043>,
+ <0x00000007 0x0000004a>,
+ <0x00000008 0x00000050>,
+ <0x00000009 0x00000059>,
+ <0x0000000a 0x0000005f>,
+ <0x0000000b 0x00000066>,
+
+ <0x00010000 0x00000023>,
+ <0x00010001 0x0000002b>,
+ <0x00010002 0x00000033>,
+ <0x00010003 0x0000003a>,
+ <0x00010004 0x00000042>,
+ <0x00010005 0x0000004a>,
+ <0x00010006 0x00000054>,
+ <0x00010007 0x0000005c>,
+ <0x00010008 0x00000065>,
+ <0x00010009 0x0000006f>,
+
+ <0x00020000 0x00000029>,
+ <0x00020001 0x00000033>,
+ <0x00020002 0x0000003d>,
+ <0x00020003 0x00000048>,
+ <0x00020004 0x00000054>,
+ <0x00020005 0x00000060>,
+ <0x00020006 0x0000006c>,
+
+ <0x00030000 0x00000025>,
+ <0x00030001 0x00000033>,
+ <0x00030002 0x00000043>,
+ <0x00030003 0x00000055>;
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
dspi0: spi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -394,10 +319,9 @@
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
clocks = <&clockgen 4 1>;
- dma-names = "tx", "rx";
- dmas = <&edma0 1 39>, <&edma0 1 38>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 38>, <&edma0 1 39>;
status = "disabled";
};
@@ -407,10 +331,9 @@
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
clocks = <&clockgen 4 1>;
- dma-names = "tx", "rx";
- dmas = <&edma0 1 37>, <&edma0 1 36>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 36>, <&edma0 1 37>;
status = "disabled";
};
@@ -420,10 +343,9 @@
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
clocks = <&clockgen 4 1>;
- dma-names = "tx", "rx";
- dmas = <&edma0 1 35>, <&edma0 1 34>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 34>, <&edma0 1 35>;
status = "disabled";
};
@@ -884,8 +806,8 @@
pcie@3400000 {
compatible = "fsl,ls1021a-pcie";
- reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
fsl,pcie-scfg = <&scfg 0>;
@@ -894,8 +816,8 @@
device_type = "pci";
num-viewport = <6>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
+ <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
@@ -908,8 +830,8 @@
pcie@3500000 {
compatible = "fsl,ls1021a-pcie";
- reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
fsl,pcie-scfg = <&scfg 1>;
@@ -918,8 +840,8 @@
device_type = "pci";
num-viewport = <6>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
+ <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
@@ -992,6 +914,7 @@
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error",
"qdma-queue0", "qdma-queue1";
+ #dma-cells = <2>;
dma-channels = <8>;
block-number = <1>;
block-offset = <0x1000>;
@@ -1005,6 +928,7 @@
compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x8>;
#fsl,rcpm-wakeup-cells = <2>;
+ #power-domain-cells = <0>;
};
ftm_alarm0: timer0@29d0000 {
@@ -1016,4 +940,37 @@
big-endian;
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
diff --git a/dts/src/arm/mps2.dtsi b/dts/src/arm/mps2.dtsi
index 37f5023f52..b99577d411 100644
--- a/dts/src/arm/mps2.dtsi
+++ b/dts/src/arm/mps2.dtsi
@@ -216,8 +216,13 @@
compatible = "syscon", "simple-mfd";
reg = <0x8000 0x10>;
- led0 {
+ ranges = <0x0 0x8000 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ led@0,0 {
compatible = "register-bit-led";
+ reg = <0x00 0x04>;
offset = <0x0>;
mask = <0x01>;
label = "userled:0";
@@ -225,8 +230,9 @@
default-state = "on";
};
- led1 {
+ led@0,1 {
compatible = "register-bit-led";
+ reg = <0x00 0x04>;
offset = <0x0>;
mask = <0x02>;
label = "userled:1";
diff --git a/dts/src/arm/mstar-v7.dtsi b/dts/src/arm/mstar-v7.dtsi
index 2273295e14..89ebfe4f29 100644
--- a/dts/src/arm/mstar-v7.dtsi
+++ b/dts/src/arm/mstar-v7.dtsi
@@ -39,6 +39,7 @@
* u-boot is broken
*/
clock-frequency = <6000000>;
+ arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
@@ -109,12 +110,20 @@
mask = <0x79>;
};
+ rtc@2400 {
+ compatible = "mstar,msc313-rtc";
+ reg = <0x2400 0x40>;
+ clocks = <&xtal_div2>;
+ interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
watchdog@6000 {
compatible = "mstar,msc313e-wdt";
reg = <0x6000 0x1f>;
clocks = <&xtal_div2>;
};
+
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
reg = <0x201310 0x40>;
diff --git a/dts/src/arm/mt7623.dtsi b/dts/src/arm/mt7623.dtsi
index a7d62dbad6..f4848362b3 100644
--- a/dts/src/arm/mt7623.dtsi
+++ b/dts/src/arm/mt7623.dtsi
@@ -585,6 +585,39 @@
status = "disabled";
};
+ usb0: usb@11200000 {
+ compatible = "mediatek,mt7623-musb",
+ "mediatek,mtk-musb";
+ reg = <0 0x11200000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ status = "disabled";
+ };
+
+ u2phy1: t-phy@11210000 {
+ compatible = "mediatek,mt7623-tphy",
+ "mediatek,generic-tphy-v1";
+ reg = <0 0x11210000 0 0x0800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port2: usb-phy@11210800 {
+ reg = <0 0x11210800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7623-audsys",
"mediatek,mt2701-audsys",
diff --git a/dts/src/arm/mt7623a.dtsi b/dts/src/arm/mt7623a.dtsi
index 0735a1fb8a..d304b62d24 100644
--- a/dts/src/arm/mt7623a.dtsi
+++ b/dts/src/arm/mt7623a.dtsi
@@ -35,6 +35,10 @@
clock-names = "ethif";
};
+&usb0 {
+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
+};
+
&usb1 {
power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
};
diff --git a/dts/src/arm/mt7623n-bananapi-bpi-r2.dts b/dts/src/arm/mt7623n-bananapi-bpi-r2.dts
index e96aa0ed1e..027c1b0c6a 100644
--- a/dts/src/arm/mt7623n-bananapi-bpi-r2.dts
+++ b/dts/src/arm/mt7623n-bananapi-bpi-r2.dts
@@ -366,6 +366,14 @@
status = "okay";
};
+&pio {
+ musb_pins: musb {
+ pins-musb {
+ pinmux = <MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS>;
+ };
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins_a>;
@@ -396,6 +404,19 @@
status = "okay";
};
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&musb_pins>;
+ status = "okay";
+ usb-role-switch;
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&usb1 {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
@@ -408,6 +429,10 @@
status = "okay";
};
+&u2phy1 {
+ status = "okay";
+};
+
&u3phy1 {
status = "okay";
};
diff --git a/dts/src/arm/mt7629-rfb.dts b/dts/src/arm/mt7629-rfb.dts
index 9980c10c6e..eb536cbebd 100644
--- a/dts/src/arm/mt7629-rfb.dts
+++ b/dts/src/arm/mt7629-rfb.dts
@@ -140,9 +140,10 @@
};
};
-&pcie {
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
+ status = "okay";
};
&pciephy1 {
diff --git a/dts/src/arm/mt7629.dtsi b/dts/src/arm/mt7629.dtsi
index 874043f049..46fc236e1b 100644
--- a/dts/src/arm/mt7629.dtsi
+++ b/dts/src/arm/mt7629.dtsi
@@ -361,16 +361,21 @@
#reset-cells = <1>;
};
- pcie: pcie@1a140000 {
+ pciecfg: pciecfg@1a140000 {
+ compatible = "mediatek,generic-pciecfg", "syscon";
+ reg = <0x1a140000 0x1000>;
+ };
+
+ pcie1: pcie@1a145000 {
compatible = "mediatek,mt7629-pcie";
device_type = "pci";
- reg = <0x1a140000 0x1000>,
- <0x1a145000 0x1000>;
- reg-names = "subsys","port1";
+ reg = <0x1a145000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "pcie_irq";
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
@@ -391,26 +396,18 @@
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+ status = "disabled";
- pcie1: pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
- ranges;
- num-lanes = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
-
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
};
};
diff --git a/dts/src/arm/omap-gpmc-smsc911x.dtsi b/dts/src/arm/omap-gpmc-smsc911x.dtsi
index ded7e8fec9..ce6c235f68 100644
--- a/dts/src/arm/omap-gpmc-smsc911x.dtsi
+++ b/dts/src/arm/omap-gpmc-smsc911x.dtsi
@@ -25,8 +25,8 @@
compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>;
gpmc,device-width = <1>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;
diff --git a/dts/src/arm/omap-gpmc-smsc9221.dtsi b/dts/src/arm/omap-gpmc-smsc9221.dtsi
index 7f6aefd134..e7534fe9c5 100644
--- a/dts/src/arm/omap-gpmc-smsc9221.dtsi
+++ b/dts/src/arm/omap-gpmc-smsc9221.dtsi
@@ -29,7 +29,7 @@
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
- gpmc,mux-add-data;
+ gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;
diff --git a/dts/src/arm/omap-zoom-common.dtsi b/dts/src/arm/omap-zoom-common.dtsi
index d4ad9e58b1..1e96c865d4 100644
--- a/dts/src/arm/omap-zoom-common.dtsi
+++ b/dts/src/arm/omap-zoom-common.dtsi
@@ -27,8 +27,8 @@
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <1>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <155>;
gpmc,cs-wr-off-ns = <155>;
diff --git a/dts/src/arm/omap2430-sdp.dts b/dts/src/arm/omap2430-sdp.dts
index 7d27e90753..207070677e 100644
--- a/dts/src/arm/omap2430-sdp.dts
+++ b/dts/src/arm/omap2430-sdp.dts
@@ -43,8 +43,8 @@
gpmc,sync-clk-ps = <0>;
gpmc,mux-add-data = <2>;
gpmc,device-width = <1>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <187>;
gpmc,cs-wr-off-ns = <187>;
diff --git a/dts/src/arm/omap3-cpu-thermal.dtsi b/dts/src/arm/omap3-cpu-thermal.dtsi
index 1ed8378593..a9069cca58 100644
--- a/dts/src/arm/omap3-cpu-thermal.dtsi
+++ b/dts/src/arm/omap3-cpu-thermal.dtsi
@@ -10,7 +10,7 @@
#include <dt-bindings/thermal/thermal.h>
-cpu_thermal: cpu_thermal {
+cpu_thermal: cpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
coefficients = <0 20000>;
diff --git a/dts/src/arm/omap3-devkit8000-common.dtsi b/dts/src/arm/omap3-devkit8000-common.dtsi
index 2c19d6e255..5e55198e45 100644
--- a/dts/src/arm/omap3-devkit8000-common.dtsi
+++ b/dts/src/arm/omap3-devkit8000-common.dtsi
@@ -267,8 +267,8 @@
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <0>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <180>;
diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi
index 938cc691bb..7e3d8147e2 100644
--- a/dts/src/arm/omap3-gta04.dtsi
+++ b/dts/src/arm/omap3-gta04.dtsi
@@ -104,16 +104,16 @@
#sound-dai-cells = <0>;
};
- spi_lcd: spi_lcd {
+ spi_lcd: spi {
compatible = "spi-gpio";
#address-cells = <0x1>;
#size-cells = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_gpio_pins>;
- gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
@@ -508,6 +508,8 @@
pinctrl-0 = <&bmp085_pins>;
interrupt-parent = <&gpio4>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */
+ vdda-supply = <&vio>;
+ vddd-supply = <&vio>;
};
/* accelerometer */
@@ -515,7 +517,7 @@
compatible = "bosch,bma180";
reg = <0x41>;
pinctrl-names = "default";
- pintcrl-0 = <&bma180_pins>;
+ pinctrl-0 = <&bma180_pins>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
};
@@ -540,28 +542,29 @@
gpio-controller;
#gpio-cells = <2>;
- gta04_led0: red_aux@0 {
+ gta04_led0: led@0 {
label = "gta04:red:aux";
reg = <0x0>;
};
- gta04_led1: green_aux@1 {
+ gta04_led1: led@1 {
label = "gta04:green:aux";
reg = <0x1>;
};
- gta04_led3: red_power@3 {
+ gta04_led3: led@3 {
label = "gta04:red:power";
reg = <0x3>;
linux,default-trigger = "default-on";
};
- gta04_led4: green_power@4 {
+ gta04_led4: led@4 {
label = "gta04:green:power";
reg = <0x4>;
};
- wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */
+ wifi_reset: led@6 {
+ /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */
reg = <0x6>;
compatible = "gpio";
};
diff --git a/dts/src/arm/omap3-gta04a5.dts b/dts/src/arm/omap3-gta04a5.dts
index 9ce8d81250..0b5bd73888 100644
--- a/dts/src/arm/omap3-gta04a5.dts
+++ b/dts/src/arm/omap3-gta04a5.dts
@@ -79,7 +79,7 @@
/*
* for WL183x module see
- * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
+ * Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml
*/
&wifi_pwrseq {
@@ -133,5 +133,7 @@
bme280@76 {
compatible = "bosch,bme280";
reg = <0x76>;
+ vdda-supply = <&vio>;
+ vddd-supply = <&vio>;
};
};
diff --git a/dts/src/arm/omap3-overo-tobiduo-common.dtsi b/dts/src/arm/omap3-overo-tobiduo-common.dtsi
index e5da3bc6f1..218a10c0d8 100644
--- a/dts/src/arm/omap3-overo-tobiduo-common.dtsi
+++ b/dts/src/arm/omap3-overo-tobiduo-common.dtsi
@@ -22,7 +22,7 @@
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
- gpmc,mux-add-data;
+ gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;
diff --git a/dts/src/arm/omap3-sb-t35.dtsi b/dts/src/arm/omap3-sb-t35.dtsi
index fb9842fa92..5ec0893415 100644
--- a/dts/src/arm/omap3-sb-t35.dtsi
+++ b/dts/src/arm/omap3-sb-t35.dtsi
@@ -108,8 +108,8 @@
reg = <4 0 0xff>;
bank-width = <2>;
gpmc,device-width = <1>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;
diff --git a/dts/src/arm/qcom-apq8026-lg-lenok.dts b/dts/src/arm/qcom-apq8026-lg-lenok.dts
new file mode 100644
index 0000000000..f350c4e8c1
--- /dev/null
+++ b/dts/src/arm/qcom-apq8026-lg-lenok.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "qcom-pm8226.dtsi"
+
+/ {
+ model = "LG G Watch R";
+ compatible = "lg,lenok", "qcom,apq8026";
+ qcom,board-id = <132 0x0a>;
+ qcom,msm-id = <199 0x20000>;
+
+ aliases {
+ serial0 = &blsp1_uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+ clock-frequency = <384000>;
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l15>;
+ vio-supply = <&pm8226_l22>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&rpm_requests {
+ pm8226-regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s1: s1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1275000>;
+ };
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhc1_pin_a>;
+};
+
+&tlmm {
+ sdhc1_pin_a: sdhc1-pin-active {
+ clk {
+ pins = "sdc1_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ touch_pins: touch {
+ irq {
+ pins = "gpio17";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ reset {
+ pins = "gpio16";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
diff --git a/dts/src/arm/qcom-apq8060-dragonboard.dts b/dts/src/arm/qcom-apq8060-dragonboard.dts
index e1189e929e..d664ccd454 100644
--- a/dts/src/arm/qcom-apq8060-dragonboard.dts
+++ b/dts/src/arm/qcom-apq8060-dragonboard.dts
@@ -357,8 +357,8 @@
};
mpps@50 {
- dragon_cm3605_mpps: cm3605-mpps {
- pinconf {
+ dragon_cm3605_mpps: cm3605-mpps-state {
+ mpp5 {
pins = "mpp5";
function = "analog";
input-enable;
@@ -899,7 +899,7 @@
};
amba {
/* Internal 3.69 GiB eMMC */
- sdcc@12400000 {
+ mmc@12400000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dragon_sdcc1_pins>;
@@ -908,7 +908,7 @@
};
/* External micro SD card, directly connected, pulled up to 2.85 V */
- sdcc@12180000 {
+ mmc@12180000 {
status = "okay";
/* Enable SSBI GPIO 22 as input, use for card detect */
pinctrl-names = "default";
@@ -922,7 +922,7 @@
* Second external micro SD card, using two TXB104RGYR levelshifters
* to lift from 1.8 V to 2.85 V
*/
- sdcc@12200000 {
+ mmc@12200000 {
status = "okay";
/* Enable SSBI GPIO 26 as input, use for card detect */
pinctrl-names = "default";
diff --git a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
index 3bce47d16a..9a835335bf 100644
--- a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
+++ b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
@@ -335,7 +335,7 @@
amba {
/* eMMC */
- sdcc@12400000 {
+ mmc@12400000 {
status = "okay";
vmmc-supply = <&pm8921_l5>;
vqmmc-supply = <&pm8921_s4>;
diff --git a/dts/src/arm/qcom-apq8064-cm-qs600.dts b/dts/src/arm/qcom-apq8064-cm-qs600.dts
index 0148148a8e..e068a8d0ad 100644
--- a/dts/src/arm/qcom-apq8064-cm-qs600.dts
+++ b/dts/src/arm/qcom-apq8064-cm-qs600.dts
@@ -220,14 +220,14 @@
amba {
/* eMMC */
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "okay";
vmmc-supply = <&pm8921_l5>;
vqmmc-supply = <&pm8921_s4>;
};
/* External micro SD card */
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
pinctrl-names = "default";
@@ -235,7 +235,7 @@
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
- sdcc4: sdcc@121c0000 {
+ sdcc4: mmc@121c0000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
vqmmc-supply = <&v3p3_fixed>;
diff --git a/dts/src/arm/qcom-apq8064-ifc6410.dts b/dts/src/arm/qcom-apq8064-ifc6410.dts
index d0a17b5a5f..2638b380be 100644
--- a/dts/src/arm/qcom-apq8064-ifc6410.dts
+++ b/dts/src/arm/qcom-apq8064-ifc6410.dts
@@ -314,14 +314,14 @@
amba {
/* eMMC */
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "okay";
vmmc-supply = <&pm8921_l5>;
vqmmc-supply = <&pm8921_s4>;
};
/* External micro SD card */
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&pm8921_l6>;
pinctrl-names = "default";
@@ -329,7 +329,7 @@
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
- sdcc4: sdcc@121c0000 {
+ sdcc4: mmc@121c0000 {
status = "okay";
vmmc-supply = <&ext_3p3v>;
vqmmc-supply = <&pm8921_lvs1>;
diff --git a/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts b/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
index 72e47bdc5c..f8c97efc61 100644
--- a/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
+++ b/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
@@ -374,14 +374,14 @@
};
amba {
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "okay";
vmmc-supply = <&pm8921_l5>;
vqmmc-supply = <&pm8921_s4>;
};
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&pm8921_l6>;
diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi
index d1c1c6aab2..4d562c94c3 100644
--- a/dts/src/arm/qcom-apq8064.dtsi
+++ b/dts/src/arm/qcom-apq8064.dtsi
@@ -95,13 +95,13 @@
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
thermal-zones {
- cpu-thermal0 {
+ cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -122,7 +122,7 @@
};
};
- cpu-thermal1 {
+ cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -143,7 +143,7 @@
};
};
- cpu-thermal2 {
+ cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -164,7 +164,7 @@
};
};
- cpu-thermal3 {
+ cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -683,12 +683,11 @@
pm8821_mpps: mpps@50 {
compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
reg = <0x50>;
- interrupts = <24 IRQ_TYPE_NONE>,
- <25 IRQ_TYPE_NONE>,
- <26 IRQ_TYPE_NONE>,
- <27 IRQ_TYPE_NONE>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pm8821_mpps 0 0 4>;
};
};
};
@@ -726,19 +725,9 @@
reg = <0x50>;
gpio-controller;
#gpio-cells = <2>;
- interrupts =
- <128 IRQ_TYPE_NONE>,
- <129 IRQ_TYPE_NONE>,
- <130 IRQ_TYPE_NONE>,
- <131 IRQ_TYPE_NONE>,
- <132 IRQ_TYPE_NONE>,
- <133 IRQ_TYPE_NONE>,
- <134 IRQ_TYPE_NONE>,
- <135 IRQ_TYPE_NONE>,
- <136 IRQ_TYPE_NONE>,
- <137 IRQ_TYPE_NONE>,
- <138 IRQ_TYPE_NONE>,
- <139 IRQ_TYPE_NONE>;
+ gpio-ranges = <&pm8921_mpps 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
rtc@11d {
@@ -1084,7 +1073,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
pinctrl-names = "default";
@@ -1104,7 +1093,7 @@
dma-names = "tx", "rx";
};
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
@@ -1122,7 +1111,7 @@
dma-names = "tx", "rx";
};
- sdcc4: sdcc@121c0000 {
+ sdcc4: mmc@121c0000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
@@ -1229,13 +1218,17 @@
&gfx3d1 30
&gfx3d1 31>;
- qcom,gpu-pwrlevels {
- compatible = "qcom,gpu-pwrlevels";
- qcom,gpu-pwrlevel@0 {
- qcom,gpu-freq = <450000000>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <450000000>;
};
- qcom,gpu-pwrlevel@1 {
- qcom,gpu-freq = <27000000>;
+
+ opp-27000000 {
+ opp-hz = /bits/ 64 <27000000>;
};
};
};
@@ -1419,9 +1412,9 @@
clocks = <&mmcc HDMI_APP_CLK>,
<&mmcc HDMI_M_AHB_CLK>,
<&mmcc HDMI_S_AHB_CLK>;
- clock-names = "core_clk",
- "master_iface_clk",
- "slave_iface_clk";
+ clock-names = "core",
+ "master_iface",
+ "slave_iface";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
@@ -1452,7 +1445,7 @@
"hdmi_pll";
clocks = <&mmcc HDMI_S_AHB_CLK>;
- clock-names = "slave_iface_clk";
+ clock-names = "slave_iface";
#phy-cells = <0>;
};
diff --git a/dts/src/arm/qcom-apq8084.dtsi b/dts/src/arm/qcom-apq8084.dtsi
index bf6a03506b..52240fc7a1 100644
--- a/dts/src/arm/qcom-apq8084.dtsi
+++ b/dts/src/arm/qcom-apq8084.dtsi
@@ -102,7 +102,7 @@
};
thermal-zones {
- cpu-thermal0 {
+ cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -122,7 +122,7 @@
};
};
- cpu-thermal1 {
+ cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -142,7 +142,7 @@
};
};
- cpu-thermal2 {
+ cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -162,7 +162,7 @@
};
};
- cpu-thermal3 {
+ cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk01.1-c1.dts b/dts/src/arm/qcom-ipq4019-ap.dk01.1-c1.dts
index 0d92f1bc3a..ddaa273f72 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/dts/src/arm/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,5 +18,5 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
-
+ compatible = "qcom,ipq4019-ap-dk01.1-c1", "qcom,ipq4019";
};
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
index c93b2164db..0c10d9e096 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi
@@ -18,7 +18,6 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
- compatible = "qcom,ipq4019";
aliases {
serial0 = &blsp1_uart1;
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk04.1-c1.dts b/dts/src/arm/qcom-ipq4019-ap.dk04.1-c1.dts
index b0f476ff01..a7b1201dd6 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk04.1-c1.dts
+++ b/dts/src/arm/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -5,7 +5,7 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
- compatible = "qcom,ipq4019-dk04.1-c1";
+ compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";
soc {
dma@7984000 {
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk04.1-c3.dts b/dts/src/arm/qcom-ipq4019-ap.dk04.1-c3.dts
index 2d1c4c6e42..7765247125 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk04.1-c3.dts
+++ b/dts/src/arm/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -5,5 +5,5 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
- compatible = "qcom,ipq4019-ap-dk04.1-c3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3", "qcom,ipq4019";
};
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts
index f343a22443..06f9f2cb2f 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -5,7 +5,7 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
- compatible = "qcom,ipq4019-ap-dk07.1-c1";
+ compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
soc {
pci@40000000 {
diff --git a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c2.dts b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c2.dts
index 582acb681a..bd3553dd20 100644
--- a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c2.dts
+++ b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -5,7 +5,7 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
- compatible = "qcom,ipq4019-ap-dk07.1-c2";
+ compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019";
soc {
pinctrl@1000000 {
diff --git a/dts/src/arm/qcom-ipq8064-ap148.dts b/dts/src/arm/qcom-ipq8064-ap148.dts
index e5b9b9cf60..b63d01d101 100644
--- a/dts/src/arm/qcom-ipq8064-ap148.dts
+++ b/dts/src/arm/qcom-ipq8064-ap148.dts
@@ -3,7 +3,7 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
- compatible = "qcom,ipq8064-ap148";
+ compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
soc {
pinmux@800000 {
diff --git a/dts/src/arm/qcom-ipq8064-rb3011.dts b/dts/src/arm/qcom-ipq8064-rb3011.dts
index f7ea2e5dd1..596d129d4a 100644
--- a/dts/src/arm/qcom-ipq8064-rb3011.dts
+++ b/dts/src/arm/qcom-ipq8064-rb3011.dts
@@ -19,12 +19,12 @@
stdout-path = "serial0:115200n8";
};
- memory@0 {
+ memory@42000000 {
reg = <0x42000000 0x3e000000>;
device_type = "memory";
};
- mdio0: mdio@0 {
+ mdio0: mdio-0 {
status = "okay";
compatible = "virtual,mdio-gpio";
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
@@ -91,7 +91,7 @@
};
};
- mdio1: mdio@1 {
+ mdio1: mdio-1 {
status = "okay";
compatible = "virtual,mdio-gpio";
gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>,
@@ -172,7 +172,7 @@
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
- norflash: s25fl016k@0 {
+ norflash: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/qcom-ipq8064.dtsi b/dts/src/arm/qcom-ipq8064.dtsi
index 4139d3817b..11481313bd 100644
--- a/dts/src/arm/qcom-ipq8064.dtsi
+++ b/dts/src/arm/qcom-ipq8064.dtsi
@@ -49,7 +49,7 @@
};
thermal-zones {
- tsens_tz_sensor0 {
+ sensor0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 0>;
@@ -69,7 +69,7 @@
};
};
- tsens_tz_sensor1 {
+ sensor1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 1>;
@@ -89,7 +89,7 @@
};
};
- tsens_tz_sensor2 {
+ sensor2-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 2>;
@@ -109,7 +109,7 @@
};
};
- tsens_tz_sensor3 {
+ sensor3-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 3>;
@@ -129,7 +129,7 @@
};
};
- tsens_tz_sensor4 {
+ sensor4-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 4>;
@@ -149,7 +149,7 @@
};
};
- tsens_tz_sensor5 {
+ sensor5-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 5>;
@@ -169,7 +169,7 @@
};
};
- tsens_tz_sensor6 {
+ sensor6-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 6>;
@@ -189,7 +189,7 @@
};
};
- tsens_tz_sensor7 {
+ sensor7-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 7>;
@@ -209,7 +209,7 @@
};
};
- tsens_tz_sensor8 {
+ sensor8-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 8>;
@@ -229,7 +229,7 @@
};
};
- tsens_tz_sensor9 {
+ sensor9-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 9>;
@@ -249,7 +249,7 @@
};
};
- tsens_tz_sensor10 {
+ sensor10-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 10>;
@@ -1181,7 +1181,7 @@
#size-cells = <1>;
ranges;
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -1201,7 +1201,7 @@
dma-names = "tx", "rx";
};
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
diff --git a/dts/src/arm/qcom-mdm9615-wp8548.dtsi b/dts/src/arm/qcom-mdm9615-wp8548.dtsi
index a725b73b5a..10ad929759 100644
--- a/dts/src/arm/qcom-mdm9615-wp8548.dtsi
+++ b/dts/src/arm/qcom-mdm9615-wp8548.dtsi
@@ -49,7 +49,7 @@
model = "Sierra Wireless WP8548 Module";
compatible = "swir,wp8548", "qcom,mdm9615";
- memory {
+ memory@48000000 {
device_type = "memory";
reg = <0x48000000 0x7F00000>;
};
diff --git a/dts/src/arm/qcom-mdm9615.dtsi b/dts/src/arm/qcom-mdm9615.dtsi
index dda2ceec65..c32415f0e6 100644
--- a/dts/src/arm/qcom-mdm9615.dtsi
+++ b/dts/src/arm/qcom-mdm9615.dtsi
@@ -300,18 +300,14 @@
pull-up;
};
- pmicmpp: mpp@50 {
+ pmicmpp: mpps@50 {
compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
- interrupt-parent = <&pmicintc>;
- interrupts = <24 IRQ_TYPE_NONE>,
- <25 IRQ_TYPE_NONE>,
- <26 IRQ_TYPE_NONE>,
- <27 IRQ_TYPE_NONE>,
- <28 IRQ_TYPE_NONE>,
- <29 IRQ_TYPE_NONE>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x50>;
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pmicmpp 0 0 6>;
};
rtc@11d {
@@ -358,7 +354,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sdcc1: sdcc@12180000 {
+ sdcc1: mmc@12180000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -378,7 +374,7 @@
assigned-clock-rates = <400000>;
};
- sdcc2: sdcc@12140000 {
+ sdcc2: mmc@12140000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
diff --git a/dts/src/arm/qcom-msm8226.dtsi b/dts/src/arm/qcom-msm8226.dtsi
index 2de69d5687..7d48599502 100644
--- a/dts/src/arm/qcom-msm8226.dtsi
+++ b/dts/src/arm/qcom-msm8226.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
@@ -20,6 +21,70 @@
reg = <0x0 0x0>;
};
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8226", "qcom,scm";
+ clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ };
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x80>;
+
+ #hwlock-cells = <1>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem_region: smem@3000000 {
+ reg = <0x3000000 0x100000>;
+ no-map;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8226";
+ qcom,smd-channels = "rpm_requests";
+ };
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -34,6 +99,136 @@
#interrupt-cells = <3>;
};
+ apcs: syscon@f9011000 {
+ compatible = "syscon";
+ reg = <0xf9011000 0x1000>;
+ };
+
+ sdhc_1: sdhci@f9824900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@f98a4900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ sdhc_3: sdhci@f9864900 {
+ compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC3_APPS_CLK>,
+ <&gcc GCC_SDCC3_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
+ blsp1_uart3: serial@f991f000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991f000 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart4: serial@f9920000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf9920000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_i2c1: i2c@f9923000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9923000 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c2: i2c@f9924000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9924000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c3: i2c@f9925000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9925000 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c3_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c4: i2c@f9926000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9926000 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c4_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c5: i2c@f9927000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9927000 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_i2c5_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
@@ -51,15 +246,41 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- };
- blsp1_uart3: serial@f991f000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991f000 0x1000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
+ blsp1_i2c1_pins: blsp1-i2c1 {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c2_pins: blsp1-i2c2 {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c3_pins: blsp1-i2c3 {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c4_pins: blsp1-i2c4 {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c5_pins: blsp1-i2c5 {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
restart@fc4ab000 {
@@ -67,6 +288,22 @@
reg = <0xfc4ab000 0x4>;
};
+ spmi_bus: spmi@fc4cf000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
@@ -131,6 +368,16 @@
status = "disabled";
};
};
+
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+
+ tcsr_mutex_block: syscon@fd484000 {
+ compatible = "syscon";
+ reg = <0xfd484000 0x2000>;
+ };
};
timer {
diff --git a/dts/src/arm/qcom-msm8660-surf.dts b/dts/src/arm/qcom-msm8660-surf.dts
index 6a321ccb0b..414280d9bd 100644
--- a/dts/src/arm/qcom-msm8660-surf.dts
+++ b/dts/src/arm/qcom-msm8660-surf.dts
@@ -35,13 +35,13 @@
amba {
/* eMMC */
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "okay";
vmmc-supply = <&vsdcc_fixed>;
};
/* External micro SD card */
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&vsdcc_fixed>;
};
diff --git a/dts/src/arm/qcom-msm8660.dtsi b/dts/src/arm/qcom-msm8660.dtsi
index 480fc08cbe..1e8aab357f 100644
--- a/dts/src/arm/qcom-msm8660.dtsi
+++ b/dts/src/arm/qcom-msm8660.dtsi
@@ -307,20 +307,9 @@
reg = <0x50>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&pm8058>;
- interrupts =
- <128 IRQ_TYPE_NONE>,
- <129 IRQ_TYPE_NONE>,
- <130 IRQ_TYPE_NONE>,
- <131 IRQ_TYPE_NONE>,
- <132 IRQ_TYPE_NONE>,
- <133 IRQ_TYPE_NONE>,
- <134 IRQ_TYPE_NONE>,
- <135 IRQ_TYPE_NONE>,
- <136 IRQ_TYPE_NONE>,
- <137 IRQ_TYPE_NONE>,
- <138 IRQ_TYPE_NONE>,
- <139 IRQ_TYPE_NONE>;
+ gpio-ranges = <&pm8058_mpps 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
pwrkey@1c {
@@ -494,7 +483,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -510,7 +499,7 @@
cap-mmc-highspeed;
};
- sdcc2: sdcc@12140000 {
+ sdcc2: mmc@12140000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -525,7 +514,7 @@
cap-mmc-highspeed;
};
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
@@ -541,7 +530,7 @@
no-1-8-v;
};
- sdcc4: sdcc@121c0000 {
+ sdcc4: mmc@121c0000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
@@ -556,7 +545,7 @@
cap-mmc-highspeed;
};
- sdcc5: sdcc@12200000 {
+ sdcc5: mmc@12200000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
diff --git a/dts/src/arm/qcom-msm8916-samsung-serranove.dts b/dts/src/arm/qcom-msm8916-samsung-serranove.dts
new file mode 100644
index 0000000000..dee2c20af3
--- /dev/null
+++ b/dts/src/arm/qcom-msm8916-samsung-serranove.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "arm64/qcom/msm8916-samsung-serranove.dts"
+#include "qcom-msm8916-smp.dtsi"
diff --git a/dts/src/arm/qcom-msm8916-smp.dtsi b/dts/src/arm/qcom-msm8916-smp.dtsi
new file mode 100644
index 0000000000..36328dbe42
--- /dev/null
+++ b/dts/src/arm/qcom-msm8916-smp.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/ {
+ cpus {
+ cpu@0 {
+ enable-method = "qcom,msm8916-smp";
+ };
+ cpu@1 {
+ enable-method = "qcom,msm8916-smp";
+ };
+ cpu@2 {
+ enable-method = "qcom,msm8916-smp";
+ };
+ cpu@3 {
+ enable-method = "qcom,msm8916-smp";
+ };
+
+ idle-states {
+ /delete-property/ entry-method;
+ };
+ };
+
+ psci {
+ status = "disabled";
+ };
+};
+
+&CPU_SLEEP_0 {
+ compatible = "qcom,idle-state-spc";
+};
+
+&cpu0_acc {
+ status = "okay";
+};
+
+&cpu0_saw {
+ status = "okay";
+};
+
+&cpu1_acc {
+ status = "okay";
+};
+
+&cpu1_saw {
+ status = "okay";
+};
+
+&cpu2_acc {
+ status = "okay";
+};
+
+&cpu2_saw {
+ status = "okay";
+};
+
+&cpu3_acc {
+ status = "okay";
+};
+
+&cpu3_saw {
+ status = "okay";
+};
diff --git a/dts/src/arm/qcom-msm8960-cdp.dts b/dts/src/arm/qcom-msm8960-cdp.dts
index e7d2e937ea..4af01039c3 100644
--- a/dts/src/arm/qcom-msm8960-cdp.dts
+++ b/dts/src/arm/qcom-msm8960-cdp.dts
@@ -26,12 +26,12 @@
amba {
/* eMMC */
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "okay";
};
/* External micro SD card */
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
status = "okay";
};
};
diff --git a/dts/src/arm/qcom-msm8960.dtsi b/dts/src/arm/qcom-msm8960.dtsi
index 172ea3c70e..2a0ec97a26 100644
--- a/dts/src/arm/qcom-msm8960.dtsi
+++ b/dts/src/arm/qcom-msm8960.dtsi
@@ -263,7 +263,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sdcc1: sdcc@12400000 {
+ sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -280,7 +280,7 @@
vmmc-supply = <&vsdcc_fixed>;
};
- sdcc3: sdcc@12180000 {
+ sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi
index 78ec496d5b..412d94736c 100644
--- a/dts/src/arm/qcom-msm8974.dtsi
+++ b/dts/src/arm/qcom-msm8974.dtsi
@@ -142,7 +142,7 @@
};
thermal-zones {
- cpu-thermal0 {
+ cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -162,7 +162,7 @@
};
};
- cpu-thermal1 {
+ cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -182,7 +182,7 @@
};
};
- cpu-thermal2 {
+ cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -202,7 +202,7 @@
};
};
- cpu-thermal3 {
+ cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -282,7 +282,7 @@
};
};
- gpu-thermal-top {
+ gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -297,7 +297,7 @@
};
};
- gpu-thermal-bottom {
+ gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1589,8 +1589,8 @@
#phy-cells = <0>;
qcom,dsi-phy-index = <0>;
- clocks = <&mmcc MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
};
};
diff --git a/dts/src/arm/qcom-pm8226.dtsi b/dts/src/arm/qcom-pm8226.dtsi
new file mode 100644
index 0000000000..dddb5150df
--- /dev/null
+++ b/dts/src/arm/qcom-pm8226.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm8226_0: pm8226@0 {
+ compatible = "qcom,pm8226", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@800 {
+ compatible = "qcom,pm8941-pwrkey";
+ reg = <0x800>;
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ };
+ };
+
+ pm8226_1: pm8226@1 {
+ compatible = "qcom,pm8226", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/dts/src/arm/qcom-pm8841.dtsi b/dts/src/arm/qcom-pm8841.dtsi
index 2fd59c4409..2caf71eacb 100644
--- a/dts/src/arm/qcom-pm8841.dtsi
+++ b/dts/src/arm/qcom-pm8841.dtsi
@@ -15,10 +15,9 @@
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <4 0xa0 0 IRQ_TYPE_NONE>,
- <4 0xa1 0 IRQ_TYPE_NONE>,
- <4 0xa2 0 IRQ_TYPE_NONE>,
- <4 0xa3 0 IRQ_TYPE_NONE>;
+ gpio-ranges = <&pm8841_mpps 0 0 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
temp-alarm@2400 {
diff --git a/dts/src/arm/qcom-pm8941.dtsi b/dts/src/arm/qcom-pm8941.dtsi
index c1f2012d1c..da00b8f5ee 100644
--- a/dts/src/arm/qcom-pm8941.dtsi
+++ b/dts/src/arm/qcom-pm8941.dtsi
@@ -79,14 +79,9 @@
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
- <0 0xa1 0 IRQ_TYPE_NONE>,
- <0 0xa2 0 IRQ_TYPE_NONE>,
- <0 0xa3 0 IRQ_TYPE_NONE>,
- <0 0xa4 0 IRQ_TYPE_NONE>,
- <0 0xa5 0 IRQ_TYPE_NONE>,
- <0 0xa6 0 IRQ_TYPE_NONE>,
- <0 0xa7 0 IRQ_TYPE_NONE>;
+ gpio-ranges = <&pm8941_mpps 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
pm8941_temp: temp-alarm@2400 {
diff --git a/dts/src/arm/qcom-pma8084.dtsi b/dts/src/arm/qcom-pma8084.dtsi
index e921c5e93a..7b8a8d9695 100644
--- a/dts/src/arm/qcom-pma8084.dtsi
+++ b/dts/src/arm/qcom-pma8084.dtsi
@@ -42,14 +42,9 @@
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
- <0 0xa1 0 IRQ_TYPE_NONE>,
- <0 0xa2 0 IRQ_TYPE_NONE>,
- <0 0xa3 0 IRQ_TYPE_NONE>,
- <0 0xa4 0 IRQ_TYPE_NONE>,
- <0 0xa5 0 IRQ_TYPE_NONE>,
- <0 0xa6 0 IRQ_TYPE_NONE>,
- <0 0xa7 0 IRQ_TYPE_NONE>;
+ gpio-ranges = <&pma8084_mpps 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
pma8084_temp: temp-alarm@2400 {
diff --git a/dts/src/arm/qcom-sdx55.dtsi b/dts/src/arm/qcom-sdx55.dtsi
index 1e6ce035f7..44526ad9d2 100644
--- a/dts/src/arm/qcom-sdx55.dtsi
+++ b/dts/src/arm/qcom-sdx55.dtsi
@@ -228,7 +228,6 @@
compatible = "qcom,sdx55-qmp-usb3-uni-phy";
reg = <0x00ff6000 0x1c0>;
status = "disabled";
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
diff --git a/dts/src/arm/r7s72100-genmai.dts b/dts/src/arm/r7s72100-genmai.dts
index 07d611d2b7..1e8447176b 100644
--- a/dts/src/arm/r7s72100-genmai.dts
+++ b/dts/src/arm/r7s72100-genmai.dts
@@ -108,6 +108,8 @@
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-idb824.2814",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
diff --git a/dts/src/arm/r7s72100-gr-peach.dts b/dts/src/arm/r7s72100-gr-peach.dts
index 2562cc9b53..105f9c71f9 100644
--- a/dts/src/arm/r7s72100-gr-peach.dts
+++ b/dts/src/arm/r7s72100-gr-peach.dts
@@ -129,6 +129,8 @@
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/src/arm/r7s72100-rskrza1.dts b/dts/src/arm/r7s72100-rskrza1.dts
index 99acfe4fe1..1c5acf6944 100644
--- a/dts/src/arm/r7s72100-rskrza1.dts
+++ b/dts/src/arm/r7s72100-rskrza1.dts
@@ -192,6 +192,8 @@
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-idb824.2814",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
diff --git a/dts/src/arm/r7s9210-rza2mevb.dts b/dts/src/arm/r7s9210-rza2mevb.dts
index 68498ce2ae..9c0d9686fe 100644
--- a/dts/src/arm/r7s9210-rza2mevb.dts
+++ b/dts/src/arm/r7s9210-rza2mevb.dts
@@ -100,6 +100,8 @@
renesas,no-ether-link;
phy-handle = <&phy1>;
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c816",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
@@ -109,6 +111,20 @@
clock-frequency = <24000000>; /* 24MHz */
};
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24128", "atmel,24c128";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
/* High resolution System tick timers */
&ostm0 {
status = "okay";
@@ -147,6 +163,11 @@
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
};
+ i2c3_pins: i2c3 {
+ pinmux = <RZA2_PINMUX(PORTD, 6, 1)>, /* RIIC3SCL */
+ <RZA2_PINMUX(PORTD, 7, 1)>; /* RIIC3SDA */
+ };
+
keyboard_pins: keyboard {
pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>; /* IRQ0 */
};
diff --git a/dts/src/arm/r8a73a4-ape6evm.dts b/dts/src/arm/r8a73a4-ape6evm.dts
index b088e8e351..e81a7213d3 100644
--- a/dts/src/arm/r8a73a4-ape6evm.dts
+++ b/dts/src/arm/r8a73a4-ape6evm.dts
@@ -199,6 +199,7 @@
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
+ reset-gpios = <&pfc 270 GPIO_ACTIVE_LOW>;
vdd33a-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_1v8>;
};
diff --git a/dts/src/arm/r8a7740-armadillo800eva.dts b/dts/src/arm/r8a7740-armadillo800eva.dts
index d960c2767f..a01f3def1c 100644
--- a/dts/src/arm/r8a7740-armadillo800eva.dts
+++ b/dts/src/arm/r8a7740-armadillo800eva.dts
@@ -170,7 +170,10 @@
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f1",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ reset-gpios = <&pfc 18 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/src/arm/r8a7742-iwg21d-q7-dbcm-ca.dts b/dts/src/arm/r8a7742-iwg21d-q7-dbcm-ca.dts
index 2bcb229844..33db5938f2 100644
--- a/dts/src/arm/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/dts/src/arm/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -66,6 +66,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1560",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
micrel,led-mode = <1>;
};
diff --git a/dts/src/arm/r8a7742-iwg21d-q7.dts b/dts/src/arm/r8a7742-iwg21d-q7.dts
index 94bf8a116b..a5a79cdbcd 100644
--- a/dts/src/arm/r8a7742-iwg21d-q7.dts
+++ b/dts/src/arm/r8a7742-iwg21d-q7.dts
@@ -175,6 +175,8 @@
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
diff --git a/dts/src/arm/r8a7743-sk-rzg1m.dts b/dts/src/arm/r8a7743-sk-rzg1m.dts
index 4ace117470..ff274bfcb6 100644
--- a/dts/src/arm/r8a7743-sk-rzg1m.dts
+++ b/dts/src/arm/r8a7743-sk-rzg1m.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a7743.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "SK-RZG1M";
@@ -69,9 +70,12 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/src/arm/r8a7745-iwg22d-sodimm.dts b/dts/src/arm/r8a7745-iwg22d-sodimm.dts
index 73bd62d8a9..c105932f64 100644
--- a/dts/src/arm/r8a7745-iwg22d-sodimm.dts
+++ b/dts/src/arm/r8a7745-iwg22d-sodimm.dts
@@ -123,6 +123,8 @@
* On some older versions of the platform (before R4.0) the phy address
* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
*/
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
micrel,led-mode = <1>;
};
diff --git a/dts/src/arm/r8a7745-sk-rzg1e.dts b/dts/src/arm/r8a7745-sk-rzg1e.dts
index 59d1a9bfab..0a75e8c79a 100644
--- a/dts/src/arm/r8a7745-sk-rzg1e.dts
+++ b/dts/src/arm/r8a7745-sk-rzg1e.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a7745.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "SK-RZG1E";
@@ -64,9 +65,12 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/src/arm/r8a77470-iwg23s-sbc.dts b/dts/src/arm/r8a77470-iwg23s-sbc.dts
index 8ac61b50ae..b024621c99 100644
--- a/dts/src/arm/r8a77470-iwg23s-sbc.dts
+++ b/dts/src/arm/r8a77470-iwg23s-sbc.dts
@@ -79,6 +79,8 @@
status = "okay";
phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7778-bockw.dts b/dts/src/arm/r8a7778-bockw.dts
index 6c7b07c4b9..9b65d246e5 100644
--- a/dts/src/arm/r8a7778-bockw.dts
+++ b/dts/src/arm/r8a7778-bockw.dts
@@ -63,7 +63,7 @@
&bsc {
ethernet@18300000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18300000 0x1000>;
phy-mode = "mii";
diff --git a/dts/src/arm/r8a7779-marzen.dts b/dts/src/arm/r8a7779-marzen.dts
index 4658453234..5f05f2b44a 100644
--- a/dts/src/arm/r8a7779-marzen.dts
+++ b/dts/src/arm/r8a7779-marzen.dts
@@ -52,7 +52,7 @@
};
ethernet@18000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18000000 0x100>;
pinctrl-0 = <&ethernet_pins>;
pinctrl-names = "default";
diff --git a/dts/src/arm/r8a7790-lager.dts b/dts/src/arm/r8a7790-lager.dts
index fa6d986b5d..57cd2fa722 100644
--- a/dts/src/arm/r8a7790-lager.dts
+++ b/dts/src/arm/r8a7790-lager.dts
@@ -678,6 +678,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7790-stout.dts b/dts/src/arm/r8a7790-stout.dts
index d51f23572d..c802f9f13c 100644
--- a/dts/src/arm/r8a7790-stout.dts
+++ b/dts/src/arm/r8a7790-stout.dts
@@ -199,6 +199,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7791-koelsch.dts b/dts/src/arm/r8a7791-koelsch.dts
index 2a8b6fd909..6e691b6cac 100644
--- a/dts/src/arm/r8a7791-koelsch.dts
+++ b/dts/src/arm/r8a7791-koelsch.dts
@@ -637,6 +637,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7791-porter.dts b/dts/src/arm/r8a7791-porter.dts
index c6ef636965..38e2ab9287 100644
--- a/dts/src/arm/r8a7791-porter.dts
+++ b/dts/src/arm/r8a7791-porter.dts
@@ -302,6 +302,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7793-gose.dts b/dts/src/arm/r8a7793-gose.dts
index 479e0fdf0c..c8978f4f62 100644
--- a/dts/src/arm/r8a7793-gose.dts
+++ b/dts/src/arm/r8a7793-gose.dts
@@ -595,6 +595,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7794-alt.dts b/dts/src/arm/r8a7794-alt.dts
index f330d796a7..99d554fe33 100644
--- a/dts/src/arm/r8a7794-alt.dts
+++ b/dts/src/arm/r8a7794-alt.dts
@@ -383,6 +383,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/r8a7794-silk.dts b/dts/src/arm/r8a7794-silk.dts
index cafa3046da..92a7616443 100644
--- a/dts/src/arm/r8a7794-silk.dts
+++ b/dts/src/arm/r8a7794-silk.dts
@@ -397,6 +397,8 @@
status = "okay";
phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1537",
+ "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/rk3036.dtsi b/dts/src/arm/rk3036.dtsi
index ffa9bc7ed3..ba2b8891bb 100644
--- a/dts/src/arm/rk3036.dtsi
+++ b/dts/src/arm/rk3036.dtsi
@@ -416,8 +416,8 @@
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
pwm0: pwm@20050000 {
@@ -575,7 +575,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@2007c000 {
+ gpio0: gpio@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -588,7 +588,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@20080000 {
+ gpio1: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -601,7 +601,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@20084000 {
+ gpio2: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/rk3066a-mk808.dts b/dts/src/arm/rk3066a-mk808.dts
index 9790bc63b5..667d57a4ff 100644
--- a/dts/src/arm/rk3066a-mk808.dts
+++ b/dts/src/arm/rk3066a-mk808.dts
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"
/ {
@@ -24,6 +25,20 @@
device_type = "memory";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <2500000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
@@ -46,6 +61,13 @@
};
};
+ vcc_2v5: vcc-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
@@ -164,6 +186,11 @@
};
};
+&saradc {
+ vref-supply = <&vcc_2v5>;
+ status = "okay";
+};
+
&uart2 {
status = "okay";
};
diff --git a/dts/src/arm/rk3066a.dtsi b/dts/src/arm/rk3066a.dtsi
index ae4055428c..c25b9695db 100644
--- a/dts/src/arm/rk3066a.dtsi
+++ b/dts/src/arm/rk3066a.dtsi
@@ -23,16 +23,15 @@
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 1416000 1300000
- 1200000 1175000
- 1008000 1125000
- 816000 1125000
- 600000 1100000
- 504000 1100000
- 312000 1075000
- >;
+ <1416000 1300000>,
+ <1200000 1175000>,
+ <1008000 1125000>,
+ <816000 1125000>,
+ <600000 1100000>,
+ <504000 1100000>,
+ <312000 1075000>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
@@ -273,7 +272,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@20034000 {
+ gpio0: gpio@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -286,7 +285,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@2003c000 {
+ gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -299,7 +298,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@2003e000 {
+ gpio2: gpio@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -312,7 +311,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@20080000 {
+ gpio3: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -325,7 +324,7 @@
#interrupt-cells = <2>;
};
- gpio4: gpio4@20084000 {
+ gpio4: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -338,7 +337,7 @@
#interrupt-cells = <2>;
};
- gpio6: gpio6@2000a000 {
+ gpio6: gpio@2000a000 {
compatible = "rockchip,gpio-bank";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -682,8 +681,7 @@
compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
usbphy: usbphy {
- compatible = "rockchip,rk3066a-usb-phy",
- "rockchip,rk3288-usb-phy";
+ compatible = "rockchip,rk3066a-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
diff --git a/dts/src/arm/rk3188.dtsi b/dts/src/arm/rk3188.dtsi
index 2c606494b7..a94321e900 100644
--- a/dts/src/arm/rk3188.dtsi
+++ b/dts/src/arm/rk3188.dtsi
@@ -54,7 +54,7 @@
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -223,7 +223,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@2000a000 {
+ gpio0: gpio@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -236,7 +236,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@2003c000 {
+ gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -249,7 +249,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@2003e000 {
+ gpio2: gpio@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -262,7 +262,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@20080000 {
+ gpio3: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -647,8 +647,7 @@
};
usbphy: usbphy {
- compatible = "rockchip,rk3188-usb-phy",
- "rockchip,rk3288-usb-phy";
+ compatible = "rockchip,rk3188-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
diff --git a/dts/src/arm/rk3229.dtsi b/dts/src/arm/rk3229.dtsi
index cb7d3fad8e..c340fb30e7 100644
--- a/dts/src/arm/rk3229.dtsi
+++ b/dts/src/arm/rk3229.dtsi
@@ -10,7 +10,7 @@
/delete-node/ opp-table0;
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
diff --git a/dts/src/arm/rk322x.dtsi b/dts/src/arm/rk322x.dtsi
index 75af99c76d..8eed9e3a92 100644
--- a/dts/src/arm/rk322x.dtsi
+++ b/dts/src/arm/rk322x.dtsi
@@ -68,7 +68,7 @@
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -477,8 +477,8 @@
compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
cru: clock-controller@110e0000 {
@@ -946,7 +946,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@11110000 {
+ gpio0: gpio@11110000 {
compatible = "rockchip,gpio-bank";
reg = <0x11110000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -959,7 +959,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@11120000 {
+ gpio1: gpio@11120000 {
compatible = "rockchip,gpio-bank";
reg = <0x11120000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -972,7 +972,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@11130000 {
+ gpio2: gpio@11130000 {
compatible = "rockchip,gpio-bank";
reg = <0x11130000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -985,7 +985,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@11140000 {
+ gpio3: gpio@11140000 {
compatible = "rockchip,gpio-bank";
reg = <0x11140000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi
index 4dcdcf17c9..aaaa618757 100644
--- a/dts/src/arm/rk3288.dtsi
+++ b/dts/src/arm/rk3288.dtsi
@@ -100,7 +100,7 @@
};
};
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -1278,7 +1278,7 @@
status = "disabled";
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-100000000 {
@@ -1422,7 +1422,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff750000 {
+ gpio0: gpio@ff750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff750000 0x0 0x100>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -1435,7 +1435,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff780000 {
+ gpio1: gpio@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -1448,7 +1448,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff790000 {
+ gpio2: gpio@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -1461,7 +1461,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff7a0000 {
+ gpio3: gpio@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7a0000 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -1474,7 +1474,7 @@
#interrupt-cells = <2>;
};
- gpio4: gpio4@ff7b0000 {
+ gpio4: gpio@ff7b0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7b0000 0x0 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -1487,7 +1487,7 @@
#interrupt-cells = <2>;
};
- gpio5: gpio5@ff7c0000 {
+ gpio5: gpio@ff7c0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7c0000 0x0 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -1500,7 +1500,7 @@
#interrupt-cells = <2>;
};
- gpio6: gpio6@ff7d0000 {
+ gpio6: gpio@ff7d0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7d0000 0x0 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
@@ -1513,7 +1513,7 @@
#interrupt-cells = <2>;
};
- gpio7: gpio7@ff7e0000 {
+ gpio7: gpio@ff7e0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7e0000 0x0 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -1526,7 +1526,7 @@
#interrupt-cells = <2>;
};
- gpio8: gpio8@ff7f0000 {
+ gpio8: gpio@ff7f0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7f0000 0x0 0x100>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/rv1108.dtsi b/dts/src/arm/rv1108.dtsi
index 24d56849af..4482549064 100644
--- a/dts/src/arm/rv1108.dtsi
+++ b/dts/src/arm/rv1108.dtsi
@@ -40,7 +40,7 @@
};
};
- cpu_opp_table: opp_table {
+ cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-408000000 {
@@ -300,8 +300,8 @@
compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
reg = <0x10350000 0x20>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
watchdog: watchdog@10360000 {
@@ -557,7 +557,7 @@
status = "disabled";
};
- gmac: eth@30200000 {
+ gmac: ethernet@30200000 {
compatible = "rockchip,rv1108-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -600,7 +600,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@20030000 {
+ gpio0: gpio@20030000 {
compatible = "rockchip,gpio-bank";
reg = <0x20030000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
@@ -613,7 +613,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@10310000 {
+ gpio1: gpio@10310000 {
compatible = "rockchip,gpio-bank";
reg = <0x10310000 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
@@ -626,7 +626,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@10320000 {
+ gpio2: gpio@10320000 {
compatible = "rockchip,gpio-bank";
reg = <0x10320000 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
@@ -639,7 +639,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@10330000 {
+ gpio3: gpio@10330000 {
compatible = "rockchip,gpio-bank";
reg = <0x10330000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm/s5pv210-fascinate4g.dts b/dts/src/arm/s5pv210-fascinate4g.dts
index b47d8300e5..7427c84f11 100644
--- a/dts/src/arm/s5pv210-fascinate4g.dts
+++ b/dts/src/arm/s5pv210-fascinate4g.dts
@@ -8,6 +8,7 @@
/ {
model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210";
compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210";
+ chassis-type = "handset";
chosen {
stdout-path = &uart2;
diff --git a/dts/src/arm/s5pv210-galaxys.dts b/dts/src/arm/s5pv210-galaxys.dts
index 560f830b6f..eeec2bdece 100644
--- a/dts/src/arm/s5pv210-galaxys.dts
+++ b/dts/src/arm/s5pv210-galaxys.dts
@@ -8,6 +8,7 @@
/ {
model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210";
compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210";
+ chassis-type = "handset";
chosen {
stdout-path = &uart2;
diff --git a/dts/src/arm/sama5d29.dtsi b/dts/src/arm/sama5d29.dtsi
new file mode 100644
index 0000000000..17991c28a2
--- /dev/null
+++ b/dts/src/arm/sama5d29.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama5d29.dtsi - Device Tree Include file for SAMA5D29 SoC of the SAMA5D2
+ * family.
+ *
+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
+ *
+ * Author: Hari Prasath <Hari.PrasathGE@microchip.com>
+ *
+ */
+
+#include "sama5d2.dtsi"
+
+&macb0 {
+ compatible = "atmel,sama5d29-gem";
+};
diff --git a/dts/src/arm/sama7g5.dtsi b/dts/src/arm/sama7g5.dtsi
index 6c58c151c6..7039311bf6 100644
--- a/dts/src/arm/sama7g5.dtsi
+++ b/dts/src/arm/sama7g5.dtsi
@@ -152,6 +152,13 @@
reg = <0xe001d060 0x48>;
};
+ rtc: rtc@e001d0a8 {
+ compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+ reg = <0xe001d0a8 0x30>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk32k 1>;
+ };
+
ps_wdt: watchdog@e001d180 {
compatible = "microchip,sama7g5-wdt";
reg = <0xe001d180 0x24>;
@@ -164,6 +171,32 @@
reg = <0xe0020000 0x8>;
};
+ tcb1: timer@e0800000 {
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe0800000 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ adc: adc@e1000000 {
+ compatible = "microchip,sama7g5-adc";
+ reg = <0xe1000000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clock-rates = <100000000>;
+ clock-names = "adc_clk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
+ dma-names = "rx";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ status = "disabled";
+ };
+
sdmmc0: mmc@e1204000 {
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
reg = <0xe1204000 0x4000>;
@@ -465,6 +498,16 @@
status = "disabled";
};
+ tcb0: timer@e2814000 {
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe2814000 0x100>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
flx8: flexcom@e2818000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe2818000 0x200>;
diff --git a/dts/src/arm/sh73a0-kzm9g.dts b/dts/src/arm/sh73a0-kzm9g.dts
index 5a8d92a061..98897f7100 100644
--- a/dts/src/arm/sh73a0-kzm9g.dts
+++ b/dts/src/arm/sh73a0-kzm9g.dts
@@ -169,7 +169,7 @@
&bsc {
ethernet@10000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
+ compatible = "smsc,lan9221", "smsc,lan9115";
reg = <0x10000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
diff --git a/dts/src/arm/socfpga_arria10_mercury_aa1.dts b/dts/src/arm/socfpga_arria10_mercury_aa1.dts
new file mode 100644
index 0000000000..2a3364b263
--- /dev/null
+++ b/dts/src/arm/socfpga_arria10_mercury_aa1.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "socfpga_arria10.dtsi"
+
+/ {
+
+ model = "Enclustra Mercury AA1";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ serial1 = &uart1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x80000000>; /* 2GB */
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
+
+&eccmgr {
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+
+ max-frame-size = <3800>;
+ status = "okay";
+
+ phy-handle = <&phy3>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy3: ethernet-phy@3 {
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ reg = <3>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ isl12022: isl12022@6f {
+ status = "okay";
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+};
+
+/* Following mappings are taken from arria10 socdk dts */
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+&osc1 {
+ clock-frequency = <33330000>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/dts/src/arm/spear1310.dtsi b/dts/src/arm/spear1310.dtsi
index c4b49baf98..2f746a9428 100644
--- a/dts/src/arm/spear1310.dtsi
+++ b/dts/src/arm/spear1310.dtsi
@@ -82,8 +82,6 @@
reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
reg-names = "dbi", "config";
interrupts = <0 68 0x4>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 0 68 0x4>;
num-lanes = <1>;
phys = <&miphy0 1>;
phy-names = "pcie-phy";
@@ -101,8 +99,6 @@
reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
reg-names = "dbi", "config";
interrupts = <0 69 0x4>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 0 69 0x4>;
num-lanes = <1>;
phys = <&miphy1 1>;
phy-names = "pcie-phy";
@@ -120,8 +116,6 @@
reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
reg-names = "dbi", "config";
interrupts = <0 70 0x4>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 0 70 0x4>;
num-lanes = <1>;
phys = <&miphy2 1>;
phy-names = "pcie-phy";
diff --git a/dts/src/arm/spear1340.dtsi b/dts/src/arm/spear1340.dtsi
index 1a8f5e8b10..827e887afb 100644
--- a/dts/src/arm/spear1340.dtsi
+++ b/dts/src/arm/spear1340.dtsi
@@ -47,8 +47,6 @@
reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
reg-names = "dbi", "config";
interrupts = <0 68 0x4>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 0 68 0x4>;
num-lanes = <1>;
phys = <&miphy0 1>;
phy-names = "pcie-phy";
diff --git a/dts/src/arm/ste-ab8500.dtsi b/dts/src/arm/ste-ab8500.dtsi
index 9baf927f9b..2cf19386a5 100644
--- a/dts/src/arm/ste-ab8500.dtsi
+++ b/dts/src/arm/ste-ab8500.dtsi
@@ -129,11 +129,6 @@
io-channel-names = "aux1", "aux2";
};
- ab8500_battery: ab8500_battery {
- stericsson,battery-type = "LIPO";
- thermistor-on-batctrl;
- };
-
ab8500_fg {
compatible = "stericsson,ab8500-fg";
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
@@ -146,7 +141,7 @@
"LOW_BAT_F",
"CC_INT_CALIB",
"CCEOC";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x08>;
io-channel-names = "main_bat_v";
};
@@ -163,7 +158,7 @@
"BTEMP_HIGH",
"BTEMP_LOW_MEDIUM",
"BTEMP_MEDIUM_HIGH";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
io-channel-names = "btemp_ball",
@@ -200,7 +195,7 @@
"VBUS_OVV",
"CH_WD_EXP",
"VBUS_CH_DROP_END";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
vddadc-supply = <&ab8500_ldo_tvout_reg>;
io-channels = <&gpadc 0x03>,
<&gpadc 0x0a>,
@@ -214,7 +209,7 @@
ab8500_chargalg {
compatible = "stericsson,ab8500-chargalg";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
};
ab8500_usb: ab8500_usb {
diff --git a/dts/src/arm/ste-ab8505.dtsi b/dts/src/arm/ste-ab8505.dtsi
index 8d018701a6..e98335e9d1 100644
--- a/dts/src/arm/ste-ab8505.dtsi
+++ b/dts/src/arm/ste-ab8505.dtsi
@@ -92,11 +92,6 @@
};
};
- ab8500_battery: ab8500_battery {
- stericsson,battery-type = "LIPO";
- thermistor-on-batctrl;
- };
-
ab8500_fg {
status = "disabled";
compatible = "stericsson,ab8500-fg";
@@ -110,7 +105,7 @@
"LOW_BAT_F",
"CC_INT_CALIB",
"CCEOC";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x08>;
io-channel-names = "main_bat_v";
};
@@ -128,7 +123,7 @@
"BTEMP_HIGH",
"BTEMP_LOW_MEDIUM",
"BTEMP_MEDIUM_HIGH";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
io-channels = <&gpadc 0x02>,
<&gpadc 0x01>;
io-channel-names = "btemp_ball",
@@ -166,7 +161,7 @@
"VBUS_OVV",
"CH_WD_EXP",
"VBUS_CH_DROP_END";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
vddadc-supply = <&ab8500_ldo_adc_reg>;
io-channels = <&gpadc 0x09>,
<&gpadc 0x0b>;
@@ -177,7 +172,7 @@
ab8500_chargalg {
status = "disabled";
compatible = "stericsson,ab8500-chargalg";
- battery = <&ab8500_battery>;
+ monitored-battery = <&battery>;
};
ab8500_usb: ab8500_usb {
diff --git a/dts/src/arm/ste-href.dtsi b/dts/src/arm/ste-href.dtsi
index 961f2c7274..718752a024 100644
--- a/dts/src/arm/ste-href.dtsi
+++ b/dts/src/arm/ste-href.dtsi
@@ -13,6 +13,12 @@
reg = <0x00000000 0x20000000>;
};
+ battery: battery {
+ compatib