diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
| commit | bfbf18d991756858337f7700e8ff0a6f0dc31afc (patch) | |
| tree | cf3568de4fdff1891e277507f08f49a871682706 /dts/src | |
| parent | 834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff) | |
| download | barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz | |
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src')
510 files changed, 26106 insertions, 6558 deletions
diff --git a/dts/src/arc/abilis_tb100_dvk.dts b/dts/src/arc/abilis_tb100_dvk.dts index 3dd6ed9414..3acf04db80 100644 --- a/dts/src/arc/abilis_tb100_dvk.dts +++ b/dts/src/arc/abilis_tb100_dvk.dts @@ -24,6 +24,7 @@ /include/ "abilis_tb100.dtsi" / { + model = "abilis,tb100"; chosen { bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8"; }; diff --git a/dts/src/arc/abilis_tb101_dvk.dts b/dts/src/arc/abilis_tb101_dvk.dts index 1cf51c280f..37d88c5dd1 100644 --- a/dts/src/arc/abilis_tb101_dvk.dts +++ b/dts/src/arc/abilis_tb101_dvk.dts @@ -24,6 +24,7 @@ /include/ "abilis_tb101.dtsi" / { + model = "abilis,tb101"; chosen { bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8"; }; diff --git a/dts/src/arc/axs101.dts b/dts/src/arc/axs101.dts index 3f9b0582e7..d9b9b9dcfc 100644 --- a/dts/src/arc/axs101.dts +++ b/dts/src/arc/axs101.dts @@ -13,6 +13,7 @@ /include/ "axs10x_mb.dtsi" / { + model = "snps,axs101"; compatible = "snps,axs101", "snps,arc-sdp"; chosen { diff --git a/dts/src/arc/axs103.dts b/dts/src/arc/axs103.dts index e6d0e31ea2..ec7fb277a0 100644 --- a/dts/src/arc/axs103.dts +++ b/dts/src/arc/axs103.dts @@ -16,6 +16,7 @@ /include/ "axs10x_mb.dtsi" / { + model = "snps,axs103"; compatible = "snps,axs103", "snps,arc-sdp"; chosen { diff --git a/dts/src/arc/axs103_idu.dts b/dts/src/arc/axs103_idu.dts index f999fef5a6..070c297822 100644 --- a/dts/src/arc/axs103_idu.dts +++ b/dts/src/arc/axs103_idu.dts @@ -16,6 +16,7 @@ /include/ "axs10x_mb.dtsi" / { + model = "snps,axs103-smp"; compatible = "snps,axs103", "snps,arc-sdp"; chosen { diff --git a/dts/src/arc/nsim_700.dts b/dts/src/arc/nsim_700.dts index 63970513e4..ce0ccd20b5 100644 --- a/dts/src/arc/nsim_700.dts +++ b/dts/src/arc/nsim_700.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" / { + model = "snps,nsim"; compatible = "snps,nsim"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arc/nsim_hs.dts b/dts/src/arc/nsim_hs.dts index bf05fe5f67..3772c40c24 100644 --- a/dts/src/arc/nsim_hs.dts +++ b/dts/src/arc/nsim_hs.dts @@ -10,6 +10,7 @@ /include/ "skeleton_hs.dtsi" / { + model = "snps,nsim_hs"; compatible = "snps,nsim_hs"; #address-cells = <2>; #size-cells = <2>; diff --git a/dts/src/arc/nsim_hs_idu.dts b/dts/src/arc/nsim_hs_idu.dts index 99eabe1a2b..48434d7c44 100644 --- a/dts/src/arc/nsim_hs_idu.dts +++ b/dts/src/arc/nsim_hs_idu.dts @@ -10,6 +10,7 @@ /include/ "skeleton_hs_idu.dtsi" / { + model = "snps,nsim_hs-smp"; compatible = "snps,nsim_hs"; interrupt-parent = <&core_intc>; diff --git a/dts/src/arc/nsimosci.dts b/dts/src/arc/nsimosci.dts index e659a340ca..bcf603142a 100644 --- a/dts/src/arc/nsimosci.dts +++ b/dts/src/arc/nsimosci.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" / { + model = "snps,nsimosci"; compatible = "snps,nsimosci"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arc/nsimosci_hs.dts b/dts/src/arc/nsimosci_hs.dts index 16ce5d65cf..14a727cbf4 100644 --- a/dts/src/arc/nsimosci_hs.dts +++ b/dts/src/arc/nsimosci_hs.dts @@ -10,6 +10,7 @@ /include/ "skeleton_hs.dtsi" / { + model = "snps,nsimosci_hs"; compatible = "snps,nsimosci_hs"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arc/nsimosci_hs_idu.dts b/dts/src/arc/nsimosci_hs_idu.dts index ce8dfbc30c..cbf65b6cc7 100644 --- a/dts/src/arc/nsimosci_hs_idu.dts +++ b/dts/src/arc/nsimosci_hs_idu.dts @@ -10,6 +10,7 @@ /include/ "skeleton_hs_idu.dtsi" / { + model = "snps,nsimosci_hs-smp"; compatible = "snps,nsimosci_hs"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arc/vdk_hs38.dts b/dts/src/arc/vdk_hs38.dts index 5d803dd2de..3c51103f0c 100644 --- a/dts/src/arc/vdk_hs38.dts +++ b/dts/src/arc/vdk_hs38.dts @@ -13,6 +13,7 @@ /include/ "vdk_axs10x_mb.dtsi" / { + model = "snps,vdk_archs"; compatible = "snps,axs103"; chosen { diff --git a/dts/src/arc/vdk_hs38_smp.dts b/dts/src/arc/vdk_hs38_smp.dts index 2ba60c399d..6be68001a6 100644 --- a/dts/src/arc/vdk_hs38_smp.dts +++ b/dts/src/arc/vdk_hs38_smp.dts @@ -13,6 +13,7 @@ /include/ "vdk_axs10x_mb.dtsi" / { + model = "snps,vdk_archs-smp"; compatible = "snps,axs103"; chosen { diff --git a/dts/src/arc/zebu_hs.dts b/dts/src/arc/zebu_hs.dts new file mode 100644 index 0000000000..1c1324e849 --- /dev/null +++ b/dts/src/arc/zebu_hs.dts @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs.dtsi" + +/ { + model = "snps,zebu_hs"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@f0000000 { + compatible = "ns8250"; + reg = <0xf0000000 0x2000>; + interrupts = <24>; + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/zebu_hs_idu.dts b/dts/src/arc/zebu_hs_idu.dts new file mode 100644 index 0000000000..65204b4c0f --- /dev/null +++ b/dts/src/arc/zebu_hs_idu.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs_idu.dtsi" + +/ { + model = "snps,zebu_hs-smp"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; /* 50 MHZ */ + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; +/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + /* <hwirq distribution> + distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ + #interrupt-cells = <2>; + interrupts = <24 25 26 27 28 29 30 31>; + + }; + + uart0: serial@f0000000 { + /* compatible = "ns8250"; Doesn't use FIFOs */ + compatible = "ns16550a"; + reg = <0xf0000000 0x2000>; + interrupt-parent = <&idu_intc>; + /* interrupts = <0 1>; DEST=1*/ + /* interrupts = <0 2>; DEST=2*/ + interrupts = <0 0>; /* RR*/ + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi index b689172632..dd45d172a8 100644 --- a/dts/src/arm/am335x-baltos.dtsi +++ b/dts/src/arm/am335x-baltos.dtsi @@ -24,12 +24,12 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -37,7 +37,7 @@ regulator-boot-on; }; - wl12xx_vmmc: fixedregulator@2 { + wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; diff --git a/dts/src/arm/am335x-base0033.dts b/dts/src/arm/am335x-base0033.dts index 58a05f7d0b..c2bee452da 100644 --- a/dts/src/arm/am335x-base0033.dts +++ b/dts/src/arm/am335x-base0033.dts @@ -29,13 +29,13 @@ compatible = "gpio-leds"; - led@0 { + led0 { label = "base:red:user"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ default-state = "off"; }; - led@1 { + led1 { label = "base:green:user"; gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ default-state = "off"; diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi index e247c15e51..007b5e5a51 100644 --- a/dts/src/arm/am335x-bone-common.dtsi +++ b/dts/src/arm/am335x-bone-common.dtsi @@ -13,7 +13,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; @@ -28,28 +28,28 @@ compatible = "gpio-leds"; - led@2 { + led2 { label = "beaglebone:green:heartbeat"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@3 { + led3 { label = "beaglebone:green:mmc0"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@4 { + led4 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@5 { + led5 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; @@ -57,7 +57,7 @@ }; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/am335x-boneblack.dts b/dts/src/arm/am335x-boneblack.dts index ca721670bd..6bbb1fee08 100644 --- a/dts/src/arm/am335x-boneblack.dts +++ b/dts/src/arm/am335x-boneblack.dts @@ -9,6 +9,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +#include <dt-bindings/display/tda998x.h> / { model = "TI AM335x BeagleBone Black"; @@ -33,17 +34,6 @@ status = "okay"; }; -&cpu0_opp_table { - /* - * All PG 2.0 silicon may not support 1GHz but some of the early - * BeagleBone Blacks have PG 2.0 silicon which is guaranteed - * to support 1GHz OPP so enable it for PG 2.0 on this board. - */ - oppnitro@1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < @@ -75,6 +65,16 @@ AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ >; }; + + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; }; &lcdc { @@ -87,16 +87,22 @@ }; &i2c0 { - tda19988 { + tda19988: tda19988 { compatible = "nxp,tda998x"; reg = <0x70>; + pinctrl-names = "default", "off"; pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - port { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; }; }; }; @@ -105,3 +111,49 @@ &rtc { system-power-controller; }; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; +}; diff --git a/dts/src/arm/am335x-chilisom.dtsi b/dts/src/arm/am335x-chilisom.dtsi index 1d647358f1..f9ee5859c1 100644 --- a/dts/src/arm/am335x-chilisom.dtsi +++ b/dts/src/arm/am335x-chilisom.dtsi @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/am335x-cm-t335.dts b/dts/src/arm/am335x-cm-t335.dts index 817b1dec06..947c81b7aa 100644 --- a/dts/src/arm/am335x-cm-t335.dts +++ b/dts/src/arm/am335x-cm-t335.dts @@ -17,7 +17,7 @@ model = "CompuLab CM-T335"; compatible = "compulab,cm-t335", "ti,am33xx"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; @@ -26,7 +26,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&gpio_led_pins>; - led@0 { + led0 { label = "cm_t335:green"; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ linux,default-trigger = "heartbeat"; @@ -34,7 +34,7 @@ }; /* regulator for mmc */ - vmmc_fixed: fixedregulator@0 { + vmmc_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmc_fixed"; regulator-min-microvolt = <3300000>; @@ -42,7 +42,7 @@ }; /* Regulator for WiFi */ - vwlan_fixed: fixedregulator@2 { + vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "vwlan_fixed"; gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts index 5d28712ad2..e82432c79f 100644 --- a/dts/src/arm/am335x-evm.dts +++ b/dts/src/arm/am335x-evm.dts @@ -20,12 +20,12 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -33,13 +33,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wlan_en_reg: fixedregulator@2 { + wlan_en_reg: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; @@ -53,7 +53,7 @@ enable-active-high; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; @@ -73,20 +73,20 @@ 0x0201006c>; /* DOWN */ }; - gpio_keys: volume_keys@0 { + gpio_keys: volume_keys0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; - switch@9 { + switch9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch@10 { + switch10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; @@ -497,6 +497,8 @@ &lcdc { status = "okay"; + + blue-and-red-wiring = "crossed"; }; &elm { diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts index 09308d6664..975c36e332 100644 --- a/dts/src/arm/am335x-evmsk.dts +++ b/dts/src/arm/am335x-evmsk.dts @@ -27,12 +27,12 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -40,13 +40,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wl12xx_vmmc: fixedregulator@2 { + wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; @@ -58,7 +58,7 @@ enable-active-high; }; - vtt_fixed: fixedregulator@3 { + vtt_fixed: fixedregulator3 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; @@ -75,26 +75,26 @@ compatible = "gpio-leds"; - led@1 { + led1 { label = "evmsk:green:usr0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "evmsk:green:usr1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "evmsk:green:mmc0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@4 { + led4 { label = "evmsk:green:heartbeat"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -102,31 +102,31 @@ }; }; - gpio_buttons: gpio_buttons@0 { + gpio_buttons: gpio_buttons0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - switch@1 { + switch1 { label = "button0"; linux,code = <0x100>; gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; }; - switch@2 { + switch2 { label = "button1"; linux,code = <0x101>; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; - switch@3 { + switch3 { label = "button2"; linux,code = <0x102>; gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; wakeup-source; }; - switch@4 { + switch4 { label = "button3"; linux,code = <0x103>; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; @@ -170,29 +170,29 @@ pinctrl-1 = <&lcd_pins_sleep>; status = "okay"; panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; }; display-timings { 480x272 { - hactive = <480>; - vactive = <272>; - hback-porch = <43>; - hfront-porch = <8>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; - vsync-len = <10>; + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; + hsync-active = <0>; + vsync-active = <0>; }; }; }; @@ -711,5 +711,7 @@ }; &lcdc { - status = "okay"; + status = "okay"; + + blue-and-red-wiring = "crossed"; }; diff --git a/dts/src/arm/am335x-icev2.dts b/dts/src/arm/am335x-icev2.dts index 7d8b8fefdf..85e04c2055 100644 --- a/dts/src/arm/am335x-icev2.dts +++ b/dts/src/arm/am335x-icev2.dts @@ -19,12 +19,12 @@ model = "TI AM3359 ICE-V2"; compatible = "ti,am3359-icev2", "ti,am33xx"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -32,7 +32,7 @@ regulator-boot-on; }; - vtt_fixed: fixedregulator@1 { + vtt_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; @@ -43,52 +43,52 @@ enable-active-high; }; - leds@0 { + leds0 { compatible = "gpio-leds"; - led@0 { + led0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@1 { + led1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@4 { + led4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@6 { + led6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@7 { + led7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -96,49 +96,58 @@ }; /* Tricolor status LEDs */ - leds@1 { + leds1 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds>; - led@0 { + led0 { label = "status0:red:cpu0"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; - led@1 { + led1 { label = "status0:green:usr"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "status0:yellow:usr"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "status1:red:mmc0"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; - led@4 { + led4 { label = "status1:green:usr"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "status1:yellow:usr"; gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; }; &am33xx_pinmux { diff --git a/dts/src/arm/am335x-igep0033.dtsi b/dts/src/arm/am335x-igep0033.dtsi index e7d9ca1305..a5769a8f5f 100644 --- a/dts/src/arm/am335x-igep0033.dtsi +++ b/dts/src/arm/am335x-igep0033.dtsi @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; @@ -31,14 +31,14 @@ compatible = "gpio-leds"; - led@0 { + led0 { label = "com:green:user"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -46,7 +46,7 @@ regulator-boot-on; }; - vmmc: fixedregulator@0 { + vmmc: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/am335x-lxm.dts b/dts/src/arm/am335x-lxm.dts index d97b0efa43..1d6c6fa703 100644 --- a/dts/src/arm/am335x-lxm.dts +++ b/dts/src/arm/am335x-lxm.dts @@ -19,13 +19,13 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; /* Power supply provides a fixed 5V @2A */ - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -34,7 +34,7 @@ }; /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: fixedregulator@1 { + vmmcsd_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/am335x-nano.dts b/dts/src/arm/am335x-nano.dts index f313999c50..483d585c89 100644 --- a/dts/src/arm/am335x-nano.dts +++ b/dts/src/arm/am335x-nano.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; @@ -27,7 +27,7 @@ leds { compatible = "gpio-leds"; - led@0 { + led0 { label = "nanobone:green:usr1"; gpios = <&gpio1 5 0>; default-state = "off"; diff --git a/dts/src/arm/am335x-pepper.dts b/dts/src/arm/am335x-pepper.dts index 8867aaaec5..30e2f8770a 100644 --- a/dts/src/arm/am335x-pepper.dts +++ b/dts/src/arm/am335x-pepper.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; @@ -41,15 +41,15 @@ compatible = "ti,da830-evm-audio"; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; }; - v3v3c_reg: fixedregulator@1 { + v3v3c_reg: fixedregulator1 { compatible = "regulator-fixed"; }; - vdd5_reg: fixedregulator@2 { + vdd5_reg: fixedregulator2 { compatible = "regulator-fixed"; }; }; @@ -595,14 +595,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; - led@0 { + led0 { label = "pepper:user0:blue"; gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "off"; }; - led@1 { + led1 { label = "pepper:user1:red"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; @@ -616,21 +616,21 @@ #address-cells = <1>; #size-cells = <0>; - button@0 { + button0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; wakeup-source; }; - button@1 { + button1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; wakeup-source; }; - buttons@2 { + buttons2 { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/am335x-phycore-som.dtsi b/dts/src/arm/am335x-phycore-som.dtsi index 1263c9d4cb..75e24add3f 100644 --- a/dts/src/arm/am335x-phycore-som.dtsi +++ b/dts/src/arm/am335x-phycore-som.dtsi @@ -25,7 +25,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; @@ -33,7 +33,7 @@ regulators { compatible = "simple-bus"; - vcc5v: fixedregulator@0 { + vcc5v: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vcc5v"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm/am335x-shc.dts b/dts/src/arm/am335x-shc.dts index 837d5b80ea..bf8727a19e 100644 --- a/dts/src/arm/am335x-shc.dts +++ b/dts/src/arm/am335x-shc.dts @@ -64,50 +64,50 @@ compatible = "gpio-leds"; - led@1 { + led1 { label = "shc:power:red"; gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "shc:power:bl"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; default-state = "on"; }; - led@3 { + led3 { label = "shc:lan:red"; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@4 { + led4 { label = "shc:lan:bl"; gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "shc:cloud:red"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@6 { + led6 { label = "shc:cloud:bl"; gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/am335x-sl50.dts b/dts/src/arm/am335x-sl50.dts index a6efbe6eda..b0dfa6f14c 100644 --- a/dts/src/arm/am335x-sl50.dts +++ b/dts/src/arm/am335x-sl50.dts @@ -19,6 +19,11 @@ }; }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + chosen { stdout-path = &uart0; }; @@ -28,25 +33,25 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - led@0 { + led0 { label = "sl50:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led1 { label = "sl50:red:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led2 { label = "sl50:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led3 { label = "sl50:red:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; @@ -103,7 +108,7 @@ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/am335x-wega.dtsi b/dts/src/arm/am335x-wega.dtsi index 282f6d4b27..02c67365c4 100644 --- a/dts/src/arm/am335x-wega.dtsi +++ b/dts/src/arm/am335x-wega.dtsi @@ -11,10 +11,14 @@ model = "Phytec AM335x phyBOARD-WEGA"; compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + regulators { compatible = "simple-bus"; - vcc3v3: fixedregulator@1 { + vcc3v3: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; @@ -24,6 +28,58 @@ }; }; +/* Audio */ +&am33xx_pinmux { + mcasp0_pins: pinmux_mcasp0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + >; + }; +}; + +&i2c0 { + tlv320aic3007: tlv320aic3007@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + AVDD-supply = <&vcc3v3>; + IOVDD-supply = <&vcc3v3>; + DRVDD-supply = <&vcc3v3>; + DVDD-supply = <&vdig1_reg>; + status = "okay"; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < + 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ + >; + tx-num-evt = <16>; + rt-num-evt = <16>; + status = "okay"; +}; + +&sound { + ti,model = "AM335x-Wega"; + ti,audio-codec = <&tlv320aic3007>; + ti,mcasp-controller = <&mcasp0>; + ti,audio-routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + clocks = <&mcasp0_fck>; + clock-names = "mclk"; + status = "okay"; +}; + /* CAN Busses */ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { @@ -99,6 +155,12 @@ status = "okay"; }; +/* Power */ +&vdig1_reg { + regulator-boot-on; + regulator-always-on; +}; + /* UARTs */ &am33xx_pinmux { uart0_pins: pinmux_uart0 { diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi index 98748c61ed..194d884c9d 100644 --- a/dts/src/arm/am33xx.dtsi +++ b/dts/src/arm/am33xx.dtsi @@ -11,11 +11,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/am33xx.h> -#include "skeleton.dtsi" - / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c0; @@ -45,9 +45,19 @@ device_type = "cpu"; reg = <0>; - operating-points-v2 = <&cpu0_opp_table>; - ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; - ti,syscon-rev = <&scm_conf 0x600>; + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -56,78 +66,6 @@ }; }; - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - /* - * The three following nodes are marked with opp-suspend - * because the can not be enabled simultaneously on a - * single SoC. - */ - opp50@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0x06 0x0010>; - opp-suspend; - }; - - opp100@275000000 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0x00FF>; - opp-suspend; - }; - - opp100@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0020>; - opp-suspend; - }; - - opp100@500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp100@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0040>; - }; - - opp120@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp120@720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x06 0x0080>; - }; - - oppturbo@720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - oppturbo@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x06 0x0100>; - }; - - oppnitro@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0x04 0x0200>; - }; - }; - pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; diff --git a/dts/src/arm/am3517-craneboard.dts b/dts/src/arm/am3517-craneboard.dts index f9d8f3948c..083ff50734 100644 --- a/dts/src/arm/am3517-craneboard.dts +++ b/dts/src/arm/am3517-craneboard.dts @@ -15,7 +15,7 @@ model = "TI AM3517 CraneBoard (TMDSEVM3517)"; compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/am3517-evm.dts b/dts/src/arm/am3517-evm.dts index b4127c6493..0e4a125f78 100644 --- a/dts/src/arm/am3517-evm.dts +++ b/dts/src/arm/am3517-evm.dts @@ -13,7 +13,7 @@ model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/am3517.dtsi b/dts/src/arm/am3517.dtsi index 5e3f5e86ff..0db19d39d2 100644 --- a/dts/src/arm/am3517.dtsi +++ b/dts/src/arm/am3517.dtsi @@ -15,7 +15,7 @@ serial3 = &uart4; }; - ocp { + ocp@68000000 { am35x_otg_hs: am35x_otg_hs@5c040000 { compatible = "ti,omap3-musb"; ti,hwmods = "am35x_otg_hs"; diff --git a/dts/src/arm/am3517_mt_ventoux.dts b/dts/src/arm/am3517_mt_ventoux.dts index fdf5ce63c8..3395783c5b 100644 --- a/dts/src/arm/am3517_mt_ventoux.dts +++ b/dts/src/arm/am3517_mt_ventoux.dts @@ -13,7 +13,7 @@ model = "TeeJet Mt.Ventoux"; compatible = "teejet,mt_ventoux", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi index 0fadae5396..a275fa9568 100644 --- a/dts/src/arm/am4372.dtsi +++ b/dts/src/arm/am4372.dtsi @@ -11,12 +11,16 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { compatible = "ti,am4372", "ti,am43"; interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; aliases { i2c0 = &i2c0; @@ -132,7 +136,7 @@ cache-level = <2>; }; - ocp { + ocp@44000000 { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/am437x-cm-t43.dts b/dts/src/arm/am437x-cm-t43.dts index 9551c47131..9e92d48057 100644 --- a/dts/src/arm/am437x-cm-t43.dts +++ b/dts/src/arm/am437x-cm-t43.dts @@ -209,7 +209,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -218,7 +217,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -227,7 +225,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-suspend-enable; regulator-min-microvolt = <1500000>; @@ -237,7 +234,6 @@ }; dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -246,7 +242,6 @@ }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -255,7 +250,6 @@ }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts index 14677d5995..957840cc7b 100644 --- a/dts/src/arm/am437x-gp-evm.dts +++ b/dts/src/arm/am437x-gp-evm.dts @@ -58,7 +58,7 @@ default-brightness-level = <8>; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; @@ -513,7 +513,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -522,7 +521,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -531,33 +529,42 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; + dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts index 12a6951838..25ce611c65 100644 --- a/dts/src/arm/am437x-idk-evm.dts +++ b/dts/src/arm/am437x-idk-evm.dts @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch0 { label = "power-button"; linux,code = <KEY_POWER>; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/am437x-sk-evm.dts b/dts/src/arm/am437x-sk-evm.dts index 5687d6b4da..319d942053 100644 --- a/dts/src/arm/am437x-sk-evm.dts +++ b/dts/src/arm/am437x-sk-evm.dts @@ -64,7 +64,7 @@ }; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; pinctrl-names = "default"; @@ -93,28 +93,28 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins>; - led@0 { + led0 { label = "am437x-sk:red:heartbeat"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@1 { + led1 { label = "am437x-sk:green:mmc1"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ linux,default-trigger = "mmc0"; default-state = "off"; }; - led@2 { + led2 { label = "am437x-sk:blue:cpu0"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ linux,default-trigger = "cpu0"; default-state = "off"; }; - led@3 { + led3 { label = "am437x-sk:blue:usr3"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ default-state = "off"; @@ -428,7 +428,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; /* VDD_CORE limits min of OPP50 and max of OPP100 */ regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; @@ -438,7 +437,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; @@ -448,16 +446,20 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdds_ddr"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; dcdc4: regulator-dcdc4 { - compatible = "ti,tps65218-dcdc4"; regulator-name = "v3_3d"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -465,8 +467,31 @@ regulator-always-on; }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-name = "v1_8d"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts index ad32e55532..9d35c3f07c 100644 --- a/dts/src/arm/am43x-epos-evm.dts +++ b/dts/src/arm/am43x-epos-evm.dts @@ -32,7 +32,7 @@ enable-active-high; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -67,7 +67,7 @@ }; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; @@ -421,7 +421,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -430,7 +429,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -439,7 +437,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; @@ -448,7 +445,6 @@ }; dcdc4: regulator-dcdc4 { - compatible = "ti,tps65218-dcdc4"; regulator-name = "vdcdc4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -457,21 +453,18 @@ }; dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; diff --git a/dts/src/arm/am572x-idk.dts b/dts/src/arm/am572x-idk.dts index e3acb99703..87bbc66f0f 100644 --- a/dts/src/arm/am572x-idk.dts +++ b/dts/src/arm/am572x-idk.dts @@ -18,7 +18,7 @@ compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/dts/src/arm/am57xx-beagle-x15-common.dtsi b/dts/src/arm/am57xx-beagle-x15-common.dtsi new file mode 100644 index 0000000000..6df7829a2c --- /dev/null +++ b/dts/src/arm/am57xx-beagle-x15-common.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + rtc2 = &rtc; + display0 = &hdmi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd_fixed"; + vin-supply = <&vdd_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + default-state = "off"; + }; + }; + + gpio_fan: gpio_fan { + /* Based on 5v 500mA AFB02505HHB */ + compatible = "gpio-fan"; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <13000 1>; + #cooling-cells = <2>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "BeagleBoard-X15"; + simple-audio-card,widgets = + "Line", "Line Out", + "Line", "Line In"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC2L", "Line In", + "MIC2R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp3>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3104>; + clocks = <&clkout2_clk>; + }; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD / VDDSHV8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHYA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + tlv320aic3104: tlv320aic3104@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3104"; + reg = <0x18>; + assigned-clocks = <&clkoutmux2_clk_mux>; + assigned-clock-parents = <&sys_clk2_dclk_div>; + + status = "okay"; + adc-settle-ms = <40>; + + AVDD-supply = <&vdd_3v3>; + IOVDD-supply = <&vdd_3v3>; + DRVDD-supply = <&vdd_3v3>; + DVDD-supply = <&aic_dvdd>; + }; + + eeprom: eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, + <&dra7_pmx_core 0x424>; + interrupt-names = "irq", "wakeup"; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; +}; + +&mac { + status = "okay"; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + /* + * Stand alone usage is peripheral only. + * However, with some resistor modifications + * this port can be used via expansion connectors + * as "host" or "dual-role". If so, provide + * the necessary dr_mode override in the expansion + * board's DT. + */ + dr_mode = "peripheral"; +}; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo4_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&pcie1 { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&sys_clkin2>; + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/dts/src/arm/am57xx-beagle-x15-revb1.dts b/dts/src/arm/am57xx-beagle-x15-revb1.dts new file mode 100644 index 0000000000..ca85570629 --- /dev/null +++ b/dts/src/arm/am57xx-beagle-x15-revb1.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am57xx-beagle-x15-common.dtsi" + +/ { + model = "TI AM5728 BeagleBoard-X15 rev B1"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + vmmc-supply = <&vdd_3v3>; + vmmc-aux-supply = <&ldo1_reg>; +}; diff --git a/dts/src/arm/am57xx-beagle-x15.dts b/dts/src/arm/am57xx-beagle-x15.dts index c4d04c5293..8c66f2efd2 100644 --- a/dts/src/arm/am57xx-beagle-x15.dts +++ b/dts/src/arm/am57xx-beagle-x15.dts @@ -1,822 +1,24 @@ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; -#include "dra74x.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "am57xx-beagle-x15-common.dtsi" / { + /* NOTE: This describes the "original" pre-production A2 revision */ model = "TI AM5728 BeagleBoard-X15"; - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - led@0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led@2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; }; -&dra7_pmx_core { - leds_pins_default: leds_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37a8, PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ - DRA7XX_CORE_IOPAD(0x37ac, PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ - DRA7XX_CORE_IOPAD(0x37c0, PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ - DRA7XX_CORE_IOPAD(0x37c4, PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ - >; - }; - - i2c1_pins_default: i2c1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - i2c3_pins_default: i2c3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - cpsw_pins_default: cpsw_pins_default { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ - >; - - }; - - cpsw_pins_sleep: cpsw_pins_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci_mdio_pins_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15) - >; - }; - - tps659038_pins_default: tps659038_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - tmp102_pins_default: tmp102_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ - >; - }; - - mcp79410_pins_default: mcp79410_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - DRA7XX_CORE_IOPAD(0x3770, PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ - >; - }; - - clkout2_pins_default: clkout2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */ - >; - }; - - clkout2_pins_sleep: clkout2_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */ - >; - }; - - mcasp3_pins_default: mcasp3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ - >; - }; - - mcasp3_pins_sleep: mcasp3_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tmp102_pins_default>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&clkout2_pins_default>; - pinctrl-1 = <&clkout2_pins_sleep>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; - - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; - - eeprom: eeprom@50 { - compatible = "at,24c32"; - reg = <0x50>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - pinctrl-names = "default"; - pinctrl-0 = <&mcp79410_pins_default>; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; &mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1 { - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&sys_clkin2>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; }; diff --git a/dts/src/arm/am57xx-cl-som-am57x.dts b/dts/src/arm/am57xx-cl-som-am57x.dts index 378b142ef8..203266f884 100644 --- a/dts/src/arm/am57xx-cl-som-am57x.dts +++ b/dts/src/arm/am57xx-cl-som-am57x.dts @@ -19,7 +19,7 @@ model = "CompuLab CL-SOM-AM57x"; compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ }; @@ -29,7 +29,7 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - led@0 { + led0 { label = "cl-som-am57x:green"; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/am57xx-idk-common.dtsi b/dts/src/arm/am57xx-idk-common.dtsi index 0e63b9dff6..03cec62260 100644 --- a/dts/src/arm/am57xx-idk-common.dtsi +++ b/dts/src/arm/am57xx-idk-common.dtsi @@ -304,3 +304,52 @@ ti,non-removable; max-frequency = <96000000>; }; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1", "jedec,spi-nor"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000040000>; + }; + partition@1 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@2 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@3 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@5 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; diff --git a/dts/src/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/dts/src/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts new file mode 100644 index 0000000000..e18769df9f --- /dev/null +++ b/dts/src/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp-ctrevb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/* + * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and + * the Rev B core tile. + */ +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; +}; diff --git a/dts/src/arm/arm-realview-eb-11mp-bbrevd.dts b/dts/src/arm/arm-realview-eb-11mp-bbrevd.dts new file mode 100644 index 0000000000..26b1c69e9f --- /dev/null +++ b/dts/src/arm/arm-realview-eb-11mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; +}; diff --git a/dts/src/arm/arm-realview-eb-11mp-revb.dts b/dts/src/arm/arm-realview-eb-11mp-ctrevb.dts index e68527b0d5..e68527b0d5 100644 --- a/dts/src/arm/arm-realview-eb-11mp-revb.dts +++ b/dts/src/arm/arm-realview-eb-11mp-ctrevb.dts diff --git a/dts/src/arm/arm-realview-eb-11mp.dts b/dts/src/arm/arm-realview-eb-11mp.dts index 87ff602a2a..aac1edd4b2 100644 --- a/dts/src/arm/arm-realview-eb-11mp.dts +++ b/dts/src/arm/arm-realview-eb-11mp.dts @@ -24,7 +24,7 @@ #include "arm-realview-eb-mp.dtsi" / { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C"; + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; arm,hbi = <0x146>; /* diff --git a/dts/src/arm/arm-realview-eb-a9mp-bbrevd.dts b/dts/src/arm/arm-realview-eb-a9mp-bbrevd.dts new file mode 100644 index 0000000000..42efac7496 --- /dev/null +++ b/dts/src/arm/arm-realview-eb-a9mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-a9mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; +}; diff --git a/dts/src/arm/arm-realview-eb-bbrevd.dts b/dts/src/arm/arm-realview-eb-bbrevd.dts new file mode 100644 index 0000000000..f533c8b49d --- /dev/null +++ b/dts/src/arm/arm-realview-eb-bbrevd.dts @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* This derives from the Realview Baseboard, and overlays the new ethernet */ +#include "arm-realview-eb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D"; +}; diff --git a/dts/src/arm/arm-realview-eb-bbrevd.dtsi b/dts/src/arm/arm-realview-eb-bbrevd.dtsi new file mode 100644 index 0000000000..a79e1d1d30 --- /dev/null +++ b/dts/src/arm/arm-realview-eb-bbrevd.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/ { + /* Introduce a fixed regulator for the new ethernet controller */ + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +/* + * The revision D has a different ethernet controller that the elder boards: + * the older board uses LAN91C111 but the new one uses LAN9118. + */ +ðernet { + compatible = "smsc,lan9118", "smsc,lan9115"; + phy-mode = "mii"; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; +}; diff --git a/dts/src/arm/arm-realview-eb.dtsi b/dts/src/arm/arm-realview-eb.dtsi index 1c6a040218..e2e9599596 100644 --- a/dts/src/arm/arm-realview-eb.dtsi +++ b/dts/src/arm/arm-realview-eb.dtsi @@ -51,14 +51,6 @@ regulator-boot-on; }; - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - xtal24mhz: xtal24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -134,16 +126,15 @@ bank-width = <4>; }; - /* SMSC 9118 ethernet with PHY and EEPROM */ + /* SMSC LAN91C111 ethernet with PHY and EEPROM */ ethernet: ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; + compatible = "smsc,lan91c111"; reg = <0x4e000000 0x10000>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; + /* + * This means the adapter can be accessed with 8, 16 or + * 32 bit reads/writes. + */ + reg-io-width = <7>; }; usb: usb@4f000000 { diff --git a/dts/src/arm/armada-370-db.dts b/dts/src/arm/armada-370-db.dts index 2364fc56ae..033fa63544 100644 --- a/dts/src/arm/armada-370-db.dts +++ b/dts/src/arm/armada-370-db.dts @@ -155,20 +155,6 @@ status = "okay"; }; - spi0: spi@10600 { - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - }; - }; - nand@d0000 { status = "okay"; num-cs = <1>; @@ -274,3 +260,18 @@ compatible = "linux,spdif-dir"; }; }; + +&spi0 { + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l25635e", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + }; +}; + diff --git a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi index 1aba08e437..01cded310c 100644 --- a/dts/src/arm/armada-370-seagate-personal-cloud.dtsi +++ b/dts/src/arm/armada-370-seagate-personal-cloud.dtsi @@ -68,26 +68,6 @@ phy-mode = "rgmii-id"; }; - spi@10600 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - /* MX25L8006E */ - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - }; - }; - usb@50000 { status = "okay"; }; @@ -176,3 +156,23 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + /* MX25L8006E */ + compatible = "mxicy,mx25l8005", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/dts/src/arm/armada-370-synology-ds213j.dts b/dts/src/arm/armada-370-synology-ds213j.dts index 8ca7a4340c..a9cc427768 100644 --- a/dts/src/arm/armada-370-synology-ds213j.dts +++ b/dts/src/arm/armada-370-synology-ds213j.dts @@ -87,62 +87,6 @@ status = "disabled"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000c0000 0x002d0000>; /* 2880KB */ - }; - - partition@00390000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x00390000 0x00440000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; - }; - i2c@11000 { compatible = "marvell,mv64xxx-i2c"; pinctrl-0 = <&i2c0_pins>; @@ -347,3 +291,59 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000c0000 0x002d0000>; /* 2880KB */ + }; + + partition@00390000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x00390000 0x00440000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/dts/src/arm/armada-370-xp.dtsi b/dts/src/arm/armada-370-xp.dtsi index a718866ba5..3ccedc9dff 100644 --- a/dts/src/arm/armada-370-xp.dtsi +++ b/dts/src/arm/armada-370-xp.dtsi @@ -148,26 +148,6 @@ interrupts = <50>; }; - spi0: spi@10600 { - reg = <0x10600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = <0x10680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; #address-cells = <1>; @@ -320,6 +300,42 @@ status = "disabled"; }; }; + + spi0: spi@10600 { + reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */ + <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */ + <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */ + <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */ + <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */ + <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */ + <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */ + <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */ + <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */ + <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */ + <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */ + <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */ + <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */ + <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */ + <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */ + <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */ + <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi index 3b06aa8354..b4258105e9 100644 --- a/dts/src/arm/armada-370.dtsi +++ b/dts/src/arm/armada-370.dtsi @@ -134,24 +134,6 @@ wt-override; }; - /* - * Default SPI pinctrl setting, can be overwritten on - * board level if a different configuration is used. - */ - spi0: spi@10600 { - compatible = "marvell,armada-370-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins1>; - pinctrl-names = "default"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-370-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - }; - i2c0: i2c@11000 { reg = <0x11000 0x20>; }; @@ -447,3 +429,19 @@ marvell,function = "ge1"; }; }; + +/* + * Default SPI pinctrl setting, can be overwritten on + * board level if a different configuration is used. + */ +&spi0 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins1>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm/armada-385-db-ap.dts b/dts/src/arm/armada-385-db-ap.dts index 2d3fd6e76e..db5b9f6b61 100644 --- a/dts/src/arm/armada-385-db-ap.dts +++ b/dts/src/arm/armada-385-db-ap.dts @@ -65,20 +65,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi1: spi@10680 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <54000000>; - }; - }; - i2c0: i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -155,6 +141,10 @@ bm,pool-short = <3>; }; + usb@58000 { + status = "okay"; + }; + /* CON4 */ ethernet@70000 { pinctrl-names = "default"; @@ -178,15 +168,35 @@ nfc: flash@d0000 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - num-cs = <1>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; marvell,nand-keep-config; marvell,nand-enable-arbiter; nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00800000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00800000 0x00400000>; + read-only; + }; + + partition@c00000 { + label = "Root"; + reg = <0x00c00000 0x3f400000>; + }; + }; }; usb3@f0000 { @@ -239,3 +249,17 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; }; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <54000000>; + }; +}; diff --git a/dts/src/arm/armada-385-linksys.dtsi b/dts/src/arm/armada-385-linksys.dtsi index 22f7a13e20..8f0e508f64 100644 --- a/dts/src/arm/armada-385-linksys.dtsi +++ b/dts/src/arm/armada-385-linksys.dtsi @@ -62,11 +62,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { - - spi@10600 { - status = "disabled"; - }; - i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -332,3 +327,7 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "disabled"; +}; diff --git a/dts/src/arm/armada-388-clearfog.dts b/dts/src/arm/armada-388-clearfog.dts index d3e6bd8050..71ce201c90 100644 --- a/dts/src/arm/armada-388-clearfog.dts +++ b/dts/src/arm/armada-388-clearfog.dts @@ -315,30 +315,6 @@ status = "okay"; }; - spi@10680 { - /* - * We don't seem to have the W25Q32 on the - * A1 Rev 2.0 boards, so disable SPI. - * CS0: W25Q32 (doesn't appear to be present) - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins - &clearfog_spi1_cs_pins - &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - status = "disabled"; - }; - }; - usb@58000 { /* CON3, nearest power. */ status = "okay"; @@ -444,3 +420,27 @@ }; }; }; + +&spi1 { + /* + * We don't seem to have the W25Q32 on the + * A1 Rev 2.0 boards, so disable SPI. + * CS0: W25Q32 (doesn't appear to be present) + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins + &clearfog_spi1_cs_pins + &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; +}; diff --git a/dts/src/arm/armada-388-db.dts b/dts/src/arm/armada-388-db.dts index ea93ed7270..de26c76223 100644 --- a/dts/src/arm/armada-388-db.dts +++ b/dts/src/arm/armada-388-db.dts @@ -70,18 +70,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -201,3 +189,16 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts index fd75e5e955..895fa6cfa1 100644 --- a/dts/src/arm/armada-388-gp.dts +++ b/dts/src/arm/armada-388-gp.dts @@ -64,21 +64,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi@10600 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; - }; - i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -433,3 +418,18 @@ marvell,function = "gpio"; }; }; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; diff --git a/dts/src/arm/armada-388-rd.dts b/dts/src/arm/armada-388-rd.dts index 853f9735cc..dd3462ddb6 100644 --- a/dts/src/arm/armada-388-rd.dts +++ b/dts/src/arm/armada-388-rd.dts @@ -70,18 +70,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { - spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -142,3 +130,16 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi index 3312be6c82..2d7668848c 100644 --- a/dts/src/arm/armada-38x.dtsi +++ b/dts/src/arm/armada-38x.dtsi @@ -170,30 +170,6 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; @@ -287,6 +263,15 @@ marvell,function = "spi1"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", + "mpp33", "mpp38", "mpp28", + "mpp40", "mpp42", "mpp35", + "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; @@ -649,6 +634,30 @@ no-memory-wc; status = "disabled"; }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/dts/src/arm/armada-390-db.dts b/dts/src/arm/armada-390-db.dts new file mode 100644 index 0000000000..34e279d973 --- /dev/null +++ b/dts/src/arm/armada-390-db.dts @@ -0,0 +1,175 @@ +/* + * Device Tree file for Marvell Armada 390 Development Board + * (DB-88F6920) + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk <jaz@semihalf.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-390.dtsi" + +/ { + model = "Marvell Armada 390 Development Board"; + compatible = "marvell,a390-db", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + /* CON104 */ + serial@12000 { + status = "okay"; + }; + + /* CON97 */ + usb@58000 { + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + + /* CON98 */ + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + /* CON30 */ + pcie@1,0 { + status = "okay"; + }; + + /* CON44 */ + pcie@2,0 { + status = "okay"; + }; + + /* CON61 */ + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", + "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; diff --git a/dts/src/arm/armada-390.dtsi b/dts/src/arm/armada-390.dtsi index 094e39c660..6cd18d8aaa 100644 --- a/dts/src/arm/armada-390.dtsi +++ b/dts/src/arm/armada-390.dtsi @@ -47,6 +47,8 @@ #include "armada-39x.dtsi" / { + compatible = "marvell,armada390"; + soc { internal-regs { pinctrl@18000 { @@ -54,4 +56,5 @@ reg = <0x18000 0x20>; }; }; + }; }; diff --git a/dts/src/arm/armada-395-gp.dts b/dts/src/arm/armada-395-gp.dts new file mode 100644 index 0000000000..2cdbba804c --- /dev/null +++ b/dts/src/arm/armada-395-gp.dts @@ -0,0 +1,163 @@ +/* + * Device Tree file for Marvell Armada 395 GP board + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk <jaz@semihalf.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-395.dtsi" + +/ { + model = "Marvell Armada 395 GP Board"; + compatible = "marvell,a395-gp", "marvell,armada395", + "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON17 + * through an FTDI + */ + status = "okay"; + }; + + /* CON1 */ + usb@58000 { + status = "okay"; + }; + + /* CON2 */ + sata@a8000 { + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00600000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00600000 0x00400000>; + read-only; + }; + + partition@1000000 { + label = "Root"; + reg = <0x00a00000 0x3f600000>; + }; + }; + }; + + /* CON18 */ + sdhci@d8000 { + clock-frequency = <200000000>; + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + no-1-8-v; + }; + + /* CON4 */ + usb3@f0000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The two PCIe units are accessible through + * mini PCIe slot on the board. + */ + + /* CON7 */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + /* CON8 */ + pcie@4,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + }; +}; diff --git a/dts/src/arm/armada-395.dtsi b/dts/src/arm/armada-395.dtsi new file mode 100644 index 0000000000..ab5dc49f2b --- /dev/null +++ b/dts/src/arm/armada-395.dtsi @@ -0,0 +1,76 @@ +/* + * Device Tree Include file for Marvell Armada 395 SoC. + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk <jaz@semihalf.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada395", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6925-pinctrl"; + reg = <0x18000 0x20>; + }; + + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/src/arm/armada-398-db.dts b/dts/src/arm/armada-398-db.dts index 788c3badb6..268c8349c8 100644 --- a/dts/src/arm/armada-398-db.dts +++ b/dts/src/arm/armada-398-db.dts @@ -65,30 +65,6 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; internal-regs { - spi@10680 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0x1000000>; - }; - }; - }; - i2c@11000 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -108,6 +84,10 @@ status = "okay"; }; + usb@58000 { + status = "okay"; + }; + flash@d0000 { status = "okay"; pinctrl-0 = <&nand_pins>; @@ -132,6 +112,10 @@ reg = <0x1000000 0x3f000000>; }; }; + + usb3@f8000 { + status = "okay"; + }; }; pcie-controller { @@ -151,3 +135,27 @@ }; }; }; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0x1000000>; + }; + }; +}; diff --git a/dts/src/arm/armada-398.dtsi b/dts/src/arm/armada-398.dtsi index fdc25914e3..234a99891a 100644 --- a/dts/src/arm/armada-398.dtsi +++ b/dts/src/arm/armada-398.dtsi @@ -44,7 +44,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armada-39x.dtsi" +#include "armada-395.dtsi" / { compatible = "marvell,armada398", "marvell,armada390"; @@ -55,6 +55,14 @@ compatible = "marvell,mv88f6928-pinctrl"; reg = <0x18000 0x20>; }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 30>; + status = "disabled"; + }; }; }; }; diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi index dc6efd386d..34cba87f92 100644 --- a/dts/src/arm/armada-39x.dtsi +++ b/dts/src/arm/armada-39x.dtsi @@ -55,6 +55,8 @@ compatible = "marvell,armada390"; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -78,6 +80,11 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", "simple-bus"; @@ -131,30 +138,6 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; @@ -269,6 +252,34 @@ }; }; + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + }; + system-controller@18200 { compatible = "marvell,armada-390-system-controller", "marvell,armada-370-xp-system-controller"; @@ -317,11 +328,29 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, + <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + pmsu@22000 { compatible = "marvell,armada-390-pmsu", "marvell,armada-380-pmsu"; @@ -368,6 +397,13 @@ }; }; + rtc@a3800 { + compatible = "marvell,armada-380-rtc"; + reg = <0xa3800 0x20>, <0x184a0 0x0c>; + reg-names = "rtc", "rtc-soc"; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + flash@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; @@ -380,7 +416,10 @@ sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; @@ -395,6 +434,12 @@ clocks = <&mainpll>; clock-output-names = "nand"; }; + + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; }; pcie-controller { @@ -501,6 +546,30 @@ status = "disabled"; }; }; + + spi0: spi@10600 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { @@ -510,5 +579,12 @@ #clock-cells = <0>; clock-frequency = <1000000000>; }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; }; diff --git a/dts/src/arm/armada-xp-axpwifiap.dts b/dts/src/arm/armada-xp-axpwifiap.dts index 5c21b23672..ce152719bc 100644 --- a/dts/src/arm/armada-xp-axpwifiap.dts +++ b/dts/src/arm/armada-xp-axpwifiap.dts @@ -135,18 +135,6 @@ phy = <&phy1>; phy-mode = "rgmii-id"; }; - - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; }; }; @@ -179,3 +167,15 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/dts/src/arm/armada-xp-db.dts b/dts/src/arm/armada-xp-db.dts index 62422a90ae..075120bc3e 100644 --- a/dts/src/arm/armada-xp-db.dts +++ b/dts/src/arm/armada-xp-db.dts @@ -231,18 +231,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - }; - }; - nand@d0000 { status = "okay"; num-cs = <1>; @@ -277,3 +265,15 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; diff --git a/dts/src/arm/armada-xp-gp.dts b/dts/src/arm/armada-xp-gp.dts index 061f423776..190e4eccb1 100644 --- a/dts/src/arm/armada-xp-gp.dts +++ b/dts/src/arm/armada-xp-gp.dts @@ -232,18 +232,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - bm@c0000 { status = "okay"; }; @@ -262,3 +250,15 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/dts/src/arm/armada-xp-linksys-mamba.dts b/dts/src/arm/armada-xp-linksys-mamba.dts index 7a461541ce..076f27f22c 100644 --- a/dts/src/arm/armada-xp-linksys-mamba.dts +++ b/dts/src/arm/armada-xp-linksys-mamba.dts @@ -279,18 +279,6 @@ reg = <0x180000 0x780000>; /* 7.5MB */ }; }; - - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <40000000>; - }; - }; }; }; @@ -398,3 +386,15 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <40000000>; + }; +}; diff --git a/dts/src/arm/armada-xp-synology-ds414.dts b/dts/src/arm/armada-xp-synology-ds414.dts index d17dab0a6f..ae286736b9 100644 --- a/dts/src/arm/armada-xp-synology-ds414.dts +++ b/dts/src/arm/armada-xp-synology-ds414.dts @@ -110,62 +110,6 @@ status = "disabled"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@003a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; - }; - i2c@11000 { clock-frequency = <400000>; status = "okay"; @@ -362,3 +306,59 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/dts/src/arm/armada-xp.dtsi b/dts/src/arm/armada-xp.dtsi index 553349c07f..4a5f99e65b 100644 --- a/dts/src/arm/armada-xp.dtsi +++ b/dts/src/arm/armada-xp.dtsi @@ -84,19 +84,6 @@ wt-override; }; - spi0: spi@10600 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - }; - - i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; @@ -362,6 +349,12 @@ marvell,function = "spi0"; }; + spi1_pins: spi1-pins { + marvell,pins = "mpp13", "mpp14", + "mpp16", "mpp17"; + marvell,function = "spi1"; + }; + uart2_pins: uart2-pins { marvell,pins = "mpp42", "mpp43"; marvell,function = "uart2"; @@ -372,3 +365,15 @@ marvell,function = "uart3"; }; }; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm/armv7-m.dtsi b/dts/src/arm/armv7-m.dtsi index 16331aa797..ba332e399b 100644 --- a/dts/src/arm/armv7-m.dtsi +++ b/dts/src/arm/armv7-m.dtsi @@ -1,5 +1,3 @@ -#include "skeleton.dtsi" - / { nvic: interrupt-controller@e000e100 { compatible = "arm,armv7m-nvic"; diff --git a/dts/src/arm/artpec6.dtsi b/dts/src/arm/artpec6.dtsi index 3fac4c4d00..3489019cc0 100644 --- a/dts/src/arm/artpec6.dtsi +++ b/dts/src/arm/artpec6.dtsi @@ -41,6 +41,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/axis,artpec6-clkctrl.h> #include "skeleton.dtsi" / { @@ -109,14 +110,14 @@ compatible = "arm,cortex-a9-global-timer"; reg = <0xfaf00200 0x20>; interrupts = <GIC_PPI 11 0xf01>; - clocks = <&clkctrl 1>; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; }; timer@faf00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfaf00600 0x20>; interrupts = <GIC_PPI 13 0xf04>; - clocks = <&clkctrl 1>; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; status = "disabled"; }; @@ -136,12 +137,20 @@ arm,data-latency = <1 1 1>; arm,tag-latency = <1 1 1>; arm,filter-ranges = <0x0 0x80000000>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,prefetch-offset = <0>; + arm,prefetch-drop = <1>; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; interrupt-parent = <&intc>; }; @@ -157,7 +166,7 @@ ethernet: ethernet@f8010000 { clock-names = "phy_ref_clk", "apb_pclk"; clocks = <ð_phy_ref_clk>, - <&clkctrl 4>; + <&clkctrl ARTPEC6_CLK_ETH_ACLK>; compatible = "snps,dwc-qos-ethernet-4.10"; interrupt-parent = <&intc>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -175,8 +184,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8036000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -184,8 +193,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8037000 0x1000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -193,8 +202,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8038000 0x1000>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -202,8 +211,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8039000 0x1000>; interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; diff --git a/dts/src/arm/axp209.dtsi b/dts/src/arm/axp209.dtsi index afbe89c01d..675bb0f308 100644 --- a/dts/src/arm/axp209.dtsi +++ b/dts/src/arm/axp209.dtsi @@ -53,6 +53,12 @@ interrupt-controller; #interrupt-cells = <1>; + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi index c3bf7d23f1..7c9e0fae9b 100644 --- a/dts/src/arm/bcm-nsp.dtsi +++ b/dts/src/arm/bcm-nsp.dtsi @@ -209,6 +209,24 @@ #dma-cells = <1>; }; + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x022000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + amac1: ethernet@23000 { + compatible = "brcm,nsp-amac"; + reg = <0x023000 0x1000>, + <0x111000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, @@ -223,6 +241,14 @@ brcm,nand-has-wp; }; + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + rng: rng@33000 { compatible = "brcm,bcm-nsp-rng"; reg = <0x33000 0x14>; @@ -246,6 +272,17 @@ clock-names = "apb_pclk"; }; + srab: srab@36000 { + compatible = "brcm,nsp-srab"; + reg = <0x36000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + /* ports are defined in board DTS */ + }; + i2c0: i2c@38000 { compatible = "brcm,iproc-i2c"; reg = <0x38000 0x50>; diff --git a/dts/src/arm/bcm2835-rpi-a-plus.dts b/dts/src/arm/bcm2835-rpi-a-plus.dts index 35ff4e7a4a..f7f9db355d 100644 --- a/dts/src/arm/bcm2835-rpi-a-plus.dts +++ b/dts/src/arm/bcm2835-rpi-a-plus.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; diff --git a/dts/src/arm/bcm2835-rpi-a.dts b/dts/src/arm/bcm2835-rpi-a.dts index 306a84ee98..8be102f5d8 100644 --- a/dts/src/arm/bcm2835-rpi-a.dts +++ b/dts/src/arm/bcm2835-rpi-a.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-a", "brcm,bcm2835"; diff --git a/dts/src/arm/bcm2835-rpi-b-plus.dts b/dts/src/arm/bcm2835-rpi-b-plus.dts index d5fdb8e761..35cde65c97 100644 --- a/dts/src/arm/bcm2835-rpi-b-plus.dts +++ b/dts/src/arm/bcm2835-rpi-b-plus.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; diff --git a/dts/src/arm/bcm2835-rpi-b-rev2.dts b/dts/src/arm/bcm2835-rpi-b-rev2.dts index bfc4bd9b77..84df85ea62 100644 --- a/dts/src/arm/bcm2835-rpi-b-rev2.dts +++ b/dts/src/arm/bcm2835-rpi-b-rev2.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts index 0371bb7374..8e626a80fe 100644 --- a/dts/src/arm/bcm2835-rpi-b.dts +++ b/dts/src/arm/bcm2835-rpi-b.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; diff --git a/dts/src/arm/bcm2835-rpi-zero.dts b/dts/src/arm/bcm2835-rpi-zero.dts new file mode 100644 index 0000000000..60e359fafc --- /dev/null +++ b/dts/src/arm/bcm2835-rpi-zero.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Stefan Wahren <stefan.wahren@i2se.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; + + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = <BCM2835_FSEL_ALT0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/dts/src/arm/bcm2836-rpi-2-b.dts b/dts/src/arm/bcm2836-rpi-2-b.dts index 29e1cfe8eb..39dccf62ac 100644 --- a/dts/src/arm/bcm2836-rpi-2-b.dts +++ b/dts/src/arm/bcm2836-rpi-2-b.dts @@ -2,6 +2,7 @@ #include "bcm2836.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; diff --git a/dts/src/arm/bcm283x-rpi-usb-host.dtsi b/dts/src/arm/bcm283x-rpi-usb-host.dtsi new file mode 100644 index 0000000000..73f4ece8dc --- /dev/null +++ b/dts/src/arm/bcm283x-rpi-usb-host.dtsi @@ -0,0 +1,3 @@ +&usb { + dr_mode = "host"; +}; diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi index 445624a1a1..46d46d894a 100644 --- a/dts/src/arm/bcm283x.dtsi +++ b/dts/src/arm/bcm283x.dtsi @@ -290,6 +290,8 @@ interrupts = <1 9>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk_usb>; + clock-names = "otg"; }; v3d: v3d@7ec00000 { @@ -317,5 +319,12 @@ clock-frequency = <19200000>; }; + clk_usb: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-output-names = "otg"; + clock-frequency = <480000000>; + }; }; }; diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi index 8af47913b3..ae4b388061 100644 --- a/dts/src/arm/bcm5301x.dtsi +++ b/dts/src/arm/bcm5301x.dtsi @@ -140,6 +140,15 @@ }; }; + usb2_phy: usb2-phy { + compatible = "brcm,ns-usb2-phy"; + reg = <0x1800c000 0x1000>; + reg-names = "dmu"; + #phy-cells = <0>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + }; + axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -232,6 +241,8 @@ #address-cells = <1>; #size-cells = <1>; + + phys = <&usb2_phy>; }; usb3: usb3@23000 { diff --git a/dts/src/arm/bcm958522er.dts b/dts/src/arm/bcm958522er.dts new file mode 100644 index 0000000000..a21b0fd21f --- /dev/null +++ b/dts/src/arm/bcm958522er.dts @@ -0,0 +1,130 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "NorthStar Plus SVK (BCM958522ER)"; + compatible = "brcm,bcm58522", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + + +&amac1 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/bcm958525er.dts b/dts/src/arm/bcm958525er.dts new file mode 100644 index 0000000000..be7f2f8ecf --- /dev/null +++ b/dts/src/arm/bcm958525er.dts @@ -0,0 +1,142 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "NorthStar Plus SVK (BCM958525ER)"; + compatible = "brcm,bcm58525", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + + +&amac1 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/bcm958525xmc.dts b/dts/src/arm/bcm958525xmc.dts index d257e83ded..959cde911c 100644 --- a/dts/src/arm/bcm958525xmc.dts +++ b/dts/src/arm/bcm958525xmc.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "NorthStar Plus XMC (BCM958525xmc)"; @@ -45,6 +46,35 @@ chosen { stdout-path = "serial0:115200n8"; }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&i2c0 { + temperature-sensor@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + }; }; &nand { @@ -85,7 +115,7 @@ }; }; -/* XHCI, SATA, MMC, and Ethernet support needed to be complete */ +/* XHCI, MMC, and Ethernet support needed to be complete */ &uart0 { status = "okay"; @@ -99,6 +129,18 @@ status = "okay"; }; +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&nand_sel>; diff --git a/dts/src/arm/bcm958622hr.dts b/dts/src/arm/bcm958622hr.dts new file mode 100644 index 0000000000..ad2aa87dd1 --- /dev/null +++ b/dts/src/arm/bcm958622hr.dts @@ -0,0 +1,170 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "NorthStar Plus SVK (BCM958622HR)"; + compatible = "brcm,bcm58622", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 and SLIC support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&srab { + compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/bcm958623hr.dts b/dts/src/arm/bcm958623hr.dts new file mode 100644 index 0000000000..4ceb8fef80 --- /dev/null +++ b/dts/src/arm/bcm958623hr.dts @@ -0,0 +1,178 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "NorthStar Plus SVK (BCM958623HR)"; + compatible = "brcm,bcm58623", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 and SLIC support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&srab { + compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/bcm958625hr.dts b/dts/src/arm/bcm958625hr.dts index 03b8bbeb69..4420025970 100644 --- a/dts/src/arm/bcm958625hr.dts +++ b/dts/src/arm/bcm958625hr.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "NorthStar Plus SVK (BCM958625HR)"; @@ -47,7 +48,14 @@ }; memory { - reg = <0x60000000 0x20000000>; + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; }; }; @@ -109,3 +117,64 @@ groups = "nand_grp"; }; }; + +&amac0 { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts index 2d8422632b..05c5f98c87 100644 --- a/dts/src/arm/bcm958625k.dts +++ b/dts/src/arm/bcm958625k.dts @@ -46,6 +46,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; }; &uart0 { @@ -56,6 +61,14 @@ status = "okay"; }; +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/dts/src/arm/bcm988312hr.dts b/dts/src/arm/bcm988312hr.dts new file mode 100644 index 0000000000..104afe98a4 --- /dev/null +++ b/dts/src/arm/bcm988312hr.dts @@ -0,0 +1,182 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "NorthStar Plus SVK (BCM988312HR)"; + compatible = "brcm,bcm88312", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/berlin2-sony-nsz-gs7.dts b/dts/src/arm/berlin2-sony-nsz-gs7.dts index 3c0907b87f..1c475796d1 100644 --- a/dts/src/arm/berlin2-sony-nsz-gs7.dts +++ b/dts/src/arm/berlin2-sony-nsz-gs7.dts @@ -49,7 +49,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; diff --git a/dts/src/arm/berlin2.dtsi b/dts/src/arm/berlin2.dtsi index ae81009741..425c48971a 100644 --- a/dts/src/arm/berlin2.dtsi +++ b/dts/src/arm/berlin2.dtsi @@ -39,13 +39,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/berlin2.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Marvell Armada 1500 (BG2) SoC"; compatible = "marvell,berlin2", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; @@ -89,7 +90,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -447,7 +448,6 @@ reg = <0x2000 0x100>; clocks = <&refclk>; interrupts = <1>; - status = "disabled"; }; wdt2: watchdog@3000 { @@ -455,7 +455,6 @@ reg = <0x3000 0x100>; clocks = <&refclk>; interrupts = <2>; - status = "disabled"; }; sm_gpio1: gpio@5000 { diff --git a/dts/src/arm/berlin2cd-google-chromecast.dts b/dts/src/arm/berlin2cd-google-chromecast.dts index 8ba8b50ce9..ca24def0ce 100644 --- a/dts/src/arm/berlin2cd-google-chromecast.dts +++ b/dts/src/arm/berlin2cd-google-chromecast.dts @@ -50,7 +50,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/berlin2cd.dtsi b/dts/src/arm/berlin2cd.dtsi index 6d06b6118d..4fe1574d08 100644 --- a/dts/src/arm/berlin2cd.dtsi +++ b/dts/src/arm/berlin2cd.dtsi @@ -39,13 +39,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/berlin2.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Marvell Armada 1500-mini (BG2CD) SoC"; compatible = "marvell,berlin2cd", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; @@ -78,7 +79,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/berlin2q-marvell-dmp.dts b/dts/src/arm/berlin2q-marvell-dmp.dts index 33b28757b8..f485308840 100644 --- a/dts/src/arm/berlin2q-marvell-dmp.dts +++ b/dts/src/arm/berlin2q-marvell-dmp.dts @@ -43,7 +43,7 @@ model = "Marvell BG2-Q DMP"; compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x80000000>; }; diff --git a/dts/src/arm/berlin2q.dtsi b/dts/src/arm/berlin2q.dtsi index 2c34bfb136..e548229697 100644 --- a/dts/src/arm/berlin2q.dtsi +++ b/dts/src/arm/berlin2q.dtsi @@ -37,11 +37,11 @@ #include <dt-bindings/clock/berlin2q.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { model = "Marvell Armada 1500 pro (BG2-Q) SoC"; compatible = "marvell,berlin2q", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; @@ -99,7 +99,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -525,7 +525,6 @@ reg = <0x2000 0x100>; clocks = <&refclk>; interrupts = <1>; - status = "disabled"; }; wdt2: watchdog@3000 { @@ -533,7 +532,6 @@ reg = <0x3000 0x100>; clocks = <&refclk>; interrupts = <2>; - status = "disabled"; }; sm_gpio1: gpio@5000 { diff --git a/dts/src/arm/da850-evm.dts b/dts/src/arm/da850-evm.dts index 1a15db8e37..41de15fe15 100644 --- a/dts/src/arm/da850-evm.dts +++ b/dts/src/arm/da850-evm.dts @@ -29,6 +29,20 @@ 0x04 0x00011000 0x000ff000 >; }; + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ + 0x1c 0x10110110 0xf0ff0ff0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; }; serial0: serial@42000 { status = "okay"; @@ -131,12 +145,7 @@ status = "okay"; }; }; - nand_cs3@62000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_cs3_pins>; - }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -250,3 +259,33 @@ &edma1 { ti,edma-reserved-slot-ranges = <32 90>; }; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "ok"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + }; + }; +}; diff --git a/dts/src/arm/da850-lcdk.dts b/dts/src/arm/da850-lcdk.dts new file mode 100644 index 0000000000..7b8ab21fed --- /dev/null +++ b/dts/src/arm/da850-lcdk.dts @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2016 BayLibre, Inc. + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "da850.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "DA850/AM1808/OMAP-L138 LCDK"; + compatible = "ti,da850-lcdk", "ti,da850"; + + aliases { + serial2 = &serial2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0xc0000000 0x08000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 LCDK"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; +}; + +&pmx_core { + status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* AHCLKX AFSX ACLKX */ + 0x00 0x00101010 0x00f0f0f0 + /* ARX13 ARX14 */ + 0x04 0x00000110 0x00000ff0 + >; + }; + + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ + 0x1c 0x10110010 0xf0ff00f0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* + * EMA_D[8], EMA_D[9], EMA_D[10], + * EMA_D[11], EMA_D[12], EMA_D[13], + * EMA_D[14], EMA_D[15] + */ + 0x20 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; +}; + +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + status = "okay"; +}; + +&mmc0 { + max-frequency = <50000000>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 1 2 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + + ti,davinci-nand-buswidth = <16>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + + /* + * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: + * "To boot from NAND Flash, the AIS should be written + * to NAND block 1 (NAND block 0 is not used by default)". + * The same doc mentions that for ROM "Silicon Revision 2.1", + * "Updated NAND boot mode to offer boot from block 0 or block 1". + * However the limitaion is left here by default for compatibility + * with older silicon and because it needs new boot pin settings + * not possible in stock LCDK. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot env"; + reg = <0 0x020000>; + }; + partition@0x020000 { + /* The LCDK defaults to booting from this partition */ + label = "u-boot"; + reg = <0x020000 0x080000>; + }; + partition@0x0a0000 { + label = "free space"; + reg = <0x0a0000 0>; + }; + }; + }; + }; +}; diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi index 25f0f8e6dd..f79e1b91c6 100644 --- a/dts/src/arm/da850.dtsi +++ b/dts/src/arm/da850.dtsi @@ -41,20 +41,40 @@ pinctrl-single,function-mask = <0xf>; status = "disabled"; - nand_cs3_pins: pinmux_nand_pins { + serial0_rtscts_pins: pinmux_serial0_rtscts_pins { pinctrl-single,bits = < - /* EMA_OE, EMA_WE */ - 0x1c 0x00110000 0x00ff0000 - /* EMA_CS[4],EMA_CS[3]*/ - 0x1c 0x00000110 0x00000ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 + /* UART0_RTS UART0_CTS */ + 0x0c 0x22000000 0xff000000 + >; + }; + serial0_rxtx_pins: pinmux_serial0_rxtx_pins { + pinctrl-single,bits = < + /* UART0_TXD UART0_RXD */ + 0x0c 0x00220000 0x00ff0000 + >; + }; + serial1_rtscts_pins: pinmux_serial1_rtscts_pins { + pinctrl-single,bits = < + /* UART1_CTS UART1_RTS */ + 0x00 0x00440000 0x00ff0000 + >; + }; + serial1_rxtx_pins: pinmux_serial1_rxtx_pins { + pinctrl-single,bits = < + /* UART1_TXD UART1_RXD */ + 0x10 0x22000000 0xff000000 + >; + }; + serial2_rtscts_pins: pinmux_serial2_rtscts_pins { + pinctrl-single,bits = < + /* UART2_CTS UART2_RTS */ + 0x00 0x44000000 0xff000000 + >; + }; + serial2_rxtx_pins: pinmux_serial2_rxtx_pins { + pinctrl-single,bits = < + /* UART2_TXD UART2_RXD */ + 0x10 0x00220000 0x00ff0000 >; }; i2c0_pins: pinmux_i2c0_pins { @@ -274,31 +294,36 @@ status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; status = "disabled"; }; ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; status = "disabled"; }; ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; status = "disabled"; }; ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; status = "disabled"; @@ -375,17 +400,14 @@ dma-names = "tx", "rx"; }; }; - nand_cs3@62000000 { - compatible = "ti,davinci-nand"; - reg = <0x62000000 0x807ff - 0x68000000 0x8000>; - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; + aemif: aemif@68000000 { + compatible = "ti,da850-aemif"; + #address-cells = <2>; + #size-cells = <1>; + + reg = <0x68000000 0x00008000>; + ranges = <0 0 0x60000000 0x08000000 + 1 0 0x68000000 0x00008000>; status = "disabled"; }; }; diff --git a/dts/src/arm/dm8148-evm.dts b/dts/src/arm/dm8148-evm.dts index 4128fa9182..d6657b3bae 100644 --- a/dts/src/arm/dm8148-evm.dts +++ b/dts/src/arm/dm8148-evm.dts @@ -12,13 +12,13 @@ model = "DM8148 EVM"; compatible = "ti,dm8148-evm", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/dm8148-t410.dts b/dts/src/arm/dm8148-t410.dts index 3f184863e0..63883b3479 100644 --- a/dts/src/arm/dm8148-t410.dts +++ b/dts/src/arm/dm8148-t410.dts @@ -11,7 +11,7 @@ model = "HP t410 Smart Zero Client"; compatible = "hp,t410", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; @@ -27,7 +27,7 @@ regulator-always-on; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/dm814x.dtsi b/dts/src/arm/dm814x.dtsi index 68e412c986..ff90a6ce6b 100644 --- a/dts/src/arm/dm814x.dtsi +++ b/dts/src/arm/dm814x.dtsi @@ -7,11 +7,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/dm814x.h> -#include "skeleton.dtsi" - / { compatible = "ti,dm814"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; diff --git a/dts/src/arm/dm8168-evm.dts b/dts/src/arm/dm8168-evm.dts index f50348bdd8..0bf55fa72d 100644 --- a/dts/src/arm/dm8168-evm.dts +++ b/dts/src/arm/dm8168-evm.dts @@ -12,14 +12,14 @@ model = "DM8168 EVM"; compatible = "ti,dm8168-evm", "ti,dm8168"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000 /* 1 GB */ 0xc0000000 0x40000000>; /* 1 GB */ }; /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/dm816x.dtsi b/dts/src/arm/dm816x.dtsi index 44e39c743b..f1e0f771ff 100644 --- a/dts/src/arm/dm816x.dtsi +++ b/dts/src/arm/dm816x.dtsi @@ -7,11 +7,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/omap.h> -#include "skeleton.dtsi" - / { compatible = "ti,dm816"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; diff --git a/dts/src/arm/dra62x-j5eco-evm.dts b/dts/src/arm/dra62x-j5eco-evm.dts index f820573f4a..155eb32ee2 100644 --- a/dts/src/arm/dra62x-j5eco-evm.dts +++ b/dts/src/arm/dra62x-j5eco-evm.dts @@ -12,13 +12,13 @@ model = "DRA62x J5 Eco EVM"; compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts index bafcfac067..132f2be108 100644 --- a/dts/src/arm/dra7-evm.dts +++ b/dts/src/arm/dra7-evm.dts @@ -16,7 +16,7 @@ model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ }; @@ -105,25 +105,25 @@ leds { compatible = "gpio-leds"; - led@0 { + led0 { label = "dra7:usr1"; gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led1 { label = "dra7:usr2"; gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led2 { label = "dra7:usr3"; gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led3 { label = "dra7:usr4"; gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; default-state = "off"; @@ -664,10 +664,10 @@ &qspi { status = "okay"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index d9bfb94a29..d4fcd68f63 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/dra.h> -#include "skeleton.dtsi" - #define MAX_SOURCES 400 / { @@ -82,9 +80,11 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points-v2 = <&cpu0_opp_table>; - ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; - ti,syscon-rev = <&scm_wkup 0x204>; + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -98,24 +98,6 @@ }; }; - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp_nom@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp_od@1176000000 { - opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>; - opp-supported-hw = <0xFF 0x02>; - }; - }; - /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -301,6 +283,7 @@ 0x82000000 0 0x20013000 0x13000 0 0xffed000>; #interrupt-cells = <1>; num-lanes = <1>; + linux,pci-domain = <0>; ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; @@ -336,6 +319,7 @@ 0x82000000 0 0x30013000 0x13000 0 0xffed000>; #interrupt-cells = <1>; num-lanes = <1>; + linux,pci-domain = <1>; ti,hwmods = "pcie2"; phys = <&pcie2_phy>; phy-names = "pcie-phy0"; @@ -1413,7 +1397,7 @@ ti,hwmods = "ocp2scp1"; usb2_phy1: phy@4a084000 { - compatible = "ti,omap-usb2"; + compatible = "ti,dra7x-usb2", "ti,omap-usb2"; reg = <0x4a084000 0x400>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, @@ -1717,7 +1701,7 @@ mac: ethernet@48484000 { compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; - clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; + clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; @@ -1726,7 +1710,7 @@ mac_control = <0x20>; slaves = <2>; active_slave = <0>; - cpts_clock_mult = <0x80000000>; + cpts_clock_mult = <0x784CFE14>; cpts_clock_shift = <29>; reg = <0x48484000 0x1000 0x48485200 0x2E00>; diff --git a/dts/src/arm/dra72-evm-common.dtsi b/dts/src/arm/dra72-evm-common.dtsi index 9d3cf50ca3..c94d8d6471 100644 --- a/dts/src/arm/dra72-evm-common.dtsi +++ b/dts/src/arm/dra72-evm-common.dtsi @@ -681,10 +681,10 @@ &qspi { status = "okay"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/dts/src/arm/dra72-evm-revc.dts b/dts/src/arm/dra72-evm-revc.dts index f9cfd3bb4d..064b322a7a 100644 --- a/dts/src/arm/dra72-evm-revc.dts +++ b/dts/src/arm/dra72-evm-revc.dts @@ -11,7 +11,7 @@ / { model = "TI DRA722 Rev C EVM"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; diff --git a/dts/src/arm/dra72-evm.dts b/dts/src/arm/dra72-evm.dts index cc1d32ca4a..e3a9b69856 100644 --- a/dts/src/arm/dra72-evm.dts +++ b/dts/src/arm/dra72-evm.dts @@ -9,7 +9,7 @@ / { model = "TI DRA722"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; diff --git a/dts/src/arm/dra74x.dtsi b/dts/src/arm/dra74x.dtsi index 8987b3e180..0a78347e66 100644 --- a/dts/src/arm/dra74x.dtsi +++ b/dts/src/arm/dra74x.dtsi @@ -17,7 +17,6 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; - operating-points-v2 = <&cpu0_opp_table>; }; }; diff --git a/dts/src/arm/dra7xx-clocks.dtsi b/dts/src/arm/dra7xx-clocks.dtsi index 8378b44ee5..3330738e4c 100644 --- a/dts/src/arm/dra7xx-clocks.dtsi +++ b/dts/src/arm/dra7xx-clocks.dtsi @@ -1003,6 +1003,14 @@ ti,index-power-of-two; }; + gmac_main_clk: gmac_main_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&gmac_250m_dclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; @@ -1718,13 +1726,12 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 { + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; ti,bit-shift = <24>; reg = <0x13d0>; - ti,dividers = <2>; }; gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { diff --git a/dts/src/arm/efm32gg-dk3750.dts b/dts/src/arm/efm32gg-dk3750.dts index 504cf45d3c..98fc667d22 100644 --- a/dts/src/arm/efm32gg-dk3750.dts +++ b/dts/src/arm/efm32gg-dk3750.dts @@ -16,7 +16,8 @@ bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0"; }; - memory { + memory@88000000 { + device_type = "memory"; reg = <0x88000000 0x400000>; }; @@ -74,7 +75,7 @@ status = "ok"; }; - boardfpga: boardfpga { + boardfpga: boardfpga@80000000 { compatible = "efm32board"; reg = <0x80000000 0x400>; irq-gpios = <&gpio 64 1>; diff --git a/dts/src/arm/efm32gg.dtsi b/dts/src/arm/efm32gg.dtsi index c747983771..b78c57e51e 100644 --- a/dts/src/arm/efm32gg.dtsi +++ b/dts/src/arm/efm32gg.dtsi @@ -4,10 +4,14 @@ * Documentation available from * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf */ + #include "armv7-m.dtsi" #include "dt-bindings/clock/efm32-cmu.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { i2c0 = &i2c0; i2c1 = &i2c1; diff --git a/dts/src/arm/exynos3250-artik5.dtsi b/dts/src/arm/exynos3250-artik5.dtsi index 130e946f14..a70819b1b7 100644 --- a/dts/src/arm/exynos3250-artik5.dtsi +++ b/dts/src/arm/exynos3250-artik5.dtsi @@ -24,7 +24,8 @@ stdout-path = &serial_2; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts index 8c89062663..66f04f6ba6 100644 --- a/dts/src/arm/exynos3250-monk.dts +++ b/dts/src/arm/exynos3250-monk.dts @@ -27,7 +27,8 @@ i2c7 = &i2c_max77836; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/dts/src/arm/exynos3250-pinctrl.dtsi b/dts/src/arm/exynos3250-pinctrl.dtsi index 40ea7de449..ec331169c3 100644 --- a/dts/src/arm/exynos3250-pinctrl.dtsi +++ b/dts/src/arm/exynos3250-pinctrl.dtsi @@ -12,58 +12,46 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 - -#define PIN_DRV_LV1 0 -#define PIN_DRV_LV2 2 -#define PIN_DRV_LV3 1 -#define PIN_DRV_LV4 3 - -#define PIN_PDN_OUT0 0 -#define PIN_PDN_OUT1 1 -#define PIN_PDN_INPUT 2 -#define PIN_PDN_PREV 3 - -#define PIN_IN(_pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <0>; \ - samsung,pin-pud = <PIN_PULL_ ##_pull>; \ - samsung,pin-drv = <PIN_DRV_ ##_drv>; \ +#include <dt-bindings/pinctrl/samsung.h> + +#define PIN_IN(_pin, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \ + samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ + samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ } -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <1>; \ - samsung,pin-pud = <0>; \ - samsung,pin-drv = <PIN_DRV_ ##_drv>; \ +#define PIN_OUT(_pin, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ + samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ } -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <1>; \ - samsung,pin-pud = <0>; \ - samsung,pin-drv = <PIN_DRV_ ##_drv>; \ - samsung,pin-val = <_val>; \ +#define PIN_OUT_SET(_pin, _val, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ + samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ + samsung,pin-val = <_val>; \ } -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = <PIN_PULL_ ##_pull>; \ - samsung,pin-drv = <PIN_DRV_ ##_drv>; \ +#define PIN_CFG(_pin, _sel, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <_sel>; \ + samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ + samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ } -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ - samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ } &pinctrl_0 { @@ -125,158 +113,158 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; mipi0_clk: mipi0-clk { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -408,164 +396,164 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpk0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts index a92181368e..3967ee5f77 100644 --- a/dts/src/arm/exynos3250-rinato.dts +++ b/dts/src/arm/exynos3250-rinato.dts @@ -27,7 +27,8 @@ i2c7 = &i2c_max77836; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi index 70e3aceab3..e9d2556c0d 100644 --- a/dts/src/arm/exynos3250.dtsi +++ b/dts/src/arm/exynos3250.dtsi @@ -17,7 +17,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos4-cpu-thermal.dtsi" #include "exynos-syscon-restart.dtsi" #include <dt-bindings/clock/exynos3250.h> @@ -25,6 +24,8 @@ / { compatible = "samsung,exynos3250"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi index 32f22e12c7..5f034eb5a5 100644 --- a/dts/src/arm/exynos4.dtsi +++ b/dts/src/arm/exynos4.dtsi @@ -21,11 +21,12 @@ #include <dt-bindings/clock/exynos4.h> #include <dt-bindings/clock/exynos-audss-clk.h> -#include "skeleton.dtsi" #include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { spi0 = &spi_0; diff --git a/dts/src/arm/exynos4210-origen.dts b/dts/src/arm/exynos4210-origen.dts index be2751eeba..a2c6a13fe6 100644 --- a/dts/src/arm/exynos4210-origen.dts +++ b/dts/src/arm/exynos4210-origen.dts @@ -24,7 +24,8 @@ model = "Insignal Origen evaluation board based on Exynos4210"; compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 0x60000000 0x10000000 diff --git a/dts/src/arm/exynos4210-pinctrl.dtsi b/dts/src/arm/exynos4210-pinctrl.dtsi index 9331c6252e..d9b6d25e4a 100644 --- a/dts/src/arm/exynos4210-pinctrl.dtsi +++ b/dts/src/arm/exynos4210-pinctrl.dtsi @@ -14,6 +14,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + / { pinctrl@11400000 { gpa0: gpa0 { @@ -146,245 +148,245 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart_audio_a: uart-audio-a { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart_audio_b: uart-audio-b { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_sync: lcd-sync { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_en: lcd-en { samsung,pins = "gpe3-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data16: lcd-data-width16 { @@ -392,9 +394,9 @@ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data18: lcd-data-width18 { @@ -403,9 +405,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data24: lcd-data-width24 { @@ -415,9 +417,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -569,263 +571,263 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <4>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; eint0: ext-int0 { samsung,pins = "gpx0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint8: ext-int8 { samsung,pins = "gpx1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint15: ext-int15 { samsung,pins = "gpx1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint16: ext-int16 { samsung,pins = "gpx2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint31: ext-int31 { samsung,pins = "gpx3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; hdmi_cec: hdmi-cec { samsung,pins = "gpx3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -838,17 +840,17 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm0_bus: pcm0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; - samsung,pin-function = <0x3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; }; diff --git a/dts/src/arm/exynos4210-smdkv310.dts b/dts/src/arm/exynos4210-smdkv310.dts index 847fae3dd1..9c98a37243 100644 --- a/dts/src/arm/exynos4210-smdkv310.dts +++ b/dts/src/arm/exynos4210-smdkv310.dts @@ -23,7 +23,8 @@ model = "Samsung smdkv310 evaluation board based on Exynos4210"; compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -136,17 +137,17 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts index 79d9830365..0ca1b4d355 100644 --- a/dts/src/arm/exynos4210-trats.dts +++ b/dts/src/arm/exynos4210-trats.dts @@ -20,7 +20,8 @@ model = "Samsung Trats based on Exynos4210"; compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 0x60000000 0x10000000 diff --git a/dts/src/arm/exynos4210-universal_c210.dts b/dts/src/arm/exynos4210-universal_c210.dts index 9a75e3effb..0c89ea99de 100644 --- a/dts/src/arm/exynos4210-universal_c210.dts +++ b/dts/src/arm/exynos4210-universal_c210.dts @@ -20,7 +20,8 @@ model = "Samsung Universal C210 based on Exynos4210 rev0"; compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000>; }; @@ -269,7 +270,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd>; hdmi-en-supply = <&hdmi_en>; @@ -521,16 +522,16 @@ &pinctrl_1 { hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; - samsung,pin-pud = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; }; &pinctrl_0 { i2c_ddc_bus: i2c-ddc-bus { samsung,pins = "gpe4-2", "gpe4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi index 58ad48e7b8..8aa19ba144 100644 --- a/dts/src/arm/exynos4412-odroid-common.dtsi +++ b/dts/src/arm/exynos4412-odroid-common.dtsi @@ -163,26 +163,26 @@ /* RSTN signal for eMMC */ &sd1_cd { - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; - samsung,pin-pud = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; - samsung,pin-pud = <1>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; }; @@ -227,7 +227,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd>; vdd-supply = <&ldo8_reg>; diff --git a/dts/src/arm/exynos4412-odroidu3.dts b/dts/src/arm/exynos4412-odroidu3.dts index d73aa6c58f..99634c54dc 100644 --- a/dts/src/arm/exynos4412-odroidu3.dts +++ b/dts/src/arm/exynos4412-odroidu3.dts @@ -18,7 +18,8 @@ model = "Hardkernel ODROID-U3 board based on Exynos4412"; compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; diff --git a/dts/src/arm/exynos4412-odroidx.dts b/dts/src/arm/exynos4412-odroidx.dts index 2af2351513..61906b35ea 100644 --- a/dts/src/arm/exynos4412-odroidx.dts +++ b/dts/src/arm/exynos4412-odroidx.dts @@ -18,7 +18,8 @@ model = "Hardkernel ODROID-X board based on Exynos4412"; compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x3FF00000>; }; @@ -83,7 +84,7 @@ &pinctrl_1 { gpio_home_key: home_key { samsung,pins = "gpx2-2"; - samsung,pin-pud = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; }; diff --git a/dts/src/arm/exynos4412-odroidx2.dts b/dts/src/arm/exynos4412-odroidx2.dts index 3e3584270e..4d228858f1 100644 --- a/dts/src/arm/exynos4412-odroidx2.dts +++ b/dts/src/arm/exynos4412-odroidx2.dts @@ -17,7 +17,8 @@ model = "Hardkernel ODROID-X2 board based on Exynos4412"; compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; }; diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts index 26a36fed96..a1ab6f94bb 100644 --- a/dts/src/arm/exynos4412-origen.dts +++ b/dts/src/arm/exynos4412-origen.dts @@ -22,7 +22,8 @@ model = "Insignal Origen evaluation board based on Exynos4412"; compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; @@ -500,16 +501,16 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos4412-smdk4412.dts b/dts/src/arm/exynos4412-smdk4412.dts index 231ffbdbf9..7fcb43431b 100644 --- a/dts/src/arm/exynos4412-smdk4412.dts +++ b/dts/src/arm/exynos4412-smdk4412.dts @@ -20,7 +20,8 @@ model = "Samsung SMDK evaluation board based on Exynos4412"; compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; @@ -115,17 +116,17 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos4412-tiny4412.dts b/dts/src/arm/exynos4412-tiny4412.dts index 4840bbdaa9..5504398e6e 100644 --- a/dts/src/arm/exynos4412-tiny4412.dts +++ b/dts/src/arm/exynos4412-tiny4412.dts @@ -23,7 +23,8 @@ stdout-path = &serial_0; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts index 129e973a06..41ecd6d465 100644 --- a/dts/src/arm/exynos4412-trats2.dts +++ b/dts/src/arm/exynos4412-trats2.dts @@ -30,7 +30,8 @@ i2c12 = &i2c_max77693_fuel; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/dts/src/arm/exynos4415-pinctrl.dtsi b/dts/src/arm/exynos4415-pinctrl.dtsi index 75af9c5612..76cfd872ea 100644 --- a/dts/src/arm/exynos4415-pinctrl.dtsi +++ b/dts/src/arm/exynos4415-pinctrl.dtsi @@ -11,6 +11,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl_0 { gpa0: gpa0 { gpio-controller; @@ -94,180 +96,180 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -392,165 +394,165 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpk0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <4>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <4>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <4>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <4>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -566,8 +568,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos4415.dtsi b/dts/src/arm/exynos4415.dtsi index 28b04b6795..3c40f8a956 100644 --- a/dts/src/arm/exynos4415.dtsi +++ b/dts/src/arm/exynos4415.dtsi @@ -16,13 +16,14 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/exynos4415.h> #include <dt-bindings/clock/exynos-audss-clk.h> / { compatible = "samsung,exynos4415"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; diff --git a/dts/src/arm/exynos4x12-pinctrl.dtsi b/dts/src/arm/exynos4x12-pinctrl.dtsi index 856b292543..a56bf9b1a4 100644 --- a/dts/src/arm/exynos4x12-pinctrl.dtsi +++ b/dts/src/arm/exynos4x12-pinctrl.dtsi @@ -12,20 +12,13 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 - -#define PIN_PDN_OUT0 0 -#define PIN_PDN_OUT1 1 -#define PIN_PDN_INPUT 2 -#define PIN_PDN_PREV 3 - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ - samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ +#include <dt-bindings/pinctrl/samsung.h> + +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ } / { @@ -136,245 +129,245 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart_audio_a: uart-audio-a { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart_audio_b: uart-audio-b { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; mipi0_clk: mipi0-clk { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; mipi1_clk: mipi1-clk { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data16: lcd-data-width16 { @@ -382,9 +375,9 @@ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data18: lcd-data-width18 { @@ -393,9 +386,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data24: lcd-data-width24 { @@ -405,39 +398,39 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_ldi: lcd-ldi { samsung,pins = "gpf3-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -613,284 +606,284 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint0: ext-int0 { samsung,pins = "gpx0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint8: ext-int8 { samsung,pins = "gpx1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint15: ext-int15 { samsung,pins = "gpx1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint16: ext-int16 { samsung,pins = "gpx2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint31: ext-int31 { samsung,pins = "gpx3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; hdmi_cec: hdmi-cec { samsung,pins = "gpx3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -906,17 +899,17 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm0_bus: pcm0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; - samsung,pin-function = <0x3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -971,9 +964,9 @@ "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", "gpv4-0", "gpv4-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; }; diff --git a/dts/src/arm/exynos4x12.dtsi b/dts/src/arm/exynos4x12.dtsi index c452499ae8..3394bdcf10 100644 --- a/dts/src/arm/exynos4x12.dtsi +++ b/dts/src/arm/exynos4x12.dtsi @@ -157,7 +157,9 @@ <&clock CLK_MOUT_MPLL_USER_T>, <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, + <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, + <&clock CLK_PWM_ISP>, + <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, <&clock CLK_DIV_MCUISP0>, <&clock CLK_DIV_MCUISP1>, <&clock CLK_UART_ISP_SCLK>, @@ -167,6 +169,7 @@ clock-names = "lite0", "lite1", "ppmuispx", "ppmuispmx", "mpll", "isp", "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "uart", "aclk200", "div_aclk200", "aclk400mcuisp", diff --git a/dts/src/arm/exynos5.dtsi b/dts/src/arm/exynos5.dtsi index cab91782e2..8f06609879 100644 --- a/dts/src/arm/exynos5.dtsi +++ b/dts/src/arm/exynos5.dtsi @@ -13,11 +13,12 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c_0; diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts index ea70603f66..6098dacd09 100644 --- a/dts/src/arm/exynos5250-arndale.dts +++ b/dts/src/arm/exynos5250-arndale.dts @@ -20,7 +20,8 @@ model = "Insignal Arndale evaluation board based on EXYNOS5250"; compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -152,7 +153,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>; diff --git a/dts/src/arm/exynos5250-pinctrl.dtsi b/dts/src/arm/exynos5250-pinctrl.dtsi index 880917e508..2f6ab32b59 100644 --- a/dts/src/arm/exynos5250-pinctrl.dtsi +++ b/dts/src/arm/exynos5250-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl_0 { gpa0: gpa0 { gpio-controller; @@ -200,392 +202,392 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ac97_bus: ac97-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spdif_bus: spdif-bus { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_hs_bus: i2c0-hs-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpc3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpc3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_clk: sd3-clk { samsung,pins = "gpc4-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpc4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cd: sd3-cd { samsung,pins = "gpc4-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpc4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; uart1_data: uart1-data { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; dp_hpd: dp_hpd { samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -666,52 +668,52 @@ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_i2c2_bus: cam-i2c2-bus { samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_bayrgb_bus: cam-bayrgb-bus { @@ -720,18 +722,18 @@ "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", "gpg2-0", "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a: cam-port-a { samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", "gph1-0", "gph1-1", "gph1-2", "gph1-3", "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -781,9 +783,9 @@ "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; c2c_txd: c2c-txd { @@ -791,9 +793,9 @@ "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -809,8 +811,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts index 381af134c4..a97a785ccc 100644 --- a/dts/src/arm/exynos5250-smdk5250.dts +++ b/dts/src/arm/exynos5250-smdk5250.dts @@ -22,7 +22,8 @@ aliases { }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -116,7 +117,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; }; &i2c_0 { @@ -416,8 +417,8 @@ &pinctrl_0 { max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5250-snow-common.dtsi b/dts/src/arm/exynos5250-snow-common.dtsi index fadbea744e..d5d51916bb 100644 --- a/dts/src/arm/exynos5250-snow-common.dtsi +++ b/dts/src/arm/exynos5250-snow-common.dtsi @@ -19,7 +19,8 @@ i2c104 = &i2c_104; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -260,7 +261,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; phy = <&hdmiphy>; @@ -440,7 +441,7 @@ * double-pulling gets us out of spec in some cases. */ &i2c2_bus { - samsung,pin-pud = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; &i2c_2 { @@ -572,81 +573,81 @@ &pinctrl_0 { wifi_en: wifi-en { samsung,pins = "gpx0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; wifi_rst: wifi-rst { samsung,pins = "gpx0-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ec_irq: ec-irq { samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; usb3_vbus_en: usb3-vbus-en { samsung,pins = "gpx2-7"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lid_irq: lid-irq { samsung,pins = "gpx3-5"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; &pinctrl_1 { arb_their_claim: arb-their-claim { samsung,pins = "gpe0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; arb_our_claim: arb-our-claim { samsung,pins = "gpf0-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; @@ -657,16 +658,16 @@ }; &sd3_bus4 { - samsung,pin-drv = <0>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &sd3_clk { - samsung,pin-drv = <0>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &sd3_cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &spi_1 { diff --git a/dts/src/arm/exynos5250-snow-rev5.dts b/dts/src/arm/exynos5250-snow-rev5.dts index f811dc8006..90560c316f 100644 --- a/dts/src/arm/exynos5250-snow-rev5.dts +++ b/dts/src/arm/exynos5250-snow-rev5.dts @@ -40,8 +40,8 @@ &pinctrl_0 { max98090_irq: max98090-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5250-snow.dts b/dts/src/arm/exynos5250-snow.dts index 995c7ce6c1..df48f2cc96 100644 --- a/dts/src/arm/exynos5250-snow.dts +++ b/dts/src/arm/exynos5250-snow.dts @@ -36,8 +36,8 @@ &pinctrl_0 { max98095_en: max98095-en { samsung,pins = "gpx1-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5250-spring.dts b/dts/src/arm/exynos5250-spring.dts index 44f4292bfe..4d7bdb735e 100644 --- a/dts/src/arm/exynos5250-spring.dts +++ b/dts/src/arm/exynos5250-spring.dts @@ -20,7 +20,8 @@ model = "Google Spring"; compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -91,7 +92,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; phy = <&hdmiphy>; @@ -357,7 +358,7 @@ * double-pulling gets us out of spec in some cases. */ &i2c2_bus { - samsung,pin-pud = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; &i2c_2 { @@ -460,92 +461,92 @@ &pinctrl_0 { s5m8767_dvs: s5m8767-dvs { samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; dp_hpd_gpio: dp-hpd-gpio { samsung,pins = "gpc3-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ec_irq: ec-irq { samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; s5m8767_ds: s5m8767-ds { samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; s5m8767_irq: s5m8767-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lid_irq: lid-irq { samsung,pins = "gpx3-5"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; &pinctrl_1 { hsic_reset: hsic-reset { samsung,pins = "gpe1-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; &sd1_bus4 { - samsung,pin-drv = <0>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &sd1_cd { - samsung,pin-drv = <0>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &sd1_clk { - samsung,pin-drv = <0>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &sd1_cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; &spi_1 { diff --git a/dts/src/arm/exynos5260-pinctrl.dtsi b/dts/src/arm/exynos5260-pinctrl.dtsi index f6ee55ea07..1b911a219a 100644 --- a/dts/src/arm/exynos5260-pinctrl.dtsi +++ b/dts/src/arm/exynos5260-pinctrl.dtsi @@ -12,9 +12,7 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 +#include <dt-bindings/pinctrl/samsung.h> &pinctrl_0 { gpa0: gpa0 { @@ -187,217 +185,217 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; usb3_vbus0_en: usb3-vbus0-en { samsung,pins = "gpa2-4"; - samsung,pin-function = <1>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; spdif1_bus: spdif1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c0_hs_bus: i2c0-hs-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb4-2", "gpb4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpb4-4", "gpb4-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpb4-6", "gpb4-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c8_bus: i2c8-bus { samsung,pins = "gpb5-0", "gpb5-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c9_bus: i2c9-bus { samsung,pins = "gpb5-2", "gpb5-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c10_bus: i2c10-bus { samsung,pins = "gpb5-4", "gpb5-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; i2c11_bus: i2c11-bus { samsung,pins = "gpb5-6", "gpb5-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_gpio_a: cam-gpio-a { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; }; @@ -444,114 +442,114 @@ sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd1_clk: sd1-clk { samsung,pins = "gpc1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd1_bus8: sd1-bus-width8 { samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; }; diff --git a/dts/src/arm/exynos5260-xyref5260.dts b/dts/src/arm/exynos5260-xyref5260.dts index 3daef94bee..d0cc300cfb 100644 --- a/dts/src/arm/exynos5260-xyref5260.dts +++ b/dts/src/arm/exynos5260-xyref5260.dts @@ -16,7 +16,8 @@ model = "SAMSUNG XYREF5260 board based on EXYNOS5260"; compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; - memory { + memory@20000000 { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; @@ -42,9 +43,9 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5260.dtsi b/dts/src/arm/exynos5260.dtsi index 36da38e290..a86a4898d0 100644 --- a/dts/src/arm/exynos5260.dtsi +++ b/dts/src/arm/exynos5260.dtsi @@ -9,13 +9,13 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" - #include <dt-bindings/clock/exynos5260-clk.h> / { compatible = "samsung,exynos5260", "samsung,exynos5"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; diff --git a/dts/src/arm/exynos5410-odroidxu.dts b/dts/src/arm/exynos5410-odroidxu.dts index f6d135245a..3c271cb4b2 100644 --- a/dts/src/arm/exynos5410-odroidxu.dts +++ b/dts/src/arm/exynos5410-odroidxu.dts @@ -21,12 +21,13 @@ model = "Hardkernel Odroid XU"; compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x7ea00000>; }; chosen { - linux,stdout-path = &serial_2; + stdout-path = "serial2:115200n8"; }; emmc_pwrseq: pwrseq { @@ -473,38 +474,38 @@ &pinctrl_0 { emmc_nrst_pin: emmc-nrst { samsung,pins = "gpd1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpx0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpx0-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; samsung,pin-val = <1>; }; max77802_irq: max77802-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5410-pinctrl.dtsi b/dts/src/arm/exynos5410-pinctrl.dtsi index b58a0f29f4..a083d23fde 100644 --- a/dts/src/arm/exynos5410-pinctrl.dtsi +++ b/dts/src/arm/exynos5410-pinctrl.dtsi @@ -9,6 +9,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl_0 { gpa0: gpa0 { gpio-controller; @@ -280,212 +282,212 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c4_hs_bus: i2c4-hs-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c5_hs_bus: i2c5-hs-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c6_hs_bus: i2c6-hs-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c7_hs_bus: i2c7-hs-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; }; diff --git a/dts/src/arm/exynos5410-smdk5410.dts b/dts/src/arm/exynos5410-smdk5410.dts index 777fcf2edd..6cc74d97da 100644 --- a/dts/src/arm/exynos5410-smdk5410.dts +++ b/dts/src/arm/exynos5410-smdk5410.dts @@ -16,7 +16,8 @@ model = "Samsung SMDK5410 board based on EXYNOS5410"; compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; @@ -66,8 +67,8 @@ srom_ctl: srom-ctl { samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; - samsung,pin-function = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; srom_ebi: srom-ebi { @@ -77,9 +78,9 @@ "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5420-arndale-octa.dts b/dts/src/arm/exynos5420-arndale-octa.dts index 39a3b81478..9cc83c51c9 100644 --- a/dts/src/arm/exynos5420-arndale-octa.dts +++ b/dts/src/arm/exynos5420-arndale-octa.dts @@ -22,7 +22,8 @@ model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; - memory { + memory@20000000 { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; @@ -70,6 +71,15 @@ status = "disabled"; }; +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; + vdd-supply = <&ldo6_reg>; + ddc = <&i2c_2>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -347,6 +357,10 @@ }; }; +&i2c_2 { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; @@ -378,9 +392,9 @@ &pinctrl_0 { s2mps11_irq: s2mps11-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts index fe4e0915c0..ec4a00f1ce 100644 --- a/dts/src/arm/exynos5420-peach-pit.dts +++ b/dts/src/arm/exynos5420-peach-pit.dts @@ -79,7 +79,8 @@ }; }; - memory { + memory@20000000 { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; @@ -179,7 +180,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; @@ -753,171 +754,171 @@ wifi_en: wifi-en { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; max98090_irq: max98090-irq { samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ mask_tpm_reset: mask-tpm-reset { samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; samsung,pin-val = <0>; }; tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; ec_irq: ec-irq { samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; max77802_irq: max77802-irq { samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; lid_irq: lid-irq { samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_1 { /* Adjust WiFi drive strengths lower for EMI */ sd1_clk: sd1-clk { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_cmd: sd1-cmd { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; }; &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_3 { /* Drive SPI lines at x2 for better integrity */ spi2-bus { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; /* Drive SPI chip select at x2 for better integrity */ ec_spi_cs: ec-spi-cs { samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_selb: pmic-selb { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5420-pinctrl.dtsi b/dts/src/arm/exynos5420-pinctrl.dtsi index 14beb7e073..3924b4fafe 100644 --- a/dts/src/arm/exynos5420-pinctrl.dtsi +++ b/dts/src/arm/exynos5420-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl_0 { gpy7: gpy7 { gpio-controller; @@ -61,9 +63,9 @@ dp_hpd: dp_hpd { samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; @@ -153,135 +155,135 @@ sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd0_rclk: sd0-rclk { samsung,pins = "gpc0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <1>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpc1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpc1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_int: sd1-int { samsung,pins = "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd1_bus8: sd1-bus-width8 { samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; }; @@ -354,52 +356,52 @@ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_i2c2_bus: cam-i2c2-bus { samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; cam_bayrgb_bus: cam-bayrgb-bus { @@ -408,9 +410,9 @@ "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", "gpg2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; @@ -489,216 +491,216 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c4_hs_bus: i2c4-hs-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c5_hs_bus: i2c5-hs-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spdif_bus: spdif-bus { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c6_hs_bus: i2c6-hs-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c7_hs_bus: i2c7-hs-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c8_hs_bus: i2c8-hs-bus { samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c9_hs_bus: i2c9-hs-bus { samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; i2c10_hs_bus: i2c10-hs-bus { samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; @@ -714,8 +716,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5420-smdk5420.dts b/dts/src/arm/exynos5420-smdk5420.dts index ed8f342691..aaccd0da41 100644 --- a/dts/src/arm/exynos5420-smdk5420.dts +++ b/dts/src/arm/exynos5420-smdk5420.dts @@ -19,7 +19,8 @@ model = "Samsung SMDK5420 board based on EXYNOS5420"; compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; - memory { + memory@20000000 { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; @@ -130,7 +131,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; }; @@ -386,25 +387,25 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_2 { usb300_vbus_en: usb300-vbus-en { samsung,pins = "gpg0-5"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gpg1-4"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi index d56253049c..246d298557 100644 --- a/dts/src/arm/exynos5422-odroidxu3-common.dtsi +++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi @@ -21,12 +21,13 @@ #include "exynos-mfc-reserved-memory.dtsi" / { - memory { + memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x7EA00000>; }; chosen { - linux,stdout-path = &serial_2; + stdout-path = "serial2:115200n8"; }; firmware@02073000 { @@ -250,7 +251,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; @@ -548,25 +549,25 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; s2mps11_irq: s2mps11-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_1 { emmc_nrst_pin: emmc-nrst { samsung,pins = "gpd1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/exynos5440-sd5v1.dts b/dts/src/arm/exynos5440-sd5v1.dts index a98501bab6..ad6f533b3f 100644 --- a/dts/src/arm/exynos5440-sd5v1.dts +++ b/dts/src/arm/exynos5440-sd5v1.dts @@ -20,6 +20,12 @@ bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; + /* FIXME: set reg property with correct start address and size */ + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + fixed-rate-clocks { xtal { compatible = "samsung,clock-xtal"; diff --git a/dts/src/arm/exynos5440-ssdk5440.dts b/dts/src/arm/exynos5440-ssdk5440.dts index 6a0d802e87..92bd2c6f76 100644 --- a/dts/src/arm/exynos5440-ssdk5440.dts +++ b/dts/src/arm/exynos5440-ssdk5440.dts @@ -21,6 +21,12 @@ bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; + /* FIXME: set reg property with correct start address and size */ + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + fixed-rate-clocks { xtal { compatible = "samsung,clock-xtal"; diff --git a/dts/src/arm/exynos5440.dtsi b/dts/src/arm/exynos5440.dtsi index fd176819b4..e6bffd13ce 100644 --- a/dts/src/arm/exynos5440.dtsi +++ b/dts/src/arm/exynos5440.dtsi @@ -10,12 +10,13 @@ */ #include <dt-bindings/clock/exynos5440.h> -#include "skeleton.dtsi" / { compatible = "samsung,exynos5440", "samsung,exynos5"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &serial_0; diff --git a/dts/src/arm/exynos54xx.dtsi b/dts/src/arm/exynos54xx.dtsi index 06a604911e..9d31cdce19 100644 --- a/dts/src/arm/exynos54xx.dtsi +++ b/dts/src/arm/exynos54xx.dtsi @@ -14,7 +14,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos5.dtsi" / { diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts index 5ec71e2400..01f466816f 100644 --- a/dts/src/arm/exynos5800-peach-pi.dts +++ b/dts/src/arm/exynos5800-peach-pi.dts @@ -79,7 +79,8 @@ }; - memory { + memory@20000000 { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; @@ -179,7 +180,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; @@ -722,171 +723,171 @@ wifi_en: wifi-en { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; max98091_irq: max98091-irq { samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ mask_tpm_reset: mask-tpm-reset { samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; samsung,pin-val = <0>; }; tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; ec_irq: ec-irq { samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; max77802_irq: max77802-irq { samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; lid_irq: lid-irq { samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_1 { /* Adjust WiFi drive strengths lower for EMI */ sd1_clk: sd1-clk { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_cmd: sd1-cmd { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; }; &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; &pinctrl_3 { /* Drive SPI lines at x2 for better integrity */ spi2-bus { - samsung,pin-drv = <2>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; /* Drive SPI chip select at x2 for better integrity */ ec_spi_cs: ec-spi-cs { samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; pmic_selb: pmic-selb { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/imx35.dtsi b/dts/src/arm/imx35.dtsi index 490b7b44f1..f812d586c5 100644 --- a/dts/src/arm/imx35.dtsi +++ b/dts/src/arm/imx35.dtsi @@ -309,6 +309,13 @@ status = "disabled"; }; + iim@53ff0000 { + compatible = "fsl,imx35-iim"; + reg = <0x53ff0000 0x4000>; + interrupts = <19>; + clocks = <&clks 80>; + }; + usbotg: usb@53ff4000 { compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; diff --git a/dts/src/arm/imx50.dtsi b/dts/src/arm/imx50.dtsi index e245713831..8fe8beeb68 100644 --- a/dts/src/arm/imx50.dtsi +++ b/dts/src/arm/imx50.dtsi @@ -227,6 +227,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 151 28>; }; gpio2: gpio@53f88000 { @@ -237,6 +238,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, + <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, + <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, + <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; }; gpio3: gpio@53f8c000 { @@ -247,6 +252,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 108 32>; }; gpio4: gpio@53f90000 { @@ -257,6 +263,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, + <&iomuxc 20 140 11>; }; wdog1: wdog@53f98000 { @@ -346,6 +354,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; }; gpio6: gpio@53fe0000 { @@ -356,6 +365,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; }; i2c3: i2c@53fec000 { diff --git a/dts/src/arm/imx53-usbarmory.dts b/dts/src/arm/imx53-usbarmory.dts new file mode 100644 index 0000000000..6782d7fc59 --- /dev/null +++ b/dts/src/arm/imx53-usbarmory.dts @@ -0,0 +1,224 @@ +/* + * USB armory MkI device tree file + * https://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano <andrej@inversepath.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "Inverse Path USB armory"; + compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; +}; + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x70000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user { + label = "LED"; + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* + * Not every i.MX53 P/N supports clock > 800MHz. + * As USB armory does not mount a specific P/N set a safe clock upper limit. + */ +&cpu0 { + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + >; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_i2c1_pmic: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x80 + MX53_PAD_EIM_D28__I2C1_SDA 0x80 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 + >; + }; + + /* + * UART mode pin header configration + * 3 - GPIO5[26], pull-down 100K + * 4 - GPIO5[27], pull-down 100K + * 5 - TX, pull-up 100K + * 6 - RX, pull-up 100K + * 7 - GPIO5[30], pull-down 100K + */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 + MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 + >; + }; +}; + +&i2c1 { + pinctrl-0 = <&pinctrl_i2c1_pmic>; + status = "okay"; + + ltc3589: pmic@34 { + compatible = "lltc,ltc3589-2"; + reg = <0x34>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <591930>; + regulator-max-microvolt = <1224671>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456803>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1341250>; + regulator-max-microvolt = <2775000>; + lltc,fb-voltage-divider = <270000 100000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + bb_out_reg: bb-out { + regulator-min-microvolt = <3387341>; + regulator-max-microvolt = <3387341>; + lltc,fb-voltage-divider = <511000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-min-microvolt = <1306329>; + regulator-max-microvolt = <1306329>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456806>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3200000>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi index cd170376ea..0777b41cdf 100644 --- a/dts/src/arm/imx53.dtsi +++ b/dts/src/arm/imx53.dtsi @@ -136,6 +136,14 @@ clock-names = "bus", "di0", "di1"; resets = <&src 2>; + ipu_csi0: port@0 { + reg = <0>; + }; + + ipu_csi1: port@1 { + reg = <1>; + }; + ipu_di0: port@2 { #address-cells = <1>; #size-cells = <0>; @@ -217,6 +225,8 @@ clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -498,6 +508,8 @@ clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -508,6 +520,8 @@ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -591,6 +605,8 @@ clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; @@ -621,6 +637,8 @@ clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/dts/src/arm/imx6dl-gw553x.dts b/dts/src/arm/imx6dl-gw553x.dts new file mode 100644 index 0000000000..59b8afc36e --- /dev/null +++ b/dts/src/arm/imx6dl-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; + compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/dts/src/arm/imx6dl-riotboard.dts b/dts/src/arm/imx6dl-riotboard.dts index 2becd7cd65..75d73437ad 100644 --- a/dts/src/arm/imx6dl-riotboard.dts +++ b/dts/src/arm/imx6dl-riotboard.dts @@ -376,18 +376,18 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ diff --git a/dts/src/arm/imx6dl-ts4900.dts b/dts/src/arm/imx6dl-ts4900.dts new file mode 100644 index 0000000000..85eddeb30e --- /dev/null +++ b/dts/src/arm/imx6dl-ts4900.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; +}; diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi index 9a4c22c2da..1ade1951e6 100644 --- a/dts/src/arm/imx6dl.dtsi +++ b/dts/src/arm/imx6dl.dtsi @@ -111,6 +111,59 @@ }; }; +&gpio1 { + gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, + <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, + <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, + <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, + <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, + <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, + <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, + <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, + <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, + <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, + <&iomuxc 28 113 4>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, + <&iomuxc 16 81 16>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, + <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, + <&iomuxc 11 151 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, + <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, + <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, + <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, + <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, + <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, + <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, + <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, + <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, + <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, + <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, + <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, + <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; +}; + &gpt { compatible = "fsl,imx6dl-gpt"; }; diff --git a/dts/src/arm/imx6q-arm2.dts b/dts/src/arm/imx6q-arm2.dts index d8acf15611..4989d0bff1 100644 --- a/dts/src/arm/imx6q-arm2.dts +++ b/dts/src/arm/imx6q-arm2.dts @@ -79,19 +79,19 @@ fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; diff --git a/dts/src/arm/imx6q-b450v3.dts b/dts/src/arm/imx6q-b450v3.dts index f0a2be5268..78bfc1a307 100644 --- a/dts/src/arm/imx6q-b450v3.dts +++ b/dts/src/arm/imx6q-b450v3.dts @@ -89,3 +89,19 @@ }; }; }; + +&pca9539 { + P04 { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "PCA9539-P04"; + }; + + P05 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "PCA9539-P05"; + }; +}; diff --git a/dts/src/arm/imx6q-b650v3.dts b/dts/src/arm/imx6q-b650v3.dts index 33cb71acad..d853887254 100644 --- a/dts/src/arm/imx6q-b650v3.dts +++ b/dts/src/arm/imx6q-b650v3.dts @@ -89,3 +89,12 @@ }; }; }; + +&pca9539 { + P05 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "PCA9539-P05"; + }; +}; diff --git a/dts/src/arm/imx6q-ba16.dtsi b/dts/src/arm/imx6q-ba16.dtsi index f2adc60723..308e11cea1 100644 --- a/dts/src/arm/imx6q-ba16.dtsi +++ b/dts/src/arm/imx6q-ba16.dtsi @@ -448,19 +448,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* FEC Reset */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* AR8033 Interrupt */ diff --git a/dts/src/arm/imx6q-bx50v3.dtsi b/dts/src/arm/imx6q-bx50v3.dtsi index cf3fd31e34..e4a415fd89 100644 --- a/dts/src/arm/imx6q-bx50v3.dtsi +++ b/dts/src/arm/imx6q-bx50v3.dtsi @@ -183,6 +183,76 @@ interrupt-controller; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + P06 { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "PCA9539-P06"; + }; + + P07 { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; + + P10 { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "PCA9539-P10"; + }; + + P11 { + gpio-hog; + gpios = <9 0>; + output-low; + line-name = "PCA9539-P11"; + }; + + P12 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PCA9539-P12"; + }; + + P13 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "PCA9539-P13"; + }; + + P14 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "PCA9539-P14"; + }; + + P15 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "PCA9539-P15"; + }; + + P16 { + gpio-hog; + gpios = <14 0>; + output-low; + line-name = "PCA9539-P16"; + }; + + P17 { + gpio-hog; + gpios = <15 0>; + output-low; + line-name = "PCA9539-P17"; + }; }; }; diff --git a/dts/src/arm/imx6q-cm-fx6.dts b/dts/src/arm/imx6q-cm-fx6.dts index b5de7e6209..59bc5a4dce 100644 --- a/dts/src/arm/imx6q-cm-fx6.dts +++ b/dts/src/arm/imx6q-cm-fx6.dts @@ -168,18 +168,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/dts/src/arm/imx6q-dmo-edmqmx6.dts b/dts/src/arm/imx6q-dmo-edmqmx6.dts index 905907325f..908dab68bd 100644 --- a/dts/src/arm/imx6q-dmo-edmqmx6.dts +++ b/dts/src/arm/imx6q-dmo-edmqmx6.dts @@ -324,18 +324,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/dts/src/arm/imx6q-evi.dts b/dts/src/arm/imx6q-evi.dts index 4fa5601922..6de21ff47c 100644 --- a/dts/src/arm/imx6q-evi.dts +++ b/dts/src/arm/imx6q-evi.dts @@ -139,6 +139,9 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; @@ -303,21 +306,22 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; diff --git a/dts/src/arm/imx6q-gw5400-a.dts b/dts/src/arm/imx6q-gw5400-a.dts index 0511137d1e..747bc104ad 100644 --- a/dts/src/arm/imx6q-gw5400-a.dts +++ b/dts/src/arm/imx6q-gw5400-a.dts @@ -421,18 +421,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/dts/src/arm/imx6q-gw553x.dts b/dts/src/arm/imx6q-gw553x.dts new file mode 100644 index 0000000000..e9c224cea7 --- /dev/null +++ b/dts/src/arm/imx6q-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; + compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/dts/src/arm/imx6q-marsboard.dts b/dts/src/arm/imx6q-marsboard.dts index 3f8013c85f..f7995c513b 100644 --- a/dts/src/arm/imx6q-marsboard.dts +++ b/dts/src/arm/imx6q-marsboard.dts @@ -252,26 +252,26 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* RGMII_nRST */ diff --git a/dts/src/arm/imx6q-novena.dts b/dts/src/arm/imx6q-novena.dts index 5acd0c63b3..1723e89e3a 100644 --- a/dts/src/arm/imx6q-novena.dts +++ b/dts/src/arm/imx6q-novena.dts @@ -549,12 +549,12 @@ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* Ethernet reset */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 diff --git a/dts/src/arm/imx6q-sbc6x.dts b/dts/src/arm/imx6q-sbc6x.dts index 86cf093646..255733063e 100644 --- a/dts/src/arm/imx6q-sbc6x.dts +++ b/dts/src/arm/imx6q-sbc6x.dts @@ -31,19 +31,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; diff --git a/dts/src/arm/imx6q-tbs2910.dts b/dts/src/arm/imx6q-tbs2910.dts index d7c8ccb2da..06f492e17c 100644 --- a/dts/src/arm/imx6q-tbs2910.dts +++ b/dts/src/arm/imx6q-tbs2910.dts @@ -284,19 +284,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 >; diff --git a/dts/src/arm/imx6q-ts4900.dts b/dts/src/arm/imx6q-ts4900.dts new file mode 100644 index 0000000000..9b81ebc8b0 --- /dev/null +++ b/dts/src/arm/imx6q-ts4900.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/dts/src/arm/imx6q.dtsi b/dts/src/arm/imx6q.dtsi index c30c8368ca..e9a5d0b8c7 100644 --- a/dts/src/arm/imx6q.dtsi +++ b/dts/src/arm/imx6q.dtsi @@ -209,6 +209,43 @@ }; }; +&gpio1 { + gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, + <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, + <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, + <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, + <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, + <&iomuxc 22 116 10>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, + <&iomuxc 31 44 1>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, + <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, + <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, + <&iomuxc 31 86 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; +}; + &hdmi { compatible = "fsl,imx6q-hdmi"; diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi index 315e033ff1..99e323b572 100644 --- a/dts/src/arm/imx6qdl-apalis.dtsi +++ b/dts/src/arm/imx6qdl-apalis.dtsi @@ -586,19 +586,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Ethernet PHY reset */ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 /* Ethernet PHY interrupt */ diff --git a/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi b/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi index da1341d47b..b2c083d575 100644 --- a/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi +++ b/dts/src/arm/imx6qdl-dfi-fs700-m60.dtsi @@ -67,18 +67,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/dts/src/arm/imx6qdl-gw51xx.dtsi b/dts/src/arm/imx6qdl-gw51xx.dtsi index 9d7ab6cdc9..afec2c7628 100644 --- a/dts/src/arm/imx6qdl-gw51xx.dtsi +++ b/dts/src/arm/imx6qdl-gw51xx.dtsi @@ -228,22 +228,28 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw51xx { pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 @@ -364,5 +370,11 @@ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw52xx.dtsi b/dts/src/arm/imx6qdl-gw52xx.dtsi index 7191b84770..a7100f9912 100644 --- a/dts/src/arm/imx6qdl-gw52xx.dtsi +++ b/dts/src/arm/imx6qdl-gw52xx.dtsi @@ -315,6 +315,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -353,6 +355,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw52xx { pinctrl_audmux: audmuxgrp { @@ -376,18 +384,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 @@ -487,6 +495,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; @@ -549,5 +558,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw53xx.dtsi b/dts/src/arm/imx6qdl-gw53xx.dtsi index 40d06b09de..8953eba057 100644 --- a/dts/src/arm/imx6qdl-gw53xx.dtsi +++ b/dts/src/arm/imx6qdl-gw53xx.dtsi @@ -312,6 +312,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -351,6 +353,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw53xx { pinctrl_audmux: audmuxgrp { @@ -365,18 +373,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 @@ -476,6 +484,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; @@ -539,5 +548,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw54xx.dtsi b/dts/src/arm/imx6qdl-gw54xx.dtsi index d6dbe2a88e..6ac41c7ed3 100644 --- a/dts/src/arm/imx6qdl-gw54xx.dtsi +++ b/dts/src/arm/imx6qdl-gw54xx.dtsi @@ -414,6 +414,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -453,6 +455,17 @@ status = "okay"; }; +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { imx6qdl-gw54xx { pinctrl_audmux: audmuxgrp { @@ -467,18 +480,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 @@ -592,6 +605,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; @@ -654,5 +668,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw551x.dtsi b/dts/src/arm/imx6qdl-gw551x.dtsi index 118bea524d..4b9fef8348 100644 --- a/dts/src/arm/imx6qdl-gw551x.dtsi +++ b/dts/src/arm/imx6qdl-gw551x.dtsi @@ -239,6 +239,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw51xx { pinctrl_flexcan1: flexcan1grp { @@ -333,5 +339,11 @@ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw552x.dtsi b/dts/src/arm/imx6qdl-gw552x.dtsi index f27f184558..805e23674a 100644 --- a/dts/src/arm/imx6qdl-gw552x.dtsi +++ b/dts/src/arm/imx6qdl-gw552x.dtsi @@ -197,6 +197,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw552x { pinctrl_gpio_leds: gpioledsgrp { @@ -286,5 +292,11 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/dts/src/arm/imx6qdl-gw553x.dtsi b/dts/src/arm/imx6qdl-gw553x.dtsi new file mode 100644 index 0000000000..86cec0527f --- /dev/null +++ b/dts/src/arm/imx6qdl-gw553x.dtsi @@ -0,0 +1,433 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P0V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/dts/src/arm/imx6qdl-icore-rqs.dtsi b/dts/src/arm/imx6qdl-icore-rqs.dtsi index f8d945a565..d5c3aa88ad 100644 --- a/dts/src/arm/imx6qdl-icore-rqs.dtsi +++ b/dts/src/arm/imx6qdl-icore-rqs.dtsi @@ -254,19 +254,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; diff --git a/dts/src/arm/imx6qdl-nit6xlite.dtsi b/dts/src/arm/imx6qdl-nit6xlite.dtsi index cfd50ea1ed..880bd782a5 100644 --- a/dts/src/arm/imx6qdl-nit6xlite.dtsi +++ b/dts/src/arm/imx6qdl-nit6xlite.dtsi @@ -361,12 +361,12 @@ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 diff --git a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi index 9677bf3238..b0b3220a1f 100644 --- a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi @@ -484,19 +484,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi index 97d9c33390..db868bc42c 100644 --- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi @@ -394,19 +394,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 diff --git a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi index d6d98d4263..e0280cac24 100644 --- a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi +++ b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi @@ -231,19 +231,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; @@ -379,6 +379,18 @@ status = "disabled"; }; +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; diff --git a/dts/src/arm/imx6qdl-rex.dtsi b/dts/src/arm/imx6qdl-rex.dtsi index cacf593370..17704a5c1b 100644 --- a/dts/src/arm/imx6qdl-rex.dtsi +++ b/dts/src/arm/imx6qdl-rex.dtsi @@ -196,19 +196,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* Phy reset */ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 diff --git a/dts/src/arm/imx6qdl-sabreauto.dtsi b/dts/src/arm/imx6qdl-sabreauto.dtsi index 6aa193fb28..e000e6f12b 100644 --- a/dts/src/arm/imx6qdl-sabreauto.dtsi +++ b/dts/src/arm/imx6qdl-sabreauto.dtsi @@ -345,19 +345,19 @@ fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi index f65fdfc253..81dd6cd193 100644 --- a/dts/src/arm/imx6qdl-sabrelite.dtsi +++ b/dts/src/arm/imx6qdl-sabrelite.dtsi @@ -359,19 +359,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 diff --git a/dts/src/arm/imx6qdl-sabresd.dtsi b/dts/src/arm/imx6qdl-sabresd.dtsi index d77ea9423b..8e9e0d98db 100644 --- a/dts/src/arm/imx6qdl-sabresd.dtsi +++ b/dts/src/arm/imx6qdl-sabresd.dtsi @@ -380,19 +380,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; diff --git a/dts/src/arm/imx6qdl-ts4900.dtsi b/dts/src/arm/imx6qdl-ts4900.dtsi new file mode 100644 index 0000000000..5c26b26e85 --- /dev/null +++ b/dts/src/arm/imx6qdl-ts4900.dtsi @@ -0,0 +1,481 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + ethernet0 = &fec; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + green-led { + label = "green-led"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + red-led { + label = "red-led"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + n25q064: flash@0 { + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + gpio8: gpio@28 { + compatible = "technologic,ts4900-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpio = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/dts/src/arm/imx6qdl-udoo.dtsi b/dts/src/arm/imx6qdl-udoo.dtsi index 3bee2f9100..c96c91d836 100644 --- a/dts/src/arm/imx6qdl-udoo.dtsi +++ b/dts/src/arm/imx6qdl-udoo.dtsi @@ -132,18 +132,18 @@ imx6q-udoo { pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/dts/src/arm/imx6qdl-wandboard.dtsi b/dts/src/arm/imx6qdl-wandboard.dtsi index 3ffe00c557..2b9c2be436 100644 --- a/dts/src/arm/imx6qdl-wandboard.dtsi +++ b/dts/src/arm/imx6qdl-wandboard.dtsi @@ -109,19 +109,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi index 542515089b..02378db3f5 100644 --- a/dts/src/arm/imx6sl.dtsi +++ b/dts/src/arm/imx6sl.dtsi @@ -375,6 +375,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, + <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, + <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, + <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, + <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, + <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; }; gpio2: gpio@020a0000 { @@ -386,6 +392,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, + <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, + <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, + <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, + <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, + <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, + <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; }; gpio3: gpio@020a4000 { @@ -397,6 +410,14 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, + <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, + <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, + <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, + <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, + <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, + <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, + <&iomuxc 31 102 1>; }; gpio4: gpio@020a8000 { @@ -408,6 +429,21 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, + <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, + <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, + <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, + <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, + <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, + <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, + <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, + <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, + <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, + <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, + <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, + <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, + <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, + <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; }; gpio5: gpio@020ac000 { @@ -419,6 +455,17 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, + <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, + <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, + <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, + <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, + <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, + <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, + <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, + <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, + <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, + <&iomuxc 21 161 1>; }; kpp: kpp@020b8000 { diff --git a/dts/src/arm/imx6sx-pinfunc.h b/dts/src/arm/imx6sx-pinfunc.h index bb9c6b78cb..42c4c800fe 100644 --- a/dts/src/arm/imx6sx-pinfunc.h +++ b/dts/src/arm/imx6sx-pinfunc.h @@ -308,6 +308,20 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +/* + * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is + * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a + * PHY in RMII mode. This configuration is valid if: + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset + * It seems to be a silicon bug that in this configuration ENET1_TX reference + * clock isn't provided automatically. According to i.MX6SX reference manual + * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it + * should be the case. + * So this might have unwanted side effects for other hardware units that are + * also connected to that pin and using respective function as input (e.g. + * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). + */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi index 2863c52be6..1a473e83ef 100644 --- a/dts/src/arm/imx6sx.dtsi +++ b/dts/src/arm/imx6sx.dtsi @@ -159,6 +159,16 @@ arm,data-latency = <4 2 3>; }; + gpu: gpu@01800000 { + compatible = "vivante,gc"; + reg = <0x01800000 0x4000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>; + clock-names = "bus", "core", "shader"; + }; + dma_apbh: dma-apbh@01804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; @@ -438,6 +448,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 5 26>; }; gpio2: gpio@020a0000 { @@ -449,6 +460,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 31 20>; }; gpio3: gpio@020a4000 { @@ -460,6 +472,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 51 29>; }; gpio4: gpio@020a8000 { @@ -471,6 +484,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 80 32>; }; gpio5: gpio@020ac000 { @@ -482,6 +496,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 24>; }; gpio6: gpio@020b0000 { @@ -493,6 +508,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; gpio7: gpio@020b4000 { @@ -504,6 +520,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; kpp: kpp@020b8000 { @@ -1273,4 +1290,9 @@ status = "disabled"; }; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu>; + }; }; diff --git a/dts/src/arm/imx6ul-geam-kit.dts b/dts/src/arm/imx6ul-geam-kit.dts new file mode 100644 index 0000000000..4c4af76143 --- /dev/null +++ b/dts/src/arm/imx6ul-geam-kit.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6ul-geam.dtsi" + +/ { + model = "Engicam GEAM6UL"; + compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <28000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <30>; + hback-porch = <30>; + hsync-len = <64>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + status = "okay"; +}; + +&tsc { + measure-delay-time = <0x1ffff>; + pre-charge-time = <0x1fff>; + status = "okay"; +}; diff --git a/dts/src/arm/imx6ul-geam.dtsi b/dts/src/arm/imx6ul-geam.dtsi new file mode 100644 index 0000000000..64eb9ed59b --- /dev/null +++ b/dts/src/arm/imx6ul-geam.dtsi @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6ul.dtsi" + +/ { + memory { + reg = <0x80000000 0x08000000>; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 + >; + }; +}; diff --git a/dts/src/arm/imx6ul-pico-hobbit.dts b/dts/src/arm/imx6ul-pico-hobbit.dts index 86f68faded..827d9e8fc7 100644 --- a/dts/src/arm/imx6ul-pico-hobbit.dts +++ b/dts/src/arm/imx6ul-pico-hobbit.dts @@ -100,6 +100,18 @@ gpio = <&gpio1 6 0>; }; + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6ul-sgtl5000"; @@ -325,12 +337,27 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; no-1-8-v; + non-removable; keep-power-in-suspend; wakeup-source; + vmmc-supply = <®_brcm>; status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ + MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ + >; + }; + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 @@ -513,4 +540,10 @@ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; }; diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi index 33b95d7883..c5c05fdccc 100644 --- a/dts/src/arm/imx6ul.dtsi +++ b/dts/src/arm/imx6ul.dtsi @@ -411,6 +411,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, + <&iomuxc 16 33 16>; }; gpio2: gpio@020a0000 { @@ -422,6 +424,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; }; gpio3: gpio@020a4000 { @@ -433,6 +436,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 65 29>; }; gpio4: gpio@020a8000 { @@ -444,6 +448,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; }; gpio5: gpio@020ac000 { @@ -455,6 +460,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; fec2: ethernet@020b4000 { @@ -644,7 +650,8 @@ }; gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6ul-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; diff --git a/dts/src/arm/imx7-colibri-eval-v3.dtsi b/dts/src/arm/imx7-colibri-eval-v3.dtsi index 1545661df5..373ee19196 100644 --- a/dts/src/arm/imx7-colibri-eval-v3.dtsi +++ b/dts/src/arm/imx7-colibri-eval-v3.dtsi @@ -138,10 +138,6 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; keep-power-in-suspend; wakeup-source; status = "okay"; diff --git a/dts/src/arm/imx7-colibri.dtsi b/dts/src/arm/imx7-colibri.dtsi index 0a9d3a822f..a9cc65725f 100644 --- a/dts/src/arm/imx7-colibri.dtsi +++ b/dts/src/arm/imx7-colibri.dtsi @@ -46,12 +46,18 @@ pwms = <&pwm1 0 5000000>; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; reg_vref_1v8: regulator-vref-1v8 { @@ -60,6 +66,22 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; }; &adc1 { @@ -97,6 +119,18 @@ pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; status = "okay"; + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_DCDC3>; + }; + ad7879@2c { compatible = "adi,ad7879-1"; reg = <0x2c>; @@ -217,6 +251,12 @@ vin-supply = <®_DCDC3>; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + &snvs_pwrkey { status = "disabled"; }; @@ -251,6 +291,14 @@ dr_mode = "host"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; @@ -528,13 +576,18 @@ pinctrl_sai1: sai1-grp { fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f >; }; + + pinctrl_sai1_mclk: sai1grp_mclk { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; }; &iomuxc_lpsr { diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi index 51c13cbdff..f6dee41a05 100644 --- a/dts/src/arm/imx7d.dtsi +++ b/dts/src/arm/imx7d.dtsi @@ -45,30 +45,42 @@ / { cpus { + cpu0: cpu@0 { + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-frequency = <996000000>; + }; + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clock-frequency = <996000000>; }; }; - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; + soc { + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; }; }; }; diff --git a/dts/src/arm/imx7s-warp.dts b/dts/src/arm/imx7s-warp.dts new file mode 100644 index 0000000000..0345267f33 --- /dev/null +++ b/dts/src/arm/imx7s-warp.dts @@ -0,0 +1,446 @@ +/* + * Copyright (C) 2016 NXP Semiconductors. + * Author: Fabio Estevam <fabio.estevam@nxp.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx7s.dtsi" + +/ { + model = "Warp i.MX7 Board"; + compatible = "warp,imx7s-warp", "fsl,imx7s"; + + memory { + reg = <0x80000000 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio>; + autorepeat; + + back { + label = "Back"; + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_BACK>; + wakeup-source; + }; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + reg_bt: regulator-bt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_reg>; + enable-active-high; + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + regulator-name = "bt_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: sgtl5000@0a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <&vgen4_reg>; + VDDD-supply = <&vgen2_reg>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ + >; + }; + + pinctrl_bt_reg: btreggrp { + fsl,pins = < + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + >; + }; + + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; +}; diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi index 1e90bdbe3a..0d7d5ac625 100644 --- a/dts/src/arm/imx7s.dtsi +++ b/dts/src/arm/imx7s.dtsi @@ -85,26 +85,12 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; + clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; }; }; - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x31001000 0x1000>, - <0x31002000 0x1000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - ckil: clock-cki { compatible = "fixed-clock"; #clock-cells = <0>; @@ -119,195 +105,205 @@ clock-output-names = "osc"; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; interrupt-parent = <&intc>; - }; + ranges; + + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + ca_funnel_ports: ports { + #address-cells = <1>; + #size-cells = <0>; - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + /* the other input ports are not connect to anything */ }; }; - }; - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; }; }; - }; - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; }; - }; - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; }; + + /* the other input ports are not connect to anything */ }; }; - }; - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&hugo_funnel_out_port0>; + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; }; - }; - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; }; }; }; - }; - - funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - /* funnel input ports */ - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { + port { + etr_in_port: endpoint { slave-mode; - remote-endpoint = <&ca_funnel_out_port0>; + remote-endpoint = <&replicator_out_port1>; }; }; + }; - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ - }; - }; + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port@2 { - reg = <0>; - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; }; }; - - /* the other input ports are not connect to anything */ }; - }; - funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; - ca_funnel_ports: ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - /* funnel input ports */ - port@0 { - reg = <0>; - ca_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; }; - }; - /* funnel output port */ - port@2 { - reg = <0>; - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; }; - }; - /* the other input ports are not connect to anything */ + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; }; - }; - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; }; - }; - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -325,6 +321,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; }; gpio2: gpio@30210000 { @@ -336,6 +333,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 13 32>; }; gpio3: gpio@30220000 { @@ -347,6 +345,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 45 29>; }; gpio4: gpio@30230000 { @@ -358,6 +357,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 74 24>; }; gpio5: gpio@30240000 { @@ -369,6 +369,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 98 18>; }; gpio6: gpio@30250000 { @@ -380,6 +381,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 116 23>; }; gpio7: gpio@30260000 { @@ -391,6 +393,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 139 16>; }; wdog1: wdog@30280000 { @@ -723,6 +726,51 @@ status = "disabled"; }; + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; + flexcan1: can@30a00000 { compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; reg = <0x30a00000 0x10000>; @@ -911,6 +959,17 @@ status = "disabled"; }; + sdma: sdma@30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SDMA_CORE_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; diff --git a/dts/src/arm/integratorap.dts b/dts/src/arm/integratorap.dts index 4b34b54e09..6f16d09dc5 100644 --- a/dts/src/arm/integratorap.dts +++ b/dts/src/arm/integratorap.dts @@ -19,7 +19,7 @@ bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; }; - /* 24 MHz chrystal on the core module */ + /* 24 MHz chrystal on the Integrator/AP development board */ xtal24mhz: xtal24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -39,6 +39,34 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; + clocks = <&xtal24mhz>; + }; + + core-module@10000000 { + /* 24 MHz chrystal on the core module */ + cm24mhz: cm24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* Oscillator on the core module, clocks the CPU core */ + cmosc: cmosc@24M { + compatible = "arm,syscon-icst525-integratorap-cm"; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Auxilary oscillator on the core module, 32.369MHz at boot */ + auxosc: auxosc@24M { + compatible = "arm,syscon-icst525"; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x1c>; + clocks = <&cm24mhz>; + }; }; syscon { @@ -47,6 +75,27 @@ interrupt-parent = <&pic>; /* These are the logical module IRQs */ interrupts = <9>, <10>, <11>, <12>; + + /* + * SYSCLK clocks PCIv3 bridge, system controller and the + * logic modules. + */ + sysclk: apsys@24M { + compatible = "arm,syscon-icst525-integratorap-sys"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; + + /* One-bit control for the PCI bus clock (33 or 25 MHz) */ + pciclk: pciclk@24M { + compatible = "arm,syscon-icst525-integratorap-pci"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; }; timer0: timer@13000000 { diff --git a/dts/src/arm/integratorcp.dts b/dts/src/arm/integratorcp.dts index 79430fbfec..1b5e4b006b 100644 --- a/dts/src/arm/integratorcp.dts +++ b/dts/src/arm/integratorcp.dts @@ -58,20 +58,37 @@ core-module@10000000 { /* 24 MHz chrystal on the core module */ - xtal24mhz: xtal24mhz@24M { + cm24mhz: cm24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - /* - * External oscillator on the core module, usually used - * to drive video circuitry. Driven from the 24MHz clock. - */ - auxosc: cm_aux_osc@25M { + /* Oscillator on the core module, clocks the CPU core */ + cmcore: cmosc@24M { + compatible = "arm,syscon-icst525-integratorcp-cm-core"; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Oscillator on the core module, clocks the memory bus */ + cmmem: cmosc@24M { + compatible = "arm,syscon-icst525-integratorcp-cm-mem"; + #clock-cells = <0>; + lock-offset = <0x14>; + vco-offset = <0x08>; + clocks = <&cm24mhz>; + }; + + /* Auxilary oscillator on the core module, clocks the CLCD */ + auxosc: auxosc@24M { + compatible = "arm,syscon-icst525"; #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; + lock-offset = <0x14>; + vco-offset = <0x1c>; + clocks = <&cm24mhz>; }; /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ @@ -80,7 +97,7 @@ compatible = "fixed-factor-clock"; clock-div = <3>; clock-mult = <1>; - clocks = <&xtal24mhz>; + clocks = <&cm24mhz>; }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ @@ -89,7 +106,7 @@ compatible = "fixed-factor-clock"; clock-div = <24>; clock-mult = <1>; - clocks = <&xtal24mhz>; + clocks = <&cm24mhz>; }; }; @@ -209,7 +226,42 @@ reg = <0xC0000000 0x1000>; interrupts = <22>; clocks = <&auxosc>, <&pclk>; - clock-names = "clcd", "apb_pclk"; + clock-names = "clcdclk", "apb_pclk"; + + port { + /* + * The VGA connected is implemented with a + * THS8134A triple DAC that can be run in 24bit + * or 16bit RGB mode. + */ + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <1 7 13>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + /* Standard 640x480 VGA timings */ + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + }; + }; }; }; }; diff --git a/dts/src/arm/keystone-k2e-evm.dts b/dts/src/arm/keystone-k2e-evm.dts index 4c32ebc142..ae1ebe7ee0 100644 --- a/dts/src/arm/keystone-k2e-evm.dts +++ b/dts/src/arm/keystone-k2e-evm.dts @@ -47,18 +47,26 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &usb1_phy { status = "okay"; }; -&usb1 { +&keystone_usb1 { status = "okay"; }; +&usb1 { + dr_mode = "peripheral"; +}; + &i2c0 { dtt@50 { compatible = "at,24c1024"; diff --git a/dts/src/arm/keystone-k2e.dtsi b/dts/src/arm/keystone-k2e.dtsi index 9a51b8c885..497c417db5 100644 --- a/dts/src/arm/keystone-k2e.dtsi +++ b/dts/src/arm/keystone-k2e.dtsi @@ -61,7 +61,7 @@ status = "disabled"; }; - usb1: usb@25000000 { + keystone_usb1: usb@25000000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -74,7 +74,7 @@ dma-ranges; status = "disabled"; - dwc3@25010000 { + usb1: dwc3@25010000 { compatible = "synopsys,dwc3"; reg = <0x25010000 0x70000>; interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; diff --git a/dts/src/arm/keystone-k2g.dtsi b/dts/src/arm/keystone-k2g.dtsi index 3372615b88..2919c51906 100644 --- a/dts/src/arm/keystone-k2g.dtsi +++ b/dts/src/arm/keystone-k2g.dtsi @@ -83,6 +83,11 @@ pinctrl-single,function-mask = <0x001b0007>; }; + devctrl: device-state-control@02620000 { + compatible = "ti,keystone-devctrl", "syscon"; + reg = <0x02620000 0x1000>; + }; + uart0: serial@02530c00 { compatible = "ns16550a"; current-speed = <115200>; @@ -93,5 +98,32 @@ clock-frequency = <200000000>; status = "disabled"; }; + + kirq0: keystone_irq@026202a0 { + compatible = "ti,keystone-irq"; + interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + msgmgr: msgmgr@02a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", + "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", + "rx_057"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; diff --git a/dts/src/arm/keystone-k2hk-evm.dts b/dts/src/arm/keystone-k2hk-evm.dts index b38b344181..2156ff92d0 100644 --- a/dts/src/arm/keystone-k2hk-evm.dts +++ b/dts/src/arm/keystone-k2hk-evm.dts @@ -83,10 +83,14 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &aemif { cs0 { #address-cells = <2>; diff --git a/dts/src/arm/keystone-k2l-evm.dts b/dts/src/arm/keystone-k2l-evm.dts index 7f9c2e94d6..056b42f99d 100644 --- a/dts/src/arm/keystone-k2l-evm.dts +++ b/dts/src/arm/keystone-k2l-evm.dts @@ -32,10 +32,14 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &i2c0 { dtt@50 { compatible = "at,24c1024"; diff --git a/dts/src/arm/keystone.dtsi b/dts/src/arm/keystone.dtsi index e23f46d15c..02708ba2d4 100644 --- a/dts/src/arm/keystone.dtsi +++ b/dts/src/arm/keystone.dtsi @@ -188,7 +188,7 @@ status = "disabled"; }; - usb: usb@2680000 { + keystone_usb0: usb@2680000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -201,7 +201,7 @@ dma-ranges; status = "disabled"; - dwc3@2690000 { + usb0: dwc3@2690000 { compatible = "synopsys,dwc3"; reg = <0x2690000 0x70000>; interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; diff --git a/dts/src/arm/kirkwood-openblocks_a6.dts b/dts/src/arm/kirkwood-openblocks_a6.dts index 0db0e3edc8..94e49f32d5 100644 --- a/dts/src/arm/kirkwood-openblocks_a6.dts +++ b/dts/src/arm/kirkwood-openblocks_a6.dts @@ -41,7 +41,7 @@ }; pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; + pinctrl-0 = <&pmx_dip_switches>; pinctrl-names = "default"; pmx_uart0: pmx-uart0 { @@ -174,3 +174,10 @@ phy-handle = <ðphy0>; }; }; + +&gpio0 { + status = "okay"; + + pinctrl-0 = <&pmx_gpio_header>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi index 1c2c746554..731ec37aed 100644 --- a/dts/src/arm/logicpd-torpedo-som.dtsi +++ b/dts/src/arm/logicpd-torpedo-som.dtsi @@ -13,6 +13,11 @@ }; }; + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + leds { compatible = "gpio-leds"; user0 { diff --git a/dts/src/arm/lpc18xx.dtsi b/dts/src/arm/lpc18xx.dtsi index fdb736c820..7cae9c5e27 100644 --- a/dts/src/arm/lpc18xx.dtsi +++ b/dts/src/arm/lpc18xx.dtsi @@ -20,6 +20,9 @@ #define LPC_GPIO(port, pin) (port * 32 + pin) / { + #address-cells = <1>; + #size-cells = <1>; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -186,6 +189,10 @@ clock-names = "stmmaceth"; resets = <&rgu 22>; reset-names = "stmmaceth"; + rx-fifo-depth = <256>; + tx-fifo-depth = <256>; + snps,pbl = <4>; /* 32 (8x mode) */ + snps,force_thresh_dma_mode; status = "disabled"; }; diff --git a/dts/src/arm/lpc32xx.dtsi b/dts/src/arm/lpc32xx.dtsi index e295e1ec82..b5841fab51 100644 --- a/dts/src/arm/lpc32xx.dtsi +++ b/dts/src/arm/lpc32xx.dtsi @@ -51,9 +51,19 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>, + ranges = <0x00000000 0x00000000 0x10000000>, + <0x20000000 0x20000000 0x30000000>, <0xe0000000 0xe0000000 0x04000000>; + iram: sram@08000000 { + compatible = "mmio-sram"; + reg = <0x08000000 0x20000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x08000000 0x20000>; + }; + /* * Enable either SLC or MLC */ diff --git a/dts/src/arm/lpc4337-ciaa.dts b/dts/src/arm/lpc4337-ciaa.dts index 5cfadb06c8..7c16d639a1 100644 --- a/dts/src/arm/lpc4337-ciaa.dts +++ b/dts/src/arm/lpc4337-ciaa.dts @@ -30,7 +30,7 @@ stdout-path = &uart2; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x0800000>; /* 8 MB */ }; diff --git a/dts/src/arm/lpc4350-hitex-eval.dts b/dts/src/arm/lpc4350-hitex-eval.dts index 6c9048d4d0..874c75d440 100644 --- a/dts/src/arm/lpc4350-hitex-eval.dts +++ b/dts/src/arm/lpc4350-hitex-eval.dts @@ -33,7 +33,7 @@ stdout-path = &uart0; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x800000>; /* 8 MB */ }; @@ -424,7 +424,7 @@ /* NXP SE97BTP with temperature sensor + eeprom */ sensor@18 { - compatible = "nxp,jc42"; + compatible = "nxp,se97", "jedec,jc-42.4-temp"; reg = <0x18>; }; diff --git a/dts/src/arm/lpc4357-ea4357-devkit.dts b/dts/src/arm/lpc4357-ea4357-devkit.dts index 1919be4dab..9b5fad6225 100644 --- a/dts/src/arm/lpc4357-ea4357-devkit.dts +++ b/dts/src/arm/lpc4357-ea4357-devkit.dts @@ -33,7 +33,7 @@ stdout-path = &uart0; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x2000000>; /* 32 MB */ }; diff --git a/dts/src/arm/ls1021a-twr.dts b/dts/src/arm/ls1021a-twr.dts index 75ecaed32a..a8b148ad1d 100644 --- a/dts/src/arm/ls1021a-twr.dts +++ b/dts/src/arm/ls1021a-twr.dts @@ -108,12 +108,23 @@ panel: panel { compatible = "nec,nl4827hc19-05b"; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; }; }; &dcu { - fsl,panel = <&panel>; status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &dspi1 { diff --git a/dts/src/arm/meson8b.dtsi b/dts/src/arm/meson8b.dtsi index fc4080de4b..41fd536718 100644 --- a/dts/src/arm/meson8b.dtsi +++ b/dts/src/arm/meson8b.dtsi @@ -162,6 +162,27 @@ reg = <0xc1108000 0x4>, <0xc1104000 0x460>; }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc1108550 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc1108650 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc11086c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + pinctrl_cbus: pinctrl@c1109880 { compatible = "amlogic,meson8b-cbus-pinctrl"; reg = <0xc1109880 0x10>; diff --git a/dts/src/arm/mps2.dtsi b/dts/src/arm/mps2.dtsi index e3fed8d345..efb8a03cb9 100644 --- a/dts/src/arm/mps2.dtsi +++ b/dts/src/arm/mps2.dtsi @@ -42,6 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" / { diff --git a/dts/src/arm/ntc-gr8-evb.dts b/dts/src/arm/ntc-gr8-evb.dts new file mode 100644 index 0000000000..4b622f3b52 --- /dev/null +++ b/dts/src/arm/ntc-gr8-evb.dts @@ -0,0 +1,342 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Mylène Josserand <mylene.josserand@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "ntc-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "NextThing GR8-EVB"; + compatible = "nextthing,gr8-evb", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 10000 0>; + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + wm8978: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@190 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <190000>; + }; + + button@390 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <390000>; + }; + + button@600 { + label = "Menu"; + linux,code = <KEY_MENU>; + channel = <0>; + voltage = <600000>; + }; + + button@800 { + label = "Search"; + linux,code = <KEY_SEARCH>; + channel = <0>; + voltage = <800000>; + }; + + button@980 { + label = "Home"; + linux,code = <KEY_HOMEPAGE>; + channel = <0>; + voltage = <980000>; + }; + + button@1180 { + label = "Esc"; + linux,code = <KEY_ESC>; + channel = <0>; + voltage = <1180000>; + }; + + button@1400 { + label = "Enter"; + linux,code = <KEY_ENTER>; + channel = <0>; + voltage = <1400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + + /* MLC Support sucks for now */ + status = "disabled"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_pin_gr8_evb: usb0-id-pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_gr8_evb>; + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&rtp { + allwinner,ts-attached; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; + +&tve0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; + status = "okay"; +}; + +&usb_otg { + /* + * The GR8-EVB has a somewhat interesting design. There's a + * pin supposed to control VBUS, an ID pin, a VBUS detect pin, + * so everything should work just fine. + * + * Except that the pin supposed to control VBUS is not + * connected to any controllable output, neither to the SoC + * through a GPIO or to the PMIC, and it is pulled down, + * meaning that we will never be able to enable VBUS on this + * board. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/ntc-gr8.dtsi b/dts/src/arm/ntc-gr8.dtsi new file mode 100644 index 0000000000..ca54e03ef3 --- /dev/null +++ b/dts/src/arm/ntc-gr8.dtsi @@ -0,0 +1,1087 @@ +/* + * Copyright 2016 Mylène Josserand + * + * Mylène Josserand <mylene.josserand@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/sun4i-a10-pll2.h> +#include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&cpu>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc3M: osc3M-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + + osc32k: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-pll2-clk"; + reg = <0x01c20008 0x8>; + clocks = <&osc24M>; + clock-output-names = "pll2-1x", "pll2-2x", + "pll2-4x", "pll2-8x"; + }; + + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2-clk { + compatible = "allwinner,sun4i-a10-pll3-2x-clk"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + + pll4: clk@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll5: clk@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2-clk { + compatible = "allwinner,sun4i-a10-pll3-2x-clk"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + + /* dummy is 200M */ + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 1>; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + + apb1: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + + axi_gates: clk@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + ahb_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <17>, <20>, + <21>, <22>, + <28>, <32>, <34>, + <36>, <40>, <44>, + <46>, <51>, + <52>; + clock-output-names = "ahb_usbotg", "ahb_ehci", + "ahb_ohci", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_nand", + "ahb_sdram", "ahb_emac", "ahb_spi0", + "ahb_spi1", "ahb_spi2", + "ahb_hstimer", "ahb_ve", "ahb_tve", + "ahb_lcd", "ahb_csi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", + "ahb_mali400"; + }; + + apb0_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>; + clock-output-names = "apb0_codec", "apb0_i2s0", + "apb0_pio", "apb0_ir"; + }; + + apb1_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <18>, <19>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_uart1", + "apb1_uart2", "apb1_uart3"; + }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s0"; + }; + + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "nextthing,gr8-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; + + de_be_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + + de_fe_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe"; + }; + + tcon_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + tcon_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + + codec_clk: clk@01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "codec"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tve0: tv-encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + }; + }; + }; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <32>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + + dr_mode = "otg"; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@01c20800 { + compatible = "nextthing,gr8-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2s0_data_pins_a: i2s0-data@0 { + allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,function = "i2s0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2s0_mclk_pins_a: i2s0-mclk@0 { + allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,function = "i2s0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; + allwinner,function = "ir0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + lcd_rgb666_pins: lcd-rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_pins_a: nand-base0@0 { + allwinner,pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_cs0_pins_a: nand-cs@0 { + allwinner,pins = "PC4"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_rb0_pins_a: nand-rb@0 { + allwinner,pins = "PC6"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB10"; + allwinner,function = "spdif"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + uart1_pins_a: uart1@1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart1_cts_rts_pins_a: uart1-cts-rts@0 { + allwinner,pins = "PG5", "PG6"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + i2s0: i2s@01c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@01c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-codec"; + reg = <0x01c22c00 0x40>; + interrupts = <30>; + clocks = <&apb0_gates 0>, <&codec_clk>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtp: rtp@01c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + timer@01c60000 { + compatible = "allwinner,sun5i-a13-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <82>, <83>; + clocks = <&ahb_gates 28>; + }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + status = "disabled"; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; + }; +}; diff --git a/dts/src/arm/omap2.dtsi b/dts/src/arm/omap2.dtsi index 578fa2a54d..4f793a025a 100644 --- a/dts/src/arm/omap2.dtsi +++ b/dts/src/arm/omap2.dtsi @@ -12,11 +12,11 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> -#include "skeleton.dtsi" - / { compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart1; diff --git a/dts/src/arm/omap2420-h4.dts b/dts/src/arm/omap2420-h4.dts index 34cdecb4fd..9265c0b9c3 100644 --- a/dts/src/arm/omap2420-h4.dts +++ b/dts/src/arm/omap2420-h4.dts @@ -13,7 +13,7 @@ model = "TI OMAP2420 H4 board"; compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; /* 64 MB */ }; diff --git a/dts/src/arm/omap2420-n8x0-common.dtsi b/dts/src/arm/omap2420-n8x0-common.dtsi index db95aadcca..7e5ffc583c 100644 --- a/dts/src/arm/omap2420-n8x0-common.dtsi +++ b/dts/src/arm/omap2420-n8x0-common.dtsi @@ -1,7 +1,7 @@ #include "omap2420.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/dts/src/arm/omap2430-sdp.dts b/dts/src/arm/omap2430-sdp.dts index 6b36ede584..4f7d9d7c00 100644 --- a/dts/src/arm/omap2430-sdp.dts +++ b/dts/src/arm/omap2430-sdp.dts @@ -13,7 +13,7 @@ model = "TI OMAP2430 SDP"; compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/dts/src/arm/omap3-beagle-xm.dts b/dts/src/arm/omap3-beagle-xm.dts index 8ffde06281..85e297ed0e 100644 --- a/dts/src/arm/omap3-beagle-xm.dts +++ b/dts/src/arm/omap3-beagle-xm.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/omap3-beagle.dts b/dts/src/arm/omap3-beagle.dts index a19d907d48..4be85ce59d 100644 --- a/dts/src/arm/omap3-beagle.dts +++ b/dts/src/arm/omap3-beagle.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-cm-t3x.dtsi b/dts/src/arm/omap3-cm-t3x.dtsi index 6a0df13fa0..57b9a028a4 100644 --- a/dts/src/arm/omap3-cm-t3x.dtsi +++ b/dts/src/arm/omap3-cm-t3x.dtsi @@ -4,7 +4,7 @@ / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-devkit8000-common.dtsi b/dts/src/arm/omap3-devkit8000-common.dtsi index 5860101797..f330c69cc6 100644 --- a/dts/src/arm/omap3-devkit8000-common.dtsi +++ b/dts/src/arm/omap3-devkit8000-common.dtsi @@ -10,7 +10,7 @@ #include "omap34xx.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-evm-37xx.dts b/dts/src/arm/omap3-evm-37xx.dts index ed449827c3..4f9a765446 100644 --- a/dts/src/arm/omap3-evm-37xx.dts +++ b/dts/src/arm/omap3-evm-37xx.dts @@ -15,7 +15,7 @@ model = "TI OMAP37XX EVM (TMDSEVM3730)"; compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-evm.dts b/dts/src/arm/omap3-evm.dts index e10dcd0fa5..99b2bfcd10 100644 --- a/dts/src/arm/omap3-evm.dts +++ b/dts/src/arm/omap3-evm.dts @@ -14,7 +14,7 @@ model = "TI OMAP35XX EVM (TMDSEVM3530)"; compatible = "ti,omap3-evm", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi index c09a0574af..b3a8b1f244 100644 --- a/dts/src/arm/omap3-gta04.dtsi +++ b/dts/src/arm/omap3-gta04.dtsi @@ -21,7 +21,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; @@ -102,7 +102,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm11 0 2000000 0>; + pwms = <&pwm11 0 12000000 0>; pwm-names = "backlight"; brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; default-brightness-level = <9>; /* => 90 */ diff --git a/dts/src/arm/omap3-igep.dtsi b/dts/src/arm/omap3-igep.dtsi index f4f2ce46d6..54c4c07bbe 100644 --- a/dts/src/arm/omap3-igep.dtsi +++ b/dts/src/arm/omap3-igep.dtsi @@ -13,7 +13,7 @@ #include "omap36xx.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/omap3-ldp.dts b/dts/src/arm/omap3-ldp.dts index 2f353dadfa..e28fe13cb0 100644 --- a/dts/src/arm/omap3-ldp.dts +++ b/dts/src/arm/omap3-ldp.dts @@ -15,7 +15,7 @@ model = "TI OMAP3430 LDP (Zoom1 Labrador)"; compatible = "ti,omap3-ldp", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/dts/src/arm/omap3-lilly-a83x.dtsi b/dts/src/arm/omap3-lilly-a83x.dtsi index eff816e0bc..fa611a5e48 100644 --- a/dts/src/arm/omap3-lilly-a83x.dtsi +++ b/dts/src/arm/omap3-lilly-a83x.dtsi @@ -17,7 +17,7 @@ bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/dts/src/arm/omap3-n900.dts b/dts/src/arm/omap3-n900.dts index 2a6078a842..87ca50b530 100644 --- a/dts/src/arm/omap3-n900.dts +++ b/dts/src/arm/omap3-n900.dts @@ -54,7 +54,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-n950-n9.dtsi b/dts/src/arm/omap3-n950-n9.dtsi index 927b17fc4e..5d8c4b4a42 100644 --- a/dts/src/arm/omap3-n950-n9.dtsi +++ b/dts/src/arm/omap3-n950-n9.dtsi @@ -24,12 +24,12 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; - vemmc: fixedregulator@0 { + vemmc: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "VEMMC"; regulator-min-microvolt = <2900000>; @@ -39,7 +39,7 @@ enable-active-high; }; - vwlan_fixed: fixedregulator@2 { + vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "VWLAN"; gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ diff --git a/dts/src/arm/omap3-overo-alto35-common.dtsi b/dts/src/arm/omap3-overo-alto35-common.dtsi index 3b3a75997f..99a7eee6e6 100644 --- a/dts/src/arm/omap3-overo-alto35-common.dtsi +++ b/dts/src/arm/omap3-overo-alto35-common.dtsi @@ -44,7 +44,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&button_pins>; - button0@10 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ diff --git a/dts/src/arm/omap3-overo-base.dtsi b/dts/src/arm/omap3-overo-base.dtsi index 3e946cac55..401fae838f 100644 --- a/dts/src/arm/omap3-overo-base.dtsi +++ b/dts/src/arm/omap3-overo-base.dtsi @@ -11,6 +11,12 @@ */ / { + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; + pwmleds { compatible = "pwm-leds"; diff --git a/dts/src/arm/omap3-overo-chestnut43-common.dtsi b/dts/src/arm/omap3-overo-chestnut43-common.dtsi index 4f4c6efbd5..56dbd11343 100644 --- a/dts/src/arm/omap3-overo-chestnut43-common.dtsi +++ b/dts/src/arm/omap3-overo-chestnut43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = <BTN_1>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/dts/src/arm/omap3-overo-common-lcd35.dtsi b/dts/src/arm/omap3-overo-common-lcd35.dtsi index ca86da6822..854117dc0b 100644 --- a/dts/src/arm/omap3-overo-common-lcd35.dtsi +++ b/dts/src/arm/omap3-overo-common-lcd35.dtsi @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - lcd0: display { + lcd0: display@1 { compatible = "lgphilips,lb035q02"; label = "lcd35"; diff --git a/dts/src/arm/omap3-overo-gallop43-common.dtsi b/dts/src/arm/omap3-overo-gallop43-common.dtsi index 250cc7fe5d..286f5baddf 100644 --- a/dts/src/arm/omap3-overo-gallop43-common.dtsi +++ b/dts/src/arm/omap3-overo-gallop43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = <BTN_1>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/dts/src/arm/omap3-overo-palo35-common.dtsi b/dts/src/arm/omap3-overo-palo35-common.dtsi index 8df7ec35d1..a8020fb424 100644 --- a/dts/src/arm/omap3-overo-palo35-common.dtsi +++ b/dts/src/arm/omap3-overo-palo35-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = <BTN_1>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/dts/src/arm/omap3-overo-palo43-common.dtsi b/dts/src/arm/omap3-overo-palo43-common.dtsi index 0ea2c451c8..11965737e2 100644 --- a/dts/src/arm/omap3-overo-palo43-common.dtsi +++ b/dts/src/arm/omap3-overo-palo43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = <BTN_1>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/dts/src/arm/omap3-pandora-common.dtsi b/dts/src/arm/omap3-pandora-common.dtsi index dbc4dc721c..53e007abdc 100644 --- a/dts/src/arm/omap3-pandora-common.dtsi +++ b/dts/src/arm/omap3-pandora-common.dtsi @@ -18,7 +18,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; @@ -45,28 +45,28 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - led@1 { + led1 { label = "pandora::sd1"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ linux,default-trigger = "mmc0"; default-state = "off"; }; - led@2 { + led2 { label = "pandora::sd2"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ linux,default-trigger = "mmc1"; default-state = "off"; }; - led@3 { + led3 { label = "pandora::bluetooth"; gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@4 { + led4 { label = "pandora::wifi"; gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ linux,default-trigger = "mmc2"; diff --git a/dts/src/arm/omap3-sniper.dts b/dts/src/arm/omap3-sniper.dts index 78a1184cb3..bc4498e77b 100644 --- a/dts/src/arm/omap3-sniper.dts +++ b/dts/src/arm/omap3-sniper.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/omap3-tao3530.dtsi b/dts/src/arm/omap3-tao3530.dtsi index 644d3c8ea6..dc80886b53 100644 --- a/dts/src/arm/omap3-tao3530.dtsi +++ b/dts/src/arm/omap3-tao3530.dtsi @@ -26,7 +26,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap3-zoom3.dts b/dts/src/arm/omap3-zoom3.dts index c29b41dc7b..45e2ce0803 100644 --- a/dts/src/arm/omap3-zoom3.dts +++ b/dts/src/arm/omap3-zoom3.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/omap3.dtsi b/dts/src/arm/omap3.dtsi index 4c3c471d2a..353d818ce5 100644 --- a/dts/src/arm/omap3.dtsi +++ b/dts/src/arm/omap3.dtsi @@ -12,11 +12,11 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> -#include "skeleton.dtsi" - / { compatible = "ti,omap3430", "ti,omap3"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; @@ -78,7 +78,7 @@ * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ - ocp { + ocp@68000000 { compatible = "ti,omap3-l3-smx", "simple-bus"; reg = <0x68000000 0x10000>; interrupts = <9 10>; diff --git a/dts/src/arm/omap3430-sdp.dts b/dts/src/arm/omap3430-sdp.dts index a0dc8d8541..abd6921143 100644 --- a/dts/src/arm/omap3430-sdp.dts +++ b/dts/src/arm/omap3430-sdp.dts @@ -13,7 +13,7 @@ model = "TI OMAP3430 SDP"; compatible = "ti,omap3430-sdp", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/dts/src/arm/omap34xx.dtsi b/dts/src/arm/omap34xx.dtsi index e446562582..e41c52d3b1 100644 --- a/dts/src/arm/omap34xx.dtsi +++ b/dts/src/arm/omap34xx.dtsi @@ -28,7 +28,7 @@ }; }; - ocp { + ocp@68000000 { omap3_pmx_core2: pinmux@480025d8 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025d8 0x24>; diff --git a/dts/src/arm/omap36xx.dtsi b/dts/src/arm/omap36xx.dtsi index 8b79791530..718fa88407 100644 --- a/dts/src/arm/omap36xx.dtsi +++ b/dts/src/arm/omap36xx.dtsi @@ -30,7 +30,7 @@ }; }; - ocp { + ocp@68000000 { uart4: serial@49042000 { compatible = "ti,omap3-uart"; reg = <0x49042000 0x400>; diff --git a/dts/src/arm/omap4-duovero-parlor.dts b/dts/src/arm/omap4-duovero-parlor.dts index 6b39808b83..1b825128a7 100644 --- a/dts/src/arm/omap4-duovero-parlor.dts +++ b/dts/src/arm/omap4-duovero-parlor.dts @@ -32,7 +32,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - button0@121 { + button0 { label = "button0"; linux,code = <BTN_0>; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ diff --git a/dts/src/arm/omap4-duovero.dtsi b/dts/src/arm/omap4-duovero.dtsi index a90b582e4c..ec0bd9779e 100644 --- a/dts/src/arm/omap4-duovero.dtsi +++ b/dts/src/arm/omap4-duovero.dtsi @@ -12,7 +12,7 @@ model = "Gumstix Duovero"; compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/dts/src/arm/omap4-kc1.dts b/dts/src/arm/omap4-kc1.dts index 2251bd54e4..e3763ac757 100644 --- a/dts/src/arm/omap4-kc1.dts +++ b/dts/src/arm/omap4-kc1.dts @@ -13,7 +13,7 @@ model = "Amazon Kindle Fire (first generation)"; compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/dts/src/arm/omap4-panda-common.dtsi b/dts/src/arm/omap4-panda-common.dtsi index f8f13952cf..1673689e67 100644 --- a/dts/src/arm/omap4-panda-common.dtsi +++ b/dts/src/arm/omap4-panda-common.dtsi @@ -8,7 +8,7 @@ #include "elpida_ecb240abacn.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; @@ -446,6 +446,8 @@ pinctrl-names = "default"; pinctrl-0 = <&wl12xx_pins>; vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x10e>; non-removable; bus-width = <4>; cap-power-off-card; diff --git a/dts/src/arm/omap4-sdp.dts b/dts/src/arm/omap4-sdp.dts index 10d73a7840..d728ec9631 100644 --- a/dts/src/arm/omap4-sdp.dts +++ b/dts/src/arm/omap4-sdp.dts @@ -14,7 +14,7 @@ model = "TI OMAP4 SDP board"; compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/dts/src/arm/omap4-var-som-om44.dtsi b/dts/src/arm/omap4-var-som-om44.dtsi index 873cfc8726..758b6eb7ae 100644 --- a/dts/src/arm/omap4-var-som-om44.dtsi +++ b/dts/src/arm/omap4-var-som-om44.dtsi @@ -12,7 +12,7 @@ model = "Variscite VAR-SOM-OM44"; compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/dts/src/arm/omap4.dtsi b/dts/src/arm/omap4.dtsi index 3fdc51cd0f..0ced079b7a 100644 --- a/dts/src/arm/omap4.dtsi +++ b/dts/src/arm/omap4.dtsi @@ -10,11 +10,11 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/omap.h> -#include "skeleton.dtsi" - / { compatible = "ti,omap4430", "ti,omap4"; interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; diff --git a/dts/src/arm/omap5-board-common.dtsi b/dts/src/arm/omap5-board-common.dtsi index 5196113202..6365635fea 100644 --- a/dts/src/arm/omap5-board-common.dtsi +++ b/dts/src/arm/omap5-board-common.dtsi @@ -77,16 +77,6 @@ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ }; - leds { - compatible = "gpio-leds"; - led@1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - tpd12s015: encoder { compatible = "ti,tpd12s015"; @@ -332,7 +322,7 @@ wlcore_irq_pin: pinmux_wlcore_irq_pin { pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ + OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ >; }; }; @@ -355,15 +345,17 @@ non-removable; cap-power-off-card; pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlcore_irq_pin>; - interrupts-extended = <&gic GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x168>; + pinctrl-0 = <&mmc3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap5_pmx_core 0x16a>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wlcore_irq_pin>; interrupt-parent = <&gpio1>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ ref-clock-frequency = <26000000>; @@ -391,14 +383,23 @@ interrupt-controller; #interrupt-cells = <2>; ti,system-power-controller; + ti,mux-pad1 = <0xa1>; + ti,mux-pad2 = <0x1b>; pinctrl-names = "default"; pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + extcon_usb3: palmas_usb { compatible = "ti,palmas-usb-vid"; ti,enable-vbus-detection; ti,enable-id-detection; ti,wakeup; + id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; }; clk32kgaudio: palmas_clk32k@1 { diff --git a/dts/src/arm/omap5-cm-t54.dts b/dts/src/arm/omap5-cm-t54.dts index a9765605d5..b153f60493 100644 --- a/dts/src/arm/omap5-cm-t54.dts +++ b/dts/src/arm/omap5-cm-t54.dts @@ -11,9 +11,9 @@ model = "CompuLab CM-T54"; compatible = "compulab,omap5-cm-t54", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2048 MB */ + reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ }; aliases { @@ -72,7 +72,7 @@ leds { compatible = "gpio-leds"; - led@1 { + led1 { label = "Heartbeat"; gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/omap5-igep0050.dts b/dts/src/arm/omap5-igep0050.dts index f75ce02fb3..8fc1921805 100644 --- a/dts/src/arm/omap5-igep0050.dts +++ b/dts/src/arm/omap5-igep0050.dts @@ -7,15 +7,47 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "omap5-board-common.dtsi" / { model = "IGEPv5"; compatible = "isee,omap5-igep0050", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7f000000>; /* 2032 MB */ + reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "board:green:usr0"; + gpios = <&tca6416 1 0>; + default-state = "off"; + }; + led@2 { + label = "board:red:usr1"; + gpios = <&tca6416 2 0>; + default-state = "off"; + }; + led@3 { + label = "board:blue:usr1"; + gpios = <&tca6416 3 0>; + default-state = "off"; + }; }; }; @@ -58,6 +90,12 @@ OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ >; }; + + power_button_pin: pinctrl_power_button_pin { + pinctrl-single,pins = < + OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ + >; + }; }; &tpd12s015 { diff --git a/dts/src/arm/omap5-uevm.dts b/dts/src/arm/omap5-uevm.dts index a51e60518e..53d31a87b4 100644 --- a/dts/src/arm/omap5-uevm.dts +++ b/dts/src/arm/omap5-uevm.dts @@ -13,9 +13,19 @@ model = "TI OMAP5 uEVM board"; compatible = "ti,omap5-uevm", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2032 MB */ + reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "omap5:blue:usr1"; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; }; }; @@ -61,3 +71,7 @@ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ >; }; + +&wlcore { + compatible = "ti,wl1837"; +}; diff --git a/dts/src/arm/omap5.dtsi b/dts/src/arm/omap5.dtsi index 84c10195e7..25262118ec 100644 --- a/dts/src/arm/omap5.dtsi +++ b/dts/src/arm/omap5.dtsi @@ -11,11 +11,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/omap.h> -#include "skeleton.dtsi" - / { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "ti,omap5"; interrupt-parent = <&wakeupgen>; @@ -92,10 +90,10 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>, - <0x48214000 0x2000>, - <0x48216000 0x2000>; + reg = <0 0x48211000 0 0x1000>, + <0 0x48212000 0 0x1000>, + <0 0x48214000 0 0x2000>, + <0 0x48216000 0 0x2000>; interrupt-parent = <&gic>; }; @@ -103,7 +101,7 @@ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; + reg = <0 0x48281000 0 0x1000>; interrupt-parent = <&gic>; }; @@ -131,11 +129,11 @@ compatible = "ti,omap5-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0xc0000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>, - <0x45000000 0x4000>; + reg = <0 0x44000000 0 0x2000>, + <0 0x44800000 0 0x3000>, + <0 0x45000000 0 0x4000>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -865,7 +863,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges; - dwc3@4a030000 { + dwc3: dwc3@4a030000 { compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm/orion5x-mv88f5181.dtsi b/dts/src/arm/orion5x-mv88f5181.dtsi new file mode 100644 index 0000000000..f667012b26 --- /dev/null +++ b/dts/src/arm/orion5x-mv88f5181.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; + + internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5181-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5181-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; + +&pinctrl { + pmx_ge: pmx-ge { + marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; + marvell,function = "ge"; + }; +}; + +ð { + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm/orion5x-netgear-wnr854t.dts b/dts/src/arm/orion5x-netgear-wnr854t.dts new file mode 100644 index 0000000000..9f6ae4e1de --- /dev/null +++ b/dts/src/arm/orion5x-netgear-wnr854t.dts @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "orion5x-mv88f5181.dtsi" + +/ { + model = "Netgear WNR854-t"; + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", + "marvell,orion5x"; + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x2000000>; /* 32 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_reset_button>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; + pinctrl-names = "default"; + + led@0 { + label = "wnr854t:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "wnr854t:blink:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "wnr854t:green:wan"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "rootfs"; + reg = <0x100000 0x660000>; + }; + + partition@760000 { + label = "uboot_env"; + reg = <0x760000 0x20000>; + }; + + partition@780000 { + label = "uboot"; + reg = <0x780000 0x80000>; + read-only; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + phy-handle = <&lan3phy>; + }; + + port@1 { + reg = <1>; + label = "lan4"; + phy-handle = <&lan4phy>; + }; + + port@2 { + reg = <2>; + label = "wan"; + phy-handle = <&wanphy>; + }; + + port@3 { + reg = <3>; + label = "cpu"; + ethernet = <ðport>; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-handle = <&lan1phy>; + }; + + port@7 { + reg = <7>; + label = "lan2"; + phy-handle = <&lan2phy>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + lan3phy: ethernet-phy@0 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan4phy: ethernet-phy@1 { + /* Marvell 88E1121R (port 2) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + wanphy: ethernet-phy@2 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan1phy: ethernet-phy@5 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <5>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan2phy: ethernet-phy@7 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + }; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + /* Hardwired to DSA switch */ + speed = <1000>; + duplex = <1>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_gpios>; + pinctrl-names = "default"; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_led_blink: pmx-power-led-blink { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_wan_led: pmx-wan-led { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ + status = "okay"; +}; diff --git a/dts/src/arm/orion5x.dtsi b/dts/src/arm/orion5x.dtsi index e1b6d2a2ac..fbccfbbab2 100644 --- a/dts/src/arm/orion5x.dtsi +++ b/dts/src/arm/orion5x.dtsi @@ -144,9 +144,10 @@ wdt: wdt@20300 { compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>; + reg = <0x20300 0x28>, <0x20108 0x4>; interrupt-parent = <&bridge_intc>; interrupts = <3>; + clocks = <&core_clk 0>; status = "okay"; }; diff --git a/dts/src/arm/qcom-apq8060-dragonboard.dts b/dts/src/arm/qcom-apq8060-dragonboard.dts index 0abc93e5bb..6c0038398e 100644 --- a/dts/src/arm/qcom-apq8060-dragonboard.dts +++ b/dts/src/arm/qcom-apq8060-dragonboard.dts @@ -239,6 +239,45 @@ }; }; }; + + led@48 { + /* + * The keypad LED @0x48 is routed to + * the sensor board where it is + * connected to an infrared LED + * SFH4650 (60mW, @850nm) next to the + * ambient light and proximity sensor + * Capella Microsystems CM3605. + */ + compatible = "qcom,pm8058-keypad-led"; + reg = <0x48>; + label = "pm8058:infrared:proximitysensor"; + default-state = "off"; + }; + led@131 { + compatible = "qcom,pm8058-led"; + reg = <0x131>; + label = "pm8058:red"; + default-state = "off"; + }; + led@132 { + /* + * This is actually green too on my + * board, but documented as yellow. + */ + compatible = "qcom,pm8058-led"; + reg = <0x132>; + label = "pm8058:yellow"; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + led@133 { + compatible = "qcom,pm8058-led"; + reg = <0x133>; + label = "pm8058:green"; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; }; }; diff --git a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts index 7b05f072bf..b72e095064 100644 --- a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts +++ b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts @@ -253,6 +253,7 @@ vddcx-supply = <&pm8921_s3>; v3p3-supply = <&pm8921_l3>; v1p8-supply = <&pm8921_l4>; + dr_mode = "otg"; }; gadget@12500000 { @@ -272,5 +273,19 @@ vqmmc-supply = <&pm8921_s4>; }; }; + + imem@2a03f000 { + compatible = "syscon", "simple-mfd"; + reg = <0x2a03f000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; }; }; diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi index 74a9b6c394..1dbe697b2e 100644 --- a/dts/src/arm/qcom-apq8064.dtsi +++ b/dts/src/arm/qcom-apq8064.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/reset/qcom,gcc-msm8960.h> #include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/soc/qcom,gsbi.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Qualcomm APQ8064"; @@ -86,6 +87,92 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 7>; + coefficients = <1199 0>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 8>; + coefficients = <1132 0>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 9>; + coefficients = <1199 0>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 10>; + coefficients = <1132 0>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; @@ -559,22 +646,50 @@ compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; reg = <0x150>; - interrupts = <192 1>, <193 1>, <194 1>, - <195 1>, <196 1>, <197 1>, - <198 1>, <199 1>, <200 1>, - <201 1>, <202 1>, <203 1>, - <204 1>, <205 1>, <206 1>, - <207 1>, <208 1>, <209 1>, - <210 1>, <211 1>, <212 1>, - <213 1>, <214 1>, <215 1>, - <216 1>, <217 1>, <218 1>, - <219 1>, <220 1>, <221 1>, - <222 1>, <223 1>, <224 1>, - <225 1>, <226 1>, <227 1>, - <228 1>, <229 1>, <230 1>, - <231 1>, <232 1>, <233 1>, - <234 1>, <235 1>; - + interrupts = <192 IRQ_TYPE_NONE>, + <193 IRQ_TYPE_NONE>, + <194 IRQ_TYPE_NONE>, + <195 IRQ_TYPE_NONE>, + <196 IRQ_TYPE_NONE>, + <197 IRQ_TYPE_NONE>, + <198 IRQ_TYPE_NONE>, + <199 IRQ_TYPE_NONE>, + <200 IRQ_TYPE_NONE>, + <201 IRQ_TYPE_NONE>, + <202 IRQ_TYPE_NONE>, + <203 IRQ_TYPE_NONE>, + <204 IRQ_TYPE_NONE>, + <205 IRQ_TYPE_NONE>, + <206 IRQ_TYPE_NONE>, + <207 IRQ_TYPE_NONE>, + <208 IRQ_TYPE_NONE>, + <209 IRQ_TYPE_NONE>, + <210 IRQ_TYPE_NONE>, + <211 IRQ_TYPE_NONE>, + <212 IRQ_TYPE_NONE>, + <213 IRQ_TYPE_NONE>, + <214 IRQ_TYPE_NONE>, + <215 IRQ_TYPE_NONE>, + <216 IRQ_TYPE_NONE>, + <217 IRQ_TYPE_NONE>, + <218 IRQ_TYPE_NONE>, + <219 IRQ_TYPE_NONE>, + <220 IRQ_TYPE_NONE>, + <221 IRQ_TYPE_NONE>, + <222 IRQ_TYPE_NONE>, + <223 IRQ_TYPE_NONE>, + <224 IRQ_TYPE_NONE>, + <225 IRQ_TYPE_NONE>, + <226 IRQ_TYPE_NONE>, + <227 IRQ_TYPE_NONE>, + <228 IRQ_TYPE_NONE>, + <229 IRQ_TYPE_NONE>, + <230 IRQ_TYPE_NONE>, + <231 IRQ_TYPE_NONE>, + <232 IRQ_TYPE_NONE>, + <233 IRQ_TYPE_NONE>, + <234 IRQ_TYPE_NONE>, + <235 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; @@ -587,9 +702,18 @@ gpio-controller; #gpio-cells = <2>; interrupts = - <128 1>, <129 1>, <130 1>, <131 1>, - <132 1>, <133 1>, <134 1>, <135 1>, - <136 1>, <137 1>, <138 1>, <139 1>; + <128 IRQ_TYPE_NONE>, + <129 IRQ_TYPE_NONE>, + <130 IRQ_TYPE_NONE>, + <131 IRQ_TYPE_NONE>, + <132 IRQ_TYPE_NONE>, + <133 IRQ_TYPE_NONE>, + <134 IRQ_TYPE_NONE>, + <135 IRQ_TYPE_NONE>, + <136 IRQ_TYPE_NONE>, + <137 IRQ_TYPE_NONE>, + <138 IRQ_TYPE_NONE>, + <139 IRQ_TYPE_NONE>; }; rtc@11d { @@ -611,11 +735,28 @@ }; }; + qfprom: qfprom@700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib { + reg = <0x414 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064"; reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #reset-cells = <1>; + #thermal-sensor-cells = <1>; }; lcc: clock-controller@28000000 { @@ -712,7 +853,6 @@ reg = <0x12500000 0x400>; interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; status = "disabled"; - dr_mode = "host"; clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; diff --git a/dts/src/arm/qcom-apq8084.dtsi b/dts/src/arm/qcom-apq8084.dtsi index 7c2df062a0..39eb7a4ed1 100644 --- a/dts/src/arm/qcom-apq8084.dtsi +++ b/dts/src/arm/qcom-apq8084.dtsi @@ -94,6 +94,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -150,6 +232,27 @@ reg = <0xf9011000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/qcom-ipq8064-ap148.dts b/dts/src/arm/qcom-ipq8064-ap148.dts index d501382493..348503d1a1 100644 --- a/dts/src/arm/qcom-ipq8064-ap148.dts +++ b/dts/src/arm/qcom-ipq8064-ap148.dts @@ -95,6 +95,7 @@ }; sata@29000000 { + ports-implemented = <0x1>; status = "ok"; }; }; diff --git a/dts/src/arm/qcom-msm8660.dtsi b/dts/src/arm/qcom-msm8660.dtsi index acbe71febe..8c65e0d825 100644 --- a/dts/src/arm/qcom-msm8660.dtsi +++ b/dts/src/arm/qcom-msm8660.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8660.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -159,21 +160,50 @@ "qcom,ssbi-gpio"; reg = <0x150>; interrupt-parent = <&pmicintc>; - interrupts = <192 1>, <193 1>, <194 1>, - <195 1>, <196 1>, <197 1>, - <198 1>, <199 1>, <200 1>, - <201 1>, <202 1>, <203 1>, - <204 1>, <205 1>, <206 1>, - <207 1>, <208 1>, <209 1>, - <210 1>, <211 1>, <212 1>, - <213 1>, <214 1>, <215 1>, - <216 1>, <217 1>, <218 1>, - <219 1>, <220 1>, <221 1>, - <222 1>, <223 1>, <224 1>, - <225 1>, <226 1>, <227 1>, - <228 1>, <229 1>, <230 1>, - <231 1>, <232 1>, <233 1>, - <234 1>, <235 1>; + interrupts = <192 IRQ_TYPE_NONE>, + <193 IRQ_TYPE_NONE>, + <194 IRQ_TYPE_NONE>, + <195 IRQ_TYPE_NONE>, + <196 IRQ_TYPE_NONE>, + <197 IRQ_TYPE_NONE>, + <198 IRQ_TYPE_NONE>, + <199 IRQ_TYPE_NONE>, + <200 IRQ_TYPE_NONE>, + <201 IRQ_TYPE_NONE>, + <202 IRQ_TYPE_NONE>, + <203 IRQ_TYPE_NONE>, + <204 IRQ_TYPE_NONE>, + <205 IRQ_TYPE_NONE>, + <206 IRQ_TYPE_NONE>, + <207 IRQ_TYPE_NONE>, + <208 IRQ_TYPE_NONE>, + <209 IRQ_TYPE_NONE>, + <210 IRQ_TYPE_NONE>, + <211 IRQ_TYPE_NONE>, + <212 IRQ_TYPE_NONE>, + <213 IRQ_TYPE_NONE>, + <214 IRQ_TYPE_NONE>, + <215 IRQ_TYPE_NONE>, + <216 IRQ_TYPE_NONE>, + <217 IRQ_TYPE_NONE>, + <218 IRQ_TYPE_NONE>, + <219 IRQ_TYPE_NONE>, + <220 IRQ_TYPE_NONE>, + <221 IRQ_TYPE_NONE>, + <222 IRQ_TYPE_NONE>, + <223 IRQ_TYPE_NONE>, + <224 IRQ_TYPE_NONE>, + <225 IRQ_TYPE_NONE>, + <226 IRQ_TYPE_NONE>, + <227 IRQ_TYPE_NONE>, + <228 IRQ_TYPE_NONE>, + <229 IRQ_TYPE_NONE>, + <230 IRQ_TYPE_NONE>, + <231 IRQ_TYPE_NONE>, + <232 IRQ_TYPE_NONE>, + <233 IRQ_TYPE_NONE>, + <234 IRQ_TYPE_NONE>, + <235 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; @@ -187,9 +217,18 @@ #gpio-cells = <2>; interrupt-parent = <&pmicintc>; interrupts = - <128 1>, <129 1>, <130 1>, <131 1>, - <132 1>, <133 1>, <134 1>, <135 1>, - <136 1>, <137 1>, <138 1>, <139 1>; + <128 IRQ_TYPE_NONE>, + <129 IRQ_TYPE_NONE>, + <130 IRQ_TYPE_NONE>, + <131 IRQ_TYPE_NONE>, + <132 IRQ_TYPE_NONE>, + <133 IRQ_TYPE_NONE>, + <134 IRQ_TYPE_NONE>, + <135 IRQ_TYPE_NONE>, + <136 IRQ_TYPE_NONE>, + <137 IRQ_TYPE_NONE>, + <138 IRQ_TYPE_NONE>, + <139 IRQ_TYPE_NONE>; }; pwrkey@1c { diff --git a/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts new file mode 100644 index 0000000000..c0fb4a698c --- /dev/null +++ b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -0,0 +1,262 @@ +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "LGE MSM 8974 HAMMERHEAD"; + compatible = "lge,hammerhead", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + smd { + rpm { + rpm_requests { + pm8841-regulators { + s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; +}; + +&soc { + serial@f991d000 { + status = "ok"; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + }; + }; +}; diff --git a/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts b/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts index 3fb4dada6b..e7c1577d56 100644 --- a/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts +++ b/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts @@ -257,23 +257,6 @@ }; }; }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; }; &soc { @@ -311,6 +294,45 @@ pinctrl-0 = <&blsp1_uart2_pin_a>; }; + i2c@f9924000 { + status = "ok"; + + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + syna,sensor-type = <1>; + }; + }; + }; + pinctrl@fd510000 { blsp1_uart2_pin_a: blsp1-uart2-pin-active { rx { @@ -330,6 +352,16 @@ }; }; + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + sdhc1_pin_a: sdhc1-pin-active { clk { pins = "sdc1_clk"; @@ -366,6 +398,16 @@ }; }; + ts_int_pin: touch-int { + pin { + pins = "gpio61"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; }; dma-controller@f9944000 { @@ -387,11 +429,6 @@ }; gpios@c000 { - boost_bypass_n_pin: boost-bypass { - pins = "gpio21"; - function = "normal"; - }; - gpio_keys_pin_a: gpio-keys-active { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "normal"; diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi index 561d4d1367..d2109475bd 100644 --- a/dts/src/arm/qcom-msm8974.dtsi +++ b/dts/src/arm/qcom-msm8974.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> +#include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi" / { @@ -131,6 +132,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -287,6 +370,27 @@ reg = <0xf9011000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -430,6 +534,15 @@ reg = <0xfc428000 0x4000>; }; + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = <0 107 0x0>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -615,4 +728,30 @@ }; }; }; + + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&boost_bypass_n_pin>; + }; + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; }; diff --git a/dts/src/arm/qcom-pm8941.dtsi b/dts/src/arm/qcom-pm8941.dtsi index d95edb6f62..f8eb5e31c9 100644 --- a/dts/src/arm/qcom-pm8941.dtsi +++ b/dts/src/arm/qcom-pm8941.dtsi @@ -88,6 +88,11 @@ <0 0xe1 0 IRQ_TYPE_NONE>, <0 0xe2 0 IRQ_TYPE_NONE>, <0 0xe3 0 IRQ_TYPE_NONE>; + + boost_bypass_n_pin: boost-bypass { + pins = "gpio21"; + function = "normal"; + }; }; pm8941_mpps: mpps@a000 { diff --git a/dts/src/arm/r7s72100-rskrza1.dts b/dts/src/arm/r7s72100-rskrza1.dts new file mode 100644 index 0000000000..e5dea5bb40 --- /dev/null +++ b/dts/src/arm/r7s72100-rskrza1.dts @@ -0,0 +1,61 @@ +/* + * Device Tree Source for the RZ/A1H RSK board + * + * Copyright (C) 2016 Renesas Electronics + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r7s72100.dtsi" + +/ { + model = "RSKRZA1"; + compatible = "renesas,rskrza1", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x02000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&mtu2 { + status = "okay"; +}; + +ðer { + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&scif2 { + status = "okay"; +}; diff --git a/dts/src/arm/r7s72100.dtsi b/dts/src/arm/r7s72100.dtsi index e8e2a5d719..fb9ef9ca12 100644 --- a/dts/src/arm/r7s72100.dtsi +++ b/dts/src/arm/r7s72100.dtsi @@ -108,6 +108,15 @@ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; }; + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&p0_clk>; + clock-indices = <R7S72100_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@fcfe0438 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -419,4 +428,17 @@ power-domains = <&cpg_clocks>; status = "disabled"; }; + + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/dts/src/arm/r8a7790.dtsi b/dts/src/arm/r8a7790.dtsi index d18558f211..351fcc2f87 100644 --- a/dts/src/arm/r8a7790.dtsi +++ b/dts/src/arm/r8a7790.dtsi @@ -944,11 +944,6 @@ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe928000 { @@ -957,12 +952,6 @@ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lut; - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <3>; - renesas,#wpf = <4>; }; vsp1@fe930000 { @@ -971,12 +960,6 @@ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe938000 { @@ -985,12 +968,6 @@ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; du: display@feb00000 { diff --git a/dts/src/arm/r8a7791.dtsi b/dts/src/arm/r8a7791.dtsi index 8f0086bbd9..162b55c665 100644 --- a/dts/src/arm/r8a7791.dtsi +++ b/dts/src/arm/r8a7791.dtsi @@ -983,12 +983,6 @@ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lut; - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <3>; - renesas,#wpf = <4>; }; vsp1@fe930000 { @@ -997,12 +991,6 @@ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe938000 { @@ -1011,12 +999,6 @@ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; du: display@feb00000 { diff --git a/dts/src/arm/r8a7792-blanche.dts b/dts/src/arm/r8a7792-blanche.dts index e7b40f0e7d..f3ea43b7b7 100644 --- a/dts/src/arm/r8a7792-blanche.dts +++ b/dts/src/arm/r8a7792-blanche.dts @@ -11,6 +11,8 @@ /dts-v1/; #include "r8a7792.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Blanche"; @@ -50,6 +52,139 @@ reg-io-width = <4>; vddvario-supply = <&d3_3v>; vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + x1_clk: x1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x2_clk: x2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + key-2 { + linux,code = <KEY_2>; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + key-3 { + linux,code = <KEY_3>; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + key-4 { + linux,code = <KEY_4>; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + key-a { + linux,code = <KEY_A>; + label = "SW24"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = <KEY_B>; + label = "SW25"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led17 { + gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; + }; + led18 { + gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; + }; + led19 { + gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; + }; + led20 { + gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -57,10 +192,139 @@ clock-frequency = <20000000>; }; +&can_clk { + clock-frequency = <48000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; + + can0_pins: can0 { + groups = "can0_data", "can_clk"; + function = "can0"; + }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins &du1_pins>; + pinctrl-names = "default"; + + clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, + <&x1_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; diff --git a/dts/src/arm/r8a7792-wheat.dts b/dts/src/arm/r8a7792-wheat.dts new file mode 100644 index 0000000000..6dbb94114a --- /dev/null +++ b/dts/src/arm/r8a7792-wheat.dts @@ -0,0 +1,199 @@ +/* + * Device Tree Source for the Wheat board + * + * Copyright (C) 2016 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7792.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Wheat"; + compatible = "renesas,wheat", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0 0x18000000 0 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + smsc,save-mac-address; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; + + keyboard { + compatible = "gpio-keys"; + + key-a { + linux,code = <KEY_A>; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = <KEY_B>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; diff --git a/dts/src/arm/r8a7792.dtsi b/dts/src/arm/r8a7792.dtsi index 3fd61d7ab9..713141d38b 100644 --- a/dts/src/arm/r8a7792.dtsi +++ b/dts/src/arm/r8a7792.dtsi @@ -18,6 +18,22 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + spi0 = &qspi; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; + vin4 = &vin4; + vin5 = &vin5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -108,6 +124,179 @@ #power-domain-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio6: gpio@e6055100 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055100 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio7: gpio@e6055200 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055200 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio8: gpio@e6055300 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055300 0 0x50>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio9: gpio@e6055400 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio10: gpio@e6055500 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055500 0 0x50>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio11: gpio@e6055600 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055600 0 0x50>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 352 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; @@ -262,6 +451,18 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7792", "renesas,rcar-gen2-jpu"; @@ -271,6 +472,242 @@ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6520000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6528000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7792", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7792_CLK_DU0>, + <&mstp7_clks R8A7792_CLK_DU1>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_CAN0>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7792_CLK_CAN1>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", @@ -291,6 +728,13 @@ clock-div = <2>; clock-mult = <1>; }; + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -298,6 +742,13 @@ clock-div = <6>; clock-mult = <1>; }; + hp_clk: hp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -319,16 +770,42 @@ clock-div = <8>; clock-mult = <1>; }; + sd_clk: sd { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + rcan_clk: rcan { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <49>; + clock-mult = <1>; + }; + zg_clk: zg { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>; + clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - clock-indices = <R8A7792_CLK_JPU>; - clock-output-names = "jpu"; + clock-indices = < + R8A7792_CLK_JPU + R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 + R8A7792_CLK_VSP1_SY + >; + clock-output-names = "jpu", "vsp1du1", "vsp1du0", + "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7792-mstp-clocks", @@ -341,6 +818,15 @@ >; clock-output-names = "sys-dmac1", "sys-dmac0"; }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&sd_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7792_CLK_SDHI0>; + clock-output-names = "sdhi0"; + }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -355,15 +841,65 @@ "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>; + <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 + R8A7792_CLK_DU1 R8A7792_CLK_DU0 >; clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0"; + "scif2", "scif1", "scif0", + "du1", "du0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&zg_clk>, <&zg_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 + R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 + R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 + R8A7792_CLK_ETHERAVB + >; + clock-output-names = "vin5", "vin4", "vin3", "vin2", + "vin1", "vin0", "etheravb"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, + <&cpg_clocks R8A7792_CLK_QSPI>, + <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 + R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 + R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 + R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 + R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 + R8A7792_CLK_QSPI_MOD + R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 + R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 + R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 + R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 + >; + clock-output-names = + "gpio7", "gpio6", "gpio5", "gpio4", + "gpio3", "gpio2", "gpio1", "gpio0", + "gpio11", "gpio10", "can1", "can0", + "qspi_mod", "gpio9", "gpio8", + "i2c5", "i2c4", "i2c3", "i2c2", + "i2c1", "i2c0"; }; }; @@ -382,4 +918,12 @@ /* This value must be overridden by the board. */ clock-frequency = <0>; }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; diff --git a/dts/src/arm/r8a7794-alt.dts b/dts/src/arm/r8a7794-alt.dts index 1ad37d431a..8d1b35afaf 100644 --- a/dts/src/arm/r8a7794-alt.dts +++ b/dts/src/arm/r8a7794-alt.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r8a7794.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Alt"; @@ -29,6 +30,63 @@ reg = <0 0x40000000 0 0x40000000>; }; + d3_3v: regulator-d3-3v { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; @@ -140,6 +198,21 @@ groups = "vin0_data8", "vin0_clk"; function = "vin0"; }; + + mmcif0_pins: mmcif0 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + }; }; &cmt0 { @@ -169,6 +242,39 @@ }; }; +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; diff --git a/dts/src/arm/r8a7794-silk.dts b/dts/src/arm/r8a7794-silk.dts index cf24f45fff..cf880ac06f 100644 --- a/dts/src/arm/r8a7794-silk.dts +++ b/dts/src/arm/r8a7794-silk.dts @@ -10,6 +10,17 @@ * kind, whether express or implied. */ +/* + * SSI-AK4643 + * + * SW1: 2-1: AK4643 + * 2-3: ADV7511 + * + * This command is required before playback/capture: + * + * amixer set "LINEOUT Mixer DACL" on + */ + /dts-v1/; #include "r8a7794.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -119,6 +130,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + x9_clk: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&soundcodec>; + simple-audio-card,frame-master = <&soundcodec>; + + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + soundcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&x9_clk>; + }; + }; }; &extal_clk { @@ -193,6 +227,16 @@ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; function = "du1"; }; + + ssi_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + audio_clk_pins: audio_clk { + groups = "audio_clkc"; + function = "audio_clk"; + }; }; &scif2 { @@ -230,6 +274,12 @@ status = "okay"; clock-frequency = <400000>; + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; @@ -392,3 +442,23 @@ }; }; }; + +&rcar_sound { + pinctrl-0 = <&ssi_pins &audio_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi index 685f986cf9..9365580a19 100644 --- a/dts/src/arm/r8a7794.dtsi +++ b/dts/src/arm/r8a7794.dtsi @@ -296,6 +296,34 @@ dma-channels = <15>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", + "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -697,7 +725,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, @@ -866,6 +894,22 @@ }; }; + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7794"; reg = <0 0xfeb00000 0 0x40000>; @@ -952,6 +996,27 @@ clock-frequency = <0>; }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7794-cpg-clocks", @@ -1183,6 +1248,15 @@ clock-indices = <R8A7794_CLK_IRQC>; clock-output-names = "irqc"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = <R8A7794_CLK_AUDIO_DMAC0 + R8A7794_CLK_PWM>; + clock-output-names = "audmac0", "pwm"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; @@ -1237,6 +1311,58 @@ "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7794-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>; + #clock-cells = <1>; + clock-indices = <R8A7794_CLK_SSI_ALL + R8A7794_CLK_SSI9 R8A7794_CLK_SSI8 + R8A7794_CLK_SSI7 R8A7794_CLK_SSI6 + R8A7794_CLK_SSI5 R8A7794_CLK_SSI4 + R8A7794_CLK_SSI3 R8A7794_CLK_SSI2 + R8A7794_CLK_SSI1 R8A7794_CLK_SSI0 + R8A7794_CLK_SCU_ALL + R8A7794_CLK_SCU_DVC1 + R8A7794_CLK_SCU_DVC0 + R8A7794_CLK_SCU_CTU1_MIX1 + R8A7794_CLK_SCU_CTU0_MIX0 + R8A7794_CLK_SCU_SRC6 + R8A7794_CLK_SCU_SRC5 + R8A7794_CLK_SCU_SRC4 + R8A7794_CLK_SCU_SRC3 + R8A7794_CLK_SCU_SRC2 + R8A7794_CLK_SCU_SRC1>; + clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", + "ssi6", "ssi5", "ssi4", "ssi3", + "ssi2", "ssi1", "ssi0", + "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src6", "scu-src5", "scu-src4", + "scu-src3", "scu-src2", "scu-src1"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; @@ -1306,4 +1432,185 @@ #iommu-cells = <1>; status = "disabled"; }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI9>, + <&mstp10_clks R8A7794_CLK_SSI8>, + <&mstp10_clks R8A7794_CLK_SSI7>, + <&mstp10_clks R8A7794_CLK_SSI6>, + <&mstp10_clks R8A7794_CLK_SSI5>, + <&mstp10_clks R8A7794_CLK_SSI4>, + <&mstp10_clks R8A7794_CLK_SSI3>, + <&mstp10_clks R8A7794_CLK_SSI2>, + <&mstp10_clks R8A7794_CLK_SSI1>, + <&mstp10_clks R8A7794_CLK_SSI0>, + <&mstp10_clks R8A7794_CLK_SCU_SRC6>, + <&mstp10_clks R8A7794_CLK_SCU_SRC5>, + <&mstp10_clks R8A7794_CLK_SCU_SRC4>, + <&mstp10_clks R8A7794_CLK_SCU_SRC3>, + <&mstp10_clks R8A7794_CLK_SCU_SRC2>, + <&mstp10_clks R8A7794_CLK_SCU_SRC1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_DVC0>, + <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", "src.2", + "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&cpg_clocks>; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + + rcar_sound,src { + src@0 { + status = "disabled"; + }; + src1: src@1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi@0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; }; diff --git a/dts/src/arm/rk3036.dtsi b/dts/src/arm/rk3036.dtsi index 843d2be2e4..a935523a1e 100644 --- a/dts/src/arm/rk3036.dtsi +++ b/dts/src/arm/rk3036.dtsi @@ -43,6 +43,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3036-cru.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> #include "skeleton.dtsi" / { @@ -313,8 +314,17 @@ }; grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon"; + compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x1d8>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; }; acodec: acodec-ana@20030000 { diff --git a/dts/src/arm/rk3288-evb-act8846.dts b/dts/src/arm/rk3288-evb-act8846.dts index 452ca2441e..041dd5d2d1 100644 --- a/dts/src/arm/rk3288-evb-act8846.dts +++ b/dts/src/arm/rk3288-evb-act8846.dts @@ -206,6 +206,10 @@ }; }; +&panel { + power-supply = <&vcc_lcd>; +}; + &pinctrl { lcd { lcd_en: lcd-en { diff --git a/dts/src/arm/rk3288-evb-rk808.dts b/dts/src/arm/rk3288-evb-rk808.dts index 736b08b0bf..44ebc6e59b 100644 --- a/dts/src/arm/rk3288-evb-rk808.dts +++ b/dts/src/arm/rk3288-evb-rk808.dts @@ -233,3 +233,7 @@ }; }; }; + +&panel { + power-supply = <&vcc_lcd>; +}; diff --git a/dts/src/arm/rk3288-evb.dtsi b/dts/src/arm/rk3288-evb.dtsi index 963365d122..d59208b5eb 100644 --- a/dts/src/arm/rk3288-evb.dtsi +++ b/dts/src/arm/rk3288-evb.dtsi @@ -48,7 +48,7 @@ reg = <0x0 0x80000000>; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; brightness-levels = < 0 1 2 3 4 5 6 7 @@ -97,6 +97,21 @@ #clock-cells = <0>; }; + panel: panel { + compatible ="lg,lp079qx1-sp0v", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lcd_cs>; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -170,6 +185,28 @@ cpu0-supply = <&vdd_cpu>; }; +&edp { + force-hpd; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -280,6 +317,12 @@ }; }; + lcd { + lcd_cs: lcd-cs { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/dts/src/arm/rk3288-fennec.dts b/dts/src/arm/rk3288-fennec.dts new file mode 100644 index 0000000000..2e3c34135e --- /dev/null +++ b/dts/src/arm/rk3288-fennec.dts @@ -0,0 +1,382 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3288.dtsi" + +/ { + model = "Rockchip RK3288 Fennec Board"; + compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; + + memory { + reg = <0x0 0x80000000>; + device_type = "memory"; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usbphy { + host_drv: host-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&host_drv>; + vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usb_hsic { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/dts/src/arm/rk3288-firefly-reload-core.dtsi b/dts/src/arm/rk3288-firefly-reload-core.dtsi new file mode 100644 index 0000000000..ec418c99de --- /dev/null +++ b/dts/src/arm/rk3288-firefly-reload-core.dtsi @@ -0,0 +1,310 @@ +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li <ayaka@soulik.info> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/input/input.h> +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_lan: REG9 { + regulator-name = "vcca_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vccio_wl: vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vccio_wl>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/dts/src/arm/rk3288-firefly-reload.dts b/dts/src/arm/rk3288-firefly-reload.dts new file mode 100644 index 0000000000..751bee8112 --- /dev/null +++ b/dts/src/arm/rk3288-firefly-reload.dts @@ -0,0 +1,403 @@ +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li <ayaka@soulik.info> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-firefly-reload-core.dtsi" + +/ { + model = "Firefly-RK3288-reload"; + compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + + gpio-keys { + compatible = "gpio-keys"; + + power { + wakeup-source; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <KEY_POWER>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; + label = "firefly:blue:power"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led>; + panic-indicator; + }; + + work { + gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; + label = "firefly:blue:user"; + linux,default-trigger = "rc-feedback"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_5v: vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + dovdd_1v8: dovdd-1v8-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "dovdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + af_28: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "af_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + dvdd_1v2: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pwr>; + regulator-name = "dvdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_io>; + }; + + vbat_wl: wifi-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; +}; + +&i2c0 { + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; +}; + +&i2c2 { + status = "okay"; + + codec: es8328@10 { + compatible = "everest,es8328"; + DVDD-supply = <&vcca_33>; + AVDD-supply = <&vcca_33>; + PVDD-supply = <&vcca_33>; + HPVDD-supply = <&vcca_33>; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + clock-names = "i2s_hclk", "i2s_clk"; + reg = <0x10>; + }; +}; + +&i2s { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + vmmc-supply = <&vbat_wl>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&usbhub_rst>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_pwr: cif-pwr { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led: power-led { + rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { + rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/src/arm/rk3288-popmetal.dts b/dts/src/arm/rk3288-popmetal.dts index dda8d259bb..56dd377d56 100644 --- a/dts/src/arm/rk3288-popmetal.dts +++ b/dts/src/arm/rk3288-popmetal.dts @@ -387,12 +387,16 @@ interrupts = <1 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&comp_int>; + vdd-supply = <&vcc_io>; + vid-supply = <&vcc_io>; }; - l3g4200d: l3g4200d@68 { + l3g4200d: l3g4200d@69 { compatible = "st,l3g4200d-gyro"; st,drdy-int-pin = <2>; - reg = <0x6b>; + reg = <0x69>; + vdd-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; }; mma8452: mma8452@1d { @@ -525,3 +529,7 @@ &usbphy { status = "okay"; }; + +&usb_otg { + status = "okay"; +}; diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index 91c4b3c7a8..17ec2e2d7a 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/power/rk3288-power.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> #include "skeleton.dtsi" / { @@ -793,6 +794,15 @@ clocks = <&cru ACLK_GPU>; }; }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x94>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; }; sgrf: syscon@ff740000 { @@ -834,6 +844,37 @@ compatible = "rockchip,rk3288-io-voltage-domain"; status = "disabled"; }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; }; wdt: watchdog@ff800000 { @@ -1087,38 +1128,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; diff --git a/dts/src/arm/rk3xxx.dtsi b/dts/src/arm/rk3xxx.dtsi index e2cd683b4e..e15beb3c67 100644 --- a/dts/src/arm/rk3xxx.dtsi +++ b/dts/src/arm/rk3xxx.dtsi @@ -43,6 +43,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> #include "skeleton.dtsi" / { @@ -246,8 +247,17 @@ }; pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; reg = <0x20004000 0x100>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; }; grf: grf@20008000 { diff --git a/dts/src/arm/s3c2416-pinctrl.dtsi b/dts/src/arm/s3c2416-pinctrl.dtsi index 527e319381..6274359fb3 100644 --- a/dts/src/arm/s3c2416-pinctrl.dtsi +++ b/dts/src/arm/s3c2416-pinctrl.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl_0 { /* * Pin banks @@ -83,91 +85,91 @@ uart0_data: uart0-data { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart0_fctl: uart0-fctl { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart1_data: uart1-data { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart1_fctl: uart1-fctl { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart2_data: uart2-data { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart2_fctl: uart2-fctl { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; uart3_data: uart3-data { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; extuart_clk: extuart-clk { samsung,pins = "gph-12"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; spi0_bus: spi0-bus { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd0_clk: sd0-clk { samsung,pins = "gpe-5"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpe-6"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd0_bus1: sd0-bus1 { samsung,pins = "gpe-7"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd0_bus4: sd0-bus4 { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpl-8"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd1_clk: sd1-clk { samsung,pins = "gpl-9"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd1_bus1: sd1-bus1 { samsung,pins = "gpl-0"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; sd1_bus4: sd1-bus4 { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = <2>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; }; }; diff --git a/dts/src/arm/s3c6410-mini6410.dts b/dts/src/arm/s3c6410-mini6410.dts index a25debb504..f4afda3594 100644 --- a/dts/src/arm/s3c6410-mini6410.dts +++ b/dts/src/arm/s3c6410-mini6410.dts @@ -201,13 +201,13 @@ &pinctrl0 { gpio_leds: gpio-leds { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; gpio_keys: gpio-keys { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; }; diff --git a/dts/src/arm/s3c64xx-pinctrl.dtsi b/dts/src/arm/s3c64xx-pinctrl.dtsi index b1197d8b04..4e8e802b4e 100644 --- a/dts/src/arm/s3c64xx-pinctrl.dtsi +++ b/dts/src/arm/s3c64xx-pinctrl.dtsi @@ -12,9 +12,7 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 2 +#include <dt-bindings/pinctrl/samsung.h> &pinctrl0 { /* @@ -138,514 +136,514 @@ uart0_data: uart0-data { samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart1_data: uart1-data { samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart2_data: uart2-data { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart3_data: uart3-data { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ext_dma_0: ext-dma-0 { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ext_dma_1: ext-dma-1 { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_data_0: irda-data-0 { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_data_1: irda-data-1 { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_sdbw: irda-sdbw { samsung,pins = "gpb-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; i2c1_bus: i2c1-bus { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <6>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_6>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi0_bus: spi0-bus { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi0_cs: spi0-cs { samsung,pins = "gpc-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; spi1_bus: spi1-bus { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi1_cs: spi1-cs { samsung,pins = "gpc-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpg-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_clk: sd0-clk { samsung,pins = "gpg-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_bus1: sd0-bus1 { samsung,pins = "gpg-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_bus4: sd0-bus4 { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_cd: sd0-cd { samsung,pins = "gpg-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; sd1_cmd: sd1-cmd { samsung,pins = "gph-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_clk: sd1-clk { samsung,pins = "gph-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus1: sd1-bus1 { samsung,pins = "gph-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus4: sd1-bus4 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus8: sd1-bus8 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_cd: sd1-cd { samsung,pins = "gpg-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_clk: sd2-clk { samsung,pins = "gpc-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_bus1: sd2-bus1 { samsung,pins = "gph-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_bus4: sd2-bus4 { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s0_bus: i2s0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s0_cdclk: i2s0-cdclk { samsung,pins = "gpd-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s1_cdclk: i2s1-cdclk { samsung,pins = "gpe-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s2_bus: i2s2-bus { /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; - samsung,pin-function = <5>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s2_cdclk: i2s2-cdclk { /* S3C6410-only */ samsung,pins = "gph-7"; - samsung,pin-function = <5>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm0_bus: pcm0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm0_extclk: pcm0-extclk { samsung,pins = "gpd-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm1_extclk: pcm1-extclk { samsung,pins = "gpe-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ac97_bus_0: ac97-bus-0 { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ac97_bus_1: ac97-bus-1 { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; cam_port: cam-port { samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; cam_rst: cam-rst { samsung,pins = "gpf-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; cam_field: cam-field { /* S3C6410-only */ samsung,pins = "gpb-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm_extclk: pwm-extclk { samsung,pins = "gpf-13"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm0_out: pwm0-out { samsung,pins = "gpf-14"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm1_out: pwm1-out { samsung,pins = "gpf-15"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; clkout0: clkout-0 { samsung,pins = "gpf-14"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col0_0: keypad-col0-0 { samsung,pins = "gph-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col1_0: keypad-col1-0 { samsung,pins = "gph-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col2_0: keypad-col2-0 { samsung,pins = "gph-2"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col3_0: keypad-col3-0 { samsung,pins = "gph-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col4_0: keypad-col4-0 { samsung,pins = "gph-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col5_0: keypad-col5-0 { samsung,pins = "gph-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col6_0: keypad-col6-0 { samsung,pins = "gph-6"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col7_0: keypad-col7-0 { samsung,pins = "gph-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col0_1: keypad-col0-1 { samsung,pins = "gpl-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col1_1: keypad-col1-1 { samsung,pins = "gpl-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col2_1: keypad-col2-1 { samsung,pins = "gpl-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col3_1: keypad-col3-1 { samsung,pins = "gpl-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col4_1: keypad-col4-1 { samsung,pins = "gpl-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col5_1: keypad-col5-1 { samsung,pins = "gpl-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col6_1: keypad-col6-1 { samsung,pins = "gpl-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col7_1: keypad-col7-1 { samsung,pins = "gpl-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row0_0: keypad-row0-0 { samsung,pins = "gpk-8"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row1_0: keypad-row1-0 { samsung,pins = "gpk-9"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row2_0: keypad-row2-0 { samsung,pins = "gpk-10"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row3_0: keypad-row3-0 { samsung,pins = "gpk-11"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row4_0: keypad-row4-0 { samsung,pins = "gpk-12"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row5_0: keypad-row5-0 { samsung,pins = "gpk-13"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row6_0: keypad-row6-0 { samsung,pins = "gpk-14"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row7_0: keypad-row7-0 { samsung,pins = "gpk-15"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row0_1: keypad-row0-1 { samsung,pins = "gpn-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row1_1: keypad-row1-1 { samsung,pins = "gpn-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row2_1: keypad-row2-1 { samsung,pins = "gpn-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row3_1: keypad-row3-1 { samsung,pins = "gpn-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row4_1: keypad-row4-1 { samsung,pins = "gpn-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row5_1: keypad-row5-1 { samsung,pins = "gpn-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row6_1: keypad-row6-1 { samsung,pins = "gpn-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row7_1: keypad-row7-1 { samsung,pins = "gpn-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; lcd_data16: lcd-data-width16 { @@ -653,8 +651,8 @@ "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; lcd_data18: lcd-data-width18 { @@ -663,8 +661,8 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; lcd_data24: lcd-data-width24 { @@ -674,14 +672,14 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-0", "gpj-1", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; hsi_bus: hsi-bus { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; }; diff --git a/dts/src/arm/s5pv210-aquila.dts b/dts/src/arm/s5pv210-aquila.dts index da24ab570b..40139923ee 100644 --- a/dts/src/arm/s5pv210-aquila.dts +++ b/dts/src/arm/s5pv210-aquila.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@30000000 { device_type = "memory"; reg = <0x30000000 0x05000000 0x40000000 0x18000000>; @@ -387,7 +387,7 @@ &pinctrl0 { t_flash_detect: t-flash-detect { samsung,pins = "gph3-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; }; diff --git a/dts/src/arm/s5pv210-goni.dts b/dts/src/arm/s5pv210-goni.dts index 0a33d40213..c56f51ee78 100644 --- a/dts/src/arm/s5pv210-goni.dts +++ b/dts/src/arm/s5pv210-goni.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@30000000 { device_type = "memory"; reg = <0x30000000 0x05000000 0x40000000 0x10000000 diff --git a/dts/src/arm/s5pv210-pinctrl.dtsi b/dts/src/arm/s5pv210-pinctrl.dtsi index 8c714088e3..9a3e851e2e 100644 --- a/dts/src/arm/s5pv210-pinctrl.dtsi +++ b/dts/src/arm/s5pv210-pinctrl.dtsi @@ -19,6 +19,8 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/pinctrl/samsung.h> + &pinctrl0 { gpa0: gpa0 { gpio-controller; @@ -270,559 +272,559 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart3_data: uart3-data { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; uart_audio: uart-audio { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s0_bus: i2s0-bus { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row0: keypad-row-0 { samsung,pins = "gph3-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row1: keypad-row-1 { samsung,pins = "gph3-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row2: keypad-row-2 { samsung,pins = "gph3-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row3: keypad-row-3 { samsung,pins = "gph3-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row4: keypad-row-4 { samsung,pins = "gph3-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row5: keypad-row-5 { samsung,pins = "gph3-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row6: keypad-row-6 { samsung,pins = "gph3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_row7: keypad-row-7 { samsung,pins = "gph3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col0: keypad-col-0 { samsung,pins = "gph2-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col1: keypad-col-1 { samsung,pins = "gph2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col2: keypad-col-2 { samsung,pins = "gph2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col3: keypad-col-3 { samsung,pins = "gph2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col4: keypad-col-4 { samsung,pins = "gph2-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col5: keypad-col-5 { samsung,pins = "gph2-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col6: keypad-col-6 { samsung,pins = "gph2-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; keypad_col7: keypad-col-7 { samsung,pins = "gph2-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; sd0_clk: sd0-clk { samsung,pins = "gpg0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpg0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_cd: sd0-cd { samsung,pins = "gpg0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpg0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_clk: sd1-clk { samsung,pins = "gpg1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpg1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_cd: sd1-cd { samsung,pins = "gpg1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpg1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_clk: sd2-clk { samsung,pins = "gpg2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_cd: sd2-cd { samsung,pins = "gpg2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpg2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_clk: sd3-clk { samsung,pins = "gpg3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpg3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_cd: sd3-cd { samsung,pins = "gpg3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpg3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; eint0: ext-int0 { samsung,pins = "gph0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint8: ext-int8 { samsung,pins = "gph1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint15: ext-int15 { samsung,pins = "gph1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint16: ext-int16 { samsung,pins = "gph2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; eint31: ext-int31 { samsung,pins = "gph3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpe1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpe1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_sync: lcd-sync { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; lcd_data24: lcd-data-width24 { @@ -832,8 +834,8 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; diff --git a/dts/src/arm/s5pv210-smdkc110.dts b/dts/src/arm/s5pv210-smdkc110.dts index 1eedab7ffe..5d14da911a 100644 --- a/dts/src/arm/s5pv210-smdkc110.dts +++ b/dts/src/arm/s5pv210-smdkc110.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/dts/src/arm/s5pv210-smdkv210.dts b/dts/src/arm/s5pv210-smdkv210.dts index 9eb6aff3e3..75398318ed 100644 --- a/dts/src/arm/s5pv210-smdkv210.dts +++ b/dts/src/arm/s5pv210-smdkv210.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x40000000>; }; diff --git a/dts/src/arm/s5pv210-torbreck.dts b/dts/src/arm/s5pv210-torbreck.dts index 622599fd2c..7cb50bcee8 100644 --- a/dts/src/arm/s5pv210-torbreck.dts +++ b/dts/src/arm/s5pv210-torbreck.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/dts/src/arm/s5pv210.dtsi b/dts/src/arm/s5pv210.dtsi index ffc36bd24d..a853918be4 100644 --- a/dts/src/arm/s5pv210.dtsi +++ b/dts/src/arm/s5pv210.dtsi @@ -19,11 +19,13 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/s5pv210.h> #include <dt-bindings/clock/s5pv210-audss.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { csis0 = &csis0; fimc0 = &fimc0; diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi index 353d0e5ec8..7173ec9059 100644 --- a/dts/src/arm/sama5d2.dtsi +++ b/dts/src/arm/sama5d2.dtsi @@ -77,6 +77,35 @@ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; }; + etb { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x740000 0x1000>; + + clocks = <&mck>; + clock-names = "apb_pclk"; + + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x73C000 0x1000>; + + clocks = <&mck>; + clock-names = "apb_pclk"; + + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + memory { reg = <0x20000000 0x20000000>; }; diff --git a/dts/src/arm/skeleton.dtsi b/dts/src/arm/skeleton.dtsi index b41d241de2..28b81d60b4 100644 --- a/dts/src/arm/skeleton.dtsi +++ b/dts/src/arm/skeleton.dtsi @@ -1,4 +1,8 @@ /* + * This file is deprecated, and will be removed once existing users have been + * updated. New dts{,i} files should *not* include skeleton.dtsi, and should + * instead explicitly provide the below nodes only as required. + * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. diff --git a/dts/src/arm/socfpga_arria10.dtsi b/dts/src/arm/socfpga_arria10.dtsi index 94000cbe57..f520cbff5e 100644 --- a/dts/src/arm/socfpga_arria10.dtsi +++ b/dts/src/arm/socfpga_arria10.dtsi @@ -639,6 +639,22 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>; }; + + dma-ecc@ff8c8000 { + compatible = "altr,socfpga-dma-ecc"; + reg = <0xff8c8000 0x400>; + altr,ecc-parent = <&pdma>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <42 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c8800 { + compatible = "altr,socfpga-usb-ecc"; + reg = <0xff8c8800 0x400>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>; + }; }; rst: rstmgr@ffd05000 { diff --git a/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts b/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts index 8a7dfa473e..040a164ba1 100644 --- a/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts +++ b/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts @@ -25,3 +25,15 @@ broken-cd; bus-width = <4>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/dts/src/arm/ste-nomadik-nhk15.dts b/dts/src/arm/ste-nomadik-nhk15.dts index d35aa88791..1ec46a794a 100644 --- a/dts/src/arm/ste-nomadik-nhk15.dts +++ b/dts/src/arm/ste-nomadik-nhk15.dts @@ -140,6 +140,10 @@ 0x03020067 // Up 0x0303006c>; // Down }; + stmpe0_pwm: stmpe_pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; }; stmpe1: stmpe2401@44 { compatible = "st,stmpe2401"; @@ -172,6 +176,50 @@ }; amba { + clcd@10120000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&clcd_24bit_mux>; + port { + nomadik_clcd_pads: endpoint { + remote-endpoint = <&nomadik_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <16 8 0>; + }; + }; + + /* + * WVGA connector 21 + * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB + * with TPO touch screen. + */ + panel { + compatible = "tpo,tpg110", "panel-dpi"; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <33200000>; + hactive = <800>; + hback-porch = <216>; + hfront-porch = <40>; + hsync-len = <1>; + vactive = <480>; + vback-porch = <35>; + vfront-porch = <10>; + vsync-len = <1>; + }; + }; + }; + /* Activate RX/TX and CTS/RTS on UART 0 */ uart0: uart@101fd000 { pinctrl-names = "default"; @@ -183,4 +231,24 @@ wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; }; }; + + bl: backlight { + compatible = "pwm-backlight"; + pwms = <&stmpe0_pwm 0 500000>; + pwm-names = "backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; }; diff --git a/dts/src/arm/ste-nomadik-stn8815.dtsi b/dts/src/arm/ste-nomadik-stn8815.dtsi index d2d532a9d7..adb1c0998b 100644 --- a/dts/src/arm/ste-nomadik-stn8815.dtsi +++ b/dts/src/arm/ste-nomadik-stn8815.dtsi @@ -166,6 +166,24 @@ }; }; }; + clcd { + /* + * This should be activated to use the additional + * 8 lines for bits 16 thru 23 from the CLCD block. + */ + clcd_24bit_mux: clcd_mux { + clcd_24bit_mux { + function = "clcd"; + groups = "clcd_16_23_b_1"; + }; + }; + }; + }; + + /* Power Management Unit */ + pmu: pmu@101e9000 { + compatible = "stericsson,nomadik-pmu", "syscon"; + reg = <0x101e0000 0x1000>; }; src: src@101e0000 { @@ -726,6 +744,16 @@ #size-cells = <1>; ranges; + clcd@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&clcdclk>, <&hclkclcd>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + vica: intc@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; diff --git a/dts/src/arm/stih407-clock.dtsi b/dts/src/arm/stih407-clock.dtsi index ad45f5e8fa..13029c03d7 100644 --- a/dts/src/arm/stih407-clock.dtsi +++ b/dts/src/arm/stih407-clock.dtsi @@ -42,7 +42,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -55,7 +55,7 @@ */ clk_m_a9: clk-m-a9@92b0000 { #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + compatible = "st,stih407-clkgen-a9-mux"; reg = <0x92b0000 0x10000>; clocks = <&clockgen_a9_pll 0>, @@ -96,7 +96,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -117,7 +117,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -134,7 +134,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -143,7 +143,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -199,7 +199,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -216,7 +216,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, @@ -233,7 +233,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -256,7 +256,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, @@ -287,7 +287,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/dts/src/arm/stih407-family.dtsi b/dts/src/arm/stih407-family.dtsi index 8b063ab10c..91096a49ef 100644 --- a/dts/src/arm/stih407-family.dtsi +++ b/dts/src/arm/stih407-family.dtsi @@ -554,7 +554,6 @@ clocks = <&clk_s_c0_flexgen CLK_MMC_0>, <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; bus-width = <8>; - non-removable; }; mmc1: sdhci@09080000 { @@ -610,6 +609,8 @@ clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + ports-implemented = <0x1>; + status = "disabled"; }; @@ -633,6 +634,8 @@ clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + ports-implemented = <0x1>; + status = "disabled"; }; @@ -669,6 +672,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9810000 0x68>; + interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default>; clock-names = "pwm"; @@ -736,6 +740,18 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; + cec: sti-cec@094a087c { + compatible = "st,stih-cec"; + reg = <0x94a087c 0x64>; + clocks = <&clk_sysin>; + clock-names = "cec-clk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>; + interrupt-names = "cec-irq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cec0_default>; + resets = <&softreset STIH407_LPM_SOFTRESET>; + }; + rng10: rng@08a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; @@ -823,5 +839,172 @@ clock-frequency = <600000000>; st,syscfg = <&syscfg_core 0x224>; }; + + /* fdma audio */ + fdma0: dma-controller@8e20000 { + compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; + reg = <0x8e20000 0x8000>, + <0x8e30000 0x3000>, + <0x8e37000 0x1000>, + <0x8e38000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma app */ + fdma1: dma-controller@8e40000 { + compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; + reg = <0x8e40000 0x8000>, + <0x8e50000 0x3000>, + <0x8e57000 0x1000>, + <0x8e58000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma free running */ + fdma2: dma-controller@8e60000 { + compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; + reg = <0x8e60000 0x8000>, + <0x8e70000 0x3000>, + <0x8e77000 0x1000>, + <0x8e78000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>; + dma-channels = <16>; + #dma-cells = <3>; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + }; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; + + sti_uni_player0: sti-uni-player@8d80000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; + assigned-clock-rates = <50000000>; + reg = <0x8d80000 0x158>; + interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; + dmas = <&fdma0 2 0 1>; + dai-name = "Uni Player #0 (HDMI)"; + dma-names = "tx"; + st,uniperiph-id = <0>; + st,version = <5>; + st,mode = "HDMI"; + + status = "disabled"; + }; + + sti_uni_player1: sti-uni-player@8d81000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; + assigned-clock-rates = <50000000>; + reg = <0x8d81000 0x158>; + interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; + dmas = <&fdma0 3 0 1>; + dai-name = "Uni Player #1 (PIO)"; + dma-names = "tx"; + st,uniperiph-id = <1>; + st,version = <5>; + st,mode = "PCM"; + + status = "disabled"; + }; + + sti_uni_player2: sti-uni-player@8d82000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; + assigned-clock-rates = <50000000>; + reg = <0x8d82000 0x158>; + interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; + dmas = <&fdma0 4 0 1>; + dai-name = "Uni Player #1 (DAC)"; + dma-names = "tx"; + st,uniperiph-id = <2>; + st,version = <5>; + st,mode = "PCM"; + + status = "disabled"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; + assigned-clock-rates = <50000000>; + reg = <0x8d85000 0x158>; + interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; + dmas = <&fdma0 7 0 1>; + dma-names = "tx"; + dai-name = "Uni Player #1 (PIO)"; + st,uniperiph-id = <3>; + st,version = <5>; + st,mode = "SPDIF"; + + status = "disabled"; + }; + + sti_uni_reader0: sti-uni-reader@8d83000 { + compatible = "st,sti-uni-reader"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d83000 0x158>; + interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; + dmas = <&fdma0 5 0 1>; + dma-names = "rx"; + dai-name = "Uni Reader #0 (PCM IN)"; + st,version = <3>; + + status = "disabled"; + }; + + sti_uni_reader1: sti-uni-reader@8d84000 { + compatible = "st,sti-uni-reader"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d84000 0x158>; + interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; + dmas = <&fdma0 6 0 1>; + dma-names = "rx"; + dai-name = "Uni Reader #1 (HDMI RX)"; + st,version = <3>; + + status = "disabled"; + }; }; }; diff --git a/dts/src/arm/stih407-pinctrl.dtsi b/dts/src/arm/stih407-pinctrl.dtsi index a538ae52d3..c325cc059a 100644 --- a/dts/src/arm/stih407-pinctrl.dtsi +++ b/dts/src/arm/stih407-pinctrl.dtsi @@ -58,7 +58,7 @@ pio0: gpio@09610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -66,7 +66,7 @@ }; pio1: gpio@09611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -74,7 +74,7 @@ }; pio2: gpio@09612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -82,7 +82,7 @@ }; pio3: gpio@09613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -90,7 +90,7 @@ }; pio4: gpio@09614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -99,7 +99,7 @@ pio5: gpio@09615000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -230,6 +230,13 @@ }; }; + pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { + st,pins { + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + pinctrl_mii1: mii1 { st,pins { txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; @@ -289,10 +296,12 @@ pinctrl_pwm1_chan0_default: pwm1-0-default { st,pins { pwm-out = <&pio3 0 ALT1 OUT>; + pwm-capturein = <&pio3 2 ALT1 IN>; }; }; pinctrl_pwm1_chan1_default: pwm1-1-default { st,pins { + pwm-capturein = <&pio4 3 ALT1 IN>; pwm-out = <&pio4 4 ALT1 OUT>; }; }; @@ -373,7 +382,7 @@ pio10: pio@09200000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -381,7 +390,7 @@ }; pio11: pio@09201000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -389,7 +398,7 @@ }; pio12: pio@09202000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -397,7 +406,7 @@ }; pio13: pio@09203000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -405,7 +414,7 @@ }; pio14: pio@09204000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -413,7 +422,7 @@ }; pio15: pio@09205000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -421,7 +430,7 @@ }; pio16: pio@09206000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -429,7 +438,7 @@ }; pio17: pio@09207000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -437,7 +446,7 @@ }; pio18: pio@09208000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x100>; @@ -445,7 +454,7 @@ }; pio19: pio@09209000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x9000 0x100>; @@ -523,6 +532,13 @@ scl = <&pio15 5 ALT2 BIDIR>; }; }; + + pinctrl_i2c2_alt2_1: i2c2-alt2-1 { + st,pins { + sda = <&pio12 6 ALT2 BIDIR>; + scl = <&pio12 5 ALT2 BIDIR>; + }; + }; }; i2c3 { @@ -916,6 +932,15 @@ interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; + pio20: pio@09210000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO20"; + }; + tsin4 { pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { st,pins { @@ -927,15 +952,6 @@ }; }; }; - - pio20: pio@09210000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; }; pin-controller-rear { @@ -951,7 +967,7 @@ pio30: gpio@09220000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -959,7 +975,7 @@ }; pio31: gpio@09221000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -967,7 +983,7 @@ }; pio32: gpio@09222000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -975,7 +991,7 @@ }; pio33: gpio@09223000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -983,7 +999,7 @@ }; pio34: gpio@09224000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -991,7 +1007,7 @@ }; pio35: gpio@09225000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -1030,6 +1046,7 @@ pwm0 { pinctrl_pwm0_chan0_default: pwm0-0-default { st,pins { + pwm-capturein = <&pio31 0 ALT1 IN>; pwm-out = <&pio31 1 ALT1 OUT>; }; }; @@ -1067,6 +1084,61 @@ }; }; + i2s_out { + pinctrl_i2s_8ch_out: i2s_8ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + data1 = <&pio34 0 ALT1 OUT>; + data2 = <&pio34 1 ALT1 OUT>; + data3 = <&pio34 2 ALT1 OUT>; + }; + }; + + pinctrl_i2s_2ch_out: i2s_2ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + }; + }; + }; + + i2s_in { + pinctrl_i2s_8ch_in: i2s_8ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + data1 = <&pio33 0 ALT1 IN>; + data2 = <&pio33 1 ALT1 IN>; + data3 = <&pio33 2 ALT1 IN>; + data4 = <&pio33 3 ALT1 IN>; + }; + }; + + pinctrl_i2s_2ch_in: i2s_2ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + }; + }; + }; + + spdif_out { + pinctrl_spdif_out: spdif_out{ + st,pins { + spdif_out = <&pio34 7 ALT1 OUT>; + }; + }; + }; + serial3 { pinctrl_serial3: serial3-0 { st,pins { @@ -1090,7 +1162,7 @@ pio40: gpio@09230000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -1098,7 +1170,7 @@ }; pio41: gpio@09231000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -1106,7 +1178,7 @@ }; pio42: gpio@09232000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; diff --git a/dts/src/arm/stih407.dtsi b/dts/src/arm/stih407.dtsi index d60f0d8add..291ffacbd2 100644 --- a/dts/src/arm/stih407.dtsi +++ b/dts/src/arm/stih407.dtsi @@ -16,7 +16,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -26,14 +29,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; diff --git a/dts/src/arm/stih410-b2260.dts b/dts/src/arm/stih410-b2260.dts new file mode 100644 index 0000000000..ef2ff2f518 --- /dev/null +++ b/dts/src/arm/stih410-b2260.dts @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2016 STMicroelectronics (R&D) Limited. + * Author: Patrice Chotard <patrice.chotard@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "stih410.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "STiH410 B2260"; + compatible = "st,stih410-b2260", "st,stih410"; + + chosen { + bootargs = "console=ttyAS1,115200 clk_ignore_unused"; + linux,stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + ttyAS1 = &uart1; + ethernet0 = ðernet0; + }; + + soc { + + leds { + compatible = "gpio-leds"; + user_green_1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user_green_2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user_green_3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user_green_4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + /* Low speed expansion connector */ + uart0: serial@9830000 { + label = "LS-UART0"; + status = "okay"; + }; + + /* Low speed expansion connector */ + uart1: serial@9831000 { + label = "LS-UART1"; + status = "okay"; + }; + + /* Low speed expansion connector */ + spi0: spi@9844000 { + label = "LS-SPI0"; + cs-gpio = <&pio30 3 0>; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c0: i2c@9840000 { + label = "LS-I2C0"; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c1: i2c@9841000 { + label = "LS-I2C1"; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c2: i2c@9842000 { + label = "HS-I2C2"; + pinctrl-0 = <&pinctrl_i2c2_alt2_1>; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c3: i2c@9843000 { + label = "HS-I2C3"; + pinctrl-0 = <&pinctrl_i2c3_alt3_0>; + status = "okay"; + }; + + mmc0: sdhci@09060000 { + pinctrl-0 = <&pinctrl_sd0>; + bus-width = <4>; + status = "okay"; + }; + + /* high speed expansion connector */ + mmc1: sdhci@09080000 { + status = "okay"; + }; + + pwm0: pwm@9810000 { + status = "okay"; + }; + + pwm1: pwm@9510000 { + status = "okay"; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + + ohci0: usb@9a03c00 { + status = "okay"; + }; + + ehci0: usb@9a03e00 { + status = "okay"; + }; + + ohci1: usb@9a83c00 { + status = "okay"; + }; + + ehci1: usb@9a83e00 { + status = "okay"; + }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + phy-mode = "rgmii"; + pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; + + snps,phy-bus-name = "stmmac"; + snps,phy-bus-id = <0>; + snps,phy-addr = <0>; + snps,reset-gpio = <&pio0 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + + status = "okay"; + }; + + /* SSC11 to HDMI */ + hdmiddc: i2c@9541000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + status = "okay"; + }; + + sti-display-subsystem { + sti_hdmi: sti-hdmi@8d04000 { + status = "okay"; + }; + }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + sata1: sata@9b28000 { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm/stih410-clock.dtsi b/dts/src/arm/stih410-clock.dtsi index fd50496821..8598effd6c 100644 --- a/dts/src/arm/stih410-clock.dtsi +++ b/dts/src/arm/stih410-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -122,7 +122,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -140,7 +140,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -150,7 +150,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -218,7 +218,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -235,7 +235,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, @@ -254,7 +254,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -277,7 +277,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, @@ -308,7 +308,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/dts/src/arm/stih410.dtsi b/dts/src/arm/stih410.dtsi index 40318869c7..a3ef7341c0 100644 --- a/dts/src/arm/stih410.dtsi +++ b/dts/src/arm/stih410.dtsi @@ -107,7 +107,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -117,14 +120,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; @@ -231,5 +241,23 @@ clock-names = "bdisp"; clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; + + hva@8c85000 { + compatible = "st,st-hva"; + reg = <0x8c85000 0x400>, <0x6000000 0x40000>; + reg-names = "hva_registers", "hva_esram"; + interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>, + <GIC_SPI 59 IRQ_TYPE_NONE>; + clock-names = "clk_hva"; + clocks = <&clk_s_c0_flexgen CLK_HVA>; + }; + + thermal@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&clk_sysin>; + interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; + }; }; }; diff --git a/dts/src/arm/stih415-pinctrl.dtsi b/dts/src/arm/stih415-pinctrl.dtsi index 3791ad95db..bd028ce98b 100644 --- a/dts/src/arm/stih415-pinctrl.dtsi +++ b/dts/src/arm/stih415-pinctrl.dtsi @@ -54,7 +54,7 @@ pio0: gpio@fe610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -62,7 +62,7 @@ }; pio1: gpio@fe611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -70,7 +70,7 @@ }; pio2: gpio@fe612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -78,7 +78,7 @@ }; pio3: gpio@fe613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -86,7 +86,7 @@ }; pio4: gpio@fe614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -208,7 +208,7 @@ pio5: gpio@fee00000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -216,7 +216,7 @@ }; pio6: gpio@fee01000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -224,7 +224,7 @@ }; pio7: gpio@fee02000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -232,7 +232,7 @@ }; pio8: gpio@fee03000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -240,7 +240,7 @@ }; pio9: gpio@fee04000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -248,7 +248,7 @@ }; pio10: gpio@fee05000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -256,7 +256,7 @@ }; pio11: gpio@fee06000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -264,7 +264,7 @@ }; pio12: gpio@fee07000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -303,7 +303,7 @@ pio13: gpio@fe820000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -311,7 +311,7 @@ }; pio14: gpio@fe821000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -319,7 +319,7 @@ }; pio15: gpio@fe822000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -327,7 +327,7 @@ }; pio16: gpio@fe823000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -335,7 +335,7 @@ }; pio17: gpio@fe824000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -343,7 +343,7 @@ }; pio18: gpio@fe825000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -465,7 +465,7 @@ pio100: gpio@fd6b0000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -473,7 +473,7 @@ }; pio101: gpio@fd6b1000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -481,7 +481,7 @@ }; pio102: gpio@fd6b2000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -502,7 +502,7 @@ pio103: gpio@fd330000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -510,7 +510,7 @@ }; pio104: gpio@fd331000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -518,7 +518,7 @@ }; pio105: gpio@fd332000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -526,7 +526,7 @@ }; pio106: gpio@fd333000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -534,7 +534,7 @@ }; pio107: gpio@fd334000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; diff --git a/dts/src/arm/stih416-b2020e.dts b/dts/src/arm/stih416-b2020e.dts index f1ceee192a..de320cd067 100644 --- a/dts/src/arm/stih416-b2020e.dts +++ b/dts/src/arm/stih416-b2020e.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "stih416.dtsi" #include "stih41x-b2020.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "STiH416 B2020 REV-E"; compatible = "st,stih416-b2020", "st,stih416"; @@ -17,13 +18,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio4 1>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&pio1 3>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; diff --git a/dts/src/arm/stih416-pinctrl.dtsi b/dts/src/arm/stih416-pinctrl.dtsi index 051fc16f37..9c97f7e651 100644 --- a/dts/src/arm/stih416-pinctrl.dtsi +++ b/dts/src/arm/stih416-pinctrl.dtsi @@ -58,7 +58,7 @@ pio0: gpio@fe610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -66,7 +66,7 @@ }; pio1: gpio@fe611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -74,7 +74,7 @@ }; pio2: gpio@fe612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -82,7 +82,7 @@ }; pio3: gpio@fe613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -90,7 +90,7 @@ }; pio4: gpio@fe614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -98,7 +98,7 @@ }; pio40: gpio@fe615000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -221,11 +221,14 @@ pinctrl_pwm1_chan0_default: pwm1-0-default { st,pins { pwm-out = <&pio3 0 ALT1 OUT>; + pwm-capturein = <&pio3 2 ALT1 IN>; + }; }; pinctrl_pwm1_chan1_default: pwm1-1-default { st,pins { pwm-out = <&pio4 4 ALT1 OUT>; + pwm-capturein = <&pio4 3 ALT1 IN>; }; }; pinctrl_pwm1_chan2_default: pwm1-2-default { @@ -254,7 +257,7 @@ pio5: gpio@fee00000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -262,7 +265,7 @@ }; pio6: gpio@fee01000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -270,7 +273,7 @@ }; pio7: gpio@fee02000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -278,7 +281,7 @@ }; pio8: gpio@fee03000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -286,7 +289,7 @@ }; pio9: gpio@fee04000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -294,7 +297,7 @@ }; pio10: gpio@fee05000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -302,7 +305,7 @@ }; pio11: gpio@fee06000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -310,7 +313,7 @@ }; pio12: gpio@fee07000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -318,7 +321,7 @@ }; pio30: gpio@fee08000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x100>; @@ -326,7 +329,7 @@ }; pio31: gpio@fee09000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x9000 0x100>; @@ -337,6 +340,7 @@ pinctrl_pwm0_chan0_default: pwm0-0-default { st,pins { pwm-out = <&pio9 7 ALT2 OUT>; + pwm-capturein = <&pio9 6 ALT2 IN>; }; }; }; @@ -404,7 +408,7 @@ pio13: gpio@fe820000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -412,7 +416,7 @@ }; pio14: gpio@fe821000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -420,7 +424,7 @@ }; pio15: gpio@fe822000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -428,7 +432,7 @@ }; pio16: gpio@fe823000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -436,7 +440,7 @@ }; pio17: gpio@fe824000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -444,7 +448,7 @@ }; pio18: gpio@fe825000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -576,6 +580,7 @@ pinctrl_pwm0_chan1_default: pwm0-1-default { st,pins { pwm-out = <&pio13 2 ALT2 OUT>; + pwm-capturein = <&pio13 1 ALT2 IN>; }; }; pinctrl_pwm0_chan2_default: pwm0-2-default { @@ -605,7 +610,7 @@ pio100: gpio@fd6b0000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -613,7 +618,7 @@ }; pio101: gpio@fd6b1000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -621,7 +626,7 @@ }; pio102: gpio@fd6b2000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -642,7 +647,7 @@ pio103: gpio@fd330000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -650,7 +655,7 @@ }; pio104: gpio@fd331000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -658,7 +663,7 @@ }; pio105: gpio@fd332000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -666,7 +671,7 @@ }; pio106: gpio@fd333000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -675,7 +680,7 @@ pio107: gpio@fd334000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; diff --git a/dts/src/arm/stih416.dtsi b/dts/src/arm/stih416.dtsi index 9e3170ccd1..fe1f9cf770 100644 --- a/dts/src/arm/stih416.dtsi +++ b/dts/src/arm/stih416.dtsi @@ -474,6 +474,7 @@ status = "disabled"; #pwm-cells = <2>; reg = <0xfed10000 0x68>; + interrupts = <GIC_SPI 200 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default @@ -481,9 +482,11 @@ &pinctrl_pwm0_chan2_default &pinctrl_pwm0_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + clock-names = "pwm", "capture"; + clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; + st,pwm-num-chan = <4>; + st,capture-num-chan = <2>; }; /* SBC PWM Module */ @@ -492,6 +495,7 @@ status = "disabled"; #pwm-cells = <2>; reg = <0xfe510000 0x68>; + interrupts = <GIC_SPI 202 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1_chan0_default diff --git a/dts/src/arm/stih418-b2199.dts b/dts/src/arm/stih418-b2199.dts index 772d2bb07e..438e54c585 100644 --- a/dts/src/arm/stih418-b2199.dts +++ b/dts/src/arm/stih418-b2199.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "stih418.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "STiH418 B2199"; compatible = "st,stih418-b2199", "st,stih418"; @@ -35,14 +36,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <2>; label = "Front Panel LED"; - gpios = <&pio4 1 0>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; @@ -86,6 +85,7 @@ sd-uhs-sdr50; sd-uhs-sdr104; sd-uhs-ddr50; + non-removable; }; miphy28lp_phy: miphy28lp@9b22000 { diff --git a/dts/src/arm/stih418-clock.dtsi b/dts/src/arm/stih418-clock.dtsi index ae6d9978ea..ee6614b79f 100644 --- a/dts/src/arm/stih418-clock.dtsi +++ b/dts/src/arm/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -120,7 +120,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -212,7 +212,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -229,7 +229,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, @@ -248,7 +248,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -271,7 +271,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, @@ -309,7 +309,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/dts/src/arm/stih41x-b2000.dtsi b/dts/src/arm/stih41x-b2000.dtsi index 5f91f455f0..9bfa0674b4 100644 --- a/dts/src/arm/stih41x-b2000.dtsi +++ b/dts/src/arm/stih41x-b2000.dtsi @@ -7,6 +7,8 @@ * publishhed by the Free Software Foundation. */ #include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + / { memory{ @@ -33,9 +35,8 @@ leds { compatible = "gpio-leds"; fp_led { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio105 7>; + gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; diff --git a/dts/src/arm/stih41x-b2020.dtsi b/dts/src/arm/stih41x-b2020.dtsi index 487d7d87db..322e0e9517 100644 --- a/dts/src/arm/stih41x-b2020.dtsi +++ b/dts/src/arm/stih41x-b2020.dtsi @@ -7,6 +7,7 @@ * publishhed by the Free Software Foundation. */ #include "stih41x-b2020x.dtsi" +#include <dt-bindings/gpio/gpio.h> / { memory{ device_type = "memory"; @@ -30,13 +31,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio4 1>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&pio4 7>; + gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; diff --git a/dts/src/arm/stihxxx-b2120.dtsi b/dts/src/arm/stihxxx-b2120.dtsi index 133375bc8a..ed2b7a99ec 100644 --- a/dts/src/arm/stihxxx-b2120.dtsi +++ b/dts/src/arm/stihxxx-b2120.dtsi @@ -18,14 +18,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <2>; label = "Front Panel LED"; - gpios = <&pio4 1 0>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; @@ -65,6 +63,7 @@ }; mmc0: sdhci@09060000 { + non-removable; status = "okay"; }; @@ -135,5 +134,50 @@ dvb-card = <STV0367_TDA18212_NIMA_1>; }; }; + + sti_uni_player2: sti-uni-player@8d82000 { + status = "okay"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + status = "okay"; + }; + + sti_sasg_codec: sti-sasg-codec { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_out>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sti audio card"; + status = "okay"; + + simple-audio-card,dai-link@0 { + /* DAC */ + format = "i2s"; + mclk-fs = <256>; + cpu { + sound-dai = <&sti_uni_player2>; + }; + + codec { + sound-dai = <&sti_sasg_codec 1>; + }; + }; + simple-audio-card,dai-link@1 { + /* SPDIF */ + format = "left_j"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player3>; + }; + + codec { + sound-dai = <&sti_sasg_codec 0>; + }; + }; + }; }; }; diff --git a/dts/src/arm/stm32f429.dtsi b/dts/src/arm/stm32f429.dtsi index 35df462559..336ee4fb58 100644 --- a/dts/src/arm/stm32f429.dtsi +++ b/dts/src/arm/stm32f429.dtsi @@ -45,6 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> @@ -176,6 +177,14 @@ reg = <0x40013800 0x400>; }; + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + pin-controller { #address-cells = <1>; #size-cells = <1>; @@ -326,6 +335,7 @@ }; rcc: rcc@40023810 { + #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; diff --git a/dts/src/arm/sun4i-a10-ba10-tvbox.dts b/dts/src/arm/sun4i-a10-ba10-tvbox.dts index f3cb297fd1..5f98582232 100644 --- a/dts/src/arm/sun4i-a10-ba10-tvbox.dts +++ b/dts/src/arm/sun4i-a10-ba10-tvbox.dts @@ -121,10 +121,6 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - &otg_sram { status = "okay"; }; diff --git a/dts/src/arm/sun5i-a13-empire-electronix-m712.dts b/dts/src/arm/sun5i-a13-empire-electronix-m712.dts new file mode 100644 index 0000000000..b1e2afd9de --- /dev/null +++ b/dts/src/arm/sun5i-a13-empire-electronix-m712.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Empire Electronix M712 tablet"; + compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +}; diff --git a/dts/src/arm/sun5i-a13-inet-98v-rev2.dts b/dts/src/arm/sun5i-a13-inet-98v-rev2.dts index 1b11ec95ae..439ae3b537 100644 --- a/dts/src/arm/sun5i-a13-inet-98v-rev2.dts +++ b/dts/src/arm/sun5i-a13-inet-98v-rev2.dts @@ -42,171 +42,9 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun5i-reference-design-tablet.dtsi" / { model = "INet-98V Rev 02"; compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; }; diff --git a/dts/src/arm/sun5i-r8-chip.dts b/dts/src/arm/sun5i-r8-chip.dts index f694482bde..b68a12374b 100644 --- a/dts/src/arm/sun5i-r8-chip.dts +++ b/dts/src/arm/sun5i-r8-chip.dts @@ -64,6 +64,16 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + status { + label = "chip:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; }; &be0 { diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi index 1867af24ff..ce1960453a 100644 --- a/dts/src/arm/sun6i-a31.dtsi +++ b/dts/src/arm/sun6i-a31.dtsi @@ -47,7 +47,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/clock/sun6i-a31-ccu.h> #include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun6i-a31-ccu.h> / { interrupt-parent = <&gic>; @@ -65,7 +67,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, + <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, + <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; status = "disabled"; }; @@ -73,7 +78,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; status = "disabled"; }; }; @@ -97,7 +104,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -192,235 +199,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - - /* - * Clock AHB1 from PLL6, instead of CPU/AXI which - * has rate changes due to cpufreq. Also the DMA - * controller requires AHB1 clocked from PLL6. - */ - assigned-clocks = <&ahb1>; - assigned-clock-parents = <&pll6 0>; - }; - - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, - <17>, <18>, <19>, - <20>, <21>, <22>, - <23>, <24>, <26>, - <27>, <29>, - <30>, <31>, <32>, - <36>, <37>, <40>, - <43>, <44>, <45>, - <46>, <47>, <50>, - <52>, <55>, <56>, - <57>, <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", - "ahb1_nand0", "ahb1_sdram", - "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", - "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", - "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", - "ahb1_ehci1", "ahb1_ohci0", - "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", - "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", - "ahb1_hdmi", "ahb1_de0", "ahb1_de1", - "ahb1_fe0", "ahb1_fe1", "ahb1_mp", - "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", - "ahb1_drc0", "ahb1_drc1"; - }; - - apb1: apb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <4>, - <5>, <12>, - <13>; - clock-output-names = "apb1_codec", "apb1_digital_mic", - "apb1_pio", "apb1_daudio0", - "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <3>, <16>, - <17>, <18>, <19>, - <20>, <21>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_i2c3", - "apb2_uart0", "apb2_uart1", - "apb2_uart2", "apb2_uart3", - "apb2_uart4", "apb2_uart5"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi2"; - }; - - spi3_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi3"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-indices = <8>, <9>, <10>, - <16>, <17>, - <18>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", - "usb_ohci0", "usb_ohci1", - "usb_ohci2"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -463,23 +241,23 @@ compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_AHB1_DMA>; + resets = <&ccu RST_AHB1_DMA>; #dma-cells = <1>; }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB1_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_AHB1_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -488,17 +266,17 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB1_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_AHB1_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -507,17 +285,17 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB1_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_AHB1_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -526,17 +304,17 @@ }; mmc3: mmc@01c12000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb1_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB1_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 11>; + resets = <&ccu RST_AHB1_MMC3>; reset-names = "ahb"; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -547,8 +325,8 @@ usb_otg: usb@01c19000 { compatible = "allwinner,sun6i-a31-musb"; reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; + clocks = <&ccu CLK_AHB1_OTG>; + resets = <&ccu RST_AHB1_OTG>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -565,15 +343,15 @@ reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>, - <&usb_clk 9>, - <&usb_clk 10>; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; clock-names = "usb0_phy", "usb1_phy", "usb2_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>, - <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; @@ -585,8 +363,8 @@ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_AHB1_EHCI0>; + resets = <&ccu RST_AHB1_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -596,8 +374,8 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_AHB1_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -607,8 +385,8 @@ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 27>; - resets = <&ahb1_rst 27>; + clocks = <&ccu CLK_AHB1_EHCI1>; + resets = <&ccu RST_AHB1_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -618,8 +396,8 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 30>, <&usb_clk 17>; - resets = <&ahb1_rst 30>; + clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_AHB1_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -629,11 +407,20 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 31>, <&usb_clk 18>; - resets = <&ahb1_rst 31>; + clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_AHB1_OHCI2>; status = "disabled"; }; + ccu: clock@01c20000 { + compatible = "allwinner,sun6i-a31-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -641,7 +428,7 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_APB1_PIO>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -762,24 +549,6 @@ }; }; - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; - }; - timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; @@ -816,8 +585,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_APB2_UART0>; + resets = <&ccu RST_APB2_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; @@ -829,8 +598,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_APB2_UART1>; + resets = <&ccu RST_APB2_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; @@ -842,8 +611,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_APB2_UART2>; + resets = <&ccu RST_APB2_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -855,8 +624,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_APB2_UART3>; + resets = <&ccu RST_APB2_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -868,8 +637,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_APB2_UART4>; + resets = <&ccu RST_APB2_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -881,8 +650,8 @@ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 21>; - resets = <&apb2_rst 21>; + clocks = <&ccu CLK_APB2_UART5>; + resets = <&ccu RST_APB2_UART5>; dmas = <&dma 22>, <&dma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -892,8 +661,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_APB2_I2C0>; + resets = <&ccu RST_APB2_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -903,8 +672,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_APB2_I2C1>; + resets = <&ccu RST_APB2_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -914,8 +683,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_APB2_I2C2>; + resets = <&ccu RST_APB2_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -925,8 +694,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 3>; - resets = <&apb2_rst 3>; + clocks = <&ccu CLK_APB2_I2C3>; + resets = <&ccu RST_APB2_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -937,9 +706,9 @@ reg = <0x01c30000 0x1054>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ahb1_rst 17>; + resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; @@ -953,9 +722,9 @@ compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_AHB1_SS>; reset-names = "ahb"; }; @@ -967,19 +736,19 @@ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 19>; - resets = <&ahb1_rst 19>; + clocks = <&ccu CLK_AHB1_HSTIMER>; + resets = <&ccu RST_AHB1_HSTIMER>; }; spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma 23>, <&dma 23>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 20>; + resets = <&ccu RST_AHB1_SPI0>; status = "disabled"; }; @@ -987,11 +756,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma 24>, <&dma 24>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 21>; + resets = <&ccu RST_AHB1_SPI1>; status = "disabled"; }; @@ -999,11 +768,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma 25>, <&dma 25>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 22>; + resets = <&ccu RST_AHB1_SPI2>; status = "disabled"; }; @@ -1011,11 +780,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma 26>, <&dma 26>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 23>; + resets = <&ccu RST_AHB1_SPI3>; status = "disabled"; }; @@ -1052,8 +821,9 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, - <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, + <&ccu CLK_PLL_PERIPH>, + <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; }; diff --git a/dts/src/arm/sun6i-a31s-colorfly-e708-q1.dts b/dts/src/arm/sun6i-a31s-colorfly-e708-q1.dts index e182eec6d8..882a4d89fa 100644 --- a/dts/src/arm/sun6i-a31s-colorfly-e708-q1.dts +++ b/dts/src/arm/sun6i-a31s-colorfly-e708-q1.dts @@ -42,32 +42,11 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun6i-reference-design-tablet.dtsi" / { model = "Colorfly E708 Q1 tablet"; compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; }; &lradc { @@ -82,103 +61,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&pio { - mma8452_int_e708_q1: mma8452_int_pin@0 { - allwinner,pins = "PA9"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - ®_dldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -186,23 +68,5 @@ }; &simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; vcc-pg-supply = <®_dldo2>; }; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp221 pmic on the board. - * - * Once we have axp221 power-supply and vbus-usb support we should switch - * to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/dts/src/arm/sun6i-a31s-inet-q972.dts b/dts/src/arm/sun6i-a31s-inet-q972.dts new file mode 100644 index 0000000000..e584e6b186 --- /dev/null +++ b/dts/src/arm/sun6i-a31s-inet-q972.dts @@ -0,0 +1,100 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sun6i-reference-design-tablet.dtsi" + +/ { + model = "iNet Q972 tablet"; + compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button@200 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <200000>; + }; + + button@900 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <900000>; + }; + + button@1200 { + label = "Back"; + linux,code = <KEY_BACK>; + channel = <0>; + voltage = <1200000>; + }; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-reference-design-tablet.dtsi b/dts/src/arm/sun6i-reference-design-tablet.dtsi new file mode 100644 index 0000000000..0c434304e0 --- /dev/null +++ b/dts/src/arm/sun6i-reference-design-tablet.dtsi @@ -0,0 +1,193 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + /* Wifi is connected here */ + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi index bd0c476602..94cf5a1c71 100644 --- a/dts/src/arm/sun7i-a20.dtsi +++ b/dts/src/arm/sun7i-a20.dtsi @@ -905,7 +905,7 @@ }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ahb_gates 8>, <&mmc0_clk 0>, @@ -922,7 +922,7 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ahb_gates 9>, <&mmc1_clk 0>, @@ -939,7 +939,7 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ahb_gates 10>, <&mmc2_clk 0>, @@ -956,7 +956,7 @@ }; mmc3: mmc@01c12000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; clocks = <&ahb_gates 11>, <&mmc3_clk 0>, diff --git a/dts/src/arm/sun8i-a23-a33.dtsi b/dts/src/arm/sun8i-a23-a33.dtsi index 7e05e09e61..48fc24f36f 100644 --- a/dts/src/arm/sun8i-a23-a33.dtsi +++ b/dts/src/arm/sun8i-a23-a33.dtsi @@ -46,7 +46,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> / { interrupt-parent = <&gic>; @@ -60,7 +62,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, + <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; status = "disabled"; }; }; @@ -111,143 +115,6 @@ clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - /* dummy clock until actually implemented */ - pll5: pll5_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll5"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - }; - - apb1: apb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <5>, - <12>, <13>; - clock-output-names = "apb1_codec", "apb1_pio", - "apb1_daudio0", "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <16>, - <17>, <18>, - <19>, <20>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_uart0", - "apb2_uart1", "apb2_uart2", - "apb2_uart3", "apb2_uart4"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun8i-a23-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", - "usb_hsic_12M", "usb_ohci0"; - }; }; soc@01c00000 { @@ -260,23 +127,23 @@ compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; #dma-cells = <1>; }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -285,17 +152,17 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -304,17 +171,17 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -322,12 +189,55 @@ #size-cells = <0>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c19000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + /* + * compatible and address regions get set in + * SoC specific dtsi file + */ + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + ehci0: usb@01c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_BUS_EHCI>; + resets = <&ccu RST_BUS_EHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -337,18 +247,26 @@ compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; + resets = <&ccu RST_BUS_OHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; + ccu: clock@01c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_BUS_PIO>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -361,6 +279,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + uart1_pins_a: uart1@0 { + allwinner,pins = "PG6", "PG7"; + allwinner,function = "uart1"; + }; + + uart1_pins_cts_rts_a: uart1-cts-rts@0 { + allwinner,pins = "PG8", "PG9"; + allwinner,function = "uart1"; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -414,24 +342,16 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - }; - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; + lcd_rgb666_pins: lcd-rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; timer@01c20c00 { @@ -469,8 +389,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; @@ -482,8 +402,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; @@ -495,8 +415,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -508,8 +428,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -521,8 +441,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -532,8 +452,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -543,8 +463,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -554,8 +474,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/sun8i-a23-gt90h-v4.dts b/dts/src/arm/sun8i-a23-gt90h-v4.dts index b2ce284a65..e3c7a25ca3 100644 --- a/dts/src/arm/sun8i-a23-gt90h-v4.dts +++ b/dts/src/arm/sun8i-a23-gt90h-v4.dts @@ -42,70 +42,27 @@ /dts-v1/; #include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> -#include <dt-bindings/pwm/pwm.h> +#include "sun8i-reference-design-tablet.dtsi" / { model = "Allwinner GT90H Dual Core Tablet (v4)"; compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; - - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_gt90h>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; &ehci0 { status = "okay"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-gt90h.fw"; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; status = "okay"; }; &lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; - button@600 { label = "Back"; linux,code = <KEY_BACK>; @@ -114,144 +71,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>; - vmmc-supply = <®_aldo1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin_gt90h: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_cd_pin_gt90h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - &usbphy { usb1_vbus-supply = <®_dldo1>; - status = "okay"; }; diff --git a/dts/src/arm/sun8i-a23-inet86dz.dts b/dts/src/arm/sun8i-a23-inet86dz.dts index 0f9f71b140..d4405752a4 100644 --- a/dts/src/arm/sun8i-a23-inet86dz.dts +++ b/dts/src/arm/sun8i-a23-inet86dz.dts @@ -53,6 +53,15 @@ status = "okay"; }; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-inet86dz.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + status = "okay"; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; diff --git a/dts/src/arm/sun8i-a23-polaroid-mid2407pxe03.dts b/dts/src/arm/sun8i-a23-polaroid-mid2407pxe03.dts index e3004428e7..a86cbedda3 100644 --- a/dts/src/arm/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/dts/src/arm/sun8i-a23-polaroid-mid2407pxe03.dts @@ -47,4 +47,72 @@ / { model = "Polaroid MID2407PXE03 tablet"; compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2407>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&i2c1 { + mma7660: accelerometer@4c { + reg = <0x4c>; + compatible = "fsl,mma7660"; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vddio-supply = <®_ldo_io1>; + status = "okay"; }; diff --git a/dts/src/arm/sun8i-a23-polaroid-mid2809pxe04.dts b/dts/src/arm/sun8i-a23-polaroid-mid2809pxe04.dts index 6d06e24d44..9955f85f91 100644 --- a/dts/src/arm/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/dts/src/arm/sun8i-a23-polaroid-mid2809pxe04.dts @@ -47,4 +47,55 @@ / { model = "Polaroid MID2809PXE04 tablet"; compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2809>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3670"; + firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; + touchscreen-size-x = <1660>; + touchscreen-size-y = <890>; + status = "okay"; }; diff --git a/dts/src/arm/sun8i-a23.dtsi b/dts/src/arm/sun8i-a23.dtsi index 92e6616979..54d045dab8 100644 --- a/dts/src/arm/sun8i-a23.dtsi +++ b/dts/src/arm/sun8i-a23.dtsi @@ -48,74 +48,10 @@ memory { reg = <0x40000000 0x40000000>; }; +}; - clocks { - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <6>, - <8>, <9>, <10>, - <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>; - clock-output-names = "ahb1_mipidsi", "ahb1_dma", - "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", - "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>; - clock-output-names = "mbus"; - }; - }; - - soc@01c00000 { - usb_otg: usb@01c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - }; +&ccu { + compatible = "allwinner,sun8i-a23-ccu"; }; &pio { @@ -124,3 +60,13 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; }; + +&usb_otg { + compatible = "allwinner,sun6i-a31-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/dts/src/arm/sun8i-a33-ga10h-v1.1.dts b/dts/src/arm/sun8i-a33-ga10h-v1.1.dts index 6566032400..f71159987c 100644 --- a/dts/src/arm/sun8i-a33-ga10h-v1.1.dts +++ b/dts/src/arm/sun8i-a33-ga10h-v1.1.dts @@ -47,12 +47,27 @@ / { model = "Allwinner GA10H Quad Core Tablet (v1.1)"; compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; + + aliases { + /* Make u-boot set mac-address for rtl8703as (no eeprom) */ + ethernet0 = &rtl8703as; + }; }; &ehci0 { status = "okay"; }; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-ga10h.fw"; + touchscreen-size-x = <1630>; + touchscreen-size-y = <990>; + touchscreen-inverted-y; + status = "okay"; +}; + &lradc { button@600 { label = "Back"; @@ -62,6 +77,19 @@ }; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8703as: sdio_wifi@1 { + reg = <1>; + }; +}; + &ohci0 { status = "okay"; }; diff --git a/dts/src/arm/sun8i-a33-inet-d978-rev2.dts b/dts/src/arm/sun8i-a33-inet-d978-rev2.dts new file mode 100644 index 0000000000..fb4665576d --- /dev/null +++ b/dts/src/arm/sun8i-a33-inet-d978-rev2.dts @@ -0,0 +1,108 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * Copyright 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-D978 Rev 02"; + compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart1; + }; + + chosen { + /* Delete debug UART as serial0 is the UART for bluetooth */ + /delete-property/stdout-path; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_d978>; + + home { + label = "d978:blue:home"; + gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + led_pin_d978: led_pin_d978@0 { + allwinner,pins = "PL5"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_uart { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, + <&uart1_pins_cts_rts_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a33-olinuxino.dts b/dts/src/arm/sun8i-a33-olinuxino.dts new file mode 100644 index 0000000000..9ea637e82b --- /dev/null +++ b/dts/src/arm/sun8i-a33-olinuxino.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 - Stefan Mavrodiev <stefan.mavrodiev@gmail.com> + * Olimex LTD. <support@olimex.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Olimex A33-OLinuXino"; + compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_olinuxino>; + + green { + label = "a33-olinuxino:green:usr"; + gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + led_pin_olinuxino: led_pins@0 { + allwinner,pins = "PB7"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PB3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a33.dtsi b/dts/src/arm/sun8i-a33.dtsi index 001d8402ca..fd1e1cddd4 100644 --- a/dts/src/arm/sun8i-a33.dtsi +++ b/dts/src/arm/sun8i-a33.dtsi @@ -59,107 +59,179 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-a33-display-engine"; + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + memory { reg = <0x40000000 0x80000000>; }; - clocks { - /* Dummy clock for pll11 (DDR1) until actually implemented */ - pll11: pll11_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll11"; - }; + soc@01c00000 { + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun8i-a33-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_LCD>; + reset-names = "lcd"; + status = "disabled"; - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a33-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>, - <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma","ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc", - "ahb1_sat"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>; - clock-output-names = "mbus"; + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; - }; - soc@01c00000 { crypto: crypto-engine@01c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_BUS_SS>; reset-names = "ahb"; }; - usb_otg: usb@01c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun8i-a33-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; }; - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; + be0: display-backend@01e60000 { + compatible = "allwinner,sun8i-a33-display-backend"; + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@01e70000 { + compatible = "allwinner,sun8i-a33-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + assigned-clocks = <&ccu CLK_DRC>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; }; }; }; +&ccu { + compatible = "allwinner,sun8i-a33-ccu"; +}; + &pio { compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, @@ -173,3 +245,13 @@ }; }; + +&usb_otg { + compatible = "allwinner,sun8i-a33-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts index f3b1d5f6db..06fddaae8e 100644 --- a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts +++ b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts @@ -185,7 +185,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; }; diff --git a/dts/src/arm/sun8i-h3-nanopi-neo.dts b/dts/src/arm/sun8i-h3-nanopi-neo.dts new file mode 100644 index 0000000000..3d64cafc1e --- /dev/null +++ b/dts/src/arm/sun8i-h3-nanopi-neo.dts @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 James Pettigrew <james@innovum.com.au> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-h3-orangepi-2.dts b/dts/src/arm/sun8i-h3-orangepi-2.dts index f93f5d1695..e5bcaba3e8 100644 --- a/dts/src/arm/sun8i-h3-orangepi-2.dts +++ b/dts/src/arm/sun8i-h3-orangepi-2.dts @@ -54,6 +54,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189; }; chosen { @@ -131,6 +133,14 @@ bus-width = <4>; non-removable; status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189: sdio_wifi@1 { + reg = <1>; + }; }; &pio { @@ -176,6 +186,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usb1_vbus_pin_a { allwinner,pins = "PG13"; }; diff --git a/dts/src/arm/sun8i-h3-orangepi-lite.dts b/dts/src/arm/sun8i-h3-orangepi-lite.dts new file mode 100644 index 0000000000..1550fee1ec --- /dev/null +++ b/dts/src/arm/sun8i-h3-orangepi-lite.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Lite"; + compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; + + aliases { + /* The H3 emac is not used so the wifi is ethernet0 */ + ethernet0 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-h3-orangepi-one.dts b/dts/src/arm/sun8i-h3-orangepi-one.dts index 0adf932fd9..5c9b5bfa5c 100644 --- a/dts/src/arm/sun8i-h3-orangepi-one.dts +++ b/dts/src/arm/sun8i-h3-orangepi-one.dts @@ -139,6 +139,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; diff --git a/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts new file mode 100644 index 0000000000..851fd2c2cc --- /dev/null +++ b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" + +/ { + model = "Xunlong Orange Pi PC Plus"; + compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; + + aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; diff --git a/dts/src/arm/sun8i-h3-orangepi-pc.dts b/dts/src/arm/sun8i-h3-orangepi-pc.dts index daf50b9a66..3ec971285a 100644 --- a/dts/src/arm/sun8i-h3-orangepi-pc.dts +++ b/dts/src/arm/sun8i-h3-orangepi-pc.dts @@ -161,6 +161,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; diff --git a/dts/src/arm/sun8i-h3-orangepi-plus.dts b/dts/src/arm/sun8i-h3-orangepi-plus.dts index b0cb41787e..bb585918cf 100644 --- a/dts/src/arm/sun8i-h3-orangepi-plus.dts +++ b/dts/src/arm/sun8i-h3-orangepi-plus.dts @@ -44,7 +44,7 @@ #include "sun8i-h3-orangepi-2.dts" / { - model = "Xunlong Orange Pi Plus"; + model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; reg_usb3_vbus: usb3-vbus { diff --git a/dts/src/arm/sun8i-h3-orangepi-plus2e.dts b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts new file mode 100644 index 0000000000..5851a47a30 --- /dev/null +++ b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, + * with 2G RAM and an external gbit ethernet phy. + */ + +#include "sun8i-h3-orangepi-pc-plus.dts" + +/ { + model = "Xunlong Orange Pi Plus 2E"; + compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; +}; diff --git a/dts/src/arm/sun8i-h3.dtsi b/dts/src/arm/sun8i-h3.dtsi index fdf9fdbda2..75a865406d 100644 --- a/dts/src/arm/sun8i-h3.dtsi +++ b/dts/src/arm/sun8i-h3.dtsi @@ -150,7 +150,7 @@ }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>, @@ -169,7 +169,7 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>, @@ -188,7 +188,7 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>, @@ -327,6 +327,27 @@ interrupt-controller; #interrupt-cells = <3>; + i2c0_pins: i2c0 { + allwinner,pins = "PA11", "PA12"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins: i2c1 { + allwinner,pins = "PA18", "PA19"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins: i2c2 { + allwinner,pins = "PE12", "PE13"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -367,12 +388,33 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart1_pins_a: uart1@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + uart1_pins: uart1 { + allwinner,pins = "PG6", "PG7"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart1_rts_cts_pins: uart1_rts_cts { + allwinner,pins = "PG8", "PG9"; allwinner,function = "uart1"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + uart2_pins: uart2 { + allwinner,pins = "PA0", "PA1"; + allwinner,function = "uart2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_pins: uart3 { + allwinner,pins = "PG13", "PG14"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; timer@01c20c00 { @@ -389,6 +431,14 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; + pwm: pwm@01c21400 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -441,6 +491,45 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/dts/src/arm/sun8i-q8-common.dtsi b/dts/src/arm/sun8i-q8-common.dtsi index 60fa958502..29f837a477 100644 --- a/dts/src/arm/sun8i-q8-common.dtsi +++ b/dts/src/arm/sun8i-q8-common.dtsi @@ -42,10 +42,59 @@ #include "sunxi-reference-design-tablet.dtsi" #include "sun8i-reference-design-tablet.dtsi" +/ { + aliases { + serial0 = &r_uart; + /* Make u-boot set mac-address for wifi without an eeprom */ + ethernet0 = &sdio_wifi; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + /* + * Q8 boards use various PL# pins as wifi-en. On other boards + * these may be connected to a wifi module output pin. To avoid + * short-circuits we configure these as inputs with pull-ups via + * pinctrl, instead of listing them as active-low reset-gpios. + */ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_q8>; + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + &ehci0 { status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6", "PL7", "PL11"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; diff --git a/dts/src/arm/sun8i-reference-design-tablet.dtsi b/dts/src/arm/sun8i-reference-design-tablet.dtsi index 9d90361405..08cd001436 100644 --- a/dts/src/arm/sun8i-reference-design-tablet.dtsi +++ b/dts/src/arm/sun8i-reference-design-tablet.dtsi @@ -63,6 +63,25 @@ }; }; +&i2c0 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * The gsl1680 is the only device on this bus. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen@0 { + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; @@ -88,6 +107,13 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + ts_power_pin: ts_power_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH8"; allwinner,function = "gpio_in"; diff --git a/dts/src/arm/sun9i-a80-cubieboard4.dts b/dts/src/arm/sun9i-a80-cubieboard4.dts index 1526b41c70..439847acd4 100644 --- a/dts/src/arm/sun9i-a80-cubieboard4.dts +++ b/dts/src/arm/sun9i-a80-cubieboard4.dts @@ -103,6 +103,11 @@ allwinner,drive = <SUN4I_PINCTRL_40_MA>; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_cubieboard4: led-pins@0 { allwinner,pins = "PH6", "PH17"; @@ -248,6 +253,146 @@ reg_rtc_ldo: rtc_ldo { regulator-name = "vcc-rtc-vdd1v8-io"; }; + + sw { + /* unused */ + }; + }; + }; + + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; }; }; }; diff --git a/dts/src/arm/sun9i-a80-optimus.dts b/dts/src/arm/sun9i-a80-optimus.dts index 7fd22e8886..ceb6ef15d6 100644 --- a/dts/src/arm/sun9i-a80-optimus.dts +++ b/dts/src/arm/sun9i-a80-optimus.dts @@ -112,7 +112,8 @@ }; &ehci1 { - status = "okay"; + /* Enable if HSIC peripheral is connected */ + status = "disabled"; }; &ehci2 { @@ -152,6 +153,11 @@ status = "okay"; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; @@ -320,6 +326,146 @@ reg_rtc_ldo: rtc_ldo { regulator-name = "vcc-rtc-vdd1v8-io"; }; + + sw { + /* unused */ + }; + }; + }; + + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; }; }; }; @@ -338,7 +484,9 @@ }; &usbphy2 { - status = "okay"; + phy-supply = <®_bldo4>; + /* Enable if HSIC peripheral is connected */ + status = "disabled"; }; &usbphy3 { diff --git a/dts/src/arm/sun9i-a80.dtsi b/dts/src/arm/sun9i-a80.dtsi index f68b3242b3..3c5214cbe4 100644 --- a/dts/src/arm/sun9i-a80.dtsi +++ b/dts/src/arm/sun9i-a80.dtsi @@ -148,15 +148,14 @@ /* * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This clock is by default enabled - * and clocked at 32768 Hz, from the oscillator connected - * to the AC100. It is configurable, but no such driver or - * bindings exist yet. + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. */ osc32k: osc32k_clk { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; clock-output-names = "osc32k"; }; @@ -899,8 +898,7 @@ resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; r_ir_pins: r_ir { diff --git a/dts/src/arm/tegra114.dtsi b/dts/src/arm/tegra114.dtsi index cb9393a534..8932ea3afd 100644 --- a/dts/src/arm/tegra114.dtsi +++ b/dts/src/arm/tegra114.dtsi @@ -672,7 +672,7 @@ }; usb@7d000000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d000000 0x4000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; @@ -684,7 +684,7 @@ }; phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra30-usb-phy"; + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>, @@ -708,7 +708,7 @@ }; usb@7d008000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d008000 0x4000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; @@ -720,7 +720,7 @@ }; phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra30-usb-phy"; + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>, diff --git a/dts/src/arm/tegra124-jetson-tk1.dts b/dts/src/arm/tegra124-jetson-tk1.dts index e52b82449a..53994f9fbb 100644 --- a/dts/src/arm/tegra124-jetson-tk1.dts +++ b/dts/src/arm/tegra124-jetson-tk1.dts @@ -2045,44 +2045,32 @@ thermal-zones { cpu { trips { - trip { + cpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ - }; }; mem { trips { - trip { + mem-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ - }; }; gpu { trips { - trip { + gpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ - }; }; }; }; diff --git a/dts/src/arm/tegra124.dtsi b/dts/src/arm/tegra124.dtsi index ea340f9de4..187a36c6d0 100644 --- a/dts/src/arm/tegra124.dtsi +++ b/dts/src/arm/tegra124.dtsi @@ -851,7 +851,9 @@ soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x1000>; + reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ + 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; @@ -859,6 +861,15 @@ resets = <&tegra_car 78>; reset-names = "soctherm"; #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <85>; + + #cooling-cells = <2>; + }; + }; }; dfll: clock@70110000 { @@ -1154,6 +1165,26 @@ thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + cpu_throttle_trip: throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; }; mem { @@ -1162,6 +1193,21 @@ thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; }; gpu { @@ -1170,6 +1216,26 @@ thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; }; pllx { @@ -1178,6 +1244,21 @@ thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; }; }; diff --git a/dts/src/arm/uniphier-common32.dtsi b/dts/src/arm/uniphier-common32.dtsi index 03f60ec340..8c8a85176b 100644 --- a/dts/src/arm/uniphier-common32.dtsi +++ b/dts/src/arm/uniphier-common32.dtsi @@ -1,7 +1,8 @@ /* * Device Tree Source commonly used by UniPhier ARM SoCs * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,6 +46,11 @@ /include/ "skeleton.dtsi" / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; @@ -66,7 +72,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -76,7 +82,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -86,7 +92,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -96,7 +102,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -114,6 +120,34 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -137,11 +171,26 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ + /* specify compatible in each SoC DTSI */ + }; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; }; }; }; diff --git a/dts/src/arm/uniphier-ph1-ld4-ref.dts b/dts/src/arm/uniphier-ld4-ref.dts index ec94b7a661..110031bc0e 100644 --- a/dts/src/arm/uniphier-ph1-ld4-ref.dts +++ b/dts/src/arm/uniphier-ld4-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD4 Reference Board + * Device Tree Source for UniPhier LD4 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-ld4.dtsi" +/include/ "uniphier-ld4.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD4 Reference Board"; - compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; + model = "UniPhier LD4 Reference Board"; + compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-ld4.dtsi b/dts/src/arm/uniphier-ld4.dtsi index debad7ffef..95f342c9d9 100644 --- a/dts/src/arm/uniphier-ph1-ld4.dtsi +++ b/dts/src/arm/uniphier-ld4.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD4 SoC + * Device Tree Source for UniPhier LD4 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,7 +46,7 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-ld4"; + compatible = "socionext,uniphier-ld4"; cpus { #address-cells = <1>; @@ -55,6 +56,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -65,18 +67,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; }; @@ -101,7 +91,7 @@ interrupts = <0 41 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -114,7 +104,7 @@ interrupts = <0 42 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -127,7 +117,7 @@ interrupts = <0 43 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 6>; clock-frequency = <400000>; }; @@ -140,7 +130,7 @@ interrupts = <0 44 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -151,6 +141,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb1: usb@5a810100 { @@ -160,6 +152,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; usb2: usb@5a820100 { @@ -169,6 +163,8 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; }; }; @@ -181,6 +177,31 @@ interrupts = <0 29 4>; }; +&mio_clk { + compatible = "socionext,uniphier-ld4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-ld4-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-ld4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-ld4-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-ld4-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-ld4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-ld4-reset"; +}; diff --git a/dts/src/arm/uniphier-ph1-ld6b-ref.dts b/dts/src/arm/uniphier-ld6b-ref.dts index b8134c6e09..c05d631dcf 100644 --- a/dts/src/arm/uniphier-ph1-ld6b-ref.dts +++ b/dts/src/arm/uniphier-ld6b-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD6b Reference Board + * Device Tree Source for UniPhier LD6b Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-ld6b.dtsi" +/include/ "uniphier-ld6b.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD6b Reference Board"; - compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; + model = "UniPhier LD6b Reference Board"; + compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-ld6b.dtsi b/dts/src/arm/uniphier-ld6b.dtsi index 19c107c66b..905c77d499 100644 --- a/dts/src/arm/uniphier-ph1-ld6b.dtsi +++ b/dts/src/arm/uniphier-ld6b.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD6b SoC + * Device Tree Source for UniPhier LD6b SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,14 +44,14 @@ */ /* - * PH1-LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the ProXstream2 die. - * Reuse the ProXstream2 device tree with some properties overridden. + * LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. */ -/include/ "uniphier-proxstream2.dtsi" +/include/ "uniphier-pxs2.dtsi" / { - compatible = "socionext,ph1-ld6b"; + compatible = "socionext,uniphier-ld6b"; }; /* UART3 unavailable: the pads are not wired to the package balls */ @@ -59,7 +60,7 @@ }; /* - * PH1-LD6b and ProXstream2 have completely different packages, + * LD6b and PXs2 have completely different packages, * which makes the pinctrl driver unshareable. */ &pinctrl { diff --git a/dts/src/arm/uniphier-ph1-pro4-ace.dts b/dts/src/arm/uniphier-pro4-ace.dts index d34358632b..0ab0a40c04 100644 --- a/dts/src/arm/uniphier-ph1-pro4-ace.dts +++ b/dts/src/arm/uniphier-pro4-ace.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Ace Board + * Device Tree Source for UniPhier Pro4 Ace Board * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,11 +44,11 @@ */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" / { - model = "UniPhier PH1-Pro4 Ace Board"; - compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Ace Board"; + compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-pro4-ref.dts b/dts/src/arm/uniphier-pro4-ref.dts index 95f631a3de..9e92e60d25 100644 --- a/dts/src/arm/uniphier-ph1-pro4-ref.dts +++ b/dts/src/arm/uniphier-pro4-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Reference Board + * Device Tree Source for UniPhier Pro4 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-Pro4 Reference Board"; - compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Reference Board"; + compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-pro4-sanji.dts b/dts/src/arm/uniphier-pro4-sanji.dts index 7c3a1fcc9f..dc4ea8832c 100644 --- a/dts/src/arm/uniphier-ph1-pro4-sanji.dts +++ b/dts/src/arm/uniphier-pro4-sanji.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Sanji Board + * Device Tree Source for UniPhier Pro4 Sanji Board * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,11 +44,11 @@ */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" / { - model = "UniPhier PH1-Pro4 Sanji Board"; - compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Sanji Board"; + compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-pro4.dtsi b/dts/src/arm/uniphier-pro4.dtsi index 7b9da08520..ba700267ad 100644 --- a/dts/src/arm/uniphier-ph1-pro4.dtsi +++ b/dts/src/arm/uniphier-pro4.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 SoC + * Device Tree Source for UniPhier Pro4 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,17 +46,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-pro4"; + compatible = "socionext,uniphier-pro4"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -63,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -73,18 +75,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -109,7 +99,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -122,7 +112,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -135,7 +125,7 @@ interrupts = <0 43 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -148,7 +138,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -161,7 +151,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -172,7 +162,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; @@ -183,6 +173,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb3: usb@5a810100 { @@ -192,6 +184,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; }; @@ -199,6 +193,31 @@ clock-frequency = <25000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pro4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro4-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro4-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pro4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro4-reset"; +}; diff --git a/dts/src/arm/uniphier-ph1-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi index 7e4aa2fde7..2c49c3614b 100644 --- a/dts/src/arm/uniphier-ph1-pro5.dtsi +++ b/dts/src/arm/uniphier-pro5.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro5 SoC + * Device Tree Source for UniPhier Pro5 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,17 +46,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-pro5"; + compatible = "socionext,uniphier-pro5"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -63,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -73,18 +75,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -121,7 +111,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -134,7 +124,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -147,7 +137,7 @@ interrupts = <0 43 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -160,7 +150,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -173,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -184,7 +174,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; }; @@ -193,6 +183,30 @@ clock-frequency = <20000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pro5-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro5-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro5-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro5-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pro5-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro5-reset"; +}; diff --git a/dts/src/arm/uniphier-proxstream2-gentil.dts b/dts/src/arm/uniphier-pxs2-gentil.dts index 98d895b7af..373818ace0 100644 --- a/dts/src/arm/uniphier-proxstream2-gentil.dts +++ b/dts/src/arm/uniphier-pxs2-gentil.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier ProXstream2 Gentil Board + * Device Tree Source for UniPhier PXs2 Gentil Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,11 +44,12 @@ */ /dts-v1/; -/include/ "uniphier-proxstream2.dtsi" +/include/ "uniphier-pxs2.dtsi" / { - model = "UniPhier ProXstream2 Gentil Board"; - compatible = "socionext,proxstream2-gentil", "socionext,proxstream2"; + model = "UniPhier PXs2 Gentil Board"; + compatible = "socionext,uniphier-pxs2-gentil", + "socionext,uniphier-pxs2"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-proxstream2-vodka.dts b/dts/src/arm/uniphier-pxs2-vodka.dts index 1fb8bd7bb6..51a3eacddf 100644 --- a/dts/src/arm/uniphier-proxstream2-vodka.dts +++ b/dts/src/arm/uniphier-pxs2-vodka.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier ProXstream2 Vodka Board + * Device Tree Source for UniPhier PXs2 Vodka Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,11 +44,11 @@ */ /dts-v1/; -/include/ "uniphier-proxstream2.dtsi" +/include/ "uniphier-pxs2.dtsi" / { - model = "UniPhier ProXstream2 Vodka Board"; - compatible = "socionext,proxstream2-vodka", "socionext,proxstream2"; + model = "UniPhier PXs2 Vodka Board"; + compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-proxstream2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi index d00d6f5c26..8789cd5189 100644 --- a/dts/src/arm/uniphier-proxstream2.dtsi +++ b/dts/src/arm/uniphier-pxs2.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier ProXstream2 SoC + * Device Tree Source for UniPhier PXs2 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,17 +46,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,proxstream2"; + compatible = "socionext,uniphier-pxs2"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -63,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -70,6 +72,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -77,6 +80,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -87,18 +91,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -123,7 +115,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -136,7 +128,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -149,7 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; interrupts = <0 43 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -162,7 +154,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -173,7 +165,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 45 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 8>; clock-frequency = <400000>; }; @@ -184,7 +176,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -195,7 +187,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; }; @@ -204,6 +196,30 @@ clock-frequency = <25000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pxs2-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pxs2-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pxs2-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pxs2-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pxs2-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pxs2-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pxs2-reset"; +}; diff --git a/dts/src/arm/uniphier-ph1-sld3-ref.dts b/dts/src/arm/uniphier-sld3-ref.dts index acb420492b..ac792ae07a 100644 --- a/dts/src/arm/uniphier-ph1-sld3-ref.dts +++ b/dts/src/arm/uniphier-sld3-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD3 Reference Board + * Device Tree Source for UniPhier sLD3 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-sld3.dtsi" +/include/ "uniphier-sld3.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-sLD3 Reference Board"; - compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; + model = "UniPhier sLD3 Reference Board"; + compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-sld3.dtsi b/dts/src/arm/uniphier-sld3.dtsi index 03292f4433..5fa96c939b 100644 --- a/dts/src/arm/uniphier-ph1-sld3.dtsi +++ b/dts/src/arm/uniphier-sld3.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD3 SoC + * Device Tree Source for UniPhier sLD3 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,17 +46,17 @@ /include/ "skeleton.dtsi" / { - compatible = "socionext,ph1-sld3"; + compatible = "socionext,uniphier-sld3"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -63,10 +64,16 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; @@ -79,18 +86,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; soc { @@ -139,7 +134,7 @@ status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -148,7 +143,7 @@ status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -157,7 +152,7 @@ status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -168,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -179,7 +174,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 42 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -190,7 +185,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -201,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 44 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -212,7 +207,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 45 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <400000>; }; @@ -229,6 +224,22 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -256,5 +267,21 @@ reg = <0x5a830100 0x100>; interrupts = <0 83 4>; }; + + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0xf1840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/dts/src/arm/uniphier-ph1-sld8-ref.dts b/dts/src/arm/uniphier-sld8-ref.dts index d594f40e7f..a8291f9880 100644 --- a/dts/src/arm/uniphier-ph1-sld8-ref.dts +++ b/dts/src/arm/uniphier-sld8-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD8 Reference Board + * Device Tree Source for UniPhier sLD8 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-sld8.dtsi" +/include/ "uniphier-sld8.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-sLD8 Reference Board"; - compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; + model = "UniPhier sLD8 Reference Board"; + compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; memory { device_type = "memory"; diff --git a/dts/src/arm/uniphier-ph1-sld8.dtsi b/dts/src/arm/uniphier-sld8.dtsi index 467f9d8e98..d8cf0e7e11 100644 --- a/dts/src/arm/uniphier-ph1-sld8.dtsi +++ b/dts/src/arm/uniphier-sld8.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD8 SoC + * Device Tree Source for UniPhier sLD8 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,7 +46,7 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-sld8"; + compatible = "socionext,uniphier-sld8"; cpus { #address-cells = <1>; @@ -55,6 +56,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -65,18 +67,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; }; @@ -101,7 +91,7 @@ interrupts = <0 41 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -114,7 +104,7 @@ interrupts = <0 42 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -127,7 +117,7 @@ interrupts = <0 43 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 6>; clock-frequency = <400000>; }; @@ -140,7 +130,7 @@ interrupts = <0 44 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -151,6 +141,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb1: usb@5a810100 { @@ -160,6 +152,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; usb2: usb@5a820100 { @@ -169,6 +163,8 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; }; }; @@ -180,6 +176,31 @@ interrupts = <0 29 4>; }; +&mio_clk { + compatible = "socionext,uniphier-sld8-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-sld8-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-sld8-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-sld8-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-sld8-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-sld8-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-sld8-reset"; +}; diff --git a/dts/src/arm/vf-colibri-eval-v3.dtsi b/dts/src/arm/vf-colibri-eval-v3.dtsi index a8a8e434fb..1e0b823f7e 100644 --- a/dts/src/arm/vf-colibri-eval-v3.dtsi +++ b/dts/src/arm/vf-colibri-eval-v3.dtsi @@ -53,6 +53,12 @@ panel: panel { compatible = "edt,et057090dhu"; backlight = <&bl>; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; }; reg_3v3: regulator-3v3 { @@ -91,8 +97,13 @@ &dcu0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dcu0_1>; - fsl,panel = <&panel>; status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &dspi1 { diff --git a/dts/src/arm/vf610m4.dtsi b/dts/src/arm/vf610m4.dtsi index 9ffe2eb68e..9f2c731839 100644 --- a/dts/src/arm/vf610m4.dtsi +++ b/dts/src/arm/vf610m4.dtsi @@ -42,6 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "vfxxx.dtsi" diff --git a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts index 90a84c514d..e6e3491d48 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts +++ b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts @@ -87,3 +87,14 @@ pinctrl-names = "default"; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm64/amlogic/meson-gxbb-p200.dts b/dts/src/arm64/amlogic/meson-gxbb-p200.dts index 62979076e2..03e3d76626 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-p200.dts +++ b/dts/src/arm64/amlogic/meson-gxbb-p200.dts @@ -50,3 +50,9 @@ compatible = "amlogic,p200", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P200 Development Board"; }; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi index f4f30f674b..06a34dc600 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi @@ -57,6 +57,19 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; + + usb_pwr: regulator-usb-pwrs { + compatible = "regulator-fixed"; + + regulator-name = "USB_PWR"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + /* signal name in schematic: USB_PWR_EN */ + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; /* This UART is brought out to the DB9 connector */ @@ -72,3 +85,25 @@ pinctrl-names = "default"; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi index 54bb7c7390..73f1593701 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi @@ -52,6 +52,19 @@ chosen { stdout-path = "serial0:115200n8"; }; + + usb_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; &uart_AO { @@ -60,3 +73,32 @@ pinctrl-names = "default"; }; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; +}; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_vbus>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/dts/src/arm64/amlogic/meson-gxbb.dtsi b/dts/src/arm64/amlogic/meson-gxbb.dtsi index bf6c8d0510..610e0e1c3c 100644 --- a/dts/src/arm64/amlogic/meson-gxbb.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb.dtsi @@ -45,6 +45,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/clock/gxbb-clkc.h> +#include <dt-bindings/clock/gxbb-aoclkc.h> +#include <dt-bindings/reset/gxbb-aoclkc.h> / { compatible = "amlogic,meson-gxbb"; @@ -99,6 +102,30 @@ method = "smc"; }; + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -124,6 +151,25 @@ #size-cells = <2>; ranges; + usb0_phy: phy@c0000000 { + compatible = "amlogic,meson-gxbb-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0xc0000000 0x0 0x20>; + resets = <&reset RESET_USB_OTG>; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + status = "disabled"; + }; + + usb1_phy: phy@c0000020 { + compatible = "amlogic,meson-gxbb-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0xc0000020 0x0 0x20>; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + status = "disabled"; + }; + cbus: cbus@c1100000 { compatible = "simple-bus"; reg = <0x0 0xc1100000 0x0 0x100000>; @@ -153,6 +199,27 @@ status = "disabled"; }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08650 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x086c0 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart_C: serial@8700 { compatible = "amlogic,meson-uart"; reg = <0x0 0x8700 0x0 0x14>; @@ -160,6 +227,51 @@ clocks = <&xtal>; status = "disabled"; }; + + watchdog@98d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0x098d0 0x0 0x10>; + clocks = <&xtal>; + }; + + spifc: spi@8c80 { + compatible = "amlogic,meson-gxbb-spifc"; + reg = <0x0 0x08c80 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SPI>; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x08500 0x0 0x20>; + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087c0 0x0 0x20>; + interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_C: i2c@87e0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087e0 0x0 0x20>; + interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gic: interrupt-controller@c4301000 { @@ -203,6 +315,56 @@ function = "uart_ao"; }; }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + i2c_ao_pins: i2c_ao { + mux { + groups = "i2c_sck_ao", + "i2c_sda_ao"; + function = "i2c_ao"; + }; + }; + + pwm_ao_a_3_pins: pwm_ao_a_3 { + mux { + groups = "pwm_ao_a_3"; + function = "pwm_ao_a_3"; + }; + }; + + pwm_ao_a_6_pins: pwm_ao_a_6 { + mux { + groups = "pwm_ao_a_6"; + function = "pwm_ao_a_6"; + }; + }; + + pwm_ao_a_12_pins: pwm_ao_a_12 { + mux { + groups = "pwm_ao_a_12"; + function = "pwm_ao_a_12"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; + }; + + clkc_AO: clock-controller@040 { + compatible = "amlogic,gxbb-aoclkc"; + reg = <0x0 0x00040 0x0 0x4>; + #clock-cells = <1>; + #reset-cells = <1>; }; uart_AO: serial@4c0 { @@ -212,6 +374,30 @@ clocks = <&xtal>; status = "disabled"; }; + + ir: ir@580 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x00580 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pwm_ab_AO: pwm@550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x0550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x500 0x0 0x20>; + interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_AO_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; periphs: periphs@c8834000 { @@ -251,6 +437,16 @@ }; }; + nor_pins: nor { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_cs"; + function = "nor"; + }; + }; + sdcard_pins: sdcard { mux { groups = "sdcard_d0", @@ -263,6 +459,25 @@ }; }; + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_irq_pins: sdio_irq { + mux { + groups = "sdio_irq"; + function = "sdio"; + }; + }; + uart_a_pins: uart_a { mux { groups = "uart_tx_a", @@ -287,6 +502,30 @@ }; }; + i2c_a_pins: i2c_a { + mux { + groups = "i2c_sck_a", + "i2c_sda_a"; + function = "i2c_a"; + }; + }; + + i2c_b_pins: i2c_b { + mux { + groups = "i2c_sck_b", + "i2c_sda_b"; + function = "i2c_b"; + }; + }; + + i2c_c_pins: i2c_c { + mux { + groups = "i2c_sck_c", + "i2c_sda_c"; + function = "i2c_c"; + }; + }; + eth_pins: eth_c { mux { groups = "eth_mdio", @@ -306,6 +545,55 @@ function = "eth"; }; }; + + pwm_a_x_pins: pwm_a_x { + mux { + groups = "pwm_a_x"; + function = "pwm_a_x"; + }; + }; + + pwm_a_y_pins: pwm_a_y { + mux { + groups = "pwm_a_y"; + function = "pwm_a_y"; + }; + }; + + pwm_b_pins: pwm_b { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_d_pins: pwm_d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_x_pins: pwm_f_x { + mux { + groups = "pwm_f_x"; + function = "pwm_f_x"; + }; + }; + + pwm_f_y_pins: pwm_f_y { + mux { + groups = "pwm_f_y"; + function = "pwm_f_y"; + }; + }; }; }; @@ -321,6 +609,15 @@ #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3db>; }; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; }; apb: apb@d0000000 { @@ -331,14 +628,40 @@ ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; }; + usb0: usb@c9000000 { + compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; + reg = <0x0 0xc9000000 0x0 0x40000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb@c9100000 { + compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; + reg = <0x0 0xc9100000 0x0 0x40000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&xtal>; - clock-names = "stmmaceth"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; phy-mode = "rgmii"; status = "disabled"; }; diff --git a/dts/src/arm64/apm/apm-mustang.dts b/dts/src/arm64/apm/apm-mustang.dts index b7fb5d9295..32a961c5e9 100644 --- a/dts/src/arm64/apm/apm-mustang.dts +++ b/dts/src/arm64/apm/apm-mustang.dts @@ -74,6 +74,7 @@ &xgenet { status = "ok"; + rxlos-gpios = <&sbgpio 12 1>; }; &mmc0 { diff --git a/dts/src/arm64/apm/apm-shadowcat.dtsi b/dts/src/arm64/apm/apm-shadowcat.dtsi index 1425ed4162..72720e9132 100644 --- a/dts/src/arm64/apm/apm-shadowcat.dtsi +++ b/dts/src/arm64/apm/apm-shadowcat.dtsi @@ -26,6 +26,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; + #clock-cells = <1>; + clocks = <&pmd0clk 0>; }; cpu@001 { device_type = "cpu"; @@ -34,6 +36,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; + #clock-cells = <1>; + clocks = <&pmd0clk 0>; }; cpu@100 { device_type = "cpu"; @@ -42,6 +46,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; + #clock-cells = <1>; + clocks = <&pmd1clk 0>; }; cpu@101 { device_type = "cpu"; @@ -50,6 +56,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; + #clock-cells = <1>; + clocks = <&pmd1clk 0>; }; cpu@200 { device_type = "cpu"; @@ -58,6 +66,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; + #clock-cells = <1>; + clocks = <&pmd2clk 0>; }; cpu@201 { device_type = "cpu"; @@ -66,6 +76,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; + #clock-cells = <1>; + clocks = <&pmd2clk 0>; }; cpu@300 { device_type = "cpu"; @@ -74,6 +86,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; + #clock-cells = <1>; + clocks = <&pmd3clk 0>; }; cpu@301 { device_type = "cpu"; @@ -82,6 +96,8 @@ enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; + #clock-cells = <1>; + clocks = <&pmd3clk 0>; }; xgene_L2_0: l2-cache-0 { compatible = "cache"; @@ -223,6 +239,46 @@ clock-output-names = "refclk"; }; + pmdpll: pmdpll@170000f0 { + compatible = "apm,xgene-pcppll-v2-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + reg = <0x0 0x170000f0 0x0 0x10>; + clock-output-names = "pmdpll"; + }; + + pmd0clk: pmd0clk@7e200200 { + compatible = "apm,xgene-pmd-clock"; + #clock-cells = <1>; + clocks = <&pmdpll 0>; + reg = <0x0 0x7e200200 0x0 0x10>; + clock-output-names = "pmd0clk"; + }; + + pmd1clk: pmd1clk@7e200210 { + compatible = "apm,xgene-pmd-clock"; + #clock-cells = <1>; + clocks = <&pmdpll 0>; + reg = <0x0 0x7e200210 0x0 0x10>; + clock-output-names = "pmd1clk"; + }; + + pmd2clk: pmd2clk@7e200220 { + compatible = "apm,xgene-pmd-clock"; + #clock-cells = <1>; + clocks = <&pmdpll 0>; + reg = <0x0 0x7e200220 0x0 0x10>; + clock-output-names = "pmd2clk"; + }; + + pmd3clk: pmd3clk@7e200230 { + compatible = "apm,xgene-pmd-clock"; + #clock-cells = <1>; + clocks = <&pmdpll 0>; + reg = <0x0 0x7e200230 0x0 0x10>; + clock-output-names = "pmd3clk"; + }; + socpll: socpll@17000120 { compatible = "apm,xgene-socpll-v2-clock"; #clock-cells = <1>; @@ -453,6 +509,64 @@ }; }; + pmu: pmu@78810000 { + compatible = "apm,xgene-pmu-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + reg = <0x0 0x78810000 0x0 0x1000>; + interrupts = <0x0 0x22 0x4>; + + pmul3c@7e610000 { + compatible = "apm,xgene-pmu-l3c"; + reg = <0x0 0x7e610000 0x0 0x1000>; + }; + + pmuiob@7e940000 { + compatible = "apm,xgene-pmu-iob"; + reg = <0x0 0x7e940000 0x0 0x1000>; + }; + + pmucmcb@7e710000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e710000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmcb@7e730000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e730000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e810000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e810000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmc@7e850000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e850000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e890000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e890000 0x0 0x1000>; + enable-bit-index = <2>; + }; + + pmucmc@7e8d0000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e8d0000 0x0 0x1000>; + enable-bit-index = <3>; + }; + }; + mailbox: mailbox@10540000 { compatible = "apm,xgene-slimpro-mbox"; reg = <0x0 0x10540000 0x0 0x8000>; @@ -472,6 +586,11 @@ mboxes = <&mailbox 0>; }; + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + serial0: serial@10600000 { device_type = "serial"; compatible = "ns16550"; @@ -508,10 +627,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; dma-coherent; clocks = <&pcie0clk 0>; msi-parent = <&v2m0>; @@ -533,10 +652,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; dma-coherent; clocks = <&pcie1clk 0>; msi-parent = <&v2m0>; diff --git a/dts/src/arm64/apm/apm-storm.dtsi b/dts/src/arm64/apm/apm-storm.dtsi index c29dab9d18..63be8e51ea 100644 --- a/dts/src/arm64/apm/apm-storm.dtsi +++ b/dts/src/arm64/apm/apm-storm.dtsi @@ -553,6 +553,64 @@ }; }; + pmu: pmu@78810000 { + compatible = "apm,xgene-pmu-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + reg = <0x0 0x78810000 0x0 0x1000>; + interrupts = <0x0 0x22 0x4>; + + pmul3c@7e610000 { + compatible = "apm,xgene-pmu-l3c"; + reg = <0x0 0x7e610000 0x0 0x1000>; + }; + + pmuiob@7e940000 { + compatible = "apm,xgene-pmu-iob"; + reg = <0x0 0x7e940000 0x0 0x1000>; + }; + + pmucmcb@7e710000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e710000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmcb@7e730000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e730000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e810000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e810000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmc@7e850000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e850000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e890000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e890000 0x0 0x1000>; + enable-bit-index = <2>; + }; + + pmucmc@7e8d0000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e8d0000 0x0 0x1000>; + enable-bit-index = <3>; + }; + }; + pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; @@ -569,10 +627,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; dma-coherent; clocks = <&pcie0clk 0>; msi-parent = <&msi>; @@ -594,10 +652,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; dma-coherent; clocks = <&pcie1clk 0>; msi-parent = <&msi>; @@ -619,10 +677,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; dma-coherent; clocks = <&pcie2clk 0>; msi-parent = <&msi>; @@ -644,10 +702,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; dma-coherent; clocks = <&pcie3clk 0>; msi-parent = <&msi>; @@ -669,10 +727,10 @@ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 + 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 + 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 + 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; dma-coherent; clocks = <&pcie4clk 0>; msi-parent = <&msi>; @@ -697,6 +755,11 @@ mboxes = <&mailbox 0>; }; + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + serial0: serial@1c020000 { status = "disabled"; device_type = "serial"; @@ -923,7 +986,7 @@ /* mac address will be overwritten by the bootloader */ local-mac-address = [00 00 00 00 00 00]; phy-connection-type = "rgmii"; - phy-handle = <&menet0phy>,<&menetphy>; + phy-handle = <&menetphy>,<&menet0phy>; mdio { compatible = "apm,xgene-mdio"; #address-cells = <1>; diff --git a/dts/src/arm64/broadcom/bcm283x.dtsi b/dts/src/arm64/broadcom/bcm283x.dtsi index 445624a1a1..46d46d894a 100644 --- a/dts/src/arm64/broadcom/bcm283x.dtsi +++ b/dts/src/arm64/broadcom/bcm283x.dtsi @@ -290,6 +290,8 @@ interrupts = <1 9>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk_usb>; + clock-names = "otg"; }; v3d: v3d@7ec00000 { @@ -317,5 +319,12 @@ clock-frequency = <19200000>; }; + clk_usb: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-output-names = "otg"; + clock-frequency = <480000000>; + }; }; }; diff --git a/dts/src/arm64/broadcom/ns2.dtsi b/dts/src/arm64/broadcom/ns2.dtsi index d4a12fad8a..d95dc40862 100644 --- a/dts/src/arm64/broadcom/ns2.dtsi +++ b/dts/src/arm64/broadcom/ns2.dtsi @@ -299,6 +299,14 @@ }; }; + pwm: pwm@66010000 { + compatible = "brcm,iproc-pwm"; + reg = <0x66010000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + mdio_mux_iproc: mdio-mux@6602023c { compatible = "brcm,mdio-mux-iproc"; reg = <0x6602023c 0x14>; diff --git a/dts/src/arm64/exynos/exynos7.dtsi b/dts/src/arm64/exynos/exynos7.dtsi index 162831546e..6328a66ed9 100644 --- a/dts/src/arm64/exynos/exynos7.dtsi +++ b/dts/src/arm64/exynos/exynos7.dtsi @@ -10,6 +10,7 @@ */ #include <dt-bindings/clock/exynos7-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "samsung,exynos7"; @@ -473,10 +474,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff08>, - <1 14 0xff08>, - <1 11 0xff08>, - <1 10 0xff08>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; pmu_system_controller: system-controller@105c0000 { diff --git a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts index 9d3e9fe1c8..dd9e91941d 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts +++ b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts @@ -56,12 +56,14 @@ gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; - serial0 = &lpuart0; - serial1 = &lpuart1; - serial2 = &lpuart2; - serial3 = &lpuart3; - serial4 = &lpuart4; - serial5 = &lpuart5; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; }; diff --git a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts index 40846319be..d2313e05fd 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts @@ -52,6 +52,14 @@ aliases { crypto = &crypto; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; }; diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi index a67e210e20..220ac7057d 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi @@ -247,6 +247,13 @@ bus-width = <4>; }; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = <0 144 0x4>; + big-endian; + }; + dspi0: dspi@2100000 { compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; @@ -495,10 +502,11 @@ }; sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci"; + compatible = "fsl,ls1043a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>; interrupts = <0 69 0x4>; clocks = <&clockgen 4 0>; + dma-coherent; }; msi1: msi-controller1@1571000 { diff --git a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts index e8801faca9..b0dd010979 100644 --- a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts +++ b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts @@ -57,6 +57,9 @@ serial1 = &serial1; }; + chosen { + stdout-path = "serial0:115200n8"; + }; }; &esdhc { diff --git a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts index e127f0baab..ad0ebb8a19 100644 --- a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts @@ -56,6 +56,10 @@ serial0 = &serial0; serial1 = &serial1; }; + + chosen { + stdout-path = "serial1:115200n8"; + }; }; &esdhc { diff --git a/dts/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/src/arm64/freescale/fsl-ls2080a.dtsi index e3b6034ea5..337da90bd7 100644 --- a/dts/src/arm64/freescale/fsl-ls2080a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls2080a.dtsi @@ -588,6 +588,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -612,6 +613,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -636,6 +638,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -660,6 +663,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -679,6 +683,7 @@ reg = <0x0 0x3200000 0x0 0x10000>; interrupts = <0 133 0x4>; /* Level high type */ clocks = <&clockgen 4 3>; + dma-coherent; }; sata1: sata@3210000 { @@ -687,6 +692,7 @@ reg = <0x0 0x3210000 0x0 0x10000>; interrupts = <0 136 0x4>; /* Level high type */ clocks = <&clockgen 4 3>; + dma-coherent; }; usb0: usb3@3100000 { @@ -715,4 +721,18 @@ interrupts = <0 12 4>; }; }; + + ddr1: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = <0 17 0x4>; + little-endian; + }; + + ddr2: memory-controller@1090000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1090000 0x0 0x1000>; + interrupts = <0 18 0x4>; + little-endian; + }; }; diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts index 593c7e43de..dba3c131c6 100644 --- a/dts/src/arm64/hisilicon/hi6220-hikey.dts +++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts @@ -29,16 +29,56 @@ * Reserve below regions from memory node: * * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using + * 0x05f0,1000 - 0x05f0,1fff: Reboot reason * 0x06df,f000 - 0x06df,ffff: Mailbox message data * 0x0740,f000 - 0x0740,ffff: MCU firmware section + * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, - <0x00000000 0x05f00000 0x00000000 0x00eff000>, + <0x00000000 0x05f00000 0x00000000 0x00001000>, + <0x00000000 0x05f02000 0x00000000 0x00efd000>, <0x00000000 0x06e00000 0x00000000 0x0060f000>, - <0x00000000 0x07410000 0x00000000 0x36bf0000>; + <0x00000000 0x07410000 0x00000000 0x1aaf0000>, + <0x00000000 0x22000000 0x00000000 0x1c000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@0x21f00000 { + compatible = "ramoops"; + reg = <0x0 0x21f00000 0x0 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00000000 0x08000000>; + linux,cma-default; + }; + }; + + reboot-mode-syscon@5f01000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x05f01000 0x0 0x00001000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; }; soc { @@ -55,6 +95,8 @@ }; uart1: uart@f7111000 { + assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; + assigned-clock-rates = <150000000>; status = "ok"; }; @@ -372,3 +414,43 @@ &uart3 { label = "LS-UART1"; }; + +&ade { + status = "ok"; +}; + +&dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + adv7533: adv7533@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <1 2>; + pd-gpio = <&gpio0 4 0>; + adi,dsi-lanes = <4>; + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; +}; diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi index 4f270410a5..17839db585 100644 --- a/dts/src/arm64/hisilicon/hi6220.dtsi +++ b/dts/src/arm64/hisilicon/hi6220.dtsi @@ -262,6 +262,11 @@ #clock-cells = <1>; }; + medianoc_ade: medianoc_ade@f4520000 { + compatible = "syscon"; + reg = <0x0 0xf4520000 0x0 0x4000>; + }; + stub_clock: stub_clock { compatible = "hisilicon,hi6220-stub-clk"; hisilicon,hi6220-clk-sram = <&sram>; @@ -766,6 +771,7 @@ interrupts = <0x0 0x48 0x4>; clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; bus-width = <0x8>; vmmc-supply = <&ldo19>; pinctrl-names = "default"; @@ -779,12 +785,16 @@ card-detect-delay = <200>; hisilicon,peripheral-syscon = <&ao_ctrl>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; reg = <0x0 0xf723e000 0x0 0x1000>; interrupts = <0x0 0x49 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; vqmmc-supply = <&ldo7>; vmmc-supply = <&ldo10>; bus-width = <0x4>; @@ -802,6 +812,7 @@ interrupts = <0x0 0x4a 0x4>; clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; bus-width = <0x4>; broken-cd; pinctrl-names = "default", "idle"; @@ -850,5 +861,55 @@ }; }; }; + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + status = "disabled"; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; }; }; diff --git a/dts/src/arm64/hisilicon/hip05.dtsi b/dts/src/arm64/hisilicon/hip05.dtsi index bf322ed038..4b472a302c 100644 --- a/dts/src/arm64/hisilicon/hip05.dtsi +++ b/dts/src/arm64/hisilicon/hip05.dtsi @@ -300,11 +300,6 @@ clock-frequency = <200000000>; }; - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,hip05-perisubc", "syscon"; - reg = < 0x0 0x80000000 0x0 0x10000>; - }; - uart0: uart@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/dts/src/arm64/hisilicon/hip05_hns.dtsi b/dts/src/arm64/hisilicon/hip05_hns.dtsi deleted file mode 100644 index b6a130c2e5..0000000000 --- a/dts/src/arm64/hisilicon/hip05_hns.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -soc0: soc@000000000 { - #address-cells = <2>; - #size-cells = <2>; - device_type = "soc"; - compatible = "simple-bus"; - ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; - chip-id = <0>; - - soc0_mdio0: mdio@803c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x803c0000 0x0 0x10000>; - subctrl-vbase = <&peri_c_subctrl>; - - soc0_phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - soc0_phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v1"; - mode = "6port-16rss"; - interrupt-parent = <&mbigen_dsa>; - - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x60000 - >; - - reg-names = "ppe-base","dsaf-base"; - subctrl-syscon = <&dsaf_subctrl>; - reset-field-offset = <0>; - interrupts = < - /* [14] ge fifo err 8 / xge 6**/ - 149 0x4 150 0x4 151 0x4 152 0x4 - 153 0x4 154 0x4 26 0x4 27 0x4 - 155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4 - /* [12] rcb com 4*3**/ - 0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4 - 16 0x4 17 0x4 18 0x4 19 0x4 - 22 0x4 23 0x4 24 0x4 25 0x4 - /* [8] ppe tnl 0-7***/ - 0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4 - 0x4 0x4 0x5 0x4 12 0x4 13 0x4 - /* [21] dsaf event int 3+18**/ - 128 0x4 129 0x4 130 0x4 - 0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4 - 0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4 - 0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4 - /* [4] debug rcb 2*2*/ - 0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1 - /* [256] sevice rcb 2*128*/ - 0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1 - 0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1 - 0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1 - 0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1 - 0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1 - 0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1 - 0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1 - 0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1 - 0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1 - 0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1 - 0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1 - 0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1 - 0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1 - 0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1 - 0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1 - 0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1 - 0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1 - 0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1 - 0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1 - 0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1 - 0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1 - 0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1 - 0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1 - 0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1 - 0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1 - 0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1 - 0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1 - 0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1 - 0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1 - 0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1 - 0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1 - 0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1 - 0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1 - 0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1 - 0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1 - 0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1 - 0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1 - 0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1 - 0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1 - 0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1 - 0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1 - 0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1 - 0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1 - 0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1 - 0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1 - 0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1 - 0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1 - 0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1 - 0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1 - 0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1 - 0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1 - 0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1 - 0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1 - 0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1 - 0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1 - 0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1 - 0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1 - 0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1 - 0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1 - 0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1 - 0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1 - 0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1 - 0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1 - 0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>; - buf-size = <4096>; - desc-num = <1024>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl0>; - }; - port@1 { - reg = <1>; - serdes-syscon = <&serdes_ctrl0>; - }; - port@4 { - reg = <4>; - phy-handle = <&soc0_phy0>; - serdes-syscon = <&serdes_ctrl1>; - }; - port@5 { - reg = <5>; - phy-handle = <&soc0_phy1>; - serdes-syscon = <&serdes_ctrl1>; - }; - }; - - eth0: ethernet@0{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 01 00 58]; - status = "disabled"; - dma-coherent; - }; - eth1: ethernet@1{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 01 00 59]; - status = "disabled"; - dma-coherent; - }; - eth2: ethernet@4{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 01 00 5a]; - status = "disabled"; - dma-coherent; - }; - eth3: ethernet@5{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 01 00 5b]; - status = "disabled"; - dma-coherent; - }; -}; diff --git a/dts/src/arm64/hisilicon/hip06-d03.dts b/dts/src/arm64/hisilicon/hip06-d03.dts index f3e5323e43..f54b283596 100644 --- a/dts/src/arm64/hisilicon/hip06-d03.dts +++ b/dts/src/arm64/hisilicon/hip06-d03.dts @@ -25,6 +25,34 @@ chosen { }; }; +ð0 { + status = "ok"; +}; + +ð1 { + status = "ok"; +}; + +ð2 { + status = "ok"; +}; + +ð3 { + status = "ok"; +}; + +&sas0 { + status = "ok"; +}; + +&sas1 { + status = "ok"; +}; + +&sas2 { + status = "ok"; +}; + &usb_ohci { status = "ok"; }; diff --git a/dts/src/arm64/hisilicon/hip06.dtsi b/dts/src/arm64/hisilicon/hip06.dtsi index 5927bc472f..b548763366 100644 --- a/dts/src/arm64/hisilicon/hip06.dtsi +++ b/dts/src/arm64/hisilicon/hip06.dtsi @@ -277,6 +277,39 @@ #interrupt-cells = <2>; num-pins = <2>; }; + + mbigen_sas1: intc_sas1 { + msi-parent = <&its_dsa 0x40000>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + + mbigen_sas2: intc_sas2 { + msi-parent = <&its_dsa 0x40040>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + }; + + mbigen_dsa@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + + mbigen_dsaf0: intc_dsaf0 { + msi-parent = <&its_dsa 0x40800>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <409>; + }; + + mbigen_sas0: intc-sas0 { + msi-parent = <&its_dsa 0x40900>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; }; soc { @@ -302,6 +335,338 @@ dma-coherent; status = "disabled"; }; + + peri_c_subctrl: sub_ctrl_c@60000000 { + compatible = "hisilicon,peri-subctrl","syscon"; + reg = <0 0x60000000 0x0 0x10000>; + }; + + dsa_subctrl: dsa_subctrl@c0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0x0 0xc0000000 0x0 0x10000>; + }; + + pcie_subctl: pcie_subctl@a0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0x0 0xa0000000 0x0 0x10000>; + }; + + serdes_ctrl: sds_ctrl@c2200000 { + compatible = "syscon"; + reg = <0 0xc2200000 0x0 0x80000>; + }; + + mdio@603c0000 { + compatible = "hisilicon,hns-mdio"; + reg = <0x0 0x603c0000 0x0 0x1000>; + subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + + dsaf0: dsa@c7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "hisilicon,hns-dsaf-v2"; + mode = "6port-16rss"; + reg = <0x0 0xc5000000 0x0 0x890000 + 0x0 0xc7000000 0x0 0x600000>; + reg-names = "ppe-base", "dsaf-base"; + interrupt-parent = <&mbigen_dsaf0>; + subctrl-syscon = <&dsa_subctrl>; + reset-field-offset = <0>; + interrupts = + <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, + <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, + <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, + <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, + <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, + <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, + <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, + <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, + <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, + <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, + <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, + <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, + <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, + <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, + <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, + <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, + <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, + <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, + <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, + <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, + <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, + <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, + <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, + <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, + <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, + <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, + <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, + <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, + <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, + <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, + <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, + <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, + <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, + <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, + <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, + <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, + <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, + <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, + <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, + <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, + <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, + <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, + <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, + <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, + <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, + <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, + <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, + <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, + <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, + <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, + <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, + <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, + <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, + <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, + <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, + <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, + <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, + <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, + <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, + <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, + <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, + <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, + <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, + <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, + <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, + <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, + <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, + <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, + <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, + <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, + <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, + <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, + <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, + <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, + <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, + <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, + <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, + <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, + <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, + <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, + <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, + <1340 1>, <1341 1>, <1342 1>, <1343 1>; + + desc-num = <0x400>; + buf-size = <0x1000>; + dma-coherent; + + port@0 { + reg = <0>; + serdes-syscon = <&serdes_ctrl>; + port-rst-offset = <0>; + port-mode-offset = <0>; + media-type = "fiber"; + }; + + port@1 { + reg = <1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <1>; + port-mode-offset = <1>; + media-type = "fiber"; + }; + + port@4 { + reg = <4>; + phy-handle = <&phy0>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <4>; + port-mode-offset = <2>; + media-type = "copper"; + }; + + port@5 { + reg = <5>; + phy-handle = <&phy1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <5>; + port-mode-offset = <3>; + media-type = "copper"; + }; + }; + + eth0: ethernet@4{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet@5{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth2: ethernet@0{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet@1{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + sas0: sas@c3000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xc3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&dsa_subctrl>; + ctrl-reset-reg = <0xa60>; + ctrl-reset-sts-reg = <0x5a30>; + ctrl-clock-ena-reg = <0x338>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas0>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, + <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, + <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, + <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, + <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, + <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, + <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, + <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, + <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, + <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, + <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, + <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, + <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, + <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, + <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, + <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, + <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, + <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, + <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, + <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, + <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, + <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, + <630 1>,<631 1>,<632 1>; + status = "disabled"; + }; + + sas1: sas@a2000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xa2000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + am-max-trans; + ctrl-reset-reg = <0xa18>; + ctrl-reset-sts-reg = <0x5a0c>; + ctrl-clock-ena-reg = <0x318>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas1>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, + <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, + <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, + <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, + <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, + <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, + <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, + <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, + <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, + <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, + <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, + <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, + <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, + <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, + <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, + <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, + <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, + <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, + <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, + <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, + <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, + <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, + <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>; + status = "disabled"; + }; + + sas2: sas@a3000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xa3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + ctrl-reset-reg = <0xae0>; + ctrl-reset-sts-reg = <0x5a70>; + ctrl-clock-ena-reg = <0x3a8>; + queue-count = <16>; + phy-count = <9>; + dma-coherent; + interrupt-parent = <&mbigen_sas2>; + interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, + <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, + <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, + <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, + <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, + <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, + <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, + <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, + <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, + <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, + <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, + <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, + <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, + <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, + <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, + <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, + <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, + <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, + <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, + <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, + <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, + <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, + <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, + <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, + <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, + <637 1>,<638 1>,<639 1>; + status = "disabled"; + }; }; }; diff --git a/dts/src/arm64/marvell/armada-8020.dtsi b/dts/src/arm64/marvell/armada-8020.dtsi index 3753c1c6d5..048e5cf516 100644 --- a/dts/src/arm64/marvell/armada-8020.dtsi +++ b/dts/src/arm64/marvell/armada-8020.dtsi @@ -47,6 +47,7 @@ #include "armada-ap806-dual.dtsi" #include "armada-cp110-master.dtsi" +#include "armada-cp110-slave.dtsi" / { model = "Marvell Armada 8020"; diff --git a/dts/src/arm64/marvell/armada-8040-db.dts b/dts/src/arm64/marvell/armada-8040-db.dts new file mode 100644 index 0000000000..6e6f182fb2 --- /dev/null +++ b/dts/src/arm64/marvell/armada-8040-db.dts @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for Marvell Armada 8040 Development board platform + */ + +#include "armada-8040.dtsi" + +/ { + model = "Marvell Armada 8040 DB board"; + compatible = "marvell,armada8040-db", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status = "okay"; +}; + + +/* CON5 on CP0 expansion */ +&cpm_pcie2 { + status = "okay"; +}; + +&cpm_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON4 on CP0 expansion */ +&cpm_sata0 { + status = "okay"; +}; + +/* CON9 on CP0 expansion */ +&cpm_usb3_0 { + status = "okay"; +}; + +/* CON10 on CP0 expansion */ +&cpm_usb3_1 { + status = "okay"; +}; + +/* CON5 on CP1 expansion */ +&cps_pcie2 { + status = "okay"; +}; + +&cps_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON4 on CP1 expansion */ +&cps_sata0 { + status = "okay"; +}; + +/* CON9 on CP1 expansion */ +&cps_usb3_0 { + status = "okay"; +}; + +/* CON10 on CP1 expansion */ +&cps_usb3_1 { + status = "okay"; +}; diff --git a/dts/src/arm64/marvell/armada-8040.dtsi b/dts/src/arm64/marvell/armada-8040.dtsi index 8bd0d8f8ad..9c1b28c476 100644 --- a/dts/src/arm64/marvell/armada-8040.dtsi +++ b/dts/src/arm64/marvell/armada-8040.dtsi @@ -47,6 +47,7 @@ #include "armada-ap806-quad.dtsi" #include "armada-cp110-master.dtsi" +#include "armada-cp110-slave.dtsi" / { model = "Marvell Armada 8040"; diff --git a/dts/src/arm64/marvell/armada-ap806.dtsi b/dts/src/arm64/marvell/armada-ap806.dtsi index c2a6745f16..7b6136182a 100644 --- a/dts/src/arm64/marvell/armada-ap806.dtsi +++ b/dts/src/arm64/marvell/armada-ap806.dtsi @@ -128,6 +128,12 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + odmi: odmi@300000 { compatible = "marvell,odmi-controller"; interrupt-controller; @@ -140,6 +146,14 @@ marvell,spi-base = <128>, <136>, <144>, <152>; }; + pic: interrupt-controller@3f0100 { + compatible = "marvell,armada-8k-pic"; + reg = <0x3f0100 0x10>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + xor@400000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x400000 0x1000>, diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi index da31bbbbb5..e5e3ed678b 100644 --- a/dts/src/arm64/marvell/armada-cp110-master.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi @@ -176,6 +176,7 @@ #interrupt-cells = <1>; device_type = "pci"; dma-coherent; + msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; ranges = @@ -201,6 +202,7 @@ #interrupt-cells = <1>; device_type = "pci"; dma-coherent; + msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; ranges = @@ -227,6 +229,7 @@ #interrupt-cells = <1>; device_type = "pci"; dma-coherent; + msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; ranges = diff --git a/dts/src/arm64/marvell/armada-cp110-slave.dtsi b/dts/src/arm64/marvell/armada-cp110-slave.dtsi new file mode 100644 index 0000000000..842fb33328 --- /dev/null +++ b/dts/src/arm64/marvell/armada-cp110-slave.dtsi @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for Marvell Armada CP110 Slave. + */ + +/ { + cp110-slave { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + config-space { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0xf4000000 0x2000000>; + + cps_syscon0: system-controller@440000 { + compatible = "marvell,cp110-system-controller0", + "syscon"; + reg = <0x440000 0x1000>; + #clock-cells = <2>; + core-clock-output-names = + "cps-apll", "cps-ppv2-core", "cps-eip", + "cps-core", "cps-nand-core"; + gate-clock-output-names = + "cps-audio", "cps-communit", "cps-nand", + "cps-ppv2", "cps-sdio", "cps-mg-domain", + "cps-mg-core", "cps-xor1", "cps-xor0", + "cps-gop-dp", "none", "cps-pcie_x10", + "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", + "cps-sata", "cps-sata-usb", "cps-main", + "cps-sd-mmc", "none", "none", + "cps-slow-io", "cps-usb3h0", "cps-usb3h1", + "cps-usb3dev", "cps-eip150", "cps-eip197"; + }; + + cps_sata0: sata@540000 { + compatible = "marvell,armada-8k-ahci"; + reg = <0x540000 0x30000>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 15>; + status = "disabled"; + }; + + cps_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + dma-coherent; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 22>; + status = "disabled"; + }; + + cps_usb3_1: usb3@510000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x510000 0x4000>; + dma-coherent; + interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 23>; + status = "disabled"; + }; + + cps_xor0: xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, + <0x6b0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cps_syscon0 1 8>; + }; + + cps_xor1: xor@6c0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6c0000 0x1000>, + <0x6d0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cps_syscon0 1 7>; + }; + + cps_spi0: spi@700600 { + compatible = "marvell,armada-380-spi"; + reg = <0x700600 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <1>; + clocks = <&cps_syscon0 0 3>; + status = "disabled"; + }; + + cps_spi1: spi@700680 { + compatible = "marvell,armada-380-spi"; + reg = <0x700680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <2>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + + cps_i2c0: i2c@701000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + + cps_i2c1: i2c@701100 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + }; + + cps_pcie0: pcie@f4600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4600000 0 0x10000>, + <0 0xfaf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <1>; + clocks = <&cps_syscon0 1 13>; + status = "disabled"; + }; + + cps_pcie1: pcie@f4620000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4620000 0 0x10000>, + <0 0xfbf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes = <1>; + clocks = <&cps_syscon0 1 11>; + status = "disabled"; + }; + + cps_pcie2: pcie@f4640000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4640000 0 0x10000>, + <0 0xfcf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes = <1>; + clocks = <&cps_syscon0 1 12>; + status = "disabled"; + }; + }; +}; diff --git a/dts/src/arm64/marvell/berlin4ct.dtsi b/dts/src/arm64/marvell/berlin4ct.dtsi index 099ad93bb4..85c23facb9 100644 --- a/dts/src/arm64/marvell/berlin4ct.dtsi +++ b/dts/src/arm64/marvell/berlin4ct.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -76,6 +77,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -84,6 +86,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -92,9 +95,14 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; + l2: cache { + compatible = "cache"; + }; + idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { @@ -115,7 +123,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, @@ -279,7 +287,6 @@ reg = <0x4000 0x100>; clocks = <&osc>; interrupts = <1>; - status = "disabled"; }; wdt2: watchdog@5000 { @@ -287,7 +294,6 @@ reg = <0x5000 0x100>; clocks = <&osc>; interrupts = <2>; - status = "disabled"; }; sm_gpio0: gpio@8000 { diff --git a/dts/src/arm64/mediatek/mt8173-evb.dts b/dts/src/arm64/mediatek/mt8173-evb.dts index 7453a47b30..2a7f731c77 100644 --- a/dts/src/arm64/mediatek/mt8173-evb.dts +++ b/dts/src/arm64/mediatek/mt8173-evb.dts @@ -42,6 +42,44 @@ gpio = <&pio 130 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; +}; + +&cec { + status = "okay"; +}; + +&dpi0 { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; }; &i2c1 { diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi index 10f638f4e7..1c71e25660 100644 --- a/dts/src/arm64/mediatek/mt8173.dtsi +++ b/dts/src/arm64/mediatek/mt8173.dtsi @@ -254,6 +254,16 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + hdmi_pin: xxx { + + /*hdmi htplg pin*/ + pins1 { + pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; + input-enable; + bias-pull-down; + }; + }; + i2c0_pins_a: i2c0 { pins1 { pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, @@ -341,6 +351,14 @@ clock-names = "spi", "wrap"; }; + cec: cec@10013000 { + compatible = "mediatek,mt8173-cec"; + reg = <0 0x10013000 0 0xbc>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + vpu: vpu@10020000 { compatible = "mediatek,mt8173-vpu"; reg = <0 0x10020000 0 0x30000>, @@ -383,6 +401,19 @@ #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt8173-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + mipi_tx0: mipi-dphy@10215000 { compatible = "mediatek,mt8173-mipi-tx"; reg = <0 0x10215000 0 0x1000>; @@ -577,6 +608,14 @@ status = "disabled"; }; + hdmiddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + reg = <0 0x11012000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C5>; + clock-names = "ddc-i2c"; + }; + i2c6: i2c@11013000 { compatible = "mediatek,mt8173-i2c"; reg = <0 0x11013000 0 0x70>, @@ -885,6 +924,12 @@ <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; status = "disabled"; + + port { + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; }; pwm0: pwm@1401e000 { @@ -942,6 +987,38 @@ clocks = <&mmsys CLK_MM_DISP_OD>; }; + hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0 0x14025000 0 0x400>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; + assigned-clock-parents = <&hdmi_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + }; + }; + larb4: larb@14027000 { compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14027000 0 0x1000>; diff --git a/dts/src/arm64/nvidia/tegra132.dtsi b/dts/src/arm64/nvidia/tegra132.dtsi index 2013f89160..3f3a46a4bd 100644 --- a/dts/src/arm64/nvidia/tegra132.dtsi +++ b/dts/src/arm64/nvidia/tegra132.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/tegra124-soctherm.h> / { compatible = "nvidia,tegra132", "nvidia,tegra124"; @@ -727,8 +728,10 @@ }; soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x1000>; + compatible = "nvidia,tegra132-soctherm"; + reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ + 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ + reg-names = "soctherm-reg", "ccroc-reg"; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; @@ -736,6 +739,118 @@ resets = <&tegra_car 78>; reset-names = "soctherm"; #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; + + #cooling-cells = <2>; + }; + }; + }; + + thermal-zones { + cpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <102000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + mem { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + gpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + pllx { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; }; ahub@70300000 { diff --git a/dts/src/arm64/nvidia/tegra210-smaug.dts b/dts/src/arm64/nvidia/tegra210-smaug.dts index 431266a48e..c2becb603e 100644 --- a/dts/src/arm64/nvidia/tegra210-smaug.dts +++ b/dts/src/arm64/nvidia/tegra210-smaug.dts @@ -27,6 +27,12 @@ reg = <0x0 0x80000000 0x0 0xc0000000>; }; + host1x@50000000 { + dpaux: dpaux@545c0000 { + status = "okay"; + }; + }; + pinmux: pinmux@700008d4 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1556,6 +1562,46 @@ }; }; + i2c@7000d100 { + status = "okay"; + clock-frequency = <400000>; + + nau8825@1a { + compatible = "nuvoton,nau8825"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>; + clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; + clock-names = "mclk"; + + nuvoton,jkdet-enable; + nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>; + nuvoton,vref-impedance = <2>; + nuvoton,micbias-voltage = <6>; + nuvoton,sar-threshold-num = <4>; + nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; + nuvoton,sar-hysteresis = <1>; + nuvoton,sar-voltage = <0>; + nuvoton,sar-compare-time = <0>; + nuvoton,sar-sampling-time = <0>; + nuvoton,short-key-debounce = <2>; + nuvoton,jack-insert-debounce = <7>; + nuvoton,jack-eject-debounce = <7>; + status = "okay"; + }; + + audio-codec@2d { + compatible = "realtek,rt5677"; + reg = <0x2d>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>; + realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; @@ -1568,12 +1614,81 @@ status = "okay"; }; + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; + phy-names = "usb2-0", "usb3-0"; + + dvddio-pex-supply = <&avddio_1v05>; + hvddio-pex-supply = <&pp1800>; + avdd-usb-supply = <&pp3300>; + avdd-pll-utmip-supply = <&pp1800>; + avdd-pll-uerefe-supply = <&pp1050_avdd>; + dvdd-pex-pll-supply = <&avddio_1v05>; + hvdd-pex-pll-e-supply = <&pp1800>; + + status = "okay"; + }; + + padctl@7009f000 { + status = "okay"; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-6 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "okay"; + vbus-supply = <&usbc_vbus>; + mode = "otg"; + }; + + usb3-0 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + }; + }; + sdhci@700b0600 { bus-width = <8>; non-removable; status = "okay"; }; + aconnect@702c0000 { + status = "okay"; + + dma@702e2000 { + status = "okay"; + }; + + agic@702f9000 { + status = "okay"; + }; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -1646,6 +1761,11 @@ }; }; + max98357a { + compatible = "maxim,max98357a"; + status = "okay"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/dts/src/arm64/nvidia/tegra210.dtsi b/dts/src/arm64/nvidia/tegra210.dtsi index c4cfdcf60d..46045fe719 100644 --- a/dts/src/arm64/nvidia/tegra210.dtsi +++ b/dts/src/arm64/nvidia/tegra210.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/memory/tegra210-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/tegra124-soctherm.h> / { compatible = "nvidia,tegra210"; @@ -34,6 +35,7 @@ clock-names = "dpaux", "parent"; resets = <&tegra_car 207>; reset-names = "dpaux"; + power-domains = <&pd_sor>; status = "disabled"; state_dpaux1_aux: pinmux-aux { @@ -108,6 +110,7 @@ clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_sor>; nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ status = "disabled"; @@ -137,6 +140,7 @@ clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 82>; reset-names = "dsi"; + power-domains = <&pd_sor>; nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ status = "disabled"; @@ -178,6 +182,7 @@ pinctrl-1 = <&state_dpaux_i2c>; pinctrl-2 = <&state_dpaux_off>; pinctrl-names = "aux", "i2c", "off"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -197,6 +202,7 @@ pinctrl-1 = <&state_dpaux1_i2c>; pinctrl-2 = <&state_dpaux1_off>; pinctrl-names = "aux", "i2c", "off"; + power-domains = <&pd_sor>; status = "disabled"; }; @@ -209,6 +215,7 @@ clock-names = "dpaux", "parent"; resets = <&tegra_car 181>; reset-names = "dpaux"; + power-domains = <&pd_sor>; status = "disabled"; state_dpaux_aux: pinmux-aux { @@ -325,7 +332,7 @@ }; gpio: gpio@6000d000 { - compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; + compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, @@ -648,27 +655,41 @@ #power-domain-cells = <0>; }; + pd_sor: sor { + clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_SOR1>, + <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_DSIA>, + <&tegra_car TEGRA210_CLK_DSIB>, + <&tegra_car TEGRA210_CLK_DPAUX>, + <&tegra_car TEGRA210_CLK_DPAUX1>, + <&tegra_car TEGRA210_CLK_MIPI_CAL>; + resets = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_SOR1>, + <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_DSIA>, + <&tegra_car TEGRA210_CLK_DSIB>, + <&tegra_car TEGRA210_CLK_DPAUX>, + <&tegra_car TEGRA210_CLK_DPAUX1>, + <&tegra_car TEGRA210_CLK_MIPI_CAL>; + #power-domain-cells = <0>; + }; + pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - clock-names = "xusb-ss"; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - reset-names = "xusb-ss"; #power-domain-cells = <0>; }; pd_xusbdev: xusbb { clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; - clock-names = "xusb-dev"; resets = <&tegra_car 95>; - reset-names = "xusb-dev"; #power-domain-cells = <0>; }; pd_xusbhost: xusbc { clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - clock-names = "xusb-host"; resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - reset-names = "xusb-host"; #power-domain-cells = <0>; }; }; @@ -948,6 +969,7 @@ reg = <0x0 0x700e3000 0x0 0x100>; clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; clock-names = "mipi-cal"; + power-domains = <&pd_sor>; #nvidia,mipi-calibrate-cells = <1>; }; @@ -961,6 +983,50 @@ #size-cells = <1>; ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; status = "disabled"; + + adma: dma@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x702e2000 0x2000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: agic@702f9000 { + compatible = "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x702f9000 0x2000>, + <0x702fa000 0x2000>; + interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA210_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; }; spi@70410000 { @@ -1094,4 +1160,130 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; }; + + soctherm: thermal-sensor@700e2000 { + compatible = "nvidia,tegra210-soctherm"; + reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ + 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, + <&tegra_car TEGRA210_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <85>; + + #cooling-cells = <2>; + }; + }; + }; + + thermal-zones { + cpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature = <102500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <98500>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + mem { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + gpu { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + + gpu_throttle_trip: throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + pllx { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature = <103000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; }; diff --git a/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi index ee828a8a82..e1e6c6b5c4 100644 --- a/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi +++ b/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi @@ -24,4 +24,52 @@ bias-pull-up; }; }; + + adv7533_int_active: adv533_int_active { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_int_suspend: adv7533_int_suspend { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + adv7533_switch_active: adv7533_switch_active { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_switch_suspend: adv7533_switch_suspend { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; }; diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi index 18639bc0a5..bb062b5471 100644 --- a/dts/src/arm64/qcom/apq8016-sbc.dtsi +++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi @@ -63,6 +63,47 @@ /* On High speed expansion */ label = "HS-I2C2"; status = "okay"; + + adv_bridge: bridge@39 { + status = "okay"; + + compatible = "adi,adv7533"; + reg = <0x39>; + + interrupt-parent = <&msmgpio>; + interrupts = <31 2>; + + adi,dsi-lanes = <4>; + + pd-gpios = <&msmgpio 32 0>; + + avdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; }; i2c@78ba000 { @@ -180,6 +221,36 @@ lpass@07708000 { status = "okay"; }; + + mdss@1a00000 { + status = "okay"; + + mdp@1a01000 { + status = "okay"; + }; + + dsi@1a98000 { + status = "okay"; + + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + + dsi-phy@1a98300 { + status = "okay"; + + vddio-supply = <&pm8916_l6>; + }; + }; }; usb2513 { @@ -194,6 +265,17 @@ pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; }; &smd_rpm_regulators { diff --git a/dts/src/arm64/qcom/apq8096-db820c-pins.dtsi b/dts/src/arm64/qcom/apq8096-db820c-pins.dtsi new file mode 100644 index 0000000000..24552f19b3 --- /dev/null +++ b/dts/src/arm64/qcom/apq8096-db820c-pins.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&msmgpio { + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/dts/src/arm64/qcom/apq8096-db820c.dts b/dts/src/arm64/qcom/apq8096-db820c.dts new file mode 100644 index 0000000000..230e9c8484 --- /dev/null +++ b/dts/src/arm64/qcom/apq8096-db820c.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "apq8096-db820c.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DB820c"; + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; +}; diff --git a/dts/src/arm64/qcom/apq8096-db820c.dtsi b/dts/src/arm64/qcom/apq8096-db820c.dtsi new file mode 100644 index 0000000000..afb218cffc --- /dev/null +++ b/dts/src/arm64/qcom/apq8096-db820c.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8996.dtsi" +#include "apq8096-db820c-pins.dtsi" + +/ { + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp2_uart2; + i2c0 = &blsp1_i2c2; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c0; + spi0 = &blsp1_spi0; + spi1 = &blsp2_spi5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@75b0000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_2pins_default>; + pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + }; + + serial@75b1000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_4pins_default>; + pinctrl-1 = <&blsp2_uart2_4pins_sleep>; + }; + + i2c@07577000 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; + }; + + i2c@075b6000 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; + }; + + spi@07575000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + + i2c@075b5000 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; + }; + + spi@075ba000{ + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; + }; + + sdhci@74a4900 { + /* External SD card */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + cd-gpios = <&msmgpio 38 0x1>; + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi index 11bdc24cfc..466ca5705c 100644 --- a/dts/src/arm64/qcom/msm8916.dtsi +++ b/dts/src/arm64/qcom/msm8916.dtsi @@ -86,6 +86,11 @@ reg = <0x0 0x89300000 0x0 0x600000>; no-map; }; + + mba_mem: mba@8ea00000 { + no-map; + reg = <0 0x8ea00000 0 0x100000>; + }; }; cpus { @@ -155,6 +160,49 @@ interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -187,10 +235,11 @@ }; firmware { - scm { + scm: scm { compatible = "qcom,scm"; clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "core", "bus", "iface"; + #reset-cells = <1>; }; }; @@ -228,6 +277,11 @@ reg = <0x1905000 0x20000>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x1937000 0x30000>; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; @@ -483,7 +537,7 @@ compatible = "qcom,ci-hdrc"; reg = <0x78d9000 0x400>; dr_mode = "peripheral"; - interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb_otg>; status = "disabled"; }; @@ -491,7 +545,7 @@ usb_host: ehci@78d9000 { compatible = "qcom,ehci-host"; reg = <0x78d9000 0x400>; - interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb_otg>; status = "disabled"; }; @@ -499,8 +553,8 @@ usb_otg: phy@78d9000 { compatible = "qcom,usb-otg-snps"; reg = <0x78d9000 0x400>; - interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>, - <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; qcom,vdd-levels = <500000 1000000 1320000>; qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>; @@ -594,7 +648,7 @@ <0x200a000 0x002100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; @@ -609,6 +663,144 @@ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; + + qfprom: qfprom@5c000 { + compatible = "qcom,qfprom"; + reg = <0x5c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0xd0 0x8>; + }; + tsens_calsel: calsel@ec { + reg = <0xec 0x4>; + }; + }; + + tsens: thermal-sensor@4a8000 { + compatible = "qcom,msm8916-tsens"; + reg = <0x4a8000 0x2000>; + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + #thermal-sensor-cells = <1>; + }; + + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "vsync_clk"; + + interrupts = <0 72 0>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk", + "vsync_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 0>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, + <&dsi_phy0 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core_clk", + "iface_clk", + "bus_clk", + "byte_clk", + "pixel_clk", + "core_clk"; + phys = <&dsi_phy0>; + phy-names = "dsi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: dsi-phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x1a98300 0xd4>, + <0x1a98500 0x280>, + <0x1a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + }; + }; }; smd { @@ -657,6 +849,88 @@ }; }; }; + + hexagon-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + wcnss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 0 13>; + qcom,ipc-6 = <&apcs 0 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "msm8916-pins.dtsi" diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi index 55ec3e8326..338f82a7fd 100644 --- a/dts/src/arm64/qcom/msm8996.dtsi +++ b/dts/src/arm64/qcom/msm8996.dtsi @@ -97,6 +97,92 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -181,6 +267,12 @@ status = "disabled"; }; + tsens0: thermal-sensor@4a8000 { + compatible = "qcom,msm8996-tsens"; + reg = <0x4a8000 0x2000>; + #thermal-sensor-cells = <1>; + }; + blsp2_uart1: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; @@ -339,7 +431,7 @@ <0x400a000 0x002100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; diff --git a/dts/src/arm64/renesas/r8a7795-h3ulcb.dts b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts new file mode 100644 index 0000000000..bcb11a8683 --- /dev/null +++ b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts @@ -0,0 +1,328 @@ +/* + * Device Tree Source for the H3ULCB board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Renesas H3ULCB board based on r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; + + sdhi0_pins_3v3: sd0_3v3 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_1v8: sd0_1v8 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk-multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins_3v3>; + pinctrl-1 = <&sdhi0_pins_1v8>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <900>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <900>; + txen-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/r8a7795-salvator-x.dts b/dts/src/arm64/renesas/r8a7795-salvator-x.dts index 98f02631a0..b1eab6876f 100644 --- a/dts/src/arm64/renesas/r8a7795-salvator-x.dts +++ b/dts/src/arm64/renesas/r8a7795-salvator-x.dts @@ -110,6 +110,17 @@ 1800000 0>; }; + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + audio_clkout: audio_clkout { /* * This is same as <&rcar_sound 0> @@ -135,6 +146,52 @@ sound-dai = <&ak4613>; }; }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; }; &extal_clk { @@ -172,6 +229,11 @@ function = "avb"; }; + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -193,6 +255,11 @@ function = "audio_clk"; }; + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + usb1_pins: usb1 { groups = "usb1"; function = "usb1"; @@ -369,6 +436,14 @@ status = "okay"; }; +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + &usb2_phy1 { pinctrl-0 = <&usb1_pins>; pinctrl-names = "default"; @@ -383,6 +458,10 @@ status = "okay"; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -391,6 +470,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -399,6 +482,10 @@ status = "okay"; }; +&hsusb { + status = "okay"; +}; + &pcie_bus_clk { clock-frequency = <100000000>; status = "okay"; diff --git a/dts/src/arm64/renesas/r8a7795.dtsi b/dts/src/arm64/renesas/r8a7795.dtsi index b902356873..8c15040f25 100644 --- a/dts/src/arm64/renesas/r8a7795.dtsi +++ b/dts/src/arm64/renesas/r8a7795.dtsi @@ -328,7 +328,8 @@ }; audma0: dma-controller@ec700000 { - compatible = "renesas,rcar-dmac"; + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; reg = <0 0xec700000 0 0x10000>; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH @@ -360,7 +361,8 @@ }; audma1: dma-controller@ec720000 { - compatible = "renesas,rcar-dmac"; + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; reg = <0 0xec720000 0 0x10000>; interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH @@ -1098,6 +1100,7 @@ reg = <0 0xee100000 0 0x2000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1107,6 +1110,7 @@ reg = <0 0xee120000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1116,8 +1120,8 @@ reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - cap-mmc-highspeed; status = "disabled"; }; @@ -1126,8 +1130,8 @@ reg = <0 0xee160000 0 0x2000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - cap-mmc-highspeed; status = "disabled"; }; @@ -1224,6 +1228,23 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7795"; reg = <0 0xfe000000 0 0x80000>; @@ -1273,5 +1294,252 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvb1>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpf2: fcp@fe952000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe952000 0 0x200>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi1>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + vspi2: vsp@fe9c0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9c0000 0 0x8000>; + interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi2>; + }; + + fcpvi2: fcp@fe9cf000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9cf000 0 0x200>; + clocks = <&cpg CPG_MOD 609>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x4000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x4000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x4000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd2>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + vspd3: vsp@fea38000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea38000 0 0x4000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd3>; + }; + + fcpvd3: fcp@fea3f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea3f000 0 0x200>; + clocks = <&cpg CPG_MOD 600>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf1>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf2>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_hdmi1: endpoint { + }; + }; + port@3 { + reg = <3>; + du_out_lvds0: endpoint { + }; + }; + }; + }; }; }; diff --git a/dts/src/arm64/renesas/r8a7796-salvator-x.dts b/dts/src/arm64/renesas/r8a7796-salvator-x.dts index e72be3856d..13db7d61c2 100644 --- a/dts/src/arm64/renesas/r8a7796-salvator-x.dts +++ b/dts/src/arm64/renesas/r8a7796-salvator-x.dts @@ -31,11 +31,27 @@ }; }; +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/dts/src/arm64/renesas/r8a7796.dtsi b/dts/src/arm64/renesas/r8a7796.dtsi index 1edf82440d..9217da9835 100644 --- a/dts/src/arm64/renesas/r8a7796.dtsi +++ b/dts/src/arm64/renesas/r8a7796.dtsi @@ -107,6 +107,123 @@ status = "disabled"; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7796"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; diff --git a/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts new file mode 100644 index 0000000000..5797933ef8 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2016 Matthias Brugger <mbrugger@suse.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3368.dtsi" + +/ { + model = "Rockchip Orion R68"; + compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + wakeup-source; + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + label = "GPIO Power"; + linux,code = <KEY_POWER>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + red { + gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + label = "orion:red:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + default-state = "on"; + }; + + blue { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "orion:blue:led"; + pinctrl-names = "default"; + pinctrl-0 = <&stby_pwren>; + default-state = "off"; + }; + }; + + vcc_18: vcc18-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + /* supplies both host and otg */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_io: vcc-io-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sd: vcc-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vccio_sd: vcc-io-sd-regulator { + compatible = "regulator-fixed"; + regulator-name= "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vccio_wl: vccio-wl-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vdd_10: vdd-10-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&emmc_pwrseq>; + mmc-hs200-1_2v; + mmc-hs200-1_8v; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 12 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + /* rtc_int is not connected */ + }; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + stby_pwren: stby-pwren { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_ctl: led-ctl { + rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <2 6 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <2 7 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <2 8 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + clock-frequency = <50000000>; + clock-freq-min-max = <400000 50000000>; + cap-sd-highspeed; + card-detect-delay = <200>; + keep-power-in-suspend; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3368-r88.dts b/dts/src/arm64/rockchip/rk3368-r88.dts index 82a32e5591..eed1ef6669 100644 --- a/dts/src/arm64/rockchip/rk3368-r88.dts +++ b/dts/src/arm64/rockchip/rk3368-r88.dts @@ -248,7 +248,6 @@ &sdio0 { assigned-clocks = <&cru SCLK_SDIO0>; assigned-clock-parents = <&cru PLL_CPLL>; - broken-cd; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; diff --git a/dts/src/arm64/rockchip/rk3368.dtsi b/dts/src/arm64/rockchip/rk3368.dtsi index 4f44d1191b..0fcb2147c9 100644 --- a/dts/src/arm64/rockchip/rk3368.dtsi +++ b/dts/src/arm64/rockchip/rk3368.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> #include <dt-bindings/thermal/thermal.h> / { @@ -641,6 +642,15 @@ compatible = "rockchip,rk3368-pmu-io-voltage-domain"; status = "disabled"; }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; }; cru: clock-controller@ff760000 { diff --git a/dts/src/arm64/rockchip/rk3399-evb.dts b/dts/src/arm64/rockchip/rk3399-evb.dts index d33aa06d46..8e82497925 100644 --- a/dts/src/arm64/rockchip/rk3399-evb.dts +++ b/dts/src/arm64/rockchip/rk3399-evb.dts @@ -49,6 +49,13 @@ compatible = "rockchip,rk3399-evb", "rockchip,rk3399", "google,rk3399evb-rev2"; + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + vdd_center: vdd-center { compatible = "pwm-regulator"; pwms = <&pwm3 0 25000 0>; @@ -69,18 +76,61 @@ regulator-max-microvolt = <3300000>; }; + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc5v0_sys>; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_phy"; regulator-always-on; regulator-boot-on; }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + }; &emmc_phy { status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + &pwm0 { status = "okay"; }; @@ -101,6 +151,36 @@ status = "okay"; }; +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn>; + status = "disabled"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { status = "okay"; }; @@ -133,4 +213,11 @@ <1 18 RK_FUNC_GPIO &pcfg_pull_down>; }; }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 25 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi index a6dd623a88..b65c193dc6 100644 --- a/dts/src/arm64/rockchip/rk3399.dtsi +++ b/dts/src/arm64/rockchip/rk3399.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/power/rk3399-power.h> #include <dt-bindings/thermal/thermal.h> / { @@ -152,6 +153,16 @@ }; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -159,10 +170,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; xin24m: xin24m { @@ -181,8 +192,8 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -191,19 +202,39 @@ dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; }; }; + gmac: ethernet@fe300000 { + compatible = "rockchip,rk3399-gmac"; + reg = <0x0 0xfe300000 0x0 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, + <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + power-domains = <&power RK3399_PD_GMAC>; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + sdio0: dwmmc@fe310000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -216,7 +247,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -228,7 +259,7 @@ sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; @@ -241,19 +272,60 @@ status = "disabled"; }; + pcie0: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie"; + reg = <0x0 0xf8000000 0x0 0x2000000>, + <0x0 0xfd000000 0x0 0x1000000>; + reg-names = "axi-base", "apb-base"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + bus-range = <0x0 0x1>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "legacy", "client"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + msi-map = <0x0 &its 0x0 0x1000>; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe"; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; + phys = <&u2phy0_host>; + phy-names = "usb"; status = "disabled"; }; usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -262,16 +334,18 @@ usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; + phys = <&u2phy1_host>; + phy-names = "usb"; status = "disabled"; }; usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -279,7 +353,7 @@ gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -290,12 +364,34 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; }; i2c1: i2c@ff110000 { @@ -305,7 +401,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -320,7 +416,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -335,7 +431,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -350,7 +446,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -365,7 +461,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -380,7 +476,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -393,7 +489,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -406,7 +502,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -419,7 +515,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -432,7 +528,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -445,7 +541,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -458,7 +554,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -471,7 +567,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -484,7 +580,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -497,7 +593,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -577,7 +673,7 @@ tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <750000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; @@ -594,6 +690,203 @@ status = "disabled"; }; + qos_gmac: qos@ffa5c000 { + compatible = "syscon"; + reg = <0x0 0xffa5c000 0x0 0x20>; + }; + + qos_hdcp: qos@ffa90000 { + compatible = "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_isp0_m0: qos@ffaa0000 { + compatible = "syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_isp0_m1: qos@ffaa0080 { + compatible = "syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_isp1_m0: qos@ffaa8000 { + compatible = "syscon"; + reg = <0x0 0xffaa8000 0x0 0x20>; + }; + + qos_isp1_m1: qos@ffaa8080 { + compatible = "syscon"; + reg = <0x0 0xffaa8080 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + qos_vop_big_r: qos@ffac8000 { + compatible = "syscon"; + reg = <0x0 0xffac8000 0x0 0x20>; + }; + + qos_vop_big_w: qos@ffac8080 { + compatible = "syscon"; + reg = <0x0 0xffac8080 0x0 0x20>; + }; + + qos_vop_little: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_gpu: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + pmu: power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + /* + * Note: RK3399 supports 6 voltage domains including VD_CORE_L, + * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. + * Some of the power domains are grouped together for every + * voltage domain. + * The detail contents as below. + */ + power: power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + pd_iep@RK3399_PD_IEP { + reg = <RK3399_PD_IEP>; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + }; + pd_rga@RK3399_PD_RGA { + reg = <RK3399_PD_RGA>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + }; + pd_vcodec@RK3399_PD_VCODEC { + reg = <RK3399_PD_VCODEC>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + }; + pd_vdu@RK3399_PD_VDU { + reg = <RK3399_PD_VDU>; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + }; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3399_PD_GPU { + reg = <RK3399_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + pd_gmac@RK3399_PD_GMAC { + reg = <RK3399_PD_GMAC>; + clocks = <&cru ACLK_GMAC>; + pm_qos = <&qos_gmac>; + }; + pd_vio@RK3399_PD_VIO { + reg = <RK3399_PD_VIO>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdcp@RK3399_PD_HDCP { + reg = <RK3399_PD_HDCP>; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + }; + pd_isp0@RK3399_PD_ISP0 { + reg = <RK3399_PD_ISP0>; + clocks = <&cru ACLK_ISP0>, + <&cru HCLK_ISP0>; + pm_qos = <&qos_isp0_m0>, + <&qos_isp0_m1>; + }; + pd_isp1@RK3399_PD_ISP1 { + reg = <RK3399_PD_ISP1>; + clocks = <&cru ACLK_ISP1>, + <&cru HCLK_ISP1>; + pm_qos = <&qos_isp1_m0>, + <&qos_isp1_m1>; + }; + pd_tcpc0@RK3399_PD_TCPC0 { + reg = <RK3399_PD_TCPD0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + pd_tcpc1@RK3399_PD_TCPC1 { + reg = <RK3399_PD_TCPD1>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; + pd_vo@RK3399_PD_VO { + reg = <RK3399_PD_VO>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vopb@RK3399_PD_VOPB { + reg = <RK3399_PD_VOPB>; + clocks = <&cru ACLK_VOP0>, + <&cru HCLK_VOP0>; + pm_qos = <&qos_vop_big_r>, + <&qos_vop_big_w>; + }; + pd_vopl@RK3399_PD_VOPL { + reg = <RK3399_PD_VOPL>; + clocks = <&cru ACLK_VOP1>, + <&cru HCLK_VOP1>; + pm_qos = <&qos_vop_little>; + }; + }; + }; + }; + }; + pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; @@ -611,7 +904,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -624,7 +917,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -639,7 +932,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -654,7 +947,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -669,7 +962,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -721,6 +1014,35 @@ status = "disabled"; }; + efuse0: efuse@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE1024NS>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpub_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage@18 { + reg = <0x18 0x1>; + }; + center_leakage: center-leakage@19 { + reg = <0x19 0x1>; + }; + cpul_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + logic_leakage: logic-leakage@1b { + reg = <0x1b 0x1>; + }; + wafer_info: wafer-info@1c { + reg = <0x1c 0x1>; + }; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; @@ -741,7 +1063,7 @@ <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; assigned-clock-rates = <594000000>, <800000000>, @@ -749,7 +1071,7 @@ <150000000>, <75000000>, <37500000>, <100000000>, <100000000>, - <50000000>, + <50000000>, <600000000>, <100000000>, <50000000>; }; @@ -764,6 +1086,40 @@ status = "disabled"; }; + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@e460 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe460 0x10>; + clocks = <&cru SCLK_USB2PHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy1_480m"; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + emmc_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; @@ -772,19 +1128,85 @@ #phy-cells = <0>; status = "disabled"; }; + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + #phy-cells = <0>; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + status = "disabled"; + }; }; - watchdog@ff840000 { + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + rockchip,typec-conn-dir = <0xe580 0 16>; + rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,external-psm = <0xe588 14 30>; + rockchip,pipe-status = <0xe5c0 0 0>; + status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + rockchip,typec-conn-dir = <0xe58c 0 16>; + rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,external-psm = <0xe594 14 30>; + rockchip,pipe-status = <0xe5c0 16 16>; + status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + watchdog@ff848000 { compatible = "snps,dw-wdt"; - reg = <0x0 0xff840000 0x0 0x100>; + reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -792,7 +1214,7 @@ spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -806,7 +1228,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -819,7 +1241,7 @@ i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -832,7 +1254,7 @@ i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -852,7 +1274,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -865,7 +1287,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -878,7 +1300,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -891,7 +1313,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -904,7 +1326,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -955,6 +1377,72 @@ drive-strength = <13>; }; + clock { + clk_32k: clk-32k { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + /* mac_txclk */ + <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxclk */ + <3 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ + <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <3 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 7 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxd3 */ + <3 3 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd2 */ + <3 2 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd2 */ + <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = + /* mac_mdio */ + <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxer */ + <3 10 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <3 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 7 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = @@ -1326,5 +1814,18 @@ <1 14 RK_FUNC_1 &pcfg_pull_none>; }; }; + + pcie { + pcie_clkreqn: pci-clkreqn { + rockchip,pins = + <2 26 RK_FUNC_2 &pcfg_pull_none>; + }; + + pcie_clkreqnb: pci-clkreqnb { + rockchip,pins = + <4 24 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; }; diff --git a/dts/src/arm64/socionext/uniphier-ld11-ref.dts b/dts/src/arm64/socionext/uniphier-ld11-ref.dts new file mode 100644 index 0000000000..7168cf818a --- /dev/null +++ b/dts/src/arm64/socionext/uniphier-ld11-ref.dts @@ -0,0 +1,100 @@ +/* + * Device Tree Source for UniPhier LD11 Reference Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ld11.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD11 Reference Board"; + compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/dts/src/arm64/socionext/uniphier-ld11.dtsi b/dts/src/arm64/socionext/uniphier-ld11.dtsi new file mode 100644 index 0000000000..3eb4c42ce7 --- /dev/null +++ b/dts/src/arm64/socionext/uniphier-ld11.dtsi @@ -0,0 +1,338 @@ +/* + * Device Tree Source for UniPhier LD11 SoC + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + +/ { + compatible = "socionext,uniphier-ld11"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&peri_clk 8>; + clock-frequency = <100000>; + }; + + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld11-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld11-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 243 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 244 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 245 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; + }; + + mioctrl@5b3e0000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x5b3e0000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + resets = <&sys_rst 7>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld11-pinctrl"; + }; + }; + + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ + <0x5fe40000 0x80000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 4>; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/dts/src/arm64/socionext/uniphier-ph1-ld20-ref.dts b/dts/src/arm64/socionext/uniphier-ld20-ref.dts index 2adad8c8cd..609162a1a3 100644 --- a/dts/src/arm64/socionext/uniphier-ph1-ld20-ref.dts +++ b/dts/src/arm64/socionext/uniphier-ld20-ref.dts @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD20 Reference Board + * Device Tree Source for UniPhier LD20 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,13 +44,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-ld20.dtsi" +/include/ "uniphier-ld20.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD20 Reference Board"; - compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; + model = "UniPhier LD20 Reference Board"; + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; memory { device_type = "memory"; diff --git a/dts/src/arm64/socionext/uniphier-ph1-ld20.dtsi b/dts/src/arm64/socionext/uniphier-ld20.dtsi index d73bdc8c91..08fd7cf776 100644 --- a/dts/src/arm64/socionext/uniphier-ph1-ld20.dtsi +++ b/dts/src/arm64/socionext/uniphier-ld20.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD20 SoC + * Device Tree Source for UniPhier LD20 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -45,7 +46,7 @@ /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ / { - compatible = "socionext,ph1-ld20"; + compatible = "socionext,uniphier-ld20"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; @@ -113,18 +114,6 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <58820000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; timer { @@ -148,7 +137,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -158,7 +147,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -168,7 +157,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -178,7 +167,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; i2c0: i2c@58780000 { @@ -190,7 +179,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -203,7 +192,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -213,7 +202,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <400000>; }; @@ -226,7 +215,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -239,7 +228,7 @@ interrupts = <0 45 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 8>; clock-frequency = <100000>; }; @@ -249,7 +238,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -259,6 +248,8 @@ reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59800000 { @@ -266,12 +257,45 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld20-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld20-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; + }; + soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { - compatible = "socionext,uniphier-ld20-pinctrl"; + compatible = "socionext,uniphier-ld20-pinctrl"; }; }; @@ -283,6 +307,22 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld20-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/dts/src/arm64/xilinx/zynqmp-ep108.dts b/dts/src/arm64/xilinx/zynqmp-ep108.dts index acb0527fdc..358089687a 100644 --- a/dts/src/arm64/xilinx/zynqmp-ep108.dts +++ b/dts/src/arm64/xilinx/zynqmp-ep108.dts @@ -29,7 +29,7 @@ memory { device_type = "memory"; - reg = <0x0 0x0 0x40000000>; + reg = <0x0 0x0 0x0 0x40000000>; }; }; diff --git a/dts/src/arm64/xilinx/zynqmp.dtsi b/dts/src/arm64/xilinx/zynqmp.dtsi index 3e2e51fbd2..68a908334c 100644 --- a/dts/src/arm64/xilinx/zynqmp.dtsi +++ b/dts/src/arm64/xilinx/zynqmp.dtsi @@ -14,7 +14,7 @@ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; cpus { #address-cells = <1>; @@ -51,6 +51,7 @@ pmu { compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, @@ -75,15 +76,15 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf902f000 0x2000>, + <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, - <0x0 0xf906f000 0x2000>; + <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; @@ -93,14 +94,14 @@ amba: amba { compatible = "simple-bus"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; - reg = <0x0 0xff060000 0x1000>; + reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; @@ -111,7 +112,7 @@ compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; - reg = <0x0 0xff070000 0x1000>; + reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; @@ -123,7 +124,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; - reg = <0x0 0xff0b0000 0x1000>; + reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; @@ -134,7 +135,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; - reg = <0x0 0xff0c0000 0x1000>; + reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; @@ -145,7 +146,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; - reg = <0x0 0xff0d0000 0x1000>; + reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; @@ -156,7 +157,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; - reg = <0x0 0xff0e0000 0x1000>; + reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; @@ -170,7 +171,7 @@ interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; - reg = <0x0 0xff0a0000 0x1000>; + reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { @@ -178,7 +179,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; - reg = <0x0 0xff020000 0x1000>; + reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; @@ -188,15 +189,54 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; - reg = <0x0 0xff030000 0x1000>; + reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; + pcie: pcie@fd0e0000 { + compatible = "xlnx,nwl-pcie-2.11"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + msi-controller; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <0 118 4>, + <0 117 4>, + <0 116 4>, + <0 115 4>, /* MSI_1 [63...32] */ + <0 114 4>; /* MSI_0 [31...0] */ + interrupt-names = "misc", "dummy", "intx", + "msi1", "msi0"; + msi-parent = <&pcie>; + reg = <0x0 0xfd0e0000 0x0 0x1000>, + <0x0 0xfd480000 0x0 0x1000>, + <0x80 0x00000000 0x0 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 + 0xe0000000 0x00000000 0x10000000 + /* non-prefetchable memory */ + 0x43000000 0x00000006 0x00000000 0x00000006 + 0x00000000 0x00000002 0x00000000>; + /* prefetchable memory */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; - reg = <0x0 0xfd0c0000 0x2000>; + reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; @@ -206,7 +246,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; - reg = <0x0 0xff160000 0x1000>; + reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; @@ -215,13 +255,13 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; - reg = <0x0 0xff170000 0x1000>; + reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; - reg = <0x0 0xfd800000 0x20000>; + reg = <0x0 0xfd800000 0x0 0x20000>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 157 4>, @@ -236,7 +276,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; - reg = <0x0 0xff040000 0x1000>; + reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -247,7 +287,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; - reg = <0x0 0xff050000 0x1000>; + reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -258,7 +298,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; - reg = <0x0 0xff110000 0x1000>; + reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; @@ -267,7 +307,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; - reg = <0x0 0xff120000 0x1000>; + reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; @@ -276,7 +316,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; - reg = <0x0 0xff130000 0x1000>; + reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; @@ -285,7 +325,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; - reg = <0x0 0xff140000 0x1000>; + reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; @@ -294,7 +334,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; - reg = <0x0 0xff000000 0x1000>; + reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; @@ -303,7 +343,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; - reg = <0x0 0xff010000 0x1000>; + reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; @@ -312,7 +352,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x40000>; + reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; @@ -321,7 +361,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x40000>; + reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; @@ -329,8 +369,8 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; - reg = <0x0 0xfd4d0000 0x1000>; + interrupts = <0 113 1>; + reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; diff --git a/dts/src/arm64/zte/zx296718-evb.dts b/dts/src/arm64/zte/zx296718-evb.dts new file mode 100644 index 0000000000..e164ff6de5 --- /dev/null +++ b/dts/src/arm64/zte/zx296718-evb.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2016 ZTE Corporation. + * Copyright 2016 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "zx296718.dtsi" + +/ { + model = "ZTE zx296718 evaluation board"; + compatible = "zte,zx296718-evb", "zte,zx296718"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm64/zte/zx296718.dtsi b/dts/src/arm64/zte/zx296718.dtsi new file mode 100644 index 0000000000..a223066f24 --- /dev/null +++ b/dts/src/arm64/zte/zx296718.dtsi @@ -0,0 +1,292 @@ +/* + * Copyright 2016 ZTE Corporation. + * Copyright 2016 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "zte,zx296718"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + clk24k: clk-24k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000>; + clock-output-names = "rtcclk"; + }; + + osc32k: clk-osc32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "osc32k"; + }; + + osc12m: clk-osc12m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + clock-output-names = "osc12m"; + }; + + osc24m: clk-osc24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc24m"; + }; + + osc25m: clk-osc25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc25m"; + }; + + osc60m: clk-osc60m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = "osc60m"; + }; + + osc99m: clk-osc99m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <99000000>; + clock-output-names = "osc99m"; + }; + + osc125m: clk-osc125m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "osc125m"; + }; + + osc198m: clk-osc198m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <198000000>; + clock-output-names = "osc198m"; + }; + + pll_audio: clk-pll-884m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <884000000>; + clock-output-names = "pll_audio"; + }; + + pll_ddr: clk-pll-932m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <932000000>; + clock-output-names = "pll_ddr"; + }; + + pll_hsic: clk-pll-960m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <960000000>; + clock-output-names = "pll_hsic"; + }; + + pll_mac: clk-pll-1000m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + clock-output-names = "pll_mac"; + }; + + pll_vga: clk-pll-1073m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1073000000>; + clock-output-names = "pll_vga"; + }; + + pll_mm0: clk-pll-1188m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1188000000>; + clock-output-names = "pll_mm0"; + }; + + pll_mm1: clk-pll-1296m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1296000000>; + clock-output-names = "pll_mm1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@2a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + #redistributor-regions = <6>; + redistributor-stride = <0x0 0x40000>; + interrupt-controller; + reg = <0x02a00000 0x10000>, + <0x02b00000 0x20000>, + <0x02b20000 0x20000>, + <0x02b40000 0x20000>, + <0x02b60000 0x20000>, + <0x02b80000 0x20000>, + <0x02ba0000 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; + }; + + uart0: uart@11f000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x001feffe>; + reg = <0x11f000 0x1000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24m>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dma: dma-controller@1460000 { + compatible = "zte,zx296702-dma"; + reg = <0x01460000 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24m>; + clock-names = "dmaclk"; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <32>; + }; + + sysctrl: sysctrl@1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm3368-netgear-cvg834g.dts b/dts/src/mips/brcm/bcm3368-netgear-cvg834g.dts new file mode 100644 index 0000000000..2f2e80fdcd --- /dev/null +++ b/dts/src/mips/brcm/bcm3368-netgear-cvg834g.dts @@ -0,0 +1,22 @@ +/dts-v1/; + +/include/ "bcm3368.dtsi" + +/ { + compatible = "netgear,cvg834g", "brcm,bcm3368"; + model = "NETGEAR CVG834G"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm3368.dtsi b/dts/src/mips/brcm/bcm3368.dtsi new file mode 100644 index 0000000000..bee855cb80 --- /dev/null +++ b/dts/src/mips/brcm/bcm3368.dtsi @@ -0,0 +1,101 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm3368"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <150000000>; + + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + ubus { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges; + + periph_cntl: syscon@fff8c000 { + compatible = "syscon"; + reg = <0xfff8c000 0xc>; + native-endian; + }; + + reboot: syscon-reboot@fff8c008 { + compatible = "syscon-reboot"; + regmap = <&periph_cntl>; + offset = <0x8>; + mask = <0x1>; + }; + + periph_intc: interrupt-controller@fff8c00c { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0xfff8c00c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + uart0: serial@fff8c100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfff8c100 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <2>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + uart1: serial@fff8c120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfff8c120 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <3>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm63268-comtrend-vr-3032u.dts b/dts/src/mips/brcm/bcm63268-comtrend-vr-3032u.dts new file mode 100644 index 0000000000..430d35ca33 --- /dev/null +++ b/dts/src/mips/brcm/bcm63268-comtrend-vr-3032u.dts @@ -0,0 +1,108 @@ +/dts-v1/; + +/include/ "bcm63268.dtsi" + +/ { + compatible = "comtrend,vr-3032u", "brcm,bcm63268"; + model = "Comtrend VR-3032u"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x04000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; +}; + +&leds0 { + status = "ok"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + + led@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + /* GPHY0 Speed 0 */ + }; + led@1 { + reg = <1>; + brcm,hardware-controlled; + brcm,link-signal-sources = <1>; + /* GPHY0 Speed 1 */ + }; + led@2 { + reg = <2>; + active-low; + label = "vr-3032u:red:inet"; + }; + led@3 { + reg = <3>; + active-low; + label = "vr-3032u:green:dsl"; + }; + led@4 { + reg = <4>; + active-low; + label = "vr-3032u:green:usb"; + }; + led@7 { + reg = <7>; + active-low; + label = "vr-3032u:green:wps"; + }; + led@8 { + reg = <8>; + active-low; + label = "vr-3032u:green:inet"; + }; + led@9 { + reg = <9>; + brcm,hardware-controlled; + /* EPHY0 Activity */ + }; + led@10 { + reg = <10>; + brcm,hardware-controlled; + /* EPHY1 Activity */ + }; + led@11 { + reg = <11>; + brcm,hardware-controlled; + /* EPHY2 Activity */ + }; + led@12 { + reg = <12>; + brcm,hardware-controlled; + /* GPHY0 Activity */ + }; + led@13 { + reg = <13>; + brcm,hardware-controlled; + /* EPHY0 Speed */ + }; + led@14 { + reg = <14>; + brcm,hardware-controlled; + /* EPHY1 Speed */ + }; + led@15 { + reg = <15>; + brcm,hardware-controlled; + /* EPHY2 Speed */ + }; + led@20 { + reg = <20>; + active-low; + label = "vr-3032u:green:power"; + default-state = "on"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm63268.dtsi b/dts/src/mips/brcm/bcm63268.dtsi new file mode 100644 index 0000000000..7e6bf2cc02 --- /dev/null +++ b/dts/src/mips/brcm/bcm63268.dtsi @@ -0,0 +1,134 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm63268"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <200000000>; + + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + ubus { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges; + + periph_cntl: syscon@10000000 { + compatible = "syscon"; + reg = <0x10000000 0x14>; + native-endian; + }; + + reboot: syscon-reboot@10000008 { + compatible = "syscon-reboot"; + regmap = <&periph_cntl>; + offset = <0x8>; + mask = <0x1>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x20>, + <0x10000040 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + uart0: serial@10000180 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000180 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <5>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + uart1: serial@100001a0 { + compatible = "brcm,bcm6345-uart"; + reg = <0x100001a0 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <34>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + leds0: led-controller@10001900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + + status = "disabled"; + }; + + ehci: usb@10002500 { + compatible = "brcm,bcm63268-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + big-endian; + + interrupt-parent = <&periph_intc>; + interrupts = <10>; + + status = "disabled"; + }; + + ohci: usb@10002600 { + compatible = "brcm,bcm63268-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + big-endian; + no-big-frame-no; + + interrupt-parent = <&periph_intc>; + interrupts = <9>; + + status = "disabled"; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm96358nb4ser.dts b/dts/src/mips/brcm/bcm6358-neufbox4-sercomm.dts index f412117972..702eae2a22 100644 --- a/dts/src/mips/brcm/bcm96358nb4ser.dts +++ b/dts/src/mips/brcm/bcm6358-neufbox4-sercomm.dts @@ -12,6 +12,7 @@ }; chosen { + bootargs = "console=ttyS0,115200"; stdout-path = &uart0; }; }; diff --git a/dts/src/mips/brcm/bcm6362-neufbox6-sercomm.dts b/dts/src/mips/brcm/bcm6362-neufbox6-sercomm.dts new file mode 100644 index 0000000000..480f2a5bf1 --- /dev/null +++ b/dts/src/mips/brcm/bcm6362-neufbox6-sercomm.dts @@ -0,0 +1,22 @@ +/dts-v1/; + +/include/ "bcm6362.dtsi" + +/ { + compatible = "sfr,nb6-ser", "brcm,bcm6362"; + model = "SFR NeufBox 6 (Sercomm)"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm6362.dtsi b/dts/src/mips/brcm/bcm6362.dtsi new file mode 100644 index 0000000000..c507da594f --- /dev/null +++ b/dts/src/mips/brcm/bcm6362.dtsi @@ -0,0 +1,134 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6362"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <200000000>; + + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + ubus { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges; + + periph_cntl: syscon@10000000 { + compatible = "syscon"; + reg = <0x10000000 0x14>; + native-endian; + }; + + reboot: syscon-reboot@10000008 { + compatible = "syscon-reboot"; + regmap = <&periph_cntl>; + offset = <0x8>; + mask = <0x1>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <3>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <4>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + leds0: led-controller@10001900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + + status = "disabled"; + }; + + ehci: usb@10002500 { + compatible = "brcm,bcm6362-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + big-endian; + + interrupt-parent = <&periph_intc>; + interrupts = <10>; + + status = "disabled"; + }; + + ohci: usb@10002600 { + compatible = "brcm,bcm6362-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + big-endian; + no-big-frame-no; + + interrupt-parent = <&periph_intc>; + interrupts = <9>; + + status = "disabled"; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm7125.dtsi b/dts/src/mips/brcm/bcm7125.dtsi index 550e1d9e3e..bbd00f65ce 100644 --- a/dts/src/mips/brcm/bcm7125.dtsi +++ b/dts/src/mips/brcm/bcm7125.dtsi @@ -26,7 +26,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -40,6 +40,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -49,7 +55,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@441400 { + periph_intc: interrupt-controller@441400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x441400 0x30>, <0x441600 0x30>; @@ -60,7 +66,7 @@ interrupts = <2>, <3>; }; - sun_l2_intc: sun_l2_intc@401800 { + sun_l2_intc: interrupt-controller@401800 { compatible = "brcm,l2-intc"; reg = <0x401800 0x30>; interrupt-controller; @@ -81,7 +87,7 @@ "avd_0", "jtag_0"; }; - upg_irq0_intc: upg_irq0_intc@406780 { + upg_irq0_intc: interrupt-controller@406780 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; @@ -183,6 +189,26 @@ status = "disabled"; }; + pwma: pwm@406580 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406580 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 18>; + }; + ehci0: usb@488300 { compatible = "brcm,bcm7125-ehci", "generic-ehci"; reg = <0x488300 0x100>; diff --git a/dts/src/mips/brcm/bcm7346.dtsi b/dts/src/mips/brcm/bcm7346.dtsi index ec959061d5..4bbcc95f1c 100644 --- a/dts/src/mips/brcm/bcm7346.dtsi +++ b/dts/src/mips/brcm/bcm7346.dtsi @@ -26,7 +26,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -40,6 +40,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -49,7 +55,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@411400 { + periph_intc: interrupt-controller@411400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x411400 0x30>, <0x411600 0x30>; @@ -60,7 +66,7 @@ interrupts = <2>, <3>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -81,7 +87,7 @@ "jtag_0", "svd_0"; }; - upg_irq0_intc: upg_irq0_intc@406780 { + upg_irq0_intc: interrupt-controller@406780 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; @@ -96,7 +102,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { + upg_aon_irq0_intc: interrupt-controller@408b80 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x408b80 0x8>; @@ -210,6 +216,59 @@ status = "disabled"; }; + pwma: pwm@406580 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406580 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + pwmb: pwm@406800 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406800 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408440 { + compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <53>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 16>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <27 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -313,6 +372,26 @@ status = "disabled"; }; + hif_l2_intc: interrupt-controller@411000 { + compatible = "brcm,l2-intc"; + reg = <0x411000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <30>; + }; + + nand: nand@412800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x412800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + }; + sata: sata@181000 { compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; @@ -352,5 +431,13 @@ #phy-cells = <0>; }; }; + + sdhci0: sdhci@413500 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x413500 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <85>; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm7358.dtsi b/dts/src/mips/brcm/bcm7358.dtsi index ca57fb5eb1..3e42535c8d 100644 --- a/dts/src/mips/brcm/bcm7358.dtsi +++ b/dts/src/mips/brcm/bcm7358.dtsi @@ -20,7 +20,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -34,6 +34,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -43,7 +49,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@411400 { + periph_intc: interrupt-controller@411400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x411400 0x30>; @@ -54,7 +60,7 @@ interrupts = <2>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -75,7 +81,7 @@ "avd_0", "jtag_0"; }; - upg_irq0_intc: upg_irq0_intc@406600 { + upg_irq0_intc: interrupt-controller@406600 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406600 0x8>; @@ -90,7 +96,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { + upg_aon_irq0_intc: interrupt-controller@408b80 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x408b80 0x8>; @@ -194,6 +200,59 @@ status = "disabled"; }; + pwma: pwm@406400 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406400 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + pwmb: pwm@406700 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406700 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408240 { + compatible = "brcm,l2-intc"; + reg = <0x408240 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <50>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -239,5 +298,25 @@ interrupts = <66>; status = "disabled"; }; + + hif_l2_intc: interrupt-controller@411000 { + compatible = "brcm,l2-intc"; + reg = <0x411000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <30>; + }; + + nand: nand@412800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x412800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm7360.dtsi b/dts/src/mips/brcm/bcm7360.dtsi index 1c0c3d438c..112a5571c5 100644 --- a/dts/src/mips/brcm/bcm7360.dtsi +++ b/dts/src/mips/brcm/bcm7360.dtsi @@ -20,7 +20,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -34,6 +34,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -43,7 +49,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@411400 { + periph_intc: interrupt-controller@411400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x411400 0x30>; @@ -54,7 +60,7 @@ interrupts = <2>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -75,7 +81,7 @@ "avd_0", "jtag_0"; }; - upg_irq0_intc: upg_irq0_intc@406600 { + upg_irq0_intc: interrupt-controller@406600 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406600 0x8>; @@ -90,7 +96,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { + upg_aon_irq0_intc: interrupt-controller@408b80 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x408b80 0x8>; @@ -194,6 +200,51 @@ status = "disabled"; }; + pwma: pwm@406400 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406400 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408440 { + compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <50>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -240,6 +291,26 @@ status = "disabled"; }; + hif_l2_intc: interrupt-controller@411000 { + compatible = "brcm,l2-intc"; + reg = <0x411000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <30>; + }; + + nand: nand@412800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x412800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + }; + sata: sata@181000 { compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; @@ -279,5 +350,13 @@ #phy-cells = <0>; }; }; + + sdhci0: sdhci@410000 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x410000 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <82>; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm7362.dtsi b/dts/src/mips/brcm/bcm7362.dtsi index 6b4713add4..34abfb0b07 100644 --- a/dts/src/mips/brcm/bcm7362.dtsi +++ b/dts/src/mips/brcm/bcm7362.dtsi @@ -26,7 +26,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -40,6 +40,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -49,7 +55,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@411400 { + periph_intc: interrupt-controller@411400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x411400 0x30>, <0x411600 0x30>; @@ -60,7 +66,7 @@ interrupts = <2>, <3>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -81,7 +87,7 @@ "avd_0", "jtag_0"; }; - upg_irq0_intc: upg_irq0_intc@406600 { + upg_irq0_intc: interrupt-controller@406600 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406600 0x8>; @@ -96,7 +102,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { + upg_aon_irq0_intc: interrupt-controller@408b80 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x408b80 0x8>; @@ -190,6 +196,51 @@ status = "disabled"; }; + pwma: pwm@406400 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406400 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408440 { + compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <50>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406500 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406500 0xa0>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 29 4>; + }; + + upg_gio_aon: gpio@408c00 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x408c00 0x60>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <21 32 2>; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -236,6 +287,26 @@ status = "disabled"; }; + hif_l2_intc: interrupt-controller@411000 { + compatible = "brcm,l2-intc"; + reg = <0x411000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <30>; + }; + + nand: nand@412800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x412800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + }; + sata: sata@181000 { compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; @@ -275,5 +346,13 @@ #phy-cells = <0>; }; }; + + sdhci0: sdhci@410000 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x410000 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <82>; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm7420.dtsi b/dts/src/mips/brcm/bcm7420.dtsi index 0586bf6625..b143723c67 100644 --- a/dts/src/mips/brcm/bcm7420.dtsi +++ b/dts/src/mips/brcm/bcm7420.dtsi @@ -26,7 +26,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -40,6 +40,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -49,7 +55,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@441400 { + periph_intc: interrupt-controller@441400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x441400 0x30>, <0x441600 0x30>; @@ -60,7 +66,7 @@ interrupts = <2>, <3>; }; - sun_l2_intc: sun_l2_intc@401800 { + sun_l2_intc: interrupt-controller@401800 { compatible = "brcm,l2-intc"; reg = <0x401800 0x30>; interrupt-controller; @@ -82,7 +88,7 @@ "jtag_0"; }; - upg_irq0_intc: upg_irq0_intc@406780 { + upg_irq0_intc: interrupt-controller@406780 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; @@ -191,6 +197,34 @@ status = "disabled"; }; + pwma: pwm@406580 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406580 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + pwmb: pwm@406880 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406880 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 27>; + }; + enet0: ethernet@468000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/dts/src/mips/brcm/bcm7425.dtsi b/dts/src/mips/brcm/bcm7425.dtsi index c1c15edaf8..2488d2f61f 100644 --- a/dts/src/mips/brcm/bcm7425.dtsi +++ b/dts/src/mips/brcm/bcm7425.dtsi @@ -26,7 +26,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -40,6 +40,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -49,7 +55,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@41a400 { + periph_intc: interrupt-controller@41a400 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x41a400 0x30>, <0x41a600 0x30>; @@ -60,7 +66,7 @@ interrupts = <2>, <3>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -83,7 +89,7 @@ "vice_0"; }; - upg_irq0_intc: upg_irq0_intc@406780 { + upg_irq0_intc: interrupt-controller@406780 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; @@ -98,7 +104,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@409480 { + upg_aon_irq0_intc: interrupt-controller@409480 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x409480 0x8>; @@ -209,6 +215,59 @@ status = "disabled"; }; + pwma: pwm@406580 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406580 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + pwmb: pwm@406800 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406800 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408440 { + compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <49>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 21>; + }; + + upg_gio_aon: gpio@4094c0 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x4094c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -312,6 +371,26 @@ status = "disabled"; }; + hif_l2_intc: interrupt-controller@41a000 { + compatible = "brcm,l2-intc"; + reg = <0x41a000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <24>; + }; + + nand: nand@41b800 { + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand"; + reg = <0x41b800 0x400>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>; + status = "disabled"; + }; + sata: sata@181000 { compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; @@ -351,5 +430,25 @@ #phy-cells = <0>; }; }; + + sdhci0: sdhci@419000 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x419000 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <43>; + sd-uhs-sdr50; + mmc-hs200-1_8v; + status = "disabled"; + }; + + sdhci1: sdhci@419200 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x419200 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <44>; + sd-uhs-sdr50; + mmc-hs200-1_8v; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm7435.dtsi b/dts/src/mips/brcm/bcm7435.dtsi index a874d3a0e2..19fa259b96 100644 --- a/dts/src/mips/brcm/bcm7435.dtsi +++ b/dts/src/mips/brcm/bcm7435.dtsi @@ -38,7 +38,7 @@ uart0 = &uart0; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -52,6 +52,12 @@ #clock-cells = <0>; clock-frequency = <81000000>; }; + + upg_clk: upg_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; rdb { @@ -61,7 +67,7 @@ compatible = "simple-bus"; ranges = <0 0x10000000 0x01000000>; - periph_intc: periph_intc@41b500 { + periph_intc: interrupt-controller@41b500 { compatible = "brcm,bcm7038-l1-intc"; reg = <0x41b500 0x40>, <0x41b600 0x40>, <0x41b700 0x40>, <0x41b800 0x40>; @@ -73,7 +79,7 @@ interrupts = <2>, <3>, <2>, <3>; }; - sun_l2_intc: sun_l2_intc@403000 { + sun_l2_intc: interrupt-controller@403000 { compatible = "brcm,l2-intc"; reg = <0x403000 0x30>; interrupt-controller; @@ -98,7 +104,7 @@ "scpu"; }; - upg_irq0_intc: upg_irq0_intc@406780 { + upg_irq0_intc: interrupt-controller@406780 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; @@ -113,7 +119,7 @@ interrupt-names = "upg_main", "upg_bsc"; }; - upg_aon_irq0_intc: upg_aon_irq0_intc@409480 { + upg_aon_irq0_intc: interrupt-controller@409480 { compatible = "brcm,bcm7120-l2-intc"; reg = <0x409480 0x8>; @@ -224,6 +230,59 @@ status = "disabled"; }; + pwma: pwm@406580 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406580 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + pwmb: pwm@406800 { + compatible = "brcm,bcm7038-pwm"; + reg = <0x406800 0x28>; + #pwm-cells = <2>; + clocks = <&upg_clk>; + status = "disabled"; + }; + + aon_pm_l2_intc: interrupt-controller@408440 { + compatible = "brcm,l2-intc"; + reg = <0x408440 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <54>; + brcm,irq-can-wake; + }; + + upg_gio: gpio@406700 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x406700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 21>; + }; + + upg_gio_aon: gpio@4094c0 { + compatible = "brcm,brcmstb-gpio"; + reg = <0x4094c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&upg_aon_irq0_intc>; + interrupts = <6>; + interrupts-extended = <&upg_aon_irq0_intc 6>, + <&aon_pm_l2_intc 5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -327,6 +386,26 @@ status = "disabled"; }; + hif_l2_intc: interrupt-controller@41b000 { + compatible = "brcm,l2-intc"; + reg = <0x41b000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <24>; + }; + + nand: nand@41c800 { + compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "nand", "flash-dma"; + reg = <0x41c800 0x600>, <0x41d000 0x100>; + interrupt-parent = <&hif_l2_intc>; + interrupts = <24>, <4>; + status = "disabled"; + }; + sata: sata@181000 { compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; reg-names = "ahci", "top-ctrl"; @@ -366,5 +445,25 @@ #phy-cells = <0>; }; }; + + sdhci0: sdhci@41a000 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x41a000 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <47>; + sd-uhs-sdr50; + mmc-hs200-1_8v; + status = "disabled"; + }; + + sdhci1: sdhci@41a200 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0x41a200 0x100>; + interrupt-parent = <&periph_intc>; + interrupts = <48>; + sd-uhs-sdr50; + mmc-hs200-1_8v; + status = "disabled"; + }; }; }; diff --git a/dts/src/mips/brcm/bcm97125cbmb.dts b/dts/src/mips/brcm/bcm97125cbmb.dts index f2449d147c..5c24eacd72 100644 --- a/dts/src/mips/brcm/bcm97125cbmb.dts +++ b/dts/src/mips/brcm/bcm97125cbmb.dts @@ -45,6 +45,10 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + /* FIXME: USB is wonky; disable it for now */ &ehci0 { status = "disabled"; diff --git a/dts/src/mips/brcm/bcm97346dbsmb.dts b/dts/src/mips/brcm/bcm97346dbsmb.dts index d3d28816a0..e67eaf30de 100644 --- a/dts/src/mips/brcm/bcm97346dbsmb.dts +++ b/dts/src/mips/brcm/bcm97346dbsmb.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "bcm7346.dtsi" +/include/ "bcm97xxx-nand-cs1-bch24.dtsi" / { compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346"; @@ -49,6 +50,14 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + +&pwmb { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -85,6 +94,10 @@ status = "okay"; }; +&nand { + status = "okay"; +}; + &sata { status = "okay"; }; @@ -92,3 +105,7 @@ &sata_phy { status = "okay"; }; + +&sdhci0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97358svmb.dts b/dts/src/mips/brcm/bcm97358svmb.dts index 02ce6b429d..ee4607fae4 100644 --- a/dts/src/mips/brcm/bcm97358svmb.dts +++ b/dts/src/mips/brcm/bcm97358svmb.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "bcm7358.dtsi" +/include/ "bcm97xxx-nand-cs1-bch4.dtsi" / { compatible = "brcm,bcm97358svmb", "brcm,bcm7358"; @@ -45,6 +46,14 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + +&pwmb { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -56,3 +65,7 @@ &ohci0 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97360svmb.dts b/dts/src/mips/brcm/bcm97360svmb.dts index 73124be954..bed821b030 100644 --- a/dts/src/mips/brcm/bcm97360svmb.dts +++ b/dts/src/mips/brcm/bcm97360svmb.dts @@ -45,6 +45,10 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -64,3 +68,7 @@ &sata_phy { status = "okay"; }; + +&sdhci0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97362svmb.dts b/dts/src/mips/brcm/bcm97362svmb.dts index 3cfcaebe7f..68fd823868 100644 --- a/dts/src/mips/brcm/bcm97362svmb.dts +++ b/dts/src/mips/brcm/bcm97362svmb.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "bcm7362.dtsi" +/include/ "bcm97xxx-nand-cs1-bch4.dtsi" / { compatible = "brcm,bcm97362svmb", "brcm,bcm7362"; @@ -41,6 +42,10 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -53,6 +58,10 @@ status = "okay"; }; +&nand { + status = "okay"; +}; + &sata { status = "okay"; }; @@ -60,3 +69,7 @@ &sata_phy { status = "okay"; }; + +&sdhci0 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97420c.dts b/dts/src/mips/brcm/bcm97420c.dts index 600d57abee..e66271af05 100644 --- a/dts/src/mips/brcm/bcm97420c.dts +++ b/dts/src/mips/brcm/bcm97420c.dts @@ -51,6 +51,14 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + +&pwmb { + status = "okay"; +}; + /* FIXME: MAC driver comes up but cannot attach to PHY */ &enet0 { status = "disabled"; diff --git a/dts/src/mips/brcm/bcm97425svmb.dts b/dts/src/mips/brcm/bcm97425svmb.dts index 119c714805..f95ba1bf3e 100644 --- a/dts/src/mips/brcm/bcm97425svmb.dts +++ b/dts/src/mips/brcm/bcm97425svmb.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "bcm7425.dtsi" +/include/ "bcm97xxx-nand-cs1-bch24.dtsi" / { compatible = "brcm,bcm97425svmb", "brcm,bcm7425"; @@ -51,6 +52,14 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + +&pwmb { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -86,3 +95,15 @@ &ohci3 { status = "okay"; }; + +&nand { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97435svmb.dts b/dts/src/mips/brcm/bcm97435svmb.dts index 43e3ba27f0..fb37b7111b 100644 --- a/dts/src/mips/brcm/bcm97435svmb.dts +++ b/dts/src/mips/brcm/bcm97435svmb.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "bcm7435.dtsi" +/include/ "bcm97xxx-nand-cs1-bch24.dtsi" / { compatible = "brcm,bcm97435svmb", "brcm,bcm7435"; @@ -51,6 +52,14 @@ status = "okay"; }; +&pwma { + status = "okay"; +}; + +&pwmb { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -87,6 +96,10 @@ status = "okay"; }; +&nand { + status = "okay"; +}; + &sata { status = "okay"; }; @@ -94,3 +107,11 @@ &sata_phy { status = "okay"; }; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; diff --git a/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi b/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi new file mode 100644 index 0000000000..3c24f97de9 --- /dev/null +++ b/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi @@ -0,0 +1,25 @@ +&nand { + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <1>; + nand-on-flash-bbt; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + brcm,nand-oob-sector-size = <27>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1.rootfs@0 { + reg = <0x0 0x10000000>; + }; + + flash1.kernel@10000000 { + reg = <0x10000000 0x400000>; + }; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi b/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi new file mode 100644 index 0000000000..cb531816ef --- /dev/null +++ b/dts/src/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi @@ -0,0 +1,25 @@ +&nand { + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <1>; + nand-on-flash-bbt; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1.rootfs@0 { + reg = <0x0 0x10000000>; + }; + + flash1.kernel@10000000 { + reg = <0x10000000 0x400000>; + }; + }; + }; +}; diff --git a/dts/src/mips/cavium-octeon/dlink_dsr-1000n.dts b/dts/src/mips/cavium-octeon/dlink_dsr-1000n.dts index b134798a0f..cfa29156eb 100644 --- a/dts/src/mips/cavium-octeon/dlink_dsr-1000n.dts +++ b/dts/src/mips/cavium-octeon/dlink_dsr-1000n.dts @@ -8,55 +8,16 @@ * published by the Free Software Foundation. */ -/include/ "octeon_3xxx.dtsi" +/include/ "dlink_dsr-500n-1000n.dtsi" #include <dt-bindings/gpio/gpio.h> / { model = "dlink,dsr-1000n"; soc@0 { - smi0: mdio@1180000001800 { - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; - - pip: pip@11800a0000000 { - interface@0 { - ethernet@0 { - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - ethernet@1 { - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - ethernet@2 { - phy-handle = <&phy8>; - }; - }; - }; - - twsi0: i2c@1180000001000 { - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - }; - uart0: serial@1180000000800 { clock-frequency = <500000000>; }; - - usbn: usbn@1180068000000 { - refclk-frequency = <12000000>; - refclk-type = "crystal"; - }; }; leds { @@ -87,8 +48,4 @@ gpios = <&gpio 18 GPIO_ACTIVE_LOW>; }; }; - - aliases { - pip = &pip; - }; }; diff --git a/dts/src/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi b/dts/src/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi new file mode 100644 index 0000000000..246b598201 --- /dev/null +++ b/dts/src/mips/cavium-octeon/dlink_dsr-500n-1000n.dtsi @@ -0,0 +1,58 @@ +/* + * Device tree source for D-Link DSR-500N/1000N (common parts). + * + * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "octeon_3xxx.dtsi" + +/ { + soc@0 { + smi0: mdio@1180000001800 { + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + pip: pip@11800a0000000 { + interface@0 { + ethernet@0 { + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + ethernet@1 { + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + ethernet@2 { + phy-handle = <&phy8>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + usbn: usbn@1180068000000 { + refclk-frequency = <12000000>; + refclk-type = "crystal"; + }; + }; + + aliases { + pip = &pip; + }; +}; diff --git a/dts/src/mips/cavium-octeon/dlink_dsr-500n.dts b/dts/src/mips/cavium-octeon/dlink_dsr-500n.dts new file mode 100644 index 0000000000..78886e172c --- /dev/null +++ b/dts/src/mips/cavium-octeon/dlink_dsr-500n.dts @@ -0,0 +1,40 @@ +/* + * Device tree source for D-Link DSR-500N. + * + * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "dlink_dsr-500n-1000n.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "dlink,dsr-500n"; + compatible = "dlink,dsr-500n", "cavium,octeon-3860"; + + soc@0 { + uart0: serial@1180000000800 { + clock-frequency = <300000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + wireless { + label = "2.4g"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/mips/mti/malta.dts b/dts/src/mips/mti/malta.dts index b18c46637d..f604a272d9 100644 --- a/dts/src/mips/mti/malta.dts +++ b/dts/src/mips/mti/malta.dts @@ -1,5 +1,8 @@ /dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/mips-gic.h> + /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */ /memreserve/ 0x00001000 0x000ef000; /* YAMON */ /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ @@ -8,4 +11,100 @@ #address-cells = <1>; #size-cells = <1>; compatible = "mti,malta"; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + gic: interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + }; + }; + + i8259: interrupt-controller@20 { + compatible = "intel,i8259"; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; + }; + + flash@1e000000 { + compatible = "intel,dt28f160", "cfi-flash"; + reg = <0x1e000000 0x400000>; + bank-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + yamon@0 { + label = "YAMON"; + reg = <0x0 0x100000>; + read-only; + }; + + user-fs@100000 { + label = "User FS"; + reg = <0x100000 0x2e0000>; + }; + + board-config@3e0000 { + label = "Board Config"; + reg = <0x3e0000 0x20000>; + read-only; + }; + }; + }; + + fpga_regs: system-controller@1f000000 { + compatible = "mti,malta-fpga", "syscon", "simple-mfd"; + reg = <0x1f000000 0x1000>; + + reboot { + compatible = "syscon-reboot"; + regmap = <&fpga_regs>; + offset = <0x500>; + mask = <0x4d>; + }; + }; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0x1000>; + + rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + + interrupt-parent = <&i8259>; + interrupts = <8>; + }; + }; }; diff --git a/dts/src/mips/mti/sead3.dts b/dts/src/mips/mti/sead3.dts index e4b317d414..b112879a5d 100644 --- a/dts/src/mips/mti/sead3.dts +++ b/dts/src/mips/mti/sead3.dts @@ -4,10 +4,23 @@ /memreserve/ 0x00001000 0x000ef000; // ROM data /memreserve/ 0x000f0000 0x004cc000; // reserved +#include <dt-bindings/interrupt-controller/mips-gic.h> + / { #address-cells = <1>; #size-cells = <1>; compatible = "mti,sead-3"; + model = "MIPS SEAD-3"; + interrupt-parent = <&gic>; + + chosen { + stdout-path = "uart1:115200"; + }; + + aliases { + uart0 = &uart0; + uart1 = &uart1; + }; cpus { cpu@0 { @@ -19,4 +32,229 @@ device_type = "memory"; reg = <0x0 0x08000000>; }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + gic: interrupt-controller@1b1c0000 { + compatible = "mti,gic"; + reg = <0x1b1c0000 0x20000>; + + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + }; + }; + + ehci@1b200000 { + compatible = "generic-ehci"; + reg = <0x1b200000 0x1000>; + + interrupts = <0>; /* GIC 0 or CPU 6 */ + + has-transaction-translator; + }; + + flash@1c000000 { + compatible = "intel,28f128j3", "cfi-flash"; + reg = <0x1c000000 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + user-fs@0 { + label = "User FS"; + reg = <0x0 0x1fc0000>; + }; + + board-config@3e0000 { + label = "Board Config"; + reg = <0x1fc0000 0x40000>; + }; + }; + }; + + fpga_regs: system-controller@1f000000 { + compatible = "mti,sead3-fpga", "syscon", "simple-mfd"; + reg = <0x1f000000 0x200>; + + reboot { + compatible = "syscon-reboot"; + regmap = <&fpga_regs>; + offset = <0x50>; + mask = <0x4d>; + }; + + poweroff { + compatible = "restart-poweroff"; + }; + }; + + system-controller@1f000200 { + compatible = "mti,sead3-cpld", "syscon", "simple-mfd"; + reg = <0x1f000200 0x300>; + + led@10.0 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x1>; + label = "pled0"; + }; + led@10.1 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x2>; + label = "pled1"; + }; + led@10.2 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x4>; + label = "pled2"; + }; + led@10.3 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x8>; + label = "pled3"; + }; + led@10.4 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x10>; + label = "pled4"; + }; + led@10.5 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x20>; + label = "pled5"; + }; + led@10.6 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x40>; + label = "pled6"; + }; + led@10.7 { + compatible = "register-bit-led"; + offset = <0x10>; + mask = <0x80>; + label = "pled7"; + }; + + led@18.0 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x1>; + label = "fled0"; + }; + led@18.1 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x2>; + label = "fled1"; + }; + led@18.2 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x4>; + label = "fled2"; + }; + led@18.3 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x8>; + label = "fled3"; + }; + led@18.4 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x10>; + label = "fled4"; + }; + led@18.5 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x20>; + label = "fled5"; + }; + led@18.6 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x40>; + label = "fled6"; + }; + led@18.7 { + compatible = "register-bit-led"; + offset = <0x18>; + mask = <0x80>; + label = "fled7"; + }; + + lcd@200 { + compatible = "mti,sead3-lcd"; + offset = <0x200>; + }; + }; + + /* UART connected to FTDI & miniUSB socket */ + uart0: uart@1f000900 { + compatible = "ns16550a"; + reg = <0x1f000900 0x20>; + reg-io-width = <4>; + reg-shift = <2>; + + clock-frequency = <14745600>; + + interrupts = <3>; /* GIC 3 or CPU 4 */ + + no-loopback-test; + }; + + /* UART connected to RS232 socket */ + uart1: uart@1f000800 { + compatible = "ns16550a"; + reg = <0x1f000800 0x20>; + reg-io-width = <4>; + reg-shift = <2>; + + clock-frequency = <14745600>; + + interrupts = <2>; /* GIC 2 or CPU 4 */ + + no-loopback-test; + }; + + eth@1f010000 { + compatible = "smsc,lan9115"; + reg = <0x1f010000 0x10000>; + reg-io-width = <4>; + + interrupts = <0>; /* GIC 0 or CPU 6 */ + + phy-mode = "mii"; + smsc,irq-push-pull; + smsc,save-mac-address; + }; }; diff --git a/dts/src/nios2/10m50_devboard.dts b/dts/src/nios2/10m50_devboard.dts index 3e411c6448..f362b2224e 100755 --- a/dts/src/nios2/10m50_devboard.dts +++ b/dts/src/nios2/10m50_devboard.dts @@ -83,6 +83,7 @@ fifo-size = <32>; reg-io-width = <4>; reg-shift = <2>; + tx-threshold = <16>; }; sysid: sysid@18001528 { diff --git a/dts/src/xtensa/csp.dts b/dts/src/xtensa/csp.dts new file mode 100644 index 0000000000..4082f26716 --- /dev/null +++ b/dts/src/xtensa/csp.dts @@ -0,0 +1,54 @@ +/dts-v1/; + +/ { + compatible = "cdns,xtensa-xtfpga"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "cdns,xtensa-cpu"; + reg = <0>; + }; + }; + + pic: pic { + compatible = "cdns,xtensa-pic"; + #interrupt-cells = <2>; + interrupt-controller; + }; + + clocks { + osc: main-oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + + uart0: serial@0d000000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + clocks = <&osc>, <&osc>; + clock-names = "uart_clk", "pclk"; + reg = <0x0d000000 0x1000>; + interrupts = <0 1>; + }; + }; +}; diff --git a/dts/src/xtensa/xtfpga.dtsi b/dts/src/xtensa/xtfpga.dtsi index cd45f9c2c4..91616a9d79 100644 --- a/dts/src/xtensa/xtfpga.dtsi +++ b/dts/src/xtensa/xtfpga.dtsi @@ -19,9 +19,7 @@ cpu@0 { compatible = "cdns,xtensa-cpu"; reg = <0>; - /* Filled in by platform_setup from FPGA register - * clock-frequency = <100000000>; - */ + clocks = <&osc>; }; }; @@ -36,11 +34,6 @@ }; clocks { - osc: main-oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - clk54: clk54 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -54,6 +47,12 @@ compatible = "simple-bus"; ranges = <0x00000000 0xf0000000 0x10000000>; + osc: main-oscillator { + #clock-cells = <0>; + compatible = "cdns,xtfpga-clock"; + reg = <0x0d020004 0x4>; + }; + serial0: serial@0d050020 { device_type = "serial"; compatible = "ns16550a"; |