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authorSascha Hauer <s.hauer@pengutronix.de>2016-10-28 08:52:27 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-10-28 08:52:27 +0200
commit3b5c343782dea7827694cafd53fed08645cb6abf (patch)
tree657125ff896c3e46e982b5d2a26363ed4bf8cc82 /dts
parentbfbf18d991756858337f7700e8ff0a6f0dc31afc (diff)
downloadbarebox-3b5c343782dea7827694cafd53fed08645cb6abf.tar.gz
dts: update to v4.9-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/ipmi/aspeed,ast2400-bt-bmc.txt23
-rw-r--r--dts/Bindings/ipmi/ipmi-smic.txt (renamed from dts/Bindings/ipmi.txt)0
-rw-r--r--dts/Bindings/pinctrl/pinctrl-aspeed.txt4
-rw-r--r--dts/Bindings/timer/jcore,pit.txt24
4 files changed, 50 insertions, 1 deletions
diff --git a/dts/Bindings/ipmi/aspeed,ast2400-bt-bmc.txt b/dts/Bindings/ipmi/aspeed,ast2400-bt-bmc.txt
new file mode 100644
index 0000000..fbbacd9
--- /dev/null
+++ b/dts/Bindings/ipmi/aspeed,ast2400-bt-bmc.txt
@@ -0,0 +1,23 @@
+* Aspeed BT (Block Transfer) IPMI interface
+
+The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
+(BaseBoard Management Controllers) and the BT interface can be used to
+perform in-band IPMI communication with their host.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-bt-bmc"
+- reg: physical address and size of the registers
+
+Optional properties:
+
+- interrupts: interrupt generated by the BT interface. without an
+ interrupt, the driver will operate in poll mode.
+
+Example:
+
+ ibt@1e789140 {
+ compatible = "aspeed,ast2400-bt-bmc";
+ reg = <0x1e789140 0x18>;
+ interrupts = <8>;
+ };
diff --git a/dts/Bindings/ipmi.txt b/dts/Bindings/ipmi/ipmi-smic.txt
index d5f1a87..d5f1a87 100644
--- a/dts/Bindings/ipmi.txt
+++ b/dts/Bindings/ipmi/ipmi-smic.txt
diff --git a/dts/Bindings/pinctrl/pinctrl-aspeed.txt b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
index 5e60ad1..2ad18c4 100644
--- a/dts/Bindings/pinctrl/pinctrl-aspeed.txt
+++ b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
-RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
+RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
+TIMER7 TIMER8 VGABIOSROM
+
Examples:
diff --git a/dts/Bindings/timer/jcore,pit.txt b/dts/Bindings/timer/jcore,pit.txt
new file mode 100644
index 0000000..af5dd35
--- /dev/null
+++ b/dts/Bindings/timer/jcore,pit.txt
@@ -0,0 +1,24 @@
+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 0x500 0x30 >;
+ interrupts = < 0x48 >;
+};