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authorSascha Hauer <s.hauer@pengutronix.de>2019-04-05 14:51:56 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-04-08 10:16:55 +0200
commit085594d8fd51379afd94f9b89fcce05ecab02d8d (patch)
treef8007ac06ed951cf8c63b9cedf067264ebac3256 /dts
parent6cec968f559cc22939dbe90ebbde245a7e8a85f4 (diff)
downloadbarebox-085594d8fd51379afd94f9b89fcce05ecab02d8d.tar.gz
dts: update to v5.1-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/i2c/i2c-iop3xx.txt (renamed from dts/Bindings/i2c/i2c-xscale.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.txt (renamed from dts/Bindings/i2c/i2c-mtk.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-stu300.txt (renamed from dts/Bindings/i2c/i2c-st-ddci2c.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-sun6i-p2wi.txt (renamed from dts/Bindings/i2c/i2c-sunxi-p2wi.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-wmt.txt (renamed from dts/Bindings/i2c/i2c-vt8500.txt)0
-rw-r--r--dts/Bindings/net/dsa/qca8k.txt73
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/src/arm/bcm2835-rpi-b-rev2.dts2
-rw-r--r--dts/src/arm/imx6dl-yapp4-common.dtsi6
-rw-r--r--dts/src/arm/imx6qdl-icore-rqs.dtsi4
-rw-r--r--dts/src/arm/imx6qdl-phytec-pfla02.dtsi1
-rw-r--r--dts/src/arm/imx6ull-pinfunc-snvs.h2
-rw-r--r--dts/src/arm/ste-nomadik-nhk15.dts9
-rw-r--r--dts/src/arm64/nvidia/tegra186.dtsi1
-rw-r--r--dts/src/arm64/renesas/r8a774c0.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi7
16 files changed, 86 insertions, 27 deletions
diff --git a/dts/Bindings/i2c/i2c-xscale.txt b/dts/Bindings/i2c/i2c-iop3xx.txt
index dcc8390..dcc8390 100644
--- a/dts/Bindings/i2c/i2c-xscale.txt
+++ b/dts/Bindings/i2c/i2c-iop3xx.txt
diff --git a/dts/Bindings/i2c/i2c-mtk.txt b/dts/Bindings/i2c/i2c-mt65xx.txt
index ee4c324..ee4c324 100644
--- a/dts/Bindings/i2c/i2c-mtk.txt
+++ b/dts/Bindings/i2c/i2c-mt65xx.txt
diff --git a/dts/Bindings/i2c/i2c-st-ddci2c.txt b/dts/Bindings/i2c/i2c-stu300.txt
index bd81a48..bd81a48 100644
--- a/dts/Bindings/i2c/i2c-st-ddci2c.txt
+++ b/dts/Bindings/i2c/i2c-stu300.txt
diff --git a/dts/Bindings/i2c/i2c-sunxi-p2wi.txt b/dts/Bindings/i2c/i2c-sun6i-p2wi.txt
index 49df005..49df005 100644
--- a/dts/Bindings/i2c/i2c-sunxi-p2wi.txt
+++ b/dts/Bindings/i2c/i2c-sun6i-p2wi.txt
diff --git a/dts/Bindings/i2c/i2c-vt8500.txt b/dts/Bindings/i2c/i2c-wmt.txt
index 94a425e..94a425e 100644
--- a/dts/Bindings/i2c/i2c-vt8500.txt
+++ b/dts/Bindings/i2c/i2c-wmt.txt
diff --git a/dts/Bindings/net/dsa/qca8k.txt b/dts/Bindings/net/dsa/qca8k.txt
index bbcb255..93a7469 100644
--- a/dts/Bindings/net/dsa/qca8k.txt
+++ b/dts/Bindings/net/dsa/qca8k.txt
@@ -12,10 +12,15 @@ Required properties:
Subnodes:
The integrated switch subnode should be specified according to the binding
-described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of
-port and PHY id, each subnode describing a port needs to have a valid phandle
-referencing the internal PHY connected to it. The CPU port of this switch is
-always port 0.
+described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
+mdio-bus each subnode describing a port needs to have a valid phandle
+referencing the internal PHY it is connected to. This is because there's no
+N:N mapping of port and PHY id.
+
+Don't use mixed external and internal mdio-bus configurations, as this is
+not supported by the hardware.
+
+The CPU port of this switch is always port 0.
A CPU port node has the following optional node:
@@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties:
- 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed.
-Example:
+Examples:
+for the external mdio-bus configuration:
&mdio0 {
phy_port1: phy@0 {
@@ -55,12 +61,12 @@ Example:
reg = <4>;
};
- switch0@0 {
+ switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <0x10>;
ports {
#address-cells = <1>;
@@ -108,3 +114,56 @@ Example:
};
};
};
+
+for the internal master mdio-bus configuration:
+
+ &mdio0 {
+ switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = 1000;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "wan";
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index 742cb47..bcfb131 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -16,6 +16,7 @@ Required properties:
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
+ * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
- reg: The base address of the UART register bank.
diff --git a/dts/src/arm/bcm2835-rpi-b-rev2.dts b/dts/src/arm/bcm2835-rpi-b-rev2.dts
index 5641d16..28e7513 100644
--- a/dts/src/arm/bcm2835-rpi-b-rev2.dts
+++ b/dts/src/arm/bcm2835-rpi-b-rev2.dts
@@ -93,7 +93,7 @@
};
&hdmi {
- hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
};
&pwm {
diff --git a/dts/src/arm/imx6dl-yapp4-common.dtsi b/dts/src/arm/imx6dl-yapp4-common.dtsi
index b715ab0..e8d800f 100644
--- a/dts/src/arm/imx6dl-yapp4-common.dtsi
+++ b/dts/src/arm/imx6dl-yapp4-common.dtsi
@@ -114,9 +114,9 @@
reg = <2>;
};
- switch@0 {
+ switch@10 {
compatible = "qca,qca8334";
- reg = <0>;
+ reg = <10>;
switch_ports: ports {
#address-cells = <1>;
@@ -125,7 +125,7 @@
ethphy0: port@0 {
reg = <0>;
label = "cpu";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
ethernet = <&fec>;
fixed-link {
diff --git a/dts/src/arm/imx6qdl-icore-rqs.dtsi b/dts/src/arm/imx6qdl-icore-rqs.dtsi
index 1d1b4bd..a4217f5 100644
--- a/dts/src/arm/imx6qdl-icore-rqs.dtsi
+++ b/dts/src/arm/imx6qdl-icore-rqs.dtsi
@@ -264,7 +264,7 @@
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmcc-supply = <&reg_sd3_vmmc>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- bus-witdh = <4>;
+ bus-width = <4>;
no-1-8-v;
status = "okay";
};
@@ -275,7 +275,7 @@
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
vmcc-supply = <&reg_sd4_vmmc>;
- bus-witdh = <8>;
+ bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
diff --git a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
index 433bf09..027df06 100644
--- a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
@@ -91,6 +91,7 @@
pinctrl-0 = <&pinctrl_enet>;
phy-handle = <&ethphy>;
phy-mode = "rgmii";
+ phy-reset-duration = <10>; /* in msecs */
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
phy-supply = <&vdd_eth_io_reg>;
status = "disabled";
diff --git a/dts/src/arm/imx6ull-pinfunc-snvs.h b/dts/src/arm/imx6ull-pinfunc-snvs.h
index f6fb678..54cfe72 100644
--- a/dts/src/arm/imx6ull-pinfunc-snvs.h
+++ b/dts/src/arm/imx6ull-pinfunc-snvs.h
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright (C) 2017 NXP
diff --git a/dts/src/arm/ste-nomadik-nhk15.dts b/dts/src/arm/ste-nomadik-nhk15.dts
index 04066f9..f2f6558 100644
--- a/dts/src/arm/ste-nomadik-nhk15.dts
+++ b/dts/src/arm/ste-nomadik-nhk15.dts
@@ -213,12 +213,13 @@
gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>;
/*
- * It's not actually active high, but the frameworks assume
- * the polarity of the passed-in GPIO is "normal" (active
- * high) then actively drives the line low to select the
- * chip.
+ * This chipselect is active high. Just setting the flags
+ * to GPIO_ACTIVE_HIGH is not enough for the SPI DT bindings,
+ * it will be ignored, only the special "spi-cs-high" flag
+ * really counts.
*/
cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ spi-cs-high;
num-chipselects = <1>;
/*
diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi
index bb2045b..97aeb94 100644
--- a/dts/src/arm64/nvidia/tegra186.dtsi
+++ b/dts/src/arm64/nvidia/tegra186.dtsi
@@ -321,7 +321,6 @@
nvidia,default-trim = <0x9>;
nvidia,dqs-trim = <63>;
mmc-hs400-1_8v;
- supports-cqe;
status = "disabled";
};
diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi
index 61a0afb..1ea684a 100644
--- a/dts/src/arm64/renesas/r8a774c0.dtsi
+++ b/dts/src/arm64/renesas/r8a774c0.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for the RZ/G2E (R8A774C0) SoC
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
@@ -1150,9 +1150,8 @@
<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
+ dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi
index a69faa6..d2ad665 100644
--- a/dts/src/arm64/renesas/r8a77990.dtsi
+++ b/dts/src/arm64/renesas/r8a77990.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
@@ -1067,9 +1067,8 @@
<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
+ dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";