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authorSascha Hauer <s.hauer@pengutronix.de>2018-09-11 08:26:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-09-11 17:23:13 +0200
commit35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (patch)
treedd2cf14c56430d21079c794fa6e03d7f5d91070e /dts
parent625eea2765d94aee016cf25d9cabecde8eae0775 (diff)
downloadbarebox-35f607bc7da71b302fd6bf3d6d48d7ea66df1195.tar.gz
dts: update to v4.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/arm/adapteva.txt7
-rw-r--r--dts/Bindings/arm/amlogic.txt13
-rw-r--r--dts/Bindings/arm/atmel-pmc.txt14
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt4
-rw-r--r--dts/Bindings/arm/coresight.txt58
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt2
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt3
-rw-r--r--dts/Bindings/arm/freescale/m4if.txt12
-rw-r--r--dts/Bindings/arm/freescale/tigerp.txt12
-rw-r--r--dts/Bindings/arm/fsl.txt4
-rw-r--r--dts/Bindings/arm/idle-states.txt4
-rw-r--r--dts/Bindings/arm/insignal-boards.txt8
-rw-r--r--dts/Bindings/arm/marvell/ap806-system-controller.txt48
-rw-r--r--dts/Bindings/arm/marvell/armada-37xx.txt15
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller.txt (renamed from dts/Bindings/arm/marvell/cp110-system-controller0.txt)61
-rw-r--r--dts/Bindings/arm/mediatek.txt10
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.txt26
-rw-r--r--dts/Bindings/arm/omap/crossbar.txt1
-rw-r--r--dts/Bindings/arm/omap/l4.txt15
-rw-r--r--dts/Bindings/arm/rockchip.txt14
-rw-r--r--dts/Bindings/arm/samsung/pmu.txt3
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt5
-rw-r--r--dts/Bindings/arm/shmobile.txt5
-rw-r--r--dts/Bindings/arm/ti/k3.txt23
-rw-r--r--dts/Bindings/arm/xilinx.txt30
-rw-r--r--dts/Bindings/ata/ahci-platform.txt2
-rw-r--r--dts/Bindings/ata/fsl-sata.txt1
-rw-r--r--dts/Bindings/ata/pata-arasan.txt2
-rw-r--r--dts/Bindings/ata/sata_rcar.txt1
-rw-r--r--dts/Bindings/board/fsl-board.txt1
-rw-r--r--dts/Bindings/bus/brcm,gisb-arb.txt2
-rw-r--r--dts/Bindings/bus/sun50i-de2-bus.txt37
-rw-r--r--dts/Bindings/bus/ti-sysc.txt1
-rw-r--r--dts/Bindings/clock/actions,owl-cmu.txt (renamed from dts/Bindings/clock/actions,s900-cmu.txt)20
-rw-r--r--dts/Bindings/clock/amlogic,axg-audio-clkc.txt56
-rw-r--r--dts/Bindings/clock/at91-clock.txt51
-rw-r--r--dts/Bindings/clock/exynos5440-clock.txt28
-rw-r--r--dts/Bindings/clock/maxim,max9485.txt59
-rw-r--r--dts/Bindings/clock/qcom,dispcc.txt19
-rw-r--r--dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt43
-rw-r--r--dts/Bindings/clock/rockchip,px30-cru.txt65
-rw-r--r--dts/Bindings/clock/sun8i-de2.txt1
-rw-r--r--dts/Bindings/connector/usb-connector.txt44
-rw-r--r--dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt2
-rw-r--r--dts/Bindings/cpufreq/cpufreq-exynos5440.txt28
-rw-r--r--dts/Bindings/crypto/amd-ccp.txt2
-rw-r--r--dts/Bindings/crypto/arm-cryptocell.txt2
-rw-r--r--dts/Bindings/crypto/fsl-sec2.txt5
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt21
-rw-r--r--dts/Bindings/crypto/hisilicon,hip07-sec.txt67
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt15
-rw-r--r--dts/Bindings/crypto/picochip-spacc.txt2
-rw-r--r--dts/Bindings/crypto/qcom,prng.txt (renamed from dts/Bindings/rng/qcom,prng.txt)4
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt211
-rw-r--r--dts/Bindings/display/brcm,bcm-vc4.txt6
-rw-r--r--dts/Bindings/display/bridge/analogix_dp.txt2
-rw-r--r--dts/Bindings/display/bridge/anx7814.txt2
-rw-r--r--dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt2
-rw-r--r--dts/Bindings/display/bridge/sii902x.txt4
-rw-r--r--dts/Bindings/display/bridge/sii9234.txt2
-rw-r--r--dts/Bindings/display/bridge/sil-sii8620.txt2
-rw-r--r--dts/Bindings/display/exynos/exynos7-decon.txt3
-rw-r--r--dts/Bindings/display/exynos/exynos_dp.txt2
-rw-r--r--dts/Bindings/display/exynos/samsung-fimd.txt3
-rw-r--r--dts/Bindings/display/ht16k33.txt2
-rw-r--r--dts/Bindings/display/ilitek,ili9341.txt27
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt3
-rw-r--r--dts/Bindings/display/marvell,pxa300-gcu.txt17
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt2
-rw-r--r--dts/Bindings/display/msm/dpu.txt131
-rw-r--r--dts/Bindings/display/msm/dsi.txt18
-rw-r--r--dts/Bindings/display/msm/edp.txt4
-rw-r--r--dts/Bindings/display/msm/mdp5.txt2
-rw-r--r--dts/Bindings/display/panel/auo,g070vvn01.txt29
-rw-r--r--dts/Bindings/display/panel/boe,hv070wsa-100.txt28
-rw-r--r--dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt8
-rw-r--r--dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt13
-rw-r--r--dts/Bindings/display/panel/edt,et-series.txt39
-rw-r--r--dts/Bindings/display/panel/edt,et070080dh6.txt10
-rw-r--r--dts/Bindings/display/panel/edt,etm0700g0dh6.txt10
-rw-r--r--dts/Bindings/display/panel/ilitek,ili9881c.txt20
-rw-r--r--dts/Bindings/display/panel/innolux,g070y2-l01.txt12
-rw-r--r--dts/Bindings/display/panel/innolux,p097pfg.txt24
-rw-r--r--dts/Bindings/display/panel/innolux,tv123wam.txt20
-rw-r--r--dts/Bindings/display/panel/kingdisplay,kd097d04.txt22
-rw-r--r--dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt (renamed from dts/Bindings/display/panel/edt,et057090dhu.txt)4
-rw-r--r--dts/Bindings/display/panel/rocktech,rk070er9427.txt25
-rw-r--r--dts/Bindings/display/panel/sharp,lq035q7db03.txt12
-rw-r--r--dts/Bindings/display/renesas,du.txt1
-rw-r--r--dts/Bindings/display/sm501fb.txt2
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt64
-rw-r--r--dts/Bindings/display/tilcdc/tilcdc.txt2
-rw-r--r--dts/Bindings/dma/jz4780-dma.txt1
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.txt1
-rw-r--r--dts/Bindings/dma/owl-dma.txt47
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps,dw-axi-dmac.txt2
-rw-r--r--dts/Bindings/dma/snps-dma.txt2
-rw-r--r--dts/Bindings/dma/ti-edma.txt1
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_dma.txt2
-rw-r--r--dts/Bindings/dma/xilinx/zynqmp_dma.txt1
-rw-r--r--dts/Bindings/eeprom/at24.txt2
-rw-r--r--dts/Bindings/extcon/extcon-rt8973a.txt2
-rw-r--r--dts/Bindings/extcon/extcon-sm5502.txt2
-rw-r--r--dts/Bindings/fsi/fsi-master-ast-cf.txt36
-rw-r--r--dts/Bindings/fsi/fsi.txt5
-rw-r--r--dts/Bindings/gnss/gnss.txt36
-rw-r--r--dts/Bindings/gnss/sirfstar.txt45
-rw-r--r--dts/Bindings/gnss/u-blox.txt44
-rw-r--r--dts/Bindings/gpio/8xxx_gpio.txt2
-rw-r--r--dts/Bindings/gpio/abilis,tb10x-gpio.txt1
-rw-r--r--dts/Bindings/gpio/brcm,brcmstb-gpio.txt3
-rw-r--r--dts/Bindings/gpio/fsl-imx-gpio.txt3
-rw-r--r--dts/Bindings/gpio/gpio-adnp.txt1
-rw-r--r--dts/Bindings/gpio/gpio-aspeed.txt1
-rw-r--r--dts/Bindings/gpio/gpio-ath79.txt1
-rw-r--r--dts/Bindings/gpio/gpio-davinci.txt2
-rw-r--r--dts/Bindings/gpio/gpio-max732x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt3
-rw-r--r--dts/Bindings/gpio/gpio-pcf857x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-uniphier.txt1
-rw-r--r--dts/Bindings/gpio/gpio-xgene-sb.txt1
-rw-r--r--dts/Bindings/gpio/gpio-xilinx.txt2
-rw-r--r--dts/Bindings/gpio/gpio-xlp.txt1
-rw-r--r--dts/Bindings/gpio/gpio-zynq.txt1
-rw-r--r--dts/Bindings/gpio/mediatek,mt7621-gpio.txt35
-rw-r--r--dts/Bindings/gpio/nintendo,hollywood-gpio.txt1
-rw-r--r--dts/Bindings/gpio/nvidia,tegra186-gpio.txt4
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt2
-rw-r--r--dts/Bindings/gpio/rockchip,rk3328-grf-gpio.txt32
-rw-r--r--dts/Bindings/gpio/snps-dwapb-gpio.txt1
-rw-r--r--dts/Bindings/hsi/omap-ssi.txt1
-rw-r--r--dts/Bindings/hwmon/npcm750-pwm-fan.txt84
-rw-r--r--dts/Bindings/i2c/i2c-aspeed.txt3
-rw-r--r--dts/Bindings/i2c/i2c-brcmstb.txt2
-rw-r--r--dts/Bindings/i2c/i2c-fsi.txt40
-rw-r--r--dts/Bindings/i2c/i2c-imx-lpi2c.txt1
-rw-r--r--dts/Bindings/i2c/i2c-jz4780.txt4
-rw-r--r--dts/Bindings/i2c/i2c-mpc.txt2
-rw-r--r--dts/Bindings/i2c/i2c-mux-pca954x.txt2
-rw-r--r--dts/Bindings/i2c/i2c-owl.txt27
-rw-r--r--dts/Bindings/i2c/i2c-pca-platform.txt2
-rw-r--r--dts/Bindings/i2c/i2c-pnx.txt2
-rw-r--r--dts/Bindings/i2c/i2c-pxa.txt3
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt5
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt4
-rw-r--r--dts/Bindings/iio/accel/adxl345.txt9
-rw-r--r--dts/Bindings/iio/accel/bma180.txt2
-rw-r--r--dts/Bindings/iio/accel/mma8452.txt2
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.txt1
-rw-r--r--dts/Bindings/iio/adc/at91-sama5d2_adc.txt9
-rw-r--r--dts/Bindings/iio/adc/avia-hx711.txt8
-rw-r--r--dts/Bindings/iio/adc/cpcap-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/fsl,imx25-gcq.txt1
-rw-r--r--dts/Bindings/iio/adc/max1027-adc.txt2
-rw-r--r--dts/Bindings/iio/adc/sigma-delta-modulator.txt2
-rw-r--r--dts/Bindings/iio/adc/sprd,sc27xx-adc.txt36
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/xilinx-xadc.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,ec-sm.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,orp-sm.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,ph-sm.txt1
-rw-r--r--dts/Bindings/iio/dac/ad5758.txt78
-rw-r--r--dts/Bindings/iio/gyroscope/invensense,mpu3050.txt1
-rw-r--r--dts/Bindings/iio/health/afe4403.txt1
-rw-r--r--dts/Bindings/iio/health/afe4404.txt1
-rw-r--r--dts/Bindings/iio/health/max30100.txt1
-rw-r--r--dts/Bindings/iio/health/max30102.txt1
-rw-r--r--dts/Bindings/iio/humidity/hts221.txt1
-rw-r--r--dts/Bindings/iio/imu/bmi160.txt1
-rw-r--r--dts/Bindings/iio/imu/inv_mpu6050.txt2
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt1
-rw-r--r--dts/Bindings/iio/light/apds9300.txt1
-rw-r--r--dts/Bindings/iio/light/apds9960.txt1
-rw-r--r--dts/Bindings/iio/light/isl29018.txt1
-rw-r--r--dts/Bindings/iio/light/isl29501.txt13
-rw-r--r--dts/Bindings/iio/light/opt3001.txt1
-rw-r--r--dts/Bindings/iio/light/tsl2583.txt1
-rw-r--r--dts/Bindings/iio/light/uvis25.txt1
-rw-r--r--dts/Bindings/iio/magnetometer/bmc150_magn.txt1
-rw-r--r--dts/Bindings/iio/pressure/bmp085.txt8
-rw-r--r--dts/Bindings/iio/pressure/zpa2326.txt2
-rw-r--r--dts/Bindings/iio/proximity/as3935.txt1
-rw-r--r--dts/Bindings/iio/proximity/sx9500.txt1
-rw-r--r--dts/Bindings/iio/sensorhub.txt1
-rw-r--r--dts/Bindings/iio/temperature/tmp007.txt2
-rw-r--r--dts/Bindings/infiniband/hisilicon-hns-roce.txt1
-rw-r--r--dts/Bindings/input/cypress,cyapa.txt2
-rw-r--r--dts/Bindings/input/cypress,tm2-touchkey.txt2
-rw-r--r--dts/Bindings/input/e3x0-button.txt2
-rw-r--r--dts/Bindings/input/elan_i2c.txt2
-rw-r--r--dts/Bindings/input/elants_i2c.txt2
-rw-r--r--dts/Bindings/input/hid-over-i2c.txt4
-rw-r--r--dts/Bindings/input/keys.txt8
-rw-r--r--dts/Bindings/input/qcom,pm8941-pwrkey.txt10
-rw-r--r--dts/Bindings/input/raydium_i2c_ts.txt1
-rw-r--r--dts/Bindings/input/rmi4/rmi_i2c.txt1
-rw-r--r--dts/Bindings/input/rmi4/rmi_spi.txt1
-rw-r--r--dts/Bindings/input/ti,palmas-pwrbutton.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ad7879.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ads7846.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ar1021.txt1
-rw-r--r--dts/Bindings/input/touchscreen/bu21029.txt35
-rw-r--r--dts/Bindings/input/touchscreen/chipone_icn8318.txt2
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/cyttsp.txt2
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.txt2
-rw-r--r--dts/Bindings/input/touchscreen/eeti.txt30
-rw-r--r--dts/Bindings/input/touchscreen/egalax-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ektf2127.txt2
-rw-r--r--dts/Bindings/input/touchscreen/exc3000.txt1
-rw-r--r--dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt1
-rw-r--r--dts/Bindings/input/touchscreen/goodix.txt1
-rw-r--r--dts/Bindings/input/touchscreen/hideep.txt1
-rw-r--r--dts/Bindings/input/touchscreen/max11801-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/melfas_mip4.txt1
-rw-r--r--dts/Bindings/input/touchscreen/resistive-adc-touch.txt30
-rw-r--r--dts/Bindings/input/touchscreen/samsung,s6sy761.txt2
-rw-r--r--dts/Bindings/input/touchscreen/silead_gsl1680.txt2
-rw-r--r--dts/Bindings/input/touchscreen/sis_i2c.txt2
-rw-r--r--dts/Bindings/input/touchscreen/st,stmfts.txt2
-rw-r--r--dts/Bindings/input/touchscreen/sx8654.txt1
-rw-r--r--dts/Bindings/input/touchscreen/touchscreen.txt3
-rw-r--r--dts/Bindings/input/touchscreen/tsc2007.txt2
-rw-r--r--dts/Bindings/input/touchscreen/zet6223.txt2
-rw-r--r--dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt1
-rw-r--r--dts/Bindings/interrupt-controller/al,alpine-msix.txt1
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt1
-rw-r--r--dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt3
-rw-r--r--dts/Bindings/interrupt-controller/atmel,aic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt3
-rw-r--r--dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt2
-rw-r--r--dts/Bindings/interrupt-controller/ingenic,intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/marvell,odmi-controller.txt2
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,cirq.txt2
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt3
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt1
-rw-r--r--dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt2
-rw-r--r--dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt6
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt3
-rw-r--r--dts/Bindings/interrupt-controller/riscv,cpu-intc.txt44
-rw-r--r--dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt2
-rw-r--r--dts/Bindings/interrupt-controller/sifive,plic-1.0.0.txt58
-rw-r--r--dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt1
-rw-r--r--dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt1
-rw-r--r--dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt4
-rw-r--r--dts/Bindings/interrupt-controller/technologic,ts4800.txt2
-rw-r--r--dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt1
-rw-r--r--dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu2
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.txt6
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.txt3
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.txt1
-rw-r--r--dts/Bindings/leds/backlight/pwm-backlight.txt34
-rw-r--r--dts/Bindings/leds/common.txt2
-rw-r--r--dts/Bindings/leds/leds-lm3692x.txt5
-rw-r--r--dts/Bindings/leds/leds-lt3593.txt32
-rw-r--r--dts/Bindings/mailbox/altera-mailbox.txt1
-rw-r--r--dts/Bindings/mailbox/fsl,mu.txt54
-rw-r--r--dts/Bindings/mailbox/mtk-gce.txt57
-rw-r--r--dts/Bindings/mailbox/ti,secure-proxy.txt50
-rw-r--r--dts/Bindings/media/cec-gpio.txt22
-rw-r--r--dts/Bindings/media/i2c/ak7375.txt8
-rw-r--r--dts/Bindings/media/i2c/aptina,mt9v111.txt46
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9807.txt9
-rw-r--r--dts/Bindings/media/i2c/nokia,smia.txt3
-rw-r--r--dts/Bindings/media/i2c/ov2680.txt46
-rw-r--r--dts/Bindings/media/i2c/ov5640.txt5
-rw-r--r--dts/Bindings/media/i2c/tc358743.txt2
-rw-r--r--dts/Bindings/media/nvidia,tegra-vde.txt11
-rw-r--r--dts/Bindings/media/qcom,camss.txt128
-rw-r--r--dts/Bindings/media/qcom,venus.txt1
-rw-r--r--dts/Bindings/media/rcar_vin.txt54
-rw-r--r--dts/Bindings/media/sh_mobile_ceu.txt1
-rw-r--r--dts/Bindings/media/video-interfaces.txt6
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.txt6
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt5
-rw-r--r--dts/Bindings/mfd/ac100.txt4
-rw-r--r--dts/Bindings/mfd/altera-a10sr.txt1
-rw-r--r--dts/Bindings/mfd/arizona.txt1
-rw-r--r--dts/Bindings/mfd/as3722.txt2
-rw-r--r--dts/Bindings/mfd/axp20x.txt8
-rw-r--r--dts/Bindings/mfd/bd9571mwv.txt1
-rw-r--r--dts/Bindings/mfd/bfticu.txt1
-rw-r--r--dts/Bindings/mfd/da9055.txt2
-rw-r--r--dts/Bindings/mfd/da9062.txt2
-rw-r--r--dts/Bindings/mfd/da9063.txt2
-rw-r--r--dts/Bindings/mfd/da9150.txt2
-rw-r--r--dts/Bindings/mfd/madera.txt102
-rw-r--r--dts/Bindings/mfd/max14577.txt1
-rw-r--r--dts/Bindings/mfd/max77686.txt1
-rw-r--r--dts/Bindings/mfd/max77693.txt1
-rw-r--r--dts/Bindings/mfd/max77802.txt1
-rw-r--r--dts/Bindings/mfd/max8998.txt2
-rw-r--r--dts/Bindings/mfd/motorola-cpcap.txt1
-rw-r--r--dts/Bindings/mfd/palmas.txt1
-rw-r--r--dts/Bindings/mfd/retu.txt1
-rw-r--r--dts/Bindings/mfd/rk808.txt1
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.txt62
-rw-r--r--dts/Bindings/mfd/samsung,sec-core.txt2
-rw-r--r--dts/Bindings/mfd/stmpe.txt1
-rw-r--r--dts/Bindings/mfd/tc3589x.txt1
-rw-r--r--dts/Bindings/mfd/tps65086.txt1
-rw-r--r--dts/Bindings/mfd/tps65910.txt2
-rw-r--r--dts/Bindings/mfd/tps65912.txt1
-rw-r--r--dts/Bindings/mfd/twl-familly.txt1
-rw-r--r--dts/Bindings/mfd/twl6040.txt1
-rw-r--r--dts/Bindings/mfd/wm831x.txt1
-rw-r--r--dts/Bindings/mips/cavium/cib.txt2
-rw-r--r--dts/Bindings/misc/aspeed,cvic.txt35
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt4
-rw-r--r--dts/Bindings/mmc/fsl-esdhc.txt1
-rw-r--r--dts/Bindings/mmc/mmc-spi-slot.txt2
-rw-r--r--dts/Bindings/mmc/pxa-mmc.txt6
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--dts/Bindings/mmc/sdhci-msm.txt7
-rw-r--r--dts/Bindings/mmc/sdhci-of-dwcmshc.txt20
-rw-r--r--dts/Bindings/mmc/sunxi-mmc.txt2
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt1
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt1
-rw-r--r--dts/Bindings/mtd/denali-nand.txt5
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt1
-rw-r--r--dts/Bindings/mtd/jedec,spi-nor.txt9
-rw-r--r--dts/Bindings/mtd/nand.txt6
-rw-r--r--dts/Bindings/mtd/nvidia-tegra20-nand.txt64
-rw-r--r--dts/Bindings/mtd/partition.txt46
-rw-r--r--dts/Bindings/mtd/partitions/brcm,trx.txt37
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt7
-rw-r--r--dts/Bindings/mtd/spear_smi.txt2
-rw-r--r--dts/Bindings/mtd/spi-nand.txt5
-rw-r--r--dts/Bindings/mux/adi,adgs1408.txt48
-rw-r--r--dts/Bindings/net/amd-xgbe.txt2
-rw-r--r--dts/Bindings/net/brcm,mdio-mux-iproc.txt7
-rw-r--r--dts/Bindings/net/btusb.txt1
-rw-r--r--dts/Bindings/net/can/holt_hi311x.txt1
-rw-r--r--dts/Bindings/net/can/microchip,mcp251x.txt1
-rw-r--r--dts/Bindings/net/can/xilinx_can.txt36
-rw-r--r--dts/Bindings/net/cpsw.txt1
-rw-r--r--dts/Bindings/net/davicom-dm9000.txt1
-rw-r--r--dts/Bindings/net/dsa/b53.txt8
-rw-r--r--dts/Bindings/net/dsa/ksz.txt4
-rw-r--r--dts/Bindings/net/dsa/marvell.txt1
-rw-r--r--dts/Bindings/net/dsa/realtek-smi.txt153
-rw-r--r--dts/Bindings/net/dsa/vitesse,vsc73xx.txt81
-rw-r--r--dts/Bindings/net/dwmac-sun8i.txt8
-rw-r--r--dts/Bindings/net/fsl-fman.txt25
-rw-r--r--dts/Bindings/net/hisilicon-hns-dsaf.txt1
-rw-r--r--dts/Bindings/net/ibm,emac.txt1
-rw-r--r--dts/Bindings/net/marvell-bt-8xxx.txt1
-rw-r--r--dts/Bindings/net/mediatek,mt7620-gsw.txt2
-rw-r--r--dts/Bindings/net/mediatek-bluetooth.txt35
-rw-r--r--dts/Bindings/net/mediatek-net.txt3
-rw-r--r--dts/Bindings/net/microchip,enc28j60.txt3
-rw-r--r--dts/Bindings/net/nfc/nxp-nci.txt1
-rw-r--r--dts/Bindings/net/nfc/pn533-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/pn544.txt3
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt1
-rw-r--r--dts/Bindings/net/nfc/st21nfca.txt2
-rw-r--r--dts/Bindings/net/nfc/st95hf.txt3
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt1
-rw-r--r--dts/Bindings/net/phy.txt2
-rw-r--r--dts/Bindings/net/qca,qca7000.txt1
-rw-r--r--dts/Bindings/net/qualcomm-bluetooth.txt29
-rw-r--r--dts/Bindings/net/ralink,rt2880-net.txt2
-rw-r--r--dts/Bindings/net/ralink,rt3050-esw.txt2
-rw-r--r--dts/Bindings/net/renesas,ravb.txt5
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt1
-rw-r--r--dts/Bindings/net/samsung-sxgbe.txt2
-rw-r--r--dts/Bindings/net/sh_eth.txt2
-rw-r--r--dts/Bindings/net/snps,dwc-qos-ethernet.txt2
-rw-r--r--dts/Bindings/net/stmmac.txt7
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt2
-rw-r--r--dts/Bindings/net/wireless/marvell-8xxx.txt1
-rw-r--r--dts/Bindings/net/wireless/ti,wl1251.txt2
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore,spi.txt4
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore.txt2
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt3
-rw-r--r--dts/Bindings/nvmem/sc27xx-efuse.txt52
-rw-r--r--dts/Bindings/pci/altera-pcie-msi.txt1
-rw-r--r--dts/Bindings/pci/altera-pcie.txt1
-rw-r--r--dts/Bindings/pci/brcm,iproc-pcie.txt1
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-ep.txt5
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-host.txt6
-rw-r--r--dts/Bindings/pci/faraday,ftpci100.txt1
-rw-r--r--dts/Bindings/pci/mobiveil-pcie.txt3
-rw-r--r--dts/Bindings/pci/pci-keystone.txt3
-rw-r--r--dts/Bindings/pci/ralink,rt3883-pci.txt3
-rw-r--r--dts/Bindings/phy/brcm,sr-pcie-phy.txt41
-rw-r--r--dts/Bindings/phy/phy-ath79-usb.txt4
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt6
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt14
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-pcie.txt24
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--dts/Bindings/pinctrl/actions,s900-pinctrl.txt10
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/berlin,pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/cirrus,madera-pinctrl.txt99
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt2
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra210-pinmux.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-bindings.txt6
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt7622.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-sx150x.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq8064-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8916-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8960-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8994-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8996-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt6
-rw-r--r--dts/Bindings/pinctrl/samsung-pinctrl.txt17
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt11
-rw-r--r--dts/Bindings/power/power_domain.txt8
-rw-r--r--dts/Bindings/power/reset/qcom,pon.txt45
-rw-r--r--dts/Bindings/power/supply/act8945a-charger.txt2
-rw-r--r--dts/Bindings/power/supply/bq24257.txt2
-rw-r--r--dts/Bindings/power/supply/lp8727_charger.txt1
-rw-r--r--dts/Bindings/power/supply/maxim,ds2760.txt26
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.txt1
-rw-r--r--dts/Bindings/power/supply/rt9455_charger.txt2
-rw-r--r--dts/Bindings/power/supply/sbs_sbs-battery.txt12
-rw-r--r--dts/Bindings/power/supply/sbs_sbs-charger.txt2
-rw-r--r--dts/Bindings/powerpc/4xx/akebono.txt2
-rw-r--r--dts/Bindings/powerpc/4xx/hsta.txt1
-rw-r--r--dts/Bindings/powerpc/4xx/ppc440spe-adma.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dcsr.txt7
-rw-r--r--dts/Bindings/powerpc/fsl/diu.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dma.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/ecm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mcm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mpc5121-psc.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/msi-pic.txt5
-rw-r--r--dts/Bindings/powerpc/fsl/pamu.txt2
-rw-r--r--dts/Bindings/powerpc/nintendo/wii.txt1
-rw-r--r--dts/Bindings/ptp/ptp-qoriq.txt15
-rw-r--r--dts/Bindings/pwm/pwm-fsl-ftm.txt5
-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt4
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt1
-rw-r--r--dts/Bindings/regulator/cpcap-regulator.txt1
-rw-r--r--dts/Bindings/regulator/max8997-regulator.txt2
-rw-r--r--dts/Bindings/regulator/palmas-pmic.txt1
-rw-r--r--dts/Bindings/regulator/pfuze100.txt86
-rw-r--r--dts/Bindings/regulator/qcom,rpmh-regulator.txt160
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.txt8
-rw-r--r--dts/Bindings/regulator/uniphier-regulator.txt57
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt7
-rw-r--r--dts/Bindings/remoteproc/ti,davinci-rproc.txt6
-rw-r--r--dts/Bindings/remoteproc/ti,keystone-rproc.txt6
-rw-r--r--dts/Bindings/reserved-memory/reserved-memory.txt2
-rw-r--r--dts/Bindings/reset/amlogic,meson-axg-audio-arb.txt21
-rw-r--r--dts/Bindings/reset/qcom,aoss-reset.txt52
-rw-r--r--dts/Bindings/reset/uniphier-reset.txt56
-rw-r--r--dts/Bindings/rtc/brcm,brcmstb-waketimer.txt2
-rw-r--r--dts/Bindings/rtc/isil,isl12057.txt3
-rw-r--r--dts/Bindings/rtc/isil,isl1219.txt29
-rw-r--r--dts/Bindings/rtc/rtc-cmos.txt1
-rw-r--r--dts/Bindings/rtc/rtc-ds1307.txt2
-rw-r--r--dts/Bindings/rtc/rtc-m41t80.txt1
-rw-r--r--dts/Bindings/rtc/rtc-omap.txt1
-rw-r--r--dts/Bindings/rtc/rtc-palmas.txt1
-rw-r--r--dts/Bindings/rtc/spear-rtc.txt2
-rw-r--r--dts/Bindings/rtc/sprd,sc27xx-rtc.txt1
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.txt2
-rw-r--r--dts/Bindings/rtc/stericsson,coh901331.txt1
-rw-r--r--dts/Bindings/security/tpm/st33zp24-i2c.txt1
-rw-r--r--dts/Bindings/security/tpm/st33zp24-spi.txt1
-rw-r--r--dts/Bindings/security/tpm/tpm_tis_mmio.txt2
-rw-r--r--dts/Bindings/serial/fsl-imx-uart.txt6
-rw-r--r--dts/Bindings/serial/maxim,max310x.txt2
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/nxp,sc16is7xx.txt4
-rw-r--r--dts/Bindings/serial/omap_serial.txt1
-rw-r--r--dts/Bindings/serial/qca,ar9330-uart.txt3
-rw-r--r--dts/Bindings/serial/renesas,rzn1-uart.txt10
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt19
-rw-r--r--dts/Bindings/serial/xlnx,opb-uartlite.txt23
-rw-r--r--dts/Bindings/slimbus/slim-ngd-qcom-ctrl.txt84
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/gpio.txt1
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt2
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt1
-rw-r--r--dts/Bindings/soc/mediatek/pwrap.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,geni-se.txt2
-rw-r--r--dts/Bindings/soc/qcom/qcom,glink.txt5
-rw-r--r--dts/Bindings/soc/qcom/rpmh-rsc.txt137
-rw-r--r--dts/Bindings/sound/ac97-bus.txt32
-rw-r--r--dts/Bindings/sound/amlogic,axg-fifo.txt23
-rw-r--r--dts/Bindings/sound/amlogic,axg-sound-card.txt124
-rw-r--r--dts/Bindings/sound/amlogic,axg-spdifout.txt20
-rw-r--r--dts/Bindings/sound/amlogic,axg-tdm-formatters.txt28
-rw-r--r--dts/Bindings/sound/amlogic,axg-tdm-iface.txt22
-rw-r--r--dts/Bindings/sound/atmel-i2s.txt11
-rw-r--r--dts/Bindings/sound/audio-graph-card.txt2
-rw-r--r--dts/Bindings/sound/cs35l33.txt2
-rw-r--r--dts/Bindings/sound/cs35l34.txt2
-rw-r--r--dts/Bindings/sound/cs35l35.txt2
-rw-r--r--dts/Bindings/sound/cs42l42.txt5
-rw-r--r--dts/Bindings/sound/da7218.txt2
-rw-r--r--dts/Bindings/sound/da7219.txt2
-rw-r--r--dts/Bindings/sound/dioo,dio2125.txt12
-rw-r--r--dts/Bindings/sound/everest,es7134.txt7
-rw-r--r--dts/Bindings/sound/everest,es7241.txt28
-rw-r--r--dts/Bindings/sound/fsl,ssi.txt2
-rw-r--r--dts/Bindings/sound/marvell,pxa2xx-ac97.txt27
-rw-r--r--dts/Bindings/sound/mrvl,pxa-ssp.txt16
-rw-r--r--dts/Bindings/sound/mrvl,pxa2xx-pcm.txt15
-rw-r--r--dts/Bindings/sound/name-prefix.txt24
-rw-r--r--dts/Bindings/sound/omap-dmic.txt1
-rw-r--r--dts/Bindings/sound/omap-mcbsp.txt1
-rw-r--r--dts/Bindings/sound/omap-mcpdm.txt1
-rw-r--r--dts/Bindings/sound/qcom,apq8096.txt15
-rw-r--r--dts/Bindings/sound/qcom,msm8916-wcd-analog.txt1
-rw-r--r--dts/Bindings/sound/qcom,q6adm.txt6
-rw-r--r--dts/Bindings/sound/qcom,q6afe.txt6
-rw-r--r--dts/Bindings/sound/qcom,q6asm.txt6
-rw-r--r--dts/Bindings/sound/qcom,sdm845.txt80
-rw-r--r--dts/Bindings/sound/qcom,wcd9335.txt123
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt1
-rw-r--r--dts/Bindings/sound/rockchip-i2s.txt1
-rw-r--r--dts/Bindings/sound/rt5514.txt1
-rw-r--r--dts/Bindings/sound/rt5682.txt50
-rw-r--r--dts/Bindings/sound/sgtl5000.txt2
-rw-r--r--dts/Bindings/sound/simple-amplifier.txt12
-rw-r--r--dts/Bindings/sound/tas571x.txt1
-rw-r--r--dts/Bindings/sound/ts3a227e.txt1
-rw-r--r--dts/Bindings/sound/ux500-msp.txt1
-rw-r--r--dts/Bindings/sound/wm8994.txt7
-rw-r--r--dts/Bindings/spi/fsl-spi.txt2
-rw-r--r--dts/Bindings/spi/sh-hspi.txt2
-rw-r--r--dts/Bindings/spi/sh-msiof.txt2
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.txt6
-rw-r--r--dts/Bindings/spi/spi-cadence.txt1
-rw-r--r--dts/Bindings/spi/spi-fsl-lpspi.txt1
-rw-r--r--dts/Bindings/spi/spi-rockchip.txt1
-rw-r--r--dts/Bindings/spi/spi-rspi.txt2
-rw-r--r--dts/Bindings/spi/spi-uniphier.txt22
-rw-r--r--dts/Bindings/spi/spi-xilinx.txt1
-rw-r--r--dts/Bindings/spi/spi-xlp.txt1
-rw-r--r--dts/Bindings/spi/spi-zynqmp-qspi.txt1
-rw-r--r--dts/Bindings/sram/sram.txt2
-rw-r--r--dts/Bindings/sram/sunxi-sram.txt31
-rw-r--r--dts/Bindings/staging/iio/adc/spear-adc.txt2
-rw-r--r--dts/Bindings/thermal/armada-thermal.txt5
-rw-r--r--dts/Bindings/thermal/brcm,avs-tmon.txt1
-rw-r--r--dts/Bindings/thermal/exynos-thermal.txt1
-rw-r--r--dts/Bindings/thermal/qcom-tsens.txt31
-rw-r--r--dts/Bindings/thermal/thermal.txt11
-rw-r--r--dts/Bindings/timer/altr,timer-1.0.txt1
-rw-r--r--dts/Bindings/timer/fsl,gtm.txt1
-rw-r--r--dts/Bindings/timer/marvell,orion-timer.txt1
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt34
-rw-r--r--dts/Bindings/timer/snps,arc-timer.txt4
-rw-r--r--dts/Bindings/timer/st,spear-timer.txt2
-rw-r--r--dts/Bindings/timer/ti,c64x+timer64.txt1
-rw-r--r--dts/Bindings/timer/ti,davinci-timer.txt37
-rw-r--r--dts/Bindings/ufs/ufs-hisi.txt41
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt10
-rw-r--r--dts/Bindings/usb/dwc3.txt6
-rw-r--r--dts/Bindings/usb/fsl-usb.txt2
-rw-r--r--dts/Bindings/usb/maxim,max3421.txt3
-rw-r--r--dts/Bindings/usb/npcm7xx-usb.txt18
-rw-r--r--dts/Bindings/usb/richtek,rt1711h.txt2
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-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts5
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-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts29
-rw-r--r--dts/src/arm64/renesas/r8a77980-v3hsk.dts23
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi403
-rw-r--r--dts/src/arm64/renesas/r8a77990-ebisu.dts37
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi169
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts133
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi251
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi34
-rw-r--r--dts/src/arm64/renesas/salvator-x.dtsi7
-rw-r--r--dts/src/arm64/renesas/salvator-xs.dtsi7
-rw-r--r--dts/src/arm64/renesas/ulcb-kf.dtsi5
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi11
-rw-r--r--dts/src/arm64/rockchip/rk3328-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi44
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb-act8846.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3368-geekbox.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-px5-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-r88.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi47
-rw-r--r--dts/src/arm64/rockchip/rk3399-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3399-ficus.dts599
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts86
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-bob.dts79
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-chromebook.dtsi397
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts86
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi367
-rw-r--r--dts/src/arm64/rockchip/rk3399-op1-opp.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi40
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts41
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi44
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi161
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts1
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts1
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi2
-rw-r--r--dts/src/arm64/sprd/sc2731.dtsi44
-rw-r--r--dts/src/arm64/sprd/sc9860.dtsi2
-rw-r--r--dts/src/arm64/sprd/whale2.dtsi6
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi31
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi87
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts36
-rw-r--r--dts/src/arm64/ti/k3-am654.dtsi115
-rw-r--r--dts/src/arm64/xilinx/avnet-ultra96-rev1.dts19
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi137
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts154
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts12
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi2
-rw-r--r--dts/src/h8300/h8300h_sim.dts2
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi19
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi32
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts10
-rw-r--r--dts/src/mips/qca/ar9132.dtsi2
-rw-r--r--dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts3
-rw-r--r--dts/src/mips/qca/ar9331.dtsi2
-rw-r--r--dts/src/mips/qca/ar9331_dpt_module.dts5
-rw-r--r--dts/src/mips/qca/ar9331_dragino_ms14.dts5
-rw-r--r--dts/src/mips/qca/ar9331_omega.dts5
-rw-r--r--dts/src/mips/qca/ar9331_tl_mr3020.dts5
-rw-r--r--dts/src/powerpc/ac14xx.dts20
-rw-r--r--dts/src/powerpc/fsl/kmcent2.dts2
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3l-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/t2080rdb.dts4
-rw-r--r--dts/src/powerpc/fsl/t4240rdb.dts8
-rw-r--r--dts/src/powerpc/pdm360ng.dts2
1200 files changed, 29720 insertions, 8347 deletions
diff --git a/dts/Bindings/arm/adapteva.txt b/dts/Bindings/arm/adapteva.txt
deleted file mode 100644
index 1d8af9e..0000000
--- a/dts/Bindings/arm/adapteva.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Adapteva Platforms Device Tree Bindings
----------------------------------------
-
-Parallella board
-
-Required root node properties:
- - compatible = "adapteva,parallella";
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 6988056..b5c2b5c 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -41,6 +41,14 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s805x", "amlogic,meson-gxl";
+
+Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s905w", "amlogic,meson-gxl";
+
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
@@ -79,6 +87,11 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
+ - "amlogic,p241" (Meson gxl s805x)
+
+ - "amlogic,p281" (Meson gxl s905w)
+ - "oranth,tx3-mini" (Meson gxl s905w)
+
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)
diff --git a/dts/Bindings/arm/atmel-pmc.txt b/dts/Bindings/arm/atmel-pmc.txt
deleted file mode 100644
index 795cc78..0000000
--- a/dts/Bindings/arm/atmel-pmc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-pmc".
- <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
- at91sam9x5, sama5d3
-
-- reg: Should contain PMC registers location and length
-
-Examples:
- pmc: pmc@fffffc00 {
- compatible = "atmel,at91rm9200-pmc";
- reg = <0xfffffc00 0x100>;
- };
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index c052caa..104cc9b 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -189,7 +189,11 @@ Power-Down (SRPD), among other things.
Required properties:
- compatible : should contain one of these
+ "brcm,brcmstb-memc-ddr-rev-b.2.1"
"brcm,brcmstb-memc-ddr-rev-b.2.2"
+ "brcm,brcmstb-memc-ddr-rev-b.2.3"
+ "brcm,brcmstb-memc-ddr-rev-b.3.0"
+ "brcm,brcmstb-memc-ddr-rev-b.3.1"
"brcm,brcmstb-memc-ddr"
- reg : the MEMC DDR register range
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 15ac8e8..5d1ad09 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -39,6 +39,8 @@ its hardware characteristcs.
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
+ - Coresight Address Translation Unit (CATU)
+ "arm,coresight-catu", "arm,primecell";
* reg: physical base address and length of the register
set(s) of the component.
@@ -84,8 +86,15 @@ its hardware characteristcs.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
- (embedded trace router)
+ (embedded trace router). This property is obsolete. The buffer size
+ can be configured dynamically via buffer_size property in sysfs.
+ * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
+ use the SG mode on this system.
+
+* Optional property for CATU :
+ * interrupts : Exactly one SPI may be listed for reporting the address
+ error
Example:
@@ -118,6 +127,35 @@ Example:
};
};
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator2_out_port0>;
+ };
+ };
+
+ /* CATU link represented by output port */
+ port@1 {
+ reg = <1>;
+ etr_out_port: endpoint {
+ remote-endpoint = <&catu_in_port>;
+ };
+ };
+ };
+ };
+
2. Links
replicator {
/* non-configurable replicators don't show up on the
@@ -247,5 +285,23 @@ Example:
};
};
+5. CATU
+
+ catu@207e0000 {
+ compatible = "arm,coresight-catu", "arm,primecell";
+ reg = <0 0x207e0000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ port {
+ catu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&etr_out_port>;
+ };
+ };
+ };
+
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 7809fbe..9b5685a 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -94,7 +94,7 @@ cpus {
};
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 29e1dc5..96dfccc 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -183,6 +183,7 @@ described below.
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"nvidia,tegra186-denver"
+ "nvidia,tegra194-carmel"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
@@ -219,6 +220,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
+ "renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
index 669808b..6dd6f39 100644
--- a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
+++ b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -18,9 +18,6 @@ Required properties:
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
-- interrupt-parent: Should be the phandle for the interrupt controller of
- the CPU the device tree is intended to be used on. This
- is either the node of the GIC or NVIC controller.
Example:
mscm_ir: interrupt-controller@40001800 {
diff --git a/dts/Bindings/arm/freescale/m4if.txt b/dts/Bindings/arm/freescale/m4if.txt
new file mode 100644
index 0000000..93bd7b8
--- /dev/null
+++ b/dts/Bindings/arm/freescale/m4if.txt
@@ -0,0 +1,12 @@
+* Freescale Multi Master Multi Memory Interface (M4IF) module
+
+Required properties:
+- compatible : Should be "fsl,imx51-m4if"
+- reg : Address and length of the register set for the device
+
+Example:
+
+m4if: m4if@83fd8000 {
+ compatible = "fsl,imx51-m4if";
+ reg = <0x83fd8000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/tigerp.txt b/dts/Bindings/arm/freescale/tigerp.txt
new file mode 100644
index 0000000..19e2aad
--- /dev/null
+++ b/dts/Bindings/arm/freescale/tigerp.txt
@@ -0,0 +1,12 @@
+* Freescale Tigerp platform module
+
+Required properties:
+- compatible : Should be "fsl,imx51-tigerp"
+- reg : Address and length of the register set for the device
+
+Example:
+
+tigerp: tigerp@83fa0000 {
+ compatible = "fsl,imx51-tigerp";
+ reg = <0x83fa0000 0x28>;
+};
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index cdb9dd7..8a1baa2 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX6SLL EVK board
+Required root node properties:
+ - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
Generic i.MX boards
-------------------
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index 7a59133..2c73847 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -237,8 +237,8 @@ processor idle states, defined as device tree nodes, are listed.
Value type: <stringlist>
Usage and definition depend on ARM architecture version.
# On ARM v8 64-bit this property is required and must
- be one of:
- - "psci" (see bindings in [2])
+ be:
+ - "psci"
# On ARM 32-bit systems this property is optional
The nodes describing the idle states (state) can only be defined within the
diff --git a/dts/Bindings/arm/insignal-boards.txt b/dts/Bindings/arm/insignal-boards.txt
deleted file mode 100644
index 524c3dc..0000000
--- a/dts/Bindings/arm/insignal-boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Insignal's Exynos4210 based Origen evaluation board
-
-Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
-
-Required root node properties:
- - compatible = should be one or more of the following.
- (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
- (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
diff --git a/dts/Bindings/arm/marvell/ap806-system-controller.txt b/dts/Bindings/arm/marvell/ap806-system-controller.txt
index 0b88744..3fd21bb 100644
--- a/dts/Bindings/arm/marvell/ap806-system-controller.txt
+++ b/dts/Bindings/arm/marvell/ap806-system-controller.txt
@@ -2,14 +2,17 @@ Marvell Armada AP806 System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains a system controller, which provides a number
-registers giving access to numerous features: clocks, pin-muxing and
-many other SoC configuration items. This DT binding allows to describe
-this system controller.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the AP806 system controller
+ - reg: register area of the AP806 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 {
gpio-ranges = <&ap_pinctrl 0 0 19>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-ap806-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel, while positive
+ IDs refer to each CPU.
+
+Example:
+ap_syscon1: system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ ap_thermal: thermal-sensor@80 {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/marvell/armada-37xx.txt b/dts/Bindings/arm/marvell/armada-37xx.txt
index 35c3c34..eddde4f 100644
--- a/dts/Bindings/arm/marvell/armada-37xx.txt
+++ b/dts/Bindings/arm/marvell/armada-37xx.txt
@@ -33,3 +33,18 @@ nb_pm: syscon@14000 {
compatible = "marvell,armada-3700-nb-pm", "syscon";
reg = <0x14000 0x60>;
}
+
+AVS
+---
+
+For AVS an other component is needed:
+
+Required properties:
+- compatible : should contain "marvell,armada-3700-avs", "syscon";
+- reg : the register start and length for the AVS
+
+Example:
+avs: avs@11500 {
+ compatible = "marvell,armada-3700-avs", "syscon";
+ reg = <0x11500 0x40>;
+}
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller.txt
index 29cdbae..81ce742 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller.txt
@@ -1,15 +1,18 @@
-Marvell Armada CP110 System Controller 0
-========================================
+Marvell Armada CP110 System Controller
+======================================
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains two sets of system control registers, System
-Controller 0 and System Controller 1. This Device Tree binding allows
-to describe the first system controller, which provides registers to
-configure various aspects of the SoC.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the CP110 system controller 0
+ - reg: register area of the CP110 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -163,26 +166,60 @@ Required properties:
Example:
-cpm_syscon0: system-controller@440000 {
+CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
- cpm_clk: clock {
+ CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
- cpm_pinctrl: pinctrl {
+ CP110_LABEL(pinctrl): pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
- cpm_gpio1: gpio@100 {
+ CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-cp110-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel.
+
+Example:
+CP110_LABEL(syscon1): system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ CP110_LABEL(thermal): thermal-sensor@70 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x70 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 7d21ab3..8f260e5 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -11,6 +11,7 @@ compatible: Must contain one of
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
+ "mediatek,mt6765"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
@@ -41,12 +42,18 @@ Supported boards:
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+- Evaluation board for MT6765(Helio P22):
+ Required root node properties:
+ - compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+- Mediatek X20 Development Board:
+ Required root node properties:
+ - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
@@ -59,9 +66,6 @@ Supported boards:
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
-- Reference board for MT7623n with NAND:
- Required root node properties:
- - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
diff --git a/dts/Bindings/arm/msm/qcom,llcc.txt b/dts/Bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..5e85749
--- /dev/null
+++ b/dts/Bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,26 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the the size of the register region.
+
+Example:
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ };
diff --git a/dts/Bindings/arm/omap/crossbar.txt b/dts/Bindings/arm/omap/crossbar.txt
index ecb360e..4cd5d87 100644
--- a/dts/Bindings/arm/omap/crossbar.txt
+++ b/dts/Bindings/arm/omap/crossbar.txt
@@ -10,7 +10,6 @@ Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- interrupt-controller: indicates that this block is an interrupt controller.
-- interrupt-parent: the interrupt controller this block is connected to.
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
diff --git a/dts/Bindings/arm/omap/l4.txt b/dts/Bindings/arm/omap/l4.txt
index b4f8a16..6816adc 100644
--- a/dts/Bindings/arm/omap/l4.txt
+++ b/dts/Bindings/arm/omap/l4.txt
@@ -7,6 +7,7 @@ Required properties:
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
+ Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
@@ -15,11 +16,21 @@ Required properties:
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
+- reg : registers link agent and interconnect agent and access protection
+- reg-names : "la" for link agent, "ia0" to "ia3" for one to three
+ interconnect agent instances, "ap" for access if it exists
Examples:
-l4: l4@48000000 {
- compatible "ti,omap2-l4", "simple-bus";
+l4: interconnect@48000000 {
+ compatible "ti,omap4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 1c1d62d..acfd3c7 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -1,5 +1,10 @@
Rockchip platforms device tree bindings
---------------------------------------
+
+- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
+ Required root node properties:
+ - compatible = "vamrs,ficus", "rockchip,rk3399";
+
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@@ -66,6 +71,15 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
+- Google Bob (Asus Chromebook Flip C101PA):
+ Required root node properties:
+ compatible = "google,bob-rev13", "google,bob-rev12",
+ "google,bob-rev11", "google,bob-rev10",
+ "google,bob-rev9", "google,bob-rev8",
+ "google,bob-rev7", "google,bob-rev6",
+ "google,bob-rev5", "google,bob-rev4",
+ "google,bob", "google,gru", "rockchip,rk3399";
+
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt
index 1668578..433bfd7 100644
--- a/dts/Bindings/arm/samsung/pmu.txt
+++ b/dts/Bindings/arm/samsung/pmu.txt
@@ -40,9 +40,6 @@ following properties:
- #interrupt-cells: must be identical to the that of the parent interrupt
controller.
-- interrupt-parent: a phandle indicating which interrupt controller
- this PMU signals interrupts to.
-
Optional nodes:
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 6970f30..56021bf 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -1,7 +1,10 @@
-* Samsung's Exynos SoC based boards
+* Samsung's Exynos and S5P SoC based boards
Required root node properties:
- compatible = should be one or more of the following.
+ - "samsung,aries" - for S5PV210-based Samsung Aries board.
+ - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
+ - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index d8cf740..89b4a38 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
-
+ - RZ/N1D (R9A06G032)
+ compatible = "renesas,r9a06g032"
Boards:
@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
+ - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
diff --git a/dts/Bindings/arm/ti/k3.txt b/dts/Bindings/arm/ti/k3.txt
new file mode 100644
index 0000000..6a059ca
--- /dev/null
+++ b/dts/Bindings/arm/ti/k3.txt
@@ -0,0 +1,23 @@
+Texas Instruments K3 Multicore SoC architecture device tree bindings
+--------------------------------------------------------------------
+
+Platforms based on Texas Instruments K3 Multicore SoC architecture
+shall follow the following scheme:
+
+SoCs
+----
+
+Each device tree root node must specify which exact SoC in K3 Multicore SoC
+architecture it uses, using one of the following compatible values:
+
+- AM654
+ compatible = "ti,am654";
+
+Boards
+------
+
+In addition, each device tree root node must specify which one or more
+of the following board-specific compatible values:
+
+- AM654 EVM
+ compatible = "ti,am654-evm", "ti,am654";
diff --git a/dts/Bindings/arm/xilinx.txt b/dts/Bindings/arm/xilinx.txt
index b9043bc..26fe5ec 100644
--- a/dts/Bindings/arm/xilinx.txt
+++ b/dts/Bindings/arm/xilinx.txt
@@ -8,18 +8,38 @@ Required root node properties:
Additional compatible strings:
-- Xilinx internal board cc108
+- Adapteva Parallella board
+ "adapteva,parallella"
+
+- Avnet MicroZed board
+ "avnet,zynq-microzed"
+ "xlnx,zynq-microzed"
+
+- Avnet ZedBoard board
+ "avnet,zynq-zed"
+ "xlnx,zynq-zed"
+
+- Digilent Zybo board
+ "digilent,zynq-zybo"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+- Xilinx CC108 internal board
"xlnx,zynq-cc108"
-- Xilinx internal board zc770 with different FMC cards
+- Xilinx ZC702 internal board
+ "xlnx,zynq-zc702"
+
+- Xilinx ZC706 internal board
+ "xlnx,zynq-zc706"
+
+- Xilinx ZC770 internal board, with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
-- Digilent Zybo Z7 board
- "digilent,zynq-zybo-z7"
-
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index c760ecb..5d5bd45 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -17,7 +17,6 @@ Required properties:
- "marvell,armada-380-ahci"
- "marvell,armada-3700-ahci"
- "snps,dwc-ahci"
- - "snps,exynos5440-ahci"
- "snps,spear-ahci"
- "generic-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
@@ -30,6 +29,7 @@ compatible:
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
+- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
diff --git a/dts/Bindings/ata/fsl-sata.txt b/dts/Bindings/ata/fsl-sata.txt
index b46bcf4..fd63bb3 100644
--- a/dts/Bindings/ata/fsl-sata.txt
+++ b/dts/Bindings/ata/fsl-sata.txt
@@ -16,7 +16,6 @@ Required properties:
4 for controller @ 0x1b000
Optional properties:
-- interrupt-parent : optional, if needed for interrupt mapping
- reg : <registers mapping>
Example:
diff --git a/dts/Bindings/ata/pata-arasan.txt b/dts/Bindings/ata/pata-arasan.txt
index 2aff154..872edc1 100644
--- a/dts/Bindings/ata/pata-arasan.txt
+++ b/dts/Bindings/ata/pata-arasan.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: "arasan,cf-spear1340"
- reg: Address range of the CF registers
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupt: Should contain the CF interrupt number
- clock-frequency: Interface clock rate, in Hz, one of
25000000
diff --git a/dts/Bindings/ata/sata_rcar.txt b/dts/Bindings/ata/sata_rcar.txt
index e20eac7..4268e17 100644
--- a/dts/Bindings/ata/sata_rcar.txt
+++ b/dts/Bindings/ata/sata_rcar.txt
@@ -8,6 +8,7 @@ Required properties:
- "renesas,sata-r8a7791" for R-Car M2-W
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
+ - "renesas,sata-r8a77965" for R-Car M3-N
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
- "renesas,rcar-sata" is deprecated
diff --git a/dts/Bindings/board/fsl-board.txt b/dts/Bindings/board/fsl-board.txt
index fb7b03e..eb52f6b 100644
--- a/dts/Bindings/board/fsl-board.txt
+++ b/dts/Bindings/board/fsl-board.txt
@@ -29,7 +29,6 @@ Required properties:
- reg: should contain the address and the length of the FPGA register set.
Optional properties:
-- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts: should specify event (wakeup) IRQ.
Example (P1022DS):
diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt
index 8a6c3c2..729def6 100644
--- a/dts/Bindings/bus/brcm,gisb-arb.txt
+++ b/dts/Bindings/bus/brcm,gisb-arb.txt
@@ -9,8 +9,6 @@ Required properties:
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
"brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this arbiter gets interrupt line from
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
the parent interrupt controller
diff --git a/dts/Bindings/bus/sun50i-de2-bus.txt b/dts/Bindings/bus/sun50i-de2-bus.txt
new file mode 100644
index 0000000..87dfb33
--- /dev/null
+++ b/dts/Bindings/bus/sun50i-de2-bus.txt
@@ -0,0 +1,37 @@
+Device tree bindings for Allwinner A64 DE2 bus
+
+The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
+to be claimed for enabling the access.
+
+Required properties:
+
+ - compatible: Should contain "allwinner,sun50i-a64-de2"
+ - reg: A resource specifier for the register space
+ - #address-cells: Must be set to 1
+ - #size-cells: Must be set to 1
+ - ranges: Must be set up to map the address space inside the
+ DE2, for the sub-blocks of DE2.
+ - allwinner,sram: the SRAM that needs to be claimed
+
+Example:
+
+ de2@1000000 {
+ compatible = "allwinner,sun50i-a64-de2";
+ reg = <0x1000000 0x400000>;
+ allwinner,sram = <&de2_sram 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000000 0x400000>;
+
+ display_clocks: clock@0 {
+ compatible = "allwinner,sun50i-a64-de2-clk";
+ reg = <0x0 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt
index d8ed5b7..91dc233 100644
--- a/dts/Bindings/bus/ti-sysc.txt
+++ b/dts/Bindings/bus/ti-sysc.txt
@@ -36,6 +36,7 @@ Required standard properties:
"ti,sysc-omap-aes"
"ti,sysc-mcasp"
"ti,sysc-usb-host-fs"
+ "ti,sysc-dra7-mcan"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
diff --git a/dts/Bindings/clock/actions,s900-cmu.txt b/dts/Bindings/clock/actions,owl-cmu.txt
index 93e4fb8..d1e60d2 100644
--- a/dts/Bindings/clock/actions,s900-cmu.txt
+++ b/dts/Bindings/clock/actions,owl-cmu.txt
@@ -1,12 +1,14 @@
-* Actions S900 Clock Management Unit (CMU)
+* Actions Semi Owl Clock Management Unit (CMU)
-The Actions S900 clock management unit generates and supplies clock to various
-controllers within the SoC. The clock binding described here is applicable to
-S900 SoC.
+The Actions Semi Owl Clock Management Unit generates and supplies clock
+to various controllers within the SoC. The clock binding described here is
+applicable to S900 and S700 SoC's.
Required Properties:
-- compatible: should be "actions,s900-cmu"
+- compatible: should be one of the following,
+ "actions,s900-cmu"
+ "actions,s700-cmu"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
@@ -15,16 +17,16 @@ Required Properties:
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/actions,s900-cmu.h header and can be used in device
-tree sources.
+All available clocks are defined as preprocessor macros in corresponding
+dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
+used in device tree sources.
External clocks:
The hosc clock used as input for the plls is generated outside the SoC. It is
expected that it is defined using standard clock bindings as "hosc".
-Actions S900 CMU also requires one more clock:
+Actions Semi S900 CMU also requires one more clock:
- "losc" - internal low frequency oscillator
Example: Clock Management Unit node:
diff --git a/dts/Bindings/clock/amlogic,axg-audio-clkc.txt b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
new file mode 100644
index 0000000..61777ad
--- /dev/null
+++ b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
@@ -0,0 +1,56 @@
+* Amlogic AXG Audio Clock Controllers
+
+The Amlogic AXG audio clock controller generates and supplies clock to the
+other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+devices.
+
+Required Properties:
+
+- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
+- reg : physical base address of the clock controller and length of
+ memory mapped region.
+- clocks : a list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+- clock-names : must contain the following:
+ * "pclk" - Main peripheral bus clock
+ may contain the following:
+ * "mst_in[0-7]" - 8 input plls to generate clock signals
+ * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
+ components.
+ * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
+ components.
+- resets : phandle of the internal reset line
+- #clock-cells : should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
+used in device tree sources.
+
+Example:
+
+clkc_audio: clock-controller@0 {
+ compatible = "amlogic,axg-audio-clkc";
+ reg = <0x0 0x0 0x0 0xb4>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc CLKID_AUDIO>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL3>,
+ <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_GP0_PLL>;
+ clock-names = "pclk",
+ "mst_in0",
+ "mst_in1",
+ "mst_in2",
+ "mst_in3",
+ "mst_in4",
+ "mst_in5",
+ "mst_in6",
+ "mst_in7";
+ resets = <&reset RESET_AUDIO>;
+};
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 51c259a..8f8f950 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -17,14 +17,13 @@ Required properties:
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
- "atmel,at91rm9200-pmc" or
- "atmel,at91sam9g45-pmc" or
- "atmel,at91sam9n12-pmc" or
- "atmel,at91sam9x5-pmc" or
- "atmel,sama5d3-pmc":
+ "atmel,<chip>-pmc":
at91 PMC (Power Management Controller)
All at91 specific clocks (clocks defined below) must be child
node of the PMC node.
+ <chip> can be: at91rm9200, at91sam9260, at91sam9261,
+ at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5,
+ sama5d2, sama5d3 or sama5d4.
"atmel,at91sam9x5-clk-slow" (under sckc node)
or
@@ -91,6 +90,9 @@ Required properties:
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
and can be used by peripheral clock or generic clock
+ "atmel,sama5d2-clk-i2s-mux" (under pmc node):
+ at91 I2S clock source selection
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -180,7 +182,6 @@ For example:
};
Required properties for main clock internal RC oscillator:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- clock-frequency : define the internal RC oscillator frequency.
@@ -197,7 +198,6 @@ For example:
};
Required properties for main clock oscillator:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
@@ -218,7 +218,6 @@ For example:
};
Required properties for main clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main clk sources (see atmel datasheet).
@@ -233,7 +232,6 @@ For example:
};
Required properties for master clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<3>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock sources (see atmel datasheet) phandles.
@@ -292,7 +290,6 @@ For example:
Required properties for pll clocks:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<1>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock phandle.
@@ -348,7 +345,6 @@ For example:
};
Required properties for programmable clocks:
-- interrupt-parent : must reference the PMC node.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the programmable clock source phandles.
@@ -451,7 +447,6 @@ For example:
Required properties for utmi clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock source phandle.
@@ -507,3 +502,35 @@ For example:
atmel,clk-output-range = <0 83000000>;
};
};
+
+Required properties for I2S mux clocks:
+- #size-cells : shall be 0 (reg is used to encode I2S bus id).
+- #address-cells : shall be 1 (reg is used to encode I2S bus id).
+- name: device tree node describing a specific mux clock.
+ * #clock-cells : from common clock binding; shall be set to 0.
+ * clocks : shall be the mux clock parent phandles; shall be 2 phandles:
+ peripheral and generated clock; the first phandle shall belong to the
+ peripheral clock and the second one shall belong to the generated
+ clock; "clock-indices" property can be user to specify
+ the correct order.
+ * reg: I2S bus id of the corresponding mux clock.
+ e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
+
+For example:
+ i2s_clkmux {
+ compatible = "atmel,sama5d2-clk-i2s-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2s0muxck: i2s0_muxclk {
+ clocks = <&i2s0_clk>, <&i2s0_gclk>;
+ #clock-cells = <0>;
+ reg = <0>;
+ };
+
+ i2s1muxck: i2s1_muxclk {
+ clocks = <&i2s1_clk>, <&i2s1_gclk>;
+ #clock-cells = <0>;
+ reg = <1>;
+ };
+ };
diff --git a/dts/Bindings/clock/exynos5440-clock.txt b/dts/Bindings/clock/exynos5440-clock.txt
deleted file mode 100644
index c7d227c..0000000
--- a/dts/Bindings/clock/exynos5440-clock.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Samsung Exynos5440 Clock Controller
-
-The Exynos5440 clock controller generates and supplies clock to various
-controllers within the Exynos5440 SoC.
-
-Required Properties:
-
-- compatible: should be "samsung,exynos5440-clock".
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5440.h header and can be used in device
-tree sources.
-
-Example: An example of a clock controller node is listed below.
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5440-clock";
- reg = <0x160000 0x10000>;
- #clock-cells = <1>;
- };
diff --git a/dts/Bindings/clock/maxim,max9485.txt b/dts/Bindings/clock/maxim,max9485.txt
new file mode 100644
index 0000000..61bec11
--- /dev/null
+++ b/dts/Bindings/clock/maxim,max9485.txt
@@ -0,0 +1,59 @@
+Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
+
+This device exposes 4 clocks in total:
+
+- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
+- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
+ frequencies
+- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
+
+MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
+requests.
+
+Required properties:
+- compatible: "maxim,max9485"
+- clocks: Input clock, must provice 27.000 MHz
+- clock-names: Must be set to "xclk"
+- #clock-cells: From common clock binding; shall be set to 1
+
+Optional properties:
+- reset-gpios: GPIO descriptor connected to the #RESET input pin
+- vdd-supply: A regulator node for Vdd
+- clock-output-names: Name of output clocks, as defined in common clock
+ bindings
+
+If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
+and "clkout2".
+
+Clocks are defined as preprocessor macros in the dt-binding header.
+
+Example:
+
+ #include <dt-bindings/clock/maxim,max9485.h>
+
+ xo-27mhz: xo-27mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ &i2c0 {
+ max9485: audio-clock@63 {
+ reg = <0x63>;
+ compatible = "maxim,max9485";
+ clock-names = "xclk";
+ clocks = <&xo-27mhz>;
+ reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&3v3-reg>;
+ #clock-cells = <1>;
+ };
+ };
+
+ // Clock consumer node
+
+ foo@0 {
+ compatible = "bar,foo";
+ /* ... */
+ clock-names = "foo-input-clk";
+ clocks = <&max9485 MAX9485_CLKOUT1>;
+ };
diff --git a/dts/Bindings/clock/qcom,dispcc.txt b/dts/Bindings/clock/qcom,dispcc.txt
new file mode 100644
index 0000000..d639e18
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc.txt
@@ -0,0 +1,19 @@
+Qualcomm Technologies, Inc. Display Clock Controller Binding
+------------------------------------------------------------
+
+Required properties :
+
+- compatible : shall contain "qcom,sdm845-dispcc"
+- reg : shall contain base register location and length.
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sdm845-dispcc";
+ reg = <0xaf00000 0x100000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt
new file mode 100644
index 0000000..d60b997
--- /dev/null
+++ b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -0,0 +1,43 @@
+* Renesas R9A06G032 SYSCTRL
+
+Required Properties:
+
+ - compatible: Must be:
+ - "renesas,r9a06g032-sysctrl"
+ - reg: Base address and length of the SYSCTRL IO block.
+ - #clock-cells: Must be 1
+ - clocks: References to the parent clocks:
+ - external 40mhz crystal.
+ - external (optional) 32.768khz
+ - external (optional) jtag input
+ - external (optional) RGMII_REFCLK
+ - clock-names: Must be:
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+
+Examples
+--------
+
+ - SYSCTRL node:
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>, <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ };
+
+ - Other nodes can use the clocks provided by SYSCTRL as in:
+
+ #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART0>;
+ clock-names = "baudclk";
+ };
diff --git a/dts/Bindings/clock/rockchip,px30-cru.txt b/dts/Bindings/clock/rockchip,px30-cru.txt
new file mode 100644
index 0000000..39f0c1a
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,px30-cru.txt
@@ -0,0 +1,65 @@
+* Rockchip PX30 Clock and Reset Unit
+
+The PX30 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
+- compatible: CRU should be "rockchip,px30-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "i2sx_clkin" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+ pmucru: clock-controller@ff2bc000 {
+ compatible = "rockchip,px30-pmucru";
+ reg = <0x0 0xff2bc000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff2b0000 {
+ compatible = "rockchip,px30-cru";
+ reg = <0x0 0xff2b0000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff030000 {
+ compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff030000 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
diff --git a/dts/Bindings/clock/sun8i-de2.txt b/dts/Bindings/clock/sun8i-de2.txt
index f2fa87c..e94582e 100644
--- a/dts/Bindings/clock/sun8i-de2.txt
+++ b/dts/Bindings/clock/sun8i-de2.txt
@@ -6,6 +6,7 @@ Required properties :
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
diff --git a/dts/Bindings/connector/usb-connector.txt b/dts/Bindings/connector/usb-connector.txt
index e1463f1..8855bfc 100644
--- a/dts/Bindings/connector/usb-connector.txt
+++ b/dts/Bindings/connector/usb-connector.txt
@@ -15,6 +15,33 @@ Optional properties:
- type: size of the connector, should be specified in case of USB-A, USB-B
non-fullsize connectors: "mini", "micro".
+Optional properties for usb-c-connector:
+- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
+ connector has power support.
+- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
+ or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
+- data-role: should be one of "host", "device", "dual"(DRD) if typec
+ connector supports USB data.
+
+Required properties for usb-c-connector with power delivery support:
+- source-pdos: An array of u32 with each entry providing supported power
+ source data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
+ Source_Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power source and power dual role.
+ User can specify the source PDO array via PDO_FIXED/BATT/VAR() defined in
+ dt-bindings/usb/pd.h.
+- sink-pdos: An array of u32 with each entry providing supported power
+ sink data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
+ Sink Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power sink and power dual role.
+ User can specify the sink PDO array via PDO_FIXED/BATT/VAR() defined in
+ dt-bindings/usb/pd.h.
+- op-sink-microwatt: Sink required operating power in microwatt, if source
+ can't offer the power, Capability Mismatch is set. Required for power
+ sink and power dual role.
+
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
@@ -73,3 +100,20 @@ ccic: s2mm005@33 {
};
};
};
+
+3. USB-C connector attached to a typec port controller(ptn5110), which has
+power delivery support and enables drp.
+
+typec: ptn5110@50 {
+ ...
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 12000, 2000)>;
+ op-sink-microwatt = <10000000>;
+ };
+};
diff --git a/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt b/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
index af23857..73470ec 100644
--- a/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
+++ b/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
@@ -29,8 +29,6 @@ Required properties:
- reg: Specifies base physical address and size of the registers.
- interrupts: The interrupt that the AVS CPU will use to interrupt the host
when a command completed.
-- interrupt-parent: The interrupt controller the above interrupt is routed
- through.
- interrupt-names: The name of the interrupt used to interrupt the host.
Optional properties:
diff --git a/dts/Bindings/cpufreq/cpufreq-exynos5440.txt b/dts/Bindings/cpufreq/cpufreq-exynos5440.txt
deleted file mode 100644
index caff1a5..0000000
--- a/dts/Bindings/cpufreq/cpufreq-exynos5440.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-
-Exynos5440 cpufreq driver
--------------------
-
-Exynos5440 SoC cpufreq driver for CPU frequency scaling.
-
-Required properties:
-- interrupts: Interrupt to know the completion of cpu frequency change.
-- operating-points: Table of frequencies and voltage CPU could be transitioned into,
- in the decreasing order. Frequency should be in KHz units and voltage
- should be in microvolts.
-
-Optional properties:
-- clock-latency: Clock monitor latency in microsecond.
-
-All the required listed above must be defined under node cpufreq.
-
-Example:
---------
- cpufreq@160000 {
- compatible = "samsung,exynos5440-cpufreq";
- reg = <0x160000 0x1000>;
- interrupts = <0 57 0>;
- operating-points = <
- 1000000 975000
- 800000 925000>;
- clock-latency = <100000>;
- };
diff --git a/dts/Bindings/crypto/amd-ccp.txt b/dts/Bindings/crypto/amd-ccp.txt
index 8c61183..d87579d 100644
--- a/dts/Bindings/crypto/amd-ccp.txt
+++ b/dts/Bindings/crypto/amd-ccp.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: Should be "amd,ccp-seattle-v1a"
- reg: Address and length of the register set for the device
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupts: Should contain the CCP interrupt
Optional properties:
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt
index c2598ab..999fb2a 100644
--- a/dts/Bindings/crypto/arm-cryptocell.txt
+++ b/dts/Bindings/crypto/arm-cryptocell.txt
@@ -7,8 +7,6 @@ Required properties:
- interrupts: Interrupt number for the device.
Optional properties:
-- interrupt-parent: The phandle for the interrupt controller that services
- interrupts for this device.
- clocks: Reference to the crypto engine clock.
- dma-coherent: Present if dma operations are coherent.
diff --git a/dts/Bindings/crypto/fsl-sec2.txt b/dts/Bindings/crypto/fsl-sec2.txt
index f0d926b..125f155 100644
--- a/dts/Bindings/crypto/fsl-sec2.txt
+++ b/dts/Bindings/crypto/fsl-sec2.txt
@@ -50,11 +50,6 @@ remaining bits are reserved for future SEC EUs.
..and so on and so forth.
-Optional properties:
-
-- interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
Example:
/* MPC8548E */
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 3c1f3a2..2fe245c 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -99,13 +99,6 @@ PROPERTIES
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
- clocks
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <prop_encoded-array>
@@ -199,13 +192,6 @@ Job Ring (JR) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
@@ -370,13 +356,6 @@ Secure Non-Volatile Storage (SNVS) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon";
diff --git a/dts/Bindings/crypto/hisilicon,hip07-sec.txt b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
new file mode 100644
index 0000000..78d2db9
--- /dev/null
+++ b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
@@ -0,0 +1,67 @@
+* Hisilicon hip07 Security Accelerator (SEC)
+
+Required properties:
+- compatible: Must contain one of
+ - "hisilicon,hip06-sec"
+ - "hisilicon,hip07-sec"
+- reg: Memory addresses and lengths of the memory regions through which
+ this device is controlled.
+ Region 0 has registers to control the backend processing engines.
+ Region 1 has registers for functionality common to all queues.
+ Regions 2-18 have registers for the 16 individual queues which are isolated
+ both in hardware and within the driver.
+- interrupts: Interrupt specifiers.
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client node
+ bindings.
+ Interrupt 0 is for the SEC unit error queue.
+ Interrupt 2N + 1 is the completion interrupt for queue N.
+ Interrupt 2N + 2 is the error interrupt for queue N.
+- dma-coherent: The driver assumes coherent dma is possible.
+
+Optional properties:
+- iommus: The SEC units are behind smmu-v3 iommus.
+ Refer to iommu/arm,smmu-v3.txt for more information.
+
+Example:
+
+p1_sec_a: crypto@400,d2000000 {
+ compatible = "hisilicon,hip07-sec";
+ reg = <0x400 0xd0000000 0x0 0x10000
+ 0x400 0xd2000000 0x0 0x10000
+ 0x400 0xd2010000 0x0 0x10000
+ 0x400 0xd2020000 0x0 0x10000
+ 0x400 0xd2030000 0x0 0x10000
+ 0x400 0xd2040000 0x0 0x10000
+ 0x400 0xd2050000 0x0 0x10000
+ 0x400 0xd2060000 0x0 0x10000
+ 0x400 0xd2070000 0x0 0x10000
+ 0x400 0xd2080000 0x0 0x10000
+ 0x400 0xd2090000 0x0 0x10000
+ 0x400 0xd20a0000 0x0 0x10000
+ 0x400 0xd20b0000 0x0 0x10000
+ 0x400 0xd20c0000 0x0 0x10000
+ 0x400 0xd20d0000 0x0 0x10000
+ 0x400 0xd20e0000 0x0 0x10000
+ 0x400 0xd20f0000 0x0 0x10000
+ 0x400 0xd2100000 0x0 0x10000>;
+ interrupt-parent = <&p1_mbigen_sec_a>;
+ iommus = <&p1_smmu_alg_a 0x600>;
+ dma-coherent;
+ interrupts = <576 4>,
+ <577 1>, <578 4>,
+ <579 1>, <580 4>,
+ <581 1>, <582 4>,
+ <583 1>, <584 4>,
+ <585 1>, <586 4>,
+ <587 1>, <588 4>,
+ <589 1>, <590 4>,
+ <591 1>, <592 4>,
+ <593 1>, <594 4>,
+ <595 1>, <596 4>,
+ <597 1>, <598 4>,
+ <599 1>, <600 4>,
+ <601 1>, <602 4>,
+ <603 1>, <604 4>,
+ <605 1>, <606 4>,
+ <607 1>, <608 4>;
+};
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 5dba55c..3bbf144 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -1,8 +1,9 @@
Inside Secure SafeXcel cryptographic engine
Required properties:
-- compatible: Should be "inside-secure,safexcel-eip197" or
- "inside-secure,safexcel-eip97".
+- compatible: Should be "inside-secure,safexcel-eip197b",
+ "inside-secure,safexcel-eip197d" or
+ "inside-secure,safexcel-eip97ies".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt numbers for the rings and engine.
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
@@ -14,10 +15,18 @@ Optional properties:
name must be "core" for the first clock and "reg" for
the second one.
+Backward compatibility:
+Two compatibles are kept for backward compatibility, but shouldn't be used for
+new submissions:
+- "inside-secure,safexcel-eip197" is equivalent to
+ "inside-secure,safexcel-eip197b".
+- "inside-secure,safexcel-eip97" is equivalent to
+ "inside-secure,safexcel-eip97ies".
+
Example:
crypto: crypto@800000 {
- compatible = "inside-secure,safexcel-eip197";
+ compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/Bindings/crypto/picochip-spacc.txt b/dts/Bindings/crypto/picochip-spacc.txt
index d8609ec..df1151f 100644
--- a/dts/Bindings/crypto/picochip-spacc.txt
+++ b/dts/Bindings/crypto/picochip-spacc.txt
@@ -7,8 +7,6 @@ Required properties:
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- reg : Offset and length of the register set for this device
- - interrupt-parent : The interrupt controller that controls the SPAcc
- interrupt.
- interrupts : The interrupt line from the SPAcc.
- ref-clock : The input clock that drives the SPAcc.
diff --git a/dts/Bindings/rng/qcom,prng.txt b/dts/Bindings/crypto/qcom,prng.txt
index 8e5853c..7ee0e9e 100644
--- a/dts/Bindings/rng/qcom,prng.txt
+++ b/dts/Bindings/crypto/qcom,prng.txt
@@ -2,7 +2,9 @@ Qualcomm MSM pseudo random number generator.
Required properties:
-- compatible : should be "qcom,prng"
+- compatible : should be "qcom,prng" for 8916 etc
+ : should be "qcom,prng-ee" for 8996 and later using EE
+ (Execution Environment) slice of prng
- reg : specifies base physical address and size of the registers map
- clocks : phandle to clock-controller plus clock-specifier pair
- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
index fc2bcbe..0ec6814 100644
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ b/dts/Bindings/devfreq/rk3399_dmc.txt
@@ -1,14 +1,10 @@
-* Rockchip rk3399 DMC(Dynamic Memory Controller) device
+* Rockchip rk3399 DMC (Dynamic Memory Controller) device
Required properties:
- compatible: Must be "rockchip,rk3399-dmc".
- devfreq-events: Node to get DDR loading, Refer to
- Documentation/devicetree/bindings/devfreq/
+ Documentation/devicetree/bindings/devfreq/event/
rockchip-dfi.txt
-- interrupts: The interrupt number to the CPU. The interrupt
- specifier format depends on the interrupt controller.
- It should be DCF interrupts, when DDR dvfs finish,
- it will happen.
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon";
@@ -17,139 +13,148 @@ Required properties:
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
-Following properties are ddr timing:
-
-- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
- it select ddr3 cl-trp-trcd type, default value
- "DDR3_DEFAULT".it must selected according to
- "Speed Bin" in ddr3 datasheet, DO NOT use
- smaller "Speed Bin" than ddr3 exactly is.
-
-- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down
- idle period, memories are places into power-down
- mode if bus is idle for PD_IDLE DFI clocks.
-
-- rockchip,sr_idle : Configure the SR_IDLE value, defined the
- selfrefresh idle period, memories are places
- into self-refresh mode if bus is idle for
- SR_IDLE*1024 DFI clocks (DFI clocks freq is
- half of dram's clocks), defaule value is "0".
-
-- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and
- controller clock gating idle period, memories
- are places into self-refresh mode and memory
- controller clock arg gating if bus is idle for
- sr_mc_gate_idle*1024 DFI clocks.
-
-- rockchip,srpd_lite_idle : Defined the self-refresh power down idle
- period, memories are places into self-refresh
- power down mode if bus is idle for
- srpd_lite_idle*1024 DFI clocks. This parameter
- is for LPDDR4 only.
-
-- rockchip,standby_idle : Defined the standby idle period, memories are
- places into self-refresh than controller, pi,
- phy and dram clock will gating if bus is idle
- for standby_idle * DFI clocks.
-
-- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in
- MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,
- ddr3 dll will bypssed note: if dll was bypassed,
- the odt also stop working.
-
-- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in
- MHz (Mega Hz), when ddr freq less than
- DRAM_DLL_DISB_FREQ, phy dll will bypssed.
- note: phy dll and phy odt are independent.
-
-- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined
- the odt disable frequency in MHz (Mega Hz),
- when ddr frequency less then ddr3_odt_disb_freq,
- the odt on dram side and controller side are
+Optional properties:
+- interrupts: The CPU interrupt number. The interrupt specifier
+ format depends on the interrupt controller.
+ It should be a DCF interrupt. When DDR DVFS finishes
+ a DCF interrupt is triggered.
+
+Following properties relate to DDR timing:
+
+- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
+ it selects the DDR3 cl-trp-trcd type. It must be
+ set according to "Speed Bin" in DDR3 datasheet,
+ DO NOT use a smaller "Speed Bin" than specified
+ for the DDR3 being used.
+
+- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
+ power-down idle period in which memories are
+ placed into power-down mode if bus is idle
+ for PD_IDLE DFI clock cycles.
+
+- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
+ self-refresh idle period in which memories are
+ placed into self-refresh mode if bus is idle
+ for SR_IDLE * 1024 DFI clock cycles (DFI
+ clocks freq is half of DRAM clock), default
+ value is "0".
+
+- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
+ clock gating idle period. Memories are placed
+ into self-refresh mode and memory controller
+ clock arg gating started if bus is idle for
+ sr_mc_gate_idle*1024 DFI clock cycles.
+
+- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
+ period in which memories are placed into
+ self-refresh power down mode if bus is idle
+ for srpd_lite_idle * 1024 DFI clock cycles.
+ This parameter is for LPDDR4 only.
+
+- rockchip,standby_idle : Defines the standby idle period in which
+ memories are placed into self-refresh mode.
+ The controller, pi, PHY and DRAM clock will
+ be gated if bus is idle for standby_idle * DFI
+ clock cycles.
+
+- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
+ When DDR frequency is less than DRAM_DLL_DISB_FREQ,
+ DDR3 DLL will be bypassed. Note: if DLL was bypassed,
+ the odt will also stop working.
+
+- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
+ MHz (Mega Hz). When DDR frequency is less than
+ DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
+ Note: PHY DLL and PHY ODT are independent.
+
+- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
+ the ODT disable frequency in MHz (Mega Hz).
+ when the DDR frequency is less then ddr3_odt_dis_freq,
+ the ODT on the DRAM side and controller side are
both disabled.
-- rockchip,ddr3_drv : When dram type is DDR3, this parameter define
- the dram side driver stength in ohm, default
+- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
+ the DRAM side driver strength in ohms. Default
value is DDR3_DS_40ohm.
-- rockchip,ddr3_odt : When dram type is DDR3, this parameter define
- the dram side ODT stength in ohm, default value
+- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
+ the DRAM side ODT strength in ohms. Default value
is DDR3_ODT_120ohm.
-- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define
- the phy side CA line(incluing command line,
+- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
+ the phy side CA line (incluing command line,
address line and clock line) driver strength.
Default value is PHY_DRV_ODT_40.
-- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define
- the phy side DQ line(incluing DQS/DQ/DM line)
- driver strength. default value is PHY_DRV_ODT_40.
+- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
+ the PHY side DQ line (including DQS/DQ/DM line)
+ driver strength. Default value is PHY_DRV_ODT_40.
-- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the
- phy side odt strength, default value is
+- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
+ the PHY side ODT strength. Default value is
PHY_DRV_ODT_240.
-- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined
- then odt disable frequency in MHz (Mega Hz),
- when ddr frequency less then ddr3_odt_disb_freq,
- the odt on dram side and controller side are
+- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
+ then ODT disable frequency in MHz (Mega Hz).
+ When DDR frequency is less then ddr3_odt_dis_freq,
+ the ODT on the DRAM side and controller side are
both disabled.
-- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define
- the dram side driver stength in ohm, default
+- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
+ the DRAM side driver strength in ohms. Default
value is LP3_DS_34ohm.
-- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define
- the dram side ODT stength in ohm, default value
+- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
+ the DRAM side ODT strength in ohms. Default value
is LP3_ODT_240ohm.
-- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define
- the phy side CA line(incluing command line,
+- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
+ the PHY side CA line (including command line,
address line and clock line) driver strength.
- default value is PHY_DRV_ODT_40.
+ Default value is PHY_DRV_ODT_40.
-- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define
- the phy side DQ line(incluing DQS/DQ/DM line)
- driver strength. default value is
+- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
+ the PHY side DQ line (including DQS/DQ/DM line)
+ driver strength. Default value is
PHY_DRV_ODT_40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
the phy side odt strength, default value is
PHY_DRV_ODT_240.
-- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter
- defined the odt disable frequency in
- MHz (Mega Hz), when ddr frequency less then
- ddr3_odt_disb_freq, the odt on dram side and
+- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
+ defines the ODT disable frequency in
+ MHz (Mega Hz). When the DDR frequency is less then
+ ddr3_odt_dis_freq, the ODT on the DRAM side and
controller side are both disabled.
-- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define
- the dram side driver stength in ohm, default
+- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
+ the DRAM side driver strength in ohms. Default
value is LP4_PDDS_60ohm.
-- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define
- the dram side ODT on dqs/dq line stength in ohm,
- default value is LP4_DQ_ODT_40ohm.
+- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
+ the DRAM side ODT on DQS/DQ line strength in ohms.
+ Default value is LP4_DQ_ODT_40ohm.
-- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define
- the dram side ODT on ca line stength in ohm,
- default value is LP4_CA_ODT_40ohm.
+- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
+ the DRAM side ODT on CA line strength in ohms.
+ Default value is LP4_CA_ODT_40ohm.
-- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define
- the phy side CA line(incluing command address
- line) driver strength. default value is
+- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
+ the PHY side CA line (including command address
+ line) driver strength. Default value is
PHY_DRV_ODT_40.
-- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define
- the phy side clock line and cs line driver
- strength. default value is PHY_DRV_ODT_80.
+- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
+ the PHY side clock line and CS line driver
+ strength. Default value is PHY_DRV_ODT_80.
-- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define
- the phy side DQ line(incluing DQS/DQ/DM line)
- driver strength. default value is PHY_DRV_ODT_80.
+- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
+ the PHY side DQ line (including DQS/DQ/DM line)
+ driver strength. Default value is PHY_DRV_ODT_80.
-- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define
- the phy side odt strength, default value is
+- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
+ the PHY side ODT strength. Default value is
PHY_DRV_ODT_60.
Example:
diff --git a/dts/Bindings/display/brcm,bcm-vc4.txt b/dts/Bindings/display/brcm,bcm-vc4.txt
index 284e2b1..26649b4 100644
--- a/dts/Bindings/display/brcm,bcm-vc4.txt
+++ b/dts/Bindings/display/brcm,bcm-vc4.txt
@@ -74,6 +74,12 @@ Required properties for DSI:
The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
dsi[01]_ddr2, and dsi[01]_ddr
+Required properties for the TXP (writeback) block:
+- compatible: Should be "brcm,bcm2835-txp"
+- reg: Physical base address and length of the TXP block's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/dts/Bindings/display/bridge/analogix_dp.txt b/dts/Bindings/display/bridge/analogix_dp.txt
index 0c7473d..027d76c 100644
--- a/dts/Bindings/display/bridge/analogix_dp.txt
+++ b/dts/Bindings/display/bridge/analogix_dp.txt
@@ -15,8 +15,6 @@ Required properties for dp-controller:
from common clock binding: handle to dp clock.
-clock-names:
from common clock binding: Shall be "dp".
- -interrupt-parent:
- phandle to Interrupt combiner node.
-phys:
from general PHY binding: the phandle for the PHY device.
-phy-names:
diff --git a/dts/Bindings/display/bridge/anx7814.txt b/dts/Bindings/display/bridge/anx7814.txt
index b2a22c2..dbd7c84 100644
--- a/dts/Bindings/display/bridge/anx7814.txt
+++ b/dts/Bindings/display/bridge/anx7814.txt
@@ -8,8 +8,6 @@ Required properties:
- compatible : "analogix,anx7814"
- reg : I2C address of the device
- - interrupt-parent : Should be the phandle of the interrupt controller
- that services interrupts for this device
- interrupts : Should contain the INTP interrupt
- hpd-gpios : Which GPIO to use for hpd
- pd-gpios : Which GPIO to use for power down
diff --git a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
index aacc8b9..09e0a21 100644
--- a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
+++ b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
@@ -19,8 +19,6 @@ hardware are EDID, HPD, and interrupts.
stdp4028-ge-b850v3-fw required properties:
- compatible : "megachips,stdp4028-ge-b850v3-fw"
- reg : I2C bus address
- - interrupt-parent : phandle of the interrupt controller that services
- interrupts to the device
- interrupts : one interrupt should be described here, as in
<0 IRQ_TYPE_LEVEL_HIGH>
- ports : One input port(reg = <0>) and one output port(reg = <1>)
diff --git a/dts/Bindings/display/bridge/sii902x.txt b/dts/Bindings/display/bridge/sii902x.txt
index 56a3e68..72d2dc6 100644
--- a/dts/Bindings/display/bridge/sii902x.txt
+++ b/dts/Bindings/display/bridge/sii902x.txt
@@ -5,8 +5,8 @@ Required properties:
- reg: i2c address of the bridge
Optional properties:
- - interrupts-extended or interrupt-parent + interrupts: describe
- the interrupt line used to inform the host about hotplug events.
+ - interrupts: describe the interrupt line used to inform the host
+ about hotplug events.
- reset-gpios: OF device-tree gpio specification for RST_N pin.
Optional subnodes:
diff --git a/dts/Bindings/display/bridge/sii9234.txt b/dts/Bindings/display/bridge/sii9234.txt
index 88041ba..a55bf77 100644
--- a/dts/Bindings/display/bridge/sii9234.txt
+++ b/dts/Bindings/display/bridge/sii9234.txt
@@ -7,7 +7,7 @@ Required properties:
- iovcc18-supply : I/O Supply Voltage (1.8V)
- avcc12-supply : TMDS Analog Supply Voltage (1.2V)
- cvcc12-supply : Digital Core Supply Voltage (1.2V)
- - interrupts, interrupt-parent: interrupt specifier of INT pin
+ - interrupts: interrupt specifier of INT pin
- reset-gpios: gpio specifier of RESET pin (active low)
- video interfaces: Device node can contain two video interface port
nodes for HDMI encoder and connector according to [1].
diff --git a/dts/Bindings/display/bridge/sil-sii8620.txt b/dts/Bindings/display/bridge/sil-sii8620.txt
index 9409d9c..b05052f 100644
--- a/dts/Bindings/display/bridge/sil-sii8620.txt
+++ b/dts/Bindings/display/bridge/sil-sii8620.txt
@@ -5,7 +5,7 @@ Required properties:
- reg: i2c address of the bridge
- cvcc10-supply: Digital Core Supply Voltage (1.0V)
- iovcc18-supply: I/O Supply Voltage (1.8V)
- - interrupts, interrupt-parent: interrupt specifier of INT pin
+ - interrupts: interrupt specifier of INT pin
- reset-gpios: gpio specifier of RESET pin
- clocks, clock-names: specification and name of "xtal" clock
- video interfaces: Device node can contain video interface port
diff --git a/dts/Bindings/display/exynos/exynos7-decon.txt b/dts/Bindings/display/exynos/exynos7-decon.txt
index 9e2e7f6..53912c9 100644
--- a/dts/Bindings/display/exynos/exynos7-decon.txt
+++ b/dts/Bindings/display/exynos/exynos7-decon.txt
@@ -9,9 +9,6 @@ Required properties:
- reg: physical base address and length of the DECON registers set.
-- interrupt-parent: should be the phandle of the decon controller's
- parent interrupt controller.
-
- interrupts: should contain a list of all DECON IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
diff --git a/dts/Bindings/display/exynos/exynos_dp.txt b/dts/Bindings/display/exynos/exynos_dp.txt
index ade5d8e..9b6cba3 100644
--- a/dts/Bindings/display/exynos/exynos_dp.txt
+++ b/dts/Bindings/display/exynos/exynos_dp.txt
@@ -25,8 +25,6 @@ Required properties for dp-controller:
from common clock binding: handle to dp clock.
-clock-names:
from common clock binding: Shall be "dp".
- -interrupt-parent:
- phandle to Interrupt combiner node.
-phys:
from general PHY binding: the phandle for the PHY device.
-phy-names:
diff --git a/dts/Bindings/display/exynos/samsung-fimd.txt b/dts/Bindings/display/exynos/samsung-fimd.txt
index 5837402..b309642 100644
--- a/dts/Bindings/display/exynos/samsung-fimd.txt
+++ b/dts/Bindings/display/exynos/samsung-fimd.txt
@@ -16,9 +16,6 @@ Required properties:
- reg: physical base address and length of the FIMD registers set.
-- interrupt-parent: should be the phandle of the fimd controller's
- parent interrupt controller.
-
- interrupts: should contain a list of all FIMD IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
diff --git a/dts/Bindings/display/ht16k33.txt b/dts/Bindings/display/ht16k33.txt
index 8e5b30b..d5a8b07 100644
--- a/dts/Bindings/display/ht16k33.txt
+++ b/dts/Bindings/display/ht16k33.txt
@@ -4,8 +4,6 @@ Holtek ht16k33 RAM mapping 16*8 LED controller driver with keyscan
Required properties:
- compatible: "holtek,ht16k33"
- reg: I2C slave address of the chip.
-- interrupt-parent: A phandle pointing to the interrupt controller
- serving the interrupt for this chip.
- interrupts: Interrupt specification for the key pressed interrupt.
- refresh-rate-hz: Display update interval in HZ.
- debounce-delay-ms: Debouncing interval time in milliseconds.
diff --git a/dts/Bindings/display/ilitek,ili9341.txt b/dts/Bindings/display/ilitek,ili9341.txt
new file mode 100644
index 0000000..169b32e
--- /dev/null
+++ b/dts/Bindings/display/ilitek,ili9341.txt
@@ -0,0 +1,27 @@
+Ilitek ILI9341 display panels
+
+This binding is for display panels using an Ilitek ILI9341 controller in SPI
+mode.
+
+Required properties:
+- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
+- dc-gpios: D/C pin
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+ display@0{
+ compatible = "adafruit,yx240qv29", "ilitek,ili9341";
+ reg = <0>;
+ spi-max-frequency = <32000000>;
+ dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ rotation = <270>;
+ backlight = <&backlight>;
+ };
diff --git a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
index f79641b..45ffd6c 100644
--- a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
+++ b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
@@ -10,6 +10,9 @@ Required properties:
- interrupts : framebuffer controller interrupt.
- clocks: phandle to input clocks
+Optional properties:
+ - lcd-supply: A phandle to a power regulator that controls the LCD voltage.
+
Required nodes:
- port: connection to the LCD panel (see video-interfaces.txt)
This node must have its properties bus-width and remote-endpoint set.
diff --git a/dts/Bindings/display/marvell,pxa300-gcu.txt b/dts/Bindings/display/marvell,pxa300-gcu.txt
new file mode 100644
index 0000000..9cfae5c
--- /dev/null
+++ b/dts/Bindings/display/marvell,pxa300-gcu.txt
@@ -0,0 +1,17 @@
+PXA3xx GCU Controller
+---------------------
+
+Required properties:
+ - compatible : "marvell,pxa300-gcu"
+ - reg : should contain the register range (address and length).
+ - interrupts : Controller interrupt.
+ - clocks: phandle to the PXA specific input clock.
+
+Example for PXA300:
+
+ display-controller@54000000 {
+ compatible = "marvell,pxa300-gcu";
+ reg = <0x54000000 0x1000>;
+ interrupts = <39>;
+ clocks = <&clks CLK_PXA300_GCU>;
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt
index 383183a..8469de5 100644
--- a/dts/Bindings/display/mediatek/mediatek,disp.txt
+++ b/dts/Bindings/display/mediatek/mediatek,disp.txt
@@ -40,7 +40,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701 and mt8173.
+ the supported chips are mt2701, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
diff --git a/dts/Bindings/display/msm/dpu.txt b/dts/Bindings/display/msm/dpu.txt
new file mode 100644
index 0000000..ad2e883
--- /dev/null
+++ b/dts/Bindings/display/msm/dpu.txt
@@ -0,0 +1,131 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+ * "mdss"
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required:
+ * "iface"
+ * "bus"
+ * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+ * "mdp"
+ * "vbif"
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required.
+ * "bus"
+ * "iface"
+ * "core"
+ * "vsync"
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+ to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ Port 0 -> DPU_INTF1 (DSI1)
+ Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+Example:
+
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&clock_dispcc 0>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <300000000>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_iommu 0>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xae00000 0xb2008>;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <0 0 300000000 19200000>;
+
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index 518e9cd..dfc7432 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -43,8 +43,6 @@ Optional properties:
the master link of the 2-DSI panel.
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
- through MDP block
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
@@ -121,6 +119,20 @@ Required properties:
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
+ panels in microseconds. Driver uses this number to adjust
+ the clock rate according to the expected transfer time.
+ Increasing this value would slow down the mdp processing
+ and can result in slower performance.
+ Decreasing this value can speed up the mdp processing,
+ but this can also impact power consumption.
+ As a rule this time should not be higher than the time
+ that would be expected with the processing at the
+ dsi link rate since anyways this would be the maximum
+ transfer time that could be achieved.
+ If ping pong split is enabled, this time should not be higher
+ than two times the dsi link rate time.
+ If the property is not specified, then the default value is 14000 us.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
@@ -171,6 +183,8 @@ Example:
qcom,master-dsi;
qcom,sync-dual-dsi;
+ qcom,mdss-mdp-transfer-time-us = <12000>;
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dsi_active>;
pinctrl-1 = <&dsi_suspend>;
diff --git a/dts/Bindings/display/msm/edp.txt b/dts/Bindings/display/msm/edp.txt
index 95ce19c..eff9daf 100644
--- a/dts/Bindings/display/msm/edp.txt
+++ b/dts/Bindings/display/msm/edp.txt
@@ -25,10 +25,6 @@ Required properties:
- panel-hpd-gpios: GPIO pin used for eDP hpd.
-Optional properties:
-- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
- through MDP block
-
Example:
mdss_edp: qcom,mdss_edp@fd923400 {
compatible = "qcom,mdss-edp";
diff --git a/dts/Bindings/display/msm/mdp5.txt b/dts/Bindings/display/msm/mdp5.txt
index 1b31977..4e11338 100644
--- a/dts/Bindings/display/msm/mdp5.txt
+++ b/dts/Bindings/display/msm/mdp5.txt
@@ -41,8 +41,6 @@ Required properties:
- reg-names: The names of register regions. The following regions are required:
* "mdp_phys"
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
-- interrupt-parent: phandle to the MDSS block
- through MDP block
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
- * "bus"
diff --git a/dts/Bindings/display/panel/auo,g070vvn01.txt b/dts/Bindings/display/panel/auo,g070vvn01.txt
new file mode 100644
index 0000000..49e4105
--- /dev/null
+++ b/dts/Bindings/display/panel/auo,g070vvn01.txt
@@ -0,0 +1,29 @@
+AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,g070vvn01"
+- backlight: phandle of the backlight device attached to the panel
+- power-supply: single regulator to provide the supply voltage
+
+Required nodes:
+- port: Parallel port mapping to connect this display
+
+This panel needs single power supply voltage. Its backlight is conntrolled
+via PWM signal.
+
+Example:
+--------
+
+Example device-tree definition when connected to iMX6Q based board
+
+ lcd_panel: lcd-panel {
+ compatible = "auo,g070vvn01";
+ backlight = <&backlight_lcd>;
+ power-supply = <&reg_display>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/boe,hv070wsa-100.txt b/dts/Bindings/display/panel/boe,hv070wsa-100.txt
new file mode 100644
index 0000000..55183d3
--- /dev/null
+++ b/dts/Bindings/display/panel/boe,hv070wsa-100.txt
@@ -0,0 +1,28 @@
+BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,hv070wsa-100"
+- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
+- enable-gpios: GPIO pin to enable and disable panel (active high)
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [1]. This
+node should describe panel's video bus.
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel: panel {
+ compatible = "boe,hv070wsa-100";
+ power-supply = <&vcc_3v3_reg>;
+ enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
+ port {
+ panel_ep: endpoint {
+ remote-endpoint = <&bridge_out_ep>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt b/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt
new file mode 100644
index 0000000..897085e
--- /dev/null
+++ b/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt
@@ -0,0 +1,8 @@
+DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
+
+Required properties:
+- compatible: should be "dataimage,scf0700c48ggu18"
+- power-supply: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt b/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt
new file mode 100644
index 0000000..bf06bb0
--- /dev/null
+++ b/dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt
@@ -0,0 +1,13 @@
+DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "dlc,dlc0700yzg-1"
+- power-supply: See simple-panel.txt
+
+Optional properties:
+- reset-gpios: See panel-common.txt
+- enable-gpios: See simple-panel.txt
+- backlight: See simple-panel.txt
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/edt,et-series.txt b/dts/Bindings/display/panel/edt,et-series.txt
new file mode 100644
index 0000000..f56b99e
--- /dev/null
+++ b/dts/Bindings/display/panel/edt,et-series.txt
@@ -0,0 +1,39 @@
+Emerging Display Technology Corp. Displays
+==========================================
+
+
+Display bindings for EDT Display Technology Corp. Displays which are
+compatible with the simple-panel binding, which is specified in
+simple-panel.txt
+
+
+5,7" WVGA TFT Panels
+--------------------
+
++-----------------+---------------------+-------------------------------------+
+| Identifier | compatbile | description |
++=================+=====================+=====================================+
+| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel |
++-----------------+---------------------+-------------------------------------+
+
+
+7,0" WVGA TFT Panels
+--------------------
+
++-----------------+---------------------+-------------------------------------+
+| Identifier | compatbile | description |
++=================+=====================+=====================================+
+| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive |
+| | | Touchscreen |
++-----------------+---------------------+-------------------------------------+
+| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with |
+| | | inverted pixel clock. |
++-----------------+---------------------+-------------------------------------+
+| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, |
+| | | but with changed Hardware for the |
+| | | backlight and the touch interface |
++-----------------+---------------------+-------------------------------------+
+| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, |
+| | | but with resistive touch. |
++-----------------+---------------------+-------------------------------------+
+
diff --git a/dts/Bindings/display/panel/edt,et070080dh6.txt b/dts/Bindings/display/panel/edt,et070080dh6.txt
deleted file mode 100644
index 20cb38e..0000000
--- a/dts/Bindings/display/panel/edt,et070080dh6.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Emerging Display Technology Corp. ET070080DH6 7.0" WVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "edt,et070080dh6"
-
-This panel is the same as ETM0700G0DH6 except for the touchscreen.
-ET070080DH6 is the model with resistive touch.
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/edt,etm0700g0dh6.txt b/dts/Bindings/display/panel/edt,etm0700g0dh6.txt
deleted file mode 100644
index ee4b180..0000000
--- a/dts/Bindings/display/panel/edt,etm0700g0dh6.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Emerging Display Technology Corp. ETM0700G0DH6 7.0" WVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "edt,etm0700g0dh6"
-
-This panel is the same as ET070080DH6 except for the touchscreen.
-ETM0700G0DH6 is the model with capacitive multitouch.
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/ilitek,ili9881c.txt b/dts/Bindings/display/panel/ilitek,ili9881c.txt
new file mode 100644
index 0000000..4a041ac
--- /dev/null
+++ b/dts/Bindings/display/panel/ilitek,ili9881c.txt
@@ -0,0 +1,20 @@
+Ilitek ILI9881c based MIPI-DSI panels
+
+Required properties:
+ - compatible: must be "ilitek,ili9881c" and one of:
+ * "bananapi,lhr050h41"
+ - reg: DSI virtual channel used by that screen
+ - power-supply: phandle to the power regulator
+ - reset-gpios: a GPIO phandle for the reset pin
+
+Optional properties:
+ - backlight: phandle to the backlight used
+
+Example:
+panel@0 {
+ compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
+ reg = <0>;
+ power-supply = <&reg_display>;
+ reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+ backlight = <&pwm_bl>;
+};
diff --git a/dts/Bindings/display/panel/innolux,g070y2-l01.txt b/dts/Bindings/display/panel/innolux,g070y2-l01.txt
new file mode 100644
index 0000000..7c234cf
--- /dev/null
+++ b/dts/Bindings/display/panel/innolux,g070y2-l01.txt
@@ -0,0 +1,12 @@
+Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,g070y2-l01"
+- power-supply: as specified in the base binding
+
+Optional properties:
+- backlight: as specified in the base binding
+- enable-gpios: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,p097pfg.txt b/dts/Bindings/display/panel/innolux,p097pfg.txt
new file mode 100644
index 0000000..595d9df
--- /dev/null
+++ b/dts/Bindings/display/panel/innolux,p097pfg.txt
@@ -0,0 +1,24 @@
+Innolux P097PFG 9.7" 1536x2048 TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,p097pfg"
+- reg: DSI virtual channel of the peripheral
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- enable-gpios: panel enable gpio
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+ &mipi_dsi {
+ panel {
+ compatible = "innolux,p079zca";
+ reg = <0>;
+ avdd-supply = <...>;
+ avee-supply = <...>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/Bindings/display/panel/innolux,tv123wam.txt b/dts/Bindings/display/panel/innolux,tv123wam.txt
new file mode 100644
index 0000000..a9b3526
--- /dev/null
+++ b/dts/Bindings/display/panel/innolux,tv123wam.txt
@@ -0,0 +1,20 @@
+Innolux TV123WAM 12.3 inch eDP 2K display panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "innolux,tv123wam"
+- power-supply: regulator to provide the supply voltage
+
+Optional properties:
+- enable-gpios: GPIO pin to enable or disable the panel
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+ panel_edp: panel-edp {
+ compatible = "innolux,tv123wam";
+ enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>;
+ power-supply = <&pm8916_l2>;
+ backlight = <&backlight>;
+ };
diff --git a/dts/Bindings/display/panel/kingdisplay,kd097d04.txt b/dts/Bindings/display/panel/kingdisplay,kd097d04.txt
new file mode 100644
index 0000000..164a5fa
--- /dev/null
+++ b/dts/Bindings/display/panel/kingdisplay,kd097d04.txt
@@ -0,0 +1,22 @@
+Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel
+
+Required properties:
+- compatible: should be "kingdisplay,kd097d04"
+- reg: DSI virtual channel of the peripheral
+- power-supply: phandle of the regulator that provides the supply voltage
+- enable-gpios: panel enable gpio
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+ &mipi_dsi {
+ panel {
+ compatible = "kingdisplay,kd097d04";
+ reg = <0>;
+ power-supply = <...>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/Bindings/display/panel/edt,et057090dhu.txt b/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt
index 4903d7b..e78292b 100644
--- a/dts/Bindings/display/panel/edt,et057090dhu.txt
+++ b/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt
@@ -1,7 +1,7 @@
-Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
+Newhaven Display International 480 x 272 TFT LCD panel
Required properties:
-- compatible: should be "edt,et057090dhu"
+- compatible: should be "newhaven,nhd-4.3-480272ef-atxl"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/rocktech,rk070er9427.txt b/dts/Bindings/display/panel/rocktech,rk070er9427.txt
new file mode 100644
index 0000000..eb1fb9f
--- /dev/null
+++ b/dts/Bindings/display/panel/rocktech,rk070er9427.txt
@@ -0,0 +1,25 @@
+Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "rocktech,rk070er9427"
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Optional nodes:
+- Video port for LCD panel input.
+
+Example:
+ panel {
+ compatible = "rocktech,rk070er9427";
+ backlight = <&backlight_lcd>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/sharp,lq035q7db03.txt b/dts/Bindings/display/panel/sharp,lq035q7db03.txt
new file mode 100644
index 0000000..0753f69
--- /dev/null
+++ b/dts/Bindings/display/panel/sharp,lq035q7db03.txt
@@ -0,0 +1,12 @@
+Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "sharp,lq035q7db03"
+- power-supply: phandle of the regulator that provides the supply voltage
+
+Optional properties:
+- enable-gpios: GPIO pin to enable or disable the panel
+- backlight: phandle of the backlight device attached to the panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index 7c6854b..ec9d34b 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -19,7 +19,6 @@ Required Properties:
- reg: the memory-mapped I/O registers base address and length
- - interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifiers for the DU interrupts.
- clocks: A list of phandles + clock-specifier pairs, one for each entry in
diff --git a/dts/Bindings/display/sm501fb.txt b/dts/Bindings/display/sm501fb.txt
index 9d9f009..1c79c26 100644
--- a/dts/Bindings/display/sm501fb.txt
+++ b/dts/Bindings/display/sm501fb.txt
@@ -9,8 +9,6 @@ Required properties:
- First entry: System Configuration register
- Second entry: IO space (Display Controller register)
- interrupts : SMI interrupt to the cpu should be described here.
-- interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
Optional properties:
- mode : select a video mode:
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index 3346c1e..f8773ec 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -103,6 +103,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
+ * allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
* bus: the HDMI PHY interface clock
@@ -111,8 +112,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 HDMI PHY requires additional clock:
+H3 and A64 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
+ - pll-1: second possible phy clock parent (A64 only)
TV Encoder
----------
@@ -145,6 +147,7 @@ Required properties:
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
* allwinner,sun8i-a83t-tcon-tv
+ * allwinner,sun8i-r40-tcon-tv
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
@@ -179,7 +182,7 @@ For TCONs with channel 0, there is one more clock required:
For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
@@ -187,6 +190,62 @@ And on the A23, A31, A31s and A33, you need one more clock line:
- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
clock, that can be used to drive the LVDS clock
+TCON TOP
+--------
+
+TCON TOPs main purpose is to configure whole display pipeline. It determines
+relationships between mixers and TCONs, selects source TCON for HDMI, muxes
+LCD and TV encoder GPIO output, selects TV encoder clock source and contains
+additional TV TCON and DSI gates.
+
+It allows display pipeline to be configured in very different ways:
+
+ / LCD0/LVDS0
+ / [0] TCON-LCD0
+ | \ MIPI DSI
+ mixer0 |
+ \ / [1] TCON-LCD1 - LCD1/LVDS1
+ TCON-TOP
+ / \ [2] TCON-TV0 [0] - TVE0/RGB
+ mixer1 | \
+ | TCON-TOP - HDMI
+ | /
+ \ [3] TCON-TV1 [1] - TVE1/RGB
+
+Note that both TCON TOP references same physical unit. Both mixers can be
+connected to any TCON.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-r40-tcon-top
+ - reg: base address and size of the memory-mapped region.
+ - clocks: phandle to the clocks feeding the TCON TOP
+ * bus: TCON TOP interface clock
+ * tcon-tv0: TCON TV0 clock
+ * tve0: TVE0 clock
+ * tcon-tv1: TCON TV1 clock
+ * tve1: TVE0 clock
+ * dsi: MIPI DSI clock
+ - clock-names: clock name mentioned above
+ - resets: phandle to the reset line driving the TCON TOP
+ - #clock-cells : must contain 1
+ - clock-output-names: Names of clocks created for TCON TV0 channel clock,
+ TCON TV1 channel clock and DSI channel clock, in that order.
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
+ be defined:
+ * port 0 is input for mixer0 mux
+ * port 1 is output for mixer0 mux
+ * port 2 is input for mixer1 mux
+ * port 3 is output for mixer1 mux
+ * port 4 is input for HDMI mux
+ * port 5 is output for HDMI mux
+ All output endpoints for mixer muxes and input endpoints for HDMI mux should
+ have reg property with the id of the target TCON, as shown in above graph
+ (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one
+ endpoint connected to remote endpoint.
+
DRC
---
@@ -341,6 +400,7 @@ Required properties:
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-a83t-display-engine
* allwinner,sun8i-h3-display-engine
+ * allwinner,sun8i-r40-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
diff --git a/dts/Bindings/display/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt
index 3055d5c..7bf1bb4 100644
--- a/dts/Bindings/display/tilcdc/tilcdc.txt
+++ b/dts/Bindings/display/tilcdc/tilcdc.txt
@@ -8,8 +8,6 @@ Required properties:
- reg: base address and size of the LCDC device
Recommended properties:
- - interrupt-parent: the phandle for the interrupt controller that
- services interrupts for this device.
- ti,hwmods: Name of the hwmod associated to the LCDC
Optional properties:
diff --git a/dts/Bindings/dma/jz4780-dma.txt b/dts/Bindings/dma/jz4780-dma.txt
index f25feee..03e9cf7 100644
--- a/dts/Bindings/dma/jz4780-dma.txt
+++ b/dts/Bindings/dma/jz4780-dma.txt
@@ -5,7 +5,6 @@ Required properties:
- compatible: Should be "ingenic,jz4780-dma"
- reg: Should contain the DMA controller registers location and length.
- interrupts: Should contain the interrupt specifier of the DMA controller.
-- interrupt-parent: Should be the phandle of the interrupt controller that
- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
DMA clients (see below).
diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.txt b/dts/Bindings/dma/nvidia,tegra210-adma.txt
index 1e1dc8f..2f35b04 100644
--- a/dts/Bindings/dma/nvidia,tegra210-adma.txt
+++ b/dts/Bindings/dma/nvidia,tegra210-adma.txt
@@ -8,7 +8,6 @@ Required properties:
- reg: Should contain DMA registers location and length. This should be
a single entry that includes all of the per-channel registers in one
contiguous bank.
-- interrupt-parent: Phandle to the interrupt parent controller.
- interrupts: Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
- clocks: Must contain one entry for the ADMA module clock
diff --git a/dts/Bindings/dma/owl-dma.txt b/dts/Bindings/dma/owl-dma.txt
new file mode 100644
index 0000000..03e9bb1
--- /dev/null
+++ b/dts/Bindings/dma/owl-dma.txt
@@ -0,0 +1,47 @@
+* Actions Semi Owl SoCs DMA controller
+
+This binding follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+- compatible: Should be "actions,s900-dma".
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain 4 interrupts shared by all channel.
+- #dma-cells: Must be <1>. Used to represent the number of integer
+ cells in the dmas property of client device.
+- dma-channels: Physical channels supported.
+- dma-requests: Number of DMA request signals supported by the controller.
+ Refer to Documentation/devicetree/bindings/dma/dma.txt
+- clocks: Phandle and Specifier of the clock feeding the DMA controller.
+
+Example:
+
+Controller:
+ dma: dma-controller@e0260000 {
+ compatible = "actions,s900-dma";
+ reg = <0x0 0xe0260000 0x0 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <12>;
+ dma-requests = <46>;
+ clocks = <&clock CLK_DMAC>;
+ };
+
+Client:
+
+DMA clients connected to the Actions Semi Owl SoCs DMA controller must
+use the format described in the dma.txt file, using a two-cell specifier
+for each channel.
+
+The two cells in order are:
+1. A phandle pointing to the DMA controller.
+2. The channel id.
+
+uart5: serial@e012a000 {
+ ...
+ dma-names = "tx", "rx";
+ dmas = <&dma 26>, <&dma 27>;
+ ...
+};
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index b1ba639..946229c 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -29,6 +29,7 @@ Required Properties:
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
+ - "renesas,dmac-r8a77990" (R-Car E3)
- "renesas,dmac-r8a77995" (R-Car D3)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.txt b/dts/Bindings/dma/snps,dw-axi-dmac.txt
index f237b79..dbe1604 100644
--- a/dts/Bindings/dma/snps,dw-axi-dmac.txt
+++ b/dts/Bindings/dma/snps,dw-axi-dmac.txt
@@ -5,8 +5,6 @@ Required properties:
- reg: Address range of the DMAC registers. This should include
all of the per-channel registers.
- interrupt: Should contain the DMAC interrupt number.
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device.
- dma-channels: Number of channels supported by hardware.
- snps,dma-masters: Number of AXI masters supported by the hardware.
- snps,data-width: Maximum AXI data width supported by hardware.
diff --git a/dts/Bindings/dma/snps-dma.txt b/dts/Bindings/dma/snps-dma.txt
index 99acc71..39e2b26 100644
--- a/dts/Bindings/dma/snps-dma.txt
+++ b/dts/Bindings/dma/snps-dma.txt
@@ -23,8 +23,6 @@ Deprecated properties:
Optional properties:
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- is_private: The device channels should be marked as private and not for by the
general purpose DMA channel allocator. False if not passed.
- multi-block: Multi block transfers supported by hardware. Array property with
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 3f15f66..4bbc94d 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -201,7 +201,6 @@ Required properties:
- #dma-cells: Should be set to <1>
Clients should use a single channel number per DMA request.
- reg: Memory map for accessing module
-- interrupt-parent: Interrupt controller the interrupt is routed through
- interrupts: Exactly 3 interrupts need to be specified in the order:
1. Transfer completion interrupt.
2. Memory protection interrupt.
diff --git a/dts/Bindings/dma/xilinx/xilinx_dma.txt b/dts/Bindings/dma/xilinx/xilinx_dma.txt
index a2b8bfa..174af2c 100644
--- a/dts/Bindings/dma/xilinx/xilinx_dma.txt
+++ b/dts/Bindings/dma/xilinx/xilinx_dma.txt
@@ -66,6 +66,8 @@ Optional child node properties:
Optional child node properties for VDMA:
- xlnx,genlock-mode: Tells Genlock synchronization is
enabled/disabled in hardware.
+- xlnx,enable-vert-flip: Tells vertical flip is
+ enabled/disabled in hardware(S2MM path).
Optional child node properties for AXI DMA:
-dma-channels: Number of dma channels in child node.
diff --git a/dts/Bindings/dma/xilinx/zynqmp_dma.txt b/dts/Bindings/dma/xilinx/zynqmp_dma.txt
index a784cdd..07a5a7a 100644
--- a/dts/Bindings/dma/xilinx/zynqmp_dma.txt
+++ b/dts/Bindings/dma/xilinx/zynqmp_dma.txt
@@ -5,7 +5,6 @@ control and rate control support for slave/peripheral dma access.
Required properties:
- compatible : Should be "xlnx,zynqmp-dma-1.0"
- reg : Memory map for gdma/adma module access.
-- interrupt-parent : Interrupt controller the interrupt is routed through
- interrupts : Should contain DMA channel interrupt.
- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
- clock-names : List of input clocks "clk_main", "clk_apb"
diff --git a/dts/Bindings/eeprom/at24.txt b/dts/Bindings/eeprom/at24.txt
index 61d833a..aededdb 100644
--- a/dts/Bindings/eeprom/at24.txt
+++ b/dts/Bindings/eeprom/at24.txt
@@ -72,6 +72,8 @@ Optional properties:
- wp-gpios: GPIO to which the write-protect pin of the chip is connected.
+ - address-width: number of address bits (one of 8, 16).
+
Example:
eeprom@52 {
diff --git a/dts/Bindings/extcon/extcon-rt8973a.txt b/dts/Bindings/extcon/extcon-rt8973a.txt
index 6dede7d..cfcf455 100644
--- a/dts/Bindings/extcon/extcon-rt8973a.txt
+++ b/dts/Bindings/extcon/extcon-rt8973a.txt
@@ -11,8 +11,6 @@ for USB D-/D+ switching.
Required properties:
- compatible: Should be "richtek,rt8973a-muic"
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
- the interrupts from rt8973a are delivered to.
- interrupts: Interrupt specifiers for detection interrupt sources.
Example:
diff --git a/dts/Bindings/extcon/extcon-sm5502.txt b/dts/Bindings/extcon/extcon-sm5502.txt
index 4ecda22..fc3888e 100644
--- a/dts/Bindings/extcon/extcon-sm5502.txt
+++ b/dts/Bindings/extcon/extcon-sm5502.txt
@@ -9,8 +9,6 @@ the host controller using an I2C interface.
Required properties:
- compatible: Should be "siliconmitus,sm5502-muic"
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
- the interrupts from sm5502 are delivered to.
- interrupts: Interrupt specifiers for detection interrupt sources.
Example:
diff --git a/dts/Bindings/fsi/fsi-master-ast-cf.txt b/dts/Bindings/fsi/fsi-master-ast-cf.txt
new file mode 100644
index 0000000..3dc752d
--- /dev/null
+++ b/dts/Bindings/fsi/fsi-master-ast-cf.txt
@@ -0,0 +1,36 @@
+Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
+------------------------------------------------------------------------
+
+Required properties:
+ - compatible =
+ "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
+ or
+ "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
+
+ - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
+ - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
+ - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
+ - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
+ - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
+ functions (eg, external FSI masters)
+ - memory-region = <phandle>; : Reference to the reserved memory for
+ the ColdFire. Must be 2M aligned on
+ AST2400 and 1M aligned on AST2500
+ - aspeed,sram = <phandle>; : Reference to the SRAM node.
+ - aspeed,cvic = <phandle>; : Reference to the CVIC node.
+
+Examples:
+
+ fsi-master {
+ compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
+
+ clock-gpios = <&gpio 0>;
+ data-gpios = <&gpio 1>;
+ enable-gpios = <&gpio 2>;
+ trans-gpios = <&gpio 3>;
+ mux-gpios = <&gpio 4>;
+
+ memory-region = <&coldfire_memory>;
+ aspeed,sram = <&sram>;
+ aspeed,cvic = <&cvic>;
+ }
diff --git a/dts/Bindings/fsi/fsi.txt b/dts/Bindings/fsi/fsi.txt
index ab516c6..afb4ecc 100644
--- a/dts/Bindings/fsi/fsi.txt
+++ b/dts/Bindings/fsi/fsi.txt
@@ -83,6 +83,10 @@ addresses and sizes in the slave address space:
#address-cells = <1>;
#size-cells = <1>;
+Optionally, a slave can provide a global unique chip ID which is used to
+identify the physical location of the chip in a system specific way
+
+ chip-id = <0>;
FSI engines (devices)
---------------------
@@ -125,6 +129,7 @@ device tree if no extra platform information is required.
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
+ chip-id = <0>;
/* FSI engine at 0xc00, using a single page. In this example,
* it's an I2C master controller, so subnodes describe the
diff --git a/dts/Bindings/gnss/gnss.txt b/dts/Bindings/gnss/gnss.txt
new file mode 100644
index 0000000..f1e4a2f
--- /dev/null
+++ b/dts/Bindings/gnss/gnss.txt
@@ -0,0 +1,36 @@
+GNSS Receiver DT binding
+
+This documents the binding structure and common properties for GNSS receiver
+devices.
+
+A GNSS receiver node is a node named "gnss" and typically resides on a serial
+bus (e.g. UART, I2C or SPI).
+
+Please refer to the following documents for generic properties:
+
+ Documentation/devicetree/bindings/serial/slave-device.txt
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Required properties:
+
+- compatible : A string reflecting the vendor and specific device the node
+ represents
+
+Optional properties:
+- enable-gpios : GPIO used to enable the device
+- timepulse-gpios : Time pulse GPIO
+
+Example:
+
+serial@1234 {
+ compatible = "ns16550a";
+
+ gnss {
+ compatible = "u-blox,neo-8";
+
+ vcc-supply = <&gnss_reg>;
+ timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+
+ current-speed = <4800>;
+ };
+};
diff --git a/dts/Bindings/gnss/sirfstar.txt b/dts/Bindings/gnss/sirfstar.txt
new file mode 100644
index 0000000..648d183
--- /dev/null
+++ b/dts/Bindings/gnss/sirfstar.txt
@@ -0,0 +1,45 @@
+SiRFstar-based GNSS Receiver DT binding
+
+SiRFstar chipsets are used in GNSS-receiver modules produced by several
+vendors and can use UART, SPI or I2C interfaces.
+
+Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
+properties.
+
+Required properties:
+
+- compatible : Must be one of
+
+ "fastrax,uc430"
+ "linx,r4"
+ "wi2wi,w2sg0008i"
+ "wi2wi,w2sg0084i"
+
+- vcc-supply : Main voltage regulator (pin name: 3V3_IN, VCC, VDD)
+
+Required properties (I2C):
+- reg : I2C slave address
+
+Required properties (SPI):
+- reg : SPI chip select address
+
+Optional properties:
+
+- sirf,onoff-gpios : GPIO used to power on and off device (pin name: ON_OFF)
+- sirf,wakeup-gpios : GPIO used to determine device power state
+ (pin name: RFPWRUP, WAKEUP)
+- timepulse-gpios : Time pulse GPIO (pin name: 1PPS, TM)
+
+Example:
+
+serial@1234 {
+ compatible = "ns16550a";
+
+ gnss {
+ compatible = "wi2wi,w2sg0084i";
+
+ vcc-supply = <&gnss_reg>;
+ sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/dts/Bindings/gnss/u-blox.txt b/dts/Bindings/gnss/u-blox.txt
new file mode 100644
index 0000000..e475659
--- /dev/null
+++ b/dts/Bindings/gnss/u-blox.txt
@@ -0,0 +1,44 @@
+u-blox GNSS Receiver DT binding
+
+The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces.
+
+Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
+properties.
+
+Required properties:
+
+- compatible : Must be one of
+
+ "u-blox,neo-8"
+ "u-blox,neo-m8"
+
+- vcc-supply : Main voltage regulator
+
+Required properties (DDC):
+- reg : DDC (I2C) slave address
+
+Required properties (SPI):
+- reg : SPI chip select address
+
+Required properties (USB):
+- reg : Number of the USB hub port or the USB host-controller port
+ to which this device is attached
+
+Optional properties:
+
+- timepulse-gpios : Time pulse GPIO
+- u-blox,extint-gpios : GPIO connected to the "external interrupt" input pin
+- v-bckp-supply : Backup voltage regulator
+
+Example:
+
+serial@1234 {
+ compatible = "ns16550a";
+
+ gnss {
+ compatible = "u-blox,neo-8";
+
+ v-bckp-supply = <&gnss_v_bckp_reg>;
+ vcc-supply = <&gnss_vcc_reg>;
+ };
+};
diff --git a/dts/Bindings/gpio/8xxx_gpio.txt b/dts/Bindings/gpio/8xxx_gpio.txt
index 798cfc9..973362e 100644
--- a/dts/Bindings/gpio/8xxx_gpio.txt
+++ b/dts/Bindings/gpio/8xxx_gpio.txt
@@ -25,8 +25,6 @@ Required properties:
- #gpio-cells: Should be two. The first cell is the pin number
and the second cell is used to specify optional
parameters (currently unused).
-- interrupt-parent: Phandle for the interrupt controller that
- services interrupts for this device.
- interrupts: Interrupt mapping for GPIO IRQ.
- gpio-controller: Marks the port as GPIO controller.
diff --git a/dts/Bindings/gpio/abilis,tb10x-gpio.txt b/dts/Bindings/gpio/abilis,tb10x-gpio.txt
index a25c87b..ce19c56 100644
--- a/dts/Bindings/gpio/abilis,tb10x-gpio.txt
+++ b/dts/Bindings/gpio/abilis,tb10x-gpio.txt
@@ -14,7 +14,6 @@ Optional Properties:
- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
- interrupts: Defines the interrupt line connecting this GPIO controller to
its parent interrupt controller.
-- interrupt-parent: Defines the parent interrupt controller.
GPIO ranges are specified as described in
Documentation/devicetree/bindings/gpio/gpio.txt
diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
index b405b44..5d468ec 100644
--- a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
+++ b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
@@ -30,9 +30,6 @@ Optional properties:
- interrupts:
The interrupt shared by all GPIO lines for this controller.
-- interrupt-parent:
- phandle of the parent interrupt controller
-
- interrupts-extended:
Alternate form of specifying interrupts and parents that allows for
multiple parents. This takes precedence over 'interrupts' and
diff --git a/dts/Bindings/gpio/fsl-imx-gpio.txt b/dts/Bindings/gpio/fsl-imx-gpio.txt
index dbd22e0..b4cd9f9 100644
--- a/dts/Bindings/gpio/fsl-imx-gpio.txt
+++ b/dts/Bindings/gpio/fsl-imx-gpio.txt
@@ -19,6 +19,9 @@ Required properties:
4 = active high level-sensitive.
8 = active low level-sensitive.
+Optional properties:
+- clocks: the clock for clocking the GPIO silicon
+
Example:
gpio0: gpio@73f84000 {
diff --git a/dts/Bindings/gpio/gpio-adnp.txt b/dts/Bindings/gpio/gpio-adnp.txt
index af66b27..a28902a 100644
--- a/dts/Bindings/gpio/gpio-adnp.txt
+++ b/dts/Bindings/gpio/gpio-adnp.txt
@@ -3,7 +3,6 @@ Avionic Design N-bit GPIO expander bindings
Required properties:
- compatible: should be "ad,gpio-adnp"
- reg: The I2C slave address for this device.
-- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
second cell is used to specify optional parameters:
diff --git a/dts/Bindings/gpio/gpio-aspeed.txt b/dts/Bindings/gpio/gpio-aspeed.txt
index fc6378c..7e9b586 100644
--- a/dts/Bindings/gpio/gpio-aspeed.txt
+++ b/dts/Bindings/gpio/gpio-aspeed.txt
@@ -17,7 +17,6 @@ Required properties:
Optional properties:
-- interrupt-parent : The parent interrupt controller, optional if inherited
- clocks : A phandle to the clock to use for debounce timings
The gpio and interrupt properties are further described in their respective
diff --git a/dts/Bindings/gpio/gpio-ath79.txt b/dts/Bindings/gpio/gpio-ath79.txt
index c522851..cf71f3e 100644
--- a/dts/Bindings/gpio/gpio-ath79.txt
+++ b/dts/Bindings/gpio/gpio-ath79.txt
@@ -12,7 +12,6 @@ Required properties:
- ngpios: Should be set to the number of GPIOs available on the SoC.
Optional properties:
-- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
diff --git a/dts/Bindings/gpio/gpio-davinci.txt b/dts/Bindings/gpio/gpio-davinci.txt
index 8beb053..553b92a 100644
--- a/dts/Bindings/gpio/gpio-davinci.txt
+++ b/dts/Bindings/gpio/gpio-davinci.txt
@@ -15,8 +15,6 @@ Required Properties:
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
-- interrupt-parent: phandle of the parent interrupt controller.
-
- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
supported at a time.
diff --git a/dts/Bindings/gpio/gpio-max732x.txt b/dts/Bindings/gpio/gpio-max732x.txt
index 5fdc843..b3a9c0c 100644
--- a/dts/Bindings/gpio/gpio-max732x.txt
+++ b/dts/Bindings/gpio/gpio-max732x.txt
@@ -30,7 +30,6 @@ Optional properties:
- #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
- first cell is the pin number
- second cell is used to specify flags
- - interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
Please refer to gpio.txt in this directory for details of the common GPIO
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index 88f2286..4e3c550 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -37,6 +37,7 @@ Required properties:
- #interrupt-cells: if to be used as interrupt expander.
Optional properties:
+ - interrupts: interrupt specifier for the device's interrupt output.
- reset-gpios: GPIO specification for the RESET input. This is an
active low signal to the PCA953x.
- vcc-supply: power supply regulator.
@@ -49,6 +50,8 @@ Example:
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9505>;
+ gpio-controller;
+ #gpio-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
};
diff --git a/dts/Bindings/gpio/gpio-pcf857x.txt b/dts/Bindings/gpio/gpio-pcf857x.txt
index 7d3bd63..a482455 100644
--- a/dts/Bindings/gpio/gpio-pcf857x.txt
+++ b/dts/Bindings/gpio/gpio-pcf857x.txt
@@ -49,7 +49,6 @@ Optional Properties:
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
- - interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
diff --git a/dts/Bindings/gpio/gpio-uniphier.txt b/dts/Bindings/gpio/gpio-uniphier.txt
index fed9158..f281f12 100644
--- a/dts/Bindings/gpio/gpio-uniphier.txt
+++ b/dts/Bindings/gpio/gpio-uniphier.txt
@@ -6,7 +6,6 @@ Required properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the pin number and the second
cell is used to specify optional parameters.
-- interrupt-parent: Specifies the parent interrupt controller.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
The second cell bits[3:0] is used to specify trigger type as follows:
diff --git a/dts/Bindings/gpio/gpio-xgene-sb.txt b/dts/Bindings/gpio/gpio-xgene-sb.txt
index 5490c1d..e90fb98 100644
--- a/dts/Bindings/gpio/gpio-xgene-sb.txt
+++ b/dts/Bindings/gpio/gpio-xgene-sb.txt
@@ -26,7 +26,6 @@ Required properties:
1 = active low
- gpio-controller: Marks the device node as a GPIO controller.
- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
-- interrupt-parent: Phandle of the parent interrupt controller.
- interrupt-cells: Should be two.
- first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
- second cell is used to specify flags.
diff --git a/dts/Bindings/gpio/gpio-xilinx.txt b/dts/Bindings/gpio/gpio-xilinx.txt
index 63bf4be..08eed23 100644
--- a/dts/Bindings/gpio/gpio-xilinx.txt
+++ b/dts/Bindings/gpio/gpio-xilinx.txt
@@ -14,8 +14,6 @@ Required properties:
Optional properties:
- interrupts : Interrupt mapping for GPIO IRQ.
-- interrupt-parent : Phandle for the interrupt controller that
- services interrupts for this device.
- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
- xlnx,gpio-width : gpio width
diff --git a/dts/Bindings/gpio/gpio-xlp.txt b/dts/Bindings/gpio/gpio-xlp.txt
index 28662d8..47fc649 100644
--- a/dts/Bindings/gpio/gpio-xlp.txt
+++ b/dts/Bindings/gpio/gpio-xlp.txt
@@ -30,7 +30,6 @@ Required properties:
4 = active high level-sensitive.
8 = active low level-sensitive.
- interrupts: Interrupt number for this device.
-- interrupt-parent: phandle of the parent interrupt controller.
- interrupt-controller: Identifies the node as an interrupt controller.
Example:
diff --git a/dts/Bindings/gpio/gpio-zynq.txt b/dts/Bindings/gpio/gpio-zynq.txt
index 7b54265..4fa4eb5 100644
--- a/dts/Bindings/gpio/gpio-zynq.txt
+++ b/dts/Bindings/gpio/gpio-zynq.txt
@@ -11,7 +11,6 @@ Required properties:
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt specifier (see interrupt bindings for
details)
-- interrupt-parent : Must be core interrupt controller
- interrupt-controller : Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2. The first cell is the GPIO number.
The second cell bits[3:0] is used to specify trigger type and level flags:
diff --git a/dts/Bindings/gpio/mediatek,mt7621-gpio.txt b/dts/Bindings/gpio/mediatek,mt7621-gpio.txt
new file mode 100644
index 0000000..ba45558
--- /dev/null
+++ b/dts/Bindings/gpio/mediatek,mt7621-gpio.txt
@@ -0,0 +1,35 @@
+Mediatek MT7621 SoC GPIO controller bindings
+
+The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
+The registers of all the banks are interwoven inside one single IO range.
+We load one GPIO controller instance per bank. Also the GPIO controller can receive
+interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
+using GIC INT12.
+
+Required properties for the top level node:
+- #gpio-cells : Should be two. The first cell is the GPIO pin number and the
+ second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
+ Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt. Should be 2. The first cell defines the interrupt number,
+ the second encodes the triger flags encoded as described in
+ Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+- compatible:
+ - "mediatek,mt7621-gpio" for Mediatek controllers
+- reg : Physical base address and length of the controller's registers
+- interrupt-parent : phandle of the parent interrupt controller.
+- interrupts : Interrupt specifier for the controllers interrupt.
+- interrupt-controller : Mark the device node as an interrupt controller.
+- gpio-controller : Marks the device node as a GPIO controller.
+
+Example:
+ gpio@600 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "mediatek,mt7621-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0x600 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/gpio/nintendo,hollywood-gpio.txt b/dts/Bindings/gpio/nintendo,hollywood-gpio.txt
index 45a61b4..df63da4 100644
--- a/dts/Bindings/gpio/nintendo,hollywood-gpio.txt
+++ b/dts/Bindings/gpio/nintendo,hollywood-gpio.txt
@@ -14,7 +14,6 @@ Optional properties:
- #interrupt-cells: Should be two.
- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
interrupt.
-- interrupt-parent: phandle of the parent interrupt controller.
Example:
diff --git a/dts/Bindings/gpio/nvidia,tegra186-gpio.txt b/dts/Bindings/gpio/nvidia,tegra186-gpio.txt
index c82a2e2..adff16c 100644
--- a/dts/Bindings/gpio/nvidia,tegra186-gpio.txt
+++ b/dts/Bindings/gpio/nvidia,tegra186-gpio.txt
@@ -68,6 +68,8 @@ Required properties:
One of:
- "nvidia,tegra186-gpio".
- "nvidia,tegra186-gpio-aon".
+ - "nvidia,tegra194-gpio".
+ - "nvidia,tegra194-gpio-aon".
- reg-names
Array of strings.
Contains a list of names for the register spaces described by the reg
@@ -91,6 +93,8 @@ Required properties:
depending on compatible value:
- "nvidia,tegra186-gpio": 6 entries.
- "nvidia,tegra186-gpio-aon": 1 entry.
+ - "nvidia,tegra194-gpio": 6 entries.
+ - "nvidia,tegra194-gpio-aon": 1 entry.
- gpio-controller
Boolean.
Marks the device node as a GPIO controller/provider.
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 378f132..4018ee5 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -17,6 +17,7 @@ Required Properties:
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
- "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller.
- "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
+ - "renesas,gpio-r8a77980": for R8A77980 (R-Car V3H) compatible GPIO controller.
- "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO controller.
- "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
- "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
@@ -31,7 +32,6 @@ Required Properties:
- reg: Base address and length of each memory resource used by the GPIO
controller hardware module.
- - interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- gpio-controller: Marks the device node as a gpio controller.
diff --git a/dts/Bindings/gpio/rockchip,rk3328-grf-gpio.txt b/dts/Bindings/gpio/rockchip,rk3328-grf-gpio.txt
new file mode 100644
index 0000000..f9231df
--- /dev/null
+++ b/dts/Bindings/gpio/rockchip,rk3328-grf-gpio.txt
@@ -0,0 +1,32 @@
+Rockchip RK3328 GRF (General Register Files) GPIO controller.
+
+In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
+control, can also be used for general purpose. It is manipulated by the
+GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can
+also be set in the same way.
+
+Currently this GPIO controller only supports the mute pin. If needed in the
+future, the HDMI pins support can also be added.
+
+Required properties:
+- compatible: Should contain "rockchip,rk3328-grf-gpio".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be 2. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = Active high,
+ 1 = Active low.
+
+Example:
+
+ grf: syscon@ff100000 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+
+ grf_gpio: grf-gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+Note: The grf_gpio node should be declared as the child of the GRF (General
+Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
diff --git a/dts/Bindings/gpio/snps-dwapb-gpio.txt b/dts/Bindings/gpio/snps-dwapb-gpio.txt
index 3c1118b..7276b50 100644
--- a/dts/Bindings/gpio/snps-dwapb-gpio.txt
+++ b/dts/Bindings/gpio/snps-dwapb-gpio.txt
@@ -25,7 +25,6 @@ controller.
interrupt. Shall be set to 2. The first cell defines the interrupt number,
the second encodes the triger flags encoded as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-- interrupt-parent : The parent interrupt controller.
- interrupts : The interrupts to the parent controller raised when GPIOs
generate the interrupts. If the controller provides one combined interrupt
for all GPIOs, specify a single interrupt. If the controller provides one
diff --git a/dts/Bindings/hsi/omap-ssi.txt b/dts/Bindings/hsi/omap-ssi.txt
index 955e335..77a0c3c 100644
--- a/dts/Bindings/hsi/omap-ssi.txt
+++ b/dts/Bindings/hsi/omap-ssi.txt
@@ -33,7 +33,6 @@ Required Port sub-node properties:
- reg-names: Contains the values "tx" and "rx" (in this order).
- reg: Contains a matching register specifier for each entry
in reg-names.
-- interrupt-parent Should be a phandle for the interrupt controller
- interrupts: Should contain interrupt specifiers for mpu interrupts
0 and 1 (in this order).
- ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE
diff --git a/dts/Bindings/hwmon/npcm750-pwm-fan.txt b/dts/Bindings/hwmon/npcm750-pwm-fan.txt
new file mode 100644
index 0000000..28f43e9
--- /dev/null
+++ b/dts/Bindings/hwmon/npcm750-pwm-fan.txt
@@ -0,0 +1,84 @@
+Nuvoton NPCM7xx PWM and Fan Tacho controller device
+
+The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
+controller outputs and 16 Fan tachometer controller inputs.
+
+Required properties for pwm-fan node
+- #address-cells : should be 1.
+- #size-cells : should be 0.
+- compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
+- reg : specifies physical base address and size of the registers.
+- reg-names : must contain:
+ * "pwm" for the PWM registers.
+ * "fan" for the Fan registers.
+- clocks : phandle of reference clocks.
+- clock-names : must contain
+ * "pwm" for PWM controller operating clock.
+ * "fan" for Fan controller operating clock.
+- interrupts : contain the Fan interrupts with flags for falling edge.
+- pinctrl-names : a pinctrl state named "default" must be defined.
+- pinctrl-0 : phandle referencing pin configuration of the PWM and Fan
+ controller ports.
+
+fan subnode format:
+===================
+Under fan subnode can be upto 8 child nodes, each child node representing a fan.
+Each fan subnode must have one PWM channel and atleast one Fan tach channel.
+
+For PWM channel can be configured cooling-levels to create cooling device.
+Cooling device could be bound to a thermal zone for the thermal control.
+
+Required properties for each child node:
+- reg : specify the PWM output channel.
+ integer value in the range 0 through 7, that represent
+ the PWM channel number that used.
+
+- fan-tach-ch : specify the Fan tach input channel.
+ integer value in the range 0 through 15, that represent
+ the fan tach channel number that used.
+
+ At least one Fan tach input channel is required
+
+Optional property for each child node:
+- cooling-levels: PWM duty cycle values in a range from 0 to 255
+ which correspond to thermal cooling states.
+
+Examples:
+
+pwm_fan:pwm-fan-controller@103000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nuvoton,npcm750-pwm-fan";
+ reg = <0x103000 0x2000>,
+ <0x180000 0x8000>;
+ reg-names = "pwm", "fan";
+ clocks = <&clk NPCM7XX_CLK_APB3>,
+ <&clk NPCM7XX_CLK_APB4>;
+ clock-names = "pwm","fan";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins
+ &fanin0_pins &fanin1_pins &fanin2_pins
+ &fanin3_pins &fanin4_pins>;
+ fan@0 {
+ reg = <0x00>;
+ fan-tach-ch = /bits/ 8 <0x00 0x01>;
+ cooling-levels = <127 255>;
+ };
+ fan@1 {
+ reg = <0x01>;
+ fan-tach-ch = /bits/ 8 <0x02 0x03>;
+ };
+ fan@2 {
+ reg = <0x02>;
+ fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+};
diff --git a/dts/Bindings/i2c/i2c-aspeed.txt b/dts/Bindings/i2c/i2c-aspeed.txt
index e7106bf..8fbd863 100644
--- a/dts/Bindings/i2c/i2c-aspeed.txt
+++ b/dts/Bindings/i2c/i2c-aspeed.txt
@@ -11,9 +11,6 @@ Required Properties:
- resets : phandle to reset controller with the reset number in
the second cell
- interrupts : interrupt number
-- interrupt-parent : interrupt controller for bus, should reference a
- aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic
- interrupt controller
Optional Properties:
- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
diff --git a/dts/Bindings/i2c/i2c-brcmstb.txt b/dts/Bindings/i2c/i2c-brcmstb.txt
index aeceace..0380609 100644
--- a/dts/Bindings/i2c/i2c-brcmstb.txt
+++ b/dts/Bindings/i2c/i2c-brcmstb.txt
@@ -10,8 +10,6 @@ Required properties:
Optional properties :
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this one is cascaded from
- interrupts: specifies the interrupt number, the irq line to be used
- interrupt-names: Interrupt name string
diff --git a/dts/Bindings/i2c/i2c-fsi.txt b/dts/Bindings/i2c/i2c-fsi.txt
new file mode 100644
index 0000000..b1be2ce
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-fsi.txt
@@ -0,0 +1,40 @@
+Device-tree bindings for FSI-attached I2C master and busses
+-----------------------------------------------------------
+
+Required properties:
+ - compatible = "ibm,i2c-fsi";
+ - reg = < address size >; : The FSI CFAM address and address
+ space size.
+ - #address-cells = <1>; : Number of address cells in child
+ nodes.
+ - #size-cells = <0>; : Number of size cells in child nodes.
+ - child nodes : Nodes to describe busses off the I2C
+ master.
+
+Child node required properties:
+ - reg = < port number > : The port number on the I2C master.
+
+Child node optional properties:
+ - child nodes : Nodes to describe devices on the I2C
+ bus.
+
+Examples:
+
+ i2c@1800 {
+ compatible = "ibm,i2c-fsi";
+ reg = < 0x1800 0x400 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-bus@0 {
+ reg = <0>;
+ };
+
+ i2c-bus@1 {
+ reg = <1>;
+
+ eeprom@50 {
+ compatible = "vendor,dev-name";
+ };
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c-imx-lpi2c.txt b/dts/Bindings/i2c/i2c-imx-lpi2c.txt
index 60fe90d..00e4365 100644
--- a/dts/Bindings/i2c/i2c-imx-lpi2c.txt
+++ b/dts/Bindings/i2c/i2c-imx-lpi2c.txt
@@ -5,7 +5,6 @@ Required properties:
- "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
- "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc
- reg : address and length of the lpi2c master registers
-- interrupt-parent : core interrupt controller
- interrupts : lpi2c interrupt
- clocks : lpi2c clock specifier
diff --git a/dts/Bindings/i2c/i2c-jz4780.txt b/dts/Bindings/i2c/i2c-jz4780.txt
index d4a082a..3738cfb 100644
--- a/dts/Bindings/i2c/i2c-jz4780.txt
+++ b/dts/Bindings/i2c/i2c-jz4780.txt
@@ -11,10 +11,6 @@ Recommended properties:
- pinctrl-names: should be "default";
- pinctrl-0: phandle to pinctrl function
-Optional properties:
-- interrupt-parent: Should be the phandle of the interrupt controller that
- delivers interrupts to the I2C block.
-
Example
/ {
diff --git a/dts/Bindings/i2c/i2c-mpc.txt b/dts/Bindings/i2c/i2c-mpc.txt
index 1eacd6b..42a3905 100644
--- a/dts/Bindings/i2c/i2c-mpc.txt
+++ b/dts/Bindings/i2c/i2c-mpc.txt
@@ -15,8 +15,6 @@ Recommended properties :
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- fsl,preserve-clocking : boolean; if defined, the clock settings
from the bootloader are preserved (not touched).
- clock-frequency : desired I2C bus clock frequency in Hz.
diff --git a/dts/Bindings/i2c/i2c-mux-pca954x.txt b/dts/Bindings/i2c/i2c-mux-pca954x.txt
index 34d9150..ccf6c86 100644
--- a/dts/Bindings/i2c/i2c-mux-pca954x.txt
+++ b/dts/Bindings/i2c/i2c-mux-pca954x.txt
@@ -28,8 +28,6 @@ Optional Properties:
- i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
children in idle state. This is necessary for example, if there are several
multiplexers on the bus and the devices behind them use same I2C addresses.
- - interrupt-parent: Phandle for the interrupt controller that services
- interrupts for this device.
- interrupts: Interrupt mapping for IRQ.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be two.
diff --git a/dts/Bindings/i2c/i2c-owl.txt b/dts/Bindings/i2c/i2c-owl.txt
new file mode 100644
index 0000000..b743fe4
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-owl.txt
@@ -0,0 +1,27 @@
+Actions Semiconductor Owl I2C controller
+
+Required properties:
+
+- compatible : Should be "actions,s900-i2c".
+- reg : Offset and length of the register set for the device.
+- #address-cells : Should be 1.
+- #size-cells : Should be 0.
+- interrupts : A single interrupt specifier.
+- clocks : Phandle of the clock feeding the I2C controller.
+
+Optional properties:
+
+- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
+ Fast modes are supported, possible values are 100000 and
+ 400000.
+Examples:
+
+ i2c0: i2c@e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0170000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C0>;
+ clock-frequency = <100000>;
+ };
diff --git a/dts/Bindings/i2c/i2c-pca-platform.txt b/dts/Bindings/i2c/i2c-pca-platform.txt
index f1f3876..73a693d 100644
--- a/dts/Bindings/i2c/i2c-pca-platform.txt
+++ b/dts/Bindings/i2c/i2c-pca-platform.txt
@@ -12,8 +12,6 @@ Required properties :
Optional properties
- interrupts : the interrupt number
- - interrupt-parent : the phandle for the interrupt controller.
- If an interrupt is not specified polling will be used.
- reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
is active low, it should be marked GPIO_ACTIVE_LOW.
- clock-frequency : I2C bus frequency.
diff --git a/dts/Bindings/i2c/i2c-pnx.txt b/dts/Bindings/i2c/i2c-pnx.txt
index fe98ada..2a59006 100644
--- a/dts/Bindings/i2c/i2c-pnx.txt
+++ b/dts/Bindings/i2c/i2c-pnx.txt
@@ -7,8 +7,6 @@ Required properties:
- interrupts: configure one interrupt line
- #address-cells: always 1 (for i2c addresses)
- #size-cells: always 0
- - interrupt-parent: the phandle for the interrupt controller that
- services interrupts for this device.
Optional properties:
diff --git a/dts/Bindings/i2c/i2c-pxa.txt b/dts/Bindings/i2c/i2c-pxa.txt
index d30f0b1..c30783c 100644
--- a/dts/Bindings/i2c/i2c-pxa.txt
+++ b/dts/Bindings/i2c/i2c-pxa.txt
@@ -12,9 +12,6 @@ Required properties :
Recommended properties :
- interrupts : the interrupt number
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device. If the parent is the default
- interrupt controller in device tree, it could be ignored.
- mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
status register of i2c controller instead.
- mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index 7ce8fae..39cd21d 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible:
"renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
"renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
+ "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
@@ -16,11 +17,13 @@ Required properties:
"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
"renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
+ "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC.
"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.
- "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
+ "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 or RZ/G2 compatible
+ device.
"renesas,i2c-rcar" (deprecated)
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/i2c/i2c-sh_mobile.txt b/dts/Bindings/i2c/i2c-sh_mobile.txt
index fc7e178..872673a 100644
--- a/dts/Bindings/i2c/i2c-sh_mobile.txt
+++ b/dts/Bindings/i2c/i2c-sh_mobile.txt
@@ -6,6 +6,7 @@ Required properties:
- "renesas,iic-r8a7740" (R-Mobile A1)
- "renesas,iic-r8a7743" (RZ/G1M)
- "renesas,iic-r8a7745" (RZ/G1E)
+ - "renesas,iic-r8a774a1" (RZ/G2M)
- "renesas,iic-r8a7790" (R-Car H2)
- "renesas,iic-r8a7791" (R-Car M2-W)
- "renesas,iic-r8a7792" (R-Car V2H)
@@ -17,7 +18,8 @@ Required properties:
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
compatible device)
- - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
+ - "renesas,rcar-gen3-iic" (generic R-Car Gen3 or RZ/G2
+ compatible device)
- "renesas,rmobile-iic" (generic device)
When compatible with a generic R-Car version, nodes
diff --git a/dts/Bindings/iio/accel/adxl345.txt b/dts/Bindings/iio/accel/adxl345.txt
index e7111b0..f9525f6 100644
--- a/dts/Bindings/iio/accel/adxl345.txt
+++ b/dts/Bindings/iio/accel/adxl345.txt
@@ -1,9 +1,12 @@
-Analog Devices ADXL345 3-Axis, +/-(2g/4g/8g/16g) Digital Accelerometer
+Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers
http://www.analog.com/en/products/mems/accelerometers/adxl345.html
+http://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html
Required properties:
- - compatible : should be "adi,adxl345"
+ - compatible : should be one of
+ "adi,adxl345"
+ "adi,adxl375"
- reg : the I2C address or SPI chip select number of the sensor
Required properties for SPI bus usage:
@@ -11,8 +14,6 @@ Required properties for SPI bus usage:
- spi-cpol and spi-cpha : must be defined for adxl345 to enable SPI mode 3
Optional properties:
- - interrupt-parent : phandle to the parent interrupt controller as documented
- in Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
diff --git a/dts/Bindings/iio/accel/bma180.txt b/dts/Bindings/iio/accel/bma180.txt
index 4a3679d..3b25b4c 100644
--- a/dts/Bindings/iio/accel/bma180.txt
+++ b/dts/Bindings/iio/accel/bma180.txt
@@ -10,8 +10,6 @@ Required properties:
Optional properties:
- - interrupt-parent : should be the phandle for the interrupt controller
-
- interrupts : interrupt mapping for GPIO IRQ, it should by configured with
flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING
For the bma250 the first interrupt listed must be the one
diff --git a/dts/Bindings/iio/accel/mma8452.txt b/dts/Bindings/iio/accel/mma8452.txt
index 45f5c5c..2100e9a 100644
--- a/dts/Bindings/iio/accel/mma8452.txt
+++ b/dts/Bindings/iio/accel/mma8452.txt
@@ -15,8 +15,6 @@ Required properties:
Optional properties:
- - interrupt-parent: should be the phandle for the interrupt controller
-
- interrupts: interrupt mapping for GPIO IRQ
- interrupt-names: should contain "INT1" and/or "INT2", the accelerometer's
diff --git a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
index d1acd5e..54b823f 100644
--- a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
+++ b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: depending on the SoC this should be one of:
- "amlogic,meson8-saradc" for Meson8
- "amlogic,meson8b-saradc" for Meson8b
+ - "amlogic,meson8m2-saradc" for Meson8m2
- "amlogic,meson-gxbb-saradc" for GXBB
- "amlogic,meson-gxl-saradc" for GXL
- "amlogic,meson-gxm-saradc" for GXM
diff --git a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
index 6469a4c..4a3c1d4 100644
--- a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
@@ -21,6 +21,14 @@ Optional properties:
- dmas: Phandle to dma channel for the ADC.
- dma-names: Must be "rx" when dmas property is being used.
See ../../dma/dma.txt for details.
+ - #io-channel-cells: in case consumer drivers are attached, this must be 1.
+ See <Documentation/devicetree/bindings/iio/iio-bindings.txt> for details.
+
+Properties for consumer drivers:
+ - Consumer drivers can be connected to this producer device, as specified
+ in <Documentation/devicetree/bindings/iio/iio-bindings.txt>
+ - Channels exposed are specified in:
+ <dt-bindings/iio/adc/at91-sama5d2_adc.txt>
Example:
@@ -38,4 +46,5 @@ adc: adc@fc030000 {
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
dma-names = "rx";
+ #io-channel-cells = <1>;
}
diff --git a/dts/Bindings/iio/adc/avia-hx711.txt b/dts/Bindings/iio/adc/avia-hx711.txt
index b362940..7222328 100644
--- a/dts/Bindings/iio/adc/avia-hx711.txt
+++ b/dts/Bindings/iio/adc/avia-hx711.txt
@@ -8,11 +8,17 @@ Required properties:
See Documentation/devicetree/bindings/gpio/gpio.txt
- avdd-supply: Definition of the regulator used as analog supply
+Optional properties:
+ - clock-frequency: Frequency of PD_SCK in Hz
+ Minimum value allowed is 10 kHz because of maximum
+ high time of 50 microseconds.
+
Example:
-weight@0 {
+weight {
compatible = "avia,hx711";
sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
avdd-suppy = <&avdd>;
+ clock-frequency = <100000>;
};
diff --git a/dts/Bindings/iio/adc/cpcap-adc.txt b/dts/Bindings/iio/adc/cpcap-adc.txt
index 487ea96..ec04008 100644
--- a/dts/Bindings/iio/adc/cpcap-adc.txt
+++ b/dts/Bindings/iio/adc/cpcap-adc.txt
@@ -2,7 +2,6 @@ Motorola CPCAP PMIC ADC binding
Required properties:
- compatible: Should be "motorola,cpcap-adc" or "motorola,mapphone-cpcap-adc"
-- interrupt-parent: The interrupt controller
- interrupts: The interrupt number for the ADC device
- interrupt-names: Should be "adcdone"
- #io-channel-cells: Number of cells in an IIO specifier
diff --git a/dts/Bindings/iio/adc/fsl,imx25-gcq.txt b/dts/Bindings/iio/adc/fsl,imx25-gcq.txt
index b0866d3..eebdcec 100644
--- a/dts/Bindings/iio/adc/fsl,imx25-gcq.txt
+++ b/dts/Bindings/iio/adc/fsl,imx25-gcq.txt
@@ -8,7 +8,6 @@ Required properties:
- reg: Should be the register range of the module.
- interrupts: Should be the interrupt number of the module.
Typically this is <1>.
- - interrupt-parent: phandle to the tsadc module of the i.MX25.
- #address-cells: Should be <1> (setting for the subnodes)
- #size-cells: Should be <0> (setting for the subnodes)
diff --git a/dts/Bindings/iio/adc/max1027-adc.txt b/dts/Bindings/iio/adc/max1027-adc.txt
index a8770cc..e680c61 100644
--- a/dts/Bindings/iio/adc/max1027-adc.txt
+++ b/dts/Bindings/iio/adc/max1027-adc.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: Should be "maxim,max1027" or "maxim,max1029" or "maxim,max1031"
- reg: SPI chip select number for the device
- - interrupt-parent: phandle to the parent interrupt controller
- see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupts: IRQ line for the ADC
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
diff --git a/dts/Bindings/iio/adc/sigma-delta-modulator.txt b/dts/Bindings/iio/adc/sigma-delta-modulator.txt
index ba24ca7..59b92cd 100644
--- a/dts/Bindings/iio/adc/sigma-delta-modulator.txt
+++ b/dts/Bindings/iio/adc/sigma-delta-modulator.txt
@@ -7,7 +7,7 @@ Required properties:
Example node:
- ads1202: adc@0 {
+ ads1202: adc {
compatible = "sd-modulator";
#io-channel-cells = <0>;
};
diff --git a/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt b/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt
new file mode 100644
index 0000000..8aad960
--- /dev/null
+++ b/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt
@@ -0,0 +1,36 @@
+Spreadtrum SC27XX series PMICs ADC binding
+
+Required properties:
+- compatible: Should be one of the following.
+ "sprd,sc2720-adc"
+ "sprd,sc2721-adc"
+ "sprd,sc2723-adc"
+ "sprd,sc2730-adc"
+ "sprd,sc2731-adc"
+- reg: The address offset of ADC controller.
+- interrupt-parent: The interrupt controller.
+- interrupts: The interrupt number for the ADC device.
+- #io-channel-cells: Number of cells in an IIO specifier.
+- hwlocks: Reference to a phandle of a hwlock provider node.
+
+Example:
+
+ sc2731_pmic: pmic@0 {
+ compatible = "sprd,sc2731";
+ reg = <0>;
+ spi-max-frequency = <26000000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic_adc: adc@480 {
+ compatible = "sprd,sc2731-adc";
+ reg = <0x480>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ hwlocks = <&hwlock 4>;
+ };
+ };
diff --git a/dts/Bindings/iio/adc/st,stm32-adc.txt b/dts/Bindings/iio/adc/st,stm32-adc.txt
index f1ead43..8346bcb 100644
--- a/dts/Bindings/iio/adc/st,stm32-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-adc.txt
@@ -60,7 +60,6 @@ Required properties:
- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
- clocks: Input clock private to this ADC instance. It's required only on
stm32f4, that has per instance clock input for registers access.
-- interrupt-parent: Phandle to the parent interrupt controller.
- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
2 for adc@200).
- st,adc-channels: List of single-ended channels muxed for this ADC.
diff --git a/dts/Bindings/iio/adc/xilinx-xadc.txt b/dts/Bindings/iio/adc/xilinx-xadc.txt
index d71258e..e0e0755 100644
--- a/dts/Bindings/iio/adc/xilinx-xadc.txt
+++ b/dts/Bindings/iio/adc/xilinx-xadc.txt
@@ -22,7 +22,6 @@ Required properties:
clock to the AXI bus interface of the core.
Optional properties:
- - interrupt-parent: phandle to the parent interrupt controller
- xlnx,external-mux:
* "none": No external multiplexer is used, this is the default
if the property is omitted.
diff --git a/dts/Bindings/iio/chemical/atlas,ec-sm.txt b/dts/Bindings/iio/chemical/atlas,ec-sm.txt
index 2962bd9..f432059 100644
--- a/dts/Bindings/iio/chemical/atlas,ec-sm.txt
+++ b/dts/Bindings/iio/chemical/atlas,ec-sm.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: must be "atlas,ec-sm"
- reg: the I2C address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/chemical/atlas,orp-sm.txt b/dts/Bindings/iio/chemical/atlas,orp-sm.txt
index 5d8b687..af1f5a9 100644
--- a/dts/Bindings/iio/chemical/atlas,orp-sm.txt
+++ b/dts/Bindings/iio/chemical/atlas,orp-sm.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: must be "atlas,orp-sm"
- reg: the I2C address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/chemical/atlas,ph-sm.txt b/dts/Bindings/iio/chemical/atlas,ph-sm.txt
index cffa190..79d90f0 100644
--- a/dts/Bindings/iio/chemical/atlas,ph-sm.txt
+++ b/dts/Bindings/iio/chemical/atlas,ph-sm.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: must be "atlas,ph-sm"
- reg: the I2C address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/dac/ad5758.txt b/dts/Bindings/iio/dac/ad5758.txt
new file mode 100644
index 0000000..bba01a5
--- /dev/null
+++ b/dts/Bindings/iio/dac/ad5758.txt
@@ -0,0 +1,78 @@
+Analog Devices AD5758 DAC device driver
+
+Required properties for the AD5758:
+ - compatible: Must be "adi,ad5758"
+ - reg: SPI chip select number for the device
+ - spi-max-frequency: Max SPI frequency to use (< 50000000)
+ - spi-cpha: is the only mode that is supported
+
+Required properties:
+
+ - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter
+ Dynamic Power Control (DPC)
+ In this mode, the AD5758 circuitry senses the output
+ voltage and dynamically regulates the supply voltage,
+ VDPC+, to meet compliance requirements plus an optimized
+ headroom voltage for the output buffer.
+
+ Programmable Power Control (PPC)
+ In this mode, the VDPC+ voltage is user-programmable to
+ a fixed level that needs to accommodate the maximum output
+ load required.
+
+ The output of the DAC core is either converted to a
+ current or voltage output at the VIOUT pin. Only one mode
+ can be enabled at any one time.
+
+ The following values are currently supported:
+ * 1: DPC current mode
+ * 2: DPC voltage mode
+ * 3: PPC current mode
+
+ Depending on the selected output mode (voltage or current) one of the
+ two properties must
+ be present:
+
+ - adi,range-microvolt: Voltage output range
+ The array of voltage output ranges must contain two fields:
+ * <0 5000000>: 0 V to 5 V voltage range
+ * <0 10000000>: 0 V to 10 V voltage range
+ * <(-5000000) 5000000>: ±5 V voltage range
+ * <(-10000000) 10000000>: ±10 V voltage range
+ - adi,range-microamp: Current output range
+ The array of current output ranges must contain two fields:
+ * <0 20000>: 0 mA to 20 mA current range
+ * <0 24000>: 0 mA to 24 mA current range
+ * <4 24000>: 4 mA to 20 mA current range
+ * <(-20000) 20000>: ±20 mA current range
+ * <(-24000) 24000>: ±24 mA current range
+ * <(-1000) 22000>: −1 mA to +22 mA current range
+
+Optional properties:
+
+ - adi,dc-dc-ilim-microamp: The dc-to-dc converter current limit
+ The following values are currently supported [uA]:
+ * 150000
+ * 200000
+ * 250000
+ * 300000
+ * 350000
+ * 400000
+
+ - adi,slew-time-us: The time it takes for the output to reach the
+ full scale [uS]
+ The supported range is between 133us up to 1023984375us
+
+AD5758 Example:
+
+ dac@0 {
+ compatible = "adi,ad5758";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+
+ adi,dc-dc-mode = <2>;
+ adi,range-microvolt = <0 10000000>;
+ adi,dc-dc-ilim-microamp = <200000>;
+ adi,slew-time-us = <125000>;
+ };
diff --git a/dts/Bindings/iio/gyroscope/invensense,mpu3050.txt b/dts/Bindings/iio/gyroscope/invensense,mpu3050.txt
index b0d3b59..233fe20 100644
--- a/dts/Bindings/iio/gyroscope/invensense,mpu3050.txt
+++ b/dts/Bindings/iio/gyroscope/invensense,mpu3050.txt
@@ -5,7 +5,6 @@ Required properties:
- reg : the I2C address of the sensor
Optional properties:
- - interrupt-parent : should be the phandle for the interrupt controller
- interrupts : interrupt mapping for the trigger interrupt from the
internal oscillator. The following IRQ modes are supported:
IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH and
diff --git a/dts/Bindings/iio/health/afe4403.txt b/dts/Bindings/iio/health/afe4403.txt
index 2fffd70..8e41205 100644
--- a/dts/Bindings/iio/health/afe4403.txt
+++ b/dts/Bindings/iio/health/afe4403.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible : Should be "ti,afe4403".
- reg : SPI chip select address of device.
- tx-supply : Regulator supply to transmitting LEDs.
- - interrupt-parent : Phandle to he parent interrupt controller.
- interrupts : The interrupt line the device ADC_RDY pin is
connected to. For details refer to,
../../interrupt-controller/interrupts.txt.
diff --git a/dts/Bindings/iio/health/afe4404.txt b/dts/Bindings/iio/health/afe4404.txt
index de69f20..0b52830 100644
--- a/dts/Bindings/iio/health/afe4404.txt
+++ b/dts/Bindings/iio/health/afe4404.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible : Should be "ti,afe4404".
- reg : I2C address of the device.
- tx-supply : Regulator supply to transmitting LEDs.
- - interrupt-parent : Phandle to he parent interrupt controller.
- interrupts : The interrupt line the device ADC_RDY pin is
connected to. For details refer to,
../interrupt-controller/interrupts.txt.
diff --git a/dts/Bindings/iio/health/max30100.txt b/dts/Bindings/iio/health/max30100.txt
index 8d81764..0054908 100644
--- a/dts/Bindings/iio/health/max30100.txt
+++ b/dts/Bindings/iio/health/max30100.txt
@@ -5,7 +5,6 @@ Maxim MAX30100 heart rate and pulse oximeter sensor
Required properties:
- compatible: must be "maxim,max30100"
- reg: the I2C address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic
diff --git a/dts/Bindings/iio/health/max30102.txt b/dts/Bindings/iio/health/max30102.txt
index ef2ca0a..7ef7ae4 100644
--- a/dts/Bindings/iio/health/max30102.txt
+++ b/dts/Bindings/iio/health/max30102.txt
@@ -7,7 +7,6 @@ Maxim MAX30105 optical particle-sensing module
Required properties:
- compatible: must be "maxim,max30102" or "maxim,max30105"
- reg: the I2C address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic
diff --git a/dts/Bindings/iio/humidity/hts221.txt b/dts/Bindings/iio/humidity/hts221.txt
index 10adeb0..84d0293 100644
--- a/dts/Bindings/iio/humidity/hts221.txt
+++ b/dts/Bindings/iio/humidity/hts221.txt
@@ -13,7 +13,6 @@ Optional properties:
when it is not active, whereas a pull-up one is needed when interrupt
line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
Refer to pinctrl/pinctrl-bindings.txt for the property description.
-- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
IRQ_TYPE_EDGE_FALLING.
diff --git a/dts/Bindings/iio/imu/bmi160.txt b/dts/Bindings/iio/imu/bmi160.txt
index ae0112c..0c1c105 100644
--- a/dts/Bindings/iio/imu/bmi160.txt
+++ b/dts/Bindings/iio/imu/bmi160.txt
@@ -9,7 +9,6 @@ Required properties:
- spi-max-frequency : set maximum clock frequency (only for SPI)
Optional properties:
- - interrupt-parent : should be the phandle of the interrupt controller
- interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW
- interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
input, set to "INT2" if INT2 pin should be used instead
diff --git a/dts/Bindings/iio/imu/inv_mpu6050.txt b/dts/Bindings/iio/imu/inv_mpu6050.txt
index 5f4777e..b2f27da 100644
--- a/dts/Bindings/iio/imu/inv_mpu6050.txt
+++ b/dts/Bindings/iio/imu/inv_mpu6050.txt
@@ -6,12 +6,12 @@ Required properties:
- compatible : should be one of
"invensense,mpu6050"
"invensense,mpu6500"
+ "invensense,mpu6515"
"invensense,mpu9150"
"invensense,mpu9250"
"invensense,mpu9255"
"invensense,icm20608"
- reg : the I2C address of the sensor
- - interrupt-parent : should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with flags
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
IRQ_TYPE_EDGE_FALLING.
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
index ef8a856..ea2d6e0 100644
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/dts/Bindings/iio/imu/st_lsm6dsx.txt
@@ -20,7 +20,6 @@ Optional properties:
IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
when it is not active, whereas a pull-up one is needed when interrupt
line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
-- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
IRQ_TYPE_EDGE_FALLING.
diff --git a/dts/Bindings/iio/light/apds9300.txt b/dts/Bindings/iio/light/apds9300.txt
index d6f66c7..aa199e0 100644
--- a/dts/Bindings/iio/light/apds9300.txt
+++ b/dts/Bindings/iio/light/apds9300.txt
@@ -9,7 +9,6 @@ Required properties:
Optional properties:
- - interrupt-parent : should be the phandle for the interrupt controller
- interrupts : interrupt mapping for GPIO IRQ
Example:
diff --git a/dts/Bindings/iio/light/apds9960.txt b/dts/Bindings/iio/light/apds9960.txt
index 174b709..3af325a 100644
--- a/dts/Bindings/iio/light/apds9960.txt
+++ b/dts/Bindings/iio/light/apds9960.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: must be "avago,apds9960"
- reg: the I2c address of the sensor
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts : the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/light/isl29018.txt b/dts/Bindings/iio/light/isl29018.txt
index 425ab45..b9bbde3 100644
--- a/dts/Bindings/iio/light/isl29018.txt
+++ b/dts/Bindings/iio/light/isl29018.txt
@@ -10,7 +10,6 @@ Required properties:
Optional properties:
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/light/isl29501.txt b/dts/Bindings/iio/light/isl29501.txt
new file mode 100644
index 0000000..4695799
--- /dev/null
+++ b/dts/Bindings/iio/light/isl29501.txt
@@ -0,0 +1,13 @@
+* ISL29501 Time-of-flight sensor.
+
+Required properties:
+
+ - compatible : should be "renesas,isl29501"
+ - reg : the I2C address of the sensor
+
+Example:
+
+isl29501@57 {
+ compatible = "renesas,isl29501";
+ reg = <0x57>;
+};
diff --git a/dts/Bindings/iio/light/opt3001.txt b/dts/Bindings/iio/light/opt3001.txt
index eac30d5..47b13eb 100644
--- a/dts/Bindings/iio/light/opt3001.txt
+++ b/dts/Bindings/iio/light/opt3001.txt
@@ -13,7 +13,6 @@ Required properties:
- reg: the I2C address of the sensor
Optional properties:
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for GPIO IRQ (configure for falling edge)
Example:
diff --git a/dts/Bindings/iio/light/tsl2583.txt b/dts/Bindings/iio/light/tsl2583.txt
index 8e2066c..059dffa 100644
--- a/dts/Bindings/iio/light/tsl2583.txt
+++ b/dts/Bindings/iio/light/tsl2583.txt
@@ -10,7 +10,6 @@ Required properties:
Optional properties:
- - interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
diff --git a/dts/Bindings/iio/light/uvis25.txt b/dts/Bindings/iio/light/uvis25.txt
index 3041207..043c139 100644
--- a/dts/Bindings/iio/light/uvis25.txt
+++ b/dts/Bindings/iio/light/uvis25.txt
@@ -5,7 +5,6 @@ Required properties:
- reg: i2c address of the sensor / spi cs line
Optional properties:
-- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
IRQ_TYPE_EDGE_FALLING.
diff --git a/dts/Bindings/iio/magnetometer/bmc150_magn.txt b/dts/Bindings/iio/magnetometer/bmc150_magn.txt
index 9f263b7..fd5fca9 100644
--- a/dts/Bindings/iio/magnetometer/bmc150_magn.txt
+++ b/dts/Bindings/iio/magnetometer/bmc150_magn.txt
@@ -9,7 +9,6 @@ Required properties:
Optional properties:
- - interrupt-parent : phandle to the parent interrupt controller
- interrupts : interrupt mapping for GPIO IRQ
Example:
diff --git a/dts/Bindings/iio/pressure/bmp085.txt b/dts/Bindings/iio/pressure/bmp085.txt
index c7198a0..61c72e6 100644
--- a/dts/Bindings/iio/pressure/bmp085.txt
+++ b/dts/Bindings/iio/pressure/bmp085.txt
@@ -8,11 +8,6 @@ Required properties:
"bosch,bme280"
Optional properties:
-- chip-id: configurable chip id for non-default chip revisions
-- temp-measurement-period: temperature measurement period (milliseconds)
-- default-oversampling: default oversampling value to be used at startup,
- value range is 0-3 with rising sensitivity.
-- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ
- reset-gpios: a GPIO line handling reset of the sensor: as the line is
active low, it should be marked GPIO_ACTIVE_LOW (see gpio/gpio.txt)
@@ -24,9 +19,6 @@ Example:
pressure@77 {
compatible = "bosch,bmp085";
reg = <0x77>;
- chip-id = <10>;
- temp-measurement-period = <100>;
- default-oversampling = <2>;
interrupt-parent = <&gpio0>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
diff --git a/dts/Bindings/iio/pressure/zpa2326.txt b/dts/Bindings/iio/pressure/zpa2326.txt
index fb85de6..a36ab3e 100644
--- a/dts/Bindings/iio/pressure/zpa2326.txt
+++ b/dts/Bindings/iio/pressure/zpa2326.txt
@@ -15,8 +15,6 @@ Optional properties:
power to the sensor
- vdd-supply: an optional regulator that needs to be on to provide VDD
power to the sensor
-- interrupt-parent: phandle to the parent interrupt controller as documented in
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
diff --git a/dts/Bindings/iio/proximity/as3935.txt b/dts/Bindings/iio/proximity/as3935.txt
index b6c1afa..8491155 100644
--- a/dts/Bindings/iio/proximity/as3935.txt
+++ b/dts/Bindings/iio/proximity/as3935.txt
@@ -6,7 +6,6 @@ Required properties:
- spi-max-frequency: specifies maximum SPI clock frequency
- spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
slave node bindings.
- - interrupt-parent : should be the phandle for the interrupt controller
- interrupts : the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic
diff --git a/dts/Bindings/iio/proximity/sx9500.txt b/dts/Bindings/iio/proximity/sx9500.txt
index b301dd2..c54455d 100644
--- a/dts/Bindings/iio/proximity/sx9500.txt
+++ b/dts/Bindings/iio/proximity/sx9500.txt
@@ -3,7 +3,6 @@ Semtech's SX9500 capacitive proximity button device driver
Required properties:
- compatible: must be "semtech,sx9500"
- reg: i2c address where to find the device
- - interrupt-parent : should be the phandle for the interrupt controller
- interrupts : the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic
diff --git a/dts/Bindings/iio/sensorhub.txt b/dts/Bindings/iio/sensorhub.txt
index 8d57571..b6ac045 100644
--- a/dts/Bindings/iio/sensorhub.txt
+++ b/dts/Bindings/iio/sensorhub.txt
@@ -6,7 +6,6 @@ of a virtual sensor device.
Required properties:
- compatible: "samsung,sensorhub-rinato" or "samsung,sensorhub-thermostat"
- spi-max-frequency: max SPI clock frequency
-- interrupt-parent: interrupt parent
- interrupts: communication interrupt
- ap-mcu-gpios: [out] ap to sensorhub line - used during communication
- mcu-ap-gpios: [in] sensorhub to ap - used during communication
diff --git a/dts/Bindings/iio/temperature/tmp007.txt b/dts/Bindings/iio/temperature/tmp007.txt
index b63aba9..da0af23 100644
--- a/dts/Bindings/iio/temperature/tmp007.txt
+++ b/dts/Bindings/iio/temperature/tmp007.txt
@@ -20,8 +20,6 @@ Required properties:
Optional properties:
- - interrupt-parent: should be the phandle for the interrupt controller
-
- interrupts: interrupt mapping for GPIO IRQ (level active low)
Example:
diff --git a/dts/Bindings/infiniband/hisilicon-hns-roce.txt b/dts/Bindings/infiniband/hisilicon-hns-roce.txt
index d3b273e..84f1a1b 100644
--- a/dts/Bindings/infiniband/hisilicon-hns-roce.txt
+++ b/dts/Bindings/infiniband/hisilicon-hns-roce.txt
@@ -19,7 +19,6 @@ representing a dsaf device.
- #size-cells: must be 2
Optional properties:
- dma-coherent: Present if DMA operations are coherent.
-- interrupt-parent: the interrupt parent of this device.
- interrupts: should contain 32 completion event irq,1 async event irq
and 1 event overflow irq.
- interrupt-names:should be one of 34 irqs for roce device
diff --git a/dts/Bindings/input/cypress,cyapa.txt b/dts/Bindings/input/cypress,cyapa.txt
index 8d91ba9..d3db659 100644
--- a/dts/Bindings/input/cypress,cyapa.txt
+++ b/dts/Bindings/input/cypress,cyapa.txt
@@ -3,8 +3,6 @@ Cypress I2C Touchpad
Required properties:
- compatible: must be "cypress,cyapa".
- reg: I2C address of the chip.
-- interrupt-parent: a phandle for the interrupt controller (see interrupt
- binding[0]).
- interrupts: interrupt to which the chip is connected (see interrupt
binding[0]).
diff --git a/dts/Bindings/input/cypress,tm2-touchkey.txt b/dts/Bindings/input/cypress,tm2-touchkey.txt
index 635f62c..0c252d9 100644
--- a/dts/Bindings/input/cypress,tm2-touchkey.txt
+++ b/dts/Bindings/input/cypress,tm2-touchkey.txt
@@ -3,8 +3,6 @@ Samsung tm2-touchkey
Required properties:
- compatible: must be "cypress,tm2-touchkey"
- reg: I2C address of the chip.
-- interrupt-parent: a phandle for the interrupt controller (see interrupt
- binding[0]).
- interrupts: interrupt to which the chip is connected (see interrupt
binding[0]).
- vcc-supply : internal regulator output. 1.8V
diff --git a/dts/Bindings/input/e3x0-button.txt b/dts/Bindings/input/e3x0-button.txt
index 751665e..907b195 100644
--- a/dts/Bindings/input/e3x0-button.txt
+++ b/dts/Bindings/input/e3x0-button.txt
@@ -7,8 +7,6 @@ This module provides a simple power button event via two interrupts.
Required properties:
- compatible: should be one of the following
- "ettus,e3x0-button": For devices such as the NI Ettus Research USRP E3x0
-- interrupt-parent:
- - a phandle to the interrupt controller that it is attached to.
- interrupts: should be one of the following
- <0 30 1>, <0 31 1>: For devices such as the NI Ettus Research USRP E3x0
- interrupt-names: should be one of the following
diff --git a/dts/Bindings/input/elan_i2c.txt b/dts/Bindings/input/elan_i2c.txt
index d80a835..7976074 100644
--- a/dts/Bindings/input/elan_i2c.txt
+++ b/dts/Bindings/input/elan_i2c.txt
@@ -3,8 +3,6 @@ Elantech I2C Touchpad
Required properties:
- compatible: must be "elan,ekth3000".
- reg: I2C address of the chip.
-- interrupt-parent: a phandle for the interrupt controller (see interrupt
- binding[0]).
- interrupts: interrupt to which the chip is connected (see interrupt
binding[0]).
diff --git a/dts/Bindings/input/elants_i2c.txt b/dts/Bindings/input/elants_i2c.txt
index 8a71038..5edac8b 100644
--- a/dts/Bindings/input/elants_i2c.txt
+++ b/dts/Bindings/input/elants_i2c.txt
@@ -3,8 +3,6 @@ Elantech I2C Touchscreen
Required properties:
- compatible: must be "elan,ekth3500".
- reg: I2C address of the chip.
-- interrupt-parent: a phandle for the interrupt controller (see interrupt
- binding[0]).
- interrupts: interrupt to which the chip is connected (see interrupt
binding[0]).
diff --git a/dts/Bindings/input/hid-over-i2c.txt b/dts/Bindings/input/hid-over-i2c.txt
index 4d3da9d..c76bafa 100644
--- a/dts/Bindings/input/hid-over-i2c.txt
+++ b/dts/Bindings/input/hid-over-i2c.txt
@@ -14,7 +14,6 @@ Required properties:
- compatible: must be "hid-over-i2c"
- reg: i2c slave address
- hid-descr-addr: HID descriptor address
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: interrupt line
Additional optional properties:
@@ -26,7 +25,8 @@ device-specific compatible properties, which should be used in addition to the
- compatible:
* "wacom,w9013" (Wacom W9013 digitizer). Supports:
- - vdd-supply
+ - vdd-supply (3.3V)
+ - vddl-supply (1.8V)
- post-power-on-delay-ms
- vdd-supply: phandle of the regulator that provides the supply voltage.
diff --git a/dts/Bindings/input/keys.txt b/dts/Bindings/input/keys.txt
new file mode 100644
index 0000000..f5a5ddd
--- /dev/null
+++ b/dts/Bindings/input/keys.txt
@@ -0,0 +1,8 @@
+General Keys Properties:
+
+Optional properties for Keys:
+- power-off-time-sec: Duration in seconds which the key should be kept
+ pressed for device to power off automatically. Device with key pressed
+ shutdown feature can specify this property.
+- linux,keycodes: Specifies the numeric keycode values to be used for
+ reporting key presses.
diff --git a/dts/Bindings/input/qcom,pm8941-pwrkey.txt b/dts/Bindings/input/qcom,pm8941-pwrkey.txt
index 07bf55f..34ab576 100644
--- a/dts/Bindings/input/qcom,pm8941-pwrkey.txt
+++ b/dts/Bindings/input/qcom,pm8941-pwrkey.txt
@@ -7,6 +7,7 @@ PROPERTIES
Value type: <string>
Definition: must be one of:
"qcom,pm8941-pwrkey"
+ "qcom,pm8941-resin"
- reg:
Usage: required
@@ -32,6 +33,14 @@ PROPERTIES
Definition: presence of this property indicates that the KPDPWR_N pin
should be configured for pull up.
+- linux,code:
+ Usage: optional
+ Value type: <u32>
+ Definition: The input key-code associated with the power key.
+ Use the linux event codes defined in
+ include/dt-bindings/input/linux-event-codes.h
+ When property is omitted KEY_POWER is assumed.
+
EXAMPLE
pwrkey@800 {
@@ -40,4 +49,5 @@ EXAMPLE
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
+ linux,code = <KEY_POWER>;
};
diff --git a/dts/Bindings/input/raydium_i2c_ts.txt b/dts/Bindings/input/raydium_i2c_ts.txt
index 5b6232d..99a4f2a 100644
--- a/dts/Bindings/input/raydium_i2c_ts.txt
+++ b/dts/Bindings/input/raydium_i2c_ts.txt
@@ -3,7 +3,6 @@ Raydium I2C touchscreen
Required properties:
- compatible: must be "raydium,rm32380"
- reg: The I2C address of the device
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: interrupt to which the chip is connected
See ../interrupt-controller/interrupts.txt
Optional properties:
diff --git a/dts/Bindings/input/rmi4/rmi_i2c.txt b/dts/Bindings/input/rmi4/rmi_i2c.txt
index ec908b9..dcb012f 100644
--- a/dts/Bindings/input/rmi4/rmi_i2c.txt
+++ b/dts/Bindings/input/rmi4/rmi_i2c.txt
@@ -16,7 +16,6 @@ Required Properties:
Optional Properties:
- interrupts: interrupt which the rmi device is connected to.
-- interrupt-parent: The interrupt controller.
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- syna,reset-delay-ms: The number of milliseconds to wait after resetting the
diff --git a/dts/Bindings/input/rmi4/rmi_spi.txt b/dts/Bindings/input/rmi4/rmi_spi.txt
index a4ca782..632f473 100644
--- a/dts/Bindings/input/rmi4/rmi_spi.txt
+++ b/dts/Bindings/input/rmi4/rmi_spi.txt
@@ -16,7 +16,6 @@ Required Properties:
Optional Properties:
- interrupts: interrupt which the rmi device is connected to.
-- interrupt-parent: The interrupt controller.
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- spi-rx-delay-us: microsecond delay after a read transfer.
diff --git a/dts/Bindings/input/ti,palmas-pwrbutton.txt b/dts/Bindings/input/ti,palmas-pwrbutton.txt
index a3dde8c..c829e18 100644
--- a/dts/Bindings/input/ti,palmas-pwrbutton.txt
+++ b/dts/Bindings/input/ti,palmas-pwrbutton.txt
@@ -9,7 +9,6 @@ This module provides a simple power button event via an Interrupt.
Required properties:
- compatible: should be one of the following
- "ti,palmas-pwrbutton": For Palmas compatible power on button
-- interrupt-parent: Parent interrupt device, must be handle of palmas node.
- interrupts: Interrupt number of power button submodule on device.
Optional Properties:
diff --git a/dts/Bindings/input/touchscreen/ad7879.txt b/dts/Bindings/input/touchscreen/ad7879.txt
index 3c8614c..cdd743a 100644
--- a/dts/Bindings/input/touchscreen/ad7879.txt
+++ b/dts/Bindings/input/touchscreen/ad7879.txt
@@ -5,7 +5,6 @@ Required properties:
for I2C slave, use "adi,ad7879-1"
- reg : SPI chipselect/I2C slave address
See spi-bus.txt for more SPI slave properties
-- interrupt-parent : the phandle for the interrupt controller
- interrupts : touch controller interrupt
- touchscreen-max-pressure : maximum reported pressure
- adi,resistance-plate-x : total resistance of X-plate (for pressure
diff --git a/dts/Bindings/input/touchscreen/ads7846.txt b/dts/Bindings/input/touchscreen/ads7846.txt
index 9fc47b0..04413da 100644
--- a/dts/Bindings/input/touchscreen/ads7846.txt
+++ b/dts/Bindings/input/touchscreen/ads7846.txt
@@ -18,7 +18,6 @@ Additional required properties:
"ti,ads7846"
"ti,ads7873"
- interrupt-parent
interrupts An interrupt node describing the IRQ line the chip's
!PENIRQ pin is connected to.
vcc-supply A regulator node for the supply voltage.
diff --git a/dts/Bindings/input/touchscreen/ar1021.txt b/dts/Bindings/input/touchscreen/ar1021.txt
index e459e85..82019bd 100644
--- a/dts/Bindings/input/touchscreen/ar1021.txt
+++ b/dts/Bindings/input/touchscreen/ar1021.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible : "microchip,ar1021-i2c"
- reg : I2C slave address
-- interrupt-parent : the phandle for the interrupt controller
- interrupts : touch controller interrupt
Example:
diff --git a/dts/Bindings/input/touchscreen/bu21029.txt b/dts/Bindings/input/touchscreen/bu21029.txt
new file mode 100644
index 0000000..8daa0e8
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/bu21029.txt
@@ -0,0 +1,35 @@
+* Rohm BU21029 Touch Screen Controller
+
+Required properties:
+ - compatible : must be "rohm,bu21029"
+ - reg : i2c device address of the chip (0x40 or 0x41)
+ - interrupt-parent : the phandle for the gpio controller
+ - interrupts : (gpio) interrupt to which the chip is connected
+ - rohm,x-plate-ohms : x-plate resistance in Ohm
+
+Optional properties:
+ - reset-gpios : gpio pin to reset the chip (active low)
+ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
+ - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
+ - touchscreen-max-pressure: maximum pressure value
+ - vdd-supply : power supply for the controller
+
+Example:
+
+ &i2c1 {
+ /* ... */
+
+ bu21029: bu21029@40 {
+ compatible = "rohm,bu21029";
+ reg = <0x40>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+ rohm,x-plate-ohms = <600>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-max-pressure = <4095>;
+ };
+
+ /* ... */
+ };
diff --git a/dts/Bindings/input/touchscreen/chipone_icn8318.txt b/dts/Bindings/input/touchscreen/chipone_icn8318.txt
index d11f8d6..38b0603 100644
--- a/dts/Bindings/input/touchscreen/chipone_icn8318.txt
+++ b/dts/Bindings/input/touchscreen/chipone_icn8318.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible : "chipone,icn8318"
- reg : I2C slave address of the chip (0x40)
- - interrupt-parent : a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- interrupts : interrupt specification for the icn8318 interrupt
- wake-gpios : GPIO specification for the WAKE input
- touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
diff --git a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
index df531b5..2e1490a 100644
--- a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
+++ b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
@@ -7,7 +7,6 @@ Required Properties:
- xm-gpios: FET gate driver for input of X-
- yp-gpios: FET gate driver for input of Y+
- ym-gpios: FET gate driver for input of Y-
-- interrupt-parent: phandle for the interrupt controller
- interrupts: pen irq interrupt for touch detection
- pinctrl-names: "idle", "default", "gpios"
- pinctrl-0: pinctrl node for pen/touch detection state pinmux
diff --git a/dts/Bindings/input/touchscreen/cyttsp.txt b/dts/Bindings/input/touchscreen/cyttsp.txt
index b75d4cf..6ee274a 100644
--- a/dts/Bindings/input/touchscreen/cyttsp.txt
+++ b/dts/Bindings/input/touchscreen/cyttsp.txt
@@ -4,8 +4,6 @@ Required properties:
- compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi"
- reg : Device I2C address or SPI chip select number
- spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi)
- - interrupt-parent : the phandle for the gpio controller
- (see interrupt binding[0]).
- interrupts : (gpio) interrupt to which the chip is connected
(see interrupt binding[0]).
- bootloader-key : the 8-byte bootloader key that is required to switch
diff --git a/dts/Bindings/input/touchscreen/edt-ft5x06.txt b/dts/Bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c..da2dc5d 100644
--- a/dts/Bindings/input/touchscreen/edt-ft5x06.txt
+++ b/dts/Bindings/input/touchscreen/edt-ft5x06.txt
@@ -22,8 +22,6 @@ Required properties:
or: "focaltech,ft6236"
- reg: I2C slave address of the chip (0x38)
- - interrupt-parent: a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- interrupts: interrupt specification for the touchdetect
interrupt
diff --git a/dts/Bindings/input/touchscreen/eeti.txt b/dts/Bindings/input/touchscreen/eeti.txt
new file mode 100644
index 0000000..32b3712
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/eeti.txt
@@ -0,0 +1,30 @@
+Bindings for EETI touchscreen controller
+
+Required properties:
+- compatible: should be "eeti,exc3000-i2c"
+- reg: I2C address of the chip. Should be set to <0xa>
+- interrupts: interrupt to which the chip is connected
+
+Optional properties:
+- attn-gpios: A handle to a GPIO to check whether interrupt is still
+ latched. This is necessary for platforms that lack
+ support for level-triggered IRQs.
+
+The following optional properties described in touchscreen.txt are
+also supported:
+
+- touchscreen-inverted-x
+- touchscreen-inverted-y
+- touchscreen-swapped-x-y
+
+Example:
+
+i2c-master {
+ touchscreen@a {
+ compatible = "eeti,exc3000-i2c";
+ reg = <0xa>;
+ interrupt-parent = <&gpio>;
+ interrupts = <123 IRQ_TYPE_EDGE_RISING>;
+ attn-gpios = <&gpio 123 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/dts/Bindings/input/touchscreen/egalax-ts.txt b/dts/Bindings/input/touchscreen/egalax-ts.txt
index 298e344..92fb262 100644
--- a/dts/Bindings/input/touchscreen/egalax-ts.txt
+++ b/dts/Bindings/input/touchscreen/egalax-ts.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible: must be "eeti,egalax_ts"
- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: touch controller interrupt
- wakeup-gpios: the gpio pin to be used for waking up the controller
and also used as irq pin
diff --git a/dts/Bindings/input/touchscreen/ektf2127.txt b/dts/Bindings/input/touchscreen/ektf2127.txt
index 5a19f4c..94c4fc6 100644
--- a/dts/Bindings/input/touchscreen/ektf2127.txt
+++ b/dts/Bindings/input/touchscreen/ektf2127.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible : "elan,ektf2127"
- reg : I2C slave address of the chip (0x40)
- - interrupt-parent : a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- interrupts : interrupt specification for the ektf2127 interrupt
- power-gpios : GPIO specification for the pin connected to the
ektf2127's wake input. This needs to be driven high
diff --git a/dts/Bindings/input/touchscreen/exc3000.txt b/dts/Bindings/input/touchscreen/exc3000.txt
index 1dcff4a..68291b9 100644
--- a/dts/Bindings/input/touchscreen/exc3000.txt
+++ b/dts/Bindings/input/touchscreen/exc3000.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible: must be "eeti,exc3000"
- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: touch controller interrupt
- touchscreen-size-x: See touchscreen.txt
- touchscreen-size-y: See touchscreen.txt
diff --git a/dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt b/dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt
index abfcab3..99d6f9d 100644
--- a/dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt
+++ b/dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt
@@ -8,7 +8,6 @@ Required properties:
- reg: Memory range of the device.
- interrupts: Should be the interrupt number associated with this module within
the tscadc unit (<0>).
- - interrupt-parent: Should be a phandle to the tscadc unit.
- fsl,wires: Should be '<4>' or '<5>'
Optional properties:
diff --git a/dts/Bindings/input/touchscreen/goodix.txt b/dts/Bindings/input/touchscreen/goodix.txt
index 0c369d8..f7e95c5 100644
--- a/dts/Bindings/input/touchscreen/goodix.txt
+++ b/dts/Bindings/input/touchscreen/goodix.txt
@@ -11,7 +11,6 @@ Required properties:
or "goodix,gt928"
or "goodix,gt967"
- reg : I2C address of the chip. Should be 0x5d or 0x14
- - interrupt-parent : Interrupt controller to which the chip is connected
- interrupts : Interrupt to which the chip is connected
Optional properties:
diff --git a/dts/Bindings/input/touchscreen/hideep.txt b/dts/Bindings/input/touchscreen/hideep.txt
index 1063c30..a47c361 100644
--- a/dts/Bindings/input/touchscreen/hideep.txt
+++ b/dts/Bindings/input/touchscreen/hideep.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible : must be "hideep,hideep-ts"
- reg : I2C slave address, (e.g. 0x6C).
-- interrupt-parent : Interrupt controller to which the chip is connected.
- interrupts : Interrupt to which the chip is connected.
Optional properties:
diff --git a/dts/Bindings/input/touchscreen/max11801-ts.txt b/dts/Bindings/input/touchscreen/max11801-ts.txt
index 40ac0fe..05e982c 100644
--- a/dts/Bindings/input/touchscreen/max11801-ts.txt
+++ b/dts/Bindings/input/touchscreen/max11801-ts.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible: must be "maxim,max11801"
- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: touch controller interrupt
Example:
diff --git a/dts/Bindings/input/touchscreen/melfas_mip4.txt b/dts/Bindings/input/touchscreen/melfas_mip4.txt
index 7b8944c..b2ab549 100644
--- a/dts/Bindings/input/touchscreen/melfas_mip4.txt
+++ b/dts/Bindings/input/touchscreen/melfas_mip4.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible: must be "melfas,mip4_ts"
- reg: I2C slave address of the chip (0x48 or 0x34)
-- interrupt-parent: interrupt controller to which the chip is connected
- interrupts: interrupt to which the chip is connected
Optional properties:
diff --git a/dts/Bindings/input/touchscreen/resistive-adc-touch.txt b/dts/Bindings/input/touchscreen/resistive-adc-touch.txt
new file mode 100644
index 0000000..51456c0
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/resistive-adc-touch.txt
@@ -0,0 +1,30 @@
+Generic resistive touchscreen ADC
+
+Required properties:
+
+ - compatible: must be "resistive-adc-touch"
+The device must be connected to an ADC device that provides channels for
+position measurement and optional pressure.
+Refer to ../iio/iio-bindings.txt for details
+ - iio-channels: must have at least two channels connected to an ADC device.
+These should correspond to the channels exposed by the ADC device and should
+have the right index as the ADC device registers them. These channels
+represent the relative position on the "x" and "y" axes.
+ - iio-channel-names: must have all the channels' names. Mandatory channels
+are "x" and "y".
+
+Optional properties:
+ - iio-channels: The third channel named "pressure" is optional and can be
+used if the ADC device also measures pressure besides position.
+If this channel is missing, pressure will be ignored and the touchscreen
+will only report position.
+ - iio-channel-names: optional channel named "pressure".
+
+Example:
+
+ resistive_touch: resistive_touch {
+ compatible = "resistive-adc-touch";
+ touchscreen-min-pressure = <50000>;
+ io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
+ io-channel-names = "x", "y", "pressure";
+ };
diff --git a/dts/Bindings/input/touchscreen/samsung,s6sy761.txt b/dts/Bindings/input/touchscreen/samsung,s6sy761.txt
index d9b7c2f..6805d10 100644
--- a/dts/Bindings/input/touchscreen/samsung,s6sy761.txt
+++ b/dts/Bindings/input/touchscreen/samsung,s6sy761.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible : must be "samsung,s6sy761"
- reg : I2C slave address, (e.g. 0x48)
-- interrupt-parent : the phandle to the interrupt controller which provides
- the interrupt
- interrupts : interrupt specification
- avdd-supply : analogic power supply
- vdd-supply : power supply
diff --git a/dts/Bindings/input/touchscreen/silead_gsl1680.txt b/dts/Bindings/input/touchscreen/silead_gsl1680.txt
index 84752de..d67e558 100644
--- a/dts/Bindings/input/touchscreen/silead_gsl1680.txt
+++ b/dts/Bindings/input/touchscreen/silead_gsl1680.txt
@@ -8,8 +8,6 @@ Required properties:
"silead,gsl3675"
"silead,gsl3692"
- reg : I2C slave address of the chip (0x40)
-- interrupt-parent : a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- interrupts : interrupt specification for the gsl1680 interrupt
- power-gpios : Specification for the pin connected to the gsl1680's
shutdown input. This needs to be driven high to take the
diff --git a/dts/Bindings/input/touchscreen/sis_i2c.txt b/dts/Bindings/input/touchscreen/sis_i2c.txt
index d87ad14..8f5322e 100644
--- a/dts/Bindings/input/touchscreen/sis_i2c.txt
+++ b/dts/Bindings/input/touchscreen/sis_i2c.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: must be "sis,9200-ts"
- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
- (see interrupt binding [0])
- interrupts: touch controller interrupt (see interrupt
binding [0])
diff --git a/dts/Bindings/input/touchscreen/st,stmfts.txt b/dts/Bindings/input/touchscreen/st,stmfts.txt
index 9683595..0a5d0cb 100644
--- a/dts/Bindings/input/touchscreen/st,stmfts.txt
+++ b/dts/Bindings/input/touchscreen/st,stmfts.txt
@@ -10,8 +10,6 @@ coordinates.
Required properties:
- compatible : must be "st,stmfts"
- reg : I2C slave address, (e.g. 0x49)
-- interrupt-parent : the phandle to the interrupt controller which provides
- the interrupt
- interrupts : interrupt specification
- avdd-supply : analogic power supply
- vdd-supply : power supply
diff --git a/dts/Bindings/input/touchscreen/sx8654.txt b/dts/Bindings/input/touchscreen/sx8654.txt
index 5aaa6b3..4886c4a 100644
--- a/dts/Bindings/input/touchscreen/sx8654.txt
+++ b/dts/Bindings/input/touchscreen/sx8654.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible: must be "semtech,sx8654"
- reg: i2c slave address
-- interrupt-parent: the phandle for the interrupt controller
- interrupts: touch controller interrupt
Example:
diff --git a/dts/Bindings/input/touchscreen/touchscreen.txt b/dts/Bindings/input/touchscreen/touchscreen.txt
index 537643e..d092d5d 100644
--- a/dts/Bindings/input/touchscreen/touchscreen.txt
+++ b/dts/Bindings/input/touchscreen/touchscreen.txt
@@ -7,6 +7,9 @@ Optional properties for Touchscreens:
(in pixels)
- touchscreen-max-pressure : maximum reported pressure (arbitrary range
dependent on the controller)
+ - touchscreen-min-pressure : minimum pressure on the touchscreen to be
+ achieved in order for the touchscreen
+ driver to report a touch event.
- touchscreen-fuzz-x : horizontal noise value of the absolute input
device (in pixels)
- touchscreen-fuzz-y : vertical noise value of the absolute input
diff --git a/dts/Bindings/input/touchscreen/tsc2007.txt b/dts/Bindings/input/touchscreen/tsc2007.txt
index ec365e1..ed00f61 100644
--- a/dts/Bindings/input/touchscreen/tsc2007.txt
+++ b/dts/Bindings/input/touchscreen/tsc2007.txt
@@ -9,8 +9,6 @@ Optional properties:
- gpios: the interrupt gpio the chip is connected to (trough the penirq pin).
The penirq pin goes to low when the panel is touched.
(see GPIO binding[1] for more details).
-- interrupt-parent: the phandle for the gpio controller
- (see interrupt binding[0]).
- interrupts: (gpio) interrupt to which the chip is connected
(see interrupt binding[0]).
- ti,max-rt: maximum pressure.
diff --git a/dts/Bindings/input/touchscreen/zet6223.txt b/dts/Bindings/input/touchscreen/zet6223.txt
index fe6a1fe..27d55a5 100644
--- a/dts/Bindings/input/touchscreen/zet6223.txt
+++ b/dts/Bindings/input/touchscreen/zet6223.txt
@@ -3,8 +3,6 @@ Zeitec ZET6223 I2C touchscreen controller
Required properties:
- compatible : "zeitec,zet6223"
- reg : I2C slave address of the chip (0x76)
-- interrupt-parent : a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- interrupts : interrupt specification for the zet6223 interrupt
Optional properties:
diff --git a/dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt b/dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt
index 9d52d5a..5a4dd26 100644
--- a/dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt
+++ b/dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt
@@ -13,7 +13,6 @@ Required properties
- interrupt-congroller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
source connected to this controller. The value shall be 2.
-- interrupt-parent: Specifies the parent interrupt controller.
- interrupts: Specifies the list of interrupt lines which are handled by
the interrupt controller in the parent controller's notation. Interrupts
are mapped one-to-one to parent interrupts.
diff --git a/dts/Bindings/interrupt-controller/al,alpine-msix.txt b/dts/Bindings/interrupt-controller/al,alpine-msix.txt
index f6f1c14..5669764 100644
--- a/dts/Bindings/interrupt-controller/al,alpine-msix.txt
+++ b/dts/Bindings/interrupt-controller/al,alpine-msix.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: should be "al,alpine-msix"
- reg: physical base address and size of the registers
-- interrupt-parent: specifies the parent interrupt controller.
- interrupt-controller: identifies the node as an interrupt controller
- msi-controller: identifies the node as an PCI Message Signaled Interrupt
controller
diff --git a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 4903fb7..24beadf 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -13,7 +13,6 @@ Required properties:
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2. The first cell is the IRQ number, the
second cell the trigger type as defined in interrupt.txt in this directory.
-- interrupt-parent: Specifies the parent interrupt controller.
- interrupts: Specifies the interrupt line (NMI) which is handled by
the interrupt controller in the parent controller's notation. This value
shall be the NMI.
diff --git a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 89674ad..1502a51 100644
--- a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -15,9 +15,6 @@ Required properties:
"amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
"amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
-- interrupt-parent : a phandle to the GIC the interrupts are routed to.
- Usually this is provided at the root level of the device tree as it is
- common to most of the SoC.
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/dts/Bindings/interrupt-controller/atmel,aic.txt b/dts/Bindings/interrupt-controller/atmel,aic.txt
index 0e9f09a..f4c5d34 100644
--- a/dts/Bindings/interrupt-controller/atmel,aic.txt
+++ b/dts/Bindings/interrupt-controller/atmel,aic.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible: Should be "atmel,<chip>-aic"
<chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"
- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: For single AIC system, it is an empty property.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
The second cell is used to specify flags:
@@ -27,7 +26,6 @@ Examples:
aic: interrupt-controller@fffff000 {
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
- interrupt-parent;
#interrupt-cells = <3>;
reg = <0xfffff000 0x200>;
};
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
index 6428a6b..0f1af5a 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -26,8 +26,6 @@ Required properties:
are 0..7 for bank 0, and 0..31 for bank 1.
Additional required properties for brcm,bcm2836-armctrl-ic:
-- interrupt-parent : Specifies the parent interrupt controller when this
- controller is the second level.
- interrupts : Specifies the interrupt on the parent for this interrupt
controller to handle.
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
index 8f48aad..37aea40 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
@@ -18,8 +18,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this one is cascaded from
- interrupts: specifies the interrupt line in the interrupt-parent controller
node, valid values depend on the type of parent interrupt controller
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt
index 4040905..2bc19b1 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt
@@ -29,8 +29,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
-- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
- this one is cascaded from
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
index cc217b2..2117d4a 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
@@ -28,8 +28,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
-- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
- this one is cascaded from
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
index 44a9bb1..addd86b 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@@ -56,8 +56,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this one is cascaded from
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node, valid values depend on the type of parent interrupt controller
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
diff --git a/dts/Bindings/interrupt-controller/brcm,l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
index 36df06c..d514ec0 100644
--- a/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
@@ -8,8 +8,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. Should be 1.
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this controller is cacaded from
- interrupts: specifies the interrupt line in the interrupt-parent irq space
to be used for cascading
diff --git a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index a4ff93d..454ce04 100644
--- a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -13,9 +13,6 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
-Optional properties:
-- interrupt-parent: the phandle to the parent interrupt controller.
-
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. If interrupt-parent is not provided, the default parent interrupt
diff --git a/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
index 3b2f4c4..a6813a0 100644
--- a/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
+++ b/dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt
@@ -68,8 +68,6 @@ Examples:
Devices connect to mbigen required properties:
----------------------------------------------------
--interrupt-parent: Specifies the mbigen device node which device connected.
-
-interrupts:Specifies the interrupt source.
For the specific information of each cell in this property,please refer to
the "interrupt-cells" description mentioned above.
diff --git a/dts/Bindings/interrupt-controller/ingenic,intc.txt b/dts/Bindings/interrupt-controller/ingenic,intc.txt
index 5f89fb6..d4373d0 100644
--- a/dts/Bindings/interrupt-controller/ingenic,intc.txt
+++ b/dts/Bindings/interrupt-controller/ingenic,intc.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible : should be "ingenic,<socname>-intc". Valid strings are:
ingenic,jz4740-intc
+ ingenic,jz4725b-intc
ingenic,jz4770-intc
ingenic,jz4775-intc
ingenic,jz4780-intc
@@ -11,7 +12,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
-- interrupt-parent : phandle of the CPU interrupt controller.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example:
diff --git a/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
index 3f6442c..930fb46 100644
--- a/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
+++ b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
@@ -26,8 +26,6 @@ Required properties:
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
for details about the GIC Device Tree binding.
-- interrupt-parent : Reference to the parent interrupt controller.
-
Example:
odmi: odmi@300000 {
diff --git a/dts/Bindings/interrupt-controller/mediatek,cirq.txt b/dts/Bindings/interrupt-controller/mediatek,cirq.txt
index a7efdbc..5865f4f 100644
--- a/dts/Bindings/interrupt-controller/mediatek,cirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,cirq.txt
@@ -16,8 +16,6 @@ Required properties:
and "mediatek,cirq" as a fallback.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
-- interrupt-parent: phandle of irq parent for cirq. The parent must
- use the same interrupt-cells format as GIC.
- reg: Physical base address of the cirq registers and length of memory
mapped region.
- mediatek,ext-irq-range: Identifies external irq number range in different
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index 07bf0b9..33a98eb 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -11,6 +11,7 @@ Required properties:
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
+ "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
@@ -21,8 +22,6 @@ Required properties:
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
-- interrupt-parent: phandle of irq parent for sysirq. The parent must
- use the same interrupt-cells format as GIC.
- reg: Physical base address of the intpol registers and length of memory
mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
need 1.
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index b47a8a0..f5baecc 100644
--- a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -7,7 +7,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
-- interrupt-parent : phandle of the CPU interrupt controller.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example:
diff --git a/dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
index f246ccb..2ff3566 100644
--- a/dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
+++ b/dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
@@ -19,8 +19,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
-- interrupt-parent : a phandle to the GIC these interrupts are routed
- to.
Notes:
diff --git a/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt b/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt
index 38211f3..0bfb3ba 100644
--- a/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt
+++ b/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt
@@ -14,8 +14,6 @@ Required properties:
Reset value is IRQ_TYPE_LEVEL_LOW.
Optional properties:
-- interrupt-parent: empty for MIC interrupt controller, link to parent
- MIC interrupt controller for SIC1 and SIC2
- interrupts: empty for MIC interrupt controller, cascaded MIC
hardware interrupts for SIC1 and SIC2
diff --git a/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt
index 475ae9b..ad70006 100644
--- a/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt
+++ b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -7,7 +7,6 @@ Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
- reg: Base address and size of the controllers memory area
-- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.txt b/dts/Bindings/interrupt-controller/qcom,pdc.txt
index 0b2c97d..8e0797c 100644
--- a/dts/Bindings/interrupt-controller/qcom,pdc.txt
+++ b/dts/Bindings/interrupt-controller/qcom,pdc.txt
@@ -35,12 +35,6 @@ Properties:
interrupt.
The second element is the trigger type.
-- interrupt-parent:
- Usage: required
- Value type: <phandle>
- Definition: Specifies the interrupt parent necessary for hierarchical
- domain to operate.
-
- interrupt-controller:
Usage: required
Value type: <bool>
diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.txt b/dts/Bindings/interrupt-controller/renesas,irqc.txt
index 20f121d..a046ed3 100644
--- a/dts/Bindings/interrupt-controller/renesas,irqc.txt
+++ b/dts/Bindings/interrupt-controller/renesas,irqc.txt
@@ -7,15 +7,18 @@ Required properties:
- "renesas,irqc-r8a73a4" (R-Mobile APE6)
- "renesas,irqc-r8a7743" (RZ/G1M)
- "renesas,irqc-r8a7745" (RZ/G1E)
+ - "renesas,irqc-r8a77470" (RZ/G1C)
- "renesas,irqc-r8a7790" (R-Car H2)
- "renesas,irqc-r8a7791" (R-Car M2-W)
- "renesas,irqc-r8a7792" (R-Car V2H)
- "renesas,irqc-r8a7793" (R-Car M2-N)
- "renesas,irqc-r8a7794" (R-Car E2)
+ - "renesas,intc-ex-r8a774a1" (RZ/G2M)
- "renesas,intc-ex-r8a7795" (R-Car H3)
- "renesas,intc-ex-r8a7796" (R-Car M3-W)
- "renesas,intc-ex-r8a77965" (R-Car M3-N)
- "renesas,intc-ex-r8a77970" (R-Car V3M)
+ - "renesas,intc-ex-r8a77980" (R-Car V3H)
- "renesas,intc-ex-r8a77995" (R-Car D3)
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
diff --git a/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt b/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt
new file mode 100644
index 0000000..b0a8af5
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt
@@ -0,0 +1,44 @@
+RISC-V Hart-Level Interrupt Controller (HLIC)
+---------------------------------------------
+
+RISC-V cores include Control Status Registers (CSRs) which are local to each
+CPU core (HART in RISC-V terminology) and can be read or written by software.
+Some of these CSRs are used to control local interrupts connected to the core.
+Every interrupt is ultimately routed through a hart's HLIC before it
+interrupts that hart.
+
+The RISC-V supervisor ISA manual specifies three interrupt sources that are
+attached to every HLIC: software interrupts, the timer interrupt, and external
+interrupts. Software interrupts are used to send IPIs between cores. The
+timer interrupt comes from an architecturally mandated real-time timer that is
+controller via Supervisor Binary Interface (SBI) calls and CSR reads. External
+interrupts connect all other device interrupts to the HLIC, which are routed
+via the platform-level interrupt controller (PLIC).
+
+All RISC-V systems that conform to the supervisor ISA specification are
+required to have a HLIC with these three interrupt sources present. Since the
+interrupt map is defined by the ISA it's not listed in the HLIC's device tree
+entry, though external interrupt controllers (like the PLIC, for example) will
+need to define how their interrupts map to the relevant HLICs. This means
+a PLIC interrupt property will typically list the HLICs for all present HARTs
+in the system.
+
+Required properties:
+- compatible : "riscv,cpu-intc"
+- #interrupt-cells : should be <1>
+- interrupt-controller : Identifies the node as an interrupt controller
+
+Furthermore, this interrupt-controller MUST be embedded inside the cpu
+definition of the hart whose CSRs control these local interrupts.
+
+An example device tree entry for a HLIC is show below.
+
+ cpu1: cpu@1 {
+ compatible = "riscv";
+ ...
+ cpu1-intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc";
+ interrupt-controller;
+ };
+ };
diff --git a/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt b/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt
index 9e5f734..19af687 100644
--- a/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt
+++ b/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt
@@ -32,8 +32,6 @@ Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
-- interrupt-parent: pHandle of the parent interrupt controller, if not
- inherited from the parent node.
Example:
diff --git a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.txt b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.txt
new file mode 100644
index 0000000..6adf7a6
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.txt
@@ -0,0 +1,58 @@
+SiFive Platform-Level Interrupt Controller (PLIC)
+-------------------------------------------------
+
+SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
+(PLIC) high-level specification in the RISC-V Privileged Architecture
+specification. The PLIC connects all external interrupts in the system to all
+hart contexts in the system, via the external interrupt source in each hart.
+
+A hart context is a privilege mode in a hardware execution thread. For example,
+in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
+privilege modes per hart; machine mode and supervisor mode.
+
+Each interrupt can be enabled on per-context basis. Any context can claim
+a pending enabled interrupt and then release it once it has been handled.
+
+Each interrupt has a configurable priority. Higher priority interrupts are
+serviced first. Each context can specify a priority threshold. Interrupts
+with priority below this threshold will not cause the PLIC to raise its
+interrupt line leading to the context.
+
+While the PLIC supports both edge-triggered and level-triggered interrupts,
+interrupt handlers are oblivious to this distinction and therefore it is not
+specified in the PLIC device-tree binding.
+
+While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
+"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
+contains a specific memory layout, which is documented in chapter 8 of the
+SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
+
+Required properties:
+- compatible : "sifive,plic-1.0.0" and a string identifying the actual
+ detailed implementation in case that specific bugs need to be worked around.
+- #address-cells : should be <0> or more.
+- #interrupt-cells : should be <1> or more.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- reg : Should contain 1 register range (address and length).
+- interrupts-extended : Specifies which contexts are connected to the PLIC,
+ with "-1" specifying that a context is not present. Each node pointed
+ to should be a riscv,cpu-intc node, which has a riscv node as parent.
+- riscv,ndev: Specifies how many external interrupts are supported by
+ this controller.
+
+Example:
+
+ plic: interrupt-controller@c000000 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0-intc 11
+ &cpu1-intc 11 &cpu1-intc 9
+ &cpu2-intc 11 &cpu2-intc 9
+ &cpu3-intc 11 &cpu3-intc 9
+ &cpu4-intc 11 &cpu4-intc 9>;
+ reg = <0xc000000 0x4000000>;
+ riscv,ndev = <10>;
+ };
diff --git a/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt b/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt
index 1f441fa..355c18a 100644
--- a/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt
+++ b/dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible: should be "sigma,smp8642-intc"
- reg: physical address of MMIO region
- ranges: address space mapping of child nodes
-- interrupt-parent: phandle of parent interrupt controller
- interrupt-controller: boolean
- #address-cells: should be <1>
- #size-cells: should be <1>
diff --git a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
index 8b46a34..09fc02b 100644
--- a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -7,7 +7,6 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
-- interrupt-parent: <reference to parent core intc>
- #interrupt-cells: Must be <1>.
Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
diff --git a/dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt b/dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt
index 4929117..086ff08 100644
--- a/dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt
+++ b/dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -11,7 +11,6 @@ Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
- interrupts: interrupt reference to primary interrupt controller
-- interrupt-parent: (optional) reference specific primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
diff --git a/dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt b/dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt
index 8b2faef..dac0846 100644
--- a/dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt
+++ b/dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt
@@ -12,7 +12,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
-- interrupt-parent : phandle of the GIC these interrupts are routed to.
- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
ones the EXIU forwards its interrups to.
diff --git a/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt b/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt
index 2ab0ea3..a407c49 100644
--- a/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt
+++ b/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt
@@ -31,10 +31,6 @@ Required properties:
parent) is equal to number of groups. The format of the interrupt
specifier depends in the interrupt parent controller.
- Optional properties:
- - interrupt-parent: pHandle of the parent interrupt controller, if not
- inherited from the parent node.
-
Example:
The following is an example from the SPEAr320 SoC dtsi file.
diff --git a/dts/Bindings/interrupt-controller/technologic,ts4800.txt b/dts/Bindings/interrupt-controller/technologic,ts4800.txt
index 7f15f1b..341ae59 100644
--- a/dts/Bindings/interrupt-controller/technologic,ts4800.txt
+++ b/dts/Bindings/interrupt-controller/technologic,ts4800.txt
@@ -11,6 +11,4 @@ Required properties:
region
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
-- interrupt-parent: phandle to the parent interrupt controller this one is
- cascaded from
- interrupts: specifies the interrupt line in the interrupt-parent controller
diff --git a/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
index 42bb796..ee3f9c3 100644
--- a/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
+++ b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
@@ -46,7 +46,6 @@ C6X Interrupt Chips
- interrupt-controller
- #interrupt-cells: <1>
- reg: base address and size of register area
- - interrupt-parent: must be core interrupt controller
- interrupts: This should have four cells; one for each interrupt combiner.
The cells contain the core priority interrupt to which the
corresponding combiner output is wired.
diff --git a/dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu b/dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu
index 18d4f40..422d690 100644
--- a/dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu
+++ b/dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -12,8 +12,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
-- interrupt-parent : a phandle to the GIC these interrupts are routed
- to.
Notes:
diff --git a/dts/Bindings/iommu/mediatek,iommu.txt b/dts/Bindings/iommu/mediatek,iommu.txt
index 53c20ca..df5db73 100644
--- a/dts/Bindings/iommu/mediatek,iommu.txt
+++ b/dts/Bindings/iommu/mediatek,iommu.txt
@@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
+ "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
@@ -50,8 +51,9 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
- dt-binding/memory/mt2701-larb-port.h for mt2701 and
- dt-binding/memory/mt8173-larb-port.h for mt8173
+ dt-binding/memory/mt2701-larb-port.h for mt2701,
+ dt-binding/memory/mt2712-larb-port.h for mt2712, and
+ dt-binding/memory/mt8173-larb-port.h for mt8173.
Example:
iommu: iommu@10205000 {
diff --git a/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt b/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
index ffadb7c..c6e2d85 100644
--- a/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
+++ b/dts/Bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -19,7 +19,10 @@ Required Properties:
- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
+ - "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
+ - "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
+ - "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
IPMMU.
diff --git a/dts/Bindings/iommu/samsung,sysmmu.txt b/dts/Bindings/iommu/samsung,sysmmu.txt
index b1682c8..525ec82 100644
--- a/dts/Bindings/iommu/samsung,sysmmu.txt
+++ b/dts/Bindings/iommu/samsung,sysmmu.txt
@@ -31,7 +31,6 @@ Required properties:
- compatible: Should be "samsung,exynos-sysmmu"
- reg: A tuple of base address and size of System MMU registers.
- #iommu-cells: Should be <0>.
-- interrupt-parent: The phandle of the interrupt controller of System MMU
- interrupts: An interrupt specifier for interrupt signal of System MMU,
according to the format defined by a particular interrupt
controller.
diff --git a/dts/Bindings/leds/backlight/pwm-backlight.txt b/dts/Bindings/leds/backlight/pwm-backlight.txt
index 3108109..64fa2fb 100644
--- a/dts/Bindings/leds/backlight/pwm-backlight.txt
+++ b/dts/Bindings/leds/backlight/pwm-backlight.txt
@@ -3,13 +3,6 @@ pwm-backlight bindings
Required properties:
- compatible: "pwm-backlight"
- pwms: OF device-tree PWM specification (see PWM binding[0])
- - brightness-levels: Array of distinct brightness levels. Typically these
- are in the range from 0 to 255, but any range starting at 0 will do.
- The actual brightness level (PWM duty cycle) will be interpolated
- from these values. 0 means a 0% duty cycle (darkest/off), while the
- last value in the array represents a 100% duty cycle (brightest).
- - default-brightness-level: the default brightness level (index into the
- array defined by the "brightness-levels" property)
- power-supply: regulator for supply voltage
Optional properties:
@@ -21,6 +14,19 @@ Optional properties:
and enabling the backlight using GPIO.
- pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO
and setting PWM value to 0.
+ - brightness-levels: Array of distinct brightness levels. Typically these
+ are in the range from 0 to 255, but any range starting at
+ 0 will do. The actual brightness level (PWM duty cycle)
+ will be interpolated from these values. 0 means a 0% duty
+ cycle (darkest/off), while the last value in the array
+ represents a 100% duty cycle (brightest).
+ - default-brightness-level: The default brightness level (index into the
+ array defined by the "brightness-levels" property).
+ - num-interpolated-steps: Number of interpolated steps between each value
+ of brightness-levels table. This way a high
+ resolution pwm duty cycle can be used without
+ having to list out every possible value in the
+ brightness-level array.
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
[1]: Documentation/devicetree/bindings/gpio/gpio.txt
@@ -39,3 +45,17 @@ Example:
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
};
+
+Example using num-interpolation-steps:
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <0 2048 4096 8192 16384 65535>;
+ num-interpolated-steps = <2048>;
+ default-brightness-level = <4096>;
+
+ power-supply = <&vdd_bl_reg>;
+ enable-gpios = <&gpio 58 0>;
+ };
diff --git a/dts/Bindings/leds/common.txt b/dts/Bindings/leds/common.txt
index 1d4afe9..aa13998 100644
--- a/dts/Bindings/leds/common.txt
+++ b/dts/Bindings/leds/common.txt
@@ -31,7 +31,7 @@ Optional properties for child nodes:
"backlight" - LED will act as a back-light, controlled by the framebuffer
system
"default-on" - LED will turn on (but for leds-gpio see "default-state"
- property in Documentation/devicetree/bindings/gpio/led.txt)
+ property in Documentation/devicetree/bindings/leds/leds-gpio.txt)
"heartbeat" - LED "double" flashes at a load average based rate
"disk-activity" - LED indicates disk activity
"ide-disk" - LED indicates IDE disk activity (deprecated),
diff --git a/dts/Bindings/leds/leds-lm3692x.txt b/dts/Bindings/leds/leds-lm3692x.txt
index 6c9074f..08b3528 100644
--- a/dts/Bindings/leds/leds-lm3692x.txt
+++ b/dts/Bindings/leds/leds-lm3692x.txt
@@ -20,7 +20,10 @@ Optional properties:
- vled-supply : LED supply
Required child properties:
- - reg : 0
+ - reg : 0 - Will enable all LED sync paths
+ 1 - Will enable the LED1 sync
+ 2 - Will enable the LED2 sync
+ 3 - Will enable the LED3 sync (LM36923 only)
Optional child properties:
- label : see Documentation/devicetree/bindings/leds/common.txt
diff --git a/dts/Bindings/leds/leds-lt3593.txt b/dts/Bindings/leds/leds-lt3593.txt
new file mode 100644
index 0000000..6b2cabc
--- /dev/null
+++ b/dts/Bindings/leds/leds-lt3593.txt
@@ -0,0 +1,32 @@
+Bindings for Linear Technologies LT3593 LED controller
+
+Required properties:
+- compatible: Should be "lltc,lt3593".
+- lltc,ctrl-gpios: A handle to the GPIO that is connected to the 'CTRL'
+ pin of the chip.
+
+The hardware supports only one LED. The properties of this LED are
+configured in a sub-node in the device node.
+
+Optional sub-node properties:
+- label: A label for the LED. If none is given, the LED will be
+ named "lt3595::".
+- linux,default-trigger: The default trigger for the LED.
+ See Documentation/devicetree/bindings/leds/common.txt
+- default-state: The initial state of the LED.
+ See Documentation/devicetree/bindings/leds/common.txt
+
+If multiple chips of this type are found in a design, each one needs to
+be handled by its own device node.
+
+Example:
+
+led-controller {
+ compatible = "lltc,lt3593";
+ lltc,ctrl-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+
+ led {
+ label = "white:backlight";
+ default-state = "on";
+ };
+};
diff --git a/dts/Bindings/mailbox/altera-mailbox.txt b/dts/Bindings/mailbox/altera-mailbox.txt
index 49cfc8c..c4dd93f 100644
--- a/dts/Bindings/mailbox/altera-mailbox.txt
+++ b/dts/Bindings/mailbox/altera-mailbox.txt
@@ -9,7 +9,6 @@ Required properties:
of cells required for the mailbox specifier. Should be 1.
Optional properties:
-- interrupt-parent : interrupt source phandle.
- interrupts : interrupt number. The interrupt specifier format
depends on the interrupt controller parent.
diff --git a/dts/Bindings/mailbox/fsl,mu.txt b/dts/Bindings/mailbox/fsl,mu.txt
new file mode 100644
index 0000000..f3cf77e
--- /dev/null
+++ b/dts/Bindings/mailbox/fsl,mu.txt
@@ -0,0 +1,54 @@
+NXP i.MX Messaging Unit (MU)
+--------------------------------------------------------------------
+
+The Messaging Unit module enables two processors within the SoC to
+communicate and coordinate by passing messages (e.g. data, status
+and control) through the MU interface. The MU also provides the ability
+for one processor to signal the other processor using interrupts.
+
+Because the MU manages the messaging between processors, the MU uses
+different clocks (from each side of the different peripheral buses).
+Therefore, the MU must synchronize the accesses from one side to the
+other. The MU accomplishes synchronization using two sets of matching
+registers (Processor A-facing, Processor B-facing).
+
+Messaging Unit Device Node:
+=============================
+
+Required properties:
+-------------------
+- compatible : should be "fsl,<chip>-mu", the supported chips include
+ imx6sx, imx7s, imx8qxp, imx8qm.
+ The "fsl,imx6sx-mu" compatible is seen as generic and should
+ be included together with SoC specific compatible.
+- reg : Should contain the registers location and length
+- interrupts : Interrupt number. The interrupt specifier format depends
+ on the interrupt controller parent.
+- #mbox-cells: Must be 2.
+ <&phandle type channel>
+ phandle : Label name of controller
+ type : Channel type
+ channel : Channel number
+
+ This MU support 4 type of unidirectional channels, each type
+ has 4 channels. A total of 16 channels. Following types are
+ supported:
+ 0 - TX channel with 32bit transmit register and IRQ transmit
+ acknowledgment support.
+ 1 - RX channel with 32bit receive register and IRQ support
+ 2 - TX doorbell channel. Without own register and no ACK support.
+ 3 - RX doorbell channel.
+
+Optional properties:
+-------------------
+- clocks : phandle to the input clock.
+- fsl,mu-side-b : Should be set for side B MU.
+
+Examples:
+--------
+lsio_mu0: mailbox@5d1b0000 {
+ compatible = "fsl,imx8qxp-mu";
+ reg = <0x0 0x5d1b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+};
diff --git a/dts/Bindings/mailbox/mtk-gce.txt b/dts/Bindings/mailbox/mtk-gce.txt
new file mode 100644
index 0000000..7d72b21
--- /dev/null
+++ b/dts/Bindings/mailbox/mtk-gce.txt
@@ -0,0 +1,57 @@
+MediaTek GCE
+===============
+
+The Global Command Engine (GCE) is used to help read/write registers with
+critical time limitation, such as updating display configuration during the
+vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
+
+CMDQ driver uses mailbox framework for communication. Please refer to
+mailbox.txt for generic information about mailbox device-tree bindings.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-gce"
+- reg: Address range of the GCE unit
+- interrupts: The interrupt signal from the GCE block
+- clock: Clocks according to the common clock binding
+- clock-names: Must be "gce" to stand for GCE clock
+- #mbox-cells: Should be 3.
+ <&phandle channel priority atomic_exec>
+ phandle: Label name of a gce node.
+ channel: Channel of mailbox. Be equal to the thread id of GCE.
+ priority: Priority of GCE thread.
+ atomic_exec: GCE processing continuous packets of commands in atomic
+ way.
+
+Required properties for a client device:
+- mboxes: Client use mailbox to communicate with GCE, it should have this
+ property and list of phandle, mailbox specifiers.
+- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
+ to the register address.
+
+Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
+sub-system ids, thread priority, event ids.
+
+Example:
+
+ gce: gce@10212000 {
+ compatible = "mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ thread-num = CMDQ_THR_MAX_COUNT;
+ #mbox-cells = <3>;
+ };
+
+Example for a client device:
+
+ mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt8173-mmsys";
+ mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
+ mediatek,gce-subsys = <SUBSYS_1400XXXX>;
+ mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
+ CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+
+ ...
+ };
diff --git a/dts/Bindings/mailbox/ti,secure-proxy.txt b/dts/Bindings/mailbox/ti,secure-proxy.txt
new file mode 100644
index 0000000..6c9c7da
--- /dev/null
+++ b/dts/Bindings/mailbox/ti,secure-proxy.txt
@@ -0,0 +1,50 @@
+Texas Instruments' Secure Proxy
+========================================
+
+The Texas Instruments' secure proxy is a mailbox controller that has
+configurable queues selectable at SoC(System on Chip) integration. The
+Message manager is broken up into different address regions that are
+called "threads" or "proxies" - each instance is unidirectional and is
+instantiated at SoC integration level by system controller to indicate
+receive or transmit path.
+
+Message Manager Device Node:
+===========================
+Required properties:
+--------------------
+- compatible: Shall be "ti,am654-secure-proxy"
+- reg-names target_data - Map the proxy data region
+ rt - Map the realtime status region
+ scfg - Map the configuration region
+- reg: Contains the register map per reg-names.
+- #mbox-cells Shall be 1 and shall refer to the transfer path
+ called thread.
+- interrupt-names: Contains interrupt names matching the rx transfer path
+ for a given SoC. Receive interrupts shall be of the
+ format: "rx_<PID>".
+- interrupts: Contains the interrupt information corresponding to
+ interrupt-names property.
+
+Example(AM654):
+------------
+
+ secure_proxy: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x32c00000 0x0 0x100000>,
+ <0x0 0x32400000 0x0 0x100000>,
+ <0x0 0x32800000 0x0 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dmsc: dmsc {
+ [...]
+ mbox-names = "rx", "tx";
+ # RX Thread ID is 11
+ # TX Thread ID is 13
+ mboxes= <&secure_proxy 11>,
+ <&secure_proxy 13>;
+ [...]
+ };
diff --git a/dts/Bindings/media/cec-gpio.txt b/dts/Bindings/media/cec-gpio.txt
index 12fcd55..47e8d73 100644
--- a/dts/Bindings/media/cec-gpio.txt
+++ b/dts/Bindings/media/cec-gpio.txt
@@ -4,8 +4,8 @@ The HDMI CEC GPIO module supports CEC implementations where the CEC line
is hooked up to a pull-up GPIO line and - optionally - the HPD line is
hooked up to another GPIO line.
-Please note: the maximum voltage for the CEC line is 3.63V, for the HPD
-line it is 5.3V. So you may need some sort of level conversion circuitry
+Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and
+5V lines it is 5.3V. So you may need some sort of level conversion circuitry
when connecting them to a GPIO line.
Required properties:
@@ -19,18 +19,24 @@ following property is also required:
- hdmi-phandle - phandle to the HDMI controller, see also cec.txt.
If the CEC line is not associated with an HDMI receiver/transmitter, then
-the following property is optional:
+the following property is optional and can be used for debugging HPD changes:
- hpd-gpios: gpio that the HPD line is connected to.
+This property is optional and can be used for debugging changes on the 5V line:
+
+ - v5-gpios: gpio that the 5V line is connected to.
+
Example for the Raspberry Pi 3 where the CEC line is connected to
-pin 26 aka BCM7 aka CE1 on the GPIO pin header and the HPD line is
-connected to pin 11 aka BCM17 (some level shifter is needed for this!):
+pin 26 aka BCM7 aka CE1 on the GPIO pin header, the HPD line is
+connected to pin 11 aka BCM17 and the 5V line is connected to pin
+15 aka BCM22 (some level shifter is needed for the HPD and 5V lines!):
#include <dt-bindings/gpio/gpio.h>
cec-gpio {
- compatible = "cec-gpio";
- cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ compatible = "cec-gpio";
+ cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ v5-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/Bindings/media/i2c/ak7375.txt b/dts/Bindings/media/i2c/ak7375.txt
new file mode 100644
index 0000000..aa3e24b
--- /dev/null
+++ b/dts/Bindings/media/i2c/ak7375.txt
@@ -0,0 +1,8 @@
+Asahi Kasei Microdevices AK7375 voice coil lens driver
+
+AK7375 is a camera voice coil lens.
+
+Mandatory properties:
+
+- compatible: "asahi-kasei,ak7375"
+- reg: I2C slave address
diff --git a/dts/Bindings/media/i2c/aptina,mt9v111.txt b/dts/Bindings/media/i2c/aptina,mt9v111.txt
new file mode 100644
index 0000000..bd896e9
--- /dev/null
+++ b/dts/Bindings/media/i2c/aptina,mt9v111.txt
@@ -0,0 +1,46 @@
+* Aptina MT9V111 CMOS sensor
+----------------------------
+
+The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
+based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP).
+
+The sensor has an active pixel array of 640x480 pixels and can output a number
+of image resolution and formats controllable through a simple two-wires
+interface.
+
+Required properties:
+--------------------
+
+- compatible: shall be "aptina,mt9v111".
+- clocks: reference to the system clock input provider.
+
+Optional properties:
+--------------------
+
+- enable-gpios: output enable signal, pin name "OE#". Active low.
+- standby-gpios: low power state control signal, pin name "STANDBY".
+ Active high.
+- reset-gpios: chip reset signal, pin name "RESET#". Active low.
+
+The device node must contain one 'port' child node with one 'endpoint' child
+sub-node for its digital output video port, in accordance with the video
+interface bindings defined in:
+Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+--------
+
+ &i2c1 {
+ camera@48 {
+ compatible = "aptina,mt9v111";
+ reg = <0x48>;
+
+ clocks = <&camera_clk>;
+
+ port {
+ mt9v111_out: endpoint {
+ remote-endpoint = <&ceu_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/i2c/dongwoon,dw9807.txt b/dts/Bindings/media/i2c/dongwoon,dw9807.txt
new file mode 100644
index 0000000..c4701f1
--- /dev/null
+++ b/dts/Bindings/media/i2c/dongwoon,dw9807.txt
@@ -0,0 +1,9 @@
+Dongwoon Anatech DW9807 voice coil lens driver
+
+DW9807 is a 10-bit DAC with current sink capability. It is intended for
+controlling voice coil lenses.
+
+Mandatory properties:
+
+- compatible: "dongwoon,dw9807-vcm"
+- reg: I2C slave address
diff --git a/dts/Bindings/media/i2c/nokia,smia.txt b/dts/Bindings/media/i2c/nokia,smia.txt
index 33f10a9..8ee7c79 100644
--- a/dts/Bindings/media/i2c/nokia,smia.txt
+++ b/dts/Bindings/media/i2c/nokia,smia.txt
@@ -29,6 +29,9 @@ Optional properties
- reset-gpios: XSHUTDOWN GPIO
- flash-leds: See ../video-interfaces.txt
- lens-focus: See ../video-interfaces.txt
+- rotation: Integer property; valid values are 0 (sensor mounted upright)
+ and 180 (sensor mounted upside down). See
+ ../video-interfaces.txt .
Endpoint node mandatory properties
diff --git a/dts/Bindings/media/i2c/ov2680.txt b/dts/Bindings/media/i2c/ov2680.txt
new file mode 100644
index 0000000..11e925e
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov2680.txt
@@ -0,0 +1,46 @@
+* Omnivision OV2680 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: should be "ovti,ov2680".
+- clocks: reference to the xvclk input clock.
+- clock-names: should be "xvclk".
+- DOVDD-supply: Digital I/O voltage supply.
+- DVDD-supply: Digital core voltage supply.
+- AVDD-supply: Analog voltage supply.
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
+ if any. This is an active low signal to the OV2680.
+
+The device node must contain one 'port' child node for its digital output
+video port, and this port must have a single endpoint in accordance with
+ the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Endpoint node required properties for CSI-2 connection are:
+- remote-endpoint: a phandle to the bus receiver's endpoint node.
+- clock-lanes: should be set to <0> (clock lane on hardware lane 0).
+- data-lanes: should be set to <1> (one CSI-2 lane supported).
+
+Example:
+
+&i2c2 {
+ ov2680: camera-sensor@36 {
+ compatible = "ovti,ov2680";
+ reg = <0x36>;
+ clocks = <&osc>;
+ clock-names = "xvclk";
+ reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ DOVDD-supply = <&sw2_reg>;
+ DVDD-supply = <&sw2_reg>;
+ AVDD-supply = <&reg_peri_3p15v>;
+
+ port {
+ ov2680_to_mipi: endpoint {
+ remote-endpoint = <&mipi_from_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/ov5640.txt b/dts/Bindings/media/i2c/ov5640.txt
index 8e36da0..c97c2f2 100644
--- a/dts/Bindings/media/i2c/ov5640.txt
+++ b/dts/Bindings/media/i2c/ov5640.txt
@@ -13,6 +13,10 @@ Optional Properties:
This is an active low signal to the OV5640.
- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
if any. This is an active high signal to the OV5640.
+- rotation: as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt,
+ valid values are 0 (sensor mounted upright) and 180 (sensor
+ mounted upside down).
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
@@ -51,6 +55,7 @@ Examples:
DVDD-supply = <&vgen2_reg>; /* 1.5v */
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ rotation = <180>;
port {
/* MIPI CSI-2 bus endpoint */
diff --git a/dts/Bindings/media/i2c/tc358743.txt b/dts/Bindings/media/i2c/tc358743.txt
index 49f8bcc..59102ed 100644
--- a/dts/Bindings/media/i2c/tc358743.txt
+++ b/dts/Bindings/media/i2c/tc358743.txt
@@ -12,7 +12,7 @@ Required Properties:
Optional Properties:
- reset-gpios: gpio phandle GPIO connected to the reset pin
-- interrupts, interrupt-parent: GPIO connected to the interrupt pin
+- interrupts: GPIO connected to the interrupt pin
- data-lanes: should be <1 2 3 4> for four-lane operation,
or <1 2> for two-lane operation
- clock-lanes: should be <0>
diff --git a/dts/Bindings/media/nvidia,tegra-vde.txt b/dts/Bindings/media/nvidia,tegra-vde.txt
index 470237e..7302e94 100644
--- a/dts/Bindings/media/nvidia,tegra-vde.txt
+++ b/dts/Bindings/media/nvidia,tegra-vde.txt
@@ -27,9 +27,15 @@ Required properties:
- sxe
- clocks : Must include the following entries:
- vde
-- resets : Must include the following entries:
+- resets : Must contain an entry for each entry in reset-names.
+- reset-names : Should include the following entries:
- vde
+Optional properties:
+- resets : Must contain an entry for each entry in reset-names.
+- reset-names : Must include the following entries:
+ - mc
+
Example:
video-codec@6001a000 {
@@ -51,5 +57,6 @@ video-codec@6001a000 {
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
interrupt-names = "sync-token", "bsev", "sxe";
clocks = <&tegra_car TEGRA20_CLK_VDE>;
- resets = <&tegra_car 61>;
+ reset-names = "vde", "mc";
+ resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
};
diff --git a/dts/Bindings/media/qcom,camss.txt b/dts/Bindings/media/qcom,camss.txt
index cadeceb..09eb6ed 100644
--- a/dts/Bindings/media/qcom,camss.txt
+++ b/dts/Bindings/media/qcom,camss.txt
@@ -5,8 +5,9 @@ Qualcomm Camera Subsystem
- compatible:
Usage: required
Value type: <stringlist>
- Definition: Should contain:
+ Definition: Should contain one of:
- "qcom,msm8916-camss"
+ - "qcom,msm8996-camss"
- reg:
Usage: required
Value type: <prop-encoded-array>
@@ -19,11 +20,16 @@ Qualcomm Camera Subsystem
- "csiphy0_clk_mux"
- "csiphy1"
- "csiphy1_clk_mux"
+ - "csiphy2" (8996 only)
+ - "csiphy2_clk_mux" (8996 only)
- "csid0"
- "csid1"
+ - "csid2" (8996 only)
+ - "csid3" (8996 only)
- "ispif"
- "csi_clk_mux"
- "vfe0"
+ - "vfe1" (8996 only)
- interrupts:
Usage: required
Value type: <prop-encoded-array>
@@ -34,10 +40,14 @@ Qualcomm Camera Subsystem
Definition: Should contain the following entries:
- "csiphy0"
- "csiphy1"
+ - "csiphy2" (8996 only)
- "csid0"
- "csid1"
+ - "csid2" (8996 only)
+ - "csid3" (8996 only)
- "ispif"
- "vfe0"
+ - "vfe1" (8996 only)
- power-domains:
Usage: required
Value type: <prop-encoded-array>
@@ -53,25 +63,42 @@ Qualcomm Camera Subsystem
Usage: required
Value type: <stringlist>
Definition: Should contain the following entries:
- - "camss_top_ahb"
- - "ispif_ahb"
- - "csiphy0_timer"
- - "csiphy1_timer"
- - "csi0_ahb"
- - "csi0"
- - "csi0_phy"
- - "csi0_pix"
- - "csi0_rdi"
- - "csi1_ahb"
- - "csi1"
- - "csi1_phy"
- - "csi1_pix"
- - "csi1_rdi"
- - "camss_ahb"
- - "camss_vfe_vfe"
- - "camss_csi_vfe"
- - "iface"
- - "bus"
+ - "top_ahb"
+ - "ispif_ahb"
+ - "csiphy0_timer"
+ - "csiphy1_timer"
+ - "csiphy2_timer" (8996 only)
+ - "csi0_ahb"
+ - "csi0"
+ - "csi0_phy"
+ - "csi0_pix"
+ - "csi0_rdi"
+ - "csi1_ahb"
+ - "csi1"
+ - "csi1_phy"
+ - "csi1_pix"
+ - "csi1_rdi"
+ - "csi2_ahb" (8996 only)
+ - "csi2" (8996 only)
+ - "csi2_phy" (8996 only)
+ - "csi2_pix" (8996 only)
+ - "csi2_rdi" (8996 only)
+ - "csi3_ahb" (8996 only)
+ - "csi3" (8996 only)
+ - "csi3_phy" (8996 only)
+ - "csi3_pix" (8996 only)
+ - "csi3_rdi" (8996 only)
+ - "ahb"
+ - "vfe0"
+ - "csi_vfe0"
+ - "vfe0_ahb", (8996 only)
+ - "vfe0_stream", (8996 only)
+ - "vfe1", (8996 only)
+ - "csi_vfe1", (8996 only)
+ - "vfe1_ahb", (8996 only)
+ - "vfe1_stream", (8996 only)
+ - "vfe_ahb"
+ - "vfe_axi"
- vdda-supply:
Usage: required
Value type: <phandle>
@@ -90,22 +117,27 @@ Qualcomm Camera Subsystem
- reg:
Usage: required
Value type: <u32>
- Definition: Selects CSI2 PHY interface - PHY0 or PHY1.
+ Definition: Selects CSI2 PHY interface - PHY0, PHY1
+ or PHY2 (8996 only)
Endpoint node properties:
- clock-lanes:
Usage: required
Value type: <u32>
- Definition: The physical clock lane index. The value
- must always be <1> as the physical clock
- lane is lane 1.
+ Definition: The physical clock lane index. On 8916
+ the value must always be <1> as the physical
+ clock lane is lane 1. On 8996 the value must
+ always be <7> as the hardware supports D-PHY
+ and C-PHY, indexes are in a common set and
+ D-PHY physical clock lane is labeled as 7.
- data-lanes:
Usage: required
Value type: <prop-encoded-array>
- Definition: An array of physical data lanes indexes.
- Position of an entry determines the logical
- lane number, while the value of an entry
- indicates physical lane index. Lane swapping
- is supported.
+ Definition: An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported. Physical lane indexes for
+ 8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3.
* An Example
@@ -161,25 +193,25 @@ Qualcomm Camera Subsystem
<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
<&gcc GCC_CAMSS_VFE_AHB_CLK>,
<&gcc GCC_CAMSS_VFE_AXI_CLK>;
- clock-names = "camss_top_ahb",
- "ispif_ahb",
- "csiphy0_timer",
- "csiphy1_timer",
- "csi0_ahb",
- "csi0",
- "csi0_phy",
- "csi0_pix",
- "csi0_rdi",
- "csi1_ahb",
- "csi1",
- "csi1_phy",
- "csi1_pix",
- "csi1_rdi",
- "camss_ahb",
- "camss_vfe_vfe",
- "camss_csi_vfe",
- "iface",
- "bus";
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe_ahb",
+ "vfe_axi";
vdda-supply = <&pm8916_l2>;
iommus = <&apps_iommu 3>;
ports {
diff --git a/dts/Bindings/media/qcom,venus.txt b/dts/Bindings/media/qcom,venus.txt
index 2693449..00d0d1b 100644
--- a/dts/Bindings/media/qcom,venus.txt
+++ b/dts/Bindings/media/qcom,venus.txt
@@ -6,6 +6,7 @@
Definition: Value should contain one of:
- "qcom,msm8916-venus"
- "qcom,msm8996-venus"
+ - "qcom,sdm845-venus"
- reg:
Usage: required
Value type: <prop-encoded-array>
diff --git a/dts/Bindings/media/rcar_vin.txt b/dts/Bindings/media/rcar_vin.txt
index a19517e..2f42005 100644
--- a/dts/Bindings/media/rcar_vin.txt
+++ b/dts/Bindings/media/rcar_vin.txt
@@ -21,7 +21,9 @@ on Gen3 platforms to a CSI-2 receiver.
- "renesas,vin-r8a7794" for the R8A7794 device
- "renesas,vin-r8a7795" for the R8A7795 device
- "renesas,vin-r8a7796" for the R8A7796 device
+ - "renesas,vin-r8a77965" for the R8A77965 device
- "renesas,vin-r8a77970" for the R8A77970 device
+ - "renesas,vin-r8a77995" for the R8A77995 device
- "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
device.
@@ -37,30 +39,51 @@ Additionally, an alias named vinX will need to be created to specify
which video input device this is.
The per-board settings Gen2 platforms:
- - port sub-node describing a single endpoint connected to the vin
- as described in video-interfaces.txt[1]. Only the first one will
- be considered as each vin interface has one input port.
+
+- port - sub-node describing a single endpoint connected to the VIN
+ from external SoC pins as described in video-interfaces.txt[1].
+ Only the first one will be considered as each vin interface has one
+ input port.
+
+ - Optional properties for endpoint nodes:
+ - hsync-active: see [1] for description. Default is active high.
+ - vsync-active: see [1] for description. Default is active high.
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+ - field-active-even: see [1] for description. Default is active high.
+ - bus-width: see [1] for description. The selected bus width depends on
+ the SoC type and selected input image format.
+ Valid values are: 8, 10, 12, 16, 24 and 32.
+ - data-shift: see [1] for description. Valid values are 0 and 8.
+ - data-enable-active: polarity of CLKENB signal, see [1] for
+ description. Default is active high.
The per-board settings Gen3 platforms:
Gen3 platforms can support both a single connected parallel input source
-from external SoC pins (port0) and/or multiple parallel input sources
-from local SoC CSI-2 receivers (port1) depending on SoC.
+from external SoC pins (port@0) and/or multiple parallel input sources
+from local SoC CSI-2 receivers (port@1) depending on SoC.
- renesas,id - ID number of the VIN, VINx in the documentation.
- ports
- - port 0 - sub-node describing a single endpoint connected to the VIN
- from external SoC pins described in video-interfaces.txt[1].
- Describing more then one endpoint in port 0 is invalid. Only VIN
- instances that are connected to external pins should have port 0.
- - port 1 - sub-nodes describing one or more endpoints connected to
+ - port@0 - sub-node describing a single endpoint connected to the VIN
+ from external SoC pins as described in video-interfaces.txt[1].
+ Describing more than one endpoint in port@0 is invalid. Only VIN
+ instances that are connected to external pins should have port@0.
+
+ Endpoint nodes of port@0 support the optional properties listed in
+ the Gen2 per-board settings description.
+
+ - port@1 - sub-nodes describing one or more endpoints connected to
the VIN from local SoC CSI-2 receivers. The endpoint numbers must
use the following schema.
- - Endpoint 0 - sub-node describing the endpoint connected to CSI20
- - Endpoint 1 - sub-node describing the endpoint connected to CSI21
- - Endpoint 2 - sub-node describing the endpoint connected to CSI40
- - Endpoint 3 - sub-node describing the endpoint connected to CSI41
+ - endpoint@0 - sub-node describing the endpoint connected to CSI20
+ - endpoint@1 - sub-node describing the endpoint connected to CSI21
+ - endpoint@2 - sub-node describing the endpoint connected to CSI40
+ - endpoint@3 - sub-node describing the endpoint connected to CSI41
+
+ Endpoint nodes of port@1 do not support any optional endpoint property.
Device node example for Gen2 platforms
--------------------------------------
@@ -107,9 +130,6 @@ Board setup example for Gen2 platforms (vin1 composite video input)
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
diff --git a/dts/Bindings/media/sh_mobile_ceu.txt b/dts/Bindings/media/sh_mobile_ceu.txt
index 17a8e81..cfa4ffa 100644
--- a/dts/Bindings/media/sh_mobile_ceu.txt
+++ b/dts/Bindings/media/sh_mobile_ceu.txt
@@ -2,7 +2,6 @@ Bindings, specific for the sh_mobile_ceu_camera.c driver:
- compatible: Should be "renesas,sh-mobile-ceu"
- reg: register base and size
- interrupts: the interrupt number
- - interrupt-parent: the interrupt controller
- renesas,max-width: maximum image width, supported on this SoC
- renesas,max-height: maximum image height, supported on this SoC
diff --git a/dts/Bindings/media/video-interfaces.txt b/dts/Bindings/media/video-interfaces.txt
index 258b8df..baf9d97 100644
--- a/dts/Bindings/media/video-interfaces.txt
+++ b/dts/Bindings/media/video-interfaces.txt
@@ -85,6 +85,10 @@ Optional properties
- lens-focus: A phandle to the node of the focus lens controller.
+- rotation: The device, typically an image sensor, is not mounted upright,
+ but a number of degrees counter clockwise. Typical values are 0 and 180
+ (upside down).
+
Optional endpoint properties
----------------------------
@@ -109,6 +113,8 @@ Optional endpoint properties
Note, that if HSYNC and VSYNC polarities are not specified, embedded
synchronization may be required, where supported.
- data-active: similar to HSYNC and VSYNC, specifies data line polarity.
+- data-enable-active: similar to HSYNC and VSYNC, specifies the data enable
+ signal polarity.
- field-even-active: field signal level during the even field data transmission.
- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
signal.
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.txt b/dts/Bindings/memory-controllers/mediatek,smi-common.txt
index aa614b2..615abdd 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-common.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt8173 uses the second
-generation of SMI HW while mt2701 uses the first generation HW of SMI.
+Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
+the second generation of SMI HW while mt2701 uses the first generation HW of
+SMI.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -15,6 +16,7 @@ not needed for SMI generation 2.
Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
+ "mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
index ddf46b8..083155c 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
@@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
- compatible : must be one of :
- "mediatek,mt8173-smi-larb"
"mediatek,mt2701-smi-larb"
+ "mediatek,mt2712-smi-larb"
+ "mediatek,mt8173-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -15,7 +16,7 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
-Required property for mt2701:
+Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
Example:
diff --git a/dts/Bindings/mfd/ac100.txt b/dts/Bindings/mfd/ac100.txt
index b8ef006..dff219f 100644
--- a/dts/Bindings/mfd/ac100.txt
+++ b/dts/Bindings/mfd/ac100.txt
@@ -10,7 +10,6 @@ Required properties:
- sub-nodes:
- codec
- compatible: "x-powers,ac100-codec"
- - interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the
IRQ_AUDIO pin
- #clock-cells: Shall be 0
@@ -20,9 +19,6 @@ Required properties:
- rtc
- compatible: "x-powers,ac100-rtc"
- - interrupt-parent: The parent interrupt controller
- - interrupts: SoC NMI / GPIO interrupt connected to the
- IRQ_RTC pin
- clocks: A phandle to the codec's "4M_adda" clock
- #clock-cells: Shall be 1
- clock-output-names: "cko1_rtc", "cko2_rtc", "cko3_rtc"
diff --git a/dts/Bindings/mfd/altera-a10sr.txt b/dts/Bindings/mfd/altera-a10sr.txt
index c8a7365..a688520 100644
--- a/dts/Bindings/mfd/altera-a10sr.txt
+++ b/dts/Bindings/mfd/altera-a10sr.txt
@@ -5,7 +5,6 @@ Required parent device properties:
- spi-max-frequency : Maximum SPI frequency.
- reg : The SPI Chip Select address for the Arria10
System Resource chip
-- interrupt-parent : The parent interrupt controller.
- interrupts : The interrupt line the device is connected to.
- interrupt-controller : Marks the device node as an interrupt controller.
- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt
index a014afb..9b62831 100644
--- a/dts/Bindings/mfd/arizona.txt
+++ b/dts/Bindings/mfd/arizona.txt
@@ -22,7 +22,6 @@ Required properties:
connected to.
- interrupt-controller : Arizona class devices contain interrupt controllers
and may provide interrupt services to other devices.
- - interrupt-parent : The parent interrupt controller.
- #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
The first cell is the IRQ number.
The second cell is the flags, encoded as the trigger masks from
diff --git a/dts/Bindings/mfd/as3722.txt b/dts/Bindings/mfd/as3722.txt
index 5297b22..2a66574 100644
--- a/dts/Bindings/mfd/as3722.txt
+++ b/dts/Bindings/mfd/as3722.txt
@@ -20,6 +20,8 @@ Optional properties:
- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on
i2c scl/sda pins. Missing this will disable internal pullup on i2c
scl/sda lines.
+- ams,enable-ac-ok-power-on: Boolean property, to enable exit out of power off
+ mode with AC_OK pin (pin enabled in power off mode).
Optional submodule and their properties:
=======================================
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index d1762f3..188f037 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -28,7 +28,6 @@ Required properties:
* "x-powers,axp809"
* "x-powers,axp813"
- reg: The I2C slave address or RSB hardware address for the AXP chip
-- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
- interrupt-controller: The PMIC has its own internal IRQs
- #interrupt-cells: Should be set to 1
@@ -45,8 +44,11 @@ Optional properties:
board is driving OTG VBus or not.
(axp221 / axp223 / axp803/ axp813 only)
-- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
- wired for master mode. The default is slave mode.
+- x-powers,self-working-mode and
+ x-powers,master-mode: Boolean (axp806 only). Set either of these when the
+ PMIC is wired for self-working mode or master mode.
+ If neither is set then slave mode is assumed.
+ This corresponds to how the MODESET pin is wired.
- <input>-supply: a phandle to the regulator supply node. May be omitted if
inputs are unregulated, such as using the IPSOUT output
diff --git a/dts/Bindings/mfd/bd9571mwv.txt b/dts/Bindings/mfd/bd9571mwv.txt
index 25d1f69..8c46786 100644
--- a/dts/Bindings/mfd/bd9571mwv.txt
+++ b/dts/Bindings/mfd/bd9571mwv.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible : Should be "rohm,bd9571mwv".
- reg : I2C slave address.
- - interrupt-parent : Phandle to the parent interrupt controller.
- interrupts : The interrupt line the device is connected to.
- interrupt-controller : Marks the device node as an interrupt controller.
- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
diff --git a/dts/Bindings/mfd/bfticu.txt b/dts/Bindings/mfd/bfticu.txt
index 65c9077..538192f 100644
--- a/dts/Bindings/mfd/bfticu.txt
+++ b/dts/Bindings/mfd/bfticu.txt
@@ -10,7 +10,6 @@ Required properties:
- interrupts: the main IRQ line to signal the collected IRQs
- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to
- reg: access on the parent local bus (chip select, offset in chip select, size)
Example:
diff --git a/dts/Bindings/mfd/da9055.txt b/dts/Bindings/mfd/da9055.txt
index 6dab34d..131a532 100644
--- a/dts/Bindings/mfd/da9055.txt
+++ b/dts/Bindings/mfd/da9055.txt
@@ -22,8 +22,6 @@ Documentation/devicetree/bindings/sound/da9055.txt
Required properties:
- compatible : Should be "dlg,da9055-pmic"
- reg: Specifies the I2C slave address (defaults to 0x5a but can be modified)
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
- the IRQs from da9055 are delivered to.
- interrupts: IRQ line info for da9055 chip.
- interrupt-controller: da9055 has internal IRQs (has own IRQ domain).
- #interrupt-cells: Should be 1, is the local IRQ number for da9055.
diff --git a/dts/Bindings/mfd/da9062.txt b/dts/Bindings/mfd/da9062.txt
index c0a418c..edca653 100644
--- a/dts/Bindings/mfd/da9062.txt
+++ b/dts/Bindings/mfd/da9062.txt
@@ -32,8 +32,6 @@ Required properties:
"dlg,da9061" for DA9061
- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
modified to match the chip's OTP settings).
-- interrupt-parent : Specifies the reference to the interrupt controller for
- the DA9062 or DA9061.
- interrupts : IRQ line information.
- interrupt-controller
diff --git a/dts/Bindings/mfd/da9063.txt b/dts/Bindings/mfd/da9063.txt
index 443e682..8da8799 100644
--- a/dts/Bindings/mfd/da9063.txt
+++ b/dts/Bindings/mfd/da9063.txt
@@ -16,8 +16,6 @@ Required properties:
- compatible : Should be "dlg,da9063" or "dlg,da9063l"
- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
modified to match the chip's OTP settings).
-- interrupt-parent : Specifies the reference to the interrupt controller for
- the DA9063.
- interrupts : IRQ line information.
- interrupt-controller
diff --git a/dts/Bindings/mfd/da9150.txt b/dts/Bindings/mfd/da9150.txt
index fd4dca7..f09b41f 100644
--- a/dts/Bindings/mfd/da9150.txt
+++ b/dts/Bindings/mfd/da9150.txt
@@ -13,8 +13,6 @@ da9150-fg : Battery Fuel-Gauge
Required properties:
- compatible : Should be "dlg,da9150"
- reg: Specifies the I2C slave address
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
- the IRQs from da9150 are delivered to.
- interrupts: IRQ line info for da9150 chip.
- interrupt-controller: da9150 has internal IRQs (own IRQ domain).
(See ../interrupt-controller/interrupts.txt for
diff --git a/dts/Bindings/mfd/madera.txt b/dts/Bindings/mfd/madera.txt
new file mode 100644
index 0000000..db32660
--- /dev/null
+++ b/dts/Bindings/mfd/madera.txt
@@ -0,0 +1,102 @@
+Cirrus Logic Madera class audio codecs Multi-Functional Device
+
+These devices are audio SoCs with extensive digital capabilities and a range
+of analogue I/O.
+
+See also the child driver bindings in:
+bindings/pinctrl/cirrus,madera-pinctrl.txt
+bindings/regulator/arizona-regulator.txt
+bindings/sound/madera.txt
+
+Required properties:
+
+ - compatible : One of the following chip-specific strings:
+ "cirrus,cs47l35"
+ "cirrus,cs47l85"
+ "cirrus,cs47l90"
+ "cirrus,cs47l91"
+ "cirrus,wm1840"
+
+ - reg : I2C slave address when connected using I2C, chip select number when
+ using SPI.
+
+ - DCVDD-supply : Power supply for the device as defined in
+ bindings/regulator/regulator.txt
+ Mandatory on CS47L35, CS47L90, CS47L91
+ Optional on CS47L85, WM1840
+
+ - AVDD-supply, DBVDD1-supply, DBVDD2-supply, CPVDD1-supply, CPVDD2-supply :
+ Power supplies for the device
+
+ - DBVDD3-supply, DBVDD4-supply : Power supplies for the device
+ (CS47L85, CS47L90, CS47L91, WM1840)
+
+ - SPKVDDL-supply, SPKVDDR-supply : Power supplies for the device
+ (CS47L85, WM1840)
+
+ - SPKVDD-supply : Power supply for the device
+ (CS47L35)
+
+ - interrupt-controller : Indicates that this device is an interrupt controller
+
+ - #interrupt-cells: the number of cells to describe an IRQ, must be 2.
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ bindings/interrupt-controller/interrupts.txt
+
+ - gpio-controller : Indicates this device is a GPIO controller.
+
+ - #gpio-cells : Must be 2. The first cell is the pin number. The second cell
+ is reserved for future use and must be zero
+
+ - interrupt-parent : The parent interrupt controller.
+
+ - interrupts : The interrupt line the /IRQ signal for the device is
+ connected to.
+
+Optional properties:
+
+ - MICVDD-supply : Power supply, only need to be specified if
+ powered externally
+
+ - reset-gpios : One entry specifying the GPIO controlling /RESET.
+ As defined in bindings/gpio.txt.
+ Although optional, it is strongly recommended to use a hardware reset
+
+ - MICBIASx : Initial data for the MICBIAS regulators, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+ One for each MICBIAS generator (MICBIAS1, MICBIAS2, ...)
+ (all codecs)
+
+ One for each output pin (MICBIAS1A, MIBCIAS1B, MICBIAS2A, ...)
+ (all except CS47L85, WM1840)
+
+ The following following additional property is supported for the generator
+ nodes:
+ - cirrus,ext-cap : Set to 1 if the MICBIAS has external decoupling
+ capacitors attached.
+
+Optional child nodes:
+ micvdd : Node containing initialization data for the micvdd regulator
+ See bindings/regulator/arizona-regulator.txt
+
+ ldo1 : Node containing initialization data for the LDO1 regulator
+ See bindings/regulator/arizona-regulator.txt
+ (cs47l85, wm1840)
+
+Example:
+
+cs47l85@0 {
+ compatible = "cirrus,cs47l85";
+ reg = <0>;
+
+ reset-gpios = <&gpio 0>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <&host_irq1>;
+ interrupt-parent = <&gic>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+};
diff --git a/dts/Bindings/mfd/max14577.txt b/dts/Bindings/mfd/max14577.txt
index 236264c..fc6f0f4 100644
--- a/dts/Bindings/mfd/max14577.txt
+++ b/dts/Bindings/mfd/max14577.txt
@@ -11,7 +11,6 @@ Required properties:
- compatible : Must be "maxim,max14577" or "maxim,max77836".
- reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836)
- interrupts : IRQ line for the chip.
-- interrupt-parent : The parent interrupt controller.
Required nodes:
diff --git a/dts/Bindings/mfd/max77686.txt b/dts/Bindings/mfd/max77686.txt
index 0f2587f..42968b7 100644
--- a/dts/Bindings/mfd/max77686.txt
+++ b/dts/Bindings/mfd/max77686.txt
@@ -15,7 +15,6 @@ Required properties:
- compatible : Must be "maxim,max77686";
- reg : Specifies the i2c slave address of PMIC block.
- interrupts : This i2c device has an IRQ line connected to the main SoC.
-- interrupt-parent : The parent interrupt controller.
Example:
diff --git a/dts/Bindings/mfd/max77693.txt b/dts/Bindings/mfd/max77693.txt
index e675497..a3c60a7 100644
--- a/dts/Bindings/mfd/max77693.txt
+++ b/dts/Bindings/mfd/max77693.txt
@@ -14,7 +14,6 @@ Required properties:
- compatible : Must be "maxim,max77693".
- reg : Specifies the i2c slave address of PMIC block.
- interrupts : This i2c device has an IRQ line connected to the main SoC.
-- interrupt-parent : The parent interrupt controller.
Optional properties:
- regulators : The regulators of max77693 have to be instantiated under subnode
diff --git a/dts/Bindings/mfd/max77802.txt b/dts/Bindings/mfd/max77802.txt
index f2f3fe7..09decac 100644
--- a/dts/Bindings/mfd/max77802.txt
+++ b/dts/Bindings/mfd/max77802.txt
@@ -14,7 +14,6 @@ Required properties:
- compatible : Must be "maxim,max77802"
- reg : Specifies the I2C slave address of PMIC block.
- interrupts : I2C device IRQ line connected to the main SoC.
-- interrupt-parent : The parent interrupt controller.
Example:
diff --git a/dts/Bindings/mfd/max8998.txt b/dts/Bindings/mfd/max8998.txt
index 23a3650..5f2f07c 100644
--- a/dts/Bindings/mfd/max8998.txt
+++ b/dts/Bindings/mfd/max8998.txt
@@ -20,8 +20,6 @@ Required properties:
- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
Optional properties:
-- interrupt-parent: Specifies the phandle of the interrupt controller to which
- the interrupts from MAX8998 are routed to.
- interrupts: Interrupt specifiers for two interrupt sources.
- First interrupt specifier is for main interrupt.
- Second interrupt specifier is for power-on/-off interrupt.
diff --git a/dts/Bindings/mfd/motorola-cpcap.txt b/dts/Bindings/mfd/motorola-cpcap.txt
index c639705..5ddcc8f 100644
--- a/dts/Bindings/mfd/motorola-cpcap.txt
+++ b/dts/Bindings/mfd/motorola-cpcap.txt
@@ -3,7 +3,6 @@ Motorola CPCAP PMIC device tree binding
Required properties:
- compatible : One or both of "motorola,cpcap" or "ste,6556002"
- reg : SPI chip select
-- interrupt-parent : The parent interrupt controller
- interrupts : The interrupt line the device is connected to
- interrupt-controller : Marks the device node as an interrupt controller
- #interrupt-cells : The number of cells to describe an IRQ, should be 2
diff --git a/dts/Bindings/mfd/palmas.txt b/dts/Bindings/mfd/palmas.txt
index 8ae1a32..e736ab3 100644
--- a/dts/Bindings/mfd/palmas.txt
+++ b/dts/Bindings/mfd/palmas.txt
@@ -25,7 +25,6 @@ and also the generic series names
The first cell is the IRQ number.
The second cell is the flags, encoded as the trigger masks from
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-- interrupt-parent : The parent interrupt controller.
Optional properties:
ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
diff --git a/dts/Bindings/mfd/retu.txt b/dts/Bindings/mfd/retu.txt
index 8762423..df3005d 100644
--- a/dts/Bindings/mfd/retu.txt
+++ b/dts/Bindings/mfd/retu.txt
@@ -9,7 +9,6 @@ Required properties:
- compatible: "nokia,retu" or "nokia,tahvo"
- reg: Specifies the CBUS slave address of the ASIC chip
- interrupts: The interrupt line the device is connected to
-- interrupt-parent: The parent interrupt controller
Example:
diff --git a/dts/Bindings/mfd/rk808.txt b/dts/Bindings/mfd/rk808.txt
index 91b6522..1683ec3 100644
--- a/dts/Bindings/mfd/rk808.txt
+++ b/dts/Bindings/mfd/rk808.txt
@@ -10,7 +10,6 @@ Required properties:
- compatible: "rockchip,rk808"
- compatible: "rockchip,rk818"
- reg: I2C slave address
-- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
diff --git a/dts/Bindings/mfd/rohm,bd71837-pmic.txt b/dts/Bindings/mfd/rohm,bd71837-pmic.txt
new file mode 100644
index 0000000..3ca56fd
--- /dev/null
+++ b/dts/Bindings/mfd/rohm,bd71837-pmic.txt
@@ -0,0 +1,62 @@
+* ROHM BD71837 Power Management Integrated Circuit bindings
+
+BD71837MWV is a programmable Power Management IC for powering single-core,
+dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for
+low BOM cost and compact solution footprint. It integrates 8 Buck
+egulators and 7 LDOs to provide all the power rails required by the SoC and
+the commonly used peripherals.
+
+Datasheet for PMIC is available at:
+https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
+
+Required properties:
+ - compatible : Should be "rohm,bd71837".
+ - reg : I2C slave address.
+ - interrupt-parent : Phandle to the parent interrupt controller.
+ - interrupts : The interrupt line the device is connected to.
+ - clocks : The parent clock connected to PMIC. If this is missing
+ 32768 KHz clock is assumed.
+ - #clock-cells : Should be 0.
+ - regulators: : List of child nodes that specify the regulators.
+ Please see ../regulator/rohm,bd71837-regulator.txt
+
+Optional properties:
+- clock-output-names : Should contain name for output clock.
+
+Example:
+
+ /* external oscillator node */
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <1>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc";
+ };
+
+ pmic: pmic@4b {
+ compatible = "rohm,bd71837";
+ reg = <0x4b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 GPIO_ACTIVE_LOW>;
+ interrupt-names = "irq";
+ #clock-cells = <0>;
+ clocks = <&osc 0>;
+ clock-output-names = "bd71837-32k-out";
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <1250>;
+ };
+ };
+ };
+
+ /* Clock consumer node */
+ rtc@0 {
+ compatible = "company,my-rtc";
+ clock-names = "my-clock";
+ clocks = <&pmic>;
+ };
diff --git a/dts/Bindings/mfd/samsung,sec-core.txt b/dts/Bindings/mfd/samsung,sec-core.txt
index cdd079b..c68cdd3 100644
--- a/dts/Bindings/mfd/samsung,sec-core.txt
+++ b/dts/Bindings/mfd/samsung,sec-core.txt
@@ -31,8 +31,6 @@ Required properties:
- reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
Optional properties:
- - interrupt-parent: Specifies the phandle of the interrupt controller to which
- the interrupts from s2mps11 are delivered to.
- interrupts: Interrupt specifiers for interrupt sources.
- samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled
down. When the system is suspended it will always go down thus triggerring
diff --git a/dts/Bindings/mfd/stmpe.txt b/dts/Bindings/mfd/stmpe.txt
index f9065a5..c797c05 100644
--- a/dts/Bindings/mfd/stmpe.txt
+++ b/dts/Bindings/mfd/stmpe.txt
@@ -10,7 +10,6 @@ Required properties:
Optional properties:
- interrupts : The interrupt outputs from the controller
- interrupt-controller : Marks the device node as an interrupt controller
- - interrupt-parent : Specifies which IRQ controller we're connected to
- wakeup-source : Marks the input device as wakable
- st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
- irq-gpio : If present, which GPIO to use for event IRQ
diff --git a/dts/Bindings/mfd/tc3589x.txt b/dts/Bindings/mfd/tc3589x.txt
index 23fc2f2..4f22b2b 100644
--- a/dts/Bindings/mfd/tc3589x.txt
+++ b/dts/Bindings/mfd/tc3589x.txt
@@ -15,7 +15,6 @@ Required properties:
- compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
"toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896"
- reg : I2C address of the device
- - interrupt-parent : specifies which IRQ controller we're connected to
- interrupts : the interrupt on the parent the controller is connected to
- interrupt-controller : marks the device node as an interrupt controller
- #interrupt-cells : should be <1>, the first cell is the IRQ offset on this
diff --git a/dts/Bindings/mfd/tps65086.txt b/dts/Bindings/mfd/tps65086.txt
index 9cfa886..67eac0e 100644
--- a/dts/Bindings/mfd/tps65086.txt
+++ b/dts/Bindings/mfd/tps65086.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible : Should be "ti,tps65086".
- reg : I2C slave address.
- - interrupt-parent : Phandle to the parent interrupt controller.
- interrupts : The interrupt line the device is connected to.
- interrupt-controller : Marks the device node as an interrupt controller.
- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
diff --git a/dts/Bindings/mfd/tps65910.txt b/dts/Bindings/mfd/tps65910.txt
index 8af1202..4f62143 100644
--- a/dts/Bindings/mfd/tps65910.txt
+++ b/dts/Bindings/mfd/tps65910.txt
@@ -22,7 +22,7 @@ Required properties:
The valid regulator-compatible values are:
tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1,
vaux2, vaux33, vmmc, vbb
- tps65911: vrtc, vio, vdd1, vdd3, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5,
+ tps65911: vrtc, vio, vdd1, vdd2, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5,
ldo6, ldo7, ldo8
- xxx-supply: Input voltage supply regulator.
diff --git a/dts/Bindings/mfd/tps65912.txt b/dts/Bindings/mfd/tps65912.txt
index 717e66d..8becb18 100644
--- a/dts/Bindings/mfd/tps65912.txt
+++ b/dts/Bindings/mfd/tps65912.txt
@@ -3,7 +3,6 @@
Required properties:
- compatible : Should be "ti,tps65912".
- reg : Slave address or chip select number (I2C / SPI).
- - interrupt-parent : The parent interrupt controller.
- interrupts : The interrupt line the device is connected to.
- interrupt-controller : Marks the device node as an interrupt controller.
- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
diff --git a/dts/Bindings/mfd/twl-familly.txt b/dts/Bindings/mfd/twl-familly.txt
index a66fcf9..56f244b 100644
--- a/dts/Bindings/mfd/twl-familly.txt
+++ b/dts/Bindings/mfd/twl-familly.txt
@@ -16,7 +16,6 @@ Required properties:
- interrupt-controller : Since the twl support several interrupts internally,
it is considered as an interrupt controller cascaded to the SoC one.
- #interrupt-cells = <1>;
-- interrupt-parent : The parent interrupt controller.
Optional node:
- Child nodes contain in the twl. The twl family is made of several variants
diff --git a/dts/Bindings/mfd/twl6040.txt b/dts/Bindings/mfd/twl6040.txt
index 9a98ee7..06e9dd7 100644
--- a/dts/Bindings/mfd/twl6040.txt
+++ b/dts/Bindings/mfd/twl6040.txt
@@ -9,7 +9,6 @@ Required properties:
- compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041
- reg: must be 0x4b for i2c address
- interrupts: twl6040 has one interrupt line connecteded to the main SoC
-- interrupt-parent: The parent interrupt controller
- gpio-controller:
- #gpio-cells = <1>: twl6040 provides GPO lines.
- #clock-cells = <0>; twl6040 is a provider of pdmclk which is used by McPDM
diff --git a/dts/Bindings/mfd/wm831x.txt b/dts/Bindings/mfd/wm831x.txt
index 5057094..6b84b1b 100644
--- a/dts/Bindings/mfd/wm831x.txt
+++ b/dts/Bindings/mfd/wm831x.txt
@@ -22,7 +22,6 @@ Required properties:
- interrupts : The interrupt line the IRQ signal for the device is
connected to.
- - interrupt-parent : The parent interrupt controller.
- interrupt-controller : wm831x devices contain interrupt controllers and
may provide interrupt services to other devices.
diff --git a/dts/Bindings/mips/cavium/cib.txt b/dts/Bindings/mips/cavium/cib.txt
index f39a1aa..410efa3 100644
--- a/dts/Bindings/mips/cavium/cib.txt
+++ b/dts/Bindings/mips/cavium/cib.txt
@@ -13,8 +13,6 @@ Properties:
- cavium,max-bits: The index (zero based) of the highest numbered bit
in the CIB block.
-- interrupt-parent: Always the CIU on the SoC.
-
- interrupts: The CIU line to which the CIB block is connected.
- #interrupt-cells: Must be <2>. The first cell is the bit within the
diff --git a/dts/Bindings/misc/aspeed,cvic.txt b/dts/Bindings/misc/aspeed,cvic.txt
new file mode 100644
index 0000000..d62c783
--- /dev/null
+++ b/dts/Bindings/misc/aspeed,cvic.txt
@@ -0,0 +1,35 @@
+* ASPEED AST2400 and AST2500 coprocessor interrupt controller
+
+This file describes the bindings for the interrupt controller present
+in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
+ColdFire coprocessor.
+
+It is not a normal interrupt controller and it would be rather
+inconvenient to create an interrupt tree for it as it somewhat shares
+some of the same sources as the main ARM interrupt controller but with
+different numbers.
+
+The AST2500 supports a SW generated interrupt
+
+Required properties:
+- reg: address and length of the register for the device.
+- compatible: "aspeed,cvic" and one of:
+ "aspeed,ast2400-cvic"