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authorLucas Stach <l.stach@pengutronix.de>2017-07-31 20:03:05 +0200
committerLucas Stach <l.stach@pengutronix.de>2017-07-31 20:03:05 +0200
commitd14b844b08635c717fb52a294ed8d6872e260315 (patch)
tree18607dcdd29688b2fa9528f79423183a68e9898d /dts
parent858b797e529e26c19bfa893fdb37ed67ff7a6006 (diff)
downloadbarebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.gz
barebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.xz
dts: update to v4.13-rc2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/arm/actions.txt39
-rw-r--r--dts/Bindings/arm/amlogic.txt23
-rw-r--r--dts/Bindings/arm/atmel-at91.txt30
-rw-r--r--dts/Bindings/arm/bcm/brcm,stingray.txt12
-rw-r--r--dts/Bindings/arm/cci.txt15
-rw-r--r--dts/Bindings/arm/ccn.txt1
-rw-r--r--dts/Bindings/arm/coresight-cpu-debug.txt49
-rw-r--r--dts/Bindings/arm/cpus.txt18
-rw-r--r--dts/Bindings/arm/gemini.txt24
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt4
-rw-r--r--dts/Bindings/arm/idle-states.txt4
-rw-r--r--dts/Bindings/arm/keystone/keystone.txt3
-rw-r--r--dts/Bindings/arm/l2c2x0.txt4
-rw-r--r--dts/Bindings/arm/marvell/ap806-system-controller.txt85
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller0.txt144
-rw-r--r--dts/Bindings/arm/mediatek.txt8
-rw-r--r--dts/Bindings/arm/realtek.txt20
-rw-r--r--dts/Bindings/arm/rockchip.txt8
-rw-r--r--dts/Bindings/arm/shmobile.txt13
-rw-r--r--dts/Bindings/arm/tegra.txt1
-rw-r--r--dts/Bindings/arm/topology.txt4
-rw-r--r--dts/Bindings/ata/ahci-fsl-qoriq.txt2
-rw-r--r--dts/Bindings/ata/cortina,gemini-sata-bridge.txt55
-rw-r--r--dts/Bindings/ata/faraday,ftide010.txt38
-rw-r--r--dts/Bindings/bus/brcm,gisb-arb.txt3
-rw-r--r--dts/Bindings/bus/simple-pm-bus.txt2
-rw-r--r--dts/Bindings/chosen.txt3
-rw-r--r--dts/Bindings/clock/amlogic,meson8b-clkc.txt11
-rw-r--r--dts/Bindings/clock/brcm,iproc-clocks.txt76
-rw-r--r--dts/Bindings/clock/hi6220-clock.txt1
-rw-r--r--dts/Bindings/clock/img,boston-clock.txt31
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt1
-rw-r--r--dts/Bindings/clock/qoriq-clock.txt6
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt10
-rw-r--r--dts/Bindings/clock/rockchip,rk3128-cru.txt56
-rw-r--r--dts/Bindings/clock/sun8i-de2.txt31
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt5
-rw-r--r--dts/Bindings/clock/ti,sci-clk.txt37
-rw-r--r--dts/Bindings/clock/ti-clkctrl.txt56
-rw-r--r--dts/Bindings/common-properties.txt2
-rw-r--r--dts/Bindings/cpufreq/ti-cpufreq.txt20
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt4
-rw-r--r--dts/Bindings/crypto/fsl-sec6.txt4
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt29
-rw-r--r--dts/Bindings/crypto/mediatek-crypto.txt8
-rw-r--r--dts/Bindings/display/brcm,bcm-vc4.txt7
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt8
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt9
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt13
-rw-r--r--dts/Bindings/display/panel/auo,p320hvn03.txt8
-rw-r--r--dts/Bindings/display/panel/display-timing.txt16
-rw-r--r--dts/Bindings/display/panel/innolux,p079zca.txt23
-rw-r--r--dts/Bindings/display/panel/nec,nl12880b20-05.txt8
-rw-r--r--dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt8
-rw-r--r--dts/Bindings/display/panel/samsung,s6e3ha2.txt5
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.txt36
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt127
-rw-r--r--dts/Bindings/display/zte,vou.txt21
-rw-r--r--dts/Bindings/dma/arm-pl08x.txt9
-rw-r--r--dts/Bindings/dma/brcm,iproc-sba.txt29
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt5
-rw-r--r--dts/Bindings/dma/shdma.txt2
-rw-r--r--dts/Bindings/fsi/fsi-master-gpio.txt24
-rw-r--r--dts/Bindings/gpio/gpio-mvebu.txt24
-rw-r--r--dts/Bindings/gpio/gpio.txt13
-rw-r--r--dts/Bindings/gpio/gpio_atmel.txt10
-rw-r--r--dts/Bindings/gpio/ingenic,gpio.txt46
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt1
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.txt86
-rw-r--r--dts/Bindings/graph.txt13
-rw-r--r--dts/Bindings/hwlock/sprd-hwspinlock.txt23
-rw-r--r--dts/Bindings/i2c/i2c-aspeed.txt48
-rw-r--r--dts/Bindings/i2c/i2c-designware.txt16
-rw-r--r--dts/Bindings/i2c/i2c-mtk.txt (renamed from dts/Bindings/i2c/i2c-mt6577.txt)10
-rw-r--r--dts/Bindings/i2c/i2c-mux-gpmux.txt99
-rw-r--r--dts/Bindings/i2c/i2c-pca-platform.txt29
-rw-r--r--dts/Bindings/i2c/i2c-zx2967.txt22
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.txt2
-rw-r--r--dts/Bindings/iio/adc/renesas,gyroadc.txt9
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt28
-rw-r--r--dts/Bindings/iio/adc/ti-adc084s021.txt19
-rw-r--r--dts/Bindings/iio/adc/ti-adc108s102.txt18
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt3
-rw-r--r--dts/Bindings/iio/multiplexer/io-channel-mux.txt39
-rw-r--r--dts/Bindings/iio/proximity/as3935.txt2
-rw-r--r--dts/Bindings/input/dlink,dir685-touchkeys.txt21
-rw-r--r--dts/Bindings/input/touchscreen/st,stmfts.txt43
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt7
-rw-r--r--dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt25
-rw-r--r--dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt9
-rw-r--r--dts/Bindings/interrupt-controller/marvell,gicp.txt27
-rw-r--r--dts/Bindings/interrupt-controller/marvell,icu.txt51
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt28
-rw-r--r--dts/Bindings/interrupt-controller/open-pic.txt5
-rw-r--r--dts/Bindings/iommu/arm,smmu-v3.txt12
-rw-r--r--dts/Bindings/leds/common.txt35
-rw-r--r--dts/Bindings/leds/pca963x.txt1
-rw-r--r--dts/Bindings/mailbox/qcom,apcs-kpss-global.txt46
-rw-r--r--dts/Bindings/media/cec.txt8
-rw-r--r--dts/Bindings/media/i2c/adv7180.txt15
-rw-r--r--dts/Bindings/media/i2c/max2175.txt59
-rw-r--r--dts/Bindings/media/i2c/ov5640.txt45
-rw-r--r--dts/Bindings/media/imx.txt53
-rw-r--r--dts/Bindings/media/mediatek-mdp.txt12
-rw-r--r--dts/Bindings/media/qcom,venus.txt107
-rw-r--r--dts/Bindings/media/rcar_vin.txt4
-rw-r--r--dts/Bindings/media/renesas,drif.txt176
-rw-r--r--dts/Bindings/media/s5p-cec.txt6
-rw-r--r--dts/Bindings/media/st,stm32-cec.txt19
-rw-r--r--dts/Bindings/media/st,stm32-dcmi.txt45
-rw-r--r--dts/Bindings/media/stih-cec.txt2
-rw-r--r--dts/Bindings/media/video-mux.txt60
-rw-r--r--dts/Bindings/mfd/arizona.txt3
-rw-r--r--dts/Bindings/mfd/hi6421.txt4
-rw-r--r--dts/Bindings/mfd/lp87565.txt43
-rw-r--r--dts/Bindings/mfd/tps65910.txt4
-rw-r--r--dts/Bindings/misc/allwinner,syscon.txt20
-rw-r--r--dts/Bindings/mmc/fsl-esdhc.txt14
-rw-r--r--dts/Bindings/mmc/k3-dw-mshc.txt1
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt5
-rw-r--r--dts/Bindings/mmc/ti-omap-hsmmc.txt2
-rw-r--r--dts/Bindings/mtd/atmel-nand.txt14
-rw-r--r--dts/Bindings/mtd/denali-nand.txt13
-rw-r--r--dts/Bindings/mtd/elm.txt2
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt2
-rw-r--r--dts/Bindings/mtd/gpmc-nor.txt4
-rw-r--r--dts/Bindings/mtd/gpmc-onenand.txt2
-rw-r--r--dts/Bindings/mtd/gpmi-nand.txt14
-rw-r--r--dts/Bindings/mtd/microchip,mchp23k256.txt18
-rw-r--r--dts/Bindings/mtd/mtk-nand.txt5
-rw-r--r--dts/Bindings/mtd/nand.txt2
-rw-r--r--dts/Bindings/mtd/partition.txt32
-rw-r--r--dts/Bindings/mux/adi,adg792a.txt75
-rw-r--r--dts/Bindings/mux/gpio-mux.txt69
-rw-r--r--dts/Bindings/mux/mmio-mux.txt60
-rw-r--r--dts/Bindings/mux/mux-controller.txt157
-rw-r--r--dts/Bindings/net/brcm,amac.txt1
-rw-r--r--dts/Bindings/net/brcm,bgmac-nsp.txt24
-rw-r--r--dts/Bindings/net/cortina.txt21
-rw-r--r--dts/Bindings/net/dsa/b53.txt3
-rw-r--r--dts/Bindings/net/dsa/ksz.txt72
-rw-r--r--dts/Bindings/net/dwmac-sun8i.txt84
-rw-r--r--dts/Bindings/net/ethernet.txt12
-rw-r--r--dts/Bindings/net/fsl-fman.txt (renamed from dts/Bindings/powerpc/fsl/fman.txt)0
-rw-r--r--dts/Bindings/net/gpmc-eth.txt4
-rw-r--r--dts/Bindings/net/macb.txt1
-rw-r--r--dts/Bindings/net/marvell-orion-mdio.txt10
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt10
-rw-r--r--dts/Bindings/net/qca,qca7000.txt88
-rw-r--r--dts/Bindings/net/qca-qca7000-spi.txt47
-rw-r--r--dts/Bindings/net/ti,dp83867.txt7
-rw-r--r--dts/Bindings/net/ti,wilink-st.txt12
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt2
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore.txt1
-rw-r--r--dts/Bindings/nvmem/rockchip-efuse.txt1
-rw-r--r--dts/Bindings/opp/opp.txt38
-rw-r--r--dts/Bindings/pci/faraday,ftpci100.txt7
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt4
-rw-r--r--dts/Bindings/pci/kirin-pcie.txt50
-rw-r--r--dts/Bindings/pci/mediatek,mt7623-pcie.txt130
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt20
-rw-r--r--dts/Bindings/pci/rcar-pci.txt2
-rw-r--r--dts/Bindings/pci/tango-pcie.txt29
-rw-r--r--dts/Bindings/phy/bcm-ns-usb3-phy.txt27
-rw-r--r--dts/Bindings/phy/brcm,ns2-drd-phy.txt30
-rw-r--r--dts/Bindings/phy/brcm-sata-phy.txt7
-rw-r--r--dts/Bindings/phy/meson-gxl-usb2-phy.txt17
-rw-r--r--dts/Bindings/phy/meson8b-usb2-phy.txt3
-rw-r--r--dts/Bindings/phy/phy-cpcap-usb.txt40
-rw-r--r--dts/Bindings/phy/phy-rockchip-inno-usb2.txt1
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb3.txt46
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/ingenic,pinctrl.txt41
-rw-r--r--dts/Bindings/pinctrl/pinctrl-bindings.txt25
-rw-r--r--dts/Bindings/pinctrl/pinctrl-zx.txt85
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt172
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/renesas,rza1-pinctrl.txt221
-rw-r--r--dts/Bindings/power/actions,owl-sps.txt17
-rw-r--r--dts/Bindings/power/rockchip-io-domain.txt7
-rw-r--r--dts/Bindings/power/supply/battery.txt57
-rw-r--r--dts/Bindings/power/supply/bq27xxx.txt31
-rw-r--r--dts/Bindings/power/supply/cpcap-battery.txt31
-rw-r--r--dts/Bindings/power/supply/ltc3651-charger.txt27
-rw-r--r--dts/Bindings/power/supply/max8903-charger.txt (renamed from dts/Bindings/power/max8903-charger.txt)0
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.txt (renamed from dts/Bindings/power_supply/maxim,max14656.txt)0
-rw-r--r--dts/Bindings/powerpc/fsl/cpus.txt6
-rw-r--r--dts/Bindings/powerpc/fsl/l2cache.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/srio-rmu.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/srio.txt3
-rw-r--r--dts/Bindings/property-units.txt3
-rw-r--r--dts/Bindings/ptp/brcm,ptp-dte.txt20
-rw-r--r--dts/Bindings/pwm/pwm-meson.txt4
-rw-r--r--dts/Bindings/pwm/pwm-stm32.txt2
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt1
-rw-r--r--dts/Bindings/regulator/regulator.txt8
-rw-r--r--dts/Bindings/remoteproc/ti,keystone-rproc.txt133
-rw-r--r--dts/Bindings/reserved-memory/reserved-memory.txt3
-rw-r--r--dts/Bindings/reset/ti,sci-reset.txt62
-rw-r--r--dts/Bindings/rng/mtk-rng.txt4
-rw-r--r--dts/Bindings/rng/timeriomem_rng.txt7
-rw-r--r--dts/Bindings/rtc/brcm,brcmstb-waketimer.txt22
-rw-r--r--dts/Bindings/rtc/cortina,gemini.txt14
-rw-r--r--dts/Bindings/rtc/faraday,ftrtc010.txt28
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.txt32
-rw-r--r--dts/Bindings/serial/8250.txt3
-rw-r--r--dts/Bindings/serial/actions,owl-uart.txt16
-rw-r--r--dts/Bindings/serial/amlogic,meson-uart.txt38
-rw-r--r--dts/Bindings/serial/fsl-lpuart.txt2
-rw-r--r--dts/Bindings/serial/mtk-uart.txt2
-rw-r--r--dts/Bindings/serial/slave-device.txt9
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt6
-rw-r--r--dts/Bindings/soc/qcom/qcom,glink.txt73
-rw-r--r--dts/Bindings/sound/audio-graph-card.txt129
-rw-r--r--dts/Bindings/sound/audio-graph-scu-card.txt122
-rw-r--r--dts/Bindings/sound/cs35l35.txt3
-rw-r--r--dts/Bindings/sound/nau8825.txt3
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt37
-rw-r--r--dts/Bindings/sound/rockchip,pdm.txt39
-rw-r--r--dts/Bindings/sound/rockchip-spdif.txt2
-rw-r--r--dts/Bindings/sound/samsung,odroid.txt15
-rw-r--r--dts/Bindings/sound/simple-scu-card.txt67
-rw-r--r--dts/Bindings/sound/st,stm32-i2s.txt62
-rw-r--r--dts/Bindings/sound/st,stm32-sai.txt41
-rw-r--r--dts/Bindings/sound/st,stm32-spdifrx.txt56
-rw-r--r--dts/Bindings/sound/sun4i-codec.txt11
-rw-r--r--dts/Bindings/sound/sun8i-codec-analog.txt1
-rw-r--r--dts/Bindings/sound/zte,zx-aud96p22.txt24
-rw-r--r--dts/Bindings/spi/sh-msiof.txt2
-rw-r--r--dts/Bindings/spi/spi-bus.txt76
-rw-r--r--dts/Bindings/spi/spi-meson.txt31
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt2
-rw-r--r--dts/Bindings/spi/spi-stm32.txt59
-rw-r--r--dts/Bindings/thermal/brcm,ns-thermal.txt (renamed from dts/Bindings/thermal/brcm,ns-thermal)0
-rw-r--r--dts/Bindings/timer/actions,owl-timer.txt20
-rw-r--r--dts/Bindings/timer/faraday,fttmr010.txt6
-rw-r--r--dts/Bindings/timer/moxa,moxart-timer.txt19
-rw-r--r--dts/Bindings/trivial-devices.txt1
-rw-r--r--dts/Bindings/usb/dwc3.txt2
-rw-r--r--dts/Bindings/usb/exynos-usb.txt4
-rw-r--r--dts/Bindings/usb/iproc-udc.txt21
-rw-r--r--dts/Bindings/usb/usb-ohci.txt1
-rw-r--r--dts/Bindings/vendor-prefixes.txt13
-rw-r--r--dts/Bindings/watchdog/da9062-wdt.txt23
-rw-r--r--dts/Bindings/watchdog/dw_wdt.txt3
-rw-r--r--dts/Bindings/watchdog/renesas-wdt.txt4
-rw-r--r--dts/Bindings/watchdog/st,stm32-iwdg.txt19
-rw-r--r--dts/Bindings/watchdog/uniphier-wdt.txt20
-rw-r--r--dts/include/dt-bindings/clock/bcm-sr.h101
-rw-r--r--dts/include/dt-bindings/clock/boston-clock.h14
-rw-r--r--dts/include/dt-bindings/clock/cortina,gemini-clock.h29
-rw-r--r--dts/include/dt-bindings/clock/exynos5420.h3
-rw-r--r--dts/include/dt-bindings/clock/gxbb-clkc.h10
-rw-r--r--dts/include/dt-bindings/clock/hi3660-clock.h17
-rw-r--r--dts/include/dt-bindings/clock/hi6220-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/histb-clock.h9
-rw-r--r--dts/include/dt-bindings/clock/imx7d-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/meson8b-clkc.h10
-rw-r--r--dts/include/dt-bindings/clock/mt2701-clk.h3
-rw-r--r--dts/include/dt-bindings/clock/mt8173-clk.h4
-rw-r--r--dts/include/dt-bindings/clock/omap4.h146
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h152
-rw-r--r--dts/include/dt-bindings/clock/r7s72100-clock.h53
-rw-r--r--dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h52
-rw-r--r--dts/include/dt-bindings/clock/r8a7791-clock.h1
-rw-r--r--dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h48
-rw-r--r--dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h43
-rw-r--r--dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h48
-rw-r--r--dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h47
-rw-r--r--dts/include/dt-bindings/clock/rk3128-cru.h282
-rw-r--r--dts/include/dt-bindings/clock/rk3228-cru.h47
-rw-r--r--dts/include/dt-bindings/clock/rk3399-cru.h2
-rw-r--r--dts/include/dt-bindings/clock/sun5i-ccu.h3
-rw-r--r--dts/include/dt-bindings/clock/sun8i-a83t-ccu.h140
-rw-r--r--dts/include/dt-bindings/clock/sun8i-de2.h18
-rw-r--r--dts/include/dt-bindings/clock/zx296718-clock.h6
-rw-r--r--dts/include/dt-bindings/gpio/gpio.h4
-rw-r--r--dts/include/dt-bindings/input/linux-event-codes.h1
-rw-r--r--dts/include/dt-bindings/interrupt-controller/mvebu-icu.h15
-rw-r--r--dts/include/dt-bindings/mux/mux.h16
-rw-r--r--dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h68
-rw-r--r--dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h16
-rw-r--r--dts/include/dt-bindings/power/mt6797-power.h30
-rw-r--r--dts/include/dt-bindings/power/owl-s500-powergate.h19
-rw-r--r--dts/include/dt-bindings/reset/altr,rst-mgr-s10.h108
-rw-r--r--dts/include/dt-bindings/reset/cortina,gemini-reset.h36
-rw-r--r--dts/include/dt-bindings/reset/sun8i-a83t-ccu.h98
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-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi18
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi165
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts70
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-ref.dts38
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi61
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts52
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts38
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi79
-rw-r--r--dts/src/arm64/socionext/uniphier-ref-daughter.dtsi38
-rw-r--r--dts/src/arm64/socionext/uniphier-support-card.dtsi42
-rw-r--r--dts/src/arm64/zte/zx296718.dtsi10
-rw-r--r--dts/src/mips/img/boston.dts224
-rw-r--r--dts/src/mips/ingenic/ci20.dts60
-rw-r--r--dts/src/mips/ingenic/jz4740.dtsi68
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi98
-rw-r--r--dts/src/mips/ingenic/qi_lb60.dts13
-rw-r--r--dts/src/mips/mti/sead3.dts24
-rw-r--r--dts/src/powerpc/ac14xx.dts2
-rw-r--r--dts/src/powerpc/digsy_mtc.dts2
-rw-r--r--dts/src/powerpc/fsl/b4qds.dtsi8
-rw-r--r--dts/src/powerpc/fsl/c293pcie.dts2
-rw-r--r--dts/src/powerpc/fsl/kmcent2.dts4
-rw-r--r--dts/src/powerpc/fsl/p1010rdb.dtsi2
-rw-r--r--dts/src/powerpc/fsl/p1023rdb.dts2
-rw-r--r--dts/src/powerpc/fsl/p2041rdb.dts4
-rw-r--r--dts/src/powerpc/fsl/p3041ds.dts4
-rw-r--r--dts/src/powerpc/fsl/p4080ds.dts4
-rw-r--r--dts/src/powerpc/fsl/p5020ds.dts4
-rw-r--r--dts/src/powerpc/fsl/p5040ds.dts4
-rw-r--r--dts/src/powerpc/fsl/t208xqds.dtsi8
-rw-r--r--dts/src/powerpc/fsl/t4240qds.dts12
-rw-r--r--dts/src/powerpc/fsl/t4240rdb.dts6
-rw-r--r--dts/src/powerpc/fsp2.dts608
-rw-r--r--dts/src/powerpc/mpc5121ads.dts4
-rw-r--r--dts/src/powerpc/mpc8308_p1m.dts2
-rw-r--r--dts/src/powerpc/mpc8349emitx.dts4
-rw-r--r--dts/src/powerpc/mpc8377_rdb.dts2
-rw-r--r--dts/src/powerpc/mpc8377_wlan.dts2
-rw-r--r--dts/src/powerpc/mpc8378_rdb.dts2
-rw-r--r--dts/src/powerpc/mpc8379_rdb.dts2
-rw-r--r--dts/src/powerpc/pcm030.dts2
-rw-r--r--dts/src/powerpc/pcm032.dts2
-rw-r--r--dts/src/powerpc/pdm360ng.dts2
-rw-r--r--dts/src/powerpc/sequoia.dts2
-rw-r--r--dts/src/powerpc/warp.dts2
871 files changed, 30978 insertions, 7085 deletions
diff --git a/dts/Bindings/arm/actions.txt b/dts/Bindings/arm/actions.txt
new file mode 100644
index 0000000000..3bc7ea5755
--- /dev/null
+++ b/dts/Bindings/arm/actions.txt
@@ -0,0 +1,39 @@
+Actions Semi platforms device tree bindings
+-------------------------------------------
+
+
+S500 SoC
+========
+
+Required root node properties:
+
+ - compatible : must contain "actions,s500"
+
+
+Modules:
+
+Root node property compatible must contain, depending on module:
+
+ - LeMaker Guitar: "lemaker,guitar"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
+
+
+S900 SoC
+========
+
+Required root node properties:
+
+- compatible : must contain "actions,s900"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index bfd5b55847..0fff40a633 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -29,26 +29,35 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
-Board compatible values:
+Board compatible values (alphabetically, grouped by SoC):
+
- "geniatech,atv1200" (Meson6)
+
- "minix,neo-x8" (Meson8)
- - "tronfy,mxq" (Meson8b)
+
- "hardkernel,odroid-c1" (Meson8b)
+ - "tronfy,mxq" (Meson8b)
+
+ - "amlogic,p200" (Meson gxbb)
+ - "amlogic,p201" (Meson gxbb)
+ - "friendlyarm,nanopi-k2" (Meson gxbb)
+ - "hardkernel,odroid-c2" (Meson gxbb)
+ - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
- - "hardkernel,odroid-c2" (Meson gxbb)
- - "amlogic,p200" (Meson gxbb)
- - "amlogic,p201" (Meson gxbb)
- "wetek,hub" (Meson gxbb)
- "wetek,play2" (Meson gxbb)
+
- "amlogic,p212" (Meson gxl s905x)
+ - "hwacom,amazetv" (Meson gxl s905x)
- "khadas,vim" (Meson gxl s905x)
+ - "libretech,cc" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- - "hwacom,amazetv" (Meson gxl s905x)
+
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- - "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
+ - "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 799af90dd7..91cb8e4f2a 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -41,6 +41,36 @@ compatible: must be one of:
- "atmel,sama5d43"
- "atmel,sama5d44"
+ * "atmel,samv7" for MCUs using a Cortex-M7, shall be extended with the specific
+ SoC family:
+ o "atmel,sams70" shall be extended with the specific MCU compatible:
+ - "atmel,sams70j19"
+ - "atmel,sams70j20"
+ - "atmel,sams70j21"
+ - "atmel,sams70n19"
+ - "atmel,sams70n20"
+ - "atmel,sams70n21"
+ - "atmel,sams70q19"
+ - "atmel,sams70q20"
+ - "atmel,sams70q21"
+ o "atmel,samv70" shall be extended with the specific MCU compatible:
+ - "atmel,samv70j19"
+ - "atmel,samv70j20"
+ - "atmel,samv70n19"
+ - "atmel,samv70n20"
+ - "atmel,samv70q19"
+ - "atmel,samv70q20"
+ o "atmel,samv71" shall be extended with the specific MCU compatible:
+ - "atmel,samv71j19"
+ - "atmel,samv71j20"
+ - "atmel,samv71j21"
+ - "atmel,samv71n19"
+ - "atmel,samv71n20"
+ - "atmel,samv71n21"
+ - "atmel,samv71q19"
+ - "atmel,samv71q20"
+ - "atmel,samv71q21"
+
Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid"
- reg : Should contain registers location and length
diff --git a/dts/Bindings/arm/bcm/brcm,stingray.txt b/dts/Bindings/arm/bcm/brcm,stingray.txt
new file mode 100644
index 0000000000..23a02178dd
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,stingray.txt
@@ -0,0 +1,12 @@
+Broadcom Stingray device tree bindings
+------------------------------------------------
+
+Boards with Stingray shall have the following properties:
+
+Required root node property:
+
+Stingray Combo SVK board
+compatible = "brcm,bcm958742k", "brcm,stingray";
+
+Stingray SST100 board
+compatible = "brcm,bcm958742t", "brcm,stingray";
diff --git a/dts/Bindings/arm/cci.txt b/dts/Bindings/arm/cci.txt
index 0f2153e8fa..9600761f2d 100644
--- a/dts/Bindings/arm/cci.txt
+++ b/dts/Bindings/arm/cci.txt
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
-Bindings for the CCI node follow the ePAPR standard, available from:
-
-www.power.org/documentation/epapr-version-1-1/
-
-with the addition of the bindings described in this document which are
-specific to ARM.
-
* CCI interconnect node
Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM.
as a tuple of cells, containing child address,
parent address and the size of the region in the
child address space.
- Definition: A standard property. Follow rules in the ePAPR for
- hierarchical bus addressing. CCI interfaces
- addresses refer to the parent node addressing
- scheme to declare their register bases.
+ Definition: A standard property. Follow rules in the Devicetree
+ Specification for hierarchical bus addressing. CCI
+ interfaces addresses refer to the parent node
+ addressing scheme to declare their register bases.
CCI interconnect node can define the following child nodes:
diff --git a/dts/Bindings/arm/ccn.txt b/dts/Bindings/arm/ccn.txt
index b100d3847d..29801456c9 100644
--- a/dts/Bindings/arm/ccn.txt
+++ b/dts/Bindings/arm/ccn.txt
@@ -3,6 +3,7 @@
Required properties:
- compatible: (standard compatible string) should be one of:
+ "arm,ccn-502"
"arm,ccn-504"
"arm,ccn-508"
diff --git a/dts/Bindings/arm/coresight-cpu-debug.txt b/dts/Bindings/arm/coresight-cpu-debug.txt
new file mode 100644
index 0000000000..298291211e
--- /dev/null
+++ b/dts/Bindings/arm/coresight-cpu-debug.txt
@@ -0,0 +1,49 @@
+* CoreSight CPU Debug Component:
+
+CoreSight CPU debug component are compliant with the ARMv8 architecture
+reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+external debug module is mainly used for two modes: self-hosted debug and
+external debug, and it can be accessed from mmio region from Coresight
+and eventually the debug module connects with CPU for debugging. And the
+debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc;
+usually every CPU has one dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be "arm,coresight-cpu-debug"; supplemented with
+ "arm,primecell" since this driver is using the AMBA bus
+ interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+ using the AMBA framework, the name of the clock providing
+ the interconnect should be "apb_pclk" and the clock is
+ mandatory. The interface between the debug logic and the
+ processor core is clocked by the internal CPU clock, so it
+ is enabled with CPU clock by default.
+
+- cpu : the CPU phandle the debug module is affined to. When omitted
+ the module is considered to belong to CPU0.
+
+Optional properties:
+
+- power-domains: a phandle to the debug power domain. We use "power-domains"
+ binding to turn on the debug logic if it has own dedicated
+ power domain and if necessary to use "cpuidle.off=1" or
+ "nohlt" in the kernel command line or sysfs node to
+ constrain idle states to ensure registers in the CPU power
+ domain are accessible.
+
+Example:
+
+ debug@f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 1030f5f502..a44253cad2 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
-Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+Bindings for CPU nodes follow the Devicetree Specification, available from:
-https://www.power.org/documentation/epapr-version-1-1/
+https://www.devicetree.org/specifications/
with updates for 32-bit and 64-bit ARM systems provided in this document.
@@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in this document.
Convention used in this document
================================
-This document follows the conventions described in the ePAPR v1.1, with
-the addition:
+This document follows the conventions described in the Devicetree
+Specification, with the addition:
- square brackets define bitfields, eg reg[7:0] value of the bitfield in
the reg property contained in bits 7 down to 0
@@ -26,8 +26,9 @@ the addition:
cpus and cpu node bindings definition
=====================================
-The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
-nodes to be present and contain the properties described below.
+The ARM architecture, in accordance with the Devicetree Specification,
+requires the cpus and cpu nodes to be present and contain the properties
+described below.
- cpus node
@@ -193,6 +194,7 @@ nodes to be present and contain the properties described below.
"spin-table"
# On ARM 32-bit systems this property is optional and
can be one of:
+ "actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
@@ -249,7 +251,7 @@ nodes to be present and contain the properties described below.
Usage: Optional
Value type: <u32>
Definition:
- # u32 value representing CPU capacity [3] in
+ # u32 value representing CPU capacity [4] in
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
@@ -476,5 +478,5 @@ cpus {
[2] arm/msm/qcom,kpss-acc.txt
[3] ARM Linux kernel documentation - idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
-[3] ARM Linux kernel documentation - cpu capacity bindings
+[4] ARM Linux kernel documentation - cpu capacity bindings
Documentation/devicetree/bindings/arm/cpu-capacity.txt
diff --git a/dts/Bindings/arm/gemini.txt b/dts/Bindings/arm/gemini.txt
index 0041eb0311..55bf7ce96c 100644
--- a/dts/Bindings/arm/gemini.txt
+++ b/dts/Bindings/arm/gemini.txt
@@ -24,6 +24,19 @@ Required nodes:
global control registers, with the compatible string
"cortina,gemini-syscon", "syscon";
+ Required properties on the syscon:
+ - reg: syscon register location and size.
+ - #clock-cells: should be set to <1> - the system controller is also a
+ clock provider.
+ - #reset-cells: should be set to <1> - the system controller is also a
+ reset line provider.
+
+ The clock sources have shorthand defines in the include file:
+ <dt-bindings/clock/cortina,gemini-clock.h>
+
+ The reset lines have shorthand defines in the include file:
+ <dt-bindings/reset/cortina,gemini-reset.h>
+
- timer: the soc bus node must have a timer node pointing to the SoC timer
block, with the compatible string "cortina,gemini-timer"
See: clocksource/cortina,gemini-timer.txt
@@ -56,12 +69,15 @@ Example:
syscon: syscon@40000000 {
compatible = "cortina,gemini-syscon", "syscon";
reg = <0x40000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
- clock-frequency = <48000000>;
+ resets = <&syscon GEMINI_RESET_UART>;
+ clocks = <&syscon GEMINI_CLK_UART>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
};
@@ -73,12 +89,18 @@ Example:
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
+ resets = <&syscon GEMINI_RESET_TIMER>;
+ /* APB clock or RTC clock */
+ clocks = <&syscon GEMINI_CLK_APB>,
+ <&syscon GEMINI_CLK_RTC>;
+ clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
intcon: interrupt-controller@48000000 {
compatible = "cortina,gemini-interrupt-controller";
reg = <0x48000000 0x1000>;
+ resets = <&syscon GEMINI_RESET_INTCON0>;
interrupt-controller;
#interrupt-cells = <2>;
};
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index 2e73215206..7111fbc82a 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -4,6 +4,10 @@ Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
+HiKey960 Board
+Required root node properties:
+ - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index b8e41c148a..7a591333f2 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -695,5 +695,5 @@ cpus {
[4] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp
-[5] ePAPR standard
- https://www.power.org/documentation/epapr-version-1-1/
+[5] Devicetree Specification
+ https://www.devicetree.org/specifications/
diff --git a/dts/Bindings/arm/keystone/keystone.txt b/dts/Bindings/arm/keystone/keystone.txt
index 48f6703a28..f310bad044 100644
--- a/dts/Bindings/arm/keystone/keystone.txt
+++ b/dts/Bindings/arm/keystone/keystone.txt
@@ -37,3 +37,6 @@ Boards:
- K2G EVM
compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
+
+- K2G Industrial Communication Engine EVM
+ compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone"
diff --git a/dts/Bindings/arm/l2c2x0.txt b/dts/Bindings/arm/l2c2x0.txt
index d9650c1788..fbe6cb21f4 100644
--- a/dts/Bindings/arm/l2c2x0.txt
+++ b/dts/Bindings/arm/l2c2x0.txt
@@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
PL310 and variants) based level 2 cache controller. All these various implementations
of the L2 cache controller have compatible programming models (Note 1).
Some of the properties that are just prefixed "cache-*" are taken from section
-3.7.3 of the ePAPR v1.1 specification which can be found at:
-https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
The ARM L2 cache representation in the device tree should be done as follows:
diff --git a/dts/Bindings/arm/marvell/ap806-system-controller.txt b/dts/Bindings/arm/marvell/ap806-system-controller.txt
index 8968371d84..0b887440e0 100644
--- a/dts/Bindings/arm/marvell/ap806-system-controller.txt
+++ b/dts/Bindings/arm/marvell/ap806-system-controller.txt
@@ -7,6 +7,14 @@ registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
this system controller.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the AP806 system controller
+
+Clocks:
+-------
+
+
The Device Tree node representing the AP806 system controller provides
a number of clocks:
@@ -17,19 +25,76 @@ a number of clocks:
Required properties:
- - compatible: must be:
- "marvell,ap806-system-controller", "syscon"
- - reg: register area of the AP806 system controller
+ - compatible: must be: "marvell,ap806-clock"
- #clock-cells: must be set to 1
- - clock-output-names: must be defined to:
- "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
+
+Pinctrl:
+--------
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+- compatible must be "marvell,ap806-pinctrl",
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, sdio(clk), spi0(clk)
+mpp1 1 gpio, sdio(cmd), spi0(miso)
+mpp2 2 gpio, sdio(d0), spi0(mosi)
+mpp3 3 gpio, sdio(d1), spi0(cs0n)
+mpp4 4 gpio, sdio(d2), i2c0(sda)
+mpp5 5 gpio, sdio(d3), i2c0(sdk)
+mpp6 6 gpio, sdio(ds)
+mpp7 7 gpio, sdio(d4), uart1(rxd)
+mpp8 8 gpio, sdio(d5), uart1(txd)
+mpp9 9 gpio, sdio(d6), spi0(cs1n)
+mpp10 10 gpio, sdio(d7)
+mpp11 11 gpio, uart0(txd)
+mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
+mpp13 13 gpio
+mpp14 14 gpio
+mpp15 15 gpio
+mpp16 16 gpio
+mpp17 17 gpio
+mpp18 18 gpio
+mpp19 19 gpio, uart0(rxd), sdio(pw_off)
+
+GPIO:
+-----
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
Example:
+ap_syscon: system-controller@6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x1000>;
- syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller", "syscon";
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
#clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
- "ap-fixed", "ap-mss";
- reg = <0x6f4000 0x1000>;
};
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+ };
+
+ ap_gpio: gpio {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <19>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 19>;
+ };
+};
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
index 07dbb35818..171d02cade 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -7,6 +7,13 @@ Controller 0 and System Controller 1. This Device Tree binding allows
to describe the first system controller, which provides registers to
configure various aspects of the SoC.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the CP110 system controller 0
+
+Clocks:
+-------
+
The Device Tree node representing this System Controller 0 provides a
number of clocks:
@@ -27,6 +34,7 @@ The following clocks are available:
- 0 2 EIP
- 0 3 Core
- 0 4 NAND core
+ - 0 5 SDIO core
- Gatable clocks
- 1 0 Audio
- 1 1 Comm Unit
@@ -56,28 +64,126 @@ The following clocks are available:
Required properties:
- compatible: must be:
- "marvell,cp110-system-controller0", "syscon";
- - reg: register area of the CP110 system controller 0
+ "marvell,cp110-clock"
- #clock-cells: must be set to 2
- - core-clock-output-names must be set to:
- "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
- - gate-clock-output-names must be set to:
- "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+
+Pinctrl:
+--------
+
+For common binding part and usage, refer to the file
+Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-7k-pinctrl",
+ "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
+ depending on the specific variant of the SoC being used.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
+mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
+mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
+mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio)
+mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
+mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
+mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
+mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
+mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
+mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
+mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act)
+mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act)
+mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
+mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso)
+mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
+mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
+mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk)
+mpp17 17 gpio, dev(ad5), ge0(txd3)
+mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
+mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
+mpp20 20 gpio, dev(ad2), ge0(txd0)
+mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
+mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
+mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
+mpp24 24 gpio, dev(a0), au(i2slrclk)
+mpp25 25 gpio, dev(oen), au(i2sdo_spdifo)
+mpp26 26 gpio, dev(wen0), au(i2sbclk)
+mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
+mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
+mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
+mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk)
+mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
+mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
+mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
+mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2
+mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3
+mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
+mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp)
+mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp)
+mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0
+mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1
+mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp)
+mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4
+mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp)
+mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp)
+mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn)
+mpp46 46 gpio, ge1(txd1), uart1(rts)
+mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc)
+mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp)
+mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp)
+mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11)
+mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
+mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
+mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
+mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
+mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
+mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
+mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
+mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)
+mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1)
+mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2)
+mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
+mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)
+
+GPIO:
+-----
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
Example:
- cpm_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0", "syscon";
- reg = <0x440000 0x1000>;
+cpm_syscon0: system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x1000>;
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
#clock-cells = <2>;
- core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
- gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
+
+ cpm_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cpm-pinctrl";
+ };
+
+ cpm_gpio1: gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ status = "disabled";
+ };
+
+};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index c860b245d8..da7bd138e6 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -12,6 +12,8 @@ compatible: Must contain one of
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6795"
+ "mediatek,mt6797"
+ "mediatek,mt7622"
"mediatek,mt7623"
"mediatek,mt8127"
"mediatek,mt8135"
@@ -38,6 +40,12 @@ Supported boards:
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+- Evaluation board for MT6797(Helio X20):
+ Required root node properties:
+ - compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+- Reference board variant 1 for MT7622:
+ Required root node properties:
+ - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Evaluation board for MT7623:
Required root node properties:
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
diff --git a/dts/Bindings/arm/realtek.txt b/dts/Bindings/arm/realtek.txt
new file mode 100644
index 0000000000..13d755787b
--- /dev/null
+++ b/dts/Bindings/arm/realtek.txt
@@ -0,0 +1,20 @@
+Realtek platforms device tree bindings
+--------------------------------------
+
+
+RTD1295 SoC
+===========
+
+Required root node properties:
+
+ - compatible : must contain "realtek,rtd1295"
+
+
+Root node property compatible must contain, depending on board:
+
+ - Zidoo X9S: "zidoo,x9s"
+
+
+Example:
+
+ compatible = "zidoo,x9s", "realtek,rtd1295";
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index c965d99e86..11c0ac4a2d 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -42,6 +42,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
+- Firefly Firefly-RK3399 board:
+ Required root node properties:
+ - compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -138,9 +142,9 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
-- Rockchip RK1108 Evaluation board
+- Rockchip RV1108 Evaluation board
Required root node properties:
- - compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
+ - compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
- Rockchip RK3368 evb:
Required root node properties:
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 170fe0562c..1a671e3298 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -55,12 +55,19 @@ Boards:
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
+ - GR-Peach (X28A-M01-E/F)
+ compatible = "renesas,gr-peach", "renesas,r7s72100"
- Gose (RTP0RC7793SEB00010S)
compatible = "renesas,gose", "renesas,r8a7793"
- - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
+ - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
+ H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
+ - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
+ compatible = "iwave,g20m", "renesas,r8a7743"
- Koelsch (RTP0RC7791SEB00010S)
compatible = "renesas,koelsch", "renesas,r8a7791"
- Kyoto Microcomputer Co. KZM-A9-Dual
@@ -69,7 +76,7 @@ Boards:
compatible = "renesas,kzm9g", "renesas,sh73a0"
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
+ - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
compatible = "renesas,m3ulcb", "renesas,r8a7796";
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
@@ -81,6 +88,8 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795";
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796";
+ - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
+ compatible = "renesas,salvator-xs", "renesas,r8a7795";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
diff --git a/dts/Bindings/arm/tegra.txt b/dts/Bindings/arm/tegra.txt
index b5a4342c1d..7f1411bbab 100644
--- a/dts/Bindings/arm/tegra.txt
+++ b/dts/Bindings/arm/tegra.txt
@@ -29,7 +29,6 @@ board-specific compatible values:
nvidia,harmony
nvidia,seaboard
nvidia,ventana
- nvidia,whistler
toradex,apalis_t30
toradex,apalis_t30-eval
toradex,apalis-tk1
diff --git a/dts/Bindings/arm/topology.txt b/dts/Bindings/arm/topology.txt
index 1061faf5f6..de9eb04866 100644
--- a/dts/Bindings/arm/topology.txt
+++ b/dts/Bindings/arm/topology.txt
@@ -29,9 +29,9 @@ corresponding to the system hierarchy; syntactically they are defined as device
tree nodes.
The remainder of this document provides the topology bindings for ARM, based
-on the ePAPR standard, available from:
+on the Devicetree Specification, available from:
-http://www.power.org/documentation/epapr-version-1-1/
+https://www.devicetree.org/specifications/
If not stated otherwise, whenever a reference to a cpu node phandle is made its
value must point to a cpu node compliant with the cpu node bindings as
diff --git a/dts/Bindings/ata/ahci-fsl-qoriq.txt b/dts/Bindings/ata/ahci-fsl-qoriq.txt
index fc33ca01e9..7c3ca0e13d 100644
--- a/dts/Bindings/ata/ahci-fsl-qoriq.txt
+++ b/dts/Bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
- chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
+ chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
diff --git a/dts/Bindings/ata/cortina,gemini-sata-bridge.txt b/dts/Bindings/ata/cortina,gemini-sata-bridge.txt
new file mode 100644
index 0000000000..1c3d3cc700
--- /dev/null
+++ b/dts/Bindings/ata/cortina,gemini-sata-bridge.txt
@@ -0,0 +1,55 @@
+* Cortina Systems Gemini SATA Bridge
+
+The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
+takes two Faraday Technology FTIDE010 PATA controllers and bridges
+them in different configurations to two SATA ports.
+
+Required properties:
+- compatible: should be
+ "cortina,gemini-sata-bridge"
+- reg: registers and size for the block
+- resets: phandles to the reset lines for both SATA bridges
+- reset-names: must be "sata0", "sata1"
+- clocks: phandles to the compulsory peripheral clocks
+- clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
+- syscon: a phandle to the global Gemini system controller
+- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for
+ the ATA controller and SATA bridges. Values 0..3:
+ Mode 0: ata0 master <-> sata0
+ ata1 master <-> sata1
+ ata0 slave interface brought out on IDE pads
+ Mode 1: ata0 master <-> sata0
+ ata1 master <-> sata1
+ ata1 slave interface brought out on IDE pads
+ Mode 2: ata1 master <-> sata1
+ ata1 slave <-> sata0
+ ata0 master and slave interfaces brought out
+ on IDE pads
+ Mode 3: ata0 master <-> sata0
+ ata0 slave <-> sata1
+ ata1 master and slave interfaces brought out
+ on IDE pads
+
+Optional boolean properties:
+- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection.
+ The muxmode setting decides whether ATA0 or ATA1 is brought out,
+ and whether master, slave or both interfaces get brought out.
+- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge
+ inside the Gemnini SoC. The Muxmode decides what PATA blocks will
+ be muxed out and how.
+
+Example:
+
+sata: sata@46000000 {
+ compatible = "cortina,gemini-sata-bridge";
+ reg = <0x46000000 0x100>;
+ resets = <&rcon 26>, <&rcon 27>;
+ reset-names = "sata0", "sata1";
+ clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
+ <&gcc GEMINI_CLK_GATE_SATA1>;
+ clock-names = "SATA0_PCLK", "SATA1_PCLK";
+ syscon = <&syscon>;
+ cortina,gemini-ata-muxmode = <3>;
+ cortina,gemini-enable-ide-pins;
+ cortina,gemini-enable-sata-bridge;
+};
diff --git a/dts/Bindings/ata/faraday,ftide010.txt b/dts/Bindings/ata/faraday,ftide010.txt
new file mode 100644
index 0000000000..a0c64a2910
--- /dev/null
+++ b/dts/Bindings/ata/faraday,ftide010.txt
@@ -0,0 +1,38 @@
+* Faraday Technology FTIDE010 PATA controller
+
+This controller is the first Faraday IDE interface block, used in the
+StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini
+platform. The controller can do PIO modes 0 through 4, Multi-word DMA
+(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6.
+
+On the Gemini platform, this PATA block is accompanied by a PATA to
+SATA bridge in order to support SATA. This is why a phandle to that
+controller is compulsory on that platform.
+
+The timing properties are unique per-SoC, not per-board.
+
+Required properties:
+- compatible: should be one of
+ "cortina,gemini-pata", "faraday,ftide010"
+ "faraday,ftide010"
+- interrupts: interrupt for the block
+- reg: registers and size for the block
+
+Optional properties:
+- clocks: a SoC clock running the peripheral.
+- clock-names: should be set to "PCLK" for the peripheral clock.
+
+Required properties for "cortina,gemini-pata" compatible:
+- sata: a phande to the Gemini PATA to SATA bridge, see
+ cortina,gemini-sata-bridge.txt for details.
+
+Example:
+
+ata@63000000 {
+ compatible = "cortina,gemini-pata", "faraday,ftide010";
+ reg = <0x63000000 0x100>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GEMINI_CLK_GATE_IDE>;
+ clock-names = "PCLK";
+ sata = <&sata>;
+};
diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt
index 1eceefb20f..8a6c3c2e58 100644
--- a/dts/Bindings/bus/brcm,gisb-arb.txt
+++ b/dts/Bindings/bus/brcm,gisb-arb.txt
@@ -3,7 +3,8 @@ Broadcom GISB bus Arbiter controller
Required properties:
- compatible:
- "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
+ "brcm,bcm7278-gisb-arb" for V7 28nm chips
+ "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
"brcm,bcm7435-gisb-arb" for newer 40nm chips
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
"brcm,bcm7038-gisb-arb" for 130nm chips
diff --git a/dts/Bindings/bus/simple-pm-bus.txt b/dts/Bindings/bus/simple-pm-bus.txt
index d032237512..6f15037131 100644
--- a/dts/Bindings/bus/simple-pm-bus.txt
+++ b/dts/Bindings/bus/simple-pm-bus.txt
@@ -10,7 +10,7 @@ enabled for child devices connected to the bus (either on-SoC or externally)
to function.
While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
-in ePAPR, it is not an extension of "simple-bus".
+in the Devicetree Specification, it is not an extension of "simple-bus".
Required properties:
diff --git a/dts/Bindings/chosen.txt b/dts/Bindings/chosen.txt
index b5e39af4dd..dee3f5d9df 100644
--- a/dts/Bindings/chosen.txt
+++ b/dts/Bindings/chosen.txt
@@ -10,7 +10,8 @@ stdout-path property
--------------------
Device trees may specify the device to be used for boot console output
-with a stdout-path property under /chosen, as described in ePAPR, e.g.
+with a stdout-path property under /chosen, as described in the Devicetree
+Specification, e.g.
/ {
chosen {
diff --git a/dts/Bindings/clock/amlogic,meson8b-clkc.txt b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
index 2b7b3fa588..606da38c09 100644
--- a/dts/Bindings/clock/amlogic,meson8b-clkc.txt
+++ b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.
Required Properties:
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:
+ - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+ - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+ - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
- reg: it must be composed by two tuples:
0) physical base address of the xtal register and length of memory
mapped region.
diff --git a/dts/Bindings/clock/brcm,iproc-clocks.txt b/dts/Bindings/clock/brcm,iproc-clocks.txt
index 6f66e9aa35..f2c5f0e4a3 100644
--- a/dts/Bindings/clock/brcm,iproc-clocks.txt
+++ b/dts/Bindings/clock/brcm,iproc-clocks.txt
@@ -219,3 +219,79 @@ BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
+
+Stingray
+-----------
+PLL and leaf clock compatible strings for Stingray are:
+ "brcm,sr-genpll0"
+ "brcm,sr-genpll1"
+ "brcm,sr-genpll2"
+ "brcm,sr-genpll3"
+ "brcm,sr-genpll4"
+ "brcm,sr-genpll5"
+ "brcm,sr-genpll6"
+
+ "brcm,sr-lcpll0"
+ "brcm,sr-lcpll1"
+ "brcm,sr-lcpll-pcie"
+
+
+The following table defines the set of PLL/clock index and ID for Stingray.
+These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-sr.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+ crmu_ref25m crystal N/A N/A
+
+ genpll0 crystal 0 BCM_SR_GENPLL0
+ clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
+ clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
+ clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
+ clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
+ clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
+ clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
+
+ genpll1 crystal 0 BCM_SR_GENPLL1
+ clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
+ clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
+
+ genpll2 crystal 0 BCM_SR_GENPLL2
+ clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
+ clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
+ clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
+ clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
+ clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
+
+ genpll3 crystal 0 BCM_SR_GENPLL3
+ clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
+ clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
+
+ genpll4 crystal 0 BCM_SR_GENPLL4
+ ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
+ clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
+ noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
+ clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
+ clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
+
+
+ genpll5 crystal 0 BCM_SR_GENPLL5
+ fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
+ crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
+ raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
+
+ genpll6 crystal 0 BCM_SR_GENPLL6
+ 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
+
+ lcpll0 crystal 0 BCM_SR_LCPLL0
+ clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
+ clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
+ clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
+ sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
+
+ lcpll1 crystal 0 BCM_SR_LCPLL1
+ wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
+
+ lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
+ pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/dts/Bindings/clock/hi6220-clock.txt b/dts/Bindings/clock/hi6220-clock.txt
index e4d5feaebc..ef3deb7b86 100644
--- a/dts/Bindings/clock/hi6220-clock.txt
+++ b/dts/Bindings/clock/hi6220-clock.txt
@@ -11,6 +11,7 @@ Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
+ - "hisilicon,hi6220-acpu-sctrl"
- "hisilicon,hi6220-aoctrl"
- "hisilicon,hi6220-sysctrl"
- "hisilicon,hi6220-mediactrl"
diff --git a/dts/Bindings/clock/img,boston-clock.txt b/dts/Bindings/clock/img,boston-clock.txt
new file mode 100644
index 0000000000..7bc5e9ffb6
--- /dev/null
+++ b/dts/Bindings/clock/img,boston-clock.txt
@@ -0,0 +1,31 @@
+Binding for Imagination Technologies MIPS Boston clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The device node must be a child node of the syscon node corresponding to the
+Boston system's platform registers.
+
+Required properties:
+- compatible : Should be "img,boston-clock".
+- #clock-cells : Should be set to 1.
+ Values available for clock consumers can be found in the header file:
+ <dt-bindings/clock/boston-clock.h>
+
+Example:
+
+ system-controller@17ffd000 {
+ compatible = "img,boston-platform-regs", "syscon";
+ reg = <0x17ffd000 0x1000>;
+
+ clk_boston: clock {
+ compatible = "img,boston-clock";
+ #clock-cells = <1>;
+ };
+ };
+
+ uart0: uart@17ffe000 {
+ /* ... */
+ clocks = <&clk_boston BOSTON_CLK_SYS>;
+ };
diff --git a/dts/Bindings/clock/qcom,gcc.txt b/dts/Bindings/clock/qcom,gcc.txt
index 5b4dfc1ea5..551d03be96 100644
--- a/dts/Bindings/clock/qcom,gcc.txt
+++ b/dts/Bindings/clock/qcom,gcc.txt
@@ -8,6 +8,7 @@ Required properties :
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-ipq4019"
+ "qcom,gcc-ipq8074"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/dts/Bindings/clock/qoriq-clock.txt b/dts/Bindings/clock/qoriq-clock.txt
index 6ed469c66b..6498e1fdbb 100644
--- a/dts/Bindings/clock/qoriq-clock.txt
+++ b/dts/Bindings/clock/qoriq-clock.txt
@@ -57,6 +57,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -73,6 +78,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index f4f944d813..0cd894f987 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,11 @@ Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+ - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
+ - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
+ - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
+ - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
+ - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
@@ -24,9 +29,10 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
+ - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+ r8a7795, r8a7796)
- "extalr" (r8a7795, r8a7796)
- - "usb_extal" (r8a7743, r8a7745)
+ - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/dts/Bindings/clock/rockchip,rk3128-cru.txt b/dts/Bindings/clock/rockchip,rk3128-cru.txt
new file mode 100644
index 0000000000..455a9a00a6
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3128-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3128 Clock and Reset Unit
+
+The RK3128 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3128-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+ cru: cru@20000000 {
+ compatible = "rockchip,rk3128-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart2: serial@20068000 {
+ compatible = "rockchip,serial";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "sclk_uart", "pclk_uart";
+ };
diff --git a/dts/Bindings/clock/sun8i-de2.txt b/dts/Bindings/clock/sun8i-de2.txt
new file mode 100644
index 0000000000..631d27cd89
--- /dev/null
+++ b/dts/Bindings/clock/sun8i-de2.txt
@@ -0,0 +1,31 @@
+Allwinner Display Engine 2.0 Clock Control Binding
+--------------------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+ - "allwinner,sun8i-a83t-de2-clk"
+ - "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-h5-de2-clk"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+ - "mod": the display engine module clock
+ - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de2_clocks: clock@1000000 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index f465647a4d..df9fad58fa 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -6,6 +6,8 @@ Required properties :
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
+ - "allwinner,sun8i-a83t-ccu"
+ - "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
- "allwinner,sun8i-v3s-ccu"
@@ -18,11 +20,12 @@ Required properties :
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
- "hosc": the high frequency oscillator (usually at 24MHz)
- "losc": the low frequency oscillator (usually at 32kHz)
+ On the A83T, this is the internal 16MHz oscillator divided by 512
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1
-For the PRCM CCUs on H3/A64, two more clocks are needed:
+For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/dts/Bindings/clock/ti,sci-clk.txt b/dts/Bindings/clock/ti,sci-clk.txt
new file mode 100644
index 0000000000..1e884c40ab
--- /dev/null
+++ b/dts/Bindings/clock/ti,sci-clk.txt
@@ -0,0 +1,37 @@
+Texas Instruments TI-SCI Clocks
+===============================
+
+All clocks on Texas Instruments' SoCs that contain a System Controller,
+are only controlled by this entity. Communication between a host processor
+running an OS and the System Controller happens through a protocol known
+as TI-SCI[1]. This clock implementation plugs into the common clock
+framework and makes use of the TI-SCI protocol on clock API requests.
+
+[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
+
+Required properties:
+-------------------
+- compatible: Must be "ti,k2g-sci-clk"
+- #clock-cells: Shall be 2.
+ In clock consumers, this cell represents the device ID and clock ID
+ exposed by the PM firmware. The assignments can be found in the header
+ files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
+ <dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
+ is the SoC involved, for example 'k2g'.
+
+Examples:
+--------
+
+pmmc: pmmc {
+ compatible = "ti,k2g-sci";
+
+ k2g_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+};
+
+uart0: serial@2530c00 {
+ compatible = "ns16550a";
+ clocks = <&k2g_clks 0x2c 0>;
+};
diff --git a/dts/Bindings/clock/ti-clkctrl.txt b/dts/Bindings/clock/ti-clkctrl.txt
new file mode 100644
index 0000000000..48ee6991f2
--- /dev/null
+++ b/dts/Bindings/clock/ti-clkctrl.txt
@@ -0,0 +1,56 @@
+Texas Instruments clkctrl clock binding
+
+Texas Instruments SoCs can have a clkctrl clock controller for each
+interconnect target module. The clkctrl clock controller manages functional
+and interface clocks for each module. Each clkctrl controller can also
+gate one or more optional functional clocks for a module, and can have one
+or more clock muxes. There is a clkctrl clock controller typically for each
+interconnect target module on omap4 and later variants.
+
+The clock consumers can specify the index of the clkctrl clock using
+the hardware offset from the clkctrl instance register space. The optional
+clocks can be specified by clkctrl hardware offset and the index of the
+optional clock.
+
+For more information, please see the Linux clock framework binding at
+Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+Required properties :
+- compatible : shall be "ti,clkctrl"
+- #clock-cells : shall contain 2 with the first entry being the instance
+ offset from the clock domain base and the second being the
+ clock index
+
+Example: Clock controller node on omap 4430:
+
+&cm2 {
+ l4per: cm@1400 {
+ cm_l4per@0 {
+ cm_l4per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1b0>;
+ #clock-cells = <2>;
+ };
+ };
+ };
+};
+
+Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
+
+#define OMAP4_CLKCTRL_OFFSET 0x20
+#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
+#define MODULEMODE_HWCTRL 1
+#define MODULEMODE_SWCTRL 2
+
+#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
+...
+#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
+
+Example: Clock consumer node for GPIO2:
+
+&gpio2 {
+ clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
+ &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+};
diff --git a/dts/Bindings/common-properties.txt b/dts/Bindings/common-properties.txt
index 3193979b1d..697714f8d7 100644
--- a/dts/Bindings/common-properties.txt
+++ b/dts/Bindings/common-properties.txt
@@ -1,6 +1,6 @@
Common properties
-The ePAPR specification does not define any properties related to hardware
+The Devicetree Specification does not define any properties related to hardware
byteswapping, but endianness issues show up frequently in porting Linux to
different machine types. This document attempts to provide a consistent
way of handling byteswapping across drivers.
diff --git a/dts/Bindings/cpufreq/ti-cpufreq.txt b/dts/Bindings/cpufreq/ti-cpufreq.txt
index ba0e15ad5b..0c38e4b8fc 100644
--- a/dts/Bindings/cpufreq/ti-cpufreq.txt
+++ b/dts/Bindings/cpufreq/ti-cpufreq.txt
@@ -63,64 +63,64 @@ cpu0_opp_table: opp-table {
* because they can not be enabled simultaneously on a
* single SoC.
*/
- opp50@300000000 {
+ opp50-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0x06 0x0010>;
opp-suspend;
};
- opp100@275000000 {
+ opp100-275000000 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0x00FF>;
opp-suspend;
};
- opp100@300000000 {
+ opp100-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0020>;
opp-suspend;
};
- opp100@500000000 {
+ opp100-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0xFFFF>;
};
- opp100@600000000 {
+ opp100-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0040>;
};
- opp120@600000000 {
+ opp120-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x01 0xFFFF>;
};
- opp120@720000000 {
+ opp120-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x06 0x0080>;
};
- oppturbo@720000000 {
+ oppturbo-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x01 0xFFFF>;
};
- oppturbo@800000000 {
+ oppturbo-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x06 0x0100>;
};
- oppnitro@1000000000 {
+ oppnitro-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0x04 0x0200>;
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 10a425f451..7aef0eae58 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -118,8 +118,8 @@ PROPERTIES
Definition: A list of clock name strings in the same order as the
clocks property.
- Note: All other standard properties (see the ePAPR) are allowed
- but are optional.
+ Note: All other standard properties (see the Devicetree Specification)
+ are allowed but are optional.
EXAMPLE
diff --git a/dts/Bindings/crypto/fsl-sec6.txt b/dts/Bindings/crypto/fsl-sec6.txt
index baf8a3c1b4..73b0eb950b 100644
--- a/dts/Bindings/crypto/fsl-sec6.txt
+++ b/dts/Bindings/crypto/fsl-sec6.txt
@@ -55,8 +55,8 @@ PROPERTIES
triplet that includes the child address, parent address, &
length.
- Note: All other standard properties (see the ePAPR) are allowed
- but are optional.
+ Note: All other standard properties (see the Devicetree Specification)
+ are allowed but are optional.
EXAMPLE
crypto@a0000 {
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
new file mode 100644
index 0000000000..f69773f425
--- /dev/null
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -0,0 +1,29 @@
+Inside Secure SafeXcel cryptographic engine
+
+Required properties:
+- compatible: Should be "inside-secure,safexcel-eip197".
+- reg: Base physical address of the engine and length of memory mapped region.
+- interrupts: Interrupt numbers for the rings and engine.
+- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
+
+Optional properties:
+- clocks: Reference to the crypto engine clock.
+- dma-mask: The address mask limitation. Defaults to 64.
+
+Example:
+
+ crypto: crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197";
+ reg = <0x800000 0x200000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
+ "eip";
+ clocks = <&cpm_syscon0 1 26>;
+ dma-mask = <0xff 0xffffffff>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/crypto/mediatek-crypto.txt b/dts/Bindings/crypto/mediatek-crypto.txt
index c204725e58..450da3661c 100644
--- a/dts/Bindings/crypto/mediatek-crypto.txt
+++ b/dts/Bindings/crypto/mediatek-crypto.txt
@@ -6,8 +6,7 @@ Required properties:
- interrupts: Should contain the five crypto engines interrupts in numeric
order. These are global system and four descriptor rings.
- clocks: the clock used by the core
-- clock-names: the names of the clock listed in the clocks property. These are
- "ethif", "cryp"
+- clock-names: Must contain "cryp".
- power-domains: Must contain a reference to the PM domain.
@@ -20,8 +19,7 @@ Example:
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
- <&ethsys CLK_ETHSYS_CRYPTO>;
- clock-names = "ethif","cryp";
+ clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
+ clock-names = "cryp";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
};
diff --git a/dts/Bindings/display/brcm,bcm-vc4.txt b/dts/Bindings/display/brcm,bcm-vc4.txt
index ca02d3e4db..284e2b14cf 100644
--- a/dts/Bindings/display/brcm,bcm-vc4.txt
+++ b/dts/Bindings/display/brcm,bcm-vc4.txt
@@ -5,7 +5,7 @@ with HDMI output and the HVS (Hardware Video Scaler) for compositing
display planes.
Required properties for VC4:
-- compatible: Should be "brcm,bcm2835-vc4"
+- compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
Required properties for Pixel Valve:
- compatible: Should be one of "brcm,bcm2835-pixelvalve0",
@@ -54,11 +54,14 @@ Required properties for VEC:
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
Required properties for V3D:
-- compatible: Should be "brcm,bcm2835-v3d"
+- compatible: Should be "brcm,bcm2835-v3d" or "brcm,cygnus-v3d"
- reg: Physical base address and length of the V3D's registers
- interrupts: The interrupt number
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+Optional properties for V3D:
+- clocks: The clock the unit runs on
+
Required properties for DSI:
- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
- reg: Physical base address and length of the DSI block's registers
diff --git a/dts/Bindings/display/bridge/adi,adv7511.txt b/dts/Bindings/display/bridge/adi,adv7511.txt
index 00ea670b8c..06668bca7f 100644
--- a/dts/Bindings/display/bridge/adi,adv7511.txt
+++ b/dts/Bindings/display/bridge/adi,adv7511.txt
@@ -78,6 +78,7 @@ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
remote endpoint phandle should be a reference to a valid mipi_dsi_host device
node.
- Video port 1 for the HDMI output
+- Audio port 2 for the HDMI audio input
Example
@@ -112,5 +113,12 @@ Example
remote-endpoint = <&hdmi_connector_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
};
};
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
index f6b3f36d42..81b68580e1 100644
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -25,7 +25,8 @@ Required properties:
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
corresponding to the video input of the controller and one port numbered 1
- corresponding to its HDMI output. Each port shall have a single endpoint.
+ corresponding to its HDMI output, and one port numbered 2 corresponding to
+ sound input of the controller. Each port shall have a single endpoint.
Optional properties:
@@ -59,6 +60,12 @@ Example:
remote-endpoint = <&hdmi0_con>;
};
};
+ port@2 {
+ reg = <2>;
+ rcar_dw_hdmi0_sound_in: endpoint {
+ remote-endpoint = <&hdmi_sound_out>;
+ };
+ };
};
};
diff --git a/dts/Bindings/display/exynos/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
index c9fd7b3807..549c538b38 100644
--- a/dts/Bindings/display/exynos/exynos5433-decon.txt
+++ b/dts/Bindings/display/exynos/exynos5433-decon.txt
@@ -8,12 +8,13 @@ Required properties:
- compatible: value should be one of:
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
- reg: physical base address and length of the DECON registers set.
-- interrupts: should contain a list of all DECON IP block interrupts in the
- order: VSYNC, LCD_SYSTEM. The interrupt specifier format
- depends on the interrupt controller used.
-- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
- in the same order as they were listed in the interrupts
- property.
+- interrupt-names: should contain the interrupt names depending on mode of work:
+ video mode: "vsync",
+ command mode: "lcd_sys",
+ command mode with software trigger: "lcd_sys", "te".
+- interrupts or interrupts-extended: list of interrupt specifiers corresponding
+ to names privided in interrupt-names, as described in
+ interrupt-controller/interrupts.txt
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
diff --git a/dts/Bindings/display/panel/auo,p320hvn03.txt b/dts/Bindings/display/panel/auo,p320hvn03.txt
new file mode 100644
index 0000000000..59bb6cd8aa
--- /dev/null
+++ b/dts/Bindings/display/panel/auo,p320hvn03.txt
@@ -0,0 +1,8 @@
+AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,p320hvn03"
+- power-supply: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/display-timing.txt b/dts/Bindings/display/panel/display-timing.txt
index 81a75893d1..58fa3e4848 100644
--- a/dts/Bindings/display/panel/display-timing.txt
+++ b/dts/Bindings/display/panel/display-timing.txt
@@ -57,11 +57,11 @@ can be specified.
The parameters are defined as:
+----------+-------------------------------------+----------+-------+
- | | ↑ | | |
+ | | ^ | | |
| | |vback_porch | | |
- | | ↓ | | |
+ | | v | | |
+----------#######################################----------+-------+
- | # ↑ # | |
+ | # ^ # | |
| # | # | |
| hback # | # hfront | hsync |
| porch # | hactive # porch | len |
@@ -69,15 +69,15 @@ The parameters are defined as:
| # | # | |
| # |vactive # | |
| # | # | |
- | # ↓ # | |
+ | # v # | |
+----------#######################################----------+-------+
- | | ↑ | | |
+ | | ^ | | |
| | |vfront_porch | | |
- | | ↓ | | |
+ | | v | | |
+----------+-------------------------------------+----------+-------+
- | | ↑ | | |
+ | | ^ | | |
| | |vsync_len | | |
- | | ↓ | | |
+ | | v | | |
+----------+-------------------------------------+----------+-------+
Example:
diff --git a/dts/Bindings/display/panel/innolux,p079zca.txt b/dts/Bindings/display/panel/innolux,p079zca.txt
new file mode 100644
index 0000000000..5c70a8380e
--- /dev/null
+++ b/dts/Bindings/display/panel/innolux,p079zca.txt
@@ -0,0 +1,23 @@
+Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,p079zca"
+- reg: DSI virtual channel of the peripheral
+- power-supply: phandle of the regulator that provides the supply voltage
+- enable-gpios: panel enable gpio
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+ &mipi_dsi {
+ panel {
+ compatible = "innolux,p079zca";
+ reg = <0>;
+ power-supply = <...>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+ };
diff --git a/dts/Bindings/display/panel/nec,nl12880b20-05.txt b/dts/Bindings/display/panel/nec,nl12880b20-05.txt
new file mode 100644
index 0000000000..71cbc49ecf
--- /dev/null
+++ b/dts/Bindings/display/panel/nec,nl12880b20-05.txt
@@ -0,0 +1,8 @@
+NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
+
+Required properties:
+- compatible: should be "nec,nl12880bc20-05"
+- power-supply: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt b/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt
new file mode 100644
index 0000000000..1a639fd877
--- /dev/null
+++ b/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt
@@ -0,0 +1,8 @@
+NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
+
+Required properties:
+- compatible: should be "nlt,nl192108ac18-02d"
+- power-supply: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/samsung,s6e3ha2.txt b/dts/Bindings/display/panel/samsung,s6e3ha2.txt
index 18854f4c83..4acea25c24 100644
--- a/dts/Bindings/display/panel/samsung,s6e3ha2.txt
+++ b/dts/Bindings/display/panel/samsung,s6e3ha2.txt
@@ -1,7 +1,10 @@
Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel
+Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel
Required properties:
- - compatible: "samsung,s6e3ha2"
+ - compatible: should be one of:
+ "samsung,s6e3ha2",
+ "samsung,s6e3hf2".
- reg: the virtual channel number of a DSI peripheral
- vdd3-supply: I/O voltage supply
- vci-supply: voltage supply for analog circuits
diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt
new file mode 100644
index 0000000000..8e1476941c
--- /dev/null
+++ b/dts/Bindings/display/st,stm32-ltdc.txt
@@ -0,0 +1,36 @@
+* STMicroelectronics STM32 lcd-tft display controller
+
+- ltdc: lcd-tft display controller host
+ must be a sub-node of st-display-subsystem
+ Required properties:
+ - compatible: "st,stm32-ltdc"
+ - reg: Physical base address of the IP registers and length of memory mapped region.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For ltdc it should contain:
+ - "lcd" for the clock feeding the output pixel clock & IP clock.
+ - resets: reset to be used by the device (defined by use of RCC macro).
+ Required nodes:
+ - Video port for RGB output.
+
+Example:
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index 57a8d06100..b83e601804 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -4,6 +4,44 @@ Allwinner A10 Display Pipeline
The Allwinner A10 Display pipeline is composed of several components
that are going to be documented below:
+For the input port of all components up to the TCON in the display
+pipeline, if there are multiple components, the local endpoint IDs
+must correspond to the index of the upstream block. For example, if
+the remote endpoint is Frontend 1, then the local endpoint ID must
+be 1.
+
+Conversely, for the output ports of the same group, the remote endpoint
+ID must be the index of the local hardware block. If the local backend
+is backend 1, then the remote endpoint ID must be 1.
+
+HDMI Encoder
+------------
+
+The HDMI Encoder supports the HDMI video and audio outputs, and does
+CEC. It is one end of the pipeline.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun5i-a10s-hdmi
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * ahb: the HDMI interface clock
+ * mod: the HDMI module clock
+ * pll-0: the first video PLL
+ * pll-1: the second video PLL
+ - clock-names: the clock names mentioned above
+ - dmas: phandles to the DMA channels used by the HDMI encoder
+ * ddc-tx: The channel for DDC transmission
+ * ddc-rx: The channel for DDC reception
+ * audio-tx: The channel used for audio transmission
+ - dma-names: the channel names mentioned above
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
TV Encoder
----------
@@ -31,6 +69,7 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
@@ -47,12 +86,15 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, the second one the output
- The output should have two endpoints. The first is the block
- connected to the TCON channel 0 (usually a panel or a bridge), the
- second the block connected to the TCON channel 1 (usually the TV
- encoder)
+ The output may have multiple endpoints. The TCON has two channels,
+ usually with the first channel being used for the panels interfaces
+ (RGB, LVDS, etc.), and the second being used for the outputs that
+ require another controller (TV Encoder, HDMI, etc.). The endpoints
+ will take an extra property, allwinner,tcon-channel, to specify the
+ channel the endpoint is associated to. If that property is not
+ present, the endpoint number will be used as the channel number.
-On SoCs other than the A33, there is one more clock required:
+On SoCs other than the A33 and V3s, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
@@ -138,6 +180,26 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the outputs
+Display Engine 2.0 Mixer
+------------------------
+
+The DE2 mixer have many functionalities, currently only layer blending is
+supported.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-v3s-de2-mixer
+ - reg: base address and size of the memory-mapped region.
+ - clocks: phandles to the clocks feeding the mixer
+ * bus: the mixer interface clock
+ * mod: the mixer module clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset controllers driving the mixer
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the output
+
Display Engine Pipeline
-----------------------
@@ -148,13 +210,15 @@ extra node.
Required properties:
- compatible: value must be one of:
+ * allwinner,sun5i-a10s-display-engine
* allwinner,sun5i-a13-display-engine
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
* allwinner,sun8i-a33-display-engine
+ * allwinner,sun8i-v3s-display-engine
- allwinner,pipelines: list of phandle to the display engine
- frontends available.
+ frontends (DE 1.0) or mixers (DE 2.0) available.
Example:
@@ -173,6 +237,57 @@ panel: panel {
};
};
+connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+};
+
+hdmi: hdmi@01c16000 {
+ compatible = "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
+
tve0: tv-encoder@01c0a000 {
compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>;
diff --git a/dts/Bindings/display/zte,vou.txt b/dts/Bindings/display/zte,vou.txt
index 9c35628423..38476475fd 100644
--- a/dts/Bindings/display/zte,vou.txt
+++ b/dts/Bindings/display/zte,vou.txt
@@ -58,6 +58,18 @@ Required properties:
integer cells. The first cell is the offset of SYSCTRL register used
to control TV Encoder DAC power, and the second cell is the bit mask.
+* VGA output device
+
+Required properties:
+ - compatible: should be "zte,zx296718-vga"
+ - reg: Physical base address and length of the VGA device IO region
+ - interrupts : VGA interrupt number to CPU
+ - clocks: Phandle with clock-specifier pointing to VGA I2C clock.
+ - clock-names: Must be "i2c_wclk".
+ - zte,vga-power-control: the phandle to SYSCTRL block followed by two
+ integer cells. The first cell is the offset of SYSCTRL register used
+ to control VGA DAC power, and the second cell is the bit mask.
+
Example:
vou: vou@1440000 {
@@ -81,6 +93,15 @@ vou: vou@1440000 {
"main_wclk", "aux_wclk";
};
+ vga: vga@8000 {
+ compatible = "zte,zx296718-vga";
+ reg = <0x8000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topcrm VGA_I2C_WCLK>;
+ clock-names = "i2c_wclk";
+ zte,vga-power-control = <&sysctrl 0x170 0xe0>;
+ };
+
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
diff --git a/dts/Bindings/dma/arm-pl08x.txt b/dts/Bindings/dma/arm-pl08x.txt
index 8a0097a029..0ba81f7926 100644
--- a/dts/Bindings/dma/arm-pl08x.txt
+++ b/dts/Bindings/dma/arm-pl08x.txt
@@ -3,6 +3,11 @@
Required properties:
- compatible: "arm,pl080", "arm,primecell";
"arm,pl081", "arm,primecell";
+ "faraday,ftdmac020", "arm,primecell"
+- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
+ in the hardware and must be specified here as <0x0003b080>. This number
+ follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
+ for Faraday Technology.
- reg: Address range of the PL08x registers
- interrupt: The PL08x interrupt number
- clocks: The clock running the IP core clock
@@ -20,8 +25,8 @@ Optional properties:
- dma-requests: contains the total number of DMA requests supported by the DMAC
- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
64, 128 or 256 bytes are legal values
-- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
- values
+- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
+ values, the Faraday FTDMAC020 can also accept 64 bits
Clients
Required properties:
diff --git a/dts/Bindings/dma/brcm,iproc-sba.txt b/dts/Bindings/dma/brcm,iproc-sba.txt
new file mode 100644
index 0000000000..092913a284
--- /dev/null
+++ b/dts/Bindings/dma/brcm,iproc-sba.txt
@@ -0,0 +1,29 @@
+* Broadcom SBA RAID engine
+
+Required properties:
+- compatible: Should be one of the following
+ "brcm,iproc-sba"
+ "brcm,iproc-sba-v2"
+ The "brcm,iproc-sba" has support for only 6 PQ coefficients
+ The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients
+- mboxes: List of phandle and mailbox channel specifiers
+
+Example:
+
+raid_mbox: mbox@67400000 {
+ ...
+ #mbox-cells = <3>;
+ ...
+};
+
+raid0 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 0 0x1 0xffff>,
+ <&raid_mbox 1 0x1 0xffff>,
+ <&raid_mbox 2 0x1 0xffff>,
+ <&raid_mbox 3 0x1 0xffff>,
+ <&raid_mbox 4 0x1 0xffff>,
+ <&raid_mbox 5 0x1 0xffff>,
+ <&raid_mbox 6 0x1 0xffff>,
+ <&raid_mbox 7 0x1 0xffff>;
+};
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 3316a9c2e6..79a204d502 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -30,8 +30,9 @@ Required Properties:
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
-- interrupt-names: one entry per channel, named "ch%u", where %u is the
- channel number ranging from zero to the number of channels minus one.
+- interrupt-names: one entry for the error interrupt, named "error", plus one
+ entry per channel, named "ch%u", where %u is the channel number ranging from
+ zero to the number of channels minus one.
- clock-names: "fck" for the functional clock
- clocks: a list of phandle + clock-specifier pairs, one for each entry
diff --git a/dts/Bindings/dma/shdma.txt b/dts/Bindings/dma/shdma.txt
index 2a3f3b8946..a91920a494 100644
--- a/dts/Bindings/dma/shdma.txt
+++ b/dts/Bindings/dma/shdma.txt
@@ -1,6 +1,6 @@
* SHDMA Device Tree bindings
-Sh-/r-mobile and r-car systems often have multiple identical DMA controller
+Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
instances, capable of serving any of a common set of DMA slave devices, using
the same configuration. To describe this topology we require all compatible
SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
diff --git a/dts/Bindings/fsi/fsi-master-gpio.txt b/dts/Bindings/fsi/fsi-master-gpio.txt
new file mode 100644
index 0000000000..a767259ded
--- /dev/null
+++ b/dts/Bindings/fsi/fsi-master-gpio.txt
@@ -0,0 +1,24 @@
+Device-tree bindings for gpio-based FSI master driver
+-----------------------------------------------------
+
+Required properties:
+ - compatible = "fsi-master-gpio";
+ - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
+ - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
+
+Optional properties:
+ - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
+ - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
+ - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
+ functions (eg, external FSI masters)
+
+Examples:
+
+ fsi-master {
+ compatible = "fsi-master-gpio", "fsi-master";
+ clock-gpios = <&gpio 0>;
+ data-gpios = <&gpio 1>;
+ enable-gpios = <&gpio 2>;
+ trans-gpios = <&gpio 3>;
+ mux-gpios = <&gpio 4>;
+ }
diff --git a/dts/Bindings/gpio/gpio-mvebu.txt b/dts/Bindings/gpio/gpio-mvebu.txt
index 01e331a5f3..38ca2201e8 100644
--- a/dts/Bindings/gpio/gpio-mvebu.txt
+++ b/dts/Bindings/gpio/gpio-mvebu.txt
@@ -2,17 +2,27 @@
Required properties:
-- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
- or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
- Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
- 370. "marvell,mv78200-gpio" should be used for the Discovery
- MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
- SoCs (MV78230, MV78260, MV78460).
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
+ "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
+
+ "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
+ Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
+ should be used for the Discovery MV78200.
+
+ "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
+ (MV78230, MV78260, MV78460).
+
+ "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
+ SoCs (either from AP or CP), see
+ Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+ and
+ Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+ for specific details about the offset property.
- reg: Address and length of the register set for the device. Only one
entry is expected, except for the "marvell,armadaxp-gpio" variant
for which two entries are expected: one for the general registers,
- one for the per-cpu registers.
+ one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
- interrupts: The list of interrupts that are used for all the pins
managed by this GPIO bank. There can be more than one interrupt
diff --git a/dts/Bindings/gpio/gpio.txt b/dts/Bindings/gpio/gpio.txt
index 84ede036f7..802402f6cc 100644
--- a/dts/Bindings/gpio/gpio.txt
+++ b/dts/Bindings/gpio/gpio.txt
@@ -74,11 +74,14 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
Optional standard bitfield specifiers for the last cell:
- Bit 0: 0 means active high, 1 means active low
-- Bit 1: 1 means single-ended wiring, see:
+- Bit 1: 0 mean push-pull wiring, see:
+ https://en.wikipedia.org/wiki/Push-pull_output
+ 1 means single-ended wiring, see:
https://en.wikipedia.org/wiki/Single-ended_triode
- When used with active-low, this means open drain/collector, see:
+- Bit 2: 0 means open-source, 1 means open drain, see:
https://en.wikipedia.org/wiki/Open_collector
- When used with active-high, this means open source/emitter
+- Bit 3: 0 means the output should be maintained during sleep/low-power mode
+ 1 means the output state can be lost during sleep/low-power mode
1.1) GPIO specifier best practices
----------------------------------
@@ -282,8 +285,8 @@ Example 1:
};
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
-pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
-pins 50..59.
+pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
+pins 50..69.
Example 2:
diff --git a/dts/Bindings/gpio/gpio_atmel.txt b/dts/Bindings/gpio/gpio_atmel.txt
index 85f8c0d084..29416f9c32 100644
--- a/dts/Bindings/gpio/gpio_atmel.txt
+++ b/dts/Bindings/gpio/gpio_atmel.txt
@@ -5,9 +5,13 @@ Required properties:
- reg: Should contain GPIO controller registers location and length
- interrupts: Should be the port interrupt shared by all the pins.
- #gpio-cells: Should be two. The first cell is the pin number and
- the second cell is used to specify optional parameters (currently
- unused).
+ the second cell is used to specify optional parameters to declare if the GPIO
+ is active high or low. See gpio.txt.
- gpio-controller: Marks the device node as a GPIO controller.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two. The first cell is the pin number and the
+ second cell is used to specify irq type flags, see the two cell description
+ in interrupt-controller/interrupts.txt for details.
optional properties:
- #gpio-lines: Number of gpio if absent 32.
@@ -21,5 +25,7 @@ Example:
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
diff --git a/dts/Bindings/gpio/ingenic,gpio.txt b/dts/Bindings/gpio/ingenic,gpio.txt
new file mode 100644
index 0000000000..7988aeb725
--- /dev/null
+++ b/dts/Bindings/gpio/ingenic,gpio.txt
@@ -0,0 +1,46 @@
+Ingenic jz47xx GPIO controller
+
+That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
+driver node.
+
+Required properties:
+--------------------
+
+ - compatible: Must contain one of:
+ - "ingenic,jz4740-gpio"
+ - "ingenic,jz4770-gpio"
+ - "ingenic,jz4780-gpio"
+ - reg: The GPIO bank number.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - interrupts: Interrupt specifier for the controllers interrupt.
+ - #interrupt-cells: Should be 2. Refer to
+ ../interrupt-controller/interrupts.txt for more details.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+ - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
+ 'gpio.txt' in this directory for more details.
+
+Example:
+--------
+
+&pinctrl {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+};
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 7c1ab3b325..6826a371fb 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -3,6 +3,7 @@
Required Properties:
- compatible: should contain one of the following.
+ - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
diff --git a/dts/Bindings/gpu/arm,mali-midgard.txt b/dts/Bindings/gpu/arm,mali-midgard.txt
new file mode 100644
index 0000000000..d3b6e1a471
--- /dev/null
+++ b/dts/Bindings/gpu/arm,mali-midgard.txt
@@ -0,0 +1,86 @@
+ARM Mali Midgard GPU
+====================
+
+Required properties:
+
+- compatible :
+ * Must contain one of the following:
+ + "arm,mali-t604"
+ + "arm,mali-t624"
+ + "arm,mali-t628"
+ + "arm,mali-t720"
+ + "arm,mali-t760"
+ + "arm,mali-t820"
+ + "arm,mali-t830"
+ + "arm,mali-t860"
+ + "arm,mali-t880"
+ * which must be preceded by one of the following vendor specifics:
+ + "amlogic,meson-gxm-mali"
+ + "rockchip,rk3288-mali"
+
+- reg : Physical base address of the device and length of the register area.
+
+- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
+
+- interrupt-names : Contains the names of IRQ resources in the order they were
+ provided in the interrupts property. Must contain: "job", "mmu", "gpu".
+
+
+Optional properties:
+
+- clocks : Phandle to clock for the Mali Midgard device.
+
+- mali-supply : Phandle to regulator for the Mali device. Refer to
+ Documentation/devicetree/bindings/regulator/regulator.txt for details.
+
+- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt
+ for details.
+
+
+Example for a Mali-T760:
+
+gpu@ffa30000 {
+ compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+ reg = <0xffa30000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&cru ACLK_GPU>;
+ mali-supply = <&vdd_gpu>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3288_PD_GPU>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp@533000000 {
+ opp-hz = /bits/ 64 <533000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp@450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-microvolt = <1150000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1125000>;
+ };
+ opp@350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-microvolt = <1075000>;
+ };
+ opp@266000000 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp@160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <925000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <912500>;
+ };
+};
diff --git a/dts/Bindings/graph.txt b/dts/Bindings/graph.txt
index fcb1c6a478..0415e2c53b 100644
--- a/dts/Bindings/graph.txt
+++ b/dts/Bindings/graph.txt
@@ -34,7 +34,7 @@ remote device, an 'endpoint' child node must be provided for each link.
If more than one port is present in a device node or there is more than one
endpoint at a port, or a port node needs to be associated with a selected
hardware interface, a common scheme using '#address-cells', '#size-cells'
-and 'reg' properties is used number the nodes.
+and 'reg' properties is used to number the nodes.
device {
...
@@ -89,9 +89,9 @@ Links between endpoints
Each endpoint should contain a 'remote-endpoint' phandle property that points
to the corresponding endpoint in the port of the remote device. In turn, the
-remote endpoint should contain a 'remote-endpoint' property. If it has one,
-it must not point to another than the local endpoint. Two endpoints with their
-'remote-endpoint' phandles pointing at each other form a link between the
+remote endpoint should contain a 'remote-endpoint' property. If it has one, it
+must not point to anything other than the local endpoint. Two endpoints with
+their 'remote-endpoint' phandles pointing at each other form a link between the
containing ports.
device-1 {
@@ -110,13 +110,12 @@ device-2 {
};
};
-
Required properties
-------------------
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
-property is present in port and/or endpoint nodes the following properties
-are required in a relevant parent node:
+property present in the port and/or endpoint nodes then the following
+properties are required in a relevant parent node:
- #address-cells : number of cells required to define port/endpoint
identifier, should be 1.
diff --git a/dts/Bindings/hwlock/sprd-hwspinlock.txt b/dts/Bindings/hwlock/sprd-hwspinlock.txt
new file mode 100644
index 0000000000..581db9d941
--- /dev/null
+++ b/dts/Bindings/hwlock/sprd-hwspinlock.txt
@@ -0,0 +1,23 @@
+SPRD Hardware Spinlock Device Binding
+-------------------------------------
+
+Required properties :
+- compatible : should be "sprd,hwspinlock-r3p0".
+- reg : the register address of hwspinlock.
+- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
+ hwlock, so the number of cells should be <1> here.
+- clock-names : Must contain "enable".
+- clocks : Must contain a phandle entry for the clock in clock-names, see the
+ common clock bindings.
+
+Please look at the generic hwlock binding for usage information for consumers,
+"Documentation/devicetree/bindings/hwlock/hwlock.txt"
+
+Example of hwlock provider:
+ hwspinlock@40500000 {
+ compatible = "sprd,hwspinlock-r3p0";
+ reg = <0 0x40500000 0 0x1000>;
+ #hwlock-cells = <1>;
+ clock-names = "enable";
+ clocks = <&clk_aon_apb_gates0 22>;
+ };
diff --git a/dts/Bindings/i2c/i2c-aspeed.txt b/dts/Bindings/i2c/i2c-aspeed.txt
new file mode 100644
index 0000000000..bd6480b195
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-aspeed.txt
@@ -0,0 +1,48 @@
+Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs.
+
+Required Properties:
+- #address-cells : should be 1
+- #size-cells : should be 0
+- reg : address offset and range of bus
+- compatible : should be "aspeed,ast2400-i2c-bus"
+ or "aspeed,ast2500-i2c-bus"
+- clocks : root clock of bus, should reference the APB
+ clock
+- interrupts : interrupt number
+- interrupt-parent : interrupt controller for bus, should reference a
+ aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic
+ interrupt controller
+
+Optional Properties:
+- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
+ specified
+- multi-master : states that there is another master active on this bus.
+
+Example:
+
+i2c {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e78a000 0x1000>;
+
+ i2c_ic: interrupt-controller@0 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2400-i2c-ic";
+ reg = <0x0 0x40>;
+ interrupts = <12>;
+ interrupt-controller;
+ };
+
+ i2c0: i2c-bus@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x40 0x40>;
+ compatible = "aspeed,ast2400-i2c-bus";
+ clocks = <&clk_apb>;
+ bus-frequency = <100000>;
+ interrupts = <0>;
+ interrupt-parent = <&i2c_ic>;
+ };
+};
diff --git a/dts/Bindings/i2c/i2c-designware.txt b/dts/Bindings/i2c/i2c-designware.txt
index fee26dc3e8..fbb0a6d8b9 100644
--- a/dts/Bindings/i2c/i2c-designware.txt
+++ b/dts/Bindings/i2c/i2c-designware.txt
@@ -20,7 +20,7 @@ Optional properties :
- i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
This value which is by default 300ns is used to compute the tHIGH period.
-Example :
+Examples :
i2c@f0000 {
#address-cells = <1>;
@@ -43,3 +43,17 @@ Example :
i2c-sda-falling-time-ns = <300>;
i2c-scl-falling-time-ns = <300>;
};
+
+ i2c@1120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2000 0x100>;
+ clock-frequency = <400000>;
+ clocks = <&i2cclk>;
+ interrupts = <0>;
+
+ eeprom@64 {
+ compatible = "linux,slave-24c02";
+ reg = <0x40000064>;
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c-mt6577.txt b/dts/Bindings/i2c/i2c-mtk.txt
index 0ce6fa3242..bd5a7befd9 100644
--- a/dts/Bindings/i2c/i2c-mt6577.txt
+++ b/dts/Bindings/i2c/i2c-mtk.txt
@@ -4,11 +4,11 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
- (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
- (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
- (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
- (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
- (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
+ "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
+ "mediatek,mt6577-i2c": for i2c compatible with mt6577.
+ "mediatek,mt6589-i2c": for i2c compatible with mt6589.
+ "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
+ "mediatek,mt8173-i2c": for i2c compatible with mt8173.
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
diff --git a/dts/Bindings/i2c/i2c-mux-gpmux.txt b/dts/Bindings/i2c/i2c-mux-gpmux.txt
new file mode 100644
index 0000000000..2907dab562
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-mux-gpmux.txt
@@ -0,0 +1,99 @@
+General Purpose I2C Bus Mux
+
+This binding describes an I2C bus multiplexer that uses a mux controller
+from the mux subsystem to route the I2C signals.
+
+ .-----. .-----.
+ | dev | | dev |
+ .------------. '-----' '-----'
+ | SoC | | |
+ | | .--------+--------'
+ | .------. | .------+ child bus A, on MUX value set to 0
+ | | I2C |-|--| Mux |
+ | '------' | '--+---+ child bus B, on MUX value set to 1
+ | .------. | | '----------+--------+--------.
+ | | MUX- | | | | | |
+ | | Ctrl |-|-----+ .-----. .-----. .-----.
+ | '------' | | dev | | dev | | dev |
+ '------------' '-----' '-----' '-----'
+
+Required properties:
+- compatible: i2c-mux
+- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
+ port is connected to.
+- mux-controls: The phandle of the mux controller to use for operating the
+ mux.
+* Standard I2C mux properties. See i2c-mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
+ is also the mux-controller state described in ../mux/mux-controller.txt
+
+Optional properties:
+- mux-locked: If present, explicitly allow unrelated I2C transactions on the
+ parent I2C adapter at these times:
+ + during setup of the multiplexer
+ + between setup of the multiplexer and the child bus I2C transaction
+ + between the child bus I2C transaction and releasing of the multiplexer
+ + during releasing of the multiplexer
+ However, I2C transactions to devices behind all I2C multiplexers connected
+ to the same parent adapter that this multiplexer is connected to are blocked
+ for the full duration of the complete multiplexed I2C transaction (i.e.
+ including the times covered by the above list).
+ If mux-locked is not present, the multiplexer is assumed to be parent-locked.
+ This means that no unrelated I2C transactions are allowed on the parent I2C
+ adapter for the complete multiplexed I2C transaction.
+ The properties of mux-locked and parent-locked multiplexers are discussed
+ in more detail in Documentation/i2c/i2c-topology.
+
+For each i2c child node, an I2C child bus will be created. They will
+be numbered based on their order in the device tree.
+
+Whenever an access is made to a device on a child bus, the value set
+in the relevant node's reg property will be set as the state in the
+mux controller.
+
+Example:
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ mux-locked;
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ compatible = "solomon,ssd1307fb-i2c";
+ reg = <0x3c>;
+ pwms = <&pwm 4 3000>;
+ reset-gpios = <&gpio2 7 1>;
+ reset-active-low;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c-pca-platform.txt b/dts/Bindings/i2c/i2c-pca-platform.txt
new file mode 100644
index 0000000000..f1f3876bb8
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-pca-platform.txt
@@ -0,0 +1,29 @@
+* NXP PCA PCA9564/PCA9665 I2C controller
+
+The PCA9564/PCA9665 serves as an interface between most standard
+parallel-bus microcontrollers/microprocessors and the serial I2C-bus
+and allows the parallel bus system to communicate bi-directionally
+with the I2C-bus.
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : one of "nxp,pca9564" or "nxp,pca9665"
+
+Optional properties
+ - interrupts : the interrupt number
+ - interrupt-parent : the phandle for the interrupt controller.
+ If an interrupt is not specified polling will be used.
+ - reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
+ is active low, it should be marked GPIO_ACTIVE_LOW.
+ - clock-frequency : I2C bus frequency.
+
+Example:
+ i2c0: i2c@80000 {
+ compatible = "nxp,pca9564";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80000 0x4>;
+ reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ clock-frequency = <100000>;
+ };
diff --git a/dts/Bindings/i2c/i2c-zx2967.txt b/dts/Bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 0000000000..cb806d1ae4
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,22 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24m>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <1600000>;
+ };
diff --git a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
index 047189192a..f413e82c8b 100644
--- a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
+++ b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
@@ -2,6 +2,8 @@
Required properties:
- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson8-saradc" for Meson8
+ - "amlogic,meson8b-saradc" for Meson8b
- "amlogic,meson-gxbb-saradc" for GXBB
- "amlogic,meson-gxl-saradc" for GXL
- "amlogic,meson-gxm-saradc" for GXM
diff --git a/dts/Bindings/iio/adc/renesas,gyroadc.txt b/dts/Bindings/iio/adc/renesas,gyroadc.txt
index f5b0adae60..df5b9f2ad8 100644
--- a/dts/Bindings/iio/adc/renesas,gyroadc.txt
+++ b/dts/Bindings/iio/adc/renesas,gyroadc.txt
@@ -1,4 +1,4 @@
-* Renesas RCar GyroADC device driver
+* Renesas R-Car GyroADC device driver
The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
@@ -16,8 +16,7 @@ Required properties:
- clocks: References to all the clocks specified in the clock-names
property as specified in
Documentation/devicetree/bindings/clock/clock-bindings.txt.
-- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block
- clock, the "if" is the interface clock.
+- clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
- power-domains: Must contain a reference to the PM domain, if available.
- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
except for "fujitsu,mb88101a". Should be <0> (setting for
@@ -75,8 +74,8 @@ Example:
adc@e6e54000 {
compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
reg = <0 0xe6e54000 0 64>;
- clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>;
- clock-names = "fck", "if";
+ clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
+ clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
pinctrl-0 = <&adc_pins>;
diff --git a/dts/Bindings/iio/adc/st,stm32-adc.txt b/dts/Bindings/iio/adc/st,stm32-adc.txt
index e35f9f1b32..8310073f14 100644
--- a/dts/Bindings/iio/adc/st,stm32-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-adc.txt
@@ -21,11 +21,19 @@ own configurable sequence and trigger:
Contents of a stm32 adc root node:
-----------------------------------
Required properties:
-- compatible: Should be "st,stm32f4-adc-core".
+- compatible: Should be one of:
+ "st,stm32f4-adc-core"
+ "st,stm32h7-adc-core"
- reg: Offset and length of the ADC block register set.
- interrupts: Must contain the interrupt for ADC block.
-- clocks: Clock for the analog circuitry (common to all ADCs).
-- clock-names: Must be "adc".
+- clocks: Core can use up to two clocks, depending on part used:
+ - "adc" clock: for the analog circuitry, common to all ADCs.
+ It's required on stm32f4.
+ It's optional on stm32h7.
+ - "bus" clock: for registers access, common to all ADCs.
+ It's not present on stm32f4.
+ It's required on stm32h7.
+- clock-names: Must be "adc" and/or "bus" depending on part used.
- interrupt-controller: Identifies the controller node as interrupt-parent
- vref-supply: Phandle to the vref input analog reference voltage.
- #interrupt-cells = <1>;
@@ -42,14 +50,18 @@ An ADC block node should contain at least one subnode, representing an
ADC instance available on the machine.
Required properties:
-- compatible: Should be "st,stm32f4-adc".
+- compatible: Should be one of:
+ "st,stm32f4-adc"
+ "st,stm32h7-adc"
- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
-- clocks: Input clock private to this ADC instance.
+- clocks: Input clock private to this ADC instance. It's required only on
+ stm32f4, that has per instance clock input for registers access.
- interrupt-parent: Phandle to the parent interrupt controller.
- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
2 for adc@200).
- st,adc-channels: List of single-ended channels muxed for this ADC.
- It can have up to 16 channels, numbered from 0 to 15 (resp. for in0..in15).
+ It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
+ from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
Documentation/devicetree/bindings/iio/iio-bindings.txt
@@ -58,7 +70,9 @@ Optional properties:
See ../../dma/dma.txt for details.
- dma-names: Must be "rx" when dmas property is being used.
- assigned-resolution-bits: Resolution (bits) to use for conversions. Must
- match device available resolutions (e.g. can be 6, 8, 10 or 12 on stm32f4).
+ match device available resolutions:
+ * can be 6, 8, 10 or 12 on stm32f4
+ * can be 8, 10, 12, 14 or 16 on stm32h7
Default is maximum resolution if unset.
Example:
diff --git a/dts/Bindings/iio/adc/ti-adc084s021.txt b/dts/Bindings/iio/adc/ti-adc084s021.txt
new file mode 100644
index 0000000000..4259e50620
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti-adc084s021.txt
@@ -0,0 +1,19 @@
+* Texas Instruments' ADC084S021
+
+Required properties:
+ - compatible : Must be "ti,adc084s021"
+ - reg : SPI chip select number for the device
+ - vref-supply : The regulator supply for ADC reference voltage
+ - spi-cpol : Per spi-bus bindings
+ - spi-cpha : Per spi-bus bindings
+ - spi-max-frequency : Per spi-bus bindings
+
+Example:
+adc@0 {
+ compatible = "ti,adc084s021";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <16000000>;
+};
diff --git a/dts/Bindings/iio/adc/ti-adc108s102.txt b/dts/Bindings/iio/adc/ti-adc108s102.txt
new file mode 100644
index 0000000000..bbbbb4a9f5
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti-adc108s102.txt
@@ -0,0 +1,18 @@
+* Texas Instruments' ADC108S102 and ADC128S102 ADC chip
+
+Required properties:
+ - compatible: Should be "ti,adc108s102"
+ - reg: spi chip select number for the device
+ - vref-supply: The regulator supply for ADC reference voltage
+
+Recommended properties:
+ - spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+adc@0 {
+ compatible = "ti,adc108s102";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+};
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
index 8305fb05ff..6f28ff55f3 100644
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/dts/Bindings/iio/imu/st_lsm6dsx.txt
@@ -13,7 +13,8 @@ Optional properties:
"data ready" (valid values: 1 or 2).
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+ flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
+ IRQ_TYPE_EDGE_FALLING.
Refer to interrupt-controller/interrupts.txt for generic interrupt
client node bindings.
diff --git a/dts/Bindings/iio/multiplexer/io-channel-mux.txt b/dts/Bindings/iio/multiplexer/io-channel-mux.txt
new file mode 100644
index 0000000000..c827940025
--- /dev/null
+++ b/dts/Bindings/iio/multiplexer/io-channel-mux.txt
@@ -0,0 +1,39 @@
+I/O channel multiplexer bindings
+
+If a multiplexer is used to select which hardware signal is fed to
+e.g. an ADC channel, these bindings describe that situation.
+
+Required properties:
+- compatible : "io-channel-mux"
+- io-channels : Channel node of the parent channel that has multiplexed
+ input.
+- io-channel-names : Should be "parent".
+- #address-cells = <1>;
+- #size-cells = <0>;
+- mux-controls : Mux controller node to use for operating the mux
+- channels : List of strings, labeling the mux controller states.
+
+For each non-empty string in the channels property, an io-channel will
+be created. The number of this io-channel is the same as the index into
+the list of strings in the channels property, and also matches the mux
+controller state. The mux controller state is described in
+../mux/mux-controller.txt
+
+Example:
+ mux: mux-controller {
+ compatible = "mux-gpio";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+
+ channels = "sync", "in", "system-regulator";
+ };
diff --git a/dts/Bindings/iio/proximity/as3935.txt b/dts/Bindings/iio/proximity/as3935.txt
index ae23dd8da7..38d74314b7 100644
--- a/dts/Bindings/iio/proximity/as3935.txt
+++ b/dts/Bindings/iio/proximity/as3935.txt
@@ -3,6 +3,7 @@ Austrian Microsystems AS3935 Franklin lightning sensor device driver
Required properties:
- compatible: must be "ams,as3935"
- reg: SPI chip select number for the device
+ - spi-max-frequency: specifies maximum SPI clock frequency
- spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
slave node bindings.
- interrupt-parent : should be the phandle for the interrupt controller
@@ -21,6 +22,7 @@ Example:
as3935@0 {
compatible = "ams,as3935";
reg = <0>;
+ spi-max-frequency = <400000>;
spi-cpha;
interrupt-parent = <&gpio1>;
interrupts = <16 1>;
diff --git a/dts/Bindings/input/dlink,dir685-touchkeys.txt b/dts/Bindings/input/dlink,dir685-touchkeys.txt
new file mode 100644
index 0000000000..10dec1c57a
--- /dev/null
+++ b/dts/Bindings/input/dlink,dir685-touchkeys.txt
@@ -0,0 +1,21 @@
+* D-Link DIR-685 Touchkeys
+
+This is a I2C one-off touchkey controller based on the Cypress Semiconductor
+CY8C214 MCU with some firmware in its internal 8KB flash. The circuit
+board inside the router is named E119921.
+
+The touchkey device node should be placed inside an I2C bus node.
+
+Required properties:
+- compatible: must be "dlink,dir685-touchkeys"
+- reg: the I2C address of the touchkeys
+- interrupts: reference to the interrupt number
+
+Example:
+
+touchkeys@26 {
+ compatible = "dlink,dir685-touchkeys";
+ reg = <0x26>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+};
diff --git a/dts/Bindings/input/touchscreen/st,stmfts.txt b/dts/Bindings/input/touchscreen/st,stmfts.txt
new file mode 100644
index 0000000000..9683595cd0
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/st,stmfts.txt
@@ -0,0 +1,43 @@
+* ST-Microelectronics FingerTip touchscreen controller
+
+The ST-Microelectronics FingerTip device provides a basic touchscreen
+functionality. Along with it the user can enable the touchkey which can work as
+a basic HOME and BACK key for phones.
+
+The driver supports also hovering as an absolute single touch event with x, y, z
+coordinates.
+
+Required properties:
+- compatible : must be "st,stmfts"
+- reg : I2C slave address, (e.g. 0x49)
+- interrupt-parent : the phandle to the interrupt controller which provides
+ the interrupt
+- interrupts : interrupt specification
+- avdd-supply : analogic power supply
+- vdd-supply : power supply
+- touchscreen-size-x : see touchscreen.txt
+- touchscreen-size-y : see touchscreen.txt
+
+Optional properties:
+- touch-key-connected : specifies whether the touchkey feature is connected
+- ledvdd-supply : power supply to the touch key leds
+
+Example:
+
+i2c@00000000 {
+
+ /* ... */
+
+ touchscreen@49 {
+ compatible = "st,stmfts";
+ reg = <0x49>;
+ interrupt-parent = <&gpa1>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ touchscreen-size-x = <1599>;
+ touchscreen-size-y = <2559>;
+ touch-key-connected;
+ avdd-supply = <&ldo30_reg>;
+ vdd-supply = <&ldo31_reg>;
+ ledvdd-supply = <&ldo33_reg>;
+ };
+};
diff --git a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 81cd369240..4ae553eb33 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
Required properties:
-- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
- "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
+- compatible : should be one of the following:
+ - "allwinner,sun7i-a20-sc-nmi"
+ - "allwinner,sun6i-a31-sc-nmi" (deprecated)
+ - "allwinner,sun6i-a31-r-intc"
+ - "allwinner,sun9i-a80-nmi"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
new file mode 100644
index 0000000000..033cc82e56
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
@@ -0,0 +1,25 @@
+Device tree configuration for the I2C Interrupt Controller on the AST24XX and
+AST25XX SoCs.
+
+Required Properties:
+- #address-cells : should be 1
+- #size-cells : should be 1
+- #interrupt-cells : should be 1
+- compatible : should be "aspeed,ast2400-i2c-ic"
+ or "aspeed,ast2500-i2c-ic"
+- reg : address start and range of controller
+- interrupts : interrupt number
+- interrupt-controller : denotes that the controller receives and fires
+ new interrupts for child busses
+
+Example:
+
+i2c_ic: interrupt-controller@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2400-i2c-ic";
+ reg = <0x0 0x40>;
+ interrupts = <12>;
+ interrupt-controller;
+};
diff --git a/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
index 6c6e85324b..e3fea0758d 100644
--- a/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
+++ b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
@@ -1,12 +1,13 @@
Aspeed Vectored Interrupt Controller
-These bindings are for the Aspeed AST2400 interrupt controller register layout.
-The SoC has an legacy register layout, but this driver does not support that
-mode of operation.
+These bindings are for the Aspeed interrupt controller. The AST2400 and
+AST2500 SoC families include a legacy register layout before a re-designed
+layout, but the bindings do not prescribe the use of one or the other.
Required properties:
-- compatible : should be "aspeed,ast2400-vic".
+- compatible : "aspeed,ast2400-vic"
+ "aspeed,ast2500-vic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/dts/Bindings/interrupt-controller/marvell,gicp.txt b/dts/Bindings/interrupt-controller/marvell,gicp.txt
new file mode 100644
index 0000000000..64a00ceb7d
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,gicp.txt
@@ -0,0 +1,27 @@
+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,ap806-gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
+ for this GICP
+
+- msi-controller: indicates that this is an MSI controller
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+};
diff --git a/dts/Bindings/interrupt-controller/marvell,icu.txt b/dts/Bindings/interrupt-controller/marvell,icu.txt
new file mode 100644
index 0000000000..aa8bf2ec89
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,icu.txt
@@ -0,0 +1,51 @@
+Marvell ICU Interrupt Controller
+--------------------------------
+
+The Marvell ICU (Interrupt Consolidation Unit) controller is
+responsible for collecting all wired-interrupt sources in the CP and
+communicating them to the GIC in the AP, the unit translates interrupt
+requests on input wires to MSG memory mapped transactions to the GIC.
+
+Required properties:
+
+- compatible: Should be "marvell,cp110-icu"
+
+- reg: Should contain ICU registers location and length.
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 3.
+
+ The 1st cell is the group type of the ICU interrupt. Possible group
+ types are:
+
+ ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
+ ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
+ ICU_GRP_SEI (0x4) : System error interrupt
+ ICU_GRP_REI (0x5) : RAM error interrupt
+
+ The 2nd cell is the index of the interrupt in the ICU unit.
+
+ The 3rd cell is the type of the interrupt. See arm,gic.txt for
+ details.
+
+- interrupt-controller: Identifies the node as an interrupt
+ controller.
+
+- msi-parent: Should point to the GICP controller, the GIC extension
+ that allows to trigger interrupts using MSG memory mapped
+ transactions.
+
+Example:
+
+icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+};
+
+usb3h0: usb3@500000 {
+ interrupt-parent = <&icu>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03bb1a..11cc87aeb2 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,21 +1,23 @@
-+Mediatek 65xx/67xx/81xx sysirq
++Mediatek MT65xx/MT67xx/MT81xx sysirq
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
-- compatible: should be one of:
- "mediatek,mt8173-sysirq"
- "mediatek,mt8135-sysirq"
- "mediatek,mt8127-sysirq"
- "mediatek,mt6795-sysirq"
- "mediatek,mt6755-sysirq"
- "mediatek,mt6592-sysirq"
- "mediatek,mt6589-sysirq"
- "mediatek,mt6582-sysirq"
- "mediatek,mt6580-sysirq"
- "mediatek,mt6577-sysirq"
- "mediatek,mt2701-sysirq"
+- compatible: should be
+ "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
+ "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
+ "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
+ "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
+ "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
+ "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
+ "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
+ "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
+ "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
+ "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
+ "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
+ "mediatek,mt6577-sysirq": for MT6577
+ "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/dts/Bindings/interrupt-controller/open-pic.txt b/dts/Bindings/interrupt-controller/open-pic.txt
index 909a902dff..ccbbfdc53c 100644
--- a/dts/Bindings/interrupt-controller/open-pic.txt
+++ b/dts/Bindings/interrupt-controller/open-pic.txt
@@ -92,7 +92,6 @@ Example 2:
* References
-[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
- Requirements (ePAPR), Version 1.0, July 2008.
- (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
+[1] Devicetree Specification
+ (https://www.devicetree.org/specifications/)
diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt
index be57550e14..c9abbf3e4f 100644
--- a/dts/Bindings/iommu/arm,smmu-v3.txt
+++ b/dts/Bindings/iommu/arm,smmu-v3.txt
@@ -26,6 +26,12 @@ the PCIe specification.
* "priq" - PRI Queue not empty
* "cmdq-sync" - CMD_SYNC complete
* "gerror" - Global Error activated
+ * "combined" - The combined interrupt is optional,
+ and should only be provided if the
+ hardware supports just a single,
+ combined interrupt line.
+ If provided, then the combined interrupt
+ will be used in preference to any others.
- #iommu-cells : See the generic IOMMU binding described in
devicetree/bindings/pci/pci-iommu.txt
@@ -49,6 +55,12 @@ the PCIe specification.
- hisilicon,broken-prefetch-cmd
: Avoid sending CMD_PREFETCH_* commands to the SMMU.
+- cavium,cn9900-broken-page1-regspace
+ : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
+ PRIQ_PROD/CONS register access with page 0 offsets.
+ Set for Cavium ThunderX2 silicon that doesn't support
+ SMMU page1 register space.
+
** Example
smmu@2b400000 {
diff --git a/dts/Bindings/leds/common.txt b/dts/Bindings/leds/common.txt
index 24b6560140..1d4afe9644 100644
--- a/dts/Bindings/leds/common.txt
+++ b/dts/Bindings/leds/common.txt
@@ -1,4 +1,4 @@
-Common leds properties.
+* Common leds properties.
LED and flash LED devices provide the same basic functionality as current
regulators, but extended with LED and flash LED specific features like
@@ -49,6 +49,22 @@ Optional properties for child nodes:
- panic-indicator : This property specifies that the LED should be used,
if at all possible, as a panic indicator.
+- trigger-sources : List of devices which should be used as a source triggering
+ this LED activity. Some LEDs can be related to a specific
+ device and should somehow indicate its state. E.g. USB 2.0
+ LED may react to device(s) in a USB 2.0 port(s).
+ Another common example is switch or router with multiple
+ Ethernet ports each of them having its own LED assigned
+ (assuming they are not hardwired). In such cases this
+ property should contain phandle(s) of related source
+ device(s).
+ In many cases LED can be related to more than one device
+ (e.g. one USB LED vs. multiple USB ports). Each source
+ should be represented by a node in the device tree and be
+ referenced by a phandle and a set of phandle arguments. A
+ length of arguments should be specified by the
+ #trigger-source-cells property in the source node.
+
Required properties for flash LED child nodes:
- flash-max-microamp : Maximum flash LED supply current in microamperes.
- flash-max-timeout-us : Maximum timeout in microseconds after which the flash
@@ -59,7 +75,17 @@ property can be omitted.
For controllers that have no configurable timeout the flash-max-timeout-us
property can be omitted.
-Examples:
+* Trigger source providers
+
+Each trigger source should be represented by a device tree node. It may be e.g.
+a USB port or an Ethernet device.
+
+Required properties for trigger source:
+- #trigger-source-cells : Number of cells in a source trigger. Typically 0 for
+ nodes of simple trigger sources (e.g. a specific USB
+ port).
+
+* Examples
gpio-leds {
compatible = "gpio-leds";
@@ -69,6 +95,11 @@ gpio-leds {
linux,default-trigger = "heartbeat";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
+
+ usb {
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
+ };
};
max77693-led {
diff --git a/dts/Bindings/leds/pca963x.txt b/dts/Bindings/leds/pca963x.txt
index dfbdb123a9..4eee414820 100644
--- a/dts/Bindings/leds/pca963x.txt
+++ b/dts/Bindings/leds/pca963x.txt
@@ -10,6 +10,7 @@ Optional properties:
- nxp,period-scale : In some configurations, the chip blinks faster than expected.
This parameter provides a scaling ratio (fixed point, decimal divided
by 1000) to compensate, e.g. 1300=1.3x and 750=0.75x.
+- nxp,inverted-out: invert the polarity of the generated PWM
Each led is represented as a sub-node of the nxp,pca963x device.
diff --git a/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt b/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt
new file mode 100644
index 0000000000..fb961c310f
--- /dev/null
+++ b/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -0,0 +1,46 @@
+Binding for the Qualcomm APCS global block
+==========================================
+
+This binding describes the APCS "global" block found in various Qualcomm
+platforms.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,msm8916-apcs-kpss-global",
+ "qcom,msm8996-apcs-hmss-global"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the global block
+
+- #mbox-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: as described in mailbox.txt, must be 1
+
+
+= EXAMPLE
+The following example describes the APCS HMSS found in MSM8996 and part of the
+GLINK RPM referencing the "rpm_hlos" doorbell therein.
+
+ apcs_glb: mailbox@9820000 {
+ compatible = "qcom,msm8996-apcs-hmss-global";
+ reg = <0x9820000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ mboxes = <&apcs_glb 0>;
+ mbox-names = "rpm_hlos";
+ };
+
diff --git a/dts/Bindings/media/cec.txt b/dts/Bindings/media/cec.txt
new file mode 100644
index 0000000000..22d7aae3d3
--- /dev/null
+++ b/dts/Bindings/media/cec.txt
@@ -0,0 +1,8 @@
+Common bindings for HDMI CEC adapters
+
+- hdmi-phandle: phandle to the HDMI controller.
+
+- needs-hpd: if present the CEC support is only available when the HPD
+ is high. Some boards only let the CEC pin through if the HPD is high,
+ for example if there is a level converter that uses the HPD to power
+ up or down.
diff --git a/dts/Bindings/media/i2c/adv7180.txt b/dts/Bindings/media/i2c/adv7180.txt
index 4da486f96f..552b6a82cb 100644
--- a/dts/Bindings/media/i2c/adv7180.txt
+++ b/dts/Bindings/media/i2c/adv7180.txt
@@ -6,6 +6,8 @@ digital interfaces like MIPI CSI-2 or parallel video.
Required Properties :
- compatible : value must be one of
"adi,adv7180"
+ "adi,adv7180cp"
+ "adi,adv7180st"
"adi,adv7182"
"adi,adv7280"
"adi,adv7280-m"
@@ -15,6 +17,19 @@ Required Properties :
"adi,adv7282"
"adi,adv7282-m"
+Device nodes of "adi,adv7180cp" and "adi,adv7180st" must contain one
+'port' child node per device input and output port, in accordance with the
+video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The port
+nodes are numbered as follows.
+
+ Port adv7180cp adv7180st
+-------------------------------------------------------------------
+ Input 0-2 0-5
+ Output 3 6
+
+The digital output port node must contain at least one endpoint.
+
Optional Properties :
- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
if any.
diff --git a/dts/Bindings/media/i2c/max2175.txt b/dts/Bindings/media/i2c/max2175.txt
new file mode 100644
index 0000000000..02b4e9cd7b
--- /dev/null
+++ b/dts/Bindings/media/i2c/max2175.txt
@@ -0,0 +1,59 @@
+Maxim Integrated MAX2175 RF to Bits tuner
+-----------------------------------------
+
+The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with
+RF to Bits® front-end designed for software-defined radio solutions.
+
+Required properties:
+--------------------
+- compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
+- clocks: clock specifier.
+- port: child port node corresponding to the I2S output, in accordance with
+ the video interface bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The port
+ node must contain at least one endpoint.
+
+Optional properties:
+--------------------
+- maxim,master : phandle to the master tuner if it is a slave. This
+ is used to define two tuners in diversity mode
+ (1 master, 1 slave). By default each tuner is an
+ individual master.
+- maxim,refout-load : load capacitance value (in picofarads) on reference
+ output drive level. The possible load values are:
+ 0 (default - refout disabled)
+ 10
+ 20
+ 30
+ 40
+ 60
+ 70
+- maxim,am-hiz-filter : empty property indicates the AM Hi-Z filter is used
+ in this hardware for AM antenna input.
+
+Example:
+--------
+
+Board specific DTS file
+
+/* Fixed XTAL clock node */
+maxim_xtal: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <36864000>;
+};
+
+/* A tuner device instance under i2c bus */
+max2175_0: tuner@60 {
+ compatible = "maxim,max2175";
+ reg = <0x60>;
+ clocks = <&maxim_xtal>;
+ maxim,refout-load = <10>;
+
+ port {
+ max2175_0_ep: endpoint {
+ remote-endpoint = <&slave_rx_device>;
+ };
+ };
+
+};
diff --git a/dts/Bindings/media/i2c/ov5640.txt b/dts/Bindings/media/i2c/ov5640.txt
new file mode 100644
index 0000000000..540b36c4b1
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov5640.txt
@@ -0,0 +1,45 @@
+* Omnivision OV5640 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: should be "ovti,ov5640"
+- clocks: reference to the xclk input clock.
+- clock-names: should be "xclk".
+- DOVDD-supply: Digital I/O voltage supply, 1.8 volts
+- AVDD-supply: Analog voltage supply, 2.8 volts
+- DVDD-supply: Digital core voltage supply, 1.5 volts
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the reset pin, if any.
+ This is an active low signal to the OV5640.
+- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
+ if any. This is an active high signal to the OV5640.
+
+The device node must contain one 'port' child node for its digital output
+video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+&i2c1 {
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v */
+ powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+
+ port {
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_from_ov5640>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/imx.txt b/dts/Bindings/media/imx.txt
new file mode 100644
index 0000000000..77f4b0a7fd
--- /dev/null
+++ b/dts/Bindings/media/imx.txt
@@ -0,0 +1,53 @@
+Freescale i.MX Media Video Device
+=================================
+
+Video Media Controller node
+---------------------------
+
+This is the media controller node for video capture support. It is a
+virtual device that lists the camera serial interface nodes that the
+media device will control.
+
+Required properties:
+- compatible : "fsl,imx-capture-subsystem";
+- ports : Should contain a list of phandles pointing to camera
+ sensor interface ports of IPU devices
+
+example:
+
+capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu1_csi0>, <&ipu1_csi1>;
+};
+
+
+mipi_csi2 node
+--------------
+
+This is the device node for the MIPI CSI-2 Receiver core in the i.MX
+SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
+combined with a D-PHY core mixed into the same register block. In
+addition this device consists of an i.MX-specific "CSI2IPU gasket"
+glue logic, also controlled from the same register block. The CSI2IPU
+gasket demultiplexes the four virtual channel streams from the host
+controller's 32-bit output image bus onto four 16-bit parallel busses
+to the i.MX IPU CSIs.
+
+Required properties:
+- compatible : "fsl,imx6-mipi-csi2";
+- reg : physical base address and length of the register set;
+- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
+ (the D-PHY clock), video_27m (D-PHY PLL reference
+ clock), and eim_podf;
+- clock-names : must contain "dphy", "ref", "pix";
+- port@* : five port nodes must exist, containing endpoints
+ connecting to the source and sink devices according to
+ of_graph bindings. The first port is an input port,
+ connecting with a MIPI CSI-2 source, and ports 1
+ through 4 are output ports connecting with parallel
+ bus sink endpoint nodes and correspond to the four
+ MIPI CSI-2 virtual channel outputs.
+
+Optional properties:
+- interrupts : must contain two level-triggered interrupts,
+ in order: 100 and 101;
diff --git a/dts/Bindings/media/mediatek-mdp.txt b/dts/Bindings/media/mediatek-mdp.txt
index 4182063a54..0d03e3ae2b 100644
--- a/dts/Bindings/media/mediatek-mdp.txt
+++ b/dts/Bindings/media/mediatek-mdp.txt
@@ -2,7 +2,7 @@
Media Data Path is used for scaling and color space conversion.
-Required properties (controller (parent) node):
+Required properties (controller node):
- compatible: "mediatek,mt8173-mdp"
- mediatek,vpu: the node of video processor unit, see
Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
@@ -32,21 +32,16 @@ Required properties (DMA function blocks, child node):
for details.
Example:
-mdp {
- compatible = "mediatek,mt8173-mdp";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- mediatek,vpu = <&vpu>;
-
mdp_rdma0: rdma@14001000 {
compatible = "mediatek,mt8173-mdp-rdma";
+ "mediatek,mt8173-mdp";
reg = <0 0x14001000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mediatek,larb = <&larb0>;
+ mediatek,vpu = <&vpu>;
};
mdp_rdma1: rdma@14002000 {
@@ -106,4 +101,3 @@ mdp {
iommus = <&iommu M4U_PORT_MDP_WROT1>;
mediatek,larb = <&larb4>;
};
-};
diff --git a/dts/Bindings/media/qcom,venus.txt b/dts/Bindings/media/qcom,venus.txt
new file mode 100644
index 0000000000..2693449daf
--- /dev/null
+++ b/dts/Bindings/media/qcom,venus.txt
@@ -0,0 +1,107 @@
+* Qualcomm Venus video encoder/decoder accelerators
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value should contain one of:
+ - "qcom,msm8916-venus"
+ - "qcom,msm8996-venus"
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register base address and length of the register map.
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Should contain interrupt line number.
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A List of phandle and clock specifier pairs as listed
+ in clock-names property.
+- clock-names:
+ Usage: required for msm8916
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "core" Core video accelerator clock
+ - "iface" Video accelerator AHB clock
+ - "bus" Video accelerator AXI clock
+- clock-names:
+ Usage: required for msm8996
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "core" Core video accelerator clock
+ - "iface" Video accelerator AHB clock
+ - "bus" Video accelerator AXI clock
+ - "mbus" Video MAXI clock
+- power-domains:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pairs to the
+ power domain which is responsible for collapsing
+ and restoring power to the peripheral.
+- iommus:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and IOMMU specifier pairs.
+- memory-region:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reserved-memory for the firmware
+ memory region.
+
+* Subnodes
+The Venus video-codec node must contain two subnodes representing
+video-decoder and video-encoder.
+
+Every of video-encoder or video-decoder subnode should have:
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value should contain "venus-decoder" or "venus-encoder"
+- clocks:
+ Usage: required for msm8996
+ Value type: <prop-encoded-array>
+ Definition: A List of phandle and clock specifier pairs as listed
+ in clock-names property.
+- clock-names:
+ Usage: required for msm8996
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "core" Subcore video accelerator clock
+
+- power-domains:
+ Usage: required for msm8996
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pairs to the
+ power domain which is responsible for collapsing
+ and restoring power to the subcore.
+
+* An Example
+ video-codec@1d00000 {
+ compatible = "qcom,msm8916-venus";
+ reg = <0x01d00000 0xff000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>;
+ clock-names = "core", "iface", "bus";
+ power-domains = <&gcc VENUS_GDSC>;
+ iommus = <&apps_iommu 5>;
+ memory-region = <&venus_mem>;
+
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ };
+ };
diff --git a/dts/Bindings/media/rcar_vin.txt b/dts/Bindings/media/rcar_vin.txt
index 6a4e61cbe0..6e4ef8caf7 100644
--- a/dts/Bindings/media/rcar_vin.txt
+++ b/dts/Bindings/media/rcar_vin.txt
@@ -1,5 +1,5 @@
-Renesas RCar Video Input driver (rcar_vin)
-------------------------------------------
+Renesas R-Car Video Input driver (rcar_vin)
+-------------------------------------------
The rcar_vin device provides video input capabilities for the Renesas R-Car
family of devices. The current blocks are always slaves and suppot one input
diff --git a/dts/Bindings/media/renesas,drif.txt b/dts/Bindings/media/renesas,drif.txt
new file mode 100644
index 0000000000..39516b94c2
--- /dev/null
+++ b/dts/Bindings/media/renesas,drif.txt
@@ -0,0 +1,176 @@
+Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
+------------------------------------------------------------
+
+R-Car Gen3 DRIF is a SPI like receive only slave device. A general
+representation of DRIF interfacing with a master device is shown below.
+
++---------------------+ +---------------------+
+| |-----SCK------->|CLK |
+| Master |-----SS-------->|SYNC DRIFn (slave) |
+| |-----SD0------->|D0 |
+| |-----SD1------->|D1 |
++---------------------+ +---------------------+
+
+As per datasheet, each DRIF channel (drifn) is made up of two internal
+channels (drifn0 & drifn1). These two internal channels share the common
+CLK & SYNC. Each internal channel has its own dedicated resources like
+irq, dma channels, address space & clock. This internal split is not
+visible to the external master device.
+
+The device tree model represents each internal channel as a separate node.
+The internal channels sharing the CLK & SYNC are tied together by their
+phandles using a property called "renesas,bonding". For the rest of
+the documentation, unless explicitly stated, the word channel implies an
+internal channel.
+
+When both internal channels are enabled they need to be managed together
+as one (i.e.) they cannot operate alone as independent devices. Out of the
+two, one of them needs to act as a primary device that accepts common
+properties of both the internal channels. This channel is identified by a
+property called "renesas,primary-bond".
+
+To summarize,
+ - When both the internal channels that are bonded together are enabled,
+ the zeroth channel is selected as primary-bond. This channels accepts
+ properties common to all the members of the bond.
+ - When only one of the bonded channels need to be enabled, the property
+ "renesas,bonding" or "renesas,primary-bond" will have no effect. That
+ enabled channel can act alone as any other independent device.
+
+Required properties of an internal channel:
+-------------------------------------------
+- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
+ "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: offset and length of that channel.
+- interrupts: associated with that channel.
+- clocks: phandle and clock specifier of that channel.
+- clock-names: clock input name string: "fck".
+- dmas: phandles to the DMA channels.
+- dma-names: names of the DMA channel: "rx".
+- renesas,bonding: phandle to the other channel.
+
+Optional properties of an internal channel:
+-------------------------------------------
+- power-domains: phandle to the respective power domain.
+
+Required properties of an internal channel when:
+ - It is the only enabled channel of the bond (or)
+ - If it acts as primary among enabled bonds
+--------------------------------------------------------
+- pinctrl-0: pin control group to be used for this channel.
+- pinctrl-names: must be "default".
+- renesas,primary-bond: empty property indicating the channel acts as primary
+ among the bonded channels.
+- port: child port node corresponding to the data input, in accordance with
+ the video interface bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The port
+ node must contain at least one endpoint.
+
+Optional endpoint property:
+---------------------------
+- sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
+ This property maps to SYNCAC bit in the hardware manual. The
+ default is 1 (active high).
+
+Example:
+--------
+
+(1) Both internal channels enabled:
+-----------------------------------
+
+When interfacing with a third party tuner device with two data pins as shown
+below.
+
++---------------------+ +---------------------+
+| |-----SCK------->|CLK |
+| Master |-----SS-------->|SYNC DRIFn (slave) |
+| |-----SD0------->|D0 |
+| |-----SD1------->|D1 |
++---------------------+ +---------------------+
+
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif01>;
+ renesas,primary-bond;
+ pinctrl-0 = <&drif0_pins>;
+ pinctrl-names = "default";
+ port {
+ drif0_ep: endpoint {
+ remote-endpoint = <&tuner_ep>;
+ };
+ };
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif00>;
+ };
+
+
+(2) Internal channel 1 alone is enabled:
+----------------------------------------
+
+When interfacing with a third party tuner device with one data pin as shown
+below.
+
++---------------------+ +---------------------+
+| |-----SCK------->|CLK |
+| Master |-----SS-------->|SYNC DRIFn (slave) |
+| | |D0 (unused) |
+| |-----SD-------->|D1 |
++---------------------+ +---------------------+
+
+ drif00: rif@e6f40000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f40000 0 0x64>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x20>, <&dmac2 0x20>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif01>;
+ };
+
+ drif01: rif@e6f50000 {
+ compatible = "renesas,r8a7795-drif",
+ "renesas,rcar-gen3-drif";
+ reg = <0 0xe6f50000 0 0x64>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>;
+ clock-names = "fck";
+ dmas = <&dmac1 0x22>, <&dmac2 0x22>;
+ dma-names = "rx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ renesas,bonding = <&drif00>;
+ pinctrl-0 = <&drif0_pins>;
+ pinctrl-names = "default";
+ port {
+ drif0_ep: endpoint {
+ remote-endpoint = <&tuner_ep>;
+ sync-active = <0>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/s5p-cec.txt b/dts/Bindings/media/s5p-cec.txt
index 4bb08d9d94..1b1a10ba48 100644
--- a/dts/Bindings/media/s5p-cec.txt
+++ b/dts/Bindings/media/s5p-cec.txt
@@ -15,7 +15,11 @@ Required properties:
- clock-names : from common clock binding: must contain "hdmicec",
corresponding to entry in the clocks property.
- samsung,syscon-phandle - phandle to the PMU system controller
- - hdmi-phandle - phandle to the HDMI controller
+ - hdmi-phandle - phandle to the HDMI controller, see also cec.txt.
+
+Optional:
+ - needs-hpd : if present the CEC support is only available when the HPD
+ is high. See cec.txt for more details.
Example:
diff --git a/dts/Bindings/media/st,stm32-cec.txt b/dts/Bindings/media/st,stm32-cec.txt
new file mode 100644
index 0000000000..6be2381c18
--- /dev/null
+++ b/dts/Bindings/media/st,stm32-cec.txt
@@ -0,0 +1,19 @@
+STMicroelectronics STM32 CEC driver
+
+Required properties:
+ - compatible : value should be "st,stm32-cec"
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+ - clocks : from common clock binding: handle to CEC clocks
+ - clock-names : from common clock binding: must be "cec" and "hdmi-cec".
+ - interrupts : CEC interrupt number to the CPU.
+
+Example for stm32f746:
+
+cec: cec@40006c00 {
+ compatible = "st,stm32-cec";
+ reg = <0x40006C00 0x400>;
+ interrupts = <94>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
+ clock-names = "cec", "hdmi-cec";
+};
diff --git a/dts/Bindings/media/st,stm32-dcmi.txt b/dts/Bindings/media/st,stm32-dcmi.txt
new file mode 100644
index 0000000000..249790a930
--- /dev/null
+++ b/dts/Bindings/media/st,stm32-dcmi.txt
@@ -0,0 +1,45 @@
+STMicroelectronics STM32 Digital Camera Memory Interface (DCMI)
+
+Required properties:
+- compatible: "st,stm32-dcmi"
+- reg: physical base address and length of the registers set for the device
+- interrupts: should contain IRQ line for the DCMI
+- resets: reference to a reset controller,
+ see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt
+- clocks: list of clock specifiers, corresponding to entries in
+ the clock-names property
+- clock-names: must contain "mclk", which is the DCMI peripherial clock
+- pinctrl: the pincontrol settings to configure muxing properly
+ for pins that connect to DCMI device.
+ See Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt.
+- dmas: phandle to DMA controller node,
+ see Documentation/devicetree/bindings/dma/stm32-dma.txt
+- dma-names: must contain "tx", which is the transmit channel from DCMI to DMA
+
+DCMI supports a single port node with parallel bus. It should contain one
+'port' child node with child 'endpoint' node. Please refer to the bindings
+defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+ dcmi: dcmi@50050000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x50050000 0x400>;
+ interrupts = <78>;
+ resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
+ clock-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcmi_pins>;
+ dmas = <&dma2 1 1 0x414 0x3>;
+ dma-names = "tx";
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <...>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/stih-cec.txt b/dts/Bindings/media/stih-cec.txt
index 289a08b336..8be2a040c6 100644
--- a/dts/Bindings/media/stih-cec.txt
+++ b/dts/Bindings/media/stih-cec.txt
@@ -9,7 +9,7 @@ Required properties:
- pinctrl-names: Contains only one value - "default"
- pinctrl-0: Specifies the pin control groups used for CEC hardware.
- resets: Reference to a reset controller
- - hdmi-phandle: Phandle to the HDMI controller
+ - hdmi-phandle: Phandle to the HDMI controller, see also cec.txt.
Example for STIH407:
diff --git a/dts/Bindings/media/video-mux.txt b/dts/Bindings/media/video-mux.txt
new file mode 100644
index 0000000000..63b9dc913e
--- /dev/null
+++ b/dts/Bindings/media/video-mux.txt
@@ -0,0 +1,60 @@
+Video Multiplexer
+=================
+
+Video multiplexers allow to select between multiple input ports. Video received
+on the active input port is passed through to the output port. Muxes described
+by this binding are controlled by a multiplexer controller that is described by
+the bindings in Documentation/devicetree/bindings/mux/mux-controller.txt
+
+Required properties:
+- compatible : should be "video-mux"
+- mux-controls : mux controller node to use for operating the mux
+- #address-cells: should be <1>
+- #size-cells: should be <0>
+- port@*: at least three port nodes containing endpoints connecting to the
+ source and sink devices according to of_graph bindings. The last port is
+ the output port, all others are inputs.
+
+Optionally, #address-cells, #size-cells, and port nodes can be grouped under a
+ports node as described in Documentation/devicetree/bindings/graph.txt.
+
+Example:
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ video-mux {
+ compatible = "video-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mux_in0: endpoint {
+ remote-endpoint = <&video_source0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mux_in1: endpoint {
+ remote-endpoint = <&video_source1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mux_out: endpoint {
+ remote-endpoint = <&capture_interface_in>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt
index 8f2e282223..b37bdde5cf 100644
--- a/dts/Bindings/mfd/arizona.txt
+++ b/dts/Bindings/mfd/arizona.txt
@@ -30,7 +30,8 @@ Required properties:
- gpio-controller : Indicates this device is a GPIO controller.
- #gpio-cells : Must be 2. The first cell is the pin number and the
- second cell is used to specify optional parameters (currently unused).
+ second cell is used to specify optional parameters, see ../gpio/gpio.txt
+ for details.
- AVDD-supply, DBVDD1-supply, CPVDD-supply : Power supplies for the device,
as covered in Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/dts/Bindings/mfd/hi6421.txt b/dts/Bindings/mfd/hi6421.txt
index 0d5a4466a4..22da96d344 100644
--- a/dts/Bindings/mfd/hi6421.txt
+++ b/dts/Bindings/mfd/hi6421.txt
@@ -1,7 +1,9 @@
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
Required parent device properties:
-- compatible : contains "hisilicon,hi6421-pmic";
+- compatible : One of the following chip-specific strings:
+ "hisilicon,hi6421-pmic";
+ "hisilicon,hi6421v530-pmic";
- reg : register range space of hi6421;
Supported Hi6421 sub-devices include:
diff --git a/dts/Bindings/mfd/lp87565.txt b/dts/Bindings/mfd/lp87565.txt
new file mode 100644
index 0000000000..a48df7c08a
--- /dev/null
+++ b/dts/Bindings/mfd/lp87565.txt
@@ -0,0 +1,43 @@
+TI LP87565 PMIC MFD driver
+
+Required properties:
+ - compatible: "ti,lp87565", "ti,lp87565-q1"
+ - reg: I2C slave address.
+ - gpio-controller: Marks the device node as a GPIO Controller.
+ - #gpio-cells: Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../gpio/gpio.txt for more information.
+ - xxx-in-supply: Phandle to parent supply node of each regulator
+ populated under regulators node. xxx should match
+ the supply_name populated in driver.
+Example:
+
+lp87565_pmic: pmic@60 {
+ compatible = "ti,lp87565-q1";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ buck10-in-supply = <&vsys_3v3>;
+ buck23-in-supply = <&vsys_3v3>;
+
+ regulators: regulators {
+ buck10_reg: buck10 {
+ /* VDD_MPU */
+ regulator-name = "buck10";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck23_reg: buck23 {
+ /* VDD_GPU */
+ regulator-name = "buck23";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/dts/Bindings/mfd/tps65910.txt b/dts/Bindings/mfd/tps65910.txt
index 38833e63a5..8af1202b38 100644
--- a/dts/Bindings/mfd/tps65910.txt
+++ b/dts/Bindings/mfd/tps65910.txt
@@ -61,6 +61,10 @@ Optional properties:
There should be 9 entries here, one for each gpio.
- ti,system-power-controller: Telling whether or not this pmic is controlling
the system power.
+- ti,sleep-enable: Enable SLEEP state.
+- ti,sleep-keep-therm: Keep thermal monitoring on in sleep state.
+- ti,sleep-keep-ck32k: Keep the 32KHz clock output on in sleep state.
+- ti,sleep-keep-hsclk: Keep high speed internal clock on in sleep state.
Regulator Optional properties:
- ti,regulator-ext-sleep-control: enable external sleep
diff --git a/dts/Bindings/misc/allwinner,syscon.txt b/dts/Bindings/misc/allwinner,syscon.txt
new file mode 100644
index 0000000000..31494a24fe
--- /dev/null
+++ b/dts/Bindings/misc/allwinner,syscon.txt
@@ -0,0 +1,20 @@
+* Allwinner sun8i system controller
+
+This file describes the bindings for the system controller present in
+Allwinner SoC H3, A83T and A64.
+The principal function of this syscon is to control EMAC PHY choice and
+config.
+
+Required properties for the system controller:
+- reg: address and length of the register for the device.
+- compatible: should be "syscon" and one of the following string:
+ "allwinner,sun8i-h3-system-controller"
+ "allwinner,sun8i-v3s-system-controller"
+ "allwinner,sun50i-a64-system-controller"
+ "allwinner,sun8i-a83t-system-controller"
+
+Example:
+syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller", "syscon";
+ reg = <0x01c00000 0x1000>;
+};
diff --git a/dts/Bindings/mmc/fsl-esdhc.txt b/dts/Bindings/mmc/fsl-esdhc.txt
index dedfb02c74..a2cf5e1c87 100644
--- a/dts/Bindings/mmc/fsl-esdhc.txt
+++ b/dts/Bindings/mmc/fsl-esdhc.txt
@@ -7,6 +7,20 @@ This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc driver.
Required properties:
+ - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
+ Possible compatibles for PowerPC:
+ "fsl,mpc8536-esdhc"
+ "fsl,mpc8378-esdhc"
+ "fsl,p2020-esdhc"
+ "fsl,p4080-esdhc"
+ "fsl,t1040-esdhc"
+ "fsl,t4240-esdhc"
+ Possible compatibles for ARM:
+ "fsl,ls1012a-esdhc"
+ "fsl,ls1088a-esdhc"
+ "fsl,ls1043a-esdhc"
+ "fsl,ls1046a-esdhc"
+ "fsl,ls2080a-esdhc"
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.
diff --git a/dts/Bindings/mmc/k3-dw-mshc.txt b/dts/Bindings/mmc/k3-dw-mshc.txt
index df370585cb..8af1afcb86 100644
--- a/dts/Bindings/mmc/k3-dw-mshc.txt
+++ b/dts/Bindings/mmc/k3-dw-mshc.txt
@@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be one of the following.
+ - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index 520d61dad6..49ed3ad252 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
@@ -31,6 +32,10 @@ Optional Properties:
probing, low speeds or in case where all phases work at tuning time.
If not specified 0 deg will be used.
+* rockchip,desired-num-phases: The desired number of times that the host
+ execute tuning when needed. If not specified, the host will do tuning
+ for 360 times, namely tuning for each degree.
+
Example:
rkdwmmc0@12200000 {
diff --git a/dts/Bindings/mmc/ti-omap-hsmmc.txt b/dts/Bindings/mmc/ti-omap-hsmmc.txt
index 74166a0d46..0e026c151c 100644
--- a/dts/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/dts/Bindings/mmc/ti-omap-hsmmc.txt
@@ -18,7 +18,7 @@ Required properties:
Optional properties:
ti,dual-volt: boolean, supports dual voltage cards
<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux" etc
+"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
ti,non-removable: non-removable slot (like eMMC)
ti,needs-special-reset: Requires a special softreset sequence
ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
diff --git a/dts/Bindings/mtd/atmel-nand.txt b/dts/Bindings/mtd/atmel-nand.txt
index f6bee57e45..9bb66e4766 100644
--- a/dts/Bindings/mtd/atmel-nand.txt
+++ b/dts/Bindings/mtd/atmel-nand.txt
@@ -59,8 +59,22 @@ Required properties:
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.
+* SAMA5 NFC I/O bindings:
+
+SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
+operations. This interface to this logic is placed in a separate I/O range and
+should thus have its own DT node.
+
+- compatible: should be "atmel,sama5d3-nfc-io", "syscon".
+- reg: should contain the I/O range used to interact with the NFC logic.
+
Example:
+ nfc_io: nfc-io@70000000 {
+ compatible = "atmel,sama5d3-nfc-io", "syscon";
+ reg = <0x70000000 0x8000000>;
+ };
+
pmecc: ecc-engine@ffffc070 {
compatible = "atmel,at91sam9g45-pmecc";
reg = <0xffffc070 0x490>,
diff --git a/dts/Bindings/mtd/denali-nand.txt b/dts/Bindings/mtd/denali-nand.txt
index e593bbeb21..504291d2e5 100644
--- a/dts/Bindings/mtd/denali-nand.txt
+++ b/dts/Bindings/mtd/denali-nand.txt
@@ -3,10 +3,23 @@
Required properties:
- compatible : should be one of the following:
"altr,socfpga-denali-nand" - for Altera SOCFPGA
+ "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
+ "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
- reg : should contain registers location and length for data and reg.
- reg-names: Should contain the reg names "nand_data" and "denali_reg"
- interrupts : The interrupt number.
+Optional properties:
+ - nand-ecc-step-size: see nand.txt for details. If present, the value must be
+ 512 for "altr,socfpga-denali-nand"
+ 1024 for "socionext,uniphier-denali-nand-v5a"
+ 1024 for "socionext,uniphier-denali-nand-v5b"
+ - nand-ecc-strength: see nand.txt for details. Valid values are:
+ 8, 15 for "altr,socfpga-denali-nand"
+ 8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
+ 8, 16 for "socionext,uniphier-denali-nand-v5b"
+ - nand-ecc-maximize: see nand.txt for details
+
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/dts/Bindings/mtd/elm.txt b/dts/Bindings/mtd/elm.txt
index 8c1528c421..59ddc61c10 100644
--- a/dts/Bindings/mtd/elm.txt
+++ b/dts/Bindings/mtd/elm.txt
@@ -1,7 +1,7 @@
Error location module
Required properties:
-- compatible: Must be "ti,am33xx-elm"
+- compatible: Must be "ti,am3352-elm"
- reg: physical base address and size of the registers map.
- interrupts: Interrupt number for the elm.
diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt
index 174f68c26c..dd55904559 100644
--- a/dts/Bindings/mtd/gpmc-nand.txt
+++ b/dts/Bindings/mtd/gpmc-nand.txt
@@ -5,7 +5,7 @@ the GPMC controller with a name of "nand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand.txt
diff --git a/dts/Bindings/mtd/gpmc-nor.txt b/dts/Bindings/mtd/gpmc-nor.txt
index 4828c17bb7..131d3a74d0 100644
--- a/dts/Bindings/mtd/gpmc-nor.txt
+++ b/dts/Bindings/mtd/gpmc-nor.txt
@@ -5,7 +5,7 @@ child nodes of the GPMC controller with a name of "nor".
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
@@ -28,7 +28,7 @@ Required properties:
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
- Documentation/devicetree/bindings/bus/ti-gpmc.txt
+ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Optional properties for partition table parsing:
- #address-cells: should be set to 1
diff --git a/dts/Bindings/mtd/gpmc-onenand.txt b/dts/Bindings/mtd/gpmc-onenand.txt
index 5d8fa527c4..b6e8bfd024 100644
--- a/dts/Bindings/mtd/gpmc-onenand.txt
+++ b/dts/Bindings/mtd/gpmc-onenand.txt
@@ -5,7 +5,7 @@ the GPMC controller with a name of "onenand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
diff --git a/dts/Bindings/mtd/gpmi-nand.txt b/dts/Bindings/mtd/gpmi-nand.txt
index d02acaff3c..b289ef3c1b 100644
--- a/dts/Bindings/mtd/gpmi-nand.txt
+++ b/dts/Bindings/mtd/gpmi-nand.txt
@@ -4,7 +4,12 @@ The GPMI nand controller provides an interface to control the
NAND flash chips.
Required properties:
- - compatible : should be "fsl,<chip>-gpmi-nand"
+ - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
+ * imx23
+ * imx28
+ * imx6q
+ * imx6sx
+ * imx7d
- reg : should contain registers location and length for gpmi and bch.
- reg-names: Should contain the reg names "gpmi-nand" and "bch"
- interrupts : BCH interrupt number.
@@ -13,6 +18,13 @@ Required properties:
and GPMI DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
+ - clocks : clocks phandle and clock specifier corresponding to each clock
+ specified in clock-names.
+ - clock-names : The "gpmi_io" clock is always required. Which clocks are
+ exactly required depends on chip:
+ * imx23/imx28 : "gpmi_io"
+ * imx6q/sx : "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"
+ * imx7d : "gpmi_io", "gpmi_bch_apb"
Optional properties:
- nand-on-flash-bbt: boolean to enable on flash bbt option if not
diff --git a/dts/Bindings/mtd/microchip,mchp23k256.txt b/dts/Bindings/mtd/microchip,mchp23k256.txt
new file mode 100644
index 0000000000..7328eb92a0
--- /dev/null
+++ b/dts/Bindings/mtd/microchip,mchp23k256.txt
@@ -0,0 +1,18 @@
+* MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
+
+Required properties:
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+ representing partitions.
+- compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024"
+- reg : Chip-Select number
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
+
+Example:
+
+ spi-sram@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,mchp23k256";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
diff --git a/dts/Bindings/mtd/mtk-nand.txt b/dts/Bindings/mtd/mtk-nand.txt
index 069c192ed5..dbf9e054c1 100644
--- a/dts/Bindings/mtd/mtk-nand.txt
+++ b/dts/Bindings/mtd/mtk-nand.txt
@@ -12,7 +12,8 @@ tree nodes.
The first part of NFC is NAND Controller Interface (NFI) HW.
Required NFI properties:
-- compatible: Should be "mediatek,mtxxxx-nfc".
+- compatible: Should be one of "mediatek,mt2701-nfc",
+ "mediatek,mt2712-nfc".
- reg: Base physical address and size of NFI.
- interrupts: Interrupts of NFI.
- clocks: NFI required clocks.
@@ -141,7 +142,7 @@ Example:
==============
Required BCH properties:
-- compatible: Should be "mediatek,mtxxxx-ecc".
+- compatible: Should be one of "mediatek,mt2701-ecc", "mediatek,mt2712-ecc".
- reg: Base physical address and size of ECC.
- interrupts: Interrupts of ECC.
- clocks: ECC required clocks.
diff --git a/dts/Bindings/mtd/nand.txt b/dts/Bindings/mtd/nand.txt
index b056016000..133f381371 100644
--- a/dts/Bindings/mtd/nand.txt
+++ b/dts/Bindings/mtd/nand.txt
@@ -21,7 +21,7 @@ Optional NAND chip properties:
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome",
- "hw_oob_first".
+ "hw_oob_first", "on-die".
Deprecated values:
"soft_bch": use "soft" and nand-ecc-algo instead
- nand-ecc-algo: string, algorithm of NAND ECC.
diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt
index 81a224da63..36f3b769a6 100644
--- a/dts/Bindings/mtd/partition.txt
+++ b/dts/Bindings/mtd/partition.txt
@@ -1,29 +1,49 @@
-Representing flash partitions in devicetree
+Flash partitions in device tree
+===============================
-Partitions can be represented by sub-nodes of an mtd device. This can be used
+Flash devices can be partitioned into one or more functional ranges (e.g. "boot
+code", "nvram", "kernel").
+
+Different devices may be partitioned in a different ways. Some may use a fixed
+flash layout set at production time. Some may use on-flash table that describes
+the geometry and naming/purpose of each functional region. It is also possible
+to see these methods mixed.
+
+To assist system software in locating partitions, we allow describing which
+method is used for a given flash device. To describe the method there should be
+a subnode of the flash device that is named 'partitions'. It must have a
+'compatible' property, which is used to identify the method to use.
+
+We currently only document a binding for fixed layouts.
+
+
+Fixed Partitions
+================
+
+Partitions can be represented by sub-nodes of a flash device. This can be used
on platforms which have strong conventions about which portions of a flash are
used for what purposes, but which don't use an on-flash partition table such
as RedBoot.
-The partition table should be a subnode of the mtd node and should be named
+The partition table should be a subnode of the flash node and should be named
'partitions'. This node should have the following property:
- compatible : (required) must be "fixed-partitions"
Partitions are then defined in subnodes of the partitions node.
-For backwards compatibility partitions as direct subnodes of the mtd device are
+For backwards compatibility partitions as direct subnodes of the flash device are
supported. This use is discouraged.
NOTE: also for backwards compatibility, direct subnodes that have a compatible
string are not considered partitions, as they may be used for other bindings.
#address-cells & #size-cells must both be present in the partitions subnode of the
-mtd device. There are two valid values for both:
+flash device. There are two valid values for both:
<1>: for partitions that require a single 32-bit cell to represent their
size/address (aka the value is below 4 GiB)
<2>: for partitions that require two 32-bit cells to represent their
size/address (aka the value is 4 GiB or greater).
Required properties:
-- reg : The partition's offset and size within the mtd bank.
+- reg : The partition's offset and size within the flash
Optional properties:
- label : The label / name for this partition. If omitted, the label is taken
diff --git a/dts/Bindings/mux/adi,adg792a.txt b/dts/Bindings/mux/adi,adg792a.txt
new file mode 100644
index 0000000000..96b787a69f
--- /dev/null
+++ b/dts/Bindings/mux/adi,adg792a.txt
@@ -0,0 +1,75 @@
+Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers
+
+Required properties:
+- compatible : "adi,adg792a" or "adi,adg792g"
+- #mux-control-cells : <0> if parallel (the three muxes are bound together
+ with a single mux controller controlling all three muxes), or <1> if
+ not (one mux controller for each mux).
+* Standard mux-controller bindings as described in mux-controller.txt
+
+Optional properties for ADG792G:
+- gpio-controller : if present, #gpio-cells below is required.
+- #gpio-cells : should be <2>
+ - First cell is the GPO line number, i.e. 0 or 1
+ - Second cell is used to specify active high (0)
+ or active low (1)
+
+Optional properties:
+- idle-state : if present, array of states that the mux controllers will have
+ when idle. The special state MUX_IDLE_AS_IS is the default and
+ MUX_IDLE_DISCONNECT is also supported.
+
+States 0 through 3 correspond to signals A through D in the datasheet.
+
+Example:
+
+ /*
+ * Three independent mux controllers (of which one is used).
+ * Mux 0 is disconnected when idle, mux 1 idles in the previously
+ * selected state and mux 2 idles with signal B.
+ */
+ &i2c0 {
+ mux: mux-controller@50 {
+ compatible = "adi,adg792a";
+ reg = <0x50>;
+ #mux-control-cells = <1>;
+
+ idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>;
+ };
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux 2>;
+
+ channels = "sync-1", "", "out";
+ };
+
+
+ /*
+ * Three parallel muxes with one mux controller, useful e.g. if
+ * the adc is differential, thus needing two signals to be muxed
+ * simultaneously for correct operation.
+ */
+ &i2c0 {
+ pmux: mux-controller@50 {
+ compatible = "adi,adg792a";
+ reg = <0x50>;
+ #mux-control-cells = <0>;
+
+ idle-state = <1>;
+ };
+ };
+
+ diff-adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&pmux>;
+
+ channels = "sync-1", "", "out";
+ };
diff --git a/dts/Bindings/mux/gpio-mux.txt b/dts/Bindings/mux/gpio-mux.txt
new file mode 100644
index 0000000000..b8f746344d
--- /dev/null
+++ b/dts/Bindings/mux/gpio-mux.txt
@@ -0,0 +1,69 @@
+GPIO-based multiplexer controller bindings
+
+Define what GPIO pins are used to control a multiplexer. Or several
+multiplexers, if the same pins control more than one multiplexer.
+
+Required properties:
+- compatible : "gpio-mux"
+- mux-gpios : list of gpios used to control the multiplexer, least
+ significant bit first.
+- #mux-control-cells : <0>
+* Standard mux-controller bindings as decribed in mux-controller.txt
+
+Optional properties:
+- idle-state : if present, the state the mux will have when idle. The
+ special state MUX_IDLE_AS_IS is the default.
+
+The multiplexer state is defined as the number represented by the
+multiplexer GPIO pins, where the first pin is the least significant
+bit. An active pin is a binary 1, an inactive pin is a binary 0.
+
+Example:
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ /* ... */
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ /* ... */
+ };
+ };
+ };
diff --git a/dts/Bindings/mux/mmio-mux.txt b/dts/Bindings/mux/mmio-mux.txt
new file mode 100644
index 0000000000..a9bfb4d8b6
--- /dev/null
+++ b/dts/Bindings/mux/mmio-mux.txt
@@ -0,0 +1,60 @@
+MMIO register bitfield-based multiplexer controller bindings
+
+Define register bitfields to be used to control multiplexers. The parent
+device tree node must be a syscon node to provide register access.
+
+Required properties:
+- compatible : "mmio-mux"
+- #mux-control-cells : <1>
+- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
+ pairs, each describing a single mux control.
+* Standard mux-controller bindings as decribed in mux-controller.txt
+
+Optional properties:
+- idle-states : if present, the state the muxes will have when idle. The
+ special state MUX_IDLE_AS_IS is the default.
+
+The multiplexer state of each multiplexer is defined as the value of the
+bitfield described by the corresponding register offset and bitfield mask pair
+in the mux-reg-masks array, accessed through the parent syscon.
+
+Example:
+
+ syscon {
+ compatible = "syscon";
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+
+ mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
+ <0x3 0x40>, /* 1: reg 0x3, bit 6 */
+ idle-states = <MUX_IDLE_AS_IS>, <0>;
+ };
+ };
+
+ video-mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+
+ ports {
+ /* inputs 0..3 */
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ port@2 {
+ reg = <2>;
+ };
+ port@3 {
+ reg = <3>;
+ };
+
+ /* output */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mux/mux-controller.txt b/dts/Bindings/mux/mux-controller.txt
new file mode 100644
index 0000000000..4f47e4bd2f
--- /dev/null
+++ b/dts/Bindings/mux/mux-controller.txt
@@ -0,0 +1,157 @@
+Common multiplexer controller bindings
+======================================
+
+A multiplexer (or mux) controller will have one, or several, consumer devices
+that uses the mux controller. Thus, a mux controller can possibly control
+several parallel multiplexers. Presumably there will be at least one
+multiplexer needed by each consumer, but a single mux controller can of course
+control several multiplexers for a single consumer.
+
+A mux controller provides a number of states to its consumers, and the state
+space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
+0-7 for an 8-way multiplexer, etc.
+
+
+Consumers
+---------
+
+Mux controller consumers should specify a list of mux controllers that they
+want to use with a property containing a 'mux-ctrl-list':
+
+ mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
+ single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
+ mux-ctrl-phandle : phandle to mux controller node
+ mux-ctrl-specifier : array of #mux-control-cells specifying the
+ given mux controller (controller specific)
+
+Mux controller properties should be named "mux-controls". The exact meaning of
+each mux controller property must be documented in the device tree binding for
+each consumer. An optional property "mux-control-names" may contain a list of
+strings to label each of the mux controllers listed in the "mux-controls"
+property.
+
+Drivers for devices that use more than a single mux controller can use the
+"mux-control-names" property to map the name of the requested mux controller
+to an index into the list given by the "mux-controls" property.
+
+mux-ctrl-specifier typically encodes the chip-relative mux controller number.
+If the mux controller chip only provides a single mux controller, the
+mux-ctrl-specifier can typically be left out.
+
+Example:
+
+ /* One consumer of a 2-way mux controller (one GPIO-line) */
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+ mux-control-names = "adc";
+
+ channels = "sync", "in";
+ };
+
+Note that in the example above, specifying the "mux-control-names" is redundant
+because there is only one mux controller in the list. However, if the driver
+for the consumer node in fact asks for a named mux controller, that name is of
+course still required.
+
+ /*
+ * Two consumers (one for an ADC line and one for an i2c bus) of
+ * parallel 4-way multiplexers controlled by the same two GPIO-lines.
+ */
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ /* ... */
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ /* ... */
+ };
+ };
+ };
+
+
+Mux controller nodes
+--------------------
+
+Mux controller nodes must specify the number of cells used for the
+specifier using the '#mux-control-cells' property.
+
+Optionally, mux controller nodes can also specify the state the mux should
+have when it is idle. The idle-state property is used for this. If the
+idle-state is not present, the mux controller is typically left as is when
+it is idle. For multiplexer chips that expose several mux controllers, the
+idle-state property is an array with one idle state for each mux controller.
+
+The special value (-1) may be used to indicate that the mux should be left
+as is when it is idle. This is the default, but can still be useful for
+mux controller chips with more than one mux controller, particularly when
+there is a need to "step past" a mux controller and set some other idle
+state for a mux controller with a higher index.
+
+Some mux controllers have the ability to disconnect the input/output of the
+multiplexer. Using this disconnected high-impedance state as the idle state
+is indicated with idle state (-2).
+
+These constants are available in
+
+ #include <dt-bindings/mux/mux.h>
+
+as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).
+
+An example mux controller node look like this (the adg972a chip is a triple
+4-way multiplexer):
+
+ mux: mux-controller@50 {
+ compatible = "adi,adg792a";
+ reg = <0x50>;
+ #mux-control-cells = <1>;
+
+ idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
+ };
diff --git a/dts/Bindings/net/brcm,amac.txt b/dts/Bindings/net/brcm,amac.txt
index 2fefa1a44a..ad16c1f481 100644
--- a/dts/Bindings/net/brcm,amac.txt
+++ b/dts/Bindings/net/brcm,amac.txt
@@ -11,6 +11,7 @@ Required properties:
- reg-names: Names of the registers.
"amac_base": Address and length of the GMAC registers
"idm_base": Address and length of the GMAC IDM registers
+ (required for NSP and Northstar2)
"nicpm_base": Address and length of the NIC Port Manager
registers (required for Northstar2)
- interrupts: Interrupt number
diff --git a/dts/Bindings/net/brcm,bgmac-nsp.txt b/dts/Bindings/net/brcm,bgmac-nsp.txt
deleted file mode 100644
index 022946caa7..0000000000
--- a/dts/Bindings/net/brcm,bgmac-nsp.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Broadcom GMAC Ethernet Controller Device Tree Bindings
--------------------------------------------------------------
-
-Required properties:
- - compatible: "brcm,bgmac-nsp"
- - reg: Address and length of the GMAC registers,
- Address and length of the GMAC IDM registers
- - reg-names: Names of the registers. Must have both "gmac_base" and
- "idm_base"
- - interrupts: Interrupt number
-
-Optional properties:
-- mac-address: See ethernet.txt file in the same directory
-
-Examples:
-
-gmac0: ethernet@18022000 {
- compatible = "brcm,bgmac-nsp";
- reg = <0x18022000 0x1000>,
- <0x18110000 0x1000>;
- reg-names = "gmac_base", "idm_base";
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-};
diff --git a/dts/Bindings/net/cortina.txt b/dts/Bindings/net/cortina.txt
new file mode 100644
index 0000000000..40d0bd9841
--- /dev/null
+++ b/dts/Bindings/net/cortina.txt
@@ -0,0 +1,21 @@
+Cortina Phy Driver Device Tree Bindings
+---------------------------------------
+
+CORTINA is a registered trademark of Cortina Systems, Inc.
+
+The driver supports the Cortina Electronic Dispersion Compensation (EDC)
+devices, equipped with clock and data recovery (CDR) circuits. These
+devices make use of registers that are not compatible with Clause 45 or
+Clause 22, therefore they need to be described using the
+"ethernet-phy-id" compatible.
+
+Since the driver only implements polling mode support, interrupts info
+can be skipped.
+
+Example (CS4340 phy):
+ mdio {
+ cs4340_phy@10 {
+ compatible = "ethernet-phy-id13e5.1002";
+ reg = <0x10>;
+ };
+ };
diff --git a/dts/Bindings/net/dsa/b53.txt b/dts/Bindings/net/dsa/b53.txt
index 8ec2ca21ad..8acf51a4df 100644
--- a/dts/Bindings/net/dsa/b53.txt
+++ b/dts/Bindings/net/dsa/b53.txt
@@ -13,6 +13,9 @@ Required properties:
"brcm,bcm5397"
"brcm,bcm5398"
+ For the BCM11360 SoC, must be:
+ "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
+
For the BCM5310x SoCs with an integrated switch, must be one of:
"brcm,bcm53010-srab"
"brcm,bcm53011-srab"
diff --git a/dts/Bindings/net/dsa/ksz.txt b/dts/Bindings/net/dsa/ksz.txt
new file mode 100644
index 0000000000..0ab8b39d0b
--- /dev/null
+++ b/dts/Bindings/net/dsa/ksz.txt
@@ -0,0 +1,72 @@
+Microchip KSZ Series Ethernet switches
+==================================
+
+Required properties:
+
+- compatible: For external switch chips, compatible string must be exactly one
+ of: "microchip,ksz9477"
+
+See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
+required and optional properties.
+
+Examples:
+
+Ethernet switch connected via SPI to the host, CPU port wired to eth0:
+
+ eth0: ethernet@10001000 {
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ spi1: spi@f8008000 {
+ pinctrl-0 = <&pinctrl_spi_ksz>;
+ cs-gpios = <&pioC 25 0>;
+ id = <1>;
+ status = "okay";
+
+ ksz9477: ksz9477@0 {
+ compatible = "microchip,ksz9477";
+ reg = <0>;
+
+ spi-max-frequency = <44000000>;
+ spi-cpha;
+ spi-cpol;
+
+ status = "okay";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ };
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&eth0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/net/dwmac-sun8i.txt b/dts/Bindings/net/dwmac-sun8i.txt
new file mode 100644
index 0000000000..725f3b1878
--- /dev/null
+++ b/dts/Bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,84 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
diff --git a/dts/Bindings/net/ethernet.txt b/dts/Bindings/net/ethernet.txt
index 3a6916909d..7da86f22a1 100644
--- a/dts/Bindings/net/ethernet.txt
+++ b/dts/Bindings/net/ethernet.txt
@@ -8,9 +8,11 @@ The following properties are common to the Ethernet controllers:
property;
- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
- the maximum frame size (there's contradiction in ePAPR).
+ the maximum frame size (there's contradiction in the Devicetree
+ Specification).
- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
standard property; supported values are:
+ * "internal"
* "mii"
* "gmii"
* "sgmii"
@@ -32,9 +34,13 @@ The following properties are common to the Ethernet controllers:
* "2000base-x",
* "2500base-x",
* "rxaui"
-- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
+ * "xaui"
+ * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+- phy-connection-type: the same as "phy-mode" property but described in the
+ Devicetree Specification;
- phy-handle: phandle, specifies a reference to a node representing a PHY
- device; this property is described in ePAPR and so preferred;
+ device; this property is described in the Devicetree Specification and so
+ preferred;
- phy: the same as "phy-handle" property, not recommended for new bindings.
- phy-device: the same as "phy-handle" property, not recommended for new
bindings.
diff --git a/dts/Bindings/powerpc/fsl/fman.txt b/dts/Bindings/net/fsl-fman.txt
index df873d1f3b..df873d1f3b 100644
--- a/dts/Bindings/powerpc/fsl/fman.txt
+++ b/dts/Bindings/net/fsl-fman.txt
diff --git a/dts/Bindings/net/gpmc-eth.txt b/dts/Bindings/net/gpmc-eth.txt
index ace4a64b36..f7da3d73ca 100644
--- a/dts/Bindings/net/gpmc-eth.txt
+++ b/dts/Bindings/net/gpmc-eth.txt
@@ -9,7 +9,7 @@ the GPMC controller with an "ethernet" name.
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For the properties relevant to the ethernet controller connected to the GPMC
refer to the binding documentation of the device. For example, the documentation
@@ -43,7 +43,7 @@ Required properties:
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
- Documentation/devicetree/bindings/bus/ti-gpmc.txt
+ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Example:
diff --git a/dts/Bindings/net/macb.txt b/dts/Bindings/net/macb.txt
index 1506e94861..27966ae741 100644
--- a/dts/Bindings/net/macb.txt
+++ b/dts/Bindings/net/macb.txt
@@ -22,6 +22,7 @@ Required properties:
Required elements: 'pclk', 'hclk'
Optional elements: 'tx_clk'
Optional elements: 'rx_clk' applies to cdns,zynqmp-gem
+ Optional elements: 'tsu_clk'
- clocks: Phandles to input clocks.
Optional properties for PHY child node:
diff --git a/dts/Bindings/net/marvell-orion-mdio.txt b/dts/Bindings/net/marvell-orion-mdio.txt
index ccdabdcc86..42cd81090a 100644
--- a/dts/Bindings/net/marvell-orion-mdio.txt
+++ b/dts/Bindings/net/marvell-orion-mdio.txt
@@ -1,12 +1,14 @@
* Marvell MDIO Ethernet Controller interface
The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x,
-MV78xx0, Armada 370 and Armada XP have an identical unit that provides
-an interface with the MDIO bus. This driver handles this MDIO
-interface.
+MV78xx0, Armada 370, Armada XP, Armada 7k and Armada 8k have an
+identical unit that provides an interface with the MDIO bus.
+Additionally, Armada 7k and Armada 8k has a second unit which
+provides an interface with the xMDIO bus. This driver handles
+these interfaces.
Required properties:
-- compatible: "marvell,orion-mdio"
+- compatible: "marvell,orion-mdio" or "marvell,xmdio"
- reg: address and length of the MDIO registers. When an interrupt is
not present, the length is the size of the SMI register (4 bytes)
otherwise it must be 0x84 bytes to cover the interrupt control
diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt
index c627bbb300..60c833d621 100644
--- a/dts/Bindings/net/nfc/trf7970a.txt
+++ b/dts/Bindings/net/nfc/trf7970a.txt
@@ -13,14 +13,10 @@ Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- autosuspend-delay: Specify autosuspend delay in milliseconds.
-- vin-voltage-override: Specify voltage of VIN pin in microvolts.
- irq-status-read-quirk: Specify that the trf7970a being used has the
"IRQ Status Read" erratum.
- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF"
erratum.
-- t5t-rmb-extra-byte-quirk: Specify that the trf7970a has the erratum
- where an extra byte is returned by Read Multiple Block commands issued
- to Type 5 tags.
- vdd-io-supply: Regulator specifying voltage for vdd-io
- clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz
@@ -37,15 +33,13 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
spi-max-frequency = <2000000>;
interrupt-parent = <&gpio2>;
interrupts = <14 0>;
- ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
- <&gpio2 5 GPIO_ACTIVE_LOW>;
+ ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>,
+ <&gpio2 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&ldo3_reg>;
- vin-voltage-override = <5000000>;
vdd-io-supply = <&ldo2_reg>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
- t5t-rmb-extra-byte-quirk;
clock-frequency = <27120000>;
status = "okay";
};
diff --git a/dts/Bindings/net/qca,qca7000.txt b/dts/Bindings/net/qca,qca7000.txt
new file mode 100644
index 0000000000..6d9efb2eb9
--- /dev/null
+++ b/dts/Bindings/net/qca,qca7000.txt
@@ -0,0 +1,88 @@
+* Qualcomm QCA7000
+
+The QCA7000 is a serial-to-powerline bridge with a host interface which could
+be configured either as SPI or UART slave. This configuration is done by
+the QCA7000 firmware.
+
+(a) Ethernet over SPI
+
+In order to use the QCA7000 as SPI device it must be defined as a child of a
+SPI master in the device tree.
+
+Required properties:
+- compatible : Should be "qca,qca7000"
+- reg : Should specify the SPI chip select
+- interrupts : The first cell should specify the index of the source
+ interrupt and the second cell should specify the trigger
+ type as rising edge
+- spi-cpha : Must be set
+- spi-cpol : Must be set
+
+Optional properties:
+- interrupt-parent : Specify the pHandle of the source interrupt
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
+ Numbers smaller than 1000000 or greater than 16000000
+ are invalid. Missing the property will set the SPI
+ frequency to 8000000 Hertz.
+- local-mac-address : see ./ethernet.txt
+- qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
+ In this mode the SPI master must toggle the chip select
+ between each data word. In burst mode these gaps aren't
+ necessary, which is faster. This setting depends on how
+ the QCA7000 is setup via GPIO pin strapping. If the
+ property is missing the driver defaults to burst mode.
+
+SPI Example:
+
+/* Freescale i.MX28 SPI master*/
+ssp2: spi@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ qca7000: ethernet@0 {
+ compatible = "qca,qca7000";
+ reg = <0x0>;
+ interrupt-parent = <&gpio3>; /* GPIO Bank 3 */
+ interrupts = <25 0x1>; /* Index: 25, rising edge */
+ spi-cpha; /* SPI mode: CPHA=1 */
+ spi-cpol; /* SPI mode: CPOL=1 */
+ spi-max-frequency = <8000000>; /* freq: 8 MHz */
+ local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
+ };
+};
+
+(b) Ethernet over UART
+
+In order to use the QCA7000 as UART slave it must be defined as a child of a
+UART master in the device tree. It is possible to preconfigure the UART
+settings of the QCA7000 firmware, but it's not possible to change them during
+runtime.
+
+Required properties:
+- compatible : Should be "qca,qca7000"
+
+Optional properties:
+- local-mac-address : see ./ethernet.txt
+- current-speed : current baud rate of QCA7000 which defaults to 115200
+ if absent, see also ../serial/slave-device.txt
+
+UART Example:
+
+/* Freescale i.MX28 UART */
+auart0: serial@8006a000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006a000 0x2000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+
+ qca7000: ethernet {
+ compatible = "qca,qca7000";
+ local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
+ current-speed = <38400>;
+ };
+};
diff --git a/dts/Bindings/net/qca-qca7000-spi.txt b/dts/Bindings/net/qca-qca7000-spi.txt
deleted file mode 100644
index c74989c0d8..0000000000
--- a/dts/Bindings/net/qca-qca7000-spi.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* Qualcomm QCA7000 (Ethernet over SPI protocol)
-
-Note: The QCA7000 is useable as a SPI device. In this case it must be defined
-as a child of a SPI master in the device tree.
-
-Required properties:
-- compatible : Should be "qca,qca7000"
-- reg : Should specify the SPI chip select
-- interrupts : The first cell should specify the index of the source interrupt
- and the second cell should specify the trigger type as rising edge
-- spi-cpha : Must be set
-- spi-cpol: Must be set
-
-Optional properties:
-- interrupt-parent : Specify the pHandle of the source interrupt
-- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
- Numbers smaller than 1000000 or greater than 16000000 are invalid. Missing
- the property will set the SPI frequency to 8000000 Hertz.
-- local-mac-address: 6 bytes, MAC address
-- qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
- In this mode the SPI master must toggle the chip select between each data
- word. In burst mode these gaps aren't necessary, which is faster.
- This setting depends on how the QCA7000 is setup via GPIO pin strapping.
- If the property is missing the driver defaults to burst mode.
-
-Example:
-
-/* Freescale i.MX28 SPI master*/
-ssp2: spi@80014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-
- qca7000: ethernet@0 {
- compatible = "qca,qca7000";
- reg = <0x0>;
- interrupt-parent = <&gpio3>; /* GPIO Bank 3 */
- interrupts = <25 0x1>; /* Index: 25, rising edge */
- spi-cpha; /* SPI mode: CPHA=1 */
- spi-cpol; /* SPI mode: CPOL=1 */
- spi-max-frequency = <8000000>; /* freq: 8 MHz */
- local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
- };
-};
diff --git a/dts/Bindings/net/ti,dp83867.txt b/dts/Bindings/net/ti,dp83867.txt
index afe9630a5e..02c4353b5c 100644
--- a/dts/Bindings/net/ti,dp83867.txt
+++ b/dts/Bindings/net/ti,dp83867.txt
@@ -18,6 +18,13 @@ Optional property:
- ti,max-output-impedance - MAC Interface Impedance control to set
the programmable output impedance to
maximum value (70 ohms).
+ - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
+ board has RX_DV/RX_CTRL pin strapped in
+ mode 1 or 2. To ensure PHY operation,
+ there are specific actions that
+ software needs to take when this pin is
+ strapped in these modes. See data manual
+ for details.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
diff --git a/dts/Bindings/net/ti,wilink-st.txt b/dts/Bindings/net/ti,wilink-st.txt
index cbad73a84a..1649c1f66b 100644
--- a/dts/Bindings/net/ti,wilink-st.txt
+++ b/dts/Bindings/net/ti,wilink-st.txt
@@ -14,6 +14,12 @@ Required properties:
- compatible: should be one of the following:
"ti,wl1271-st"
"ti,wl1273-st"
+ "ti,wl1281-st"
+ "ti,wl1283-st"
+ "ti,wl1285-st"
+ "ti,wl1801-st"
+ "ti,wl1805-st"
+ "ti,wl1807-st"
"ti,wl1831-st"
"ti,wl1835-st"
"ti,wl1837-st"
@@ -22,6 +28,10 @@ Optional properties:
- enable-gpios : GPIO signal controlling enabling of BT. Active high.
- vio-supply : Vio input supply (1.8V)
- vbat-supply : Vbat input supply (2.9-4.8V)
+ - clocks : Must contain an entry, for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names : Must include the following entry:
+ "ext_clock" (External clock provided to the TI combo chip).
Example:
@@ -31,5 +41,7 @@ Example:
bluetooth {
compatible = "ti,wl1835-st";
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ clocks = <&clk32k_wl18xx>;
+ clock-names = "ext_clock";
};
};
diff --git a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
index 5dbf169cd8..590f622188 100644
--- a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
+++ b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
@@ -31,7 +31,7 @@ mmc3: mmc@01c12000 {
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
diff --git a/dts/Bindings/net/wireless/ti,wlcore.txt b/dts/Bindings/net/wireless/ti,wlcore.txt
index 2a3d90de18..7b2cbb1411 100644
--- a/dts/Bindings/net/wireless/ti,wlcore.txt
+++ b/dts/Bindings/net/wireless/ti,wlcore.txt
@@ -10,6 +10,7 @@ Required properties:
* "ti,wl1273"
* "ti,wl1281"
* "ti,wl1283"
+ * "ti,wl1285"
* "ti,wl1801"
* "ti,wl1805"
* "ti,wl1807"
diff --git a/dts/Bindings/nvmem/rockchip-efuse.txt b/dts/Bindings/nvmem/rockchip-efuse.txt
index 94aeeeabad..1ff02afdc5 100644
--- a/dts/Bindings/nvmem/rockchip-efuse.txt
+++ b/dts/Bindings/nvmem/rockchip-efuse.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be one of the following.
- "rockchip,rk3066a-efuse" - for RK3066a SoCs.
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
+ - "rockchip,rk3228-efuse" - for RK3228 SoCs.
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
- "rockchip,rk3399-efuse" - for RK3399 SoCs.
- reg: Should contain the registers location and exact eFuse size
diff --git a/dts/Bindings/opp/opp.txt b/dts/Bindings/opp/opp.txt
index 63725498bd..e36d261b9b 100644
--- a/dts/Bindings/opp/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -186,20 +186,20 @@ Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
compatible = "operating-points-v2";
opp-shared;
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
- opp@1100000000 {
+ opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
clock-latency-ns = <290000>;
@@ -265,20 +265,20 @@ independently.
* independently.
*/
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
- opp@1100000000 {
+ opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
opp-microamp = <90000;
@@ -341,20 +341,20 @@ DVFS state together.
compatible = "operating-points-v2";
opp-shared;
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
- opp@1100000000 {
+ opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
opp-microamp = <90000>;
@@ -367,20 +367,20 @@ DVFS state together.
compatible = "operating-points-v2";
opp-shared;
- opp@1300000000 {
+ opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1050000 1045000 1055000>;
opp-microamp = <95000>;
clock-latency-ns = <400000>;
opp-suspend;
};
- opp@1400000000 {
+ opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1075000>;
opp-microamp = <100000>;
clock-latency-ns = <400000>;
};
- opp@1500000000 {
+ opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1100000 1010000 1110000>;
opp-microamp = <95000>;
@@ -409,7 +409,7 @@ Example 4: Handling multiple regulators
compatible = "operating-points-v2";
opp-shared;
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000>, /* Supply 0 */
<960000>, /* Supply 1 */
@@ -422,7 +422,7 @@ Example 4: Handling multiple regulators
/* OR */
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000 970000 985000>, /* Supply 0 */
<965000 960000 975000>, /* Supply 1 */
@@ -435,7 +435,7 @@ Example 4: Handling multiple regulators
/* OR */
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000 970000 985000>, /* Supply 0 */
<965000 960000 975000>, /* Supply 1 */
@@ -467,7 +467,7 @@ Example 5: opp-supported-hw
status = "okay";
opp-shared;
- opp@600000000 {
+ opp-600000000 {
/*
* Supports all substrate and process versions for 0xF
* cuts, i.e. only first four cuts.
@@ -478,7 +478,7 @@ Example 5: opp-supported-hw
...
};
- opp@800000000 {
+ opp-800000000 {
/*
* Supports:
* - cuts: only one, 6th cut (represented by 6th bit).
@@ -510,7 +510,7 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
compatible = "operating-points-v2";
opp-shared;
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt-slow = <915000 900000 925000>;
opp-microvolt-fast = <975000 970000 985000>;
@@ -518,7 +518,7 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
opp-microamp-fast = <71000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
<925000 910000 935000>; /* Supply vcc1 */
diff --git a/dts/Bindings/pci/faraday,ftpci100.txt b/dts/Bindings/pci/faraday,ftpci100.txt
index 35d4a979bb..89a84f8aa6 100644
--- a/dts/Bindings/pci/faraday,ftpci100.txt
+++ b/dts/Bindings/pci/faraday,ftpci100.txt
@@ -30,6 +30,13 @@ Mandatory properties:
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
pre-fetchable.
+Optional properties:
+- clocks: when present, this should contain the peripheral clock (PCLK) and the
+ PCI clock (PCICLK). If these are not present, they are assumed to be
+ hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
+- clock-names: when present, this should contain "PCLK" for the peripheral
+ clock and "PCICLK" for the PCI-side clock.
+
Mandatory subnodes:
- For "faraday,ftpci100" a node representing the interrupt-controller inside the
host bridge is mandatory. It has the following mandatory properties:
diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.txt b/dts/Bindings/pci/fsl,imx6q-pcie.txt
index e3d5680875..cf92d3ba5a 100644
--- a/dts/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/dts/Bindings/pci/fsl,imx6q-pcie.txt
@@ -33,6 +33,10 @@ Optional properties:
- reset-gpio-active-high: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state).
+- vpcie-supply: Should specify the regulator in charge of PCIe port power.
+ The regulator will be enabled when initializing the PCIe host and
+ disabled either as part of the init process or when shutting down the
+ host.
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:
diff --git a/dts/Bindings/pci/kirin-pcie.txt b/dts/Bindings/pci/kirin-pcie.txt
new file mode 100644
index 0000000000..68ffa0fbcd
--- /dev/null
+++ b/dts/Bindings/pci/kirin-pcie.txt
@@ -0,0 +1,50 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
diff --git a/dts/Bindings/pci/mediatek,mt7623-pcie.txt b/dts/Bindings/pci/mediatek,mt7623-pcie.txt
new file mode 100644
index 0000000000..fe80dda9bf
--- /dev/null
+++ b/dts/Bindings/pci/mediatek,mt7623-pcie.txt
@@ -0,0 +1,130 @@
+MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
+
+PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
+ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
+
+Required properties:
+- compatible: Should contain "mediatek,mt7623-pcie".
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe controller.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - free_ck :for reference clock of PCIe subsys
+ - sys_ck0 :for clock of Port0
+ - sys_ck1 :for clock of Port1
+ - sys_ck2 :for clock of Port2
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - pcie-rst0 :port0 reset
+ - pcie-rst1 :port1 reset
+ - pcie-rst2 :port2 reset
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+ which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+ and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+ property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples:
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie-controller@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
+
+ pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+ };
diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt
index e15f9b1990..9d418b7177 100644
--- a/dts/Bindings/pci/qcom,pcie.txt
+++ b/dts/Bindings/pci/qcom,pcie.txt
@@ -8,6 +8,7 @@
- "qcom,pcie-apq8064" for apq8064
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
+ - "qcom,pcie-ipq4019" for ipq4019
- reg:
Usage: required
@@ -87,7 +88,7 @@
- "core" Clocks the pcie hw block
- "phy" Clocks the pcie PHY block
- clock-names:
- Usage: required for apq8084
+ Usage: required for apq8084/ipq4019
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary (AUX) clock
@@ -126,6 +127,23 @@
Definition: Should contain the following entries
- "core" Core reset
+- reset-names:
+ Usage: required for ipq/apq8064
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "axi_m" AXI master reset
+ - "axi_s" AXI slave reset
+ - "pipe" PIPE reset
+ - "axi_m_vmid" VMID reset
+ - "axi_s_xpu" XPU reset
+ - "parf" PARF reset
+ - "phy" PHY reset
+ - "axi_m_sticky" AXI sticky reset
+ - "pipe_sticky" PIPE sticky reset
+ - "pwr" PWR reset
+ - "ahb" AHB reset
+ - "phy_ahb" PHY AHB reset
+
- power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: <prop-encoded-array>
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index 34712d6fd2..bd27428dda 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -1,4 +1,4 @@
-* Renesas RCar PCIe interface
+* Renesas R-Car PCIe interface
Required properties:
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
diff --git a/dts/Bindings/pci/tango-pcie.txt b/dts/Bindings/pci/tango-pcie.txt
new file mode 100644
index 0000000000..244683836a
--- /dev/null
+++ b/dts/Bindings/pci/tango-pcie.txt
@@ -0,0 +1,29 @@
+Sigma Designs Tango PCIe controller
+
+Required properties:
+
+- compatible: "sigma,smp8759-pcie"
+- reg: address/size of PCI configuration space, address/size of register area
+- bus-range: defined by size of PCI configuration space
+- device_type: "pci"
+- #size-cells: <2>
+- #address-cells: <3>
+- msi-controller
+- ranges: translation from system to bus addresses
+- interrupts: spec for misc interrupts, spec for MSI
+
+Example:
+
+ pcie@2e000 {
+ compatible = "sigma,smp8759-pcie";
+ reg = <0x50000000 0x400000>, <0x2e000 0x100>;
+ bus-range = <0 3>;
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ msi-controller;
+ ranges = <0x02000000 0x0 0x00400000 0x50400000 0x0 0x3c00000>;
+ interrupts =
+ <54 IRQ_TYPE_LEVEL_HIGH>, /* misc interrupts */
+ <55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
+ };
diff --git a/dts/Bindings/phy/bcm-ns-usb3-phy.txt b/dts/Bindings/phy/bcm-ns-usb3-phy.txt
index 09aeba9453..32f0572603 100644
--- a/dts/Bindings/phy/bcm-ns-usb3-phy.txt
+++ b/dts/Bindings/phy/bcm-ns-usb3-phy.txt
@@ -3,9 +3,10 @@ Driver for Broadcom Northstar USB 3.0 PHY
Required properties:
- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
-- reg: register mappings for DMP (Device Management Plugin) and ChipCommon B
- MMI.
-- reg-names: "dmp" and "ccb-mii"
+- reg: address of MDIO bus device
+- usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
+ registers
+- #phy-cells: must be 0
Initialization of USB 3.0 PHY depends on Northstar version. There are currently
three known series: Ax, Bx and Cx.
@@ -15,9 +16,19 @@ Known B1: BCM4707 rev 6
Known C0: BCM47094 rev 0
Example:
- usb3-phy {
- compatible = "brcm,ns-ax-usb3-phy";
- reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
- reg-names = "dmp", "ccb-mii";
- #phy-cells = <0>;
+ mdio: mdio@0 {
+ reg = <0x0>;
+ #size-cells = <1>;
+ #address-cells = <0>;
+
+ usb3-phy@10 {
+ compatible = "brcm,ns-ax-usb3-phy";
+ reg = <0x10>;
+ usb3-dmp-syscon = <&usb3_dmp>;
+ #phy-cells = <0>;
+ };
+ };
+
+ usb3_dmp: syscon@18105000 {
+ reg = <0x18105000 0x1000>;
};
diff --git a/dts/Bindings/phy/brcm,ns2-drd-phy.txt b/dts/Bindings/phy/brcm,ns2-drd-phy.txt
new file mode 100644
index 0000000000..04f063aa78
--- /dev/null
+++ b/dts/Bindings/phy/brcm,ns2-drd-phy.txt
@@ -0,0 +1,30 @@
+BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
+
+Required properties:
+ - compatible: brcm,ns2-drd-phy
+ - reg: offset and length of the NS2 PHY related registers.
+ - reg-names
+ The below registers must be provided.
+ icfg - for DRD ICFG configurations
+ rst-ctrl - for DRD IDM reset
+ crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
+ usb2-strap - for port over current polarity reversal
+ - #phy-cells: Must be 0. No args required.
+ - vbus-gpios: vbus gpio binding
+ - id-gpios: id gpio binding
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+ usbdrd_phy: phy@66000960 {
+ #phy-cells = <0>;
+ compatible = "brcm,ns2-drd-phy";
+ reg = <0x66000960 0x24>,
+ <0x67012800 0x4>,
+ <0x6501d148 0x4>,
+ <0x664d0700 0x4>;
+ reg-names = "icfg", "rst-ctrl",
+ "crmu-ctrl", "usb2-strap";
+ id-gpios = <&gpio_g 30 0>;
+ vbus-gpios = <&gpio_g 31 0>;
+ };
diff --git a/dts/Bindings/phy/brcm-sata-phy.txt b/dts/Bindings/phy/brcm-sata-phy.txt
index 6ccce09d8b..97977cd29a 100644
--- a/dts/Bindings/phy/brcm-sata-phy.txt
+++ b/dts/Bindings/phy/brcm-sata-phy.txt
@@ -7,12 +7,13 @@ Required properties:
"brcm,iproc-ns2-sata-phy"
"brcm,iproc-nsp-sata-phy"
"brcm,phy-sata3"
+ "brcm,iproc-sr-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- reg: register ranges for the PHY PCB interface
- reg-names: should be "phy" and "phy-ctrl"
The "phy-ctrl" registers are only required for
- "brcm,iproc-ns2-sata-phy".
+ "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy".
Sub-nodes:
Each port's PHY should be represented as a sub-node.
@@ -23,8 +24,8 @@ Sub-nodes required properties:
Sub-nodes optional properties:
- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
- This property is not applicable for "brcm,iproc-ns2-sata-phy" and
- "brcm,iproc-nsp-sata-phy".
+ This property is not applicable for "brcm,iproc-ns2-sata-phy",
+ "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".
Example:
sata-phy@f0458100 {
diff --git a/dts/Bindings/phy/meson-gxl-usb2-phy.txt b/dts/Bindings/phy/meson-gxl-usb2-phy.txt
new file mode 100644
index 0000000000..a105494a0f
--- /dev/null
+++ b/dts/Bindings/phy/meson-gxl-usb2-phy.txt
@@ -0,0 +1,17 @@
+* Amlogic Meson GXL and GXM USB2 PHY binding
+
+Required properties:
+- compatible: Should be "amlogic,meson-gxl-usb2-phy"
+- reg: The base address and length of the registers
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+
+Example:
+ usb2_phy0: phy@78000 {
+ compatible = "amlogic,meson-gxl-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x78000 0x0 0x20>;
+ };
diff --git a/dts/Bindings/phy/meson8b-usb2-phy.txt b/dts/Bindings/phy/meson8b-usb2-phy.txt
index 5fa73b9d20..d81d73aea6 100644
--- a/dts/Bindings/phy/meson8b-usb2-phy.txt
+++ b/dts/Bindings/phy/meson8b-usb2-phy.txt
@@ -1,7 +1,8 @@
-* Amlogic Meson8b and GXBB USB2 PHY
+* Amlogic Meson8, Meson8b and GXBB USB2 PHY
Required properties:
- compatible: Depending on the platform this should be one of:
+ "amlogic,meson8-usb2-phy"
"amlogic,meson8b-usb2-phy"
"amlogic,meson-gxbb-usb2-phy"
- reg: The base address and length of the registers
diff --git a/dts/Bindings/phy/phy-cpcap-usb.txt b/dts/Bindings/phy/phy-cpcap-usb.txt
new file mode 100644
index 0000000000..2eb9b2b690
--- /dev/null
+++ b/dts/Bindings/phy/phy-cpcap-usb.txt
@@ -0,0 +1,40 @@
+Motorola CPCAP PMIC USB PHY binding
+
+Required properties:
+compatible: Shall be either "motorola,cpcap-usb-phy" or
+ "motorola,mapphone-cpcap-usb-phy"
+#phy-cells: Shall be 0
+interrupts: CPCAP PMIC interrupts used by the USB PHY
+interrupt-names: Interrupt names
+io-channels: IIO ADC channels used by the USB PHY
+io-channel-names: IIO ADC channel names
+vusb-supply: Regulator for the PHY
+
+Optional properties:
+pinctrl: Optional alternate pin modes for the PHY
+pinctrl-names: Names for optional pin modes
+mode-gpios: Optional GPIOs for configuring alternate modes
+
+Example:
+cpcap_usb2_phy: phy {
+ compatible = "motorola,mapphone-cpcap-usb-phy";
+ pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
+ pinctrl-1 = <&usb_ulpi_pins>;
+ pinctrl-2 = <&usb_utmi_pins>;
+ pinctrl-3 = <&uart3_pins>;
+ pinctrl-names = "default", "ulpi", "utmi", "uart";
+ #phy-cells = <0>;
+ interrupts-extended = <
+ &cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
+ &cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
+ &cpcap 48 1
+ >;
+ interrupt-names =
+ "id_ground", "id_float", "se0conn", "vbusvld",
+ "sessvld", "sessend", "se1", "dm", "dp";
+ mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
+ &gpio1 0 GPIO_ACTIVE_HIGH>;
+ io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
+ io-channel-names = "vbus", "id";
+ vusb-supply = <&vusb>;
+};
diff --git a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
index e71a8d23f4..84d59b0db8 100644
--- a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
@@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
Required properties (phy (parent) node):
- compatible : should be one of the listed compatibles:
+ * "rockchip,rk3228-usb2phy"
* "rockchip,rk3328-usb2phy"
* "rockchip,rk3366-usb2phy"
* "rockchip,rk3399-usb2phy"
diff --git a/dts/Bindings/phy/rcar-gen3-phy-usb3.txt b/dts/Bindings/phy/rcar-gen3-phy-usb3.txt
new file mode 100644
index 0000000000..f94cea48f6
--- /dev/null
+++ b/dts/Bindings/phy/rcar-gen3-phy-usb3.txt
@@ -0,0 +1,46 @@
+* Renesas R-Car generation 3 USB 3.0 PHY
+
+This file provides information on what the device node for the R-Car generation
+3 USB 3.0 PHY contains.
+If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL
+instead of USB3_CLK. However, if you don't want to these features, you don't
+need this driver.
+
+Required properties:
+- compatible: "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
+ SoC.
+ "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
+ SoC.
+ "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
+ device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: offset and length of the USB 3.0 PHY register block.
+- clocks: A list of phandles and clock-specifier pairs.
+- clock-names: Name of the clocks.
+ - The funcional clock must be "usb3-if".
+ - The usb3's external clock must be "usb3s_clk".
+ - The usb2's external clock must be "usb_extal". If you want to use the ssc,
+ the clock-frequency must not be 0.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
+
+Optional properties:
+- renesas,ssc-range: Enable/disable spread spectrum clock (ssc) by using
+ the following values as u32:
+ - 0 (or the property doesn't exist): disable the ssc
+ - 4980: enable the ssc as -4980 ppm
+ - 4492: enable the ssc as -4492 ppm
+ - 4003: enable the ssc as -4003 ppm
+
+Example (R-Car H3):
+
+ usb-phy@e65ee000 {
+ compatible = "renesas,r8a7795-usb3-phy",
+ "renesas,rcar-gen3-usb3-phy";
+ reg = <0 0xe65ee000 0 0x90>;
+ clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>;
+ clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+ };
diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index b532244736..6f2ec9af0d 100644
--- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,8 +20,10 @@ Required properties:
"allwinner,sun9i-a80-pinctrl"
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
+ "allwinner,sun8i-a83t-r-pinctrl"
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
+ "allwinner,sun8i-r40-pinctrl"
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
diff --git a/dts/Bindings/pinctrl/ingenic,pinctrl.txt b/dts/Bindings/pinctrl/ingenic,pinctrl.txt
new file mode 100644
index 0000000000..ca313a7aea
--- /dev/null
+++ b/dts/Bindings/pinctrl/ingenic,pinctrl.txt
@@ -0,0 +1,41 @@
+Ingenic jz47xx pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
+be used as GPIOs, multiplexed device functions are configured within the
+GPIO port configuration registers and it is typical to refer to pins using the
+naming scheme "PxN" where x is a character identifying the GPIO port with
+which the pin is associated and N is an integer from 0 to 31 identifying the
+pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
+PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
+PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
+total of 192 pins.
+
+
+Required properties:
+--------------------
+
+ - compatible: One of:
+ - "ingenic,jz4740-pinctrl"
+ - "ingenic,jz4770-pinctrl"
+ - "ingenic,jz4780-pinctrl"
+ - reg: Address range of the pinctrl registers.
+
+
+GPIO sub-nodes
+--------------
+
+The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
+please refer to ../gpio/ingenic,gpio.txt.
+
+
+Example:
+--------
+
+pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+};
diff --git a/dts/Bindings/pinctrl/pinctrl-bindings.txt b/dts/Bindings/pinctrl/pinctrl-bindings.txt
index f01d154090..62d0f33fa6 100644
--- a/dts/Bindings/pinctrl/pinctrl-bindings.txt
+++ b/dts/Bindings/pinctrl/pinctrl-bindings.txt
@@ -204,21 +204,22 @@ each single pin the number of required sub-nodes containing "pin" and
maintain.
For cases like this, the pin controller driver may use the pinmux helper
-property, where the pin identifier is packed with mux configuration settings
-in a single integer.
+property, where the pin identifier is provided with mux configuration settings
+in a pinmux group. A pinmux group consists of the pin identifier and mux
+settings represented as a single integer or an array of integers.
-The pinmux property accepts an array of integers, each of them describing
+The pinmux property accepts an array of pinmux groups, each of them describing
a single pin multiplexing configuration.
pincontroller {
state_0_node_a {
- pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ...;
+ pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
};
};
Each individual pin controller driver bindings documentation shall specify
-how those values (pin IDs and pin multiplexing configuration) are defined and
-assembled together.
+how pin IDs and pin multiplexing configuration are defined and assembled
+together in a pinmux group.
== Generic pin configuration node content ==
@@ -251,14 +252,20 @@ drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
-input-enable - enable input on pin (no effect on output)
-input-disable - disable input on pin (no effect on output)
+input-enable - enable input on pin (no effect on output, such as
+ enabling an input buffer)
+input-disable - disable input on pin (no effect on output, such as
+ disabling an input buffer)
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
power-source - select between different power supplies
low-power-enable - enable low power mode
low-power-disable - disable low power mode
+output-disable - disable output on a pin (such as disable an output
+ buffer)
+output-enable - enable output on a pin without actively driving it
+ (such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
@@ -300,7 +307,7 @@ arguments are described below.
- pinmux takes a list of pin IDs and mux settings as required argument. The
specific bindings for the hardware defines:
- How pin IDs and mux settings are defined and assembled together in a single
- integer.
+ integer or an array of integers.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
diff --git a/dts/Bindings/pinctrl/pinctrl-zx.txt b/dts/Bindings/pinctrl/pinctrl-zx.txt
new file mode 100644
index 0000000000..e219849b21
--- /dev/null
+++ b/dts/Bindings/pinctrl/pinctrl-zx.txt
@@ -0,0 +1,85 @@
+* ZTE ZX Pin Controller
+
+The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of
+a main controller and an auxiliary one. For example, on ZX296718 SoC, the
+main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
+controllers work together to control pin multiplexing and configuration in
+the way illustrated as below.
+
+
+ GMII_RXD3 ---+
+ |
+ DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
+ |
+ BGPIO16 ---+ ^
+ | pinconf
+ ^ |
+ | pinmux |
+ | |
+
+ TOP_PMM (main) AON_IOCFG (aux)
+
+ | | |
+ | pinmux | |
+ | pinmux v |
+ v | pinconf
+ KEY_ROW2 ---+ v
+ PORT1_LCD_TE ---+ |
+ | AGPIO10 ---+------ KEY_ROW2 (AON pin)
+ I2S0_DOUT3 ---+ |
+ |-----------------------+
+ PWM_OUT3 ---+
+ |
+ VGA_VS1 ---+
+
+
+For most of pins like GMII_RXD3 in the figure, the pinmux function is
+controlled by TOP_PMM block only, and this type of pins are meant by term
+'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
+TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
+the pin spread in both controllers. This type of pins are called 'AON pins'.
+Though pinmux implementation is quite different, pinconf is same for both
+types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
+on ZX296718.
+
+Required properties:
+- compatible: should be "zte,zx296718-pmm".
+- reg: the register physical address and length.
+- zte,auxiliary-controller: phandle to the auxiliary pin controller which
+ implements pinmux for AON pins and pinconf for all pins.
+
+The following pin configuration are supported. Please refer to
+pinctrl-bindings.txt in this directory for more details of the common
+pinctrl bindings used by client devices.
+
+- bias-pull-up
+- bias-pull-down
+- drive-strength
+- input-enable
+- slew-rate
+
+Examples:
+
+iocfg: pin-controller@119000 {
+ compatible = "zte,zx296718-iocfg";
+ reg = <0x119000 0x1000>;
+};
+
+pmm: pin-controller@1462000 {
+ compatible = "zte,zx296718-pmm";
+ reg = <0x1462000 0x1000>;
+ zte,auxiliary-controller = <&iocfg>;
+};
+
+&pmm {
+ vga_pins: vga {
+ pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
+ function = "VGA";
+ };
+};
+
+&vga {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vga_pins>;
+ status = "okay";
+};
diff --git a/dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt
new file mode 100644
index 0000000000..407b944362
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt
@@ -0,0 +1,172 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode. Valid pins are:
+ gpio0-gpio69
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+ atest_char, atest_char0, atest_char1, atest_char2,
+ atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
+ audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
+ audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
+ blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
+ blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
+ blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
+ blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
+ blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
+ cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
+ ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
+ mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
+ mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
+ pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
+ pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
+ pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
+ qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
+ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+ qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+ qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
+ qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
+ qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
+ qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
+ wci2b, wci2c, wci2d
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart2: uart2-default {
+ mux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ };
+
+ rx {
+ pins = "gpio23";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ tx {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 13df949831..645082f032 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -13,6 +13,8 @@ Required Properties:
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+ - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
+ - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
diff --git a/dts/Bindings/pinctrl/renesas,rza1-pinctrl.txt b/dts/Bindings/pinctrl/renesas,rza1-pinctrl.txt
new file mode 100644
index 0000000000..43e2147452
--- /dev/null
+++ b/dts/Bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -0,0 +1,221 @@
+Renesas RZ/A1 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
+named "Ports" in the hardware reference manual.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis
+writing configuration values to per-port register sets.
+Each "port" features up to 16 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+-------------------
+
+Required properties:
+ - compatible
+ this shall be "renesas,r7s72100-ports".
+
+ - reg
+ address base and length of the memory area where the pin controller
+ hardware is mapped to.
+
+Example:
+Pin controller node for RZ/A1H SoC (r7s72100)
+
+pinctrl: pin-controller@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ reg = <0xfcfe3000 0x4230>;
+};
+
+Sub-nodes
+---------
+
+The child nodes of the pin controller node describe a pin multiplexing
+function or a GPIO controller alternatively.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ A single sub-node may define several pin configurations.
+ A few alternate function require special pin configuration flags to be
+ supplied along with the alternate function configuration number.
+ The hardware reference manual specifies when a pin function requires
+ "software IO driven" mode to be specified. To do so use the generic
+ properties from the <include/linux/pinctrl/pinconf_generic.h> header file
+ to instruct the pin controller to perform the desired pin configuration
+ operation.
+ Please refer to pinctrl-bindings.txt to get to know more on generic
+ pin properties usage.
+
+ The allowed generic formats for a pin multiplexing sub-node are the
+ following ones:
+
+ node-1 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ node-2 {
+ sub-node-1 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ sub-node-2 {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+
+ ...
+
+ sub-node-n {
+ pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
+ GENERIC_PINCONFIG;
+ };
+ };
+
+ Use the second format when pins part of the same logical group need to have
+ different generic pin configuration flags applied.
+
+ Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
+ of the most external one.
+
+ Eg.
+
+ client-1 {
+ ...
+ pinctrl-0 = <&node-1>;
+ ...
+ };
+
+ client-2 {
+ ...
+ pinctrl-0 = <&node-2>;
+ ...
+ };
+
+ Required properties:
+ - pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+ <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 16 + PIN) | MUX_FUNC << 16)
+
+ Optional generic properties:
+ - input-enable:
+ enable input bufer for pins requiring software driven IO input
+ operations.
+ - output-high:
+ enable output buffer for pins requiring software driven IO output
+ operations. output-low can be used alternatively, as line value is
+ ignored by the driver.
+
+ The hardware reference manual specifies when a pin has to be configured to
+ work in bi-directional mode and when the IO direction has to be specified
+ by software. Bi-directional pins are managed by the pin controller driver
+ internally, while software driven IO direction has to be explicitly
+ selected when multiple options are available.
+
+ Example:
+ A serial communication interface with a TX output pin and an RX input pin.
+
+ &pinctrl {
+ scif2_pins: serial2 {
+ pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
+ };
+ };
+
+ Pin #0 on port #3 is configured as alternate function #6.
+ Pin #2 on port #3 is configured as alternate function #4.
+
+ Example 2:
+ I2c master: both SDA and SCL pins need bi-directional operations
+
+ &pinctrl {
+ i2c2_pins: i2c2 {
+ pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
+ };
+ };
+
+ Pin #4 on port #1 is configured as alternate function #1.
+ Pin #5 on port #1 is configured as alternate function #1.
+ Both need to work in bi-directional mode, the driver manages this internally.
+
+ Example 3:
+ Multi-function timer input and output compare pins.
+ Configure TIOC0A as software driven input and TIOC0B as software driven
+ output.
+
+ &pinctrl {
+ tioc0_pins: tioc0 {
+ tioc0_input_pins {
+ pinumx = <RZA1_PINMUX(4, 0, 2)>;
+ input-enable;
+ };
+
+ tioc0_output_pins {
+ pinmux = <RZA1_PINMUX(4, 1, 1)>;
+ output-enable;
+ };
+ };
+ };
+
+ &tioc0 {
+ ...
+ pinctrl-0 = <&tioc0_pins>;
+ ...
+ };
+
+ Pin #0 on port #4 is configured as alternate function #2 with IO direction
+ specified by software as input.
+ Pin #1 on port #4 is configured as alternate function #1 with IO direction
+ specified by software as output.
+
+- GPIO controller sub-nodes:
+ Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
+ Different SoCs have different numbers of available pins per port, but
+ generally speaking, each of them can be configured in GPIO ("port") mode
+ on this hardware.
+ Describe GPIO controllers using sub-nodes with the following properties.
+
+ Required properties:
+ - gpio-controller
+ empty property as defined by the GPIO bindings documentation.
+ - #gpio-cells
+ number of cells required to identify and configure a GPIO.
+ Shall be 2.
+ - gpio-ranges
+ Describes a GPIO controller specifying its specific pin base, the pin
+ base in the global pin numbering space, and the number of controlled
+ pins, as defined by the GPIO bindings documentation. Refer to
+ Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
+ description.
+
+ Example:
+ A GPIO controller node, controlling 16 pins indexed from 0.
+ The GPIO controller base in the global pin indexing space is pin 48, thus
+ pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
+ indexing space.
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ A device node willing to use pins controlled by this GPIO controller, shall
+ refer to it as follows:
+
+ led1 {
+ gpios = <&port3 10 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/power/actions,owl-sps.txt b/dts/Bindings/power/actions,owl-sps.txt
new file mode 100644
index 0000000000..007b9a7ae7
--- /dev/null
+++ b/dts/Bindings/power/actions,owl-sps.txt
@@ -0,0 +1,17 @@
+Actions Semi Owl Smart Power System (SPS)
+
+Required properties:
+- compatible : "actions,s500-sps" for S500
+- reg : Offset and length of the register set for the device.
+- #power-domain-cells : Must be 1.
+ See macros in:
+ include/dt-bindings/power/owl-s500-powergate.h for S500
+
+
+Example:
+
+ sps: power-controller@b01b0100 {
+ compatible = "actions,s500-sps";
+ reg = <0xb01b0100 0x100>;
+ #power-domain-cells = <1>;
+ };
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
index d3a5a93a65..43c21fb045 100644
--- a/dts/Bindings/power/rockchip-io-domain.txt
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -32,6 +32,7 @@ SoC is on the same page.
Required properties:
- compatible: should be one of:
- "rockchip,rk3188-io-voltage-domain" for rk3188
+ - "rockchip,rk3228-io-voltage-domain" for rk3228
- "rockchip,rk3288-io-voltage-domain" for rk3288
- "rockchip,rk3328-io-voltage-domain" for rk3328
- "rockchip,rk3368-io-voltage-domain" for rk3368
@@ -59,6 +60,12 @@ Possible supplies for rk3188:
- vccio1-supply: The supply connected to VCCIO1.
Sometimes also labeled VCCIO1 and VCCIO2.
+Possible supplies for rk3228:
+- vccio1-supply: The supply connected to VCCIO1.
+- vccio2-supply: The supply connected to VCCIO2.
+- vccio3-supply: The supply connected to VCCIO3.
+- vccio4-supply: The supply connected to VCCIO4.
+
Possible supplies for rk3288:
- audio-supply: The supply connected to APIO4_VDD.
- bb-supply: The supply connected to APIO5_VDD.
diff --git a/dts/Bindings/power/supply/battery.txt b/dts/Bindings/power/supply/battery.txt
new file mode 100644
index 0000000000..f4d3b4a10b
--- /dev/null
+++ b/dts/Bindings/power/supply/battery.txt
@@ -0,0 +1,57 @@
+Battery Characteristics
+
+The devicetree battery node provides static battery characteristics.
+In smart batteries, these are typically stored in non-volatile memory
+on a fuel gauge chip. The battery node should be used where there is
+no appropriate non-volatile memory, or it is unprogrammed/incorrect.
+
+Upstream dts files should not include battery nodes, unless the battery
+represented cannot easily be replaced in the system by one of a
+different type. This prevents unpredictable, potentially harmful,
+behavior should a replacement that changes the battery type occur
+without a corresponding update to the dtb.
+
+Required Properties:
+ - compatible: Must be "simple-battery"
+
+Optional Properties:
+ - voltage-min-design-microvolt: drained battery voltage
+ - energy-full-design-microwatt-hours: battery design energy
+ - charge-full-design-microamp-hours: battery design capacity
+ - precharge-current-microamp: current for pre-charge phase
+ - charge-term-current-microamp: current for charge termination phase
+ - constant-charge-current-max-microamp: maximum constant input current
+ - constant-charge-voltage-max-microvolt: maximum constant input voltage
+
+Battery properties are named, where possible, for the corresponding
+elements in enum power_supply_property, defined in
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/power_supply.h
+
+Batteries must be referenced by chargers and/or fuel-gauges
+using a phandle. The phandle's property should be named
+"monitored-battery".
+
+Example:
+
+ bat: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3200000>;
+ energy-full-design-microwatt-hours = <5290000>;
+ charge-full-design-microamp-hours = <1430000>;
+ precharge-current-microamp = <256000>;
+ charge-term-current-microamp = <128000>;
+ constant-charge-current-max-microamp = <900000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ };
+
+ charger: charger@11 {
+ ....
+ monitored-battery = <&bat>;
+ ...
+ };
+
+ fuel_gauge: fuel-gauge@22 {
+ ....
+ monitored-battery = <&bat>;
+ ...
+ };
diff --git a/dts/Bindings/power/supply/bq27xxx.txt b/dts/Bindings/power/supply/bq27xxx.txt
index b0c95ef63e..6858e1a804 100644
--- a/dts/Bindings/power/supply/bq27xxx.txt
+++ b/dts/Bindings/power/supply/bq27xxx.txt
@@ -1,7 +1,7 @@
-Binding for TI BQ27XXX fuel gauge family
+TI BQ27XXX fuel gauge family
Required properties:
-- compatible: Should contain one of the following:
+- compatible: contains one of the following:
* "ti,bq27200" - BQ27200
* "ti,bq27210" - BQ27210
* "ti,bq27500" - deprecated, use revision specific property below
@@ -26,11 +26,28 @@ Required properties:
* "ti,bq27425" - BQ27425
* "ti,bq27441" - BQ27441
* "ti,bq27621" - BQ27621
-- reg: integer, i2c address of the device.
+- reg: integer, I2C address of the fuel gauge.
+
+Optional properties:
+- monitored-battery: phandle of battery characteristics node
+ The fuel gauge uses the following battery properties:
+ + energy-full-design-microwatt-hours
+ + charge-full-design-microamp-hours
+ + voltage-min-design-microvolt
+ Both or neither of the *-full-design-*-hours properties must be set.
+ See Documentation/devicetree/bindings/power/supply/battery.txt
Example:
-bq27510g3 {
- compatible = "ti,bq27510g3";
- reg = <0x55>;
-};
+ bat: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3200000>;
+ energy-full-design-microwatt-hours = <5290000>;
+ charge-full-design-microamp-hours = <1430000>;
+ };
+
+ bq27510g3: fuel-gauge@55 {
+ compatible = "ti,bq27510g3";
+ reg = <0x55>;
+ monitored-battery = <&bat>;
+ };
diff --git a/dts/Bindings/power/supply/cpcap-battery.txt b/dts/Bindings/power/supply/cpcap-battery.txt
new file mode 100644
index 0000000000..a04efa22da
--- /dev/null
+++ b/dts/Bindings/power/supply/cpcap-battery.txt
@@ -0,0 +1,31 @@
+Motorola CPCAP PMIC battery driver binding
+
+Required properties:
+- compatible: Shall be "motorola,cpcap-battery"
+- interrupts: Interrupt specifier for each name in interrupt-names
+- interrupt-names: Should contain the following entries:
+ "lowbph", "lowbpl", "chrgcurr1", "battdetb"
+- io-channels: IIO ADC channel specifier for each name in io-channel-names
+- io-channel-names: Should contain the following entries:
+ "battdetb", "battp", "chg_isense", "batti"
+- power-supplies: List of phandles for power-supplying devices, as
+ described in power_supply.txt. Typically a reference
+ to cpcap_charger.
+
+Example:
+
+cpcap_battery: battery {
+ compatible = "motorola,cpcap-battery";
+ interrupts-extended = <
+ &cpcap 5 0 &cpcap 3 0
+ &cpcap 20 0 &cpcap 54 0
+ >;
+ interrupt-names =
+ "lowbph", "lowbpl",
+ "chrgcurr1", "battdetb";
+ io-channels = <&cpcap_adc 0 &cpcap_adc 1
+ &cpcap_adc 5 &cpcap_adc 6>;
+ io-channel-names = "battdetb", "battp",
+ "chg_isense", "batti";
+ power-supplies = <&cpcap_charger>;
+};
diff --git a/dts/Bindings/power/supply/ltc3651-charger.txt b/dts/Bindings/power/supply/ltc3651-charger.txt
new file mode 100644
index 0000000000..71f2840e82
--- /dev/null
+++ b/dts/Bindings/power/supply/ltc3651-charger.txt
@@ -0,0 +1,27 @@
+ltc3651-charger
+
+Required properties:
+ - compatible: "lltc,ltc3651-charger"
+ - lltc,acpr-gpios: Connect to ACPR output. See remark below.
+
+Optional properties:
+ - lltc,fault-gpios: Connect to FAULT output. See remark below.
+ - lltc,chrg-gpios: Connect to CHRG output. See remark below.
+
+The ltc3651 outputs are open-drain type and active low. The driver assumes the
+GPIO reports "active" when the output is asserted, so if the pins have been
+connected directly, the GPIO flags should be set to active low also.
+
+The driver will attempt to aquire interrupts for all GPIOs to detect changes in
+line state. If the system is not capabale of providing interrupts, the driver
+cannot report changes and userspace will need to periodically read the sysfs
+attributes to detect changes.
+
+Example:
+
+ charger: battery-charger {
+ compatible = "lltc,ltc3651-charger";
+ lltc,acpr-gpios = <&gpio0 68 GPIO_ACTIVE_LOW>;
+ lltc,fault-gpios = <&gpio0 64 GPIO_ACTIVE_LOW>;
+ lltc,chrg-gpios = <&gpio0 63 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/power/max8903-charger.txt b/dts/Bindings/power/supply/max8903-charger.txt
index f0f4e12b07..f0f4e12b07 100644
--- a/dts/Bindings/power/max8903-charger.txt
+++ b/dts/Bindings/power/supply/max8903-charger.txt
diff --git a/dts/Bindings/power_supply/maxim,max14656.txt b/dts/Bindings/power/supply/maxim,max14656.txt
index e03e85ae65..e03e85ae65 100644
--- a/dts/Bindings/power_supply/maxim,max14656.txt
+++ b/dts/Bindings/power/supply/maxim,max14656.txt
diff --git a/dts/Bindings/powerpc/fsl/cpus.txt b/dts/Bindings/powerpc/fsl/cpus.txt
index f8cd2397aa..d63ab1dec1 100644
--- a/dts/Bindings/powerpc/fsl/cpus.txt
+++ b/dts/Bindings/powerpc/fsl/cpus.txt
@@ -3,10 +3,10 @@ Power Architecture CPU Binding
Copyright 2013 Freescale Semiconductor Inc.
Power Architecture CPUs in Freescale SOCs are represented in device trees as
-per the definition in ePAPR.
+per the definition in the Devicetree Specification.
-In addition to the ePAPR definitions, the properties defined below may be
-present on CPU nodes.
+In addition to the the Devicetree Specification definitions, the properties
+defined below may be present on CPU nodes.
PROPERTIES
diff --git a/dts/Bindings/powerpc/fsl/l2cache.txt b/dts/Bindings/powerpc/fsl/l2cache.txt
index dc9bb31825..8a70696395 100644
--- a/dts/Bindings/powerpc/fsl/l2cache.txt
+++ b/dts/Bindings/powerpc/fsl/l2cache.txt
@@ -1,7 +1,7 @@
Freescale L2 Cache Controller
L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
-The cache bindings explained below are ePAPR compliant
+The cache bindings explained below are Devicetree Specification compliant
Required Properties:
diff --git a/dts/Bindings/powerpc/fsl/srio-rmu.txt b/dts/Bindings/powerpc/fsl/srio-rmu.txt
index b9a8a2bcfa..0496ada4bb 100644
--- a/dts/Bindings/powerpc/fsl/srio-rmu.txt
+++ b/dts/Bindings/powerpc/fsl/srio-rmu.txt
@@ -124,8 +124,8 @@ Port-Write Unit:
A single IRQ that handles port-write conditions is
specified by this property. (Typically shared with error).
- Note: All other standard properties (see the ePAPR) are allowed
- but are optional.
+ Note: All other standard properties (see the Devicetree Specification)
+ are allowed but are optional.
Example:
rmu: rmu@d3000 {
diff --git a/dts/Bindings/powerpc/fsl/srio.txt b/dts/Bindings/powerpc/fsl/srio.txt
index 07abf0f2f4..86ee6ea737 100644
--- a/dts/Bindings/powerpc/fsl/srio.txt
+++ b/dts/Bindings/powerpc/fsl/srio.txt
@@ -72,7 +72,8 @@ the following properties:
represents the LIODN associated with maintenance transactions
for the port.
-Note: All other standard properties (see ePAPR) are allowed but are optional.
+Note: All other standard properties (see the Devicetree Specification)
+are allowed but are optional.
Example:
diff --git a/dts/Bindings/property-units.txt b/dts/Bindings/property-units.txt
index 12278d79f6..45ce054d84 100644
--- a/dts/Bindings/property-units.txt
+++ b/dts/Bindings/property-units.txt
@@ -25,9 +25,12 @@ Distance
Electricity
----------------------------------------
-microamp : micro amps
+-microamp-hours : micro amp-hours
-ohms : Ohms
-micro-ohms : micro Ohms
+-microwatt-hours: micro Watt-hours
-microvolt : micro volts
+-picofarads : picofarads
Temperature
----------------------------------------
diff --git a/dts/Bindings/ptp/brcm,ptp-dte.txt b/dts/Bindings/ptp/brcm,ptp-dte.txt
new file mode 100644
index 0000000000..7c04e22a5d
--- /dev/null
+++ b/dts/Bindings/ptp/brcm,ptp-dte.txt
@@ -0,0 +1,20 @@
+* Broadcom Digital Timing Engine(DTE) based PTP clock
+
+Required properties:
+- compatible: should contain the core compatibility string
+ and the SoC compatibility string. The SoC
+ compatibility string is to handle SoC specific
+ hardware differences.
+ Core compatibility string:
+ "brcm,ptp-dte"
+ SoC compatibility strings:
+ "brcm,iproc-ptp-dte" - for iproc based SoC's
+- reg: address and length of the DTE block's NCO registers
+
+Example:
+
+ptp: ptp-dte@180af650 {
+ compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
+ reg = <0x180af650 0x10>;
+ status = "okay";
+};
diff --git a/dts/Bindings/pwm/pwm-meson.txt b/dts/Bindings/pwm/pwm-meson.txt
index 5376a4468c..5b07bebbf6 100644
--- a/dts/Bindings/pwm/pwm-meson.txt
+++ b/dts/Bindings/pwm/pwm-meson.txt
@@ -2,7 +2,9 @@ Amlogic Meson PWM Controller
============================
Required properties:
-- compatible: Shall contain "amlogic,meson8b-pwm" or "amlogic,meson-gxbb-pwm".
+- compatible: Shall contain "amlogic,meson8b-pwm"
+ or "amlogic,meson-gxbb-pwm"
+ or "amlogic,meson-gxbb-ao-pwm"
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/pwm/pwm-stm32.txt b/dts/Bindings/pwm/pwm-stm32.txt
index 6dd040363e..3e6d55018d 100644
--- a/dts/Bindings/pwm/pwm-stm32.txt
+++ b/dts/Bindings/pwm/pwm-stm32.txt
@@ -24,7 +24,7 @@ Example:
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 160>;
- clock-names = "clk_int";
+ clock-names = "int";
pwm {
compatible = "st,stm32-pwm";
diff --git a/dts/Bindings/pwm/renesas,pwm-rcar.txt b/dts/Bindings/pwm/renesas,pwm-rcar.txt
index d6de643350..7e94b80239 100644
--- a/dts/Bindings/pwm/renesas,pwm-rcar.txt
+++ b/dts/Bindings/pwm/renesas,pwm-rcar.txt
@@ -8,6 +8,7 @@ Required Properties:
- "renesas,pwm-r8a7791": for R-Car M2-W
- "renesas,pwm-r8a7794": for R-Car E2
- "renesas,pwm-r8a7795": for R-Car H3
+ - "renesas,pwm-r8a7796": for R-Car M3-W
- reg: base address and length of the registers block for the PWM.
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/regulator/regulator.txt b/dts/Bindings/regulator/regulator.txt
index d18edb075e..378f6dc8b8 100644
--- a/dts/Bindings/regulator/regulator.txt
+++ b/dts/Bindings/regulator/regulator.txt
@@ -24,6 +24,14 @@ Optional properties:
- regulator-settling-time-us: Settling time, in microseconds, for voltage
change if regulator have the constant time for any level voltage change.
This is useful when regulator have exponential voltage change.
+- regulator-settling-time-up-us: Settling time, in microseconds, for voltage
+ increase if the regulator needs a constant time to settle after voltage
+ increases of any level. This is useful for regulators with exponential
+ voltage changes.
+- regulator-settling-time-down-us: Settling time, in microseconds, for voltage
+ decrease if the regulator needs a constant time to settle after voltage
+ decreases of any level. This is useful for regulators with exponential
+ voltage changes.
- regulator-soft-start: Enable soft start so that voltage ramps slowly
- regulator-state-mem sub-root node for Suspend-to-RAM mode
: suspend to memory, the device goes to sleep, but all data stored in memory,
diff --git a/dts/Bindings/remoteproc/ti,keystone-rproc.txt b/dts/Bindings/remoteproc/ti,keystone-rproc.txt
new file mode 100644
index 0000000000..2aac1aa412
--- /dev/null
+++ b/dts/Bindings/remoteproc/ti,keystone-rproc.txt
@@ -0,0 +1,133 @@
+TI Keystone DSP devices
+=======================
+
+The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
+sub-systems that are used to offload some of the processor-intensive tasks or
+algorithms, for achieving various system level goals.
+
+These processor sub-systems usually contain additional sub-modules like L1
+and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
+a dedicated local power/sleep controller etc. The DSP processor core in
+Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
+
+DSP Device Node:
+================
+Each DSP Core sub-system is represented as a single DT node, and should also
+have an alias with the stem 'rproc' defined. Each node has a number of required
+or optional properties that enable the OS running on the host processor (ARM
+CorePac) to perform the device management of the remote processor and to
+communicate with the remote processor.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
+ "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
+ "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
+
+- reg: Should contain an entry for each value in 'reg-names'.
+ Each entry should have the memory region's start address
+ and the size of the region, the representation matching
+ the parent node's '#address-cells' and '#size-cells' values.
+
+- reg-names: Should contain strings with the following names, each
+ representing a specific internal memory region, and
+ should be defined in this order,
+ "l2sram", "l1pram", "l1dram"
+
+- clocks: Should contain the device's input clock, and should be
+ defined as per the bindings in,
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+
+- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device
+ State Control node, and the register offset of the DSP
+ boot address register within that node's address space.
+
+- resets: Should contain the phandle to the reset controller node
+ managing the resets for this device, and a reset
+ specifier. Please refer to the following reset bindings
+ for the reset argument specifier as per SoC,
+ Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+ for 66AK2HK/66AK2L/66AK2E SoCs
+
+- interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller
+ IP node that is used by the ARM CorePac processor to
+ receive interrupts from the DSP remote processors. See
+ Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
+ for details.
+
+- interrupts: Should contain an entry for each value in 'interrupt-names'.
+ Each entry should have the interrupt source number used by
+ the remote processor to the host processor. The values should
+ follow the interrupt-specifier format as dictated by the
+ 'interrupt-parent' node. The purpose of each is as per the
+ description in the 'interrupt-names' property.
+
+- interrupt-names: Should contain strings with the following names, each
+ representing a specific interrupt,
+ "vring" - interrupt for virtio based IPC
+ "exception" - interrupt for exception notification
+
+- kick-gpios: Should specify the gpio device needed for the virtio IPC
+ stack. This will be used to interrupt the remote processor.
+ The gpio device to be used is as per the bindings in,
+ Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
+
+Optional properties:
+--------------------
+
+- memory-region: phandle to the reserved memory node to be associated
+ with the remoteproc device. The reserved memory node
+ can be a CMA memory node, and should be defined as
+ per the bindings in
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
+
+Example:
+--------
+ /* 66AK2H/K DSP aliases */
+ aliases {
+ rproc0 = &dsp0;
+ rproc1 = &dsp1;
+ rproc2 = &dsp2;
+ rproc3 = &dsp3;
+ rproc4 = &dsp4;
+ rproc5 = &dsp5;
+ rproc6 = &dsp6;
+ rproc7 = &dsp7;
+ };
+
+ /* 66AK2H/K DSP memory node */
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ };
+ };
+
+ /* 66AK2H/K DSP node */
+ soc {
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem0>;
+ ti,syscon-dev = <&devctrl 0x40>;
+ resets = <&pscrst 0>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ memory-region = <&dsp_common_memory>;
+ };
+
+ };
diff --git a/dts/Bindings/reserved-memory/reserved-memory.txt b/dts/Bindings/reserved-memory/reserved-memory.txt
index 3da0ebdba8..16291f2a46 100644
--- a/dts/Bindings/reserved-memory/reserved-memory.txt
+++ b/dts/Bindings/reserved-memory/reserved-memory.txt
@@ -68,6 +68,9 @@ Linux implementation note:
- If a "linux,cma-default" property is present, then Linux will use the
region for the default pool of the contiguous memory allocator.
+- If a "linux,dma-default" property is present, then Linux will use the
+ region for the default pool of the consistent DMA allocator.
+
Device node references to reserved memory
-----------------------------------------
Regions in the /reserved-memory node may be referenced by other device
diff --git a/dts/Bindings/reset/ti,sci-reset.txt b/dts/Bindings/reset/ti,sci-reset.txt
new file mode 100644
index 0000000000..8b1cf022f1
--- /dev/null
+++ b/dts/Bindings/reset/ti,sci-reset.txt
@@ -0,0 +1,62 @@
+Texas Instruments System Control Interface (TI-SCI) Reset Controller
+=====================================================================
+
+Some TI SoCs contain a system controller (like the Power Management Micro
+Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+the state of the various hardware modules present on the SoC. Communication
+between the host processor running an OS and the system controller happens
+through a protocol called TI System Control Interface (TI-SCI protocol).
+For TI SCI details, please refer to the document,
+Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
+
+TI-SCI Reset Controller Node
+============================
+This reset controller node uses the TI SCI protocol to perform the reset
+management of various hardware modules present on the SoC. Must be a child
+node of the associated TI-SCI system controller node.
+
+Required properties:
+--------------------
+ - compatible : Should be "ti,sci-reset"
+ - #reset-cells : Should be 2. Please see the reset consumer node below for
+ usage details.
+
+TI-SCI Reset Consumer Nodes
+===========================
+Each of the reset consumer nodes should have the following properties,
+in addition to their own properties.
+
+Required properties:
+--------------------
+ - resets : A phandle and reset specifier pair, one pair for each reset
+ signal that affects the device, or that the device manages.
+ The phandle should point to the TI-SCI reset controller node,
+ and the reset specifier should have 2 cell-values. The first
+ cell should contain the device ID. The second cell should
+ contain the reset mask value used by system controller.
+ Please refer to the protocol documentation for these values
+ to be used for different devices,
+ http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
+
+Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
+common reset controller usage by consumers.
+
+Example:
+--------
+The following example demonstrates both a TI-SCI reset controller node and a
+consumer (a DSP device) on the 66AK2G SoC.
+
+pmmc: pmmc {
+ compatible = "ti,k2g-sci";
+
+ k2g_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+};
+
+dsp0: dsp@10800000 {
+ ...
+ resets = <&k2g_reset 0x0046 0x1>;
+ ...
+};
diff --git a/dts/Bindings/rng/mtk-rng.txt b/dts/Bindings/rng/mtk-rng.txt
index a6d62a2abd..366b99bff8 100644
--- a/dts/Bindings/rng/mtk-rng.txt
+++ b/dts/Bindings/rng/mtk-rng.txt
@@ -2,7 +2,9 @@ Device-Tree bindings for Mediatek random number generator
found in Mediatek SoC family
Required properties:
-- compatible : Should be "mediatek,mt7623-rng"
+- compatible : Should be
+ "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622
+ "mediatek,mt7623-rng" : for MT7623
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : Should contain "rng" entries;
diff --git a/dts/Bindings/rng/timeriomem_rng.txt b/dts/Bindings/rng/timeriomem_rng.txt
index 6616d15866..214940093b 100644
--- a/dts/Bindings/rng/timeriomem_rng.txt
+++ b/dts/Bindings/rng/timeriomem_rng.txt
@@ -5,6 +5,13 @@ Required properties:
- reg : base address to sample from
- period : wait time in microseconds to use between samples
+Optional properties:
+- quality : estimated number of bits of true entropy per 1024 bits read from the
+ rng. Defaults to zero which causes the kernel's default quality to
+ be used instead. Note that the default quality is usually zero
+ which disables using this rng to automatically fill the kernel's
+ entropy pool.
+
N.B. currently 'reg' must be four bytes wide and aligned
Example:
diff --git a/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt b/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt
new file mode 100644
index 0000000000..1d990bcc0b
--- /dev/null
+++ b/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt
@@ -0,0 +1,22 @@
+Broadcom STB wake-up Timer
+
+The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
+ability to wake up the system from low-power suspend/standby modes.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-waketimer"
+- reg : the register start and length for the WKTMR block
+- interrupts : The TIMER interrupt
+- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
+ interrupt controller node
+- clocks : The phandle to the UPG fixed clock (27Mhz domain)
+
+Example:
+
+waketimer@f0411580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0xf0411580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ clocks = <&upg_fixed>;
+};
diff --git a/dts/Bindings/rtc/cortina,gemini.txt b/dts/Bindings/rtc/cortina,gemini.txt
deleted file mode 100644
index 4ce4e794dd..0000000000
--- a/dts/Bindings/rtc/cortina,gemini.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Cortina Systems Gemini RTC
-
-Gemini SoC real-time clock.
-
-Required properties:
-- compatible : Should be "cortina,gemini-rtc"
-
-Examples:
-
-rtc@45000000 {
- compatible = "cortina,gemini-rtc";
- reg = <0x45000000 0x100>;
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
-};
diff --git a/dts/Bindings/rtc/faraday,ftrtc010.txt b/dts/Bindings/rtc/faraday,ftrtc010.txt
new file mode 100644
index 0000000000..e3938f5e0b
--- /dev/null
+++ b/dts/Bindings/rtc/faraday,ftrtc010.txt
@@ -0,0 +1,28 @@
+* Faraday Technology FTRTC010 Real Time Clock
+
+This RTC appears in for example the Storlink Gemini family of
+SoCs.
+
+Required properties:
+- compatible : Should be one of:
+ "faraday,ftrtc010"
+ "cortina,gemini-rtc", "faraday,ftrtc010"
+
+Optional properties:
+- clocks: when present should contain clock references to the
+ PCLK and EXTCLK clocks. Faraday calls the later CLK1HZ and
+ says the clock should be 1 Hz, but implementers actually seem
+ to choose different clocks here, like Cortina who chose
+ 32768 Hz (a typical low-power clock).
+- clock-names: should name the clocks "PCLK" and "EXTCLK"
+ respectively.
+
+Examples:
+
+rtc@45000000 {
+ compatible = "cortina,gemini-rtc";
+ reg = <0x45000000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&foo 0>, <&foo 1>;
+ clock-names = "PCLK", "EXTCLK";
+};
diff --git a/dts/Bindings/rtc/st,stm32-rtc.txt b/dts/Bindings/rtc/st,stm32-rtc.txt
index e2837b9512..0a4c371a9b 100644
--- a/dts/Bindings/rtc/st,stm32-rtc.txt
+++ b/dts/Bindings/rtc/st,stm32-rtc.txt
@@ -1,17 +1,25 @@
STM32 Real Time Clock
Required properties:
-- compatible: "st,stm32-rtc".
+- compatible: can be either "st,stm32-rtc" or "st,stm32h7-rtc", depending on
+ the device is compatible with stm32(f4/f7) or stm32h7.
- reg: address range of rtc register set.
-- clocks: reference to the clock entry ck_rtc.
+- clocks: can use up to two clocks, depending on part used:
+ - "rtc_ck": RTC clock source.
+ It is required on stm32(f4/f7) and stm32h7.
+ - "pclk": RTC APB interface clock.
+ It is not present on stm32(f4/f7).
+ It is required on stm32h7.
+- clock-names: must be "rtc_ck" and "pclk".
+ It is required only on stm32h7.
- interrupt-parent: phandle for the interrupt controller.
- interrupts: rtc alarm interrupt.
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
(RTC registers) write protection.
-Optional properties (to override default ck_rtc parent clock):
-- assigned-clocks: reference to the ck_rtc clock entry.
-- assigned-clock-parents: phandle of the new parent clock of ck_rtc.
+Optional properties (to override default rtc_ck parent clock):
+- assigned-clocks: reference to the rtc_ck clock entry.
+- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
Example:
@@ -25,3 +33,17 @@ Example:
interrupts = <17 1>;
st,syscfg = <&pwrcfg>;
};
+
+ rtc: rtc@58004000 {
+ compatible = "st,stm32h7-rtc";
+ reg = <0x58004000 0x400>;
+ clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
+ clock-names = "pclk", "rtc_ck";
+ assigned-clocks = <&rcc RTC_CK>;
+ assigned-clock-parents = <&rcc LSE_CK>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 1>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/serial/8250.txt b/dts/Bindings/serial/8250.txt
index 10276a46ec..419ff6c0a4 100644
--- a/dts/Bindings/serial/8250.txt
+++ b/dts/Bindings/serial/8250.txt
@@ -20,6 +20,8 @@ Required properties:
- "fsl,16550-FIFO64"
- "fsl,ns16550"
- "ti,da830-uart"
+ - "aspeed,ast2400-vuart"
+ - "aspeed,ast2500-vuart"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
@@ -45,6 +47,7 @@ Optional properties:
property.
- tx-threshold: Specify the TX FIFO low water indication for parts with
programmable TX FIFO thresholds.
+- resets : phandle + reset specifier pairs
Note:
* fsl,ns16550:
diff --git a/dts/Bindings/serial/actions,owl-uart.txt b/dts/Bindings/serial/actions,owl-uart.txt
new file mode 100644
index 0000000000..aa873eada0
--- /dev/null
+++ b/dts/Bindings/serial/actions,owl-uart.txt
@@ -0,0 +1,16 @@
+Actions Semi Owl UART
+
+Required properties:
+- compatible : "actions,s500-uart", "actions,owl-uart" for S500
+ "actions,s900-uart", "actions,owl-uart" for S900
+- reg : Offset and length of the register set for the device.
+- interrupts : Should contain UART interrupt.
+
+
+Example:
+
+ uart3: serial@b0126000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0126000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/serial/amlogic,meson-uart.txt b/dts/Bindings/serial/amlogic,meson-uart.txt
new file mode 100644
index 0000000000..8ff65fa632
--- /dev/null
+++ b/dts/Bindings/serial/amlogic,meson-uart.txt
@@ -0,0 +1,38 @@
+Amlogic Meson SoC UART Serial Interface
+=======================================
+
+The Amlogic Meson SoC UART Serial Interface is present on a large range
+of SoCs, and can be present either in the "Always-On" power domain or the
+"Everything-Else" power domain.
+
+The particularity of the "Always-On" Serial Interface is that the hardware
+is active since power-on and does not need any clock gating and is usable
+as very early serial console.
+
+Required properties:
+- compatible : compatible: value should be different for each SoC family as :
+ - Meson6 : "amlogic,meson6-uart"
+ - Meson8 : "amlogic,meson8-uart"
+ - Meson8b : "amlogic,meson8b-uart"
+ - GX (GXBB, GXL, GXM) : "amlogic,meson-gx-uart"
+ eventually followed by : "amlogic,meson-ao-uart" if this UART interface
+ is in the "Always-On" power domain.
+- reg : offset and length of the register set for the device.
+- interrupts : identifier to the device interrupt
+- clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock names.
+- clocks-names :
+ * "xtal" for external xtal clock identifier
+ * "pclk" for the bus core clock, either the clk81 clock or the gate clock
+ * "baud" for the source of the baudrate generator, can be either the xtal
+ or the pclk.
+
+e.g.
+uart_A: serial@84c0 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x84c0 0x0 0x14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ /* Use xtal as baud rate clock source */
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
diff --git a/dts/Bindings/serial/fsl-lpuart.txt b/dts/Bindings/serial/fsl-lpuart.txt
index c95005efbc..a1252a047f 100644
--- a/dts/Bindings/serial/fsl-lpuart.txt
+++ b/dts/Bindings/serial/fsl-lpuart.txt
@@ -6,6 +6,8 @@ Required properties:
on Vybrid vf610 SoC with 8-bit register organization
- "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
on LS1021A SoC with 32-bit big-endian register organization
+ - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
+ on i.MX7ULP SoC with 32-bit little-endian register organization
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
- clocks : phandle + clock specifier pairs, one for each entry in clock-names
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index 0015c722be..b6cf384597 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -8,6 +8,8 @@ Required properties:
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6755-uart" for MT6755 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
+ * "mediatek,mt6797-uart" for MT6797 compatible UARTS
+ * "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
diff --git a/dts/Bindings/serial/slave-device.txt b/dts/Bindings/serial/slave-device.txt
index f66037928f..40110e0196 100644
--- a/dts/Bindings/serial/slave-device.txt
+++ b/dts/Bindings/serial/slave-device.txt
@@ -21,6 +21,15 @@ Optional Properties:
can support. For example, a particular board has some signal
quality issue or the host processor can't support higher
baud rates.
+- current-speed : The current baud rate the device operates at. This should
+ only be present in case a driver has no chance to know
+ the baud rate of the slave device.
+ Examples:
+ * device supports auto-baud
+ * the rate is setup by a bootloader and there is no
+ way to reset the device
+ * device baud rate is configured by its firmware but
+ there is no way to request the actual settings
Example:
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
index 16fe94d778..b1d165b4d4 100644
--- a/dts/Bindings/soc/mediatek/scpsys.txt
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -9,11 +9,14 @@ domain control.
The driver implements the Generic PM domain bindings described in
power/power_domain.txt. It provides the power domains defined in
-include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
+- include/dt-bindings/power/mt8173-power.h
+- include/dt-bindings/power/mt6797-power.h
+- include/dt-bindings/power/mt2701-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
+ - "mediatek,mt6797-scpsys"
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@@ -22,6 +25,7 @@ Required properties:
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
+ Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
diff --git a/dts/Bindings/soc/qcom/qcom,glink.txt b/dts/Bindings/soc/qcom/qcom,glink.txt
new file mode 100644
index 0000000000..50fc20c6ce
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,glink.txt
@@ -0,0 +1,73 @@
+Qualcomm RPM GLINK binding
+
+This binding describes the Qualcomm RPM GLINK, a fifo based mechanism for
+communication with the Resource Power Management system on various Qualcomm
+platforms.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,glink-rpm"
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the IRQ used by the remote processor to
+ signal this processor about communication related events
+
+- qcom,rpm-msg-ram:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: handle to RPM message memory resource
+
+- mboxes:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the "rpm_hlos" mailbox in APCS, as described
+ in mailbox/mailbox.txt
+
+= GLINK DEVICES
+Each subnode of the GLINK node represent function tied to a virtual
+communication channel. The name of the nodes are not important. The properties
+of these nodes are defined by the individual bindings for the specific function
+- but must contain the following property:
+
+- qcom,glink-channels:
+ Usage: required
+ Value type: <stringlist>
+ Definition: a list of channels tied to this function, used for matching
+ the function to a set of virtual channels
+
+= EXAMPLE
+The following example represents the GLINK RPM node on a MSM8996 device, with
+the function for the "rpm_request" channel defined, which is used for
+regualtors and root clocks.
+
+ apcs_glb: mailbox@9820000 {
+ compatible = "qcom,msm8996-apcs-hmss-global";
+ reg = <0x9820000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ rpm_msg_ram: memory@68000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x68000 0x6000>;
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ mboxes = <&apcs_glb 0>;
+
+ rpm-requests {
+ compatible = "qcom,rpm-msm8996";
+ qcom,glink-channels = "rpm_requests";
+
+ ...
+ };
+ };
diff --git a/dts/Bindings/sound/audio-graph-card.txt b/dts/Bindings/sound/audio-graph-card.txt
new file mode 100644
index 0000000000..6e6720aa33
--- /dev/null
+++ b/dts/Bindings/sound/audio-graph-card.txt
@@ -0,0 +1,129 @@
+Audio Graph Card:
+
+Audio Graph Card specifies audio DAI connections of SoC <-> codec.
+It is based on common bindings for device graphs.
+see ${LINUX}/Documentation/devicetree/bindings/graph.txt
+
+Basically, Audio Graph Card property is same as Simple Card.
+see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt
+
+Below are same as Simple-Card.
+
+- label
+- widgets
+- routing
+- dai-format
+- frame-master
+- bitclock-master
+- bitclock-inversion
+- frame-inversion
+- dai-tdm-slot-num
+- dai-tdm-slot-width
+- clocks / system-clock-frequency
+
+Required properties:
+
+- compatible : "audio-graph-card";
+- dais : list of CPU DAI port{s}
+
+Optional properties:
+- pa-gpios: GPIO used to control external amplifier.
+
+Example: Single DAI case
+
+ sound_card {
+ compatible = "audio-graph-card";
+
+ dais = <&cpu_port>;
+ };
+
+ dai-controller {
+ ...
+ cpu_port: port {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+
+ dai-format = "left_j";
+ ...
+ };
+ };
+ };
+
+ audio-codec {
+ ...
+ port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint>;
+ };
+ };
+ };
+
+Example: Multi DAI case
+
+ sound-card {
+ compatible = "audio-graph-card";
+
+ label = "sound-card";
+
+ dais = <&cpu_port0
+ &cpu_port1
+ &cpu_port2>;
+ };
+
+ audio-codec@0 {
+ ...
+ port {
+ codec0_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint0>;
+ };
+ };
+ };
+
+ audio-codec@1 {
+ ...
+ port {
+ codec1_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint1>;
+ };
+ };
+ };
+
+ audio-codec@2 {
+ ...
+ port {
+ codec2_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint2>;
+ };
+ };
+ };
+
+ dai-controller {
+ ...
+ ports {
+ cpu_port0: port@0 {
+ cpu_endpoint0: endpoint {
+ remote-endpoint = <&codec0_endpoint>;
+
+ dai-format = "left_j";
+ ...
+ };
+ };
+ cpu_port1: port@1 {
+ cpu_endpoint1: endpoint {
+ remote-endpoint = <&codec1_endpoint>;
+
+ dai-format = "i2s";
+ ...
+ };
+ };
+ cpu_port2: port@2 {
+ cpu_endpoint2: endpoint {
+ remote-endpoint = <&codec2_endpoint>;
+
+ dai-format = "i2s";
+ ...
+ };
+ };
+ };
+ };
+
diff --git a/dts/Bindings/sound/audio-graph-scu-card.txt b/dts/Bindings/sound/audio-graph-scu-card.txt
new file mode 100644
index 0000000000..8b8afe9fcb
--- /dev/null
+++ b/dts/Bindings/sound/audio-graph-scu-card.txt
@@ -0,0 +1,122 @@
+Audio-Graph-SCU-Card:
+
+Audio-Graph-SCU-Card is "Audio-Graph-Card" + "ALSA DPCM".
+
+It is based on common bindings for device graphs.
+see ${LINUX}/Documentation/devicetree/bindings/graph.txt
+
+Basically, Audio-Graph-SCU-Card property is same as
+Simple-Card / Simple-SCU-Card / Audio-Graph-Card.
+see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt
+ ${LINUX}/Documentation/devicetree/bindings/sound/simple-scu-card.txt
+ ${LINUX}/Documentation/devicetree/bindings/sound/audio-graph-card.txt
+
+Below are same as Simple-Card / Audio-Graph-Card.
+
+- label
+- dai-format
+- frame-master
+- bitclock-master
+- bitclock-inversion
+- frame-inversion
+- dai-tdm-slot-num
+- dai-tdm-slot-width
+- clocks / system-clock-frequency
+
+Below are same as Simple-SCU-Card.
+
+- convert-rate
+- convert-channels
+- prefix
+- routing
+
+Required properties:
+
+- compatible : "audio-graph-scu-card";
+- dais : list of CPU DAI port{s}
+
+Example 1. Sampling Rate Conversion
+
+ sound_card {
+ compatible = "audio-graph-scu-card";
+
+ label = "sound-card";
+ prefix = "codec";
+ routing = "codec Playback", "DAI0 Playback",
+ "codec Playback", "DAI1 Playback";
+ convert-rate = <48000>;
+
+ dais = <&cpu_port>;
+ };
+
+ audio-codec {
+ ...
+
+ port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint>;
+ };
+ };
+ };
+
+ dai-controller {
+ ...
+ cpu_port: port {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+
+ dai-format = "left_j";
+ ...
+ };
+ };
+ };
+
+Example 2. 2 CPU 1 Codec (Mixing)
+
+ sound_card {
+ compatible = "audio-graph-scu-card";
+
+ label = "sound-card";
+ prefix = "codec";
+ routing = "codec Playback", "DAI0 Playback",
+ "codec Playback", "DAI1 Playback";
+ convert-rate = <48000>;
+
+ dais = <&cpu_port0
+ &cpu_port1>;
+ };
+
+ audio-codec {
+ ...
+
+ port {
+ codec_endpoint0: endpoint {
+ remote-endpoint = <&cpu_endpoint0>;
+ };
+ codec_endpoint1: endpoint {
+ remote-endpoint = <&cpu_endpoint1>;
+ };
+ };
+ };
+
+ dai-controller {
+ ...
+ ports {
+ cpu_port0: port {
+ cpu_endpoint0: endpoint {
+ remote-endpoint = <&codec_endpoint0>;
+
+ dai-format = "left_j";
+ ...
+ };
+ };
+ cpu_port1: port {
+ cpu_endpoint1: endpoint {
+ remote-endpoint = <&codec_endpoint1>;
+
+ dai-format = "left_j";
+ ...
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/cs35l35.txt b/dts/Bindings/sound/cs35l35.txt
index 016b768bc7..77ee75c392 100644
--- a/dts/Bindings/sound/cs35l35.txt
+++ b/dts/Bindings/sound/cs35l35.txt
@@ -16,6 +16,9 @@ Required properties:
(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
for further information relating to interrupt properties)
+ - cirrus,boost-ind-nanohenry: Inductor value for boost converter. The value is
+ in nH and they can be values of 1000nH, 1200nH, 1500nH, and 2200nH.
+
Optional properties:
- reset-gpios : gpio used to reset the amplifier
diff --git a/dts/Bindings/sound/nau8825.txt b/dts/Bindings/sound/nau8825.txt
index d3374231c8..2f5e973285 100644
--- a/dts/Bindings/sound/nau8825.txt
+++ b/dts/Bindings/sound/nau8825.txt
@@ -69,6 +69,8 @@ Optional properties:
- nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
- nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
+ - nuvoton,crosstalk-bypass: make crosstalk function bypass if set.
+
- clocks: list of phandle and clock specifier pairs according to common clock bindings for the
clocks described in clock-names
- clock-names: should include "mclk" for the MCLK master clock
@@ -96,6 +98,7 @@ Example:
nuvoton,short-key-debounce = <2>;
nuvoton,jack-insert-debounce = <7>;
nuvoton,jack-eject-debounce = <7>;
+ nuvoton,crosstalk-bypass;
clock-names = "mclk";
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index 15a7316e4c..7246bb268b 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -83,11 +83,11 @@ SRC can convert [xx]Hz to [yy]Hz. Then, it has below 2 modes
** Asynchronous mode
------------------
-You need to use "renesas,rsrc-card" sound card for it.
+You need to use "simple-scu-audio-card" sound card for it.
example)
sound {
- compatible = "renesas,rsrc-card";
+ compatible = "simple-scu-audio-card";
...
/*
* SRC Asynchronous mode setting
@@ -97,12 +97,12 @@ example)
* Inputed 48kHz data will be converted to
* system specified Hz
*/
- convert-rate = <48000>;
+ simple-audio-card,convert-rate = <48000>;
...
- cpu {
+ simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
- codec {
+ simple-audio-card,codec {
...
};
};
@@ -141,23 +141,23 @@ For more detail information, see below
${LINUX}/sound/soc/sh/rcar/ctu.c
- comment of header
-You need to use "renesas,rsrc-card" sound card for it.
+You need to use "simple-scu-audio-card" sound card for it.
example)
sound {
- compatible = "renesas,rsrc-card";
+ compatible = "simple-scu-audio-card";
...
/*
* CTU setting
* All input data will be converted to 2ch
* as output data
*/
- convert-channels = <2>;
+ simple-audio-card,convert-channels = <2>;
...
- cpu {
+ simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
- codec {
+ simple-audio-card,codec {
...
};
};
@@ -190,22 +190,22 @@ and these sounds will be merged by MIX.
aplay -D plughw:0,0 xxxx.wav &
aplay -D plughw:0,1 yyyy.wav
-You need to use "renesas,rsrc-card" sound card for it.
+You need to use "simple-scu-audio-card" sound card for it.
Ex)
[MEM] -> [SRC1] -> [CTU02] -+-> [MIX0] -> [DVC0] -> [SSI0]
|
[MEM] -> [SRC2] -> [CTU03] -+
sound {
- compatible = "renesas,rsrc-card";
+ compatible = "simple-scu-audio-card";
...
- cpu@0 {
+ simple-audio-card,cpu@0 {
sound-dai = <&rcar_sound 0>;
};
- cpu@1 {
+ simple-audio-card,cpu@1 {
sound-dai = <&rcar_sound 1>;
};
- codec {
+ simple-audio-card,codec {
...
};
};
@@ -368,6 +368,10 @@ Required properties:
see below for detail.
- #sound-dai-cells : it must be 0 if your system is using single DAI
it must be 1 if your system is using multi DAI
+- clocks : References to SSI/SRC/MIX/CTU/DVC/AUDIO_CLK clocks.
+- clock-names : List of necessary clock names.
+ "ssi-all", "ssi.X", "src.X", "mix.X", "ctu.X",
+ "dvc.X", "clk_a", "clk_b", "clk_c", "clk_i"
Optional properties:
- #clock-cells : it must be 0 if your system has audio_clkout
@@ -375,6 +379,9 @@ Optional properties:
- clock-frequency : for all audio_clkout0/1/2/3
- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn
is asynchronizes with lr-clock.
+- resets : References to SSI resets.
+- reset-names : List of valid reset names.
+ "ssi-all", "ssi.X"
SSI subnode properties:
- interrupts : Should contain SSI interrupt for PIO transfer
diff --git a/dts/Bindings/sound/rockchip,pdm.txt b/dts/Bindings/sound/rockchip,pdm.txt
new file mode 100644
index 0000000000..921729de73
--- /dev/null
+++ b/dts/Bindings/sound/rockchip,pdm.txt
@@ -0,0 +1,39 @@
+* Rockchip PDM controller
+
+Required properties:
+
+- compatible: "rockchip,pdm"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- dmas: DMA specifiers for rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: should include "rx".
+- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
+- clock-names: should contain following:
+ - "pdm_hclk": clock for PDM BUS
+ - "pdm_clk" : clock for PDM controller
+- pinctrl-names: Must contain a "default" entry.
+- pinctrl-N: One property must exist for each entry in
+ pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
+ for details of the property values.
+
+Example for rk3328 PDM controller:
+
+pdm: pdm@ff040000 {
+ compatible = "rockchip,pdm";
+ reg = <0x0 0xff040000 0x0 0x1000>;
+ clocks = <&clk_pdm>, <&clk_gates28 0>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&pdma 16>;
+ #dma-cells = <1>;
+ dma-names = "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_fsync
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-1 = <&pdmm0_sleep>;
+ status = "disabled";
+};
diff --git a/dts/Bindings/sound/rockchip-spdif.txt b/dts/Bindings/sound/rockchip-spdif.txt
index 11046429a1..4706b96d45 100644
--- a/dts/Bindings/sound/rockchip-spdif.txt
+++ b/dts/Bindings/sound/rockchip-spdif.txt
@@ -9,7 +9,9 @@ Required properties:
- compatible: should be one of the following:
- "rockchip,rk3066-spdif"
- "rockchip,rk3188-spdif"
+ - "rockchip,rk3228-spdif"
- "rockchip,rk3288-spdif"
+ - "rockchip,rk3328-spdif"
- "rockchip,rk3366-spdif"
- "rockchip,rk3368-spdif"
- "rockchip,rk3399-spdif"
diff --git a/dts/Bindings/sound/samsung,odroid.txt b/dts/Bindings/sound/samsung,odroid.txt
index c1ac70cb0a..c30934dd97 100644
--- a/dts/Bindings/sound/samsung,odroid.txt
+++ b/dts/Bindings/sound/samsung,odroid.txt
@@ -5,11 +5,6 @@ Required properties:
- compatible - "samsung,odroidxu3-audio" - for Odroid XU3 board,
"samsung,odroidxu4-audio" - for Odroid XU4 board
- model - the user-visible name of this sound complex
- - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
- controller
- - 'codec' subnode with a 'sound-dai' property containing list of phandles
- to the CODEC nodes, first entry must be corresponding to the MAX98090
- CODEC and the second entry must be the phandle of the HDMI IP block node
- clocks - should contain entries matching clock names in the clock-names
property
- clock-names - should contain following entries:
@@ -32,12 +27,18 @@ Required properties:
For Odroid XU4:
no entries
+Required sub-nodes:
+
+ - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
+ controller
+ - 'codec' subnode with a 'sound-dai' property containing list of phandles
+ to the CODEC nodes, first entry must be corresponding to the MAX98090
+ CODEC and the second entry must be the phandle of the HDMI IP block node
+
Example:
sound {
compatible = "samsung,odroidxu3-audio";
- samsung,cpu-dai = <&i2s0>;
- samsung,codec-dai = <&max98090>;
model = "Odroid-XU3";
samsung,audio-routing =
"Headphone Jack", "HPL",
diff --git a/dts/Bindings/sound/simple-scu-card.txt b/dts/Bindings/sound/simple-scu-card.txt
index d6fe47ed09..327d229a51 100644
--- a/dts/Bindings/sound/simple-scu-card.txt
+++ b/dts/Bindings/sound/simple-scu-card.txt
@@ -1,35 +1,29 @@
-ASoC simple SCU Sound Card
+ASoC Simple SCU Sound Card
-Simple-Card specifies audio DAI connections of SoC <-> codec.
+Simple SCU Sound Card is "Simple Sound Card" + "ALSA DPCM".
+For example, you can use this driver if you want to exchange sampling rate convert,
+Mixing, etc...
Required properties:
- compatible : "simple-scu-audio-card"
"renesas,rsrc-card"
-
Optional properties:
-- simple-audio-card,name : User specified audio sound card name, one string
- property.
-- simple-audio-card,cpu : CPU sub-node
-- simple-audio-card,codec : CODEC sub-node
+- simple-audio-card,name : see simple-audio-card.txt
+- simple-audio-card,cpu : see simple-audio-card.txt
+- simple-audio-card,codec : see simple-audio-card.txt
Optional subnode properties:
-- simple-audio-card,format : CPU/CODEC common audio format.
- "i2s", "right_j", "left_j" , "dsp_a"
- "dsp_b", "ac97", "pdm", "msb", "lsb"
-- simple-audio-card,frame-master : Indicates dai-link frame master.
- phandle to a cpu or codec subnode.
-- simple-audio-card,bitclock-master : Indicates dai-link bit clock master.
- phandle to a cpu or codec subnode.
-- simple-audio-card,bitclock-inversion : bool property. Add this if the
- dai-link uses bit clock inversion.
-- simple-audio-card,frame-inversion : bool property. Add this if the
- dai-link uses frame clock inversion.
+- simple-audio-card,format : see simple-audio-card.txt
+- simple-audio-card,frame-master : see simple-audio-card.txt
+- simple-audio-card,bitclock-master : see simple-audio-card.txt
+- simple-audio-card,bitclock-inversion : see simple-audio-card.txt
+- simple-audio-card,frame-inversion : see simple-audio-card.txt
- simple-audio-card,convert-rate : platform specified sampling rate convert
- simple-audio-card,convert-channels : platform specified converted channel size (2 - 8 ch)
-- simple-audio-card,prefix : see audio-routing
+- simple-audio-card,prefix : see routing
- simple-audio-card,routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source. Valid names for sources.
@@ -38,32 +32,23 @@ Optional subnode properties:
Required CPU/CODEC subnodes properties:
-- sound-dai : phandle and port of CPU/CODEC
+- sound-dai : see simple-audio-card.txt
Optional CPU/CODEC subnodes properties:
-- clocks / system-clock-frequency : specify subnode's clock if needed.
- it can be specified via "clocks" if system has
- clock node (= common clock), or "system-clock-frequency"
- (if system doens't support common clock)
- If a clock is specified, it is
- enabled with clk_prepare_enable()
- in dai startup() and disabled with
- clk_disable_unprepare() in dai
- shutdown().
+- clocks / system-clock-frequency : see simple-audio-card.txt
-Example 1. Sampling Rate Covert
+Example 1. Sampling Rate Conversion
sound {
compatible = "simple-scu-audio-card";
simple-audio-card,name = "rsnd-ak4643";
simple-audio-card,format = "left_j";
- simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
- simple-audio-card,convert-rate = <48000>; /* see audio_clk_a */
+ simple-audio-card,convert-rate = <48000>;
simple-audio-card,prefix = "ak4642";
simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback",
@@ -79,20 +64,18 @@ sound {
};
};
-Example 2. 2 CPU 1 Codec
+Example 2. 2 CPU 1 Codec (Mixing)
sound {
- compatible = "renesas,rsrc-card";
-
- card-name = "rsnd-ak4643";
- format = "left_j";
- bitclock-master = <&dpcmcpu>;
- frame-master = <&dpcmcpu>;
+ compatible = "simple-scu-audio-card";
- convert-rate = <48000>; /* see audio_clk_a */
+ simple-audio-card,name = "rsnd-ak4643";
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&dpcmcpu>;
+ simple-audio-card,frame-master = <&dpcmcpu>;
- audio-prefix = "ak4642";
- audio-routing = "ak4642 Playback", "DAI0 Playback",
+ simple-audio-card,prefix = "ak4642";
+ simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback",
"ak4642 Playback", "DAI1 Playback";
dpcmcpu: cpu@0 {
diff --git a/dts/Bindings/sound/st,stm32-i2s.txt b/dts/Bindings/sound/st,stm32-i2s.txt
new file mode 100644
index 0000000000..4bda520424
--- /dev/null
+++ b/dts/Bindings/sound/st,stm32-i2s.txt
@@ -0,0 +1,62 @@
+STMicroelectronics STM32 SPI/I2S Controller
+
+The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
+Only some SPI instances support I2S.
+
+Required properties:
+ - compatible: Must be "st,stm32h7-i2s"
+ - reg: Offset and length of the device's register set.
+ - interrupts: Must contain the interrupt line id.
+ - clocks: Must contain phandle and clock specifier pairs for each entry
+ in clock-names.
+ - clock-names: Must contain "i2sclk", "pclk", "x8k" and "x11k".
+ "i2sclk": clock which feeds the internal clock generator
+ "pclk": clock which feeds the peripheral bus interface
+ "x8k": I2S parent clock for sampling rates multiple of 8kHz.
+ "x11k": I2S parent clock for sampling rates multiple of 11.025kHz.
+ - dmas: DMA specifiers for tx and rx dma.
+ See Documentation/devicetree/bindings/dma/stm32-dma.txt.
+ - dma-names: Identifier for each DMA request line. Must be "tx" and "rx".
+ - pinctrl-names: should contain only value "default"
+ - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
+
+Optional properties:
+ - resets: Reference to a reset controller asserting the reset controller
+
+The device node should contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in Documentation/devicetree/bindings/
+graph.txt.
+
+Example:
+sound_card {
+ compatible = "audio-graph-card";
+ dais = <&i2s2_port>;
+};
+
+i2s2: audio-controller@40003800 {
+ compatible = "st,stm32h7-i2s";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
+ dmas = <&dmamux2 2 39 0x400 0x1>,
+ <&dmamux2 3 40 0x400 0x1>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s2>;
+
+ i2s2_port: port@0 {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ format = "i2s";
+ };
+ };
+};
+
+audio-codec {
+ codec_port: port@0 {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint>;
+ };
+ };
+};
diff --git a/dts/Bindings/sound/st,stm32-sai.txt b/dts/Bindings/sound/st,stm32-sai.txt
index c59a3d779e..f1c5ae59e7 100644
--- a/dts/Bindings/sound/st,stm32-sai.txt
+++ b/dts/Bindings/sound/st,stm32-sai.txt
@@ -6,7 +6,7 @@ The SAI contains two independent audio sub-blocks. Each sub-block has
its own clock generator and I/O lines controller.
Required properties:
- - compatible: Should be "st,stm32f4-sai"
+ - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai"
- reg: Base address and size of SAI common register set.
- clocks: Must contain phandle and clock specifier pairs for each entry
in clock-names.
@@ -36,6 +36,10 @@ SAI subnodes required properties:
- pinctrl-names: should contain only value "default"
- pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
+The device node should contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in Documentation/devicetree/bindings/
+graph.txt.
+
Example:
sound_card {
compatible = "audio-graph-card";
@@ -43,38 +47,29 @@ sound_card {
};
sai1: sai1@40015800 {
- compatible = "st,stm32f4-sai";
+ compatible = "st,stm32h7-sai";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 0x40015800 0x400>;
reg = <0x40015800 0x4>;
- clocks = <&rcc 1 CLK_SAIQ_PDIV>, <&rcc 1 CLK_I2SQ_PDIV>;
+ clocks = <&rcc PLL1_Q>, <&rcc PLL2_P>;
clock-names = "x8k", "x11k";
interrupts = <87>;
- sai1b: audio-controller@40015824 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x40015824 0x1C>;
- clocks = <&rcc 1 CLK_SAI2>;
+ sai1a: audio-controller@40015804 {
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1C>;
+ clocks = <&rcc SAI1_CK>;
clock-names = "sai_ck";
- dmas = <&dma2 5 0 0x400 0x0>;
+ dmas = <&dmamux1 1 87 0x400 0x0>;
dma-names = "tx";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai1b>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai1a>;
- sai1b_port: port@0 {
- reg = <0>;
- cpu_endpoint: endpoint {
- remote-endpoint = <&codec_endpoint>;
- audio-graph-card,format = "i2s";
- audio-graph-card,bitclock-master = <&codec_endpoint>;
- audio-graph-card,frame-master = <&codec_endpoint>;
- };
+ sai1b_port: port {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ format = "i2s";
};
};
};
diff --git a/dts/Bindings/sound/st,stm32-spdifrx.txt b/dts/Bindings/sound/st,stm32-spdifrx.txt
new file mode 100644
index 0000000000..33826f2459
--- /dev/null
+++ b/dts/Bindings/sound/st,stm32-spdifrx.txt
@@ -0,0 +1,56 @@
+STMicroelectronics STM32 S/PDIF receiver (SPDIFRX).
+
+The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with
+IEC-60958 and IEC-61937.
+
+Required properties:
+ - compatible: should be "st,stm32h7-spdifrx"
+ - reg: cpu DAI IP base address and size
+ - clocks: must contain an entry for kclk (used as S/PDIF signal reference)
+ - clock-names: must contain "kclk"
+ - interrupts: cpu DAI interrupt line
+ - dmas: DMA specifiers for audio data DMA and iec control flow DMA
+ See STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt
+ - dma-names: two dmas have to be defined, "rx" and "rx-ctrl"
+
+Optional properties:
+ - resets: Reference to a reset controller asserting the SPDIFRX
+
+The device node should contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in Documentation/devicetree/bindings/
+graph.txt.
+
+Example:
+spdifrx: spdifrx@40004000 {
+ compatible = "st,stm32h7-spdifrx";
+ reg = <0x40004000 0x400>;
+ clocks = <&rcc SPDIFRX_CK>;
+ clock-names = "kclk";
+ interrupts = <97>;
+ dmas = <&dmamux1 2 93 0x400 0x0>,
+ <&dmamux1 3 94 0x400 0x0>;
+ dma-names = "rx", "rx-ctrl";
+ pinctrl-0 = <&spdifrx_pins>;
+ pinctrl-names = "default";
+
+ spdifrx_port: port {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ };
+ };
+};
+
+spdif_in: spdif-in {
+ compatible = "linux,spdif-dir";
+
+ codec_port: port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint>;
+ };
+ };
+};
+
+soundcard {
+ compatible = "audio-graph-card";
+ dais = <&spdifrx_port>;
+};
diff --git a/dts/Bindings/sound/sun4i-codec.txt b/dts/Bindings/sound/sun4i-codec.txt
index 3863531d1e..2d4e10deb6 100644
--- a/dts/Bindings/sound/sun4i-codec.txt
+++ b/dts/Bindings/sound/sun4i-codec.txt
@@ -7,6 +7,7 @@ Required properties:
- "allwinner,sun7i-a20-codec"
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+ - "allwinner,sun8i-v3s-codec"
- reg: must contain the registers location and length
- interrupts: must contain the codec interrupt
- dmas: DMA channels for tx and rx dma. See the DMA client binding,
@@ -25,6 +26,7 @@ Required properties for the following compatibles:
- "allwinner,sun6i-a31-codec"
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+ - "allwinner,sun8i-v3s-codec"
- resets: phandle to the reset control for this device
- allwinner,audio-routing: A list of the connections between audio components.
Each entry is a pair of strings, the first being the
@@ -34,15 +36,15 @@ Required properties for the following compatibles:
Audio pins on the SoC:
"HP"
"HPCOM"
- "LINEIN"
- "LINEOUT" (not on sun8i-a23)
+ "LINEIN" (not on sun8i-v3s)
+ "LINEOUT" (not on sun8i-a23 or sun8i-v3s)
"MIC1"
- "MIC2"
+ "MIC2" (not on sun8i-v3s)
"MIC3" (sun6i-a31 only)
Microphone biases from the SoC:
"HBIAS"
- "MBIAS"
+ "MBIAS" (not on sun8i-v3s)
Board connectors:
"Headphone"
@@ -55,6 +57,7 @@ Required properties for the following compatibles:
Required properties for the following compatibles:
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+ - "allwinner,sun8i-v3s-codec"
- allwinner,codec-analog-controls: A phandle to the codec analog controls
block in the PRCM.
diff --git a/dts/Bindings/sound/sun8i-codec-analog.txt b/dts/Bindings/sound/sun8i-codec-analog.txt
index 779b735781..1b6e7c4e50 100644
--- a/dts/Bindings/sound/sun8i-codec-analog.txt
+++ b/dts/Bindings/sound/sun8i-codec-analog.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: must be one of the following compatibles:
- "allwinner,sun8i-a23-codec-analog"
- "allwinner,sun8i-h3-codec-analog"
+ - "allwinner,sun8i-v3s-codec-analog"
Required properties if not a sub-node of the PRCM node:
- reg: must contain the registers location and length
diff --git a/dts/Bindings/sound/zte,zx-aud96p22.txt b/dts/Bindings/sound/zte,zx-aud96p22.txt
new file mode 100644
index 0000000000..41bb1040eb
--- /dev/null
+++ b/dts/Bindings/sound/zte,zx-aud96p22.txt
@@ -0,0 +1,24 @@
+ZTE ZX AUD96P22 Audio Codec
+
+Required properties:
+ - compatible: Must be "zte,zx-aud96p22"
+ - #sound-dai-cells: Should be 0
+ - reg: I2C bus slave address of AUD96P22
+
+Example:
+
+ i2c0: i2c@1486000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x01486000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&audiocrm AUDIO_I2C0_WCLK>;
+ clock-frequency = <1600000>;
+
+ aud96p22: codec@22 {
+ compatible = "zte,zx-aud96p22";
+ #sound-dai-cells = <0>;
+ reg = <0x22>;
+ };
+ };
diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt
index dc975064fa..64ee489571 100644
--- a/dts/Bindings/spi/sh-msiof.txt
+++ b/dts/Bindings/spi/sh-msiof.txt
@@ -38,6 +38,8 @@ Optional properties:
specifiers, one for transmission, and one for
reception.
- dma-names : Must contain a list of two DMA names, "tx" and "rx".
+- spi-slave : Empty property indicating the SPI controller is used
+ in slave mode.
- renesas,dtdl : delay sync signal (setup) in transmit mode.
Must contain one of the following values:
0 (no bit delay)
diff --git a/dts/Bindings/spi/spi-bus.txt b/dts/Bindings/spi/spi-bus.txt
index 4b1d6e74c7..1f6e86f787 100644
--- a/dts/Bindings/spi/spi-bus.txt
+++ b/dts/Bindings/spi/spi-bus.txt
@@ -1,17 +1,23 @@
SPI (Serial Peripheral Interface) busses
-SPI busses can be described with a node for the SPI master device
-and a set of child nodes for each SPI slave on the bus. For this
-discussion, it is assumed that the system's SPI controller is in
-SPI master mode. This binding does not describe SPI controllers
-in slave mode.
+SPI busses can be described with a node for the SPI controller device
+and a set of child nodes for each SPI slave on the bus. The system's SPI
+controller may be described for use in SPI master mode or in SPI slave mode,
+but not for both at the same time.
-The SPI master node requires the following properties:
+The SPI controller node requires the following properties:
+- compatible - Name of SPI bus controller following generic names
+ recommended practice.
+
+In master mode, the SPI controller node requires the following additional
+properties:
- #address-cells - number of cells required to define a chip select
address on the SPI bus.
- #size-cells - should be zero.
-- compatible - name of SPI bus controller following generic names
- recommended practice.
+
+In slave mode, the SPI controller node requires one additional property:
+- spi-slave - Empty property.
+
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
@@ -21,7 +27,7 @@ assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
-Optional properties:
+Optional properties (master mode only):
- cs-gpios - gpios chip select.
- num-cs - total number of chipselects.
@@ -41,28 +47,36 @@ cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
-SPI slave nodes must be children of the SPI master node and can
-contain the following properties.
-- reg - (required) chip select address of device.
-- compatible - (required) name of SPI device following generic names
- recommended practice.
-- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz.
-- spi-cpol - (optional) Empty property indicating device requires
- inverse clock polarity (CPOL) mode.
-- spi-cpha - (optional) Empty property indicating device requires
- shifted clock phase (CPHA) mode.
-- spi-cs-high - (optional) Empty property indicating device requires
- chip select active high.
-- spi-3wire - (optional) Empty property indicating device requires
- 3-wire mode.
-- spi-lsb-first - (optional) Empty property indicating device requires
- LSB first mode.
-- spi-tx-bus-width - (optional) The bus width (number of data wires) that is
- used for MOSI. Defaults to 1 if not present.
-- spi-rx-bus-width - (optional) The bus width (number of data wires) that is
- used for MISO. Defaults to 1 if not present.
-- spi-rx-delay-us - (optional) Microsecond delay after a read transfer.
-- spi-tx-delay-us - (optional) Microsecond delay after a write transfer.
+
+SPI slave nodes must be children of the SPI controller node.
+
+In master mode, one or more slave nodes (up to the number of chip selects) can
+be present. Required properties are:
+- compatible - Name of SPI device following generic names recommended
+ practice.
+- reg - Chip select address of device.
+- spi-max-frequency - Maximum SPI clocking speed of device in Hz.
+
+In slave mode, the (single) slave node is optional.
+If present, it must be called "slave". Required properties are:
+- compatible - Name of SPI device following generic names recommended
+ practice.
+
+All slave nodes can contain the following optional properties:
+- spi-cpol - Empty property indicating device requires inverse clock
+ polarity (CPOL) mode.
+- spi-cpha - Empty property indicating device requires shifted clock
+ phase (CPHA) mode.
+- spi-cs-high - Empty property indicating device requires chip select
+ active high.
+- spi-3wire - Empty property indicating device requires 3-wire mode.
+- spi-lsb-first - Empty property indicating device requires LSB first mode.
+- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
+ Defaults to 1 if not present.
+- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
+ Defaults to 1 if not present.
+- spi-rx-delay-us - Microsecond delay after a read transfer.
+- spi-tx-delay-us - Microsecond delay after a write transfer.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
diff --git a/dts/Bindings/spi/spi-meson.txt b/dts/Bindings/spi/spi-meson.txt
index dc6d031332..825c39cae7 100644
--- a/dts/Bindings/spi/spi-meson.txt
+++ b/dts/Bindings/spi/spi-meson.txt
@@ -20,3 +20,34 @@ Required properties:
#address-cells = <1>;
#size-cells = <0>;
};
+
+* SPICC (SPI Communication Controller)
+
+The Meson SPICC is generic SPI controller for general purpose Full-Duplex
+communications with dedicated 16 words RX/TX PIO FIFOs.
+
+Required properties:
+ - compatible: should be "amlogic,meson-gx-spicc" on Amlogic GX SoCs.
+ - reg: physical base address and length of the controller registers
+ - interrupts: The interrupt specifier
+ - clock-names: Must contain "core"
+ - clocks: phandle of the input clock for the baud rate generator
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Optional properties:
+ - resets: phandle of the internal reset line
+
+See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
+required and optional properties.
+
+Example :
+ spi@c1108d80 {
+ compatible = "amlogic,meson-gx-spicc";
+ reg = <0xc1108d80 0x80>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&clk81>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/spi/spi-mt65xx.txt b/dts/Bindings/spi/spi-mt65xx.txt
index e43f4cf4cf..e0318cf92d 100644
--- a/dts/Bindings/spi/spi-mt65xx.txt
+++ b/dts/Bindings/spi/spi-mt65xx.txt
@@ -3,7 +3,9 @@ Binding for MTK SPI controller
Required properties:
- compatible: should be one of the following.
- mediatek,mt2701-spi: for mt2701 platforms
+ - mediatek,mt2712-spi: for mt2712 platforms
- mediatek,mt6589-spi: for mt6589 platforms
+ - mediatek,mt7622-spi: for mt7622 platforms
- mediatek,mt8135-spi: for mt8135 platforms
- mediatek,mt8173-spi: for mt8173 platforms
diff --git a/dts/Bindings/spi/spi-stm32.txt b/dts/Bindings/spi/spi-stm32.txt
new file mode 100644
index 0000000000..1b3fa2c119
--- /dev/null
+++ b/dts/Bindings/spi/spi-stm32.txt
@@ -0,0 +1,59 @@
+STMicroelectronics STM32 SPI Controller
+
+The STM32 SPI controller is used to communicate with external devices using
+the Serial Peripheral Interface. It supports full-duplex, half-duplex and
+simplex synchronous serial communication with external devices. It supports
+from 4 to 32-bit data size. Although it can be configured as master or slave,
+only master is supported by the driver.
+
+Required properties:
+- compatible: Must be "st,stm32h7-spi".
+- reg: Offset and length of the device's register set.
+- interrupts: Must contain the interrupt id.
+- clocks: Must contain an entry for spiclk (which feeds the internal clock
+ generator).
+- #address-cells: Number of cells required to define a chip select address.
+- #size-cells: Should be zero.
+
+Optional properties:
+- resets: Must contain the phandle to the reset controller.
+- A pinctrl state named "default" may be defined to set pins in mode of
+ operation for SPI transfer.
+- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the
+ STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt.
+- dma-names: DMA request names should include "tx" and "rx" if present.
+- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+
+Child nodes represent devices on the SPI bus
+ See ../spi/spi-bus.txt
+
+Optional properties:
+- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in
+ nanoseconds inserted between two consecutive data frames.
+
+
+Example:
+ spi2: spi@40003800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc SPI2_CK>;
+ resets = <&rcc 1166>;
+ dmas = <&dmamux1 0 39 0x400 0x01>,
+ <&dmamux1 1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ pinctrl-0 = <&spi2_pins_b>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpioa 11 0>;
+
+ aardvark@0 {
+ compatible = "totalphase,aardvark";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ st,spi-midi-ns = <4000>;
+ };
+ };
diff --git a/dts/Bindings/thermal/brcm,ns-thermal b/dts/Bindings/thermal/brcm,ns-thermal.txt
index 68e0471700..68e0471700 100644
--- a/dts/Bindings/thermal/brcm,ns-thermal
+++ b/dts/Bindings/thermal/brcm,ns-thermal.txt
diff --git a/dts/Bindings/timer/actions,owl-timer.txt b/dts/Bindings/timer/actions,owl-timer.txt
new file mode 100644
index 0000000000..e3c28da80c
--- /dev/null
+++ b/dts/Bindings/timer/actions,owl-timer.txt
@@ -0,0 +1,20 @@
+Actions Semi Owl Timer
+
+Required properties:
+- compatible : "actions,s500-timer" for S500
+ "actions,s900-timer" for S900
+- reg : Offset and length of the register set for the device.
+- interrupts : Should contain the interrupts.
+- interrupt-names : Valid names are: "2hz0", "2hz1",
+ "timer0", "timer1", "timer2", "timer3"
+ See ../resource-names.txt
+
+Example:
+
+ timer@b0168000 {
+ compatible = "actions,s500-timer";
+ reg = <0xb0168000 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "timer0", "timer1";
+ };
diff --git a/dts/Bindings/timer/faraday,fttmr010.txt b/dts/Bindings/timer/faraday,fttmr010.txt
index b73ca6cd07..1957922704 100644
--- a/dts/Bindings/timer/faraday,fttmr010.txt
+++ b/dts/Bindings/timer/faraday,fttmr010.txt
@@ -7,7 +7,11 @@ Required properties:
- compatible : Must be one of
"faraday,fttmr010"
- "cortina,gemini-timer"
+ "cortina,gemini-timer", "faraday,fttmr010"
+ "moxa,moxart-timer", "faraday,fttmr010"
+ "aspeed,ast2400-timer"
+ "aspeed,ast2500-timer"
+
- reg : Should contain registers location and length
- interrupts : Should contain the three timer interrupts usually with
flags for falling edge
diff --git a/dts/Bindings/timer/moxa,moxart-timer.txt b/dts/Bindings/timer/moxa,moxart-timer.txt
deleted file mode 100644
index e207c11630..0000000000
--- a/dts/Bindings/timer/moxa,moxart-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-MOXA ART timer
-
-Required properties:
-
-- compatible : Must be one of:
- - "moxa,moxart-timer"
- - "aspeed,ast2400-timer"
-- reg : Should contain registers location and length
-- interrupts : Should contain the timer interrupt number
-- clocks : Should contain phandle for the clock that drives the counter
-
-Example:
-
- timer: timer@98400000 {
- compatible = "moxa,moxart-timer";
- reg = <0x98400000 0x42>;
- interrupts = <19 1>;
- clocks = <&coreclk>;
- };
diff --git a/dts/Bindings/trivial-devices.txt b/dts/Bindings/trivial-devices.txt
index 3e0a34c88e..35f406dd86 100644
--- a/dts/Bindings/trivial-devices.txt
+++ b/dts/Bindings/trivial-devices.txt
@@ -55,6 +55,7 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In
infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
+isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor
maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt
index f658f394c2..52fb41046b 100644
--- a/dts/Bindings/usb/dwc3.txt
+++ b/dts/Bindings/usb/dwc3.txt
@@ -45,6 +45,8 @@ Optional properties:
a free-running PHY clock.
- snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
from P0 to P1/P2/P3 without delay.
+ - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
+ during HS transmit.
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold
diff --git a/dts/Bindings/usb/exynos-usb.txt b/dts/Bindings/usb/exynos-usb.txt
index 9b4dbe3b2a..78ebebb66d 100644
--- a/dts/Bindings/usb/exynos-usb.txt
+++ b/dts/Bindings/usb/exynos-usb.txt
@@ -92,6 +92,8 @@ Required properties:
parent's address space
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clocks correseponding to IDs in the clock property
+ - vdd10-supply: 1.0V powr supply
+ - vdd33-supply: 3.0V/3.3V power supply
Sub-nodes:
The dwc3 core should be added as subnode to Exynos dwc3 glue.
@@ -107,6 +109,8 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ vdd10-supply = <&ldo11_reg>;
+ vdd33-supply = <&ldo9_reg>;
dwc3 {
compatible = "synopsys,dwc3";
diff --git a/dts/Bindings/usb/iproc-udc.txt b/dts/Bindings/usb/iproc-udc.txt
new file mode 100644
index 0000000000..272d7faf1a
--- /dev/null
+++ b/dts/Bindings/usb/iproc-udc.txt
@@ -0,0 +1,21 @@
+Broadcom IPROC USB Device controller.
+
+The device node is used for UDCs integrated into Broadcom's
+iProc family (Northstar2, Cygnus) of SoCs'. The UDC is based
+on Synopsys Designware Cores AHB Subsystem Device Controller
+IP.
+
+Required properties:
+ - compatible: Add the compatibility strings for supported platforms.
+ For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
+ For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
+ - reg: Offset and length of UDC register set
+ - interrupts: description of interrupt line
+ - phys: phandle to phy node.
+
+Example:
+ udc_dwc: usb@664e0000 {
+ compatible = "brcm,ns2-udc", "brcm,iproc-udc";
+ reg = <0x664e0000 0x2000>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy>;
diff --git a/dts/Bindings/usb/usb-ohci.txt b/dts/Bindings/usb/usb-ohci.txt
index 9df4569685..e8766b08c9 100644
--- a/dts/Bindings/usb/usb-ohci.txt
+++ b/dts/Bindings/usb/usb-ohci.txt
@@ -10,6 +10,7 @@ Optional properties:
- big-endian-desc : boolean, set this for hcds with big-endian descriptors
- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA
+- remote-wakeup-connected: remote wakeup is wired on the platform
- num-ports : u32, to override the detected port count
- clocks : a list of phandle + clock specifier pairs
- phys : phandle + phy specifier pair
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index c03d201403..daf465bef7 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -5,6 +5,7 @@ using them to avoid name-space collisions.
abcn Abracon Corporation
abilis Abilis Systems
+actions Actions Semiconductor Co., Ltd.
active-semi Active-Semi International Inc
ad Avionic Design GmbH
adapteva Adapteva, Inc.
@@ -28,6 +29,7 @@ andestech Andes Technology Corporation
apm Applied Micro Circuits Corporation (APM)
aptina Aptina Imaging
arasan Arasan Chip Systems
+arctic Arctic Sand
aries Aries Embedded GmbH
arm ARM Ltd.
armadeus ARMadeus Systems SARL
@@ -44,6 +46,7 @@ avia avia semiconductor
avic Shanghai AVIC Optoelectronics Co., Ltd.
axentia Axentia Technologies AB
axis Axis Communications AB
+bananapi BIPAI KEJI LIMITED
boe BOE Technology Group Co., Ltd.
bosch Bosch Sensortec GmbH
boundary Boundary Devices Inc.
@@ -158,6 +161,8 @@ iom Iomega Corporation
isee ISEE 2007 S.L.
isil Intersil
issi Integrated Silicon Solutions Inc.
+itead ITEAD Intelligent Systems Co.Ltd
+iwave iWave Systems Technologies Pvt. Ltd.
jdi Japan Display Inc.
jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
@@ -165,6 +170,7 @@ keithkoep Keith & Koep GmbH
keymile Keymile GmbH
khadas Khadas
kinetic Kinetic Technologies
+kingnovel Kingnovel Technology Co., Ltd.
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
@@ -172,8 +178,10 @@ lantiq Lantiq Semiconductor
lego LEGO Systems A/S
lenovo Lenovo Group Ltd.
lg LG Corporation
+libretech Shenzhen Libre Technology Co., Ltd
licheepi Lichee Pi
linaro Linaro Limited
+linksys Belkin International, Inc. (Linksys)
linux Linux-specific binding
lltc Linear Technology Corporation
lsi LSI Corp. (LSI Logic)
@@ -219,6 +227,7 @@ nexbox Nexbox
newhaven Newhaven Display International
ni National Instruments
nintendo Nintendo
+nlt NLT Technologies, Ltd.
nokia Nokia
nordic Nordic Semiconductor
nuvoton Nuvoton Technology Corporation
@@ -266,8 +275,10 @@ renesas Renesas Electronics Corporation
richtek Richtek Technology Corporation
ricoh Ricoh Co. Ltd.
rikomagic Rikomagic Tech Corp. Ltd
+riscv RISC-V Foundation
rockchip Fuzhou Rockchip Electronics Co., Ltd
rohm ROHM Semiconductor Co., Ltd
+roofull Shenzhen Roofull Technology Co, Ltd
samsung Samsung Semiconductor
samtec Samtec/Softing company
sandisk Sandisk Corporation
@@ -331,6 +342,7 @@ tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
tyan Tyan Computer Corporation
+ucrobotics uCRobotics
udoo Udoo
uniwest United Western Technologies Corp (UniWest)
upisemi uPI Semiconductor Corp.
@@ -356,6 +368,7 @@ xlnx Xilinx
xunlong Shenzhen Xunlong Software CO.,Limited
zarlink Zarlink Semiconductor
zeitec ZEITEC Semiconductor Co., LTD.
+zidoo Shenzhen Zidoo Technology Co., Ltd.
zii Zodiac Inflight Innovations
zte ZTE Corp.
zyxel ZyXEL Communications Corp.
diff --git a/dts/Bindings/watchdog/da9062-wdt.txt b/dts/Bindings/watchdog/da9062-wdt.txt
new file mode 100644
index 0000000000..b935b526d2
--- /dev/null
+++ b/dts/Bindings/watchdog/da9062-wdt.txt
@@ -0,0 +1,23 @@
+* Dialog Semiconductor DA9062/61 Watchdog Timer
+
+Required properties:
+
+- compatible: should be one of the following valid compatible string lines:
+ "dlg,da9061-watchdog", "dlg,da9062-watchdog"
+ "dlg,da9062-watchdog"
+
+Example: DA9062
+
+ pmic0: da9062@58 {
+ watchdog {
+ compatible = "dlg,da9062-watchdog";
+ };
+ };
+
+Example: DA9061 using a fall-back compatible for the DA9062 watchdog driver
+
+ pmic0: da9061@58 {
+ watchdog {
+ compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
+ };
+ };
diff --git a/dts/Bindings/watchdog/dw_wdt.txt b/dts/Bindings/watchdog/dw_wdt.txt
index 08e16f684f..eb0914420c 100644
--- a/dts/Bindings/watchdog/dw_wdt.txt
+++ b/dts/Bindings/watchdog/dw_wdt.txt
@@ -10,6 +10,8 @@ Required Properties:
Optional Properties:
- interrupts : The interrupt used for the watchdog timeout warning.
+- resets : phandle pointing to the system reset controller with
+ line index for the watchdog.
Example:
@@ -18,4 +20,5 @@ Example:
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
+ resets = <&rst WDT0_RESET>;
};
diff --git a/dts/Bindings/watchdog/renesas-wdt.txt b/dts/Bindings/watchdog/renesas-wdt.txt
index da24e31334..9e306afbbd 100644
--- a/dts/Bindings/watchdog/renesas-wdt.txt
+++ b/dts/Bindings/watchdog/renesas-wdt.txt
@@ -2,10 +2,11 @@ Renesas Watchdog Timer (WDT) Controller
Required properties:
- compatible : Should be "renesas,<soctype>-wdt", and
- "renesas,rcar-gen3-wdt" as fallback.
+ "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback.
Examples with soctypes are:
- "renesas,r8a7795-wdt" (R-Car H3)
- "renesas,r8a7796-wdt" (R-Car M3-W)
+ - "renesas,r7s72100-wdt" (RZ/A1)
When compatible with the generic version, nodes must list the SoC-specific
version corresponding to the platform first, followed by the generic
@@ -17,6 +18,7 @@ Required properties:
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
- power-domains : the power domain the WDT belongs to
+- interrupts: Some WDTs have an interrupt when used in interval timer mode
Examples:
diff --git a/dts/Bindings/watchdog/st,stm32-iwdg.txt b/dts/Bindings/watchdog/st,stm32-iwdg.txt
new file mode 100644
index 0000000000..cc13b10a3f
--- /dev/null
+++ b/dts/Bindings/watchdog/st,stm32-iwdg.txt
@@ -0,0 +1,19 @@
+STM32 Independent WatchDoG (IWDG)
+---------------------------------
+
+Required properties:
+- compatible: "st,stm32-iwdg"
+- reg: physical base address and length of the registers set for the device
+- clocks: must contain a single entry describing the clock input
+
+Optional Properties:
+- timeout-sec: Watchdog timeout value in seconds.
+
+Example:
+
+iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ timeout-sec = <32>;
+};
diff --git a/dts/Bindings/watchdog/uniphier-wdt.txt b/dts/Bindings/watchdog/uniphier-wdt.txt
new file mode 100644
index 0000000000..bf6337546d
--- /dev/null
+++ b/dts/Bindings/watchdog/uniphier-wdt.txt
@@ -0,0 +1,20 @@
+UniPhier watchdog timer controller
+
+This UniPhier watchdog timer controller must be under sysctrl node.
+
+Required properties:
+- compatible: should be "socionext,uniphier-wdt"
+
+Example:
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld11-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ }
+
+ other nodes ...
+ };
diff --git a/dts/include/dt-bindings/clock/bcm-sr.h b/dts/include/dt-bindings/clock/bcm-sr.h
new file mode 100644
index 0000000000..cff6c6fe29
--- /dev/null
+++ b/dts/include/dt-bindings/clock/bcm-sr.h
@@ -0,0 +1,101 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_SR_H
+#define _CLOCK_BCM_SR_H
+
+/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
+#define BCM_SR_GENPLL0 0
+#define BCM_SR_GENPLL0_SATA_CLK 1
+#define BCM_SR_GENPLL0_SCR_CLK 2
+#define BCM_SR_GENPLL0_250M_CLK 3
+#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
+#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
+#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
+
+/* GENPLL 1 clock channel ID MHB PCIE NITRO */
+#define BCM_SR_GENPLL1 0
+#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
+#define BCM_SR_GENPLL1_MHB_APB_CLK 2
+
+/* GENPLL 2 clock channel ID NITRO MHB*/
+#define BCM_SR_GENPLL2 0
+#define BCM_SR_GENPLL2_NIC_CLK 1
+#define BCM_SR_GENPLL2_250_NITRO_CLK 2
+#define BCM_SR_GENPLL2_125_NITRO_CLK 3
+#define BCM_SR_GENPLL2_CHIMP_CLK 4
+
+/* GENPLL 3 HSLS clock channel ID */
+#define BCM_SR_GENPLL3 0
+#define BCM_SR_GENPLL3_HSLS_CLK 1
+#define BCM_SR_GENPLL3_SDIO_CLK 2
+
+/* GENPLL 4 SCR clock channel ID */
+#define BCM_SR_GENPLL4 0
+#define BCM_SR_GENPLL4_CCN_CLK 1
+
+/* GENPLL 5 FS4 clock channel ID */
+#define BCM_SR_GENPLL5 0
+#define BCM_SR_GENPLL5_FS_CLK 1
+#define BCM_SR_GENPLL5_SPU_CLK 2
+
+/* GENPLL 6 NITRO clock channel ID */
+#define BCM_SR_GENPLL6 0
+#define BCM_SR_GENPLL6_48_USB_CLK 1
+
+/* LCPLL0 clock channel ID */
+#define BCM_SR_LCPLL0 0
+#define BCM_SR_LCPLL0_SATA_REF_CLK 1
+#define BCM_SR_LCPLL0_USB_REF_CLK 2
+#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
+
+/* LCPLL1 clock channel ID */
+#define BCM_SR_LCPLL1 0
+#define BCM_SR_LCPLL1_WAN_CLK 1
+
+/* LCPLL PCIE clock channel ID */
+#define BCM_SR_LCPLL_PCIE 0
+#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL0 0
+#define BCM_SR_EMEMPLL0_EMEM_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL1 0
+#define BCM_SR_EMEMPLL1_EMEM_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL2 0
+#define BCM_SR_EMEMPLL2_EMEM_CLK 1
+
+#endif /* _CLOCK_BCM_SR_H */
diff --git a/dts/include/dt-bindings/clock/boston-clock.h b/dts/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 0000000000..a6f0098211
--- /dev/null
+++ b/dts/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
diff --git a/dts/include/dt-bindings/clock/cortina,gemini-clock.h b/dts/include/dt-bindings/clock/cortina,gemini-clock.h
new file mode 100644
index 0000000000..acf5cd550b
--- /dev/null
+++ b/dts/include/dt-bindings/clock/cortina,gemini-clock.h
@@ -0,0 +1,29 @@
+#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+
+/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */
+#define GEMINI_NUM_CLKS 20
+
+#define GEMINI_CLK_RTC 0
+#define GEMINI_CLK_AHB 1
+#define GEMINI_CLK_APB 2
+#define GEMINI_CLK_CPU 3
+#define GEMINI_CLK_PCI 4
+#define GEMINI_CLK_TVC 5
+#define GEMINI_CLK_UART 6
+#define GEMINI_CLK_GATES 7
+#define GEMINI_CLK_GATE_SECURITY 7
+#define GEMINI_CLK_GATE_GMAC0 8
+#define GEMINI_CLK_GATE_GMAC1 9
+#define GEMINI_CLK_GATE_SATA0 10
+#define GEMINI_CLK_GATE_SATA1 11
+#define GEMINI_CLK_GATE_USB0 12
+#define GEMINI_CLK_GATE_USB1 13
+#define GEMINI_CLK_GATE_IDE 14
+#define GEMINI_CLK_GATE_PCI 15
+#define GEMINI_CLK_GATE_DDR 16
+#define GEMINI_CLK_GATE_FLASH 17
+#define GEMINI_CLK_GATE_TVC 18
+#define GEMINI_CLK_GATE_BOOT 19
+
+#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */
diff --git a/dts/include/dt-bindings/clock/exynos5420.h b/dts/include/dt-bindings/clock/exynos5420.h
index 6fd21c2914..2740ae0424 100644
--- a/dts/include/dt-bindings/clock/exynos5420.h
+++ b/dts/include/dt-bindings/clock/exynos5420.h
@@ -217,6 +217,9 @@
#define CLK_MOUT_MCLK_CDREX 654
#define CLK_MOUT_BPLL 655
#define CLK_MOUT_MX_MSPLL_CCORE 656
+#define CLK_MOUT_EPLL 657
+#define CLK_MOUT_MAU_EPLL 658
+#define CLK_MOUT_USER_MAU_EPLL 659
/* divider clocks */
#define CLK_DOUT_PIXEL 768
diff --git a/dts/include/dt-bindings/clock/gxbb-clkc.h b/dts/include/dt-bindings/clock/gxbb-clkc.h
index 3190e30b93..e3e9f7919c 100644
--- a/dts/include/dt-bindings/clock/gxbb-clkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,7 +5,6 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
-#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
@@ -13,24 +12,30 @@
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
+#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
#define CLKID_RNG0 25
+#define CLKID_UART0 26
#define CLKID_SPI 34
#define CLKID_ETH 36
#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
#define CLKID_MIXER_IFACE 44
#define CLKID_AIU 47
+#define CLKID_UART1 48
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_UART2 68
#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
@@ -42,5 +47,8 @@
#define CLKID_MALI_1_SEL 103
#define CLKID_MALI_1 105
#define CLKID_MALI 106
+#define CLKID_CTS_AMCLK 107
+#define CLKID_CTS_MCLK_I958 110
+#define CLKID_CTS_I958 113
#endif /* __GXBB_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/hi3660-clock.h b/dts/include/dt-bindings/clock/hi3660-clock.h
index 1c00b7fe29..adb768d447 100644
--- a/dts/include/dt-bindings/clock/hi3660-clock.h
+++ b/dts/include/dt-bindings/clock/hi3660-clock.h
@@ -154,6 +154,23 @@
#define HI3660_CLK_DIV_UFSPERI 137
#define HI3660_CLK_DIV_AOMM 138
#define HI3660_CLK_DIV_IOPERI 139
+#define HI3660_VENC_VOLT_HOLD 140
+#define HI3660_PERI_VOLT_HOLD 141
+#define HI3660_CLK_GATE_VENC 142
+#define HI3660_CLK_GATE_VDEC 143
+#define HI3660_CLK_ANDGT_VENC 144
+#define HI3660_CLK_ANDGT_VDEC 145
+#define HI3660_CLK_MUX_VENC 146
+#define HI3660_CLK_MUX_VDEC 147
+#define HI3660_CLK_DIV_VENC 148
+#define HI3660_CLK_DIV_VDEC 149
+#define HI3660_CLK_FAC_ISP_SNCLK 150
+#define HI3660_CLK_GATE_ISP_SNCLK0 151
+#define HI3660_CLK_GATE_ISP_SNCLK1 152
+#define HI3660_CLK_GATE_ISP_SNCLK2 153
+#define HI3660_CLK_ANGT_ISP_SNCLK 154
+#define HI3660_CLK_MUX_ISP_SNCLK 155
+#define HI3660_CLK_DIV_ISP_SNCLK 156
/* clk in pmuctrl */
#define HI3660_GATE_ABB_192 0
diff --git a/dts/include/dt-bindings/clock/hi6220-clock.h b/dts/include/dt-bindings/clock/hi6220-clock.h
index b8ba665aab..409cc02cd8 100644
--- a/dts/include/dt-bindings/clock/hi6220-clock.h
+++ b/dts/include/dt-bindings/clock/hi6220-clock.h
@@ -174,4 +174,8 @@
#define HI6220_DDRC_AXI1 7
#define HI6220_POWER_NR_CLKS 8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S 0
+
#endif
diff --git a/dts/include/dt-bindings/clock/histb-clock.h b/dts/include/dt-bindings/clock/histb-clock.h
index 181c0f070f..067f5e501b 100644
--- a/dts/include/dt-bindings/clock/histb-clock.h
+++ b/dts/include/dt-bindings/clock/histb-clock.h
@@ -53,7 +53,14 @@
#define HISTB_ETH1_MAC_CLK 31
#define HISTB_ETH1_MACIF_CLK 32
#define HISTB_COMBPHY1_CLK 33
-
+#define HISTB_USB2_BUS_CLK 34
+#define HISTB_USB2_PHY_CLK 35
+#define HISTB_USB2_UTMI_CLK 36
+#define HISTB_USB2_12M_CLK 37
+#define HISTB_USB2_48M_CLK 38
+#define HISTB_USB2_OTG_UTMI_CLK 39
+#define HISTB_USB2_PHY1_REF_CLK 40
+#define HISTB_USB2_PHY2_REF_CLK 41
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
diff --git a/dts/include/dt-bindings/clock/imx7d-clock.h b/dts/include/dt-bindings/clock/imx7d-clock.h
index a7a1a50f33..de62a83b6c 100644
--- a/dts/include/dt-bindings/clock/imx7d-clock.h
+++ b/dts/include/dt-bindings/clock/imx7d-clock.h
@@ -450,5 +450,7 @@
#define IMX7D_CLK_ARM 437
#define IMX7D_CKIL 438
#define IMX7D_OCOTP_CLK 439
-#define IMX7D_CLK_END 440
+#define IMX7D_NAND_RAWNAND_CLK 440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_CLK_END 442
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index a55ff8c9b3..e29227fb52 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,5 +21,15 @@
#define CLKID_ZERO 13
#define CLKID_MPEG_SEL 14
#define CLKID_MPEG_DIV 15
+#define CLKID_SAR_ADC 23
+#define CLKID_RNG0 25
+#define CLKID_SDIO 30
+#define CLKID_ETH 36
+#define CLKID_USB0 50
+#define CLKID_USB1 51
+#define CLKID_USB 55
+#define CLKID_USB1_DDR_BRIDGE 64
+#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
#endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/mt2701-clk.h b/dts/include/dt-bindings/clock/mt2701-clk.h
index 2062c67e2e..551f7600ab 100644
--- a/dts/include/dt-bindings/clock/mt2701-clk.h
+++ b/dts/include/dt-bindings/clock/mt2701-clk.h
@@ -221,7 +221,8 @@
#define CLK_INFRA_PMICWRAP 17
#define CLK_INFRA_DDCCI 18
#define CLK_INFRA_CLK_13M 19
-#define CLK_INFRA_NR 20
+#define CLK_INFRA_CPUSEL 20
+#define CLK_INFRA_NR 21
/* PERICFG */
diff --git a/dts/include/dt-bindings/clock/mt8173-clk.h b/dts/include/dt-bindings/clock/mt8173-clk.h
index 6094bf7e50..8aea623dd5 100644
--- a/dts/include/dt-bindings/clock/mt8173-clk.h
+++ b/dts/include/dt-bindings/clock/mt8173-clk.h
@@ -193,7 +193,9 @@
#define CLK_INFRA_PMICSPI 10
#define CLK_INFRA_PMICWRAP 11
#define CLK_INFRA_CLK_13M 12
-#define CLK_INFRA_NR_CLK 13
+#define CLK_INFRA_CA53SEL 13
+#define CLK_INFRA_CA57SEL 14
+#define CLK_INFRA_NR_CLK 15
/* PERI_SYS */
diff --git a/dts/include/dt-bindings/clock/omap4.h b/dts/include/dt-bindings/clock/omap4.h
new file mode 100644
index 0000000000..e86c758e50
--- /dev/null
+++ b/dts/include/dt-bindings/clock/omap4.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET 0x20
+#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
+
+/* mpuss clocks */
+#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* tesla clocks */
+#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+
+/* l4_ao clocks */
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* l3_1 clocks */
+#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_2 clocks */
+#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* ducati clocks */
+#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_dma clocks */
+#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_emif clocks */
+#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+
+/* d2d clocks */
+#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l4_cfg clocks */
+#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+
+/* l3_instr clocks */
+#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+
+/* ivahd clocks */
+#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* iss clocks */
+#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+
+/* l3_dss clocks */
+#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_gfx clocks */
+#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_init clocks */
+#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+
+/* l4_per clocks */
+#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
+
+/* l4_wkup clocks */
+#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
+
+/* emu_sys clocks */
+#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h
new file mode 100644
index 0000000000..370c83c3bc
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+
+#define GPLL0 0
+#define GPLL0_MAIN 1
+#define GCC_SLEEP_CLK_SRC 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14
+#define BLSP1_UART1_APPS_CLK_SRC 15
+#define BLSP1_UART2_APPS_CLK_SRC 16
+#define BLSP1_UART3_APPS_CLK_SRC 17
+#define BLSP1_UART4_APPS_CLK_SRC 18
+#define BLSP1_UART5_APPS_CLK_SRC 19
+#define BLSP1_UART6_APPS_CLK_SRC 20
+#define GCC_BLSP1_AHB_CLK 21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33
+#define GCC_BLSP1_UART1_APPS_CLK 34
+#define GCC_BLSP1_UART2_APPS_CLK 35
+#define GCC_BLSP1_UART3_APPS_CLK 36
+#define GCC_BLSP1_UART4_APPS_CLK 37
+#define GCC_BLSP1_UART5_APPS_CLK 38
+#define GCC_BLSP1_UART6_APPS_CLK 39
+#define GCC_PRNG_AHB_CLK 40
+#define GCC_QPIC_AHB_CLK 41
+#define GCC_QPIC_CLK 42
+#define PCNOC_BFDCD_CLK_SRC 43
+
+#define GCC_BLSP1_BCR 0
+#define GCC_BLSP1_QUP1_BCR 1
+#define GCC_BLSP1_UART1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_UART2_BCR 4
+#define GCC_BLSP1_QUP3_BCR 5
+#define GCC_BLSP1_UART3_BCR 6
+#define GCC_BLSP1_QUP4_BCR 7
+#define GCC_BLSP1_UART4_BCR 8
+#define GCC_BLSP1_QUP5_BCR 9
+#define GCC_BLSP1_UART5_BCR 10
+#define GCC_BLSP1_QUP6_BCR 11
+#define GCC_BLSP1_UART6_BCR 12
+#define GCC_IMEM_BCR 13
+#define GCC_SMMU_BCR 14
+#define GCC_APSS_TCU_BCR 15
+#define GCC_SMMU_XPU_BCR 16
+#define GCC_PCNOC_TBU_BCR 17
+#define GCC_SMMU_CFG_BCR 18
+#define GCC_PRNG_BCR 19
+#define GCC_BOOT_ROM_BCR 20
+#define GCC_CRYPTO_BCR 21
+#define GCC_WCSS_BCR 22
+#define GCC_WCSS_Q6_BCR 23
+#define GCC_NSS_BCR 24
+#define GCC_SEC_CTRL_BCR 25
+#define GCC_ADSS_BCR 26
+#define GCC_DDRSS_BCR 27
+#define GCC_SYSTEM_NOC_BCR 28
+#define GCC_PCNOC_BCR 29
+#define GCC_TCSR_BCR 30
+#define GCC_QDSS_BCR 31
+#define GCC_DCD_BCR 32
+#define GCC_MSG_RAM_BCR 33
+#define GCC_MPM_BCR 34
+#define GCC_SPMI_BCR 35
+#define GCC_SPDM_BCR 36
+#define GCC_RBCPR_BCR 37
+#define GCC_RBCPR_MX_BCR 38
+#define GCC_TLMM_BCR 39
+#define GCC_RBCPR_WCSS_BCR 40
+#define GCC_USB0_PHY_BCR 41
+#define GCC_USB3PHY_0_PHY_BCR 42
+#define GCC_USB0_BCR 43
+#define GCC_USB1_PHY_BCR 44
+#define GCC_USB3PHY_1_PHY_BCR 45
+#define GCC_USB1_BCR 46
+#define GCC_QUSB2_0_PHY_BCR 47
+#define GCC_QUSB2_1_PHY_BCR 48
+#define GCC_SDCC1_BCR 49
+#define GCC_SDCC2_BCR 50
+#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
+#define GCC_SNOC_BUS_TIMEOUT2_BCR 52
+#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63
+#define GCC_UNIPHY0_BCR 64
+#define GCC_UNIPHY1_BCR 65
+#define GCC_UNIPHY2_BCR 66
+#define GCC_CMN_12GPLL_BCR 67
+#define GCC_QPIC_BCR 68
+#define GCC_MDIO_BCR 69
+#define GCC_PCIE1_TBU_BCR 70
+#define GCC_WCSS_CORE_TBU_BCR 71
+#define GCC_WCSS_Q6_TBU_BCR 72
+#define GCC_USB0_TBU_BCR 73
+#define GCC_USB1_TBU_BCR 74
+#define GCC_PCIE0_TBU_BCR 75
+#define GCC_NSS_NOC_TBU_BCR 76
+#define GCC_PCIE0_BCR 77
+#define GCC_PCIE0_PHY_BCR 78
+#define GCC_PCIE0PHY_PHY_BCR 79
+#define GCC_PCIE0_LINK_DOWN_BCR 80
+#define GCC_PCIE1_BCR 81
+#define GCC_PCIE1_PHY_BCR 82
+#define GCC_PCIE1PHY_PHY_BCR 83
+#define GCC_PCIE1_LINK_DOWN_BCR 84
+#define GCC_DCC_BCR 85
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
+#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
+#define GCC_SMMU_CATS_BCR 88
+
+#endif
diff --git a/dts/include/dt-bindings/clock/r7s72100-clock.h b/dts/include/dt-bindings/clock/r7s72100-clock.h
index bc256d3109..7dd8bc0c3c 100644
--- a/dts/include/dt-bindings/clock/r7s72100-clock.h
+++ b/dts/include/dt-bindings/clock/r7s72100-clock.h
@@ -12,8 +12,18 @@
#define R7S72100_CLK_PLL 0
+/* MSTP2 */
+#define R7S72100_CLK_CORESIGHT 0
+
/* MSTP3 */
+#define R7S72100_CLK_IEBUS 7
+#define R7S72100_CLK_IRDA 6
+#define R7S72100_CLK_LIN0 5
+#define R7S72100_CLK_LIN1 4
#define R7S72100_CLK_MTU2 3
+#define R7S72100_CLK_CAN 2
+#define R7S72100_CLK_ADCPWR 1
+#define R7S72100_CLK_PWM 0
/* MSTP4 */
#define R7S72100_CLK_SCIF0 7
@@ -26,23 +36,51 @@
#define R7S72100_CLK_SCIF7 0
/* MSTP5 */
+#define R7S72100_CLK_SCI0 7
+#define R7S72100_CLK_SCI1 6
+#define R7S72100_CLK_SG0 5
+#define R7S72100_CLK_SG1 4
+#define R7S72100_CLK_SG2 3
+#define R7S72100_CLK_SG3 2
#define R7S72100_CLK_OSTM0 1
#define R7S72100_CLK_OSTM1 0
/* MSTP6 */
+#define R7S72100_CLK_ADC 7
+#define R7S72100_CLK_CEU 6
+#define R7S72100_CLK_DOC0 5
+#define R7S72100_CLK_DOC1 4
+#define R7S72100_CLK_DRC0 3
+#define R7S72100_CLK_DRC1 2
+#define R7S72100_CLK_JCU 1
#define R7S72100_CLK_RTC 0
/* MSTP7 */
+#define R7S72100_CLK_VDEC0 7
+#define R7S72100_CLK_VDEC1 6
#define R7S72100_CLK_ETHER 4
+#define R7S72100_CLK_NAND 3
+#define R7S72100_CLK_USB0 1
+#define R7S72100_CLK_USB1 0
/* MSTP8 */
+#define R7S72100_CLK_IMR0 7
+#define R7S72100_CLK_IMR1 6
+#define R7S72100_CLK_IMRDISP 5
#define R7S72100_CLK_MMCIF 4
+#define R7S72100_CLK_MLB 3
+#define R7S72100_CLK_ETHAVB 2
+#define R7S72100_CLK_SCUX 1
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
#define R7S72100_CLK_I2C2 5
#define R7S72100_CLK_I2C3 4
+#define R7S72100_CLK_SPIBSC0 3
+#define R7S72100_CLK_SPIBSC1 2
+#define R7S72100_CLK_VDC50 1 /* and LVDS */
+#define R7S72100_CLK_VDC51 0
/* MSTP10 */
#define R7S72100_CLK_SPI0 7
@@ -50,6 +88,17 @@
#define R7S72100_CLK_SPI2 5
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
+#define R7S72100_CLK_CDROM 2
+#define R7S72100_CLK_SPDIF 1
+#define R7S72100_CLK_RGPVG2 0
+
+/* MSTP11 */
+#define R7S72100_CLK_SSI0 5
+#define R7S72100_CLK_SSI1 4
+#define R7S72100_CLK_SSI2 3
+#define R7S72100_CLK_SSI3 2
+#define R7S72100_CLK_SSI4 1
+#define R7S72100_CLK_SSI5 0
/* MSTP12 */
#define R7S72100_CLK_SDHI00 3
@@ -57,4 +106,8 @@
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
+/* MSTP13 */
+#define R7S72100_CLK_PIX1 2
+#define R7S72100_CLK_PIX0 1
+
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644
index 0000000000..1625b8bf34
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z 0
+#define R8A7790_CLK_Z2 1
+#define R8A7790_CLK_ZG 2
+#define R8A7790_CLK_ZTR 3
+#define R8A7790_CLK_ZTRD2 4
+#define R8A7790_CLK_ZT 5
+#define R8A7790_CLK_ZX 6
+#define R8A7790_CLK_ZS 7
+#define R8A7790_CLK_HP 8
+#define R8A7790_CLK_I 9
+#define R8A7790_CLK_B 10
+#define R8A7790_CLK_LB 11
+#define R8A7790_CLK_P 12
+#define R8A7790_CLK_CL 13
+#define R8A7790_CLK_M2 14
+#define R8A7790_CLK_ADSP 15
+#define R8A7790_CLK_IMP 16
+#define R8A7790_CLK_ZB3 17
+#define R8A7790_CLK_ZB3D2 18
+#define R8A7790_CLK_DDR 19
+#define R8A7790_CLK_SDH 20
+#define R8A7790_CLK_SD0 21
+#define R8A7790_CLK_SD1 22
+#define R8A7790_CLK_SD2 23
+#define R8A7790_CLK_SD3 24
+#define R8A7790_CLK_MMC0 25
+#define R8A7790_CLK_MMC1 26
+#define R8A7790_CLK_MP 27
+#define R8A7790_CLK_SSP 28
+#define R8A7790_CLK_SSPRS 29
+#define R8A7790_CLK_QSPI 30
+#define R8A7790_CLK_CP 31
+#define R8A7790_CLK_RCAN 32
+#define R8A7790_CLK_R 33
+#define R8A7790_CLK_OSC 34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7791-clock.h b/dts/include/dt-bindings/clock/r8a7791-clock.h
index adc50dc31a..ef69213414 100644
--- a/dts/include/dt-bindings/clock/r8a7791-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7791-clock.h
@@ -109,6 +109,7 @@
#define R8A7791_CLK_SATA0 15
/* MSTP9 */
+#define R8A7791_CLK_GYROADC 1
#define R8A7791_CLK_GPIO7 4
#define R8A7791_CLK_GPIO6 5
#define R8A7791_CLK_GPIO5 7
diff --git a/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h
new file mode 100644
index 0000000000..e8823410c0
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7791 CPG Core Clocks */
+#define R8A7791_CLK_Z 0
+#define R8A7791_CLK_ZG 1
+#define R8A7791_CLK_ZTR 2
+#define R8A7791_CLK_ZTRD2 3
+#define R8A7791_CLK_ZT 4
+#define R8A7791_CLK_ZX 5
+#define R8A7791_CLK_ZS 6
+#define R8A7791_CLK_HP 7
+#define R8A7791_CLK_I 8
+#define R8A7791_CLK_B 9
+#define R8A7791_CLK_LB 10
+#define R8A7791_CLK_P 11
+#define R8A7791_CLK_CL 12
+#define R8A7791_CLK_M2 13
+#define R8A7791_CLK_ADSP 14
+#define R8A7791_CLK_ZB3 15
+#define R8A7791_CLK_ZB3D2 16
+#define R8A7791_CLK_DDR 17
+#define R8A7791_CLK_SDH 18
+#define R8A7791_CLK_SD0 19
+#define R8A7791_CLK_SD2 20
+#define R8A7791_CLK_SD3 21
+#define R8A7791_CLK_MMC0 22
+#define R8A7791_CLK_MP 23
+#define R8A7791_CLK_SSP 24
+#define R8A7791_CLK_SSPRS 25
+#define R8A7791_CLK_QSPI 26
+#define R8A7791_CLK_CP 27
+#define R8A7791_CLK_RCAN 28
+#define R8A7791_CLK_R 29
+#define R8A7791_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h
new file mode 100644
index 0000000000..72ce85cb2f
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7792 CPG Core Clocks */
+#define R8A7792_CLK_Z 0
+#define R8A7792_CLK_ZG 1
+#define R8A7792_CLK_ZTR 2
+#define R8A7792_CLK_ZTRD2 3
+#define R8A7792_CLK_ZT 4
+#define R8A7792_CLK_ZX 5
+#define R8A7792_CLK_ZS 6
+#define R8A7792_CLK_HP 7
+#define R8A7792_CLK_I 8
+#define R8A7792_CLK_B 9
+#define R8A7792_CLK_LB 10
+#define R8A7792_CLK_P 11
+#define R8A7792_CLK_CL 12
+#define R8A7792_CLK_M2 13
+#define R8A7792_CLK_IMP 14
+#define R8A7792_CLK_ZB3 15
+#define R8A7792_CLK_ZB3D2 16
+#define R8A7792_CLK_DDR 17
+#define R8A7792_CLK_SD 18
+#define R8A7792_CLK_MP 19
+#define R8A7792_CLK_QSPI 20
+#define R8A7792_CLK_CP 21
+#define R8A7792_CLK_CPEX 22
+#define R8A7792_CLK_RCAN 23
+#define R8A7792_CLK_R 24
+#define R8A7792_CLK_OSC 25
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h
new file mode 100644
index 0000000000..8809b0f62d
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7793 CPG Core Clocks */
+#define R8A7793_CLK_Z 0
+#define R8A7793_CLK_ZG 1
+#define R8A7793_CLK_ZTR 2
+#define R8A7793_CLK_ZTRD2 3
+#define R8A7793_CLK_ZT 4
+#define R8A7793_CLK_ZX 5
+#define R8A7793_CLK_ZS 6
+#define R8A7793_CLK_HP 7
+#define R8A7793_CLK_I 8
+#define R8A7793_CLK_B 9
+#define R8A7793_CLK_LB 10
+#define R8A7793_CLK_P 11
+#define R8A7793_CLK_CL 12
+#define R8A7793_CLK_M2 13
+#define R8A7793_CLK_ADSP 14
+#define R8A7793_CLK_ZB3 15
+#define R8A7793_CLK_ZB3D2 16
+#define R8A7793_CLK_DDR 17
+#define R8A7793_CLK_SDH 18
+#define R8A7793_CLK_SD0 19
+#define R8A7793_CLK_SD2 20
+#define R8A7793_CLK_SD3 21
+#define R8A7793_CLK_MMC0 22
+#define R8A7793_CLK_MP 23
+#define R8A7793_CLK_SSP 24
+#define R8A7793_CLK_SSPRS 25
+#define R8A7793_CLK_QSPI 26
+#define R8A7793_CLK_CP 27
+#define R8A7793_CLK_RCAN 28
+#define R8A7793_CLK_R 29
+#define R8A7793_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h
new file mode 100644
index 0000000000..9d720311ae
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2 0
+#define R8A7794_CLK_ZG 1
+#define R8A7794_CLK_ZTR 2
+#define R8A7794_CLK_ZTRD2 3
+#define R8A7794_CLK_ZT 4
+#define R8A7794_CLK_ZX 5
+#define R8A7794_CLK_ZS 6
+#define R8A7794_CLK_HP 7
+#define R8A7794_CLK_I 8
+#define R8A7794_CLK_B 9
+#define R8A7794_CLK_LB 10
+#define R8A7794_CLK_P 11
+#define R8A7794_CLK_CL 12
+#define R8A7794_CLK_CP 13
+#define R8A7794_CLK_M2 14
+#define R8A7794_CLK_ADSP 15
+#define R8A7794_CLK_ZB3 16
+#define R8A7794_CLK_ZB3D2 17
+#define R8A7794_CLK_DDR 18
+#define R8A7794_CLK_SDH 19
+#define R8A7794_CLK_SD0 20
+#define R8A7794_CLK_SD2 21
+#define R8A7794_CLK_SD3 22
+#define R8A7794_CLK_MMC0 23
+#define R8A7794_CLK_MP 24
+#define R8A7794_CLK_QSPI 25
+#define R8A7794_CLK_CPEX 26
+#define R8A7794_CLK_RCAN 27
+#define R8A7794_CLK_R 28
+#define R8A7794_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/rk3128-cru.h b/dts/include/dt-bindings/clock/rk3128-cru.h
new file mode 100644
index 0000000000..92894f4306
--- /dev/null
+++ b/dts/include/dt-bindings/clock/rk3128-cru.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define ARMCLK 5
+#define PLL_GPLL_DIV2 6
+#define PLL_GPLL_DIV3 7
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0 65
+#define SCLK_NANDC 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S0 80
+#define SCLK_I2S1 81
+#define SCLK_SPDIF 83
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_TIMER4 89
+#define SCLK_TIMER5 90
+#define SCLK_SARADC 91
+#define SCLK_I2S_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_VOP 122
+#define SCLK_MAC_SRC 124
+#define SCLK_MAC 126
+#define SCLK_MAC_REFOUT 127
+#define SCLK_MAC_REF 128
+#define SCLK_MAC_RX 129
+#define SCLK_MAC_TX 130
+#define SCLK_HEVC_CORE 134
+#define SCLK_RGA 135
+#define SCLK_CRYPTO 138
+#define SCLK_TSP 139
+#define SCLK_OTGPHY0 142
+#define SCLK_OTGPHY1 143
+#define SCLK_DDRC 144
+#define SCLK_PVTM_FUNC 145
+#define SCLK_PVTM_CORE 146
+#define SCLK_PVTM_GPU 147
+#define SCLK_MIPI_24M 148
+#define SCLK_PVTM 149
+#define SCLK_CIF_SRC 150
+#define SCLK_CIF_OUT_SRC 151
+#define SCLK_CIF_OUT 152
+#define SCLK_SFC 153
+#define SCLK_USB480M 154
+
+/* dclk gates */
+#define DCLK_VOP 190
+#define DCLK_EBC 191
+
+/* aclk gates */
+#define ACLK_VIO0 192
+#define ACLK_VIO1 193
+#define ACLK_DMAC 194
+#define ACLK_CPU 195
+#define ACLK_VEPU 196
+#define ACLK_VDPU 197
+#define ACLK_CIF 198
+#define ACLK_IEP 199
+#define ACLK_LCDC0 204
+#define ACLK_RGA 205
+#define ACLK_PERI 210
+#define ACLK_VOP 211
+#define ACLK_GMAC 212
+#define ACLK_GPU 213
+
+/* pclk gates */
+#define PCLK_SARADC 318
+#define PCLK_WDT 319
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_VIO_H2P 324
+#define PCLK_MIPI 325
+#define PCLK_EFUSE 326
+#define PCLK_HDMI 327
+#define PCLK_ACODEC 328
+#define PCLK_GRF 329
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_SPI0 338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_TSADC 344
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_CPU 354
+#define PCLK_PERI 363
+#define PCLK_GMAC 367
+#define PCLK_PMU_PRE 368
+#define PCLK_SIM_CARD 369
+
+/* hclk gates */
+#define HCLK_SPDIF 440
+#define HCLK_GPS 441
+#define HCLK_USBHOST 442
+#define HCLK_I2S_8CH 443
+#define HCLK_I2S_2CH 444
+#define HCLK_VOP 452
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_CPU 460
+#define HCLK_VEPU 461
+#define HCLK_VDPU 462
+#define HCLK_LCDC0 463
+#define HCLK_EBC 465
+#define HCLK_VIO 466
+#define HCLK_RGA 467
+#define HCLK_IEP 468
+#define HCLK_VIO_H2P 469
+#define HCLK_CIF 470
+#define HCLK_HOST2 473
+#define HCLK_OTG 474
+#define HCLK_TSP 475
+#define HCLK_CRYPTO 476
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_TOPDBG 12
+#define SRST_ACLK_CORE 13
+#define SRST_STRC_SYS_A 14
+#define SRST_L2C 15
+
+#define SRST_CPUSYS_H 18
+#define SRST_AHB2APBSYS_H 19
+#define SRST_SPDIF 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_PERI_NIU 23
+#define SRST_I2S_2CH 24
+#define SRST_I2S_8CH 25
+#define SRST_GPU_PVTM 26
+#define SRST_FUNC_PVTM 27
+#define SRST_CORE_PVTM 29
+#define SRST_EFUSE_P 30
+#define SRST_ACODEC_P 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+#define SRST_MIPIPHY_P 36
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_I2C3 46
+#define SRST_SFC 47
+
+#define SRST_PWM 48
+#define SRST_DAP_PO 50
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_CRYPTO 53
+#define SRST_GRF 55
+#define SRST_GMAC 56
+#define SRST_PERIPH_SYS_A 57
+#define SRST_PERIPH_SYS_H 58
+#define SRST_PERIPH_SYS_P 59
+#define SRST_SMART_CARD 60
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA 64
+#define SRST_GPS 67
+#define SRST_NANDC 68
+#define SRST_USBOTG0 69
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_OTGC1 74
+#define SRST_DDRMSCH 79
+
+#define SRST_SDMMC 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI 84
+#define SRST_WDT 86
+#define SRST_SARADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_P 89
+#define SRST_DDRCTRL 90
+#define SRST_DDRCTRL_P 91
+#define SRST_TSP 92
+#define SRST_TSP_CLKIN 93
+#define SRST_HOST0_ECHI 94
+
+#define SRST_HDMI_P 96
+#define SRST_VIO_ARBI_H 97
+#define SRST_VIO0_A 98
+#define SRST_VIO_BUS_H 99
+#define SRST_VOP_A 100
+#define SRST_VOP_H 101
+#define SRST_VOP_D 102
+#define SRST_UTMI0 103
+#define SRST_UTMI1 104
+#define SRST_USBPOR 105
+#define SRST_IEP_A 106
+#define SRST_IEP_H 107
+#define SRST_RGA_A 108
+#define SRST_RGA_H 109
+#define SRST_CIF0 110
+#define SRST_PMU 111
+
+#define SRST_VCODEC_A 112
+#define SRST_VCODEC_H 113
+#define SRST_VIO1_A 114
+#define SRST_HEVC_CORE 115
+#define SRST_VCODEC_NIU_A 116
+#define SRST_PMU_NIU_P 117
+#define SRST_LCDC0_S 119
+#define SRST_GPU 120
+#define SRST_GPU_NIU_A 122
+#define SRST_EBC_A 123
+#define SRST_EBC_H 124
+
+#define SRST_CORE_DBG 128
+#define SRST_DBG_P 129
+#define SRST_TIMER0 130
+#define SRST_TIMER1 131
+#define SRST_TIMER2 132
+#define SRST_TIMER3 133
+#define SRST_TIMER4 134
+#define SRST_TIMER5 135
+#define SRST_VIO_H2P 136
+#define SRST_VIO_MIPI_DSI 137
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3228-cru.h b/dts/include/dt-bindings/clock/rk3228-cru.h
index b27e2b1a65..56f841c228 100644
--- a/dts/include/dt-bindings/clock/rk3228-cru.h
+++ b/dts/include/dt-bindings/clock/rk3228-cru.h
@@ -61,6 +61,17 @@
#define SCLK_MAC_TX 130
#define SCLK_MAC_PHY 131
#define SCLK_MAC_OUT 132
+#define SCLK_VDEC_CABAC 133
+#define SCLK_VDEC_CORE 134
+#define SCLK_RGA 135
+#define SCLK_HDCP 136
+#define SCLK_HDMI_CEC 137
+#define SCLK_CRYPTO 138
+#define SCLK_TSP 139
+#define SCLK_HSADC 140
+#define SCLK_WIFI 141
+#define SCLK_OTGPHY0 142
+#define SCLK_OTGPHY1 143
/* dclk gates */
#define DCLK_VOP 190
@@ -68,15 +79,32 @@
/* aclk gates */
#define ACLK_DMAC 194
+#define ACLK_CPU 195
+#define ACLK_VPU_PRE 196
+#define ACLK_RKVDEC_PRE 197
+#define ACLK_RGA_PRE 198
+#define ACLK_IEP_PRE 199
+#define ACLK_HDCP_PRE 200
+#define ACLK_VOP_PRE 201
+#define ACLK_VPU 202
+#define ACLK_RKVDEC 203
+#define ACLK_IEP 204
+#define ACLK_RGA 205
+#define ACLK_HDCP 206
#define ACLK_PERI 210
#define ACLK_VOP 211
#define ACLK_GMAC 212
+#define ACLK_GPU 213
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
+#define PCLK_VIO_H2P 324
+#define PCLK_HDCP 325
+#define PCLK_EFUSE_1024 326
+#define PCLK_EFUSE_256 327
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
@@ -89,6 +117,7 @@
#define PCLK_TSADC 344
#define PCLK_PWM 350
#define PCLK_TIMER 353
+#define PCLK_CPU 354
#define PCLK_PERI 363
#define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365
@@ -104,6 +133,24 @@
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_CPU 460
+#define HCLK_VPU_PRE 461
+#define HCLK_RKVDEC_PRE 462
+#define HCLK_VIO_PRE 463
+#define HCLK_VPU 464
+#define HCLK_RKVDEC 465
+#define HCLK_VIO 466
+#define HCLK_RGA 467
+#define HCLK_IEP 468
+#define HCLK_VIO_H2P 469
+#define HCLK_HDCP_MMU 470
+#define HCLK_HOST0 471
+#define HCLK_HOST1 472
+#define HCLK_HOST2 473
+#define HCLK_OTG 474
+#define HCLK_TSP 475
+#define HCLK_M_CRYPTO 476
+#define HCLK_S_CRYPTO 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
diff --git a/dts/include/dt-bindings/clock/rk3399-cru.h b/dts/include/dt-bindings/clock/rk3399-cru.h
index 220a60f20d..22cb1dfa90 100644
--- a/dts/include/dt-bindings/clock/rk3399-cru.h
+++ b/dts/include/dt-bindings/clock/rk3399-cru.h
@@ -132,6 +132,8 @@
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
#define SCLK_DDRC 168
+#define SCLK_TESTCLKOUT1 169
+#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180
#define DCLK_VOP1 181
diff --git a/dts/include/dt-bindings/clock/sun5i-ccu.h b/dts/include/dt-bindings/clock/sun5i-ccu.h
index aeb2e2f781..81f34d477a 100644
--- a/dts/include/dt-bindings/clock/sun5i-ccu.h
+++ b/dts/include/dt-bindings/clock/sun5i-ccu.h
@@ -19,6 +19,9 @@
#define CLK_HOSC 1
+#define CLK_PLL_VIDEO0_2X 9
+
+#define CLK_PLL_VIDEO1_2X 16
#define CLK_CPU 17
#define CLK_AHB_OTG 23
diff --git a/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h b/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h
new file mode 100644
index 0000000000..78af5085f6
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+
+#define CLK_PLL_PERIPH 6
+
+#define CLK_PLL_DE 9
+
+#define CLK_C0CPUX 11
+#define CLK_C1CPUX 12
+
+#define CLK_BUS_MIPI_DSI 19
+#define CLK_BUS_SS 20
+#define CLK_BUS_DMA 21
+#define CLK_BUS_MMC0 22
+#define CLK_BUS_MMC1 23
+#define CLK_BUS_MMC2 24
+#define CLK_BUS_NAND 25
+#define CLK_BUS_DRAM 26
+#define CLK_BUS_EMAC 27
+#define CLK_BUS_HSTIMER 28
+#define CLK_BUS_SPI0 29
+#define CLK_BUS_SPI1 30
+#define CLK_BUS_OTG 31
+#define CLK_BUS_EHCI0 32
+#define CLK_BUS_EHCI1 33
+#define CLK_BUS_OHCI0 34
+
+#define CLK_BUS_VE 35
+#define CLK_BUS_TCON0 36
+#define CLK_BUS_TCON1 37
+#define CLK_BUS_CSI 38
+#define CLK_BUS_HDMI 39
+#define CLK_BUS_DE 40
+#define CLK_BUS_GPU 41
+#define CLK_BUS_MSGBOX 42
+#define CLK_BUS_SPINLOCK 43
+
+#define CLK_BUS_SPDIF 44
+#define CLK_BUS_PIO 45
+#define CLK_BUS_I2S0 46
+#define CLK_BUS_I2S1 47
+#define CLK_BUS_I2S2 48
+#define CLK_BUS_TDM 49
+
+#define CLK_BUS_I2C0 50
+#define CLK_BUS_I2C1 51
+#define CLK_BUS_I2C2 52
+#define CLK_BUS_UART0 53
+#define CLK_BUS_UART1 54
+#define CLK_BUS_UART2 55
+#define CLK_BUS_UART3 56
+#define CLK_BUS_UART4 57
+
+#define CLK_NAND 59
+#define CLK_MMC0 60
+#define CLK_MMC0_SAMPLE 61
+#define CLK_MMC0_OUTPUT 62
+#define CLK_MMC1 63
+#define CLK_MMC1_SAMPLE 64
+#define CLK_MMC1_OUTPUT 65
+#define CLK_MMC2 66
+#define CLK_MMC2_SAMPLE 67
+#define CLK_MMC2_OUTPUT 68
+#define CLK_SS 69
+#define CLK_SPI0 70
+#define CLK_SPI1 71
+#define CLK_I2S0 72
+#define CLK_I2S1 73
+#define CLK_I2S2 74
+#define CLK_TDM 75
+#define CLK_SPDIF 76
+#define CLK_USB_PHY0 77
+#define CLK_USB_PHY1 78
+#define CLK_USB_HSIC 79
+#define CLK_USB_HSIC_12M 80
+#define CLK_USB_OHCI0 81
+
+#define CLK_DRAM_VE 83
+#define CLK_DRAM_CSI 84
+
+#define CLK_TCON0 85
+#define CLK_TCON1 86
+#define CLK_CSI_MISC 87
+#define CLK_MIPI_CSI 88
+#define CLK_CSI_MCLK 89
+#define CLK_CSI_SCLK 90
+#define CLK_VE 91
+#define CLK_AVS 92
+#define CLK_HDMI 93
+#define CLK_HDMI_SLOW 94
+
+#define CLK_MIPI_DSI0 96
+#define CLK_MIPI_DSI1 97
+#define CLK_GPU_CORE 98
+#define CLK_GPU_MEMORY 99
+#define CLK_GPU_HYD 100
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
diff --git a/dts/include/dt-bindings/clock/sun8i-de2.h b/dts/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index 0000000000..3bed63b524
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0 0
+#define CLK_BUS_MIXER1 1
+#define CLK_BUS_WB 2
+
+#define CLK_MIXER0 6
+#define CLK_MIXER1 7
+#define CLK_WB 8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/dts/include/dt-bindings/clock/zx296718-clock.h b/dts/include/dt-bindings/clock/zx296718-clock.h
index 822d523850..092c9751a6 100644
--- a/dts/include/dt-bindings/clock/zx296718-clock.h
+++ b/dts/include/dt-bindings/clock/zx296718-clock.h
@@ -157,7 +157,11 @@
#define AUDIO_TDM_WCLK 17
#define AUDIO_TDM_PCLK 18
#define AUDIO_TS_PCLK 19
+#define I2S0_WCLK_MUX 20
+#define I2S1_WCLK_MUX 21
+#define I2S2_WCLK_MUX 22
+#define I2S3_WCLK_MUX 23
-#define AUDIO_NR_CLKS 20
+#define AUDIO_NR_CLKS 24
#endif
diff --git a/dts/include/dt-bindings/gpio/gpio.h b/dts/include/dt-bindings/gpio/gpio.h
index b4f54da694..c507458456 100644
--- a/dts/include/dt-bindings/gpio/gpio.h
+++ b/dts/include/dt-bindings/gpio/gpio.h
@@ -28,4 +28,8 @@
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+/* Bit 3 express GPIO suspend/resume persistence */
+#define GPIO_SLEEP_MAINTAIN_VALUE 0
+#define GPIO_SLEEP_MAY_LOOSE_VALUE 8
+
#endif
diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h
index f5a8d96e1e..179891074b 100644
--- a/dts/include/dt-bindings/input/linux-event-codes.h
+++ b/dts/include/dt-bindings/input/linux-event-codes.h
@@ -600,6 +600,7 @@
#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
+#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */
#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
diff --git a/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h b/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h
new file mode 100644
index 0000000000..8249558545
--- /dev/null
+++ b/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for the MVEBU ICU driver.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+
+/* interrupt specifier cell 0 */
+
+#define ICU_GRP_NSR 0x0
+#define ICU_GRP_SR 0x1
+#define ICU_GRP_SEI 0x4
+#define ICU_GRP_REI 0x5
+
+#endif
diff --git a/dts/include/dt-bindings/mux/mux.h b/dts/include/dt-bindings/mux/mux.h
new file mode 100644
index 0000000000..c8e855c4a6
--- /dev/null
+++ b/dts/include/dt-bindings/mux/mux.h
@@ -0,0 +1,16 @@
+/*
+ * This header provides constants for most Multiplexer bindings.
+ *
+ * Most Multiplexer bindings specify an idle state. In most cases, the
+ * the multiplexer can be left as is when idle, and in some cases it can
+ * disconnect the input/output and leave the multiplexer in a high
+ * impedance state.
+ */
+
+#ifndef _DT_BINDINGS_MUX_MUX_H
+#define _DT_BINDINGS_MUX_MUX_H
+
+#define MUX_IDLE_AS_IS (-1)
+#define MUX_IDLE_DISCONNECT (-2)
+
+#endif
diff --git a/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h b/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
new file mode 100644
index 0000000000..caa6c664b4
--- /dev/null
+++ b/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
@@ -0,0 +1,68 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+
+/* Alternate functions available in MUX controller */
+#define MODE_NITRO 0
+#define MODE_NAND 1
+#define MODE_PNOR 2
+#define MODE_GPIO 3
+
+/* Pad configuration attribute */
+#define PAD_SLEW_RATE_ENA (1 << 0)
+#define PAD_SLEW_RATE_ENA_MASK (1 << 0)
+
+#define PAD_DRIVE_STRENGTH_2_MA (0 << 1)
+#define PAD_DRIVE_STRENGTH_4_MA (1 << 1)
+#define PAD_DRIVE_STRENGTH_6_MA (2 << 1)
+#define PAD_DRIVE_STRENGTH_8_MA (3 << 1)
+#define PAD_DRIVE_STRENGTH_10_MA (4 << 1)
+#define PAD_DRIVE_STRENGTH_12_MA (5 << 1)
+#define PAD_DRIVE_STRENGTH_14_MA (6 << 1)
+#define PAD_DRIVE_STRENGTH_16_MA (7 << 1)
+#define PAD_DRIVE_STRENGTH_MASK (7 << 1)
+
+#define PAD_PULL_UP_ENA (1 << 4)
+#define PAD_PULL_UP_ENA_MASK (1 << 4)
+
+#define PAD_PULL_DOWN_ENA (1 << 5)
+#define PAD_PULL_DOWN_ENA_MASK (1 << 5)
+
+#define PAD_INPUT_PATH_DIS (1 << 6)
+#define PAD_INPUT_PATH_DIS_MASK (1 << 6)
+
+#define PAD_HYSTERESIS_ENA (1 << 7)
+#define PAD_HYSTERESIS_ENA_MASK (1 << 7)
+
+#endif
diff --git a/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
new file mode 100644
index 0000000000..6b609fe109
--- /dev/null
+++ b/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
@@ -0,0 +1,16 @@
+/*
+ * Defines macros and constants for Renesas RZ/A1 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+
+#define RZA1_PINS_PER_PORT 16
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16))
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
diff --git a/dts/include/dt-bindings/power/mt6797-power.h b/dts/include/dt-bindings/power/mt6797-power.h
new file mode 100644
index 0000000000..a60c1d81cf
--- /dev/null
+++ b/dts/include/dt-bindings/power/mt6797-power.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Mars.C <mars.cheng@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT6797_POWER_H
+#define _DT_BINDINGS_POWER_MT6797_POWER_H
+
+#define MT6797_POWER_DOMAIN_VDEC 0
+#define MT6797_POWER_DOMAIN_VENC 1
+#define MT6797_POWER_DOMAIN_ISP 2
+#define MT6797_POWER_DOMAIN_MM 3
+#define MT6797_POWER_DOMAIN_AUDIO 4
+#define MT6797_POWER_DOMAIN_MFG_ASYNC 5
+#define MT6797_POWER_DOMAIN_MFG 6
+#define MT6797_POWER_DOMAIN_MFG_CORE0 7
+#define MT6797_POWER_DOMAIN_MFG_CORE1 8
+#define MT6797_POWER_DOMAIN_MFG_CORE2 9
+#define MT6797_POWER_DOMAIN_MFG_CORE3 10
+#define MT6797_POWER_DOMAIN_MJC 11
+
+#endif /* _DT_BINDINGS_POWER_MT6797_POWER_H */
diff --git a/dts/include/dt-bindings/power/owl-s500-powergate.h b/dts/include/dt-bindings/power/owl-s500-powergate.h
new file mode 100644
index 0000000000..0a1c451865
--- /dev/null
+++ b/dts/include/dt-bindings/power/owl-s500-powergate.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+#ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
+#define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
+
+#define S500_PD_VDE 0
+#define S500_PD_VCE_SI 1
+#define S500_PD_USB2_1 2
+#define S500_PD_CPU2 3
+#define S500_PD_CPU3 4
+#define S500_PD_DMA 5
+#define S500_PD_DS 6
+#define S500_PD_USB3 7
+#define S500_PD_USB2_0 8
+
+#endif
diff --git a/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h b/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000000..7978c21e4f
--- /dev/null
+++ b/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Intel Corporation. All rights reserved
+ * Copyright (C) 2016 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define CPU2_RESET 2
+#define CPU3_RESET 3
+
+/* PER0MODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define EMAC2_RESET 34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+/* 38 is empty */
+#define SDMMC_RESET 39
+#define EMAC0_OCP_RESET 40
+#define EMAC1_OCP_RESET 41
+#define EMAC2_OCP_RESET 42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+/* 46 is empty */
+#define SDMMC_OCP_RESET 47
+#define DMA_RESET 48
+#define SPIM0_RESET 49
+#define SPIM1_RESET 50
+#define SPIS0_RESET 51
+#define SPIS1_RESET 52
+#define DMA_OCP_RESET 53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET 56
+#define DMAIF1_RESET 57
+#define DMAIF2_RESET 58
+#define DMAIF3_RESET 59
+#define DMAIF4_RESET 60
+#define DMAIF5_RESET 61
+#define DMAIF6_RESET 62
+#define DMAIF7_RESET 63
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET 64
+#define WATCHDOG1_RESET 65
+#define WATCHDOG2_RESET 66
+#define WATCHDOG3_RESET 67
+#define L4SYSTIMER0_RESET 68
+#define L4SYSTIMER1_RESET 69
+#define SPTIMER0_RESET 70
+#define SPTIMER1_RESET 71
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is empty */
+#define UART0_RESET 80
+#define UART1_RESET 81
+/* 82-87 is empty */
+#define GPIO0_RESET 88
+#define GPIO1_RESET 89
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2SOC_RESET 98
+#define F2SSDRAM0_RESET 99
+#define F2SSDRAM1_RESET 100
+#define F2SSDRAM2_RESET 101
+#define DDRSCH_RESET 102
+
+/* COLDMODRST */
+#define CPUPO0_RESET 160
+#define CPUPO1_RESET 161
+#define CPUPO2_RESET 162
+#define CPUPO3_RESET 163
+/* 164-167 is empty */
+#define L2_RESET 168
+
+/* DBGMODRST */
+#define DBG_RESET 224
+#define CSDAP_RESET 225
+
+/* TAPMODRST */
+#define TAP_RESET 256
+
+#endif
diff --git a/dts/include/dt-bindings/reset/cortina,gemini-reset.h b/dts/include/dt-bindings/reset/cortina,gemini-reset.h
new file mode 100644
index 0000000000..0b886aee65
--- /dev/null
+++ b/dts/include/dt-bindings/reset/cortina,gemini-reset.h
@@ -0,0 +1,36 @@
+#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H
+#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H
+
+#define GEMINI_RESET_DRAM 0
+#define GEMINI_RESET_FLASH 1
+#define GEMINI_RESET_IDE 2
+#define GEMINI_RESET_RAID 3
+#define GEMINI_RESET_SECURITY 4
+#define GEMINI_RESET_GMAC0 5
+#define GEMINI_RESET_GMAC1 6
+#define GEMINI_RESET_PCI 7
+#define GEMINI_RESET_USB0 8
+#define GEMINI_RESET_USB1 9
+#define GEMINI_RESET_DMAC 10
+#define GEMINI_RESET_APB 11
+#define GEMINI_RESET_LPC 12
+#define GEMINI_RESET_LCD 13
+#define GEMINI_RESET_INTCON0 14
+#define GEMINI_RESET_INTCON1 15
+#define GEMINI_RESET_RTC 16
+#define GEMINI_RESET_TIMER 17
+#define GEMINI_RESET_UART 18
+#define GEMINI_RESET_SSP 19
+#define GEMINI_RESET_GPIO0 20
+#define GEMINI_RESET_GPIO1 21
+#define GEMINI_RESET_GPIO2 22
+#define GEMINI_RESET_WDOG 23
+#define GEMINI_RESET_EXTERN 24
+#define GEMINI_RESET_CIR 25
+#define GEMINI_RESET_SATA0 26
+#define GEMINI_RESET_SATA1 27
+#define GEMINI_RESET_TVC 28
+#define GEMINI_RESET_CPU1 30
+#define GEMINI_RESET_GLOBAL 31
+
+#endif
diff --git a/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h b/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h
new file mode 100644
index 0000000000..784f6e1166
--- /dev/null
+++ b/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_HSIC 2
+
+#define RST_DRAM 3
+#define RST_MBUS 4
+
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_SS 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_NAND 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_EMAC 13
+#define RST_BUS_HSTIMER 14
+#define RST_BUS_SPI0 15
+#define RST_BUS_SPI1 16
+#define RST_BUS_OTG 17
+#define RST_BUS_EHCI0 18
+#define RST_BUS_EHCI1 19
+#define RST_BUS_OHCI0 20
+
+#define RST_BUS_VE 21
+#define RST_BUS_TCON0 22
+#define RST_BUS_TCON1 23
+#define RST_BUS_CSI 24
+#define RST_BUS_HDMI0 25
+#define RST_BUS_HDMI1 26
+#define RST_BUS_DE 27
+#define RST_BUS_GPU 28
+#define RST_BUS_MSGBOX 29
+#define RST_BUS_SPINLOCK 30
+
+#define RST_BUS_LVDS 31
+
+#define RST_BUS_SPDIF 32
+#define RST_BUS_I2S0 33
+#define RST_BUS_I2S1 34
+#define RST_BUS_I2S2 35
+#define RST_BUS_TDM 36
+
+#define RST_BUS_I2C0 37
+#define RST_BUS_I2C1 38
+#define RST_BUS_I2C2 39
+#define RST_BUS_UART0 40
+#define RST_BUS_UART1 41
+#define RST_BUS_UART2 42
+#define RST_BUS_UART3 43
+#define RST_BUS_UART4 44
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */
diff --git a/dts/include/dt-bindings/reset/sun8i-de2.h b/dts/include/dt-bindings/reset/sun8i-de2.h
new file mode 100644
index 0000000000..9526017432
--- /dev/null
+++ b/dts/include/dt-bindings/reset/sun8i-de2.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
+#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
+
+#define RST_MIXER0 0
+#define RST_MIXER1 1
+#define RST_WB 2
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
diff --git a/dts/src/arm/aks-cdu.dts b/dts/src/arm/aks-cdu.dts
index 5b1bf92d92..888bfcd4a4 100644
--- a/dts/src/arm/aks-cdu.dts
+++ b/dts/src/arm/aks-cdu.dts
@@ -62,32 +62,36 @@
status = "okay";
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- status = "okay";
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x40000>;
- };
-
- uboot@40000 {
- label = "uboot";
- reg = <0x40000 0x80000>;
- };
- ubootenv@c0000 {
- label = "ubootenv";
- reg = <0xc0000 0x40000>;
- };
- kernel@100000 {
- label = "kernel";
- reg = <0x100000 0x400000>;
- };
- rootfs@500000 {
- label = "rootfs";
- reg = <0x500000 0x7b00000>;
+ ebi: ebi@10000000 {
+ nand_controller: nand-controller {
+ nand: nand@3 {
+ partitions {
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "uboot";
+ reg = <0x40000 0x80000>;
+ };
+
+ ubootenv@c0000 {
+ label = "ubootenv";
+ reg = <0xc0000 0x40000>;
+ };
+
+ kernel@100000 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ rootfs@500000 {
+ label = "rootfs";
+ reg = <0x500000 0x7b00000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi
index d42b98f15e..ec6052c521 100644
--- a/dts/src/arm/am335x-baltos.dtsi
+++ b/dts/src/arm/am335x-baltos.dtsi
@@ -255,7 +255,7 @@
};
at24@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
pagesize = <8>;
reg = <0x50>;
};
diff --git a/dts/src/arm/am335x-base0033.dts b/dts/src/arm/am335x-base0033.dts
index c2bee452da..29782be076 100644
--- a/dts/src/arm/am335x-base0033.dts
+++ b/dts/src/arm/am335x-base0033.dts
@@ -89,7 +89,7 @@
&i2c0 {
eeprom: eeprom@50 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
};
diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi
index bf6b26abe3..1d154444df 100644
--- a/dts/src/arm/am335x-bone-common.dtsi
+++ b/dts/src/arm/am335x-bone-common.dtsi
@@ -232,7 +232,7 @@
};
baseboard_eeprom: baseboard_eeprom@50 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
#address-cells = <1>;
@@ -251,7 +251,7 @@
clock-frequency = <100000>;
cape_eeprom0: cape_eeprom0@54 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x54>;
#address-cells = <1>;
#size-cells = <1>;
@@ -261,7 +261,7 @@
};
cape_eeprom1: cape_eeprom1@55 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x55>;
#address-cells = <1>;
#size-cells = <1>;
@@ -271,7 +271,7 @@
};
cape_eeprom2: cape_eeprom2@56 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x56>;
#address-cells = <1>;
#size-cells = <1>;
@@ -281,7 +281,7 @@
};
cape_eeprom3: cape_eeprom3@57 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x57>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/am335x-boneblack-wireless.dts b/dts/src/arm/am335x-boneblack-wireless.dts
index 105bd10655..83f49f616b 100644
--- a/dts/src/arm/am335x-boneblack-wireless.dts
+++ b/dts/src/arm/am335x-boneblack-wireless.dts
@@ -97,6 +97,11 @@
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins &bt_pins>;
status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
};
&gpio3 {
diff --git a/dts/src/arm/am335x-boneblack.dts b/dts/src/arm/am335x-boneblack.dts
index 935ed17d22..d154d3133c 100644
--- a/dts/src/arm/am335x-boneblack.dts
+++ b/dts/src/arm/am335x-boneblack.dts
@@ -22,7 +22,7 @@
* BeagleBone Blacks have PG 2.0 silicon which is guaranteed
* to support 1GHz OPP so enable it for PG 2.0 on this board.
*/
- oppnitro@1000000000 {
+ oppnitro-1000000000 {
opp-supported-hw = <0x06 0x0100>;
};
};
diff --git a/dts/src/arm/am335x-boneblue.dts b/dts/src/arm/am335x-boneblue.dts
new file mode 100644
index 0000000000..cdc1b2be79
--- /dev/null
+++ b/dts/src/arm/am335x-boneblue.dts
@@ -0,0 +1,460 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "TI AM335x BeagleBone Blue";
+ compatible = "ti,am335x-bone-blue", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ usr_0_led {
+ label = "beaglebone:green:usr0";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ usr_1_led {
+ label = "beaglebone:green:usr1";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ usr_2_led {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ usr_3_led {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ wifi_led {
+ label = "wifi";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "phy0assoc";
+ };
+
+ red_led {
+ label = "red";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ green_led {
+ label = "green";
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ batt_1_led {
+ label = "bat25";
+ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ batt_2_led {
+ label = "bat50";
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ batt_3_led {
+ label = "bat75";
+ gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ batt_4_led {
+ label = "bat100";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ vmmcsd_fixed: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ wlan_en_reg: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us= <70000>;
+
+ /* WL_EN */
+ gpio = <&gpio3 9 0>;
+ enable-active-high;
+ };
+};
+
+&am33xx_pinmux {
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+ AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+ AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+ AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+ AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */
+ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */
+ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */
+ AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */
+ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */
+ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */
+
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */
+ AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */
+ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */
+ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */
+ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */
+ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */
+ >;
+ };
+
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */
+ AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */
+ AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */
+ AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */
+ AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */
+ AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */
+ >;
+ };
+
+ bt_pins: pinmux_bt_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+ AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+ AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */
+ >;
+ };
+
+ wl18xx_pins: pinmux_wl18xx_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */
+ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ interrupts-extended = <&intc 18 &tps 0>;
+ interrupt-names = "mc", "vbus";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ baseboard_eeprom: baseboard_eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ baseboard_data: baseboard_data@0 {
+ reg = <0 0x100>;
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ mpu9250@68 {
+ compatible = "invensense,mpu9250";
+ reg = <0x68>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <21 GPIO_ACTIVE_LOW>;
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ax8975@c {
+ compatible = "ak,ak8975";
+ reg = <0x0c>;
+ };
+ };
+ };
+
+ pressure@76 {
+ compatible = "bosch,bmp280";
+ reg = <0x76>;
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ interrupts = <7>; /* NMI */
+ interrupt-parent = <&intc>;
+
+ charger {
+ interrupts = <0>, <1>;
+ interrupt-names = "USB", "AC";
+ status = "okay";
+ };
+
+ pwrbutton {
+ interrupts = <2>;
+ status = "okay";
+ };
+
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-name = "vdds_dpr";
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1351500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-name = "vio,vrtc,vdds";
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-name = "vdd_3v3aux";
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-name = "vdd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-name = "vdd_3v3a";
+ regulator-always-on;
+ };
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+};
+
+&mmc3 {
+ dmas = <&edma_xbar 12 0 1
+ &edma_xbar 13 0 2>;
+ dma-names = "tx", "rx";
+ status = "okay";
+ vmmc-supply = <&wlan_en_reg>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ ti,needs-special-hs-handling;
+ keep-power-in-suspend;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1835";
+ reg = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&tscadc {
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins &bt_pins>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&aes {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
+
+&rtc {
+ system-power-controller;
+ clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clock-names = "ext-clk", "int-clk";
+};
+
+&gpio3 {
+ ls_buf_en {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LS_BUF_EN";
+ };
+};
diff --git a/dts/src/arm/am335x-bonegreen-wireless.dts b/dts/src/arm/am335x-bonegreen-wireless.dts
index 9d1a0fd555..57731f0daf 100644
--- a/dts/src/arm/am335x-bonegreen-wireless.dts
+++ b/dts/src/arm/am335x-bonegreen-wireless.dts
@@ -97,6 +97,11 @@
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins &bt_pins>;
status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ };
};
&gpio1 {
diff --git a/dts/src/arm/am335x-nano.dts b/dts/src/arm/am335x-nano.dts
index 807494bc72..946d7069f4 100644
--- a/dts/src/arm/am335x-nano.dts
+++ b/dts/src/arm/am335x-nano.dts
@@ -224,7 +224,7 @@
};
eeprom@53 {
- compatible = "microchip,24c02";
+ compatible = "microchip,24c02", "atmel,24c02";
reg = <0x53>;
pagesize = <8>;
};
diff --git a/dts/src/arm/am335x-pepper.dts b/dts/src/arm/am335x-pepper.dts
index 30e2f8770a..03c7d77023 100644
--- a/dts/src/arm/am335x-pepper.dts
+++ b/dts/src/arm/am335x-pepper.dts
@@ -67,7 +67,7 @@
};
eeprom: eeprom@50 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/arm/am335x-phycore-som.dtsi b/dts/src/arm/am335x-phycore-som.dtsi
index 14533ff6d0..428a25e952 100644
--- a/dts/src/arm/am335x-phycore-som.dtsi
+++ b/dts/src/arm/am335x-phycore-som.dtsi
@@ -138,7 +138,7 @@
};
i2c_rtc: rtc@68 {
- compatible = "rv4162";
+ compatible = "microcrystal,rv4162";
reg = <0x68>;
status = "disabled";
};
diff --git a/dts/src/arm/am335x-shc.dts b/dts/src/arm/am335x-shc.dts
index bf8727a19e..4f6a286ea2 100644
--- a/dts/src/arm/am335x-shc.dts
+++ b/dts/src/arm/am335x-shc.dts
@@ -188,7 +188,7 @@
};
at24@50 {
- compatible = "at24,24c32";
+ compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
};
diff --git a/dts/src/arm/am335x-sl50.dts b/dts/src/arm/am335x-sl50.dts
index fc864a8559..1bcc60424e 100644
--- a/dts/src/arm/am335x-sl50.dts
+++ b/dts/src/arm/am335x-sl50.dts
@@ -305,7 +305,7 @@
};
eeprom: eeprom@50 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index 9e242943dc..7d7ca054c5 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -64,64 +64,64 @@
* because the can not be enabled simultaneously on a
* single SoC.
*/
- opp50@300000000 {
+ opp50-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0x06 0x0010>;
opp-suspend;
};
- opp100@275000000 {
+ opp100-275000000 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0x00FF>;
opp-suspend;
};
- opp100@300000000 {
+ opp100-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0020>;
opp-suspend;
};
- opp100@500000000 {
+ opp100-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0xFFFF>;
};
- opp100@600000000 {
+ opp100-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0040>;
};
- opp120@600000000 {
+ opp120-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x01 0xFFFF>;
};
- opp120@720000000 {
+ opp120-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x06 0x0080>;
};
- oppturbo@720000000 {
+ oppturbo-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x01 0xFFFF>;
};
- oppturbo@800000000 {
+ oppturbo-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x06 0x0100>;
};
- oppnitro@1000000000 {
+ oppnitro-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0x04 0x0200>;
@@ -431,7 +431,6 @@
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
interrupts = <64>;
- interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
@@ -444,7 +443,6 @@
&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <28>;
- interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
@@ -454,7 +452,6 @@
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
- interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
@@ -853,7 +850,6 @@
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
@@ -908,7 +904,6 @@
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
@@ -917,7 +912,6 @@
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi
index 176e09e9a4..e5b061469b 100644
--- a/dts/src/arm/am4372.dtsi
+++ b/dts/src/arm/am4372.dtsi
@@ -59,32 +59,32 @@
compatible = "operating-points-v2-ti-cpu";
syscon = <&scm_conf>;
- opp50@300000000 {
+ opp50-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
- opp100@600000000 {
+ opp100-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0xFF 0x04>;
};
- opp120@720000000 {
+ opp120-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0xFF 0x08>;
};
- oppturbo@800000000 {
+ oppturbo-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0xFF 0x10>;
};
- oppnitro@1000000000 {
+ oppnitro-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0xFF 0x20>;
diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts
index 397e98b7e2..29a538ecd4 100644
--- a/dts/src/arm/am437x-gp-evm.dts
+++ b/dts/src/arm/am437x-gp-evm.dts
@@ -549,8 +549,6 @@
dcdc3: regulator-dcdc3 {
regulator-name = "vdcdc3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts
index c1f7f9336e..5e36447306 100644
--- a/dts/src/arm/am437x-idk-evm.dts
+++ b/dts/src/arm/am437x-idk-evm.dts
@@ -339,7 +339,7 @@
clock-frequency = <400000>;
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
pagesize = <64>;
reg = <0x50>;
};
diff --git a/dts/src/arm/am437x-sk-evm.dts b/dts/src/arm/am437x-sk-evm.dts
index 4dc54bee2f..2c6bf0684f 100644
--- a/dts/src/arm/am437x-sk-evm.dts
+++ b/dts/src/arm/am437x-sk-evm.dts
@@ -451,8 +451,6 @@
dcdc3: regulator-dcdc3 {
regulator-name = "vdds_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
@@ -511,7 +509,7 @@
};
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
pagesize = <64>;
reg = <0x50>;
};
diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts
index 9acd4ccdec..54f40f3700 100644
--- a/dts/src/arm/am43x-epos-evm.dts
+++ b/dts/src/arm/am43x-epos-evm.dts
@@ -442,8 +442,6 @@
dcdc3: regulator-dcdc3 {
regulator-name = "vdcdc3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
@@ -477,7 +475,7 @@
};
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
pagesize = <64>;
reg = <0x50>;
};
diff --git a/dts/src/arm/am43xx-clocks.dtsi b/dts/src/arm/am43xx-clocks.dtsi
index d1d73b725f..430be5829f 100644
--- a/dts/src/arm/am43xx-clocks.dtsi
+++ b/dts/src/arm/am43xx-clocks.dtsi
@@ -833,4 +833,40 @@
ti,bit-shift = <23>;
reg = <0x4100>;
};
+
+ clkout2_src_mux_ck: clkout2_src_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+ <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+ <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
+ reg = <0x4108>;
+ };
+
+ clkout2_pre_div_ck: clkout2_pre_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_src_mux_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <8>;
+ reg = <0x4108>;
+ };
+
+ clkout2_post_div_ck: clkout2_post_div_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_pre_div_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <32>;
+ ti,index-power-of-two;
+ reg = <0x4108>;
+ };
+
+ clkout2_ck: clkout2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkout2_post_div_ck>;
+ ti,bit-shift = <16>;
+ reg = <0x4108>;
+ };
};
diff --git a/dts/src/arm/am571x-idk.dts b/dts/src/arm/am571x-idk.dts
index ad68d1eb3b..7b207835b2 100644
--- a/dts/src/arm/am571x-idk.dts
+++ b/dts/src/arm/am571x-idk.dts
@@ -79,3 +79,20 @@
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/dts/src/arm/am572x-idk.dts b/dts/src/arm/am572x-idk.dts
index 8350b4b34b..9da6d83ca1 100644
--- a/dts/src/arm/am572x-idk.dts
+++ b/dts/src/arm/am572x-idk.dts
@@ -91,3 +91,23 @@
&pcie1 {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/dts/src/arm/am57xx-beagle-x15-common.dtsi b/dts/src/arm/am57xx-beagle-x15-common.dtsi
index 585d792a8f..fdfe5b16b8 100644
--- a/dts/src/arm/am57xx-beagle-x15-common.dtsi
+++ b/dts/src/arm/am57xx-beagle-x15-common.dtsi
@@ -388,7 +388,7 @@
};
eeprom: eeprom@50 {
- compatible = "at,24c32";
+ compatible = "atmel,24c32";
reg = <0x50>;
};
};
diff --git a/dts/src/arm/animeo_ip.dts b/dts/src/arm/animeo_ip.dts
index 9cc372b9fb..26ade8c0a9 100644
--- a/dts/src/arm/animeo_ip.dts
+++ b/dts/src/arm/animeo_ip.dts
@@ -83,25 +83,44 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- barebox@0 {
- label = "barebox";
- reg = <0x0 0x58000>;
- };
-
- u_boot_env@58000 {
- label = "u_boot_env";
- reg = <0x58000 0x8000>;
- };
-
- ubi@60000 {
- label = "ubi";
- reg = <0x60000 0x1FA0000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ barebox@0 {
+ label = "barebox";
+ reg = <0x0 0x58000>;
+ };
+
+ u_boot_env@58000 {
+ label = "u_boot_env";
+ reg = <0x58000 0x8000>;
+ };
+
+ ubi@60000 {
+ label = "ubi";
+ reg = <0x60000 0x1FA0000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi
index cc011c8bc3..f9cf1273f3 100644
--- a/dts/src/arm/armada-370.dtsi
+++ b/dts/src/arm/armada-370.dtsi
@@ -137,29 +137,38 @@
};
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <2>;
gpio-controller;
diff --git a/dts/src/arm/armada-385-linksys-caiman.dts b/dts/src/arm/armada-385-linksys-caiman.dts
index f3cee918d2..ee669ae610 100644
--- a/dts/src/arm/armada-385-linksys-caiman.dts
+++ b/dts/src/arm/armada-385-linksys-caiman.dts
@@ -44,71 +44,128 @@
model = "Linksys WRT1200AC";
compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+};
+
+&expander0 {
+ wan_amber@0 {
+ label = "caiman:amber:wan";
+ reg = <0x0>;
+ };
+
+ wan_white@1 {
+ label = "caiman:white:wan";
+ reg = <0x1>;
+ };
+
+ wlan_2g@2 {
+ label = "caiman:white:wlan_2g";
+ reg = <0x2>;
+ };
+
+ wlan_5g@3 {
+ label = "caiman:white:wlan_5g";
+ reg = <0x3>;
+ };
+
+ usb2@5 {
+ label = "caiman:white:usb2";
+ reg = <0x5>;
+ };
+
+ usb3_1@6 {
+ label = "caiman:white:usb3_1";
+ reg = <0x6>;
+ };
+
+ usb3_2@7 {
+ label = "caiman:white:usb3_2";
+ reg = <0x7>;
+ };
+
+ wps_white@8 {
+ label = "caiman:white:wps";
+ reg = <0x8>;
+ };
+
+ wps_amber@9 {
+ label = "caiman:amber:wps";
+ reg = <0x9>;
+ };
+};
+
+&gpio_leds {
+ power {
+ label = "caiman:white:power";
+ };
+
+ sata {
+ label = "caiman:white:sata";
+ };
+};
+
+&nand {
+ /* 128MiB */
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x200000>; /* 2MiB */
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u_env";
+ reg = <0x200000 0x40000>; /* 256KiB */
+ };
+
+ partition@140000 {
+ label = "s_env";
+ reg = <0x240000 0x40000>; /* 256KiB */
+ };
+
+ partition@900000 {
+ label = "devinfo";
+ reg = <0x900000 0x100000>; /* 1MiB */
+ read-only;
+ };
+
+ /* kernel1 overlaps with rootfs1 by design */
+ partition@a00000 {
+ label = "kernel1";
+ reg = <0xa00000 0x2800000>; /* 40MiB */
+ };
+
+ partition@1000000 {
+ label = "rootfs1";
+ reg = <0x1000000 0x2200000>; /* 34MiB */
+ };
+
+ /* kernel2 overlaps with rootfs2 by design */
+ partition@3200000 {
+ label = "kernel2";
+ reg = <0x3200000 0x2800000>; /* 40MiB */
+ };
+
+ partition@3800000 {
+ label = "rootfs2";
+ reg = <0x3800000 0x2200000>; /* 34MiB */
+ };
+
+ /*
+ * 38MiB, last MiB is for the BBT, not writable
+ */
+ partition@5a00000 {
+ label = "syscfg";
+ reg = <0x5a00000 0x2600000>;
+ };
- soc {
- internal-regs{
- i2c@11000 {
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan_amber@0 {
- label = "caiman:amber:wan";
- reg = <0x0>;
- };
-
- wan_white@1 {
- label = "caiman:white:wan";
- reg = <0x1>;
- };
-
- wlan_2g@2 {
- label = "caiman:white:wlan_2g";
- reg = <0x2>;
- };
-
- wlan_5g@3 {
- label = "caiman:white:wlan_5g";
- reg = <0x3>;
- };
-
- usb2@5 {
- label = "caiman:white:usb2";
- reg = <0x5>;
- };
-
- usb3_1@6 {
- label = "caiman:white:usb3_1";
- reg = <0x6>;
- };
-
- usb3_2@7 {
- label = "caiman:white:usb3_2";
- reg = <0x7>;
- };
-
- wps_white@8 {
- label = "caiman:white:wps";
- reg = <0x8>;
- };
-
- wps_amber@9 {
- label = "caiman:amber:wps";
- reg = <0x9>;
- };
- };
- };
- };
- };
-
- gpio-leds {
- power {
- label = "caiman:white:power";
- };
-
- sata {
- label = "caiman:white:sata";
- };
+ /*
+ * Unused area between "s_env" and "devinfo".
+ * Moved here because otherwise the renumbered
+ * partitions would break the bootloader
+ * supplied bootargs
+ */
+ partition@180000 {
+ label = "unused_area";
+ reg = <0x280000 0x680000>; /* 6.5MiB */
};
};
diff --git a/dts/src/arm/armada-385-linksys-cobra.dts b/dts/src/arm/armada-385-linksys-cobra.dts
index 1110718605..5169ca89c5 100644
--- a/dts/src/arm/armada-385-linksys-cobra.dts
+++ b/dts/src/arm/armada-385-linksys-cobra.dts
@@ -44,71 +44,128 @@
model = "Linksys WRT1900ACv2";
compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+};
+
+&expander0 {
+ wan_amber@0 {
+ label = "cobra:amber:wan";
+ reg = <0x0>;
+ };
+
+ wan_white@1 {
+ label = "cobra:white:wan";
+ reg = <0x1>;
+ };
+
+ wlan_2g@2 {
+ label = "cobra:white:wlan_2g";
+ reg = <0x2>;
+ };
+
+ wlan_5g@3 {
+ label = "cobra:white:wlan_5g";
+ reg = <0x3>;
+ };
+
+ usb2@5 {
+ label = "cobra:white:usb2";
+ reg = <0x5>;
+ };
+
+ usb3_1@6 {
+ label = "cobra:white:usb3_1";
+ reg = <0x6>;
+ };
+
+ usb3_2@7 {
+ label = "cobra:white:usb3_2";
+ reg = <0x7>;
+ };
+
+ wps_white@8 {
+ label = "cobra:white:wps";
+ reg = <0x8>;
+ };
+
+ wps_amber@9 {
+ label = "cobra:amber:wps";
+ reg = <0x9>;
+ };
+};
+
+&gpio_leds {
+ power {
+ label = "cobra:white:power";
+ };
+
+ sata {
+ label = "cobra:white:sata";
+ };
+};
+
+&nand {
+ /* 128MiB */
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x200000>; /* 2MiB */
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u_env";
+ reg = <0x200000 0x40000>; /* 256KiB */
+ };
+
+ partition@140000 {
+ label = "s_env";
+ reg = <0x240000 0x40000>; /* 256KiB */
+ };
+
+ partition@900000 {
+ label = "devinfo";
+ reg = <0x900000 0x100000>; /* 1MiB */
+ read-only;
+ };
+
+ /* kernel1 overlaps with rootfs1 by design */
+ partition@a00000 {
+ label = "kernel1";
+ reg = <0xa00000 0x2800000>; /* 40MiB */
+ };
+
+ partition@1000000 {
+ label = "rootfs1";
+ reg = <0x1000000 0x2200000>; /* 34MiB */
+ };
+
+ /* kernel2 overlaps with rootfs2 by design */
+ partition@3200000 {
+ label = "kernel2";
+ reg = <0x3200000 0x2800000>; /* 40MiB */
+ };
+
+ partition@3800000 {
+ label = "rootfs2";
+ reg = <0x3800000 0x2200000>; /* 34MiB */
+ };
+
+ /*
+ * 38MiB, last MiB is for the BBT, not writable
+ */
+ partition@5a00000 {
+ label = "syscfg";
+ reg = <0x5a00000 0x2600000>;
+ };
- soc {
- internal-regs{
- i2c@11000 {
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan_amber@0 {
- label = "cobra:amber:wan";
- reg = <0x0>;
- };
-
- wan_white@1 {
- label = "cobra:white:wan";
- reg = <0x1>;
- };
-
- wlan_2g@2 {
- label = "cobra:white:wlan_2g";
- reg = <0x2>;
- };
-
- wlan_5g@3 {
- label = "cobra:white:wlan_5g";
- reg = <0x3>;
- };
-
- usb2@5 {
- label = "cobra:white:usb2";
- reg = <0x5>;
- };
-
- usb3_1@6 {
- label = "cobra:white:usb3_1";
- reg = <0x6>;
- };
-
- usb3_2@7 {
- label = "cobra:white:usb3_2";
- reg = <0x7>;
- };
-
- wps_white@8 {
- label = "cobra:white:wps";
- reg = <0x8>;
- };
-
- wps_amber@9 {
- label = "cobra:amber:wps";
- reg = <0x9>;
- };
- };
- };
- };
- };
-
- gpio-leds {
- power {
- label = "cobra:white:power";
- };
-
- sata {
- label = "cobra:white:sata";
- };
+ /*
+ * Unused area between "s_env" and "devinfo".
+ * Moved here because otherwise the renumbered
+ * partitions would break the bootloader
+ * supplied bootargs
+ */
+ partition@180000 {
+ label = "unused_area";
+ reg = <0x280000 0x680000>; /* 6.5MiB */
};
};
diff --git a/dts/src/arm/armada-385-linksys-rango.dts b/dts/src/arm/armada-385-linksys-rango.dts
new file mode 100644
index 0000000000..da8a0f3d43
--- /dev/null
+++ b/dts/src/arm/armada-385-linksys-rango.dts
@@ -0,0 +1,203 @@
+/*
+ * Device Tree file for the Linksys WRT3200ACM (Rango)
+ *
+ * Copyright (C) 2016 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-385-linksys.dtsi"
+
+/ {
+ model = "Linksys WRT3200ACM";
+ compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
+ "marvell,armada380";
+};
+
+&expander0 {
+ wan_amber@0 {
+ label = "rango:amber:wan";
+ reg = <0x0>;
+ };
+
+ wan_white@1 {
+ label = "rango:white:wan";
+ reg = <0x1>;
+ };
+
+ usb2@5 {
+ label = "rango:white:usb2";
+ reg = <0x5>;
+ };
+
+ usb3_1@6 {
+ label = "rango:white:usb3_1";
+ reg = <0x6>;
+ };
+
+ usb3_2@7 {
+ label = "rango:white:usb3_2";
+ reg = <0x7>;
+ };
+
+ wps_white@8 {
+ label = "rango:white:wps";
+ reg = <0x8>;
+ };
+
+ wps_amber@9 {
+ label = "rango:amber:wps";
+ reg = <0x9>;
+ };
+};
+
+&gpio_leds {
+ power {
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ label = "rango:white:power";
+ };
+
+ sata {
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ label = "rango:white:sata";
+ };
+
+ wlan_2g {
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ label = "rango:white:wlan_2g";
+ };
+
+ wlan_5g {
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ label = "rango:white:wlan_5g";
+ };
+};
+
+&gpio_leds_pins {
+ marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
+};
+
+&nand {
+ /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x200000>; /* 2MiB */
+ read-only;
+ };
+
+ partition@200000 {
+ label = "u_env";
+ reg = <0x200000 0x20000>; /* 128KiB */
+ };
+
+ partition@220000 {
+ label = "s_env";
+ reg = <0x220000 0x40000>; /* 256KiB */
+ };
+
+ partition@7e0000 {
+ label = "devinfo";
+ reg = <0x7e0000 0x40000>; /* 256KiB */
+ read-only;
+ };
+
+ partition@820000 {
+ label = "sysdiag";
+ reg = <0x820000 0x1e0000>; /* 1920KiB */
+ read-only;
+ };
+
+ /* kernel1 overlaps with rootfs1 by design */
+ partition@a00000 {
+ label = "kernel1";
+ reg = <0xa00000 0x5000000>; /* 80MiB */
+ };
+
+ partition@1000000 {
+ label = "rootfs1";
+ reg = <0x1000000 0x4a00000>; /* 74MiB */
+ };
+
+ /* kernel2 overlaps with rootfs2 by design */
+ partition@5a00000 {
+ label = "kernel2";
+ reg = <0x5a00000 0x5000000>; /* 80MiB */
+ };
+
+ partition@6000000 {
+ label = "rootfs2";
+ reg = <0x6000000 0x4a00000>; /* 74MiB */
+ };
+
+ /*
+ * 86MiB, last MiB is for the BBT, not writable
+ */
+ partition@aa00000 {
+ label = "syscfg";
+ reg = <0xaa00000 0x5600000>;
+ };
+
+ /*
+ * Unused area between "s_env" and "devinfo".
+ * Moved here because otherwise the renumbered
+ * partitions would break the bootloader
+ * supplied bootargs
+ */
+ partition@180000 {
+ label = "unused_area";
+ reg = <0x260000 0x5c0000>; /* 5.75MiB */
+ };
+};
+
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ no-1-8-v;
+ non-removable;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&usb3_1_vbus {
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3_1_vbus_pins {
+ marvell,pins = "mpp44";
+};
diff --git a/dts/src/arm/armada-385-linksys-shelby.dts b/dts/src/arm/armada-385-linksys-shelby.dts
index c7a8ddd7f9..94aa35bc0b 100644
--- a/dts/src/arm/armada-385-linksys-shelby.dts
+++ b/dts/src/arm/armada-385-linksys-shelby.dts
@@ -44,71 +44,128 @@
model = "Linksys WRT1900ACS";
compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+};
+
+&expander0 {
+ wan_amber@0 {
+ label = "shelby:amber:wan";
+ reg = <0x0>;
+ };
+
+ wan_white@1 {
+ label = "shelby:white:wan";
+ reg = <0x1>;
+ };
+
+ wlan_2g@2 {
+ label = "shelby:white:wlan_2g";
+ reg = <0x2>;
+ };
+
+ wlan_5g@3 {
+ label = "shelby:white:wlan_5g";
+ reg = <0x3>;
+ };
+
+ usb2@5 {
+ label = "shelby:white:usb2";
+ reg = <0x5>;
+ };
+
+ usb3_1@6 {
+ label = "shelby:white:usb3_1";
+ reg = <0x6>;
+ };
+
+ usb3_2@7 {
+ label = "shelby:white:usb3_2";
+ reg = <0x7>;
+ };
+
+ wps_white@8 {
+ label = "shelby:white:wps";
+ reg = <0x8>;
+ };
+
+ wps_amber@9 {
+ label = "shelby:amber:wps";
+ reg = <0x9>;
+ };
+};
+
+&gpio_leds {
+ power {
+ label = "shelby:white:power";
+ };
+
+ sata {
+ label = "shelby:white:sata";
+ };
+};
+
+&nand {
+ /* 128MiB */
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x200000>; /* 2MiB */
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u_env";
+ reg = <0x200000 0x40000>; /* 256KiB */
+ };
+
+ partition@140000 {
+ label = "s_env";
+ reg = <0x240000 0x40000>; /* 256KiB */
+ };
+
+ partition@900000 {
+ label = "devinfo";
+ reg = <0x900000 0x100000>; /* 1MiB */
+ read-only;
+ };
+
+ /* kernel1 overlaps with rootfs1 by design */
+ partition@a00000 {
+ label = "kernel1";
+ reg = <0xa00000 0x2800000>; /* 40MiB */
+ };
+
+ partition@1000000 {
+ label = "rootfs1";
+ reg = <0x1000000 0x2200000>; /* 34MiB */
+ };
+
+ /* kernel2 overlaps with rootfs2 by design */
+ partition@3200000 {
+ label = "kernel2";
+ reg = <0x3200000 0x2800000>; /* 40MiB */
+ };
+
+ partition@3800000 {
+ label = "rootfs2";
+ reg = <0x3800000 0x2200000>; /* 34MiB */
+ };
+
+ /*
+ * 38MiB, last MiB is for the BBT, not writable
+ */
+ partition@5a00000 {
+ label = "syscfg";
+ reg = <0x5a00000 0x2600000>;
+ };
- soc {
- internal-regs{
- i2c@11000 {
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan_amber@0 {
- label = "shelby:amber:wan";
- reg = <0x0>;
- };
-
- wan_white@1 {
- label = "shelby:white:wan";
- reg = <0x1>;
- };
-
- wlan_2g@2 {
- label = "shelby:white:wlan_2g";
- reg = <0x2>;
- };
-
- wlan_5g@3 {
- label = "shelby:white:wlan_5g";
- reg = <0x3>;
- };
-
- usb2@5 {
- label = "shelby:white:usb2";
- reg = <0x5>;
- };
-
- usb3_1@6 {
- label = "shelby:white:usb3_1";
- reg = <0x6>;
- };
-
- usb3_2@7 {
- label = "shelby:white:usb3_2";
- reg = <0x7>;
- };
-
- wps_white@8 {
- label = "shelby:white:wps";
- reg = <0x8>;
- };
-
- wps_amber@9 {
- label = "shelby:amber:wps";
- reg = <0x9>;
- };
- };
- };
- };
- };
-
- gpio-leds {
- power {
- label = "shelby:white:power";
- };
-
- sata {
- label = "shelby:white:sata";
- };
+ /*
+ * Unused area between "s_env" and "devinfo".
+ * Moved here because otherwise the renumbered
+ * partitions would break the bootloader
+ * supplied bootargs
+ */
+ partition@180000 {
+ label = "unused_area";
+ reg = <0x280000 0x680000>; /* 6.5MiB */
};
};
diff --git a/dts/src/arm/armada-385-linksys.dtsi b/dts/src/arm/armada-385-linksys.dtsi
index 2306c45685..e1f355ffc8 100644
--- a/dts/src/arm/armada-385-linksys.dtsi
+++ b/dts/src/arm/armada-385-linksys.dtsi
@@ -52,7 +52,7 @@
memory {
device_type = "memory";
- reg = <0x00000000 0x20000000>; /* 512 MB */
+ reg = <0x00000000 0x20000000>; /* 512 MiB */
};
soc {
@@ -61,255 +61,45 @@
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-
- internal-regs {
- i2c@11000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- tmp421@4c {
- compatible = "ti,tmp421";
- reg = <0x4c>;
- };
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,pca9635";
- reg = <0x68>;
- };
- };
-
- /* J10: VCC, NC, RX, NC, TX, GND */
- serial@12000 {
- status = "okay";
- };
-
- ethernet@70000 {
- status = "okay";
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- status = "okay";
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- mdio@72004 {
- status = "okay";
-
- switch@0 {
- compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan4";
- };
-
- port@1 {
- reg = <1>;
- label = "lan3";
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- };
-
- port@3 {
- reg = <3>;
- label = "lan1";
- };
-
- port@4 {
- reg = <4>;
- label = "wan";
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&eth2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
- };
-
- sata@a8000 {
- status = "okay";
- };
-
- bm@c8000 {
- status = "okay";
- };
-
- /* USB part of the eSATA/USB 2.0 port */
- usb@58000 {
- status = "okay";
- };
-
- usb3@f8000 {
- status = "okay";
- usb-phy = <&usb3_phy>;
- };
-
- flash@d0000 {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x200000>; /* 2MB */
- read-only;
- };
-
- partition@100000 {
- label = "u_env";
- reg = <0x200000 0x40000>; /* 256KB */
- };
-
- partition@140000 {
- label = "s_env";
- reg = <0x240000 0x40000>; /* 256KB */
- };
-
- partition@900000 {
- label = "devinfo";
- reg = <0x900000 0x100000>; /* 1MB */
- read-only;
- };
-
- /* kernel1 overlaps with rootfs1 by design */
- partition@a00000 {
- label = "kernel1";
- reg = <0xa00000 0x2800000>; /* 40MB */
- };
-
- partition@1000000 {
- label = "rootfs1";
- reg = <0x1000000 0x2200000>; /* 34MB */
- };
-
- /* kernel2 overlaps with rootfs2 by design */
- partition@3200000 {
- label = "kernel2";
- reg = <0x3200000 0x2800000>; /* 40MB */
- };
-
- partition@3800000 {
- label = "rootfs2";
- reg = <0x3800000 0x2200000>; /* 34MB */
- };
-
- /*
- * 38MB, last MB is for the BBT, not writable
- */
- partition@5a00000 {
- label = "syscfg";
- reg = <0x5a00000 0x2600000>;
- };
-
- /*
- * Unused area between "s_env" and "devinfo".
- * Moved here because otherwise the renumbered
- * partitions would break the bootloader
- * supplied bootargs
- */
- partition@180000 {
- label = "unused_area";
- reg = <0x280000 0x680000>; /* 6.5MB */
- };
- };
- };
-
- bm-bppi {
- status = "okay";
- };
-
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Marvell 88W8864, 5GHz-only */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Marvell 88W8864, 2GHz-only */
- status = "okay";
- };
- };
};
- usb3_phy: usb3_phy {
+ usb3_1_phy: usb3_1-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&reg_xhci0_vbus>;
+ vcc-supply = <&usb3_1_vbus>;
};
- reg_xhci0_vbus: xhci0-vbus {
+ usb3_1_vbus: usb3_1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&xhci0_vbus_pins>;
- regulator-name = "xhci0-vbus";
+ pinctrl-0 = <&usb3_1_vbus_pins>;
+ regulator-name = "usb3_1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
- gpio_keys {
+ gpio_keys: gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&keys_pin>;
+ pinctrl-0 = <&gpio_keys_pins>;
pinctrl-names = "default";
- button@1 {
+ wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
- button@2 {
+ reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
};
- gpio-leds {
+ gpio_leds: gpio-leds {
compatible = "gpio-leds";
- pinctrl-0 = <&power_led_pin &sata_led_pin>;
+ pinctrl-0 = <&gpio_leds_pins>;
pinctrl-names = "default";
power {
@@ -323,21 +113,83 @@
linux,default-trigger = "disk-activity";
};
};
+};
- dsa@0 {
- status = "disabled";
+&ahci0 {
+ status = "okay";
+};
+
+&bm {
+ status = "okay";
+};
- compatible = "marvell,dsa";
- #address-cells = <2>;
+&bm_bppi {
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&eth2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <3>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ tmp421@4c {
+ compatible = "ti,tmp421";
+ reg = <0x4c>;
+ };
+
+ expander0: pca9635@68 {
+ #address-cells = <1>;
#size-cells = <0>;
+ compatible = "nxp,pca9635";
+ reg = <0x68>;
+ };
+};
+
+&nand {
+ /* 128MiB or 256MiB */
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+};
- dsa,ethernet = <&eth2>;
- dsa,mii-bus = <&mdio>;
+&mdio {
+ status = "okay";
- switch@0 {
+ switch@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */
port@0 {
reg = <0>;
@@ -367,28 +219,45 @@
port@5 {
reg = <5>;
label = "cpu";
+ ethernet = <&eth2>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
};
};
};
+&pciec {
+ status = "okay";
+};
+
+&pcie1 {
+ /* Marvell 88W8864, 5GHz-only */
+ status = "okay";
+};
+
+&pcie2 {
+ /* Marvell 88W8864, 2GHz-only */
+ status = "okay";
+};
+
&pinctrl {
- keys_pin: keys-pin {
+ gpio_keys_pins: gpio-keys-pins {
+ /* mpp24: wps, mpp29: reset */
marvell,pins = "mpp24", "mpp29";
marvell,function = "gpio";
};
- power_led_pin: power-led-pin {
- marvell,pins = "mpp55";
- marvell,function = "gpio";
- };
-
- sata_led_pin: sata-led-pin {
- marvell,pins = "mpp54";
+ gpio_leds_pins: gpio-leds-pins {
+ /* mpp54: sata, mpp55: power */
+ marvell,pins = "mpp54", "mpp55";
marvell,function = "gpio";
};
- xhci0_vbus_pins: xhci0-vbus-pins {
+ usb3_1_vbus_pins: usb3_1-vbus-pins {
marvell,pins = "mpp50";
marvell,function = "gpio";
};
@@ -397,3 +266,18 @@
&spi0 {
status = "disabled";
};
+
+&uart0 {
+ /* J10: VCC, NC, RX, NC, TX, GND */
+ status = "okay";
+};
+
+&usb0 {
+ /* USB part of the eSATA/USB 2.0 port */
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+ usb-phy = <&usb3_1_phy>;
+};
diff --git a/dts/src/arm/armada-385-turris-omnia.dts b/dts/src/arm/armada-385-turris-omnia.dts
index 28eede180e..be16ce39fb 100644
--- a/dts/src/arm/armada-385-turris-omnia.dts
+++ b/dts/src/arm/armada-385-turris-omnia.dts
@@ -171,7 +171,7 @@
/* leds device (in STM32F0) at address 0x2b */
eeprom@54 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x54>;
/* The EEPROM contains data for bootloader.
diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi
index 8b165c31de..af31f5d6c0 100644
--- a/dts/src/arm/armada-38x.dtsi
+++ b/dts/src/arm/armada-38x.dtsi
@@ -312,31 +312,39 @@
};
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&coreclk 0>;
};
systemc: system-controller@18200 {
diff --git a/dts/src/arm/armada-xp-98dx3236.dtsi b/dts/src/arm/armada-xp-98dx3236.dtsi
index 84cc232a29..be22ec5236 100644
--- a/dts/src/arm/armada-xp-98dx3236.dtsi
+++ b/dts/src/arm/armada-xp-98dx3236.dtsi
@@ -311,6 +311,10 @@
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
+&rtc {
+ status = "disabled";
+};
+
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
diff --git a/dts/src/arm/armada-xp-98dx4251.dtsi b/dts/src/arm/armada-xp-98dx4251.dtsi
index 51de91b31a..bc9f824020 100644
--- a/dts/src/arm/armada-xp-98dx4251.dtsi
+++ b/dts/src/arm/armada-xp-98dx4251.dtsi
@@ -87,4 +87,5 @@
&pp0 {
compatible = "marvell,prestera-98dx4251";
+ interrupts = <33>, <34>, <35>, <36>;
};
diff --git a/dts/src/arm/armada-xp-linksys-mamba.dts b/dts/src/arm/armada-xp-linksys-mamba.dts
index 9efcf59c9b..6d705f5182 100644
--- a/dts/src/arm/armada-xp-linksys-mamba.dts
+++ b/dts/src/arm/armada-xp-linksys-mamba.dts
@@ -308,13 +308,11 @@
};
};
- gpio_fan {
+ pwm_fan {
/* SUNON HA4010V4-0000-C99 */
- compatible = "gpio-fan";
- gpios = <&gpio0 24 0>;
- gpio-fan,speed-map = <0 0
- 4500 1>;
+ compatible = "pwm-fan";
+ pwms = <&gpio0 24 4000>;
};
dsa {
diff --git a/dts/src/arm/armada-xp-mv78230.dtsi b/dts/src/arm/armada-xp-mv78230.dtsi
index 07c5090ecd..9f25814077 100644
--- a/dts/src/arm/armada-xp-mv78230.dtsi
+++ b/dts/src/arm/armada-xp-mv78230.dtsi
@@ -202,25 +202,33 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
+ clocks = <&coreclk 0>;
};
};
};
diff --git a/dts/src/arm/armada-xp-mv78260.dtsi b/dts/src/arm/armada-xp-mv78260.dtsi
index 64e936ae7b..2bfe07aebf 100644
--- a/dts/src/arm/armada-xp-mv78260.dtsi
+++ b/dts/src/arm/armada-xp-mv78260.dtsi
@@ -285,29 +285,38 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
diff --git a/dts/src/arm/armada-xp-mv78460.dtsi b/dts/src/arm/armada-xp-mv78460.dtsi
index d1383dde43..6c33935f70 100644
--- a/dts/src/arm/armada-xp-mv78460.dtsi
+++ b/dts/src/arm/armada-xp-mv78460.dtsi
@@ -323,29 +323,38 @@
internal-regs {
gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index 8c6bc29eb7..8a04c7e2d8 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -886,13 +886,12 @@
};
timer: timer@1e782000 {
+ /* This timer is a Faraday FTTMR010 derivative */
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
- // The moxart_timer driver registers only one
- // interrupt and assumes it's for timer 1
- //interrupts = <16 17 18 35 36 37 38 39>;
- interrupts = <16>;
+ interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
+ clock-names = "PCLK";
};
wdt1: wdt@1e785000 {
diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi
index a0bea4a6ec..9cffe347b8 100644
--- a/dts/src/arm/aspeed-g5.dtsi
+++ b/dts/src/arm/aspeed-g5.dtsi
@@ -993,13 +993,12 @@
};
timer: timer@1e782000 {
+ /* This timer is a Faraday FTTMR010 derivative */
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
- // The moxart_timer driver registers only one
- // interrupt and assumes it's for timer 1
- //interrupts = <16 17 18 35 36 37 38 39>;
- interrupts = <16>;
+ interrupts = <16 17 18 35 36 37 38 39>;
clocks = <&clk_apb>;
+ clock-names = "PCLK";
};
diff --git a/dts/src/arm/at91-cosino.dtsi b/dts/src/arm/at91-cosino.dtsi
index 02d8ef43de..89cde17515 100644
--- a/dts/src/arm/at91-cosino.dtsi
+++ b/dts/src/arm/at91-cosino.dtsi
@@ -82,38 +82,61 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc; /* Enable PMECC */
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand
+ &pinctrl_ebi_data_0_7>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- uboot@40000 {
- label = "u-boot";
- reg = <0x40000 0x80000>;
- };
-
- ubootenv@c0000 {
- label = "U-Boot Env";
- reg = <0xc0000 0x140000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
-
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0x80000>;
+ };
+
+ ubootenv@c0000 {
+ label = "U-Boot Env";
+ reg = <0xc0000 0x140000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-kizbox.dts b/dts/src/arm/at91-kizbox.dts
index b4f147c193..1f31df846d 100644
--- a/dts/src/arm/at91-kizbox.dts
+++ b/dts/src/arm/at91-kizbox.dts
@@ -59,19 +59,39 @@
status = "okay";
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
+ ebi: ebi@10000000 {
status = "okay";
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-kizbox2.dts b/dts/src/arm/at91-kizbox2.dts
index 50a14568f0..4372c0287c 100644
--- a/dts/src/arm/at91-kizbox2.dts
+++ b/dts/src/arm/at91-kizbox2.dts
@@ -141,23 +141,40 @@
status = "okay";
};
- nand0: nand@60000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
status = "okay";
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-kizboxmini.dts b/dts/src/arm/at91-kizboxmini.dts
index 9682d105d4..33238fcb6d 100644
--- a/dts/src/arm/at91-kizboxmini.dts
+++ b/dts/src/arm/at91-kizboxmini.dts
@@ -68,6 +68,49 @@
status = "okay";
};
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand
+ &pinctrl_ebi_data_0_7>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+ };
+ };
+
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
@@ -77,15 +120,6 @@
nand-on-flash-bbt;
status = "okay";
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
};
};
diff --git a/dts/src/arm/at91-linea.dtsi b/dts/src/arm/at91-linea.dtsi
index 0721c84725..87e5090fb4 100644
--- a/dts/src/arm/at91-linea.dtsi
+++ b/dts/src/arm/at91-linea.dtsi
@@ -31,19 +31,30 @@
status = "okay";
eeprom@51 {
- compatible = "st,24c64";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x51>;
pagesize = <32>;
};
};
-&nand0 {
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
status = "okay";
+};
+
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+&nand_controller {
+ status = "okay";
+
+ nand: nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+ };
};
diff --git a/dts/src/arm/at91-qil_a9260.dts b/dts/src/arm/at91-qil_a9260.dts
index 8f019184fc..f46352790a 100644
--- a/dts/src/arm/at91-qil_a9260.dts
+++ b/dts/src/arm/at91-qil_a9260.dts
@@ -107,50 +107,69 @@
status = "okay";
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@a0000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@c0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4c0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7cc0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@a0000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@c0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4c0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7cc0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts
index 0bef9e0b89..2e2c3d1a1f 100644
--- a/dts/src/arm/at91-sama5d2_xplained.dts
+++ b/dts/src/arm/at91-sama5d2_xplained.dts
@@ -56,10 +56,6 @@
stdout-path = "serial0:115200n8";
};
- memory {
- reg = <0x20000000 0x80000>;
- };
-
clocks {
slow_xtal {
clock-frequency = <32768>;
@@ -227,6 +223,10 @@
};
};
+ pwm0: pwm@f802c000 {
+ status = "okay";
+ };
+
flx0: flexcom@f8034000 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */
@@ -258,6 +258,12 @@
status = "okay";
};
+ can0: can@f8054000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+ status = "okay";
+ };
+
uart3: serial@fc008000 {
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -322,6 +328,18 @@
bias-disable;
};
+ pinctrl_can0_default: can0_default {
+ pinmux = <PIN_PC10__CANTX0>,
+ <PIN_PC11__CANRX0>;
+ bias-disable;
+ };
+
+ pinctrl_can1_default: can1_default {
+ pinmux = <PIN_PC26__CANTX1>,
+ <PIN_PC27__CANRX1>;
+ bias-disable;
+ };
+
pinctrl_charger_chglev: charger_chglev {
pinmux = <PIN_PA12__GPIO>;
bias-disable;
@@ -469,6 +487,12 @@
};
};
+
+ can1: can@fc050000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
+ status = "okay";
+ };
};
};
diff --git a/dts/src/arm/at91-sama5d3_xplained.dts b/dts/src/arm/at91-sama5d3_xplained.dts
index 5a53fcf542..3af088d2cb 100644
--- a/dts/src/arm/at91-sama5d3_xplained.dts
+++ b/dts/src/arm/at91-sama5d3_xplained.dts
@@ -235,46 +235,6 @@
};
};
- nand0: nand@60000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
- status = "okay";
-
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
-
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
-
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
-
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
- };
- };
-
usb0: gadget@00500000 {
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */
pinctrl-names = "default";
@@ -294,6 +254,63 @@
usb2: ehci@00700000 {
status = "okay";
};
+
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
+ };
+ };
};
vcc_mmc0_reg: fixedregulator_mmc0 {
diff --git a/dts/src/arm/at91-sama5d4_ma5d4.dtsi b/dts/src/arm/at91-sama5d4_ma5d4.dtsi
index b5a5a91bc2..b813fdfa28 100644
--- a/dts/src/arm/at91-sama5d4_ma5d4.dtsi
+++ b/dts/src/arm/at91-sama5d4_ma5d4.dtsi
@@ -75,7 +75,7 @@
reg = <0>;
clocks = <&clk20m>;
interrupt-parent = <&pioE>;
- interrupts = <6 GPIO_ACTIVE_LOW>;
+ interrupts = <6 IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <10000000>;
};
@@ -84,7 +84,7 @@
reg = <1>;
clocks = <&clk20m>;
interrupt-parent = <&pioE>;
- interrupts = <7 GPIO_ACTIVE_LOW>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <10000000>;
};
};
diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts
index 5ab14cedb1..cf712444b2 100644
--- a/dts/src/arm/at91-sama5d4_xplained.dts
+++ b/dts/src/arm/at91-sama5d4_xplained.dts
@@ -190,41 +190,60 @@
status = "okay";
};
- nand0: nand@80000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- atmel,has-pmecc;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe
+ &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy
+ &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
-
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
-
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts
index f8b96cef5e..bae5248f12 100644
--- a/dts/src/arm/at91-sama5d4ek.dts
+++ b/dts/src/arm/at91-sama5d4ek.dts
@@ -236,41 +236,60 @@
status = "okay";
};
- nand0: nand@80000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- atmel,has-pmecc;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe
+ &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy
+ &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
-
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
-
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91-tse850-3.dts b/dts/src/arm/at91-tse850-3.dts
index 498fba3e52..5f29010cdb 100644
--- a/dts/src/arm/at91-tse850-3.dts
+++ b/dts/src/arm/at91-tse850-3.dts
@@ -161,45 +161,51 @@
};
};
-&nand0 {
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
+&nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
- barebox@40000 {
- label = "bootloader";
- reg = <0x40000 0x60000>;
- };
+ barebox@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x60000>;
+ };
- bareboxenv@c0000 {
- label = "bareboxenv";
- reg = <0xc0000 0x40000>;
- };
+ bareboxenv@c0000 {
+ label = "bareboxenv";
+ reg = <0xc0000 0x40000>;
+ };
- bareboxenv2@100000 {
- label = "bareboxenv2";
- reg = <0x100000 0x40000>;
- };
+ bareboxenv2@100000 {
+ label = "bareboxenv2";
+ reg = <0x100000 0x40000>;
+ };
- oftree@180000 {
- label = "oftree";
- reg = <0x180000 0x20000>;
- };
+ oftree@180000 {
+ label = "oftree";
+ reg = <0x180000 0x20000>;
+ };
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x500000>;
- };
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x500000>;
+ };
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
- };
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
- ovlfs@10000000 {
- label = "ovlfs";
- reg = <0x10000000 0x10000000>;
+ ovlfs@10000000 {
+ label = "ovlfs";
+ reg = <0x10000000 0x10000000>;
+ };
};
};
@@ -239,7 +245,7 @@
};
eeprom@50 {
- compatible = "nxp,24c02";
+ compatible = "nxp,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi
index 9e035b21e1..6582f3cca9 100644
--- a/dts/src/arm/at91sam9260.dtsi
+++ b/dts/src/arm/at91sam9260.dtsi
@@ -99,6 +99,16 @@
reg = <0xffffea00 0x200>;
};
+ smc: smc@ffffec00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffec00 0x200>;
+ };
+
+ matrix: matrix@ffffee00 {
+ compatible = "atmel,at91sam9260-matrix", "syscon";
+ reg = <0xffffee00 0x200>;
+ };
+
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
@@ -522,10 +532,14 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
- <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */
- AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
+ <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -985,24 +999,6 @@
};
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40000000 0x10000000
- 0xffffe800 0x200
- >;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioC 13 GPIO_ACTIVE_HIGH
- &pioC 14 GPIO_ACTIVE_HIGH
- 0
- >;
- status = "disabled";
- };
-
usb0: ohci@500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
@@ -1011,6 +1007,33 @@
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9260-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x80000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000
+ 0x6 0x0 0x70000000 0x10000000
+ 0x7 0x0 0x80000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9260-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c-gpio-0 {
diff --git a/dts/src/arm/at91sam9261.dtsi b/dts/src/arm/at91sam9261.dtsi
index 7e80acda8f..a05353f961 100644
--- a/dts/src/arm/at91sam9261.dtsi
+++ b/dts/src/arm/at91sam9261.dtsi
@@ -91,20 +91,31 @@
status = "disabled";
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9261-ebi";
+ #address-cells = <2>;
#size-cells = <1>;
- reg = <0x40000000 0x10000000>;
- atmel,nand-addr-offset = <22>;
- atmel,nand-cmd-offset = <21>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
- <&pioC 14 GPIO_ACTIVE_HIGH>,
- <0>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x80000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000
+ 0x6 0x0 0x70000000 0x10000000
+ 0x7 0x0 0x80000000 0x10000000>;
+ clocks = <&mck>;
status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9261-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
};
apb {
@@ -262,6 +273,11 @@
reg = <0xffffea00 0x200>;
};
+ smc: smc@ffffec00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffec00 0x200>;
+ };
+
matrix: matrix@ffffee00 {
compatible = "atmel,at91sam9261-matrix", "syscon";
reg = <0xffffee00 0x200>;
@@ -362,9 +378,13 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
- <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
diff --git a/dts/src/arm/at91sam9261ek.dts b/dts/src/arm/at91sam9261ek.dts
index 55bd51f07f..157e1493e6 100644
--- a/dts/src/arm/at91sam9261ek.dts
+++ b/dts/src/arm/at91sam9261ek.dts
@@ -68,40 +68,59 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
-
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
-
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
-
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi
index a1888f6d89..ed4b564f8d 100644
--- a/dts/src/arm/at91sam9263.dtsi
+++ b/dts/src/arm/at91sam9263.dtsi
@@ -361,11 +361,26 @@
reg = <0xffffe200 0x200>;
};
+ smc0: smc@ffffe400 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffe400 0x200>;
+ };
+
ramc1: ramc@ffffe800 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe800 0x200>;
};
+ smc1: smc@ffffea00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x200>;
+ };
+
+ matrix: matrix@ffffec00 {
+ compatible = "atmel,at91sam9263-matrix", "syscon";
+ reg = <0xffffec00 0x200>;
+ };
+
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
@@ -472,10 +487,14 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
- <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
- AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
+ <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -991,24 +1010,6 @@
status = "disabled";
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40000000 0x10000000
- 0xffffe000 0x200
- >;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioA 22 GPIO_ACTIVE_HIGH
- &pioD 15 GPIO_ACTIVE_HIGH
- 0
- >;
- status = "disabled";
- };
-
usb0: ohci@00a00000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
@@ -1017,6 +1018,52 @@
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
+
+ ebi0: ebi@10000000 {
+ compatible = "atmel,at91sam9263-ebi0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc0>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x80000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller0: nand-controller {
+ compatible = "atmel,at91sam9260-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
+ ebi1: ebi@70000000 {
+ compatible = "atmel,at91sam9263-ebi1";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc1>;
+ atmel,matrix = <&matrix>;
+ reg = <0x80000000 0x20000000>;
+ ranges = <0x0 0x0 0x80000000 0x10000000
+ 0x1 0x0 0x90000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller1: nand-controller {
+ compatible = "atmel,at91sam9260-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c-gpio-0 {
diff --git a/dts/src/arm/at91sam9263ek.dts b/dts/src/arm/at91sam9263ek.dts
index 127cc42e9e..10a0925da1 100644
--- a/dts/src/arm/at91sam9263ek.dts
+++ b/dts/src/arm/at91sam9263ek.dts
@@ -125,50 +125,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt = <1>;
+ ebi0: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/at91sam9g20ek_common.dtsi b/dts/src/arm/at91sam9g20ek_common.dtsi
index 27847a47c1..ac9a1511e2 100644
--- a/dts/src/arm/at91sam9g20ek_common.dtsi
+++ b/dts/src/arm/at91sam9g20ek_common.dtsi
@@ -123,50 +123,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index e567d5fd3f..a4808c4fbc 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -113,6 +113,16 @@
clock-names = "ddrck";
};
+ smc: smc@ffffe800 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffe800 0x200>;
+ };
+
+ matrix: matrix@ffffea00 {
+ compatible = "atmel,at91sam9g45-matrix", "syscon";
+ reg = <0xffffea00 0x200>;
+ };
+
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
@@ -601,10 +611,14 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
- <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
- AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
+ <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -1278,25 +1292,6 @@
status = "disabled";
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40000000 0x10000000
- 0xffffe200 0x200
- >;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioC 8 GPIO_ACTIVE_HIGH
- &pioC 14 GPIO_ACTIVE_HIGH
- 0
- >;
- status = "disabled";
- };
-
usb0: ohci@00700000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
@@ -1314,6 +1309,31 @@
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9g45-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x80000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9g45-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c-gpio-0 {
diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts
index 2400c99134..2522c33083 100644
--- a/dts/src/arm/at91sam9m10g45ek.dts
+++ b/dts/src/arm/at91sam9m10g45ek.dts
@@ -245,25 +245,44 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- boot@0 {
- label = "bootstrap/uboot/kernel";
- reg = <0x0 0x400000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
- rootfs@400000 {
- label = "rootfs";
- reg = <0x400000 0x3C00000>;
- };
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "bootstrap/uboot/kernel";
+ reg = <0x0 0x400000>;
+ };
- data@4000000 {
- label = "data";
- reg = <0x4000000 0xC000000>;
+ rootfs@400000 {
+ label = "rootfs";
+ reg = <0x400000 0x3C00000>;
+ };
+
+ data@4000000 {
+ label = "data";
+ reg = <0x4000000 0xC000000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi
index f43d769535..06516d02d3 100644
--- a/dts/src/arm/at91sam9n12.dtsi
+++ b/dts/src/arm/at91sam9n12.dtsi
@@ -89,6 +89,17 @@
atmel,external-irqs = <31>;
};
+ matrix: matrix@ffffde00 {
+ compatible = "atmel,at91sam9n12-matrix", "syscon";
+ reg = <0xffffde00 0x100>;
+ };
+
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x600>,
+ <0xffffe600 0x200>;
+ };
+
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
@@ -96,6 +107,11 @@
clock-names = "ddrck";
};
+ smc: smc@ffffea00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x200>;
+ };
+
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9n12-pmc", "syscon";
reg = <0xfffffc00 0x200>;
@@ -627,10 +643,14 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
- <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
- AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -998,28 +1018,6 @@
};
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = < 0x40000000 0x10000000
- 0xffffe000 0x00000600
- 0xffffe600 0x00000200
- 0x00108000 0x00018000
- >;
- atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioD 5 GPIO_ACTIVE_HIGH
- &pioD 4 GPIO_ACTIVE_HIGH
- 0
- >;
- status = "disabled";
- };
-
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
@@ -1028,6 +1026,32 @@
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9x5-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x60000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9g45-nand-controller";
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c-gpio-0 {
diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts
index 626c67d666..5bea8c59b1 100644
--- a/dts/src/arm/at91sam9n12ek.dts
+++ b/dts/src/arm/at91sam9n12ek.dts
@@ -147,14 +147,26 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <2>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-ecc-strength = <2>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+ };
+ };
};
usb0: ohci@00500000 {
diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi
index f4c129a98f..7768342a66 100644
--- a/dts/src/arm/at91sam9rl.dtsi
+++ b/dts/src/arm/at91sam9rl.dtsi
@@ -92,21 +92,29 @@
status = "disabled";
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9rl-ebi";
+ #address-cells = <2>;
#size-cells = <1>;
- reg = <0x40000000 0x10000000>,
- <0xffffe800 0x200>;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
- <&pioB 6 GPIO_ACTIVE_HIGH>,
- <0>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x80000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9g45-nand-controller";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
};
apb {
@@ -364,6 +372,16 @@
reg = <0xffffea00 0x200>;
};
+ smc: smc@ffffec00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffec00 0x200>;
+ };
+
+ matrix: matrix@ffffee00 {
+ compatible = "atmel,at91sam9rl-matrix", "syscon";
+ reg = <0xffffee00 0x200>;
+ };
+
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
compatible = "atmel,at91rm9200-aic";
@@ -443,6 +461,14 @@
};
};
+ ebi {
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
fb {
pinctrl_fb: fb-0 {
atmel,pins =
@@ -507,28 +533,21 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
- <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
- <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
- pinctrl_nand0_ale_cle: nand_ale_cle-0 {
+ pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
- <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
- pinctrl_nand0_oe_we: nand_oe_we-0 {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
-
- pinctrl_nand0_cs: nand_cs-0 {
- atmel,pins =
- <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
- };
};
pwm0 {
diff --git a/dts/src/arm/at91sam9rlek.dts b/dts/src/arm/at91sam9rlek.dts
index 2e567d90fb..9047c16829 100644
--- a/dts/src/arm/at91sam9rlek.dts
+++ b/dts/src/arm/at91sam9rlek.dts
@@ -63,40 +63,63 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt = <1>;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
-
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
-
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi
index f66bae9257..57f307541d 100644
--- a/dts/src/arm/at91sam9x5.dtsi
+++ b/dts/src/arm/at91sam9x5.dtsi
@@ -97,6 +97,17 @@
atmel,external-irqs = <31>;
};
+ matrix: matrix@ffffde00 {
+ compatible = "atmel,at91sam9x5-matrix", "syscon";
+ reg = <0xffffde00 0x100>;
+ };
+
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x600>,
+ <0xffffe600 0x200>;
+ };
+
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
@@ -104,6 +115,11 @@
clock-names = "ddrck";
};
+ smc: smc@ffffea00 {
+ compatible = "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x200>;
+ };
+
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
@@ -465,6 +481,38 @@
};
};
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_data_8_15: ebi-data-msb-0 {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -551,34 +599,20 @@
};
nand {
- pinctrl_nand: nand-0 {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
- <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
- AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
- AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
- AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
- AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
- AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
- AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
- AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
- AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
- AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
- AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
- AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
- AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
- AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
- };
-
- pinctrl_nand_16bits: nand_16bits-0 {
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
- AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
- AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
- AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
- AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
- AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
- AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
- AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -1197,28 +1231,6 @@
};
};
- nand0: nand@40000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40000000 0x10000000
- 0xffffe000 0x600 /* PMECC Registers */
- 0xffffe600 0x200 /* PMECC Error Location Registers */
- 0x00108000 0x18000 /* PMECC looup table in ROM code */
- >;
- atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- gpios = <&pioD 5 GPIO_ACTIVE_HIGH
- &pioD 4 GPIO_ACTIVE_HIGH
- 0
- >;
- status = "disabled";
- };
-
usb0: ohci@00600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
@@ -1236,6 +1248,32 @@
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,at91sam9x5-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x60000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,at91sam9g45-nand-controller";
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
};
i2c-gpio-0 {
diff --git a/dts/src/arm/at91sam9x5cm.dtsi b/dts/src/arm/at91sam9x5cm.dtsi
index b098ad8cd9..bdeaa0b64a 100644
--- a/dts/src/arm/at91sam9x5cm.dtsi
+++ b/dts/src/arm/at91sam9x5cm.dtsi
@@ -37,38 +37,61 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc; /* Enable PMECC */
- atmel,pmecc-cap = <2>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand
+ &pinctrl_ebi_data_0_7>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
-
- uboot@40000 {
- label = "u-boot";
- reg = <0x40000 0x80000>;
- };
-
- ubootenv@c0000 {
- label = "U-Boot Env";
- reg = <0xc0000 0x140000>;
- };
-
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
-
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x1f800000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <2>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0x80000>;
+ };
+
+ ubootenv@c0000 {
+ label = "U-Boot Env";
+ reg = <0xc0000 0x140000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/axp209.dtsi b/dts/src/arm/axp209.dtsi
index 9677dd5cf6..3c8fa26e87 100644
--- a/dts/src/arm/axp209.dtsi
+++ b/dts/src/arm/axp209.dtsi
@@ -64,6 +64,11 @@
#gpio-cells = <2>;
};
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp209-battery-power-supply";
+ status = "disabled";
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <1500>;
diff --git a/dts/src/arm/axp22x.dtsi b/dts/src/arm/axp22x.dtsi
index 67331c5f17..87fb08e812 100644
--- a/dts/src/arm/axp22x.dtsi
+++ b/dts/src/arm/axp22x.dtsi
@@ -57,6 +57,11 @@
status = "disabled";
};
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp221-battery-power-supply";
+ status = "disabled";
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi
index 9644fddb5e..bf8c838157 100644
--- a/dts/src/arm/bcm-cygnus.dtsi
+++ b/dts/src/arm/bcm-cygnus.dtsi
@@ -142,6 +142,55 @@
interrupts = <0>;
};
+ mdio: mdio@18002000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18002000 0x8>;
+ #size-cells = <1>;
+ #address-cells = <0>;
+ status = "disabled";
+
+ gphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ gphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ switch: switch@18007000 {
+ compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
+ reg = <0x18007000 0x1000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ phy-handle = <&gphy0>;
+ phy-mode = "rgmii";
+ };
+
+ port@1 {
+ reg = <1>;
+ phy-handle = <&gphy1>;
+ phy-mode = "rgmii";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&eth0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
@@ -295,6 +344,15 @@
status = "disabled";
};
+ eth0: ethernet@18042000 {
+ compatible = "brcm,amac";
+ reg = <0x18042000 0x1000>,
+ <0x18110000 0x1000>;
+ reg-names = "amac_base", "idm_base";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
@@ -386,6 +444,19 @@
status = "disabled";
};
+ v3d: v3d@180a2000 {
+ compatible = "brcm,cygnus-v3d";
+ reg = <0x180a2000 0x1000>;
+ clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
+ clock-names = "v3d_clk";
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ vc4: gpu {
+ compatible = "brcm,cygnus-vc4";
+ };
+
adc: adc@180a6000 {
compatible = "brcm,iproc-static-adc";
#io-channel-cells = <1>;
diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi
index fe6cba994a..7204d1def2 100644
--- a/dts/src/arm/bcm-nsp.dtsi
+++ b/dts/src/arm/bcm-nsp.dtsi
@@ -413,6 +413,12 @@
<0x3f408 0x04>;
};
+ thermal: thermal@3f2c0 {
+ compatible = "brcm,ns-thermal";
+ reg = <0x3f2c0 0x10>;
+ #thermal-sensor-cells = <0>;
+ };
+
sata_phy: sata_phy@40100 {
compatible = "brcm,iproc-nsp-sata-phy";
reg = <0x40100 0x340>;
@@ -563,4 +569,24 @@
brcm,pcie-msi-inten;
};
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ coefficients = <(-556) 418000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
};
diff --git a/dts/src/arm/bcm2835-rpi-zero.dts b/dts/src/arm/bcm2835-rpi-zero.dts
index cc8b832c4c..79a20d5209 100644
--- a/dts/src/arm/bcm2835-rpi-zero.dts
+++ b/dts/src/arm/bcm2835-rpi-zero.dts
@@ -12,7 +12,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
-#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-usb-otg.dtsi"
/ {
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi
index a7b5ce1337..e55b362b9d 100644
--- a/dts/src/arm/bcm2835-rpi.dtsi
+++ b/dts/src/arm/bcm2835-rpi.dtsi
@@ -65,13 +65,13 @@
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
- status = "okay";
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
bus-width = <4>;
};
diff --git a/dts/src/arm/bcm2835.dtsi b/dts/src/arm/bcm2835.dtsi
index 0890d97e67..659b6e9513 100644
--- a/dts/src/arm/bcm2835.dtsi
+++ b/dts/src/arm/bcm2835.dtsi
@@ -24,6 +24,10 @@
};
};
+&cpu_thermal {
+ coefficients = <(-538) 407000>;
+};
+
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2835-thermal";
diff --git a/dts/src/arm/bcm2836.dtsi b/dts/src/arm/bcm2836.dtsi
index 519a44f5d2..da3deeb425 100644
--- a/dts/src/arm/bcm2836.dtsi
+++ b/dts/src/arm/bcm2836.dtsi
@@ -77,6 +77,10 @@
interrupts = <8>;
};
+&cpu_thermal {
+ coefficients = <(-538) 407000>;
+};
+
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2836-thermal";
diff --git a/dts/src/arm/bcm2837-rpi-3-b.dts b/dts/src/arm/bcm2837-rpi-3-b.dts
new file mode 100644
index 0000000000..c72a27d908
--- /dev/null
+++ b/dts/src/arm/bcm2837-rpi-3-b.dts
@@ -0,0 +1 @@
+#include "arm64/broadcom/bcm2837-rpi-3-b.dts"
diff --git a/dts/src/arm/bcm283x-rpi-usb-otg.dtsi b/dts/src/arm/bcm283x-rpi-usb-otg.dtsi
new file mode 100644
index 0000000000..e7d217c967
--- /dev/null
+++ b/dts/src/arm/bcm283x-rpi-usb-otg.dtsi
@@ -0,0 +1,10 @@
+&usb {
+ dr_mode = "otg";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ /*
+ * According to dwc2 the sum of all device EP
+ * fifo sizes shouldn't exceed 3776 bytes.
+ */
+ g-tx-fifo-size = <256 256 512 512 512 768 768>;
+};
diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi
index 9444a9a9ba..431dcfc900 100644
--- a/dts/src/arm/bcm283x.dtsi
+++ b/dts/src/arm/bcm283x.dtsi
@@ -24,6 +24,26 @@
bootargs = "earlyprintk console=ttyAMA0";
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <80000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -435,6 +455,7 @@
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
status = "disabled";
};
@@ -573,6 +594,8 @@
#size-cells = <0>;
clocks = <&clk_usb>;
clock-names = "otg";
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
};
v3d: v3d@7ec00000 {
@@ -608,4 +631,8 @@
clock-frequency = <480000000>;
};
};
+
+ usbphy: phy {
+ compatible = "usb-nop-xceiv";
+ };
};
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index acee36a610..98647d22b2 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -320,6 +320,14 @@
};
};
+ mdio: mdio@18003000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18003000 0x8>;
+ #size-cells = <1>;
+ #address-cells = <0>;
+ status = "disabled";
+ };
+
i2c0: i2c@18009000 {
compatible = "brcm,iproc-i2c";
reg = <0x18009000 0x50>;
@@ -349,6 +357,12 @@
"sata2";
};
+ thermal: thermal@1800c2c0 {
+ compatible = "brcm,ns-thermal";
+ reg = <0x1800c2c0 0x10>;
+ #thermal-sensor-cells = <0>;
+ };
+
srab: srab@18007000 {
compatible = "brcm,bcm5301x-srab";
reg = <0x18007000 0x1000>;
@@ -412,4 +426,24 @@
status = "disabled";
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ coefficients = <(-556) 418000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
};
diff --git a/dts/src/arm/bcm911360_entphn.dts b/dts/src/arm/bcm911360_entphn.dts
index 8b3800f462..000f5f1921 100644
--- a/dts/src/arm/bcm911360_entphn.dts
+++ b/dts/src/arm/bcm911360_entphn.dts
@@ -57,6 +57,26 @@
};
};
+&eth0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+};
+
+&v3d {
+ assigned-clocks =
+ <&mipipll BCM_CYGNUS_MIPIPLL>,
+ <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
+ assigned-clock-rates = <525000000>, <300000000>;
+ status = "okay";
+};
+
&uart3 {
status = "okay";
};
diff --git a/dts/src/arm/da850-evm.dts b/dts/src/arm/da850-evm.dts
index 8d244cd76c..a423e8ebfb 100644
--- a/dts/src/arm/da850-evm.dts
+++ b/dts/src/arm/da850-evm.dts
@@ -82,6 +82,8 @@
tca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
};
wdt: wdt@21000 {
diff --git a/dts/src/arm/da850-lego-ev3.dts b/dts/src/arm/da850-lego-ev3.dts
index 512604ad8b..45983c04a8 100644
--- a/dts/src/arm/da850-lego-ev3.dts
+++ b/dts/src/arm/da850-lego-ev3.dts
@@ -172,6 +172,18 @@
gpio = <&gpio 111 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ /*
+ * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack.
+ */
+ battery {
+ pinctrl-names = "default";
+ pintctrl-0 = <&battery_pins>;
+ compatible = "lego,ev3-battery";
+ io-channels = <&adc 4>, <&adc 3>;
+ io-channel-names = "voltage", "current";
+ rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>;
+ };
};
&pmx_core {
@@ -228,6 +240,15 @@
0x34 0x00000008 0x0000000f
>;
};
+
+ battery_pins: pinmux_battery_pins {
+ pinctrl-single,bits = <
+ /* GP0[6] */
+ 0x04 0x00000080 0x000000f0
+ /* GP8[8] */
+ 0x4c 0x00000080 0x000000f0
+ >;
+ };
};
&pinconf {
@@ -342,6 +363,13 @@
&gpio {
status = "okay";
+
+ /* Don't pull down battery voltage adc io channel */
+ batt_volt_en {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
};
&usb_phy {
diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi
index 941d455000..af68ef7b0c 100644
--- a/dts/src/arm/da850.dtsi
+++ b/dts/src/arm/da850.dtsi
@@ -446,13 +446,38 @@
};
usb0: usb@200000 {
compatible = "ti,da830-musb";
- reg = <0x200000 0x10000>;
+ reg = <0x200000 0x1000>;
+ ranges;
interrupts = <58>;
interrupt-names = "mc";
dr_mode = "otg";
phys = <&usb_phy 0>;
phy-names = "usb-phy";
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dmas = <&cppi41dma 0 0 &cppi41dma 1 0
+ &cppi41dma 2 0 &cppi41dma 3 0
+ &cppi41dma 0 1 &cppi41dma 1 1
+ &cppi41dma 2 1 &cppi41dma 3 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4",
+ "tx1", "tx2", "tx3", "tx4";
+
+ cppi41dma: dma-controller@201000 {
+ compatible = "ti,da830-cppi41";
+ reg = <0x201000 0x1000
+ 0x202000 0x1000
+ 0x204000 0x4000>;
+ reg-names = "controller",
+ "scheduler", "queuemgr";
+ interrupts = <58>;
+ #dma-cells = <2>;
+ #dma-channels = <4>;
+ status = "okay";
+ };
};
sata: sata@218000 {
compatible = "ti,da850-ahci";
@@ -503,6 +528,8 @@
ti,ngpio = <144>;
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
pinconf: pin-controller@22c00c {
compatible = "ti,da850-pupd";
diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts
index 31a9e061dd..f47fc4daf0 100644
--- a/dts/src/arm/dra7-evm.dts
+++ b/dts/src/arm/dra7-evm.dts
@@ -529,7 +529,8 @@
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ extcon = <&extcon_usb1>;
};
&usb2 {
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index e7144662af..0f0f6f58bd 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -99,14 +99,14 @@
compatible = "operating-points-v2-ti-cpu";
syscon = <&scm_wkup>;
- opp_nom@1000000000 {
+ opp_nom-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
- opp_od@1176000000 {
+ opp_od-1176000000 {
opp-hz = /bits/ 64 <1176000000>;
opp-microvolt = <1160000 885000 1160000>;
opp-supported-hw = <0xFF 0x02>;
diff --git a/dts/src/arm/dra72-evm-common.dtsi b/dts/src/arm/dra72-evm-common.dtsi
index ad24544adf..85780549bc 100644
--- a/dts/src/arm/dra72-evm-common.dtsi
+++ b/dts/src/arm/dra72-evm-common.dtsi
@@ -392,7 +392,8 @@
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ extcon = <&extcon_usb1>;
};
&usb2 {
diff --git a/dts/src/arm/dra7xx-clocks.dtsi b/dts/src/arm/dra7xx-clocks.dtsi
index 3330738e4c..cf229dfabf 100644
--- a/dts/src/arm/dra7xx-clocks.dtsi
+++ b/dts/src/arm/dra7xx-clocks.dtsi
@@ -338,6 +338,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+ assigned-clocks = <&dpll_dsp_ck>;
+ assigned-clock-rates = <600000000>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
@@ -349,6 +351,8 @@
reg = <0x0244>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_dsp_m2_ck>;
+ assigned-clock-rates = <600000000>;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -372,6 +376,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <1165000000>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
@@ -383,6 +389,8 @@
reg = <0x01b0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m2_ck>;
+ assigned-clock-rates = <388333334>;
};
iva_dclk: iva_dclk {
@@ -406,6 +414,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+ assigned-clocks = <&dpll_gpu_ck>;
+ assigned-clock-rates = <1277000000>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
@@ -417,6 +427,8 @@
reg = <0x02e8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_gpu_m2_ck>;
+ assigned-clock-rates = <425666667>;
};
dpll_core_m2_ck: dpll_core_m2_ck@130 {
@@ -659,6 +671,8 @@
reg = <0x0248>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_dsp_m3x2_ck>;
+ assigned-clock-rates = <400000000>;
};
dpll_gmac_x2_ck: dpll_gmac_x2_ck {
@@ -791,6 +805,8 @@
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
+ assigned-clocks = <&ipu1_gfclk_mux>;
+ assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
@@ -1748,6 +1764,8 @@
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
+ assigned-clocks = <&gpu_core_gclk_mux>;
+ assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
@@ -1756,6 +1774,8 @@
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
+ assigned-clocks = <&gpu_hyd_gclk_mux>;
+ assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
diff --git a/dts/src/arm/emev2.dtsi b/dts/src/arm/emev2.dtsi
index 0124faf175..42ea246e71 100644
--- a/dts/src/arm/emev2.dtsi
+++ b/dts/src/arm/emev2.dtsi
@@ -197,7 +197,7 @@
clock-names = "sclk";
};
- pfc: pfc@e0140200 {
+ pfc: pin-controller@e0140200 {
compatible = "renesas,pfc-emev2";
reg = <0xe0140200 0x100>;
};
diff --git a/dts/src/arm/ethernut5.dts b/dts/src/arm/ethernut5.dts
index 4687229a3a..123b203be0 100644
--- a/dts/src/arm/ethernut5.dts
+++ b/dts/src/arm/ethernut5.dts
@@ -55,25 +55,38 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- gpios = <0
- &pioC 14 GPIO_ACTIVE_HIGH
- 0
- >;
-
- root@0 {
- label = "root";
- reg = <0x0 0x08000000>;
- };
-
- data@20000 {
- label = "data";
- reg = <0x08000000 0x38000000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs>;
+ pinctrl-names = "default";
+
+ nand: nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ root@0 {
+ label = "root";
+ reg = <0x0 0x08000000>;
+ };
+
+ data@20000 {
+ label = "data";
+ reg = <0x08000000 0x38000000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts
index cccfe4b791..accee81da2 100644
--- a/dts/src/arm/exynos3250-monk.dts
+++ b/dts/src/arm/exynos3250-monk.dts
@@ -67,7 +67,7 @@
max77836: subpmic@25 {
compatible = "maxim,max77836";
interrupt-parent = <&gpx1>;
- interrupts = <5 0>;
+ interrupts = <5 IRQ_TYPE_NONE>;
reg = <0x25>;
wakeup-source;
@@ -191,7 +191,7 @@
s2mps14_pmic@66 {
compatible = "samsung,s2mps14-pmic";
interrupt-parent = <&gpx0>;
- interrupts = <7 0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
reg = <0x66>;
wakeup-source;
@@ -414,7 +414,7 @@
fuelgauge@36 {
compatible = "maxim,max77836-battery";
interrupt-parent = <&gpx1>;
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x36>;
};
};
diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts
index c9f191ca7b..443e0c98dc 100644
--- a/dts/src/arm/exynos3250-rinato.dts
+++ b/dts/src/arm/exynos3250-rinato.dts
@@ -58,7 +58,7 @@
max77836: subpmic@25 {
compatible = "maxim,max77836";
interrupt-parent = <&gpx1>;
- interrupts = <5 0>;
+ interrupts = <5 IRQ_TYPE_NONE>;
reg = <0x25>;
wakeup-source;
@@ -240,7 +240,7 @@
reg = <0>;
vdd3-supply = <&ldo16_reg>;
vci-supply = <&ldo20_reg>;
- reset-gpios = <&gpe0 1 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>;
te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
power-on-delay= <30>;
power-off-delay= <120>;
@@ -295,7 +295,7 @@
s2mps14_pmic@66 {
compatible = "samsung,s2mps14-pmic";
interrupt-parent = <&gpx0>;
- interrupts = <7 0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
reg = <0x66>;
wakeup-source;
@@ -626,7 +626,7 @@
fuelgauge@36 {
compatible = "maxim,max77836-battery";
interrupt-parent = <&gpx1>;
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x36>;
};
};
diff --git a/dts/src/arm/exynos4210-origen.dts b/dts/src/arm/exynos4210-origen.dts
index 312650e245..084fcc5574 100644
--- a/dts/src/arm/exynos4210-origen.dts
+++ b/dts/src/arm/exynos4210-origen.dts
@@ -151,7 +151,7 @@
compatible = "maxim,max8997-pmic";
reg = <0x66>;
interrupt-parent = <&gpx0>;
- interrupts = <4 0>, <3 0>;
+ interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>;
max8997,pmic-buck1-dvs-voltage = <1350000>;
max8997,pmic-buck2-dvs-voltage = <1100000>;
diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts
index 1743ca8500..645feffb92 100644
--- a/dts/src/arm/exynos4210-trats.dts
+++ b/dts/src/arm/exynos4210-trats.dts
@@ -281,7 +281,7 @@
compatible = "melfas,mms114";
reg = <0x48>;
interrupt-parent = <&gpx0>;
- interrupts = <4 2>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
x-size = <720>;
y-size = <1280>;
avdd-supply = <&tsp_reg>;
@@ -302,7 +302,7 @@
reg = <0x66>;
interrupt-parent = <&gpx0>;
- interrupts = <7 0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
max8997,pmic-buck1-uses-gpio-dvs;
max8997,pmic-buck2-uses-gpio-dvs;
diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi
index 0f1ff792fe..219d587c5a 100644
--- a/dts/src/arm/exynos4412-odroid-common.dtsi
+++ b/dts/src/arm/exynos4412-odroid-common.dtsi
@@ -32,7 +32,7 @@
power_key {
interrupt-parent = <&gpx1>;
- interrupts = <3 0>;
+ interrupts = <3 IRQ_TYPE_NONE>;
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "power key";
@@ -266,7 +266,7 @@
max77686: pmic@09 {
compatible = "maxim,max77686";
interrupt-parent = <&gpx3>;
- interrupts = <2 0>;
+ interrupts = <2 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
reg = <0x09>;
@@ -484,7 +484,7 @@
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpx0>;
- interrupts = <0 0>;
+ interrupts = <0 IRQ_TYPE_NONE>;
clocks = <&i2s0 CLK_I2S_CDCLK>;
clock-names = "mclk";
#sound-dai-cells = <0>;
diff --git a/dts/src/arm/exynos4412-odroidu3.dts b/dts/src/arm/exynos4412-odroidu3.dts
index 7504a5aa53..44a4de0846 100644
--- a/dts/src/arm/exynos4412-odroidu3.dts
+++ b/dts/src/arm/exynos4412-odroidu3.dts
@@ -78,6 +78,10 @@
regulator-max-microvolt = <3300000>;
};
+&hdmicec {
+ needs-hpd;
+};
+
/* VDDQ for MSHC (eMMC card) */
&ldo22_reg {
regulator-name = "LDO22_VDDQ_MMC4_2.8V";
diff --git a/dts/src/arm/exynos4412-odroidx.dts b/dts/src/arm/exynos4412-odroidx.dts
index 46b931eec2..97882267ef 100644
--- a/dts/src/arm/exynos4412-odroidx.dts
+++ b/dts/src/arm/exynos4412-odroidx.dts
@@ -44,7 +44,7 @@
home_key {
interrupt-parent = <&gpx2>;
- interrupts = <2 0>;
+ interrupts = <2 IRQ_TYPE_NONE>;
gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_HOME>;
label = "home key";
diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts
index 82221a0044..35e9b94b86 100644
--- a/dts/src/arm/exynos4412-trats2.dts
+++ b/dts/src/arm/exynos4412-trats2.dts
@@ -144,7 +144,7 @@
max77693@66 {
compatible = "maxim,max77693";
interrupt-parent = <&gpx1>;
- interrupts = <5 2>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reg = <0x66>;
regulators {
@@ -224,7 +224,7 @@
compatible = "capella,cm36651";
reg = <0x18>;
interrupt-parent = <&gpx0>;
- interrupts = <2 2>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
vled-supply = <&ps_als_reg>;
};
};
@@ -573,7 +573,7 @@
compatible = "melfas,mms114";
reg = <0x48>;
interrupt-parent = <&gpm2>;
- interrupts = <3 2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
x-size = <720>;
y-size = <1280>;
avdd-supply = <&ldo23_reg>;
@@ -611,7 +611,7 @@
max77686: max77686_pmic@09 {
compatible = "maxim,max77686";
interrupt-parent = <&gpx0>;
- interrupts = <7 0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/dts/src/arm/exynos5.dtsi b/dts/src/arm/exynos5.dtsi
index b74c5379ca..66d22521c9 100644
--- a/dts/src/arm/exynos5.dtsi
+++ b/dts/src/arm/exynos5.dtsi
@@ -55,38 +55,38 @@
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
- interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
- <0 1 IRQ_TYPE_LEVEL_HIGH>,
- <0 2 IRQ_TYPE_LEVEL_HIGH>,
- <0 3 IRQ_TYPE_LEVEL_HIGH>,
- <0 4 IRQ_TYPE_LEVEL_HIGH>,
- <0 5 IRQ_TYPE_LEVEL_HIGH>,
- <0 6 IRQ_TYPE_LEVEL_HIGH>,
- <0 7 IRQ_TYPE_LEVEL_HIGH>,
- <0 8 IRQ_TYPE_LEVEL_HIGH>,
- <0 9 IRQ_TYPE_LEVEL_HIGH>,
- <0 10 IRQ_TYPE_LEVEL_HIGH>,
- <0 11 IRQ_TYPE_LEVEL_HIGH>,
- <0 12 IRQ_TYPE_LEVEL_HIGH>,
- <0 13 IRQ_TYPE_LEVEL_HIGH>,
- <0 14 IRQ_TYPE_LEVEL_HIGH>,
- <0 15 IRQ_TYPE_LEVEL_HIGH>,
- <0 16 IRQ_TYPE_LEVEL_HIGH>,
- <0 17 IRQ_TYPE_LEVEL_HIGH>,
- <0 18 IRQ_TYPE_LEVEL_HIGH>,
- <0 19 IRQ_TYPE_LEVEL_HIGH>,
- <0 20 IRQ_TYPE_LEVEL_HIGH>,
- <0 21 IRQ_TYPE_LEVEL_HIGH>,
- <0 22 IRQ_TYPE_LEVEL_HIGH>,
- <0 23 IRQ_TYPE_LEVEL_HIGH>,
- <0 24 IRQ_TYPE_LEVEL_HIGH>,
- <0 25 IRQ_TYPE_LEVEL_HIGH>,
- <0 26 IRQ_TYPE_LEVEL_HIGH>,
- <0 27 IRQ_TYPE_LEVEL_HIGH>,
- <0 28 IRQ_TYPE_LEVEL_HIGH>,
- <0 29 IRQ_TYPE_LEVEL_HIGH>,
- <0 30 IRQ_TYPE_LEVEL_HIGH>,
- <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10481000 {
@@ -109,31 +109,31 @@
serial_0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
};
serial_1: serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
serial_2: serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
};
serial_3: serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
i2c_0: i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -143,7 +143,7 @@
i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -153,7 +153,7 @@
i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
- interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -163,7 +163,7 @@
i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
- interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -180,8 +180,8 @@
rtc: rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
- interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>,
- <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
diff --git a/dts/src/arm/exynos5250-arndale.dts b/dts/src/arm/exynos5250-arndale.dts
index 6098dacd09..6a432460eb 100644
--- a/dts/src/arm/exynos5250-arndale.dts
+++ b/dts/src/arm/exynos5250-arndale.dts
@@ -14,7 +14,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include "exynos5250.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/dts/src/arm/exynos5250-pinctrl.dtsi b/dts/src/arm/exynos5250-pinctrl.dtsi
index 2f6ab32b59..1fd122db18 100644
--- a/dts/src/arm/exynos5250-pinctrl.dtsi
+++ b/dts/src/arm/exynos5250-pinctrl.dtsi
@@ -589,6 +589,13 @@
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
+
+ hdmi_cec: hdmi-cec {
+ samsung,pins = "gpx3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
};
&pinctrl_1 {
diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts
index a97a785ccc..6632f65739 100644
--- a/dts/src/arm/exynos5250-smdk5250.dts
+++ b/dts/src/arm/exynos5250-smdk5250.dts
@@ -13,7 +13,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos5250.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/dts/src/arm/exynos5250-snow-common.dtsi b/dts/src/arm/exynos5250-snow-common.dtsi
index 8f3a804307..e1d293dbbe 100644
--- a/dts/src/arm/exynos5250-snow-common.dtsi
+++ b/dts/src/arm/exynos5250-snow-common.dtsi
@@ -272,6 +272,10 @@
vdd_pll-supply = <&ldo8_reg>;
};
+&hdmicec {
+ status = "okay";
+};
+
&i2c_0 {
status = "okay";
samsung,i2c-sda-delay = <100>;
diff --git a/dts/src/arm/exynos5250-spring.dts b/dts/src/arm/exynos5250-spring.dts
index 4d7bdb735e..95c3bcace9 100644
--- a/dts/src/arm/exynos5250-spring.dts
+++ b/dts/src/arm/exynos5250-spring.dts
@@ -14,7 +14,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include "exynos5250.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Google Spring";
diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi
index 79c9c88561..8dbeb873e9 100644
--- a/dts/src/arm/exynos5250.dtsi
+++ b/dts/src/arm/exynos5250.dtsi
@@ -153,10 +153,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
/*
* Unfortunately we need this since some versions
* of U-Boot on Exynos don't set the CNTFRQ register,
@@ -689,6 +689,19 @@
samsung,syscon-phandle = <&pmu_system_controller>;
};
+ hdmicec: cec@101B0000 {
+ compatible = "samsung,s5p-cec";
+ reg = <0x101B0000 0x200>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_HDMI_CEC>;
+ clock-names = "hdmicec";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ hdmi-phandle = <&hdmi>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "disabled";
+ };
+
mixer@14450000 {
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
diff --git a/dts/src/arm/exynos5420-arndale-octa.dts b/dts/src/arm/exynos5420-arndale-octa.dts
index 9cc83c51c9..ee1bb9b8b3 100644
--- a/dts/src/arm/exynos5420-arndale-octa.dts
+++ b/dts/src/arm/exynos5420-arndale-octa.dts
@@ -16,7 +16,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts
index 1f964ec35c..f9a75bfd3f 100644
--- a/dts/src/arm/exynos5420-peach-pit.dts
+++ b/dts/src/arm/exynos5420-peach-pit.dts
@@ -16,7 +16,6 @@
#include <dt-bindings/regulator/maxim,max77802.h>
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Google Peach Pit Rev 6+";
@@ -604,7 +603,7 @@
max98090: codec@10 {
compatible = "maxim,max98090";
reg = <0x10>;
- interrupts = <2 0>;
+ interrupts = <2 IRQ_TYPE_NONE>;
interrupt-parent = <&gpx0>;
pinctrl-names = "default";
pinctrl-0 = <&max98090_irq>;
@@ -945,7 +944,7 @@
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
interrupt-parent = <&gpx1>;
- interrupts = <5 0>;
+ interrupts = <5 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&ec_spi_cs &ec_irq>;
reg = <0>;
diff --git a/dts/src/arm/exynos5420-pinctrl.dtsi b/dts/src/arm/exynos5420-pinctrl.dtsi
index 3924b4fafe..65aa0e300c 100644
--- a/dts/src/arm/exynos5420-pinctrl.dtsi
+++ b/dts/src/arm/exynos5420-pinctrl.dtsi
@@ -67,6 +67,13 @@
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
+
+ hdmi_cec: hdmi-cec {
+ samsung,pins = "gpx3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
};
&pinctrl_1 {
diff --git a/dts/src/arm/exynos5420-smdk5420.dts b/dts/src/arm/exynos5420-smdk5420.dts
index aaccd0da41..08c8ab173e 100644
--- a/dts/src/arm/exynos5420-smdk5420.dts
+++ b/dts/src/arm/exynos5420-smdk5420.dts
@@ -13,7 +13,6 @@
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Samsung SMDK5420 board based on EXYNOS5420";
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 0db0bcf8da..02d2f898ef 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -193,7 +193,7 @@
mfc: codec@11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
@@ -203,7 +203,7 @@
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
@@ -215,7 +215,7 @@
mmc_1: mmc@12210000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
@@ -227,7 +227,7 @@
mmc_2: mmc@12220000 {
compatible = "samsung,exynos5420-dw-mshc";
- interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -325,37 +325,37 @@
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
- interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl@14000000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl@14010000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
- interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_4: pinctrl@03860000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
amba {
@@ -368,7 +368,7 @@
adma: adma@03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
- interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -379,7 +379,7 @@
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -390,7 +390,7 @@
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -401,7 +401,7 @@
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -412,7 +412,7 @@
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -484,7 +484,7 @@
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -500,7 +500,7 @@
spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -516,7 +516,7 @@
spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -544,7 +544,7 @@
dsi@14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
- interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
@@ -557,7 +557,7 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -569,7 +569,7 @@
hsi2c_8: i2c@12E00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -582,7 +582,7 @@
hsi2c_9: i2c@12E10000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
- interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -595,7 +595,7 @@
hsi2c_10: i2c@12E20000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
- interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -608,7 +608,7 @@
hdmi: hdmi@14530000 {
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -624,10 +624,23 @@
reg = <0x145D0000 0x20>;
};
+ hdmicec: cec@101B0000 {
+ compatible = "samsung,s5p-cec";
+ reg = <0x101B0000 0x200>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_HDMI_CEC>;
+ clock-names = "hdmicec";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ hdmi-phandle = <&hdmi>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "disabled";
+ };
+
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -638,7 +651,7 @@
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -647,7 +660,7 @@
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -657,7 +670,7 @@
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -667,7 +680,7 @@
jpeg_0: jpeg@11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
@@ -676,7 +689,7 @@
jpeg_1: jpeg@11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
- interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
@@ -696,7 +709,7 @@
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
@@ -705,7 +718,7 @@
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
@@ -714,7 +727,7 @@
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
- interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
@@ -723,7 +736,7 @@
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
- interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
@@ -732,7 +745,7 @@
tmu_gpu: tmu@100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
- interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos5420-tmu-sensor-conf.dtsi"
@@ -804,7 +817,7 @@
sysmmu_scaler1r: sysmmu@0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
- interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
@@ -813,7 +826,7 @@
sysmmu_scaler2r: sysmmu@0x128A0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
- interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
@@ -872,7 +885,7 @@
sysmmu_jpeg1: sysmmu@0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
- interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
diff --git a/dts/src/arm/exynos5422-odroidxu3-audio.dtsi b/dts/src/arm/exynos5422-odroidxu3-audio.dtsi
index 9493923ec6..c0b85981c6 100644
--- a/dts/src/arm/exynos5422-odroidxu3-audio.dtsi
+++ b/dts/src/arm/exynos5422-odroidxu3-audio.dtsi
@@ -49,7 +49,7 @@
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpx3>;
- interrupts = <2 0>;
+ interrupts = <2 IRQ_TYPE_NONE>;
clocks = <&i2s0 CLK_I2S_CDCLK>;
clock-names = "mclk";
#sound-dai-cells = <0>;
diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
index 05b9afdd67..f92f957412 100644
--- a/dts/src/arm/exynos5422-odroidxu3-common.dtsi
+++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
@@ -18,7 +18,6 @@
#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5800.dtsi"
#include "exynos5422-cpus.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
memory@40000000 {
@@ -265,6 +264,10 @@
vdd-supply = <&ldo6_reg>;
};
+&hdmicec {
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
diff --git a/dts/src/arm/exynos5440.dtsi b/dts/src/arm/exynos5440.dtsi
index a4ea018464..bc4954e69f 100644
--- a/dts/src/arm/exynos5440.dtsi
+++ b/dts/src/arm/exynos5440.dtsi
@@ -200,7 +200,7 @@
compatible = "snps,dwmac-3.70a", "snps,dwmac";
reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 31 4>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
phy-mode = "sgmii";
clocks = <&clock CLK_GMAC0>;
diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts
index f9ff7f07ae..953dc8677d 100644
--- a/dts/src/arm/exynos5800-peach-pi.dts
+++ b/dts/src/arm/exynos5800-peach-pi.dts
@@ -16,7 +16,6 @@
#include <dt-bindings/regulator/maxim,max77802.h>
#include "exynos5800.dtsi"
#include "exynos5420-cpus.dtsi"
-#include "exynos-mfc-reserved-memory.dtsi"
/ {
model = "Google Peach Pi Rev 10+";
@@ -604,7 +603,7 @@
max98091: codec@10 {
compatible = "maxim,max98091";
reg = <0x10>;
- interrupts = <2 0>;
+ interrupts = <2 IRQ_TYPE_NONE>;
interrupt-parent = <&gpx0>;
pinctrl-names = "default";
pinctrl-0 = <&max98091_irq>;
@@ -914,7 +913,7 @@
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
interrupt-parent = <&gpx1>;
- interrupts = <5 0>;
+ interrupts = <5 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&ec_spi_cs &ec_irq>;
reg = <0>;
diff --git a/dts/src/arm/ge863-pro3.dtsi b/dts/src/arm/ge863-pro3.dtsi
index 4aee5cc75f..8613944ea5 100644
--- a/dts/src/arm/ge863-pro3.dtsi
+++ b/dts/src/arm/ge863-pro3.dtsi
@@ -23,20 +23,39 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- boot@0 {
- label = "boot";
- reg = <0x0 0x7c0000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "boot";
+ reg = <0x0 0x7c0000>;
+ };
- root@07c0000 {
- label = "root";
- reg = <0x7c0000 0x7840000>;
+ root@07c0000 {
+ label = "root";
+ reg = <0x7c0000 0x7840000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/gemini-nas4220b.dts b/dts/src/arm/gemini-nas4220b.dts
index 7668ba5215..55f6a4f1f8 100644
--- a/dts/src/arm/gemini-nas4220b.dts
+++ b/dts/src/arm/gemini-nas4220b.dts
@@ -98,5 +98,15 @@
read-only;
};
};
+
+ sata: sata@46000000 {
+ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+ };
+
+ ata@63000000 {
+ status = "okay";
+ };
};
};
diff --git a/dts/src/arm/gemini-sq201.dts b/dts/src/arm/gemini-sq201.dts
index 46309e79cc..4d200f0bcd 100644
--- a/dts/src/arm/gemini-sq201.dts
+++ b/dts/src/arm/gemini-sq201.dts
@@ -93,6 +93,12 @@
};
};
+ sata: sata@46000000 {
+ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+ };
+
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
@@ -114,5 +120,9 @@
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
};
+
+ ata@63000000 {
+ status = "okay";
+ };
};
};
diff --git a/dts/src/arm/gemini.dtsi b/dts/src/arm/gemini.dtsi
index b8d011bdcc..141d8d3a1d 100644
--- a/dts/src/arm/gemini.dtsi
+++ b/dts/src/arm/gemini.dtsi
@@ -25,8 +25,11 @@
};
syscon: syscon@40000000 {
- compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
+ compatible = "cortina,gemini-syscon",
+ "syscon", "simple-mfd";
reg = <0x40000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
syscon-reboot {
compatible = "syscon-reboot";
@@ -42,23 +45,30 @@
compatible = "cortina,gemini-watchdog";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon 23>;
+ clocks = <&syscon 2>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
- clock-frequency = <48000000>;
+ resets = <&syscon 18>;
+ clocks = <&syscon 6>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
};
timer@43000000 {
- compatible = "cortina,gemini-timer";
+ compatible = "faraday,fttmr010";
reg = <0x43000000 0x1000>;
interrupt-parent = <&intcon>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
+ resets = <&syscon 17>;
+ /* APB clock or RTC clock */
+ clocks = <&syscon 2>, <&syscon 0>;
+ clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
@@ -66,11 +76,28 @@
compatible = "cortina,gemini-rtc";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon 16>;
+ clocks = <&syscon 2>, <&syscon 0>;
+ clock-names = "PCLK", "EXTCLK";
+ };
+
+ sata: sata@46000000 {
+ compatible = "cortina,gemini-sata-bridge";
+ reg = <0x46000000 0x100>;
+ resets = <&syscon 26>,
+ <&syscon 27>;
+ reset-names = "sata0", "sata1";
+ clocks = <&syscon 10>,
+ <&syscon 11>;
+ clock-names = "SATA0_PCLK", "SATA1_PCLK";
+ syscon = <&syscon>;
+ status = "disabled";
};
intcon: interrupt-controller@48000000 {
compatible = "faraday,ftintc010";
reg = <0x48000000 0x1000>;
+ resets = <&syscon 14>;
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -85,6 +112,8 @@
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4d000000 0x100>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon 20>;
+ clocks = <&syscon 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -95,6 +124,8 @@
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4e000000 0x100>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon 21>;
+ clocks = <&syscon 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -105,6 +136,8 @@
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
reg = <0x4f000000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon 22>;
+ clocks = <&syscon 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -118,6 +151,9 @@
* to configure the host bridge.
*/
reg = <0x50000000 0x100>;
+ resets = <&syscon 7>;
+ clocks = <&syscon 15>, <&syscon 4>;
+ clock-names = "PCLK", "PCICLK";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -152,5 +188,44 @@
#interrupt-cells = <1>;
};
};
+
+ ata@63000000 {
+ compatible = "cortina,gemini-pata", "faraday,ftide010";
+ reg = <0x63000000 0x1000>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon 2>;
+ clocks = <&syscon 14>;
+ clock-names = "PCLK";
+ sata = <&sata>;
+ status = "disabled";
+ };
+
+ ata@63400000 {
+ compatible = "cortina,gemini-pata", "faraday,ftide010";
+ reg = <0x63400000 0x1000>;
+ interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon 2>;
+ clocks = <&syscon 14>;
+ clock-names = "PCLK";
+ sata = <&sata>;
+ status = "disabled";
+ };
+
+ dma-controller@67000000 {
+ compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
+ /* Faraday Technology FTDMAC020 variant */
+ arm,primecell-periphid = <0x0003b080>;
+ reg = <0x67000000 0x1000>;
+ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon 10>;
+ clocks = <&syscon 1>;
+ clock-names = "apb_pclk";
+ /* Bus interface AHB1 (AHB0) is totally tilted */
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
};
};
diff --git a/dts/src/arm/imx23-sansa.dts b/dts/src/arm/imx23-sansa.dts
index 4ec32f4c78..221fd55e96 100644
--- a/dts/src/arm/imx23-sansa.dts
+++ b/dts/src/arm/imx23-sansa.dts
@@ -42,6 +42,7 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"
/ {
@@ -149,9 +150,8 @@
regulator-name = "vdd-touchpad0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio0 26 0>;
+ gpio = <&gpio0 26 GPIO_ACTIVE_LOW>;
regulator-always-on;
- enable-active-low;
};
reg_vdd_tuner: regulator-vdd-tuner0 {
@@ -159,9 +159,8 @@
regulator-name = "vdd-tuner0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio0 29 0>;
+ gpio = <&gpio0 29 GPIO_ACTIVE_LOW>;
regulator-always-on;
- enable-active-low;
};
backlight {
diff --git a/dts/src/arm/imx25-karo-tx25.dts b/dts/src/arm/imx25-karo-tx25.dts
index 9b31faa963..30a62d4be8 100644
--- a/dts/src/arm/imx25-karo-tx25.dts
+++ b/dts/src/arm/imx25-karo-tx25.dts
@@ -97,7 +97,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
- phy-reset-gpios = <&gpio3 7 0>;
+ phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
phy-mode = "rmii";
phy-supply = <&reg_fec_phy>;
status = "okay";
diff --git a/dts/src/arm/imx25-pdk.dts b/dts/src/arm/imx25-pdk.dts
index d921dd2ed6..c52692821f 100644
--- a/dts/src/arm/imx25-pdk.dts
+++ b/dts/src/arm/imx25-pdk.dts
@@ -125,7 +125,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-supply = <&reg_fec_3v3>;
- phy-reset-gpios = <&gpio4 8 0>;
+ phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi
index 0cdf333336..dfcc8e00cf 100644
--- a/dts/src/arm/imx25.dtsi
+++ b/dts/src/arm/imx25.dtsi
@@ -9,6 +9,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <dt-bindings/gpio/gpio.h>
#include "imx25-pinfunc.h"
/ {
diff --git a/dts/src/arm/imx27-phytec-phycard-s-som.dtsi b/dts/src/arm/imx27-phytec-phycard-s-som.dtsi
index 4f3e0f4735..0b8490b21a 100644
--- a/dts/src/arm/imx27-phytec-phycard-s-som.dtsi
+++ b/dts/src/arm/imx27-phytec-phycard-s-som.dtsi
@@ -40,7 +40,7 @@
status = "okay";
at24@52 {
- compatible = "at,24c32";
+ compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
};
diff --git a/dts/src/arm/imx27-phytec-phycore-som.dtsi b/dts/src/arm/imx27-phytec-phycore-som.dtsi
index 82fec935ce..c973c5d918 100644
--- a/dts/src/arm/imx27-phytec-phycore-som.dtsi
+++ b/dts/src/arm/imx27-phytec-phycore-som.dtsi
@@ -193,7 +193,7 @@
status = "okay";
at24@52 {
- compatible = "at,24c32";
+ compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
};
diff --git a/dts/src/arm/imx28-cfa10037.dts b/dts/src/arm/imx28-cfa10037.dts
index e5beaa58bb..3d13b321d2 100644
--- a/dts/src/arm/imx28-cfa10037.dts
+++ b/dts/src/arm/imx28-cfa10037.dts
@@ -64,7 +64,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a
&mac0_pins_cfa10037>;
- phy-reset-gpios = <&gpio2 21 0>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-cfa10049.dts b/dts/src/arm/imx28-cfa10049.dts
index a9c347e48b..4cd52d53cf 100644
--- a/dts/src/arm/imx28-cfa10049.dts
+++ b/dts/src/arm/imx28-cfa10049.dts
@@ -327,7 +327,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a
&mac0_pins_cfa10049>;
- phy-reset-gpios = <&gpio2 21 0>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-cfa10057.dts b/dts/src/arm/imx28-cfa10057.dts
index 7a80bd686c..c6067915b2 100644
--- a/dts/src/arm/imx28-cfa10057.dts
+++ b/dts/src/arm/imx28-cfa10057.dts
@@ -162,7 +162,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio2 21 0>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-cfa10058.dts b/dts/src/arm/imx28-cfa10058.dts
index f5c6dce34a..70c7bb4a5a 100644
--- a/dts/src/arm/imx28-cfa10058.dts
+++ b/dts/src/arm/imx28-cfa10058.dts
@@ -129,7 +129,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio2 21 0>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-eukrea-mbmx287lc.dts b/dts/src/arm/imx28-eukrea-mbmx287lc.dts
index e773144e1e..b61fd61eb1 100644
--- a/dts/src/arm/imx28-eukrea-mbmx287lc.dts
+++ b/dts/src/arm/imx28-eukrea-mbmx287lc.dts
@@ -31,7 +31,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
- phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-evk.dts b/dts/src/arm/imx28-evk.dts
index a5ba669b4e..5309bb90d7 100644
--- a/dts/src/arm/imx28-evk.dts
+++ b/dts/src/arm/imx28-evk.dts
@@ -203,7 +203,7 @@
};
at24@51 {
- compatible = "at24,24c32";
+ compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
};
@@ -262,7 +262,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_fec_3v3>;
- phy-reset-gpios = <&gpio4 13 0>;
+ phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx28-m28cu3.dts b/dts/src/arm/imx28-m28cu3.dts
index bb5329479c..9d6c8fe28d 100644
--- a/dts/src/arm/imx28-m28cu3.dts
+++ b/dts/src/arm/imx28-m28cu3.dts
@@ -188,7 +188,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio4 13 0>;
+ phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};
diff --git a/dts/src/arm/imx50-evk.dts b/dts/src/arm/imx50-evk.dts
index dba2d951aa..98b5faa06e 100644
--- a/dts/src/arm/imx50-evk.dts
+++ b/dts/src/arm/imx50-evk.dts
@@ -53,7 +53,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio4 12 0>;
+ phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx50.dtsi b/dts/src/arm/imx50.dtsi
index 2a98afcd8a..3747d80104 100644
--- a/dts/src/arm/imx50.dtsi
+++ b/dts/src/arm/imx50.dtsi
@@ -12,6 +12,7 @@
*/
#include "imx50-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx5-clock.h>
/ {
diff --git a/dts/src/arm/imx51-apf51.dts b/dts/src/arm/imx51-apf51.dts
index e88b2a6be0..c83ac16003 100644
--- a/dts/src/arm/imx51-apf51.dts
+++ b/dts/src/arm/imx51-apf51.dts
@@ -36,7 +36,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
- phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
diff --git a/dts/src/arm/imx53-mba53.dts b/dts/src/arm/imx53-mba53.dts
index 2e44d2aba1..df705ba488 100644
--- a/dts/src/arm/imx53-mba53.dts
+++ b/dts/src/arm/imx53-mba53.dts
@@ -195,7 +195,7 @@
};
&fec {
- phy-reset-gpios = <&gpio7 6 0>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx53-qsb-common.dtsi b/dts/src/arm/imx53-qsb-common.dtsi
index 40b3e31935..683dcbe27c 100644
--- a/dts/src/arm/imx53-qsb-common.dtsi
+++ b/dts/src/arm/imx53-qsb-common.dtsi
@@ -344,7 +344,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 0>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx53-smd.dts b/dts/src/arm/imx53-smd.dts
index 472f6f0f55..33cb64fc83 100644
--- a/dts/src/arm/imx53-smd.dts
+++ b/dts/src/arm/imx53-smd.dts
@@ -273,6 +273,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 0>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx53-tqma53.dtsi b/dts/src/arm/imx53-tqma53.dtsi
index 85972f2201..eecdc1c55e 100644
--- a/dts/src/arm/imx53-tqma53.dtsi
+++ b/dts/src/arm/imx53-tqma53.dtsi
@@ -272,7 +272,7 @@
};
eeprom: 24c64@50 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x50>;
};
diff --git a/dts/src/arm/imx53-tx53.dtsi b/dts/src/arm/imx53-tx53.dtsi
index 3a32201419..7807c1fa11 100644
--- a/dts/src/arm/imx53-tx53.dtsi
+++ b/dts/src/arm/imx53-tx53.dtsi
@@ -201,7 +201,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-handle = <&phy0>;
mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
status = "okay";
diff --git a/dts/src/arm/imx53-voipac-dmm-668.dtsi b/dts/src/arm/imx53-voipac-dmm-668.dtsi
index 524192cf6a..df8dafe256 100644
--- a/dts/src/arm/imx53-voipac-dmm-668.dtsi
+++ b/dts/src/arm/imx53-voipac-dmm-668.dtsi
@@ -137,7 +137,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio4 2 0>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6dl-gw560x.dts b/dts/src/arm/imx6dl-gw560x.dts
new file mode 100644
index 0000000000..21bdfaf8df
--- /dev/null
+++ b/dts/src/arm/imx6dl-gw560x.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw560x.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X";
+ compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/dts/src/arm/imx6dl-riotboard.dts b/dts/src/arm/imx6dl-riotboard.dts
index 2cb72824e8..29b45f2e64 100644
--- a/dts/src/arm/imx6dl-riotboard.dts
+++ b/dts/src/arm/imx6dl-riotboard.dts
@@ -94,7 +94,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio3 31 0>;
+ phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/dts/src/arm/imx6dl-sabrelite.dts b/dts/src/arm/imx6dl-sabrelite.dts
index 2f904527a0..33040761b2 100644
--- a/dts/src/arm/imx6dl-sabrelite.dts
+++ b/dts/src/arm/imx6dl-sabrelite.dts
@@ -48,3 +48,8 @@
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/dts/src/arm/imx6dl-sabresd.dts b/dts/src/arm/imx6dl-sabresd.dts
index 1e45f2f9d0..9607afe088 100644
--- a/dts/src/arm/imx6dl-sabresd.dts
+++ b/dts/src/arm/imx6dl-sabresd.dts
@@ -15,3 +15,8 @@
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi
index 7aa120fbdc..8475e6cc59 100644
--- a/dts/src/arm/imx6dl.dtsi
+++ b/dts/src/arm/imx6dl.dtsi
@@ -100,6 +100,11 @@
};
};
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu1_csi0>, <&ipu1_csi1>;
+ };
+
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
@@ -164,6 +169,116 @@
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
};
+&gpr {
+ ipu1_csi0_mux: ipu1_csi0_mux@34 {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ipu1_csi0_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu1_csi1_mux: ipu1_csi1_mux@34 {
+ compatible = "video-mux";
+ mux-controls = <&mux 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi1_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi1_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi1_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ipu1_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ipu1_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+ };
+ };
+ };
+};
+
&gpt {
compatible = "fsl,imx6dl-gpt";
};
@@ -172,6 +287,12 @@
compatible = "fsl,imx6dl-hdmi";
};
+&ipu1_csi1 {
+ ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -181,6 +302,74 @@
"di0", "di1";
};
+&mipi_csi {
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+
+ mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+ };
+
+ mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+ };
+
+ mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+ };
+
+ mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
+&mux {
+ mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
+ <0x34 0x00000038>, /* IPU_CSI1_MUX */
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
diff --git a/dts/src/arm/imx6q-ba16.dtsi b/dts/src/arm/imx6q-ba16.dtsi
index 14fa6b25dc..5fcb0372d5 100644
--- a/dts/src/arm/imx6q-ba16.dtsi
+++ b/dts/src/arm/imx6q-ba16.dtsi
@@ -321,7 +321,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
fsl,tx-swing-full = <103>;
fsl,tx-swing-low = <103>;
status = "okay";
diff --git a/dts/src/arm/imx6q-cm-fx6.dts b/dts/src/arm/imx6q-cm-fx6.dts
index 66cac5328b..fe6ab0aa34 100644
--- a/dts/src/arm/imx6q-cm-fx6.dts
+++ b/dts/src/arm/imx6q-cm-fx6.dts
@@ -64,6 +64,14 @@
};
};
+ awnh387_pwrseq: pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwrseq>;
+ compatible = "mmc-pwrseq-sd8787";
+ powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ };
+
reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
compatible = "regulator-fixed";
regulator-name = "regulator-pcie-power-on-gpio";
@@ -215,7 +223,7 @@
clock-frequency = <100000>;
eeprom@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
@@ -304,6 +312,13 @@
>;
};
+ pinctrl_pwrseq: pwrseqgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
@@ -330,6 +345,17 @@
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
>;
};
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
};
&pcie {
@@ -382,3 +408,18 @@
dr_mode = "otg";
status = "okay";
};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ mmc-pwrseq = <&awnh387_pwrseq>;
+ non-removable;
+ /*
+ * If the OS probes the Bluetooth AMP function advertised on this bus
+ * but the firmware in place does not support it, the WiFi/BT module
+ * gets unresponsive.
+ * Users who configured their OS properly can enable this node to gain
+ * WiFi and/or plain Bluetooth support.
+ */
+ status = "disabled";
+};
diff --git a/dts/src/arm/imx6q-dmo-edmqmx6.dts b/dts/src/arm/imx6q-dmo-edmqmx6.dts
index f28883bbe7..33eb7f1809 100644
--- a/dts/src/arm/imx6q-dmo-edmqmx6.dts
+++ b/dts/src/arm/imx6q-dmo-edmqmx6.dts
@@ -118,7 +118,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 0>;
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen2_1v2_eth>;
status = "okay";
};
@@ -435,7 +435,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 8 0>;
+ reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6q-evi.dts b/dts/src/arm/imx6q-evi.dts
index fd2220aa49..1f0f950dc1 100644
--- a/dts/src/arm/imx6q-evi.dts
+++ b/dts/src/arm/imx6q-evi.dts
@@ -135,7 +135,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 0>;
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/dts/src/arm/imx6q-gw5400-a.dts b/dts/src/arm/imx6q-gw5400-a.dts
index 8e84713f42..9dbeea05a9 100644
--- a/dts/src/arm/imx6q-gw5400-a.dts
+++ b/dts/src/arm/imx6q-gw5400-a.dts
@@ -19,7 +19,6 @@
/* these are used by bootloader for disabling nodes */
aliases {
- ethernet1 = &eth1;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
@@ -154,7 +153,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -347,10 +346,6 @@
&pcie {
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
-
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
- compatible = "marvell,sky2";
- };
};
&ssi1 {
diff --git a/dts/src/arm/imx6q-gw560x.dts b/dts/src/arm/imx6q-gw560x.dts
new file mode 100644
index 0000000000..735f2bbf14
--- /dev/null
+++ b/dts/src/arm/imx6q-gw560x.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw560x.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW560X";
+ compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6q-novena.dts b/dts/src/arm/imx6q-novena.dts
index 0fa32b2f3a..d83cfb6ec5 100644
--- a/dts/src/arm/imx6q-novena.dts
+++ b/dts/src/arm/imx6q-novena.dts
@@ -217,7 +217,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_novena>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
@@ -446,7 +446,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_novena>;
- reset-gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6q-sabrelite.dts b/dts/src/arm/imx6q-sabrelite.dts
index 02a7cdfd57..dc51262e7b 100644
--- a/dts/src/arm/imx6q-sabrelite.dts
+++ b/dts/src/arm/imx6q-sabrelite.dts
@@ -52,3 +52,8 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/dts/src/arm/imx6q-sabresd.dts b/dts/src/arm/imx6q-sabresd.dts
index 9cbdfe7a09..527772b62f 100644
--- a/dts/src/arm/imx6q-sabresd.dts
+++ b/dts/src/arm/imx6q-sabresd.dts
@@ -23,3 +23,8 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/dts/src/arm/imx6q-utilite-pro.dts b/dts/src/arm/imx6q-utilite-pro.dts
index d900ad6ec5..16d5be1aeb 100644
--- a/dts/src/arm/imx6q-utilite-pro.dts
+++ b/dts/src/arm/imx6q-utilite-pro.dts
@@ -130,7 +130,7 @@
#size-cells = <0>;
eeprom@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
diff --git a/dts/src/arm/imx6q-zii-rdu2.dts b/dts/src/arm/imx6q-zii-rdu2.dts
index b2d346640f..6be8a1eea8 100644
--- a/dts/src/arm/imx6q-zii-rdu2.dts
+++ b/dts/src/arm/imx6q-zii-rdu2.dts
@@ -41,8 +41,8 @@
/dts-v1/;
-#include <imx6q.dtsi>
-#include <imx6qdl-zii-rdu2.dtsi>
+#include "imx6q.dtsi"
+#include "imx6qdl-zii-rdu2.dtsi"
/ {
model = "ZII RDU2 Board";
diff --git a/dts/src/arm/imx6q.dtsi b/dts/src/arm/imx6q.dtsi
index e9a5d0b8c7..90a741732f 100644
--- a/dts/src/arm/imx6q.dtsi
+++ b/dts/src/arm/imx6q.dtsi
@@ -125,7 +125,7 @@
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
ipu2: ipu@02800000 {
@@ -143,10 +143,18 @@
ipu2_csi0: port@0 {
reg = <0>;
+
+ ipu2_csi0_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+ };
};
ipu2_csi1: port@1 {
reg = <1>;
+
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+ };
};
ipu2_di0: port@2 {
@@ -198,6 +206,11 @@
};
};
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
+ };
+
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
@@ -246,6 +259,68 @@
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};
+&gpr {
+ ipu1_csi0_mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu2_csi1_mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu2_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu2_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+ };
+ };
+ };
+};
+
&hdmi {
compatible = "fsl,imx6q-hdmi";
@@ -266,6 +341,12 @@
};
};
+&ipu1_csi1 {
+ ipu1_csi1_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -312,6 +393,40 @@
};
};
+&mipi_csi {
+ port@1 {
+ reg = <1>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mipi_vc1_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ mipi_vc2_to_ipu2_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ mipi_vc3_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
&mipi_dsi {
ports {
port@2 {
@@ -332,6 +447,16 @@
};
};
+&mux {
+ mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
+ <0x04 0x00100000>, /* MIPI_IPU2_MUX */
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
diff --git a/dts/src/arm/imx6qdl-apf6dev.dtsi b/dts/src/arm/imx6qdl-apf6dev.dtsi
index 550e100e85..9cd2a7477e 100644
--- a/dts/src/arm/imx6qdl-apf6dev.dtsi
+++ b/dts/src/arm/imx6qdl-apf6dev.dtsi
@@ -232,7 +232,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-aristainetos.dtsi b/dts/src/arm/imx6qdl-aristainetos.dtsi
index b2debc0aa7..7d64075204 100644
--- a/dts/src/arm/imx6qdl-aristainetos.dtsi
+++ b/dts/src/arm/imx6qdl-aristainetos.dtsi
@@ -118,7 +118,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-aristainetos2.dtsi b/dts/src/arm/imx6qdl-aristainetos2.dtsi
index ec68f1cace..1b18728732 100644
--- a/dts/src/arm/imx6qdl-aristainetos2.dtsi
+++ b/dts/src/arm/imx6qdl-aristainetos2.dtsi
@@ -320,7 +320,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
@@ -335,7 +335,7 @@
};
&pcie {
- reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-colibri.dtsi b/dts/src/arm/imx6qdl-colibri.dtsi
index e8078758f2..ad84eddb68 100644
--- a/dts/src/arm/imx6qdl-colibri.dtsi
+++ b/dts/src/arm/imx6qdl-colibri.dtsi
@@ -254,6 +254,7 @@
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
+ lrclk-strength = <3>;
};
/* STMPE811 touch screen controller */
diff --git a/dts/src/arm/imx6qdl-gw53xx.dtsi b/dts/src/arm/imx6qdl-gw53xx.dtsi
index a208e7e0dc..5bc6ed1a5b 100644
--- a/dts/src/arm/imx6qdl-gw53xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw53xx.dtsi
@@ -14,7 +14,6 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
- ethernet1 = &eth1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@@ -342,10 +341,6 @@
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
-
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
- compatible = "marvell,sky2";
- };
};
&pwm2 {
diff --git a/dts/src/arm/imx6qdl-gw54xx.dtsi b/dts/src/arm/imx6qdl-gw54xx.dtsi
index 968fda94d1..66fcf838e9 100644
--- a/dts/src/arm/imx6qdl-gw54xx.dtsi
+++ b/dts/src/arm/imx6qdl-gw54xx.dtsi
@@ -14,7 +14,6 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
- ethernet1 = &eth1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@@ -379,10 +378,6 @@
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
-
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
- compatible = "marvell,sky2";
- };
};
&pwm1 {
diff --git a/dts/src/arm/imx6qdl-gw560x.dtsi b/dts/src/arm/imx6qdl-gw560x.dtsi
new file mode 100644
index 0000000000..d894dde6e8
--- /dev/null
+++ b/dts/src/arm/imx6qdl-gw560x.dtsi
@@ -0,0 +1,749 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ ssi0 = &ssi1;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight-display {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100
+ >;
+ default-brightness-level = <100>;
+ };
+
+ backlight-keypad {
+ compatible = "gpio-backlight";
+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ default-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_12p0v: regulator-12p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "12P0V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_1p4v: regulator-vddsoc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_soc";
+ regulator-min-microvolt = <1400000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ventana-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "sgtl5000-audio";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom1: eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom2: eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom3: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom4: eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ pca9555: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ds1672: rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ VDDA-supply = <&reg_1p8v>;
+ VDDIO-supply = <&reg_3p3v>;
+ };
+
+ tca8418: keypad@34 {
+ compatible = "ti,tca8418";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_keypad>;
+ reg = <0x34>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
+ MATRIX_KEY(0x00, 0x00, BTN_1)
+ MATRIX_KEY(0x01, 0x01, BTN_2)
+ MATRIX_KEY(0x01, 0x00, BTN_3)
+ MATRIX_KEY(0x02, 0x00, BTN_4)
+ MATRIX_KEY(0x00, 0x03, BTN_5)
+ MATRIX_KEY(0x00, 0x02, BTN_6)
+ MATRIX_KEY(0x01, 0x03, BTN_7)
+ MATRIX_KEY(0x01, 0x02, BTN_8)
+ MATRIX_KEY(0x02, 0x02, BTN_9)
+ >;
+ keypad,num-rows = <4>;
+ keypad,num-columns = <4>;
+ };
+
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x3c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+ /* VDD_DDR (1+R1/R2 = 2.105) */
+ reg_vdd_ddr: sw2 {
+ regulator-name = "vddddr";
+ regulator-min-microvolt = <868310>;
+ regulator-max-microvolt = <1684000>;
+ lltc,fb-voltage-divider = <221000 200000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* VDD_ARM (1+R1/R2 = 1.931) */
+ reg_vdd_arm: sw3 {
+ regulator-name = "vddarm";
+ regulator-min-microvolt = <796551>;
+ regulator-max-microvolt = <1544827>;
+ lltc,fb-voltage-divider = <243000 261000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ linux,phandle = <&reg_vdd_arm>;
+ };
+
+ /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
+ reg_1p8v: sw4 {
+ regulator-name = "vdd1p8";
+ regulator-min-microvolt = <1033310>;
+ regulator-max-microvolt = <2004000>;
+ lltc,fb-voltage-divider = <301000 200000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
+ reg_1p0v: ldo2 {
+ regulator-name = "vdd1p0";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1050000>;
+ lltc,fb-voltage-divider = <78700 200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* VDD_AUD_1P8: Audio codec */
+ reg_aud_1p8v: ldo3 {
+ regulator-name = "vdd1p8a";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ /* VDD_HIGH (1+R1/R2 = 4.17) */
+ reg_3p0v: ldo4 {
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <3023250>;
+ regulator-max-microvolt = <3023250>;
+ lltc,fb-voltage-divider = <634000 200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ egalax_ts: touchscreen@4 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ldb {
+ fsl,dual-channel;
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: hsd100pxn1 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <220>;
+ hfront-porch = <40>;
+ vback-porch = <21>;
+ vfront-porch = <7>;
+ hsync-len = <60>;
+ vsync-len = <10>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ vmmc-supply = <&reg_3p3v>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ /* AUD4 */
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
+ /* AUD6 */
+ MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
+ MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
+ MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
+ MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
+ >;
+ };
+
+ pinctrl_ecspi3: escpi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
+ >;
+ };
+
+ pinctrl_flexcan: flexcangrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
+ >;
+ };
+
+ pinctrl_keypad: keypadgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/dts/src/arm/imx6qdl-microsom-ar8035.dtsi b/dts/src/arm/imx6qdl-microsom-ar8035.dtsi
index a9b207751a..900e8c781f 100644
--- a/dts/src/arm/imx6qdl-microsom-ar8035.dtsi
+++ b/dts/src/arm/imx6qdl-microsom-ar8035.dtsi
@@ -46,7 +46,7 @@
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-mode = "rgmii";
phy-reset-duration = <2>;
- phy-reset-gpios = <&gpio4 15 0>;
+ phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
index bad3c9f9ee..b63134e3b5 100644
--- a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi
@@ -408,7 +408,7 @@
};
rtc: rtc@68 {
- compatible = "st,rv4162";
+ compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv4162>;
reg = <0x68>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
index 559da17297..aeaa5a6e4f 100644
--- a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi
@@ -326,7 +326,7 @@
};
rtc@68 {
- compatible = "st,rv4162";
+ compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv4162>;
reg = <0x68>;
diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
index 70772ebadd..f22e587934 100644
--- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi
+++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi
@@ -271,7 +271,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 27 0>;
+ phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
diff --git a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
index 6e5cb6a995..d81b0078a1 100644
--- a/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
+++ b/dts/src/arm/imx6qdl-phytec-pfla02.dtsi
@@ -374,7 +374,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 17 0>;
+ reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/dts/src/arm/imx6qdl-sabreauto.dtsi b/dts/src/arm/imx6qdl-sabreauto.dtsi
index a2a714d199..6a7594e5d1 100644
--- a/dts/src/arm/imx6qdl-sabreauto.dtsi
+++ b/dts/src/arm/imx6qdl-sabreauto.dtsi
@@ -108,6 +108,76 @@
default-brightness-level = <7>;
status = "okay";
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3mux>;
+ mux-gpios = <&gpio5 4 0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ adv7180: camera@21 {
+ compatible = "adi,adv7180";
+ reg = <0x21>;
+ powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ port {
+ adv7180_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
+
+ max7310_a: gpio@30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio@32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7310>;
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+
+ max7310_c: gpio@34 {
+ compatible = "maxim,max7310";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&clks {
@@ -290,27 +360,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
-
- max7310_a: gpio@30 {
- compatible = "maxim,max7310";
- reg = <0x30>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_b: gpio@32 {
- compatible = "maxim,max7310";
- reg = <0x32>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_c: gpio@34 {
- compatible = "maxim,max7310";
- reg = <0x34>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
&iomuxc {
@@ -418,12 +467,52 @@
>;
};
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
+ pinctrl_max7310: max7310grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
+ pinctrl_gpt_input_capture0: gptinputcapture0grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpt_input_capture1: gptinputcapture1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi
index 84131794e9..afe7449c47 100644
--- a/dts/src/arm/imx6qdl-sabrelite.dtsi
+++ b/dts/src/arm/imx6qdl-sabrelite.dtsi
@@ -39,6 +39,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -94,6 +96,42 @@
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
+
+ reg_1p5v: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_2p8v: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "2P8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+ };
+
+ mipi_xclk: mipi_xclk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ clock-output-names = "mipi_pwm3";
+ pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
+ status = "okay";
};
gpio-keys {
@@ -220,6 +258,22 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -270,9 +324,6 @@
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
- fsl,err006687-workaround-present;
status = "okay";
};
@@ -301,6 +352,53 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ ov5640: camera@40 {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x40>;
+ clocks = <&mipi_xclk>;
+ clock-names = "xclk";
+ DOVDD-supply = <&reg_1p8v>;
+ AVDD-supply = <&reg_2p8v>;
+ DVDD-supply = <&reg_1p5v>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
+ powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ ov5642: camera@42 {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "xclk";
+ reg = <0x42>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
};
&i2c3 {
@@ -373,7 +471,6 @@
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -415,6 +512,23 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
+ >;
+ };
+
pinctrl_j15: j15grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
@@ -448,6 +562,22 @@
>;
};
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0
+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@@ -602,3 +732,17 @@
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
+
+&mipi_csi {
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi2_in: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+};
diff --git a/dts/src/arm/imx6qdl-sabresd.dtsi b/dts/src/arm/imx6qdl-sabresd.dtsi
index 58055ceec6..b72b6fa475 100644
--- a/dts/src/arm/imx6qdl-sabresd.dtsi
+++ b/dts/src/arm/imx6qdl-sabresd.dtsi
@@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -146,6 +147,36 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi2_in: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -178,7 +209,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 0>;
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -213,7 +244,32 @@
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
- };
+ };
+
+ ov5642: camera@3c {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ reg = <0x3c>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
};
&i2c2 {
@@ -222,6 +278,32 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@@ -425,6 +507,36 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
diff --git a/dts/src/arm/imx6qdl-tx6.dtsi b/dts/src/arm/imx6qdl-tx6.dtsi
index 1691714f13..c6bec97fbe 100644
--- a/dts/src/arm/imx6qdl-tx6.dtsi
+++ b/dts/src/arm/imx6qdl-tx6.dtsi
@@ -133,8 +133,7 @@
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
- enable-active-low;
+ gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
};
reg_lcd0_pwr: regulator-lcd0-pwr {
@@ -249,7 +248,7 @@
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-handle = <&etnphy>;
phy-supply = <&reg_3v3_etn>;
status = "okay";
diff --git a/dts/src/arm/imx6qdl-wandboard.dtsi b/dts/src/arm/imx6qdl-wandboard.dtsi
index 82dc5744ae..b4fa7f1d63 100644
--- a/dts/src/arm/imx6qdl-wandboard.dtsi
+++ b/dts/src/arm/imx6qdl-wandboard.dtsi
@@ -88,6 +88,7 @@
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
+ lrclk-strength = <3>;
};
};
@@ -208,7 +209,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio3 29 0>;
+ phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index e426faa9c2..a9723b94ba 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -156,7 +156,7 @@
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
gpu_2d: gpu@00134000 {
@@ -166,7 +166,7 @@
clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
timer@00a00600 {
@@ -434,7 +434,7 @@
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
clock-names = "per", "ahb";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
resets = <&src 1>;
iram = <&ocram>;
};
@@ -644,6 +644,7 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
regulator-3p0 {
@@ -658,6 +659,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
regulator-2p5 {
@@ -672,6 +674,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
@@ -797,19 +800,39 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
- pu-supply = <&reg_pu>;
- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
- <&clks IMX6QDL_CLK_GPU3D_SHADER>,
- <&clks IMX6QDL_CLK_GPU2D_CORE>,
- <&clks IMX6QDL_CLK_GPU2D_AXI>,
- <&clks IMX6QDL_CLK_OPENVG_AXI>,
- <&clks IMX6QDL_CLK_VPU_AXI>;
- #power-domain-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_IPG>;
+ clock-names = "ipg";
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ };
+ pd_pu: power-domain@1 {
+ reg = <1>;
+ #power-domain-cells = <0>;
+ power-supply = <&reg_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ };
+ };
};
gpr: iomuxc-gpr@020e0000 {
- compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x020e0000 0x38>;
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ };
};
iomuxc: iomuxc@020e0000 {
@@ -1135,7 +1158,16 @@
};
mipi_csi: mipi@021dc000 {
+ compatible = "fsl,imx6-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>,
+ <&clks IMX6QDL_CLK_EIM_PODF>;
+ clock-names = "dphy", "ref", "pix";
+ status = "disabled";
};
mipi_dsi: mipi@021e0000 {
@@ -1237,6 +1269,10 @@
ipu1_csi0: port@0 {
reg = <0>;
+
+ ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+ };
};
ipu1_csi1: port@1 {
diff --git a/dts/src/arm/imx6qp-zii-rdu2.dts b/dts/src/arm/imx6qp-zii-rdu2.dts
index 882b3bd97e..547a76677a 100644
--- a/dts/src/arm/imx6qp-zii-rdu2.dts
+++ b/dts/src/arm/imx6qp-zii-rdu2.dts
@@ -41,8 +41,8 @@
/dts-v1/;
-#include <imx6qp.dtsi>
-#include <imx6qdl-zii-rdu2.dtsi>
+#include "imx6qp.dtsi"
+#include "imx6qdl-zii-rdu2.dtsi"
/ {
model = "ZII RDU2+ Board";
diff --git a/dts/src/arm/imx6qp.dtsi b/dts/src/arm/imx6qp.dtsi
index 59453f2ac4..299d863690 100644
--- a/dts/src/arm/imx6qp.dtsi
+++ b/dts/src/arm/imx6qp.dtsi
@@ -120,6 +120,10 @@
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
+&gpc {
+ compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
+};
+
&ipu1 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
fsl,prg = <&prg1>;
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index cc9572ea28..3243af4a99 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -530,6 +530,7 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
regulator-3p0 {
@@ -544,6 +545,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
regulator-2p5 {
@@ -558,6 +560,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
diff --git a/dts/src/arm/imx6sx-nitrogen6sx.dts b/dts/src/arm/imx6sx-nitrogen6sx.dts
index 802da45aa5..c5578d1c1e 100644
--- a/dts/src/arm/imx6sx-nitrogen6sx.dts
+++ b/dts/src/arm/imx6sx-nitrogen6sx.dts
@@ -296,7 +296,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -374,7 +374,7 @@
cap-sdio-irq;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio7>;
diff --git a/dts/src/arm/imx6sx-sdb.dts b/dts/src/arm/imx6sx-sdb.dts
index d71da30c9c..c0139d7e49 100644
--- a/dts/src/arm/imx6sx-sdb.dts
+++ b/dts/src/arm/imx6sx-sdb.dts
@@ -128,3 +128,11 @@
reg = <1>;
};
};
+
+&reg_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+&reg_soc {
+ vin-supply = <&sw1a_reg>;
+};
diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi
index 3f1416be4c..f16b9df9d0 100644
--- a/dts/src/arm/imx6sx.dtsi
+++ b/dts/src/arm/imx6sx.dtsi
@@ -587,6 +587,7 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
regulator-3p0 {
@@ -601,6 +602,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
regulator-2p5 {
@@ -615,6 +617,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
diff --git a/dts/src/arm/imx6ul-opos6ul.dtsi b/dts/src/arm/imx6ul-opos6ul.dtsi
index 51095df33a..aec5ccce03 100644
--- a/dts/src/arm/imx6ul-opos6ul.dtsi
+++ b/dts/src/arm/imx6ul-opos6ul.dtsi
@@ -120,7 +120,7 @@
#address-cells = <1>;
#size-cells = <0>;
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
diff --git a/dts/src/arm/imx6ul-tx6ul-mainboard.dts b/dts/src/arm/imx6ul-tx6ul-mainboard.dts
index 7c5dd1b316..28d055e3f3 100644
--- a/dts/src/arm/imx6ul-tx6ul-mainboard.dts
+++ b/dts/src/arm/imx6ul-tx6ul-mainboard.dts
@@ -78,7 +78,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "okay";
diff --git a/dts/src/arm/imx6ul-tx6ul.dtsi b/dts/src/arm/imx6ul-tx6ul.dtsi
index c784a0b75c..ec745eb3b6 100644
--- a/dts/src/arm/imx6ul-tx6ul.dtsi
+++ b/dts/src/arm/imx6ul-tx6ul.dtsi
@@ -173,8 +173,7 @@
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
- gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
- enable-active-low;
+ gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
};
reg_lcd_pwr: regulator-lcdpwr {
@@ -308,7 +307,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy0>;
status = "okay";
@@ -343,7 +342,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "disabled";
diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi
index b9d7d2d094..6da2b77edd 100644
--- a/dts/src/arm/imx6ul.dtsi
+++ b/dts/src/arm/imx6ul.dtsi
@@ -542,6 +542,7 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
diff --git a/dts/src/arm/imx7-colibri.dtsi b/dts/src/arm/imx7-colibri.dtsi
index 2d87489f91..d7753f7993 100644
--- a/dts/src/arm/imx7-colibri.dtsi
+++ b/dts/src/arm/imx7-colibri.dtsi
@@ -43,7 +43,7 @@
/ {
bl: backlight {
compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
+ pwms = <&pwm1 0 5000000 0>;
};
reg_module_3v3: regulator-module-3v3 {
diff --git a/dts/src/arm/imx7d-nitrogen7.dts b/dts/src/arm/imx7d-nitrogen7.dts
index 5d98e2b5d5..e799830886 100644
--- a/dts/src/arm/imx7d-nitrogen7.dts
+++ b/dts/src/arm/imx7d-nitrogen7.dts
@@ -67,7 +67,7 @@
backlight-j20 {
compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
+ pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
@@ -279,7 +279,7 @@
status = "okay";
rtc@68 {
- compatible = "rv4162";
+ compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_rv4162>;
reg = <0x68>;
@@ -738,7 +738,7 @@
pinctrl_wdog1: wdog1grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x75
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75
>;
};
};
diff --git a/dts/src/arm/imx7d-pico.dts b/dts/src/arm/imx7d-pico.dts
new file mode 100644
index 0000000000..e78c2c9cc2
--- /dev/null
+++ b/dts/src/arm/imx7d-pico.dts
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+ model = "Technexion Pico i.MX7D Board";
+ compatible = "technexion,imx7d-pico", "fsl,imx7d";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx7-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ status = "okay";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ VDDA-supply = <&reg_2p5v>;
+ VDDIO-supply = <&reg_vref_1v8>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pmic: pfuze3000@08 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+ /* use sw1c_reg to align with pfuze100/pfuze200 */
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+ <&clks IMX7D_SAI1_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <24576000>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ no-1-8-v;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
+ MX7D_PAD_SD2_WP__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
+ MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
+ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
+ MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
+ MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
+ MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
+ MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
+ >;
+ };
+
+ pinctrl_usbotg1_pwr: usbotg_pwr {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7d-pinfunc.h b/dts/src/arm/imx7d-pinfunc.h
index f6f7e78f88..f2493bc63d 100644
--- a/dts/src/arm/imx7d-pinfunc.h
+++ b/dts/src/arm/imx7d-pinfunc.h
@@ -17,9 +17,9 @@
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts
index 5be01a1bf8..54c4540228 100644
--- a/dts/src/arm/imx7d-sdb.dts
+++ b/dts/src/arm/imx7d-sdb.dts
@@ -52,47 +52,70 @@
reg = <0x80000000 0x80000000>;
};
- regulators {
- compatible = "simple-bus";
+ spi4 {
+ compatible = "spi-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi4>;
+ gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
+ extended_io: gpio-expander@0 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ #gpio-cells = <2>;
reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ registers-number = <1>;
+ spi-max-frequency = <100000>;
};
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_can2_3v3: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "can2-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
+ reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_vref_1v8: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vref-1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
+ reg_can2_3v3: regulator-can2-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_brcm: regulator-brcm {
+ compatible = "regulator-fixed";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "brcm_reg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_brcm_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <200000>;
};
};
@@ -328,6 +351,11 @@
};
};
+&pcie {
+ reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
@@ -342,6 +370,15 @@
status = "okay";
};
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
@@ -363,6 +400,19 @@
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ wakeup-source;
+ keep-power-in-suspend;
+ non-removable;
+ vmmc-supply = <&reg_brcm>;
+ fsl,tuning-step = <2>;
+ status = "okay";
+};
+
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -387,6 +437,12 @@
pinctrl-0 = <&pinctrl_hog>;
imx7d-sdb {
+ pinctrl_brcm_reg: brcmreggrp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
+ >;
+ };
+
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
@@ -554,7 +610,6 @@
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
- MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
>;
};
@@ -634,7 +689,7 @@
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
@@ -642,5 +697,13 @@
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
>;
+
+ pinctrl_spi4: spi4grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
+ >;
+ };
};
};
diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi
index f6dee41a05..f46814a7ea 100644
--- a/dts/src/arm/imx7d.dtsi
+++ b/dts/src/arm/imx7d.dtsi
@@ -42,6 +42,7 @@
*/
#include "imx7s.dtsi"
+#include <dt-bindings/reset/imx7-reset.h>
/ {
cpus {
@@ -127,6 +128,42 @@
fsl,num-rx-queues=<3>;
status = "disabled";
};
+
+ pcie: pcie@0x33800000 {
+ compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
+ reg = <0x33800000 0x4000>,
+ <0x4ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
+ <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
+ <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie_phy>;
+ resets = <&src IMX7_RESET_PCIEPHY>,
+ <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
+ reset-names = "pciephy", "apps";
+ status = "disabled";
+ };
};
&ca_funnel_ports {
diff --git a/dts/src/arm/imx7s-warp.dts b/dts/src/arm/imx7s-warp.dts
index d5237fd0fa..07b63f8b73 100644
--- a/dts/src/arm/imx7s-warp.dts
+++ b/dts/src/arm/imx7s-warp.dts
@@ -295,6 +295,7 @@
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
+ no-1-8-v;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
@@ -442,7 +443,7 @@
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index c4f12fd2e0..4cf6c458b5 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -42,6 +42,7 @@
*/
#include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -119,7 +120,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&intc>;
+ interrupt-parent = <&gpc>;
ranges;
funnel@30041000 {
@@ -301,6 +302,7 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
@@ -309,6 +311,7 @@
timer {
compatible = "arm,armv7-timer";
+ interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -488,7 +491,8 @@
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx7d-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -516,6 +520,7 @@
anatop-min-bit-val = <8>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1200000>;
+ anatop-enable-bit = <0>;
};
};
@@ -563,6 +568,27 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx7d-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&intc>;
+ #power-domain-cells = <1>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY {
+ #power-domain-cells = <0>;
+ reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
+ power-supply = <&reg_1p0d>;
+ };
+ };
+ };
};
aips2: aips-bus@30400000 {
@@ -609,7 +635,7 @@
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
<&clks IMX7D_PWM1_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -620,7 +646,7 @@
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
<&clks IMX7D_PWM2_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -631,7 +657,7 @@
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
<&clks IMX7D_PWM3_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -642,7 +668,7 @@
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
<&clks IMX7D_PWM4_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -934,8 +960,8 @@
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@@ -946,8 +972,8 @@
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@@ -958,8 +984,8 @@
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
diff --git a/dts/src/arm/keystone-k2g-evm.dts b/dts/src/arm/keystone-k2g-evm.dts
index 692fcbb143..61883cb969 100644
--- a/dts/src/arm/keystone-k2g-evm.dts
+++ b/dts/src/arm/keystone-k2g-evm.dts
@@ -20,7 +20,7 @@
compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
model = "Texas Instruments K2G General Purpose EVM";
- memory {
+ memory@800000000 {
device_type = "memory";
reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
};
diff --git a/dts/src/arm/keystone-k2g-ice.dts b/dts/src/arm/keystone-k2g-ice.dts
new file mode 100644
index 0000000000..d820d37b51
--- /dev/null
+++ b/dts/src/arm/keystone-k2g-ice.dts
@@ -0,0 +1,35 @@
+/*
+ * Device Tree Source for K2G Industrial Communication Engine EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+ compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
+ model = "Texas Instruments K2G Industrial Communication EVM";
+
+ memory@800000000 {
+ device_type = "memory";
+ reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
+ };
+};
+
+&k2g_pinctrl {
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
diff --git a/dts/src/arm/keystone-k2g.dtsi b/dts/src/arm/keystone-k2g.dtsi
index f59567fe7d..a789f75a1e 100644
--- a/dts/src/arm/keystone-k2g.dtsi
+++ b/dts/src/arm/keystone-k2g.dtsi
@@ -15,7 +15,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/keystone.h>
-#include "skeleton.dtsi"
/ {
compatible = "ti,k2g","ti,keystone";
@@ -24,6 +23,8 @@
#size-cells = <2>;
interrupt-parent = <&gic>;
+ chosen { };
+
aliases {
serial0 = &uart0;
};
diff --git a/dts/src/arm/kirkwood-openblocks_a6.dts b/dts/src/arm/kirkwood-openblocks_a6.dts
index 94e49f32d5..c75da5f0ca 100644
--- a/dts/src/arm/kirkwood-openblocks_a6.dts
+++ b/dts/src/arm/kirkwood-openblocks_a6.dts
@@ -141,7 +141,7 @@
partition@d4000 {
label = "test";
- reg = <0xd4000 0x24000>;
+ reg = <0xd4000 0x20000>;
};
partition@f4000 {
diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi
index efe53998c9..6d89736c7b 100644
--- a/dts/src/arm/logicpd-torpedo-som.dtsi
+++ b/dts/src/arm/logicpd-torpedo-som.dtsi
@@ -7,6 +7,10 @@
#include <dt-bindings/input/input.h>
/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
diff --git a/dts/src/arm/ls1021a.dtsi b/dts/src/arm/ls1021a.dtsi
index 45ea57fafa..7bb9df2c14 100644
--- a/dts/src/arm/ls1021a.dtsi
+++ b/dts/src/arm/ls1021a.dtsi
@@ -75,7 +75,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
- clocks = <&cluster1_clk>;
+ clocks = <&clockgen 1 0>;
#cooling-cells = <2>;
};
@@ -83,10 +83,17 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
- clocks = <&cluster1_clk>;
+ clocks = <&clockgen 1 0>;
};
};
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -165,7 +172,7 @@
<0x0 0x20220520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
dma-coherent;
status = "disabled";
};
@@ -216,41 +223,10 @@
};
clockgen: clocking@1ee1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x1ee1000 0x10000>;
-
- sysclk: sysclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-output-names = "sysclk";
- };
-
- cga_pll1: pll@800 {
- compatible = "fsl,qoriq-core-pll-2.0";
- #clock-cells = <1>;
- reg = <0x800 0x10>;
- clocks = <&sysclk>;
- clock-output-names = "cga-pll1", "cga-pll1-div2",
- "cga-pll1-div4";
- };
-
- platform_clk: pll@c00 {
- compatible = "fsl,qoriq-core-pll-2.0";
- #clock-cells = <1>;
- reg = <0xc00 0x10>;
- clocks = <&sysclk>;
- clock-output-names = "platform-clk", "platform-clk-div2";
- };
-
- cluster1_clk: clk0c0@0 {
- compatible = "fsl,qoriq-core-mux-2.0";
- #clock-cells = <0>;
- reg = <0x0 0x10>;
- clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
- clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
- clock-output-names = "cluster1-clk";
- };
+ compatible = "fsl,ls1021a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
};
tmu: tmu@1f00000 {
@@ -338,7 +314,7 @@
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -351,7 +327,7 @@
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -364,7 +340,7 @@
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -375,7 +351,7 @@
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -386,7 +362,7 @@
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -479,7 +455,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -488,7 +464,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -497,7 +473,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -506,7 +482,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -515,7 +491,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -524,7 +500,7 @@
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "wdog-en";
big-endian;
};
@@ -534,8 +510,8 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b50000 0x0 0x10000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>, <&platform_clk 1>,
- <&platform_clk 1>, <&platform_clk 1>;
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
@@ -548,8 +524,8 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b60000 0x0 0x10000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>, <&platform_clk 1>,
- <&platform_clk 1>, <&platform_clk 1>;
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
@@ -569,16 +545,16 @@
dma-channels = <32>;
big-endian;
clock-names = "dmamux0", "dmamux1";
- clocks = <&platform_clk 1>,
- <&platform_clk 1>;
+ clocks = <&clockgen 4 1>,
+ <&clockgen 4 1>;
};
dcu: dcu@2ce0000 {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce0000 0x0 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 0>,
- <&platform_clk 0>;
+ clocks = <&clockgen 4 0>,
+ <&clockgen 4 0>;
clock-names = "dcu", "pix";
big-endian;
status = "disabled";
diff --git a/dts/src/arm/meson.dtsi b/dts/src/arm/meson.dtsi
index 8c77c87660..15204e4416 100644
--- a/dts/src/arm/meson.dtsi
+++ b/dts/src/arm/meson.dtsi
@@ -45,6 +45,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/include/ "skeleton.dtsi"
/ {
@@ -65,99 +67,158 @@
#interrupt-cells = <3>;
};
- timer@c1109940 {
- compatible = "amlogic,meson6-timer";
- reg = <0xc1109940 0x18>;
- interrupts = <0 10 1>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- wdt: watchdog@c1109900 {
- compatible = "amlogic,meson6-wdt";
- reg = <0xc1109900 0x8>;
- interrupts = <0 0 1>;
- };
-
- uart_AO: serial@c81004c0 {
- compatible = "amlogic,meson-uart";
- reg = <0xc81004c0 0x18>;
- interrupts = <0 90 1>;
- clocks = <&clk81>;
- status = "disabled";
- };
-
- uart_A: serial@c11084c0 {
- compatible = "amlogic,meson-uart";
- reg = <0xc11084c0 0x18>;
- interrupts = <0 26 1>;
- clocks = <&clk81>;
- status = "disabled";
- };
-
- uart_B: serial@c11084dc {
- compatible = "amlogic,meson-uart";
- reg = <0xc11084dc 0x18>;
- interrupts = <0 75 1>;
- clocks = <&clk81>;
- status = "disabled";
- };
-
- uart_C: serial@c1108700 {
- compatible = "amlogic,meson-uart";
- reg = <0xc1108700 0x18>;
- interrupts = <0 93 1>;
- clocks = <&clk81>;
- status = "disabled";
- };
-
- i2c_AO: i2c@c8100500 {
- compatible = "amlogic,meson6-i2c";
- reg = <0xc8100500 0x20>;
- interrupts = <0 92 1>;
- clocks = <&clk81>;
+ cbus: cbus@c1100000 {
+ compatible = "simple-bus";
+ reg = <0xc1100000 0x200000>;
#address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ #size-cells = <1>;
+ ranges = <0x0 0xc1100000 0x200000>;
+
+ hwrng: rng@8100 {
+ compatible = "amlogic,meson-rng";
+ reg = <0x8100 0x8>;
+ };
+
+ uart_A: serial@84c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x84c0 0x18>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart_B: serial@84dc {
+ compatible = "amlogic,meson-uart";
+ reg = <0x84dc 0x18>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ i2c_A: i2c@8500 {
+ compatible = "amlogic,meson6-i2c";
+ reg = <0x8500 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x8680 0x34>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart_C: serial@8700 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x8700 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ i2c_B: i2c@87c0 {
+ compatible = "amlogic,meson6-i2c";
+ reg = <0x87c0 0x20>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb0_phy: phy@8800 {
+ compatible = "amlogic,meson-mx-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x8800 0x20>;
+ status = "disabled";
+ };
+
+ usb1_phy: phy@8820 {
+ compatible = "amlogic,meson-mx-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x8820 0x20>;
+ status = "disabled";
+ };
+
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson6-spifc";
+ reg = <0x8c80 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@9900 {
+ compatible = "amlogic,meson6-wdt";
+ reg = <0x9900 0x8>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ timer@9940 {
+ compatible = "amlogic,meson6-timer";
+ reg = <0x9940 0x18>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
+ };
};
- i2c_A: i2c@c1108500 {
- compatible = "amlogic,meson6-i2c";
- reg = <0xc1108500 0x20>;
- interrupts = <0 21 1>;
- clocks = <&clk81>;
+ aobus: aobus@c8100000 {
+ compatible = "simple-bus";
+ reg = <0xc8100000 0x100000>;
#address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ #size-cells = <1>;
+ ranges = <0x0 0xc8100000 0x100000>;
+
+ ir_receiver: ir-receiver@480 {
+ compatible= "amlogic,meson6-ir";
+ reg = <0x480 0x20>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart_AO: serial@4c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x4c0 0x18>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ i2c_AO: i2c@500 {
+ compatible = "amlogic,meson6-i2c";
+ reg = <0x500 0x20>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
- i2c_B: i2c@c11087c0 {
- compatible = "amlogic,meson6-i2c";
- reg = <0xc11087c0 0x20>;
- interrupts = <0 128 1>;
- clocks = <&clk81>;
+ usb0: usb@c9040000 {
+ compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0xc9040000 0x40000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>;
+ phys = <&usb0_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
status = "disabled";
};
- ir_receiver: ir-receiver@c8100480 {
- compatible= "amlogic,meson6-ir";
- reg = <0xc8100480 0x20>;
- interrupts = <0 15 1>;
- status = "disabled";
- };
-
- spifc: spi@c1108c80 {
- compatible = "amlogic,meson6-spifc";
- reg = <0xc1108c80 0x80>;
+ usb1: usb@c90c0000 {
+ compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clk81>;
+ reg = <0xc90c0000 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
+ phys = <&usb1_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
status = "disabled";
};
@@ -165,10 +226,8 @@
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
0xc1108108 0x4>;
- interrupts = <0 8 1>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq";
- clocks = <&clk81>;
- clock-names = "stmmaceth";
status = "disabled";
};
};
diff --git a/dts/src/arm/meson6-atv1200.dts b/dts/src/arm/meson6-atv1200.dts
index 1237faa63c..9444b0d962 100644
--- a/dts/src/arm/meson6-atv1200.dts
+++ b/dts/src/arm/meson6-atv1200.dts
@@ -46,7 +46,7 @@
*/
/dts-v1/;
-/include/ "meson6.dtsi"
+#include "meson6.dtsi"
/ {
model = "Geniatech ATV1200";
diff --git a/dts/src/arm/meson6.dtsi b/dts/src/arm/meson6.dtsi
index 8b33be15af..8557b6117a 100644
--- a/dts/src/arm/meson6.dtsi
+++ b/dts/src/arm/meson6.dtsi
@@ -45,14 +45,12 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "meson.dtsi"
+#include "meson.dtsi"
/ {
model = "Amlogic Meson6 SoC";
compatible = "amlogic,meson6";
- interrupt-parent = <&gic>;
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/meson8.dtsi b/dts/src/arm/meson8.dtsi
index ebc763eab1..cada358289 100644
--- a/dts/src/arm/meson8.dtsi
+++ b/dts/src/arm/meson8.dtsi
@@ -43,15 +43,14 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
-/include/ "meson.dtsi"
+#include "meson.dtsi"
/ {
model = "Amlogic Meson8 SoC";
compatible = "amlogic,meson8";
- interrupt-parent = <&gic>;
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,34 +84,68 @@
};
};
- clk81: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <141666666>;
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* 2 MiB reserved for Hardware ROM Firmware? */
+ hwrom@0 {
+ reg = <0x0 0x200000>;
+ no-map;
+ };
+
+ /*
+ * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+ * code which is responsible for system suspend. It loads a
+ * piece of ARC code ("arc_power" in the vendor u-boot tree)
+ * into SRAM, executes that and shuts down the (last) ARM core.
+ * The arc_power firmware then checks various wakeup sources
+ * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+ * simply the power key) and re-starts the ARM core once it
+ * detects a wakeup request.
+ */
+ power-firmware@4f00000 {
+ reg = <0x4f00000 0x100000>;
+ no-map;
+ };
+ };
+
+ scu@c4300000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xc4300000 0x100>;
};
+}; /* end of / */
- pinctrl_cbus: pinctrl@c1109880 {
- compatible = "amlogic,meson8-cbus-pinctrl";
- reg = <0xc1109880 0x10>;
+&aobus {
+ pinctrl_aobus: pinctrl@84 {
+ compatible = "amlogic,meson8-aobus-pinctrl";
+ reg = <0x84 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- gpio: banks@c11080b0 {
- reg = <0xc11080b0 0x28>,
- <0xc11080e8 0x18>,
- <0xc1108120 0x18>,
- <0xc1108030 0x30>;
- reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio_ao: ao-bank@14 {
+ reg = <0x14 0x4>,
+ <0x2c 0x4>,
+ <0x24 0x8>;
+ reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_cbus 0 0 120>;
+ gpio-ranges = <&pinctrl_aobus 0 120 16>;
};
- spi_nor_pins: nor {
+ uart_ao_a_pins: uart_ao_a {
mux {
- groups = "nor_d", "nor_q", "nor_c", "nor_cs";
- function = "nor";
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
+ };
+ };
+
+ i2c_ao_pins: i2c_mst_ao {
+ mux {
+ groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
+ function = "i2c_mst_ao";
};
};
@@ -123,47 +156,168 @@
};
};
- eth_pins: ethernet {
+ pwm_f_ao_pins: pwm-f-ao {
mux {
- groups = "eth_tx_clk_50m", "eth_tx_en",
- "eth_txd1", "eth_txd0",
- "eth_rx_clk_in", "eth_rx_dv",
- "eth_rxd1", "eth_rxd0", "eth_mdio",
- "eth_mdc";
- function = "ethernet";
+ groups = "pwm_f_ao";
+ function = "pwm_f_ao";
};
};
};
+};
- pinctrl_aobus: pinctrl@c8100084 {
- compatible = "amlogic,meson8-aobus-pinctrl";
- reg = <0xc8100084 0xc>;
+&cbus {
+ clkc: clock-controller@4000 {
+ #clock-cells = <1>;
+ compatible = "amlogic,meson8-clkc";
+ reg = <0x8000 0x4>, <0x4000 0x460>;
+ };
+
+ pinctrl_cbus: pinctrl@9880 {
+ compatible = "amlogic,meson8-cbus-pinctrl";
+ reg = <0x9880 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- gpio_ao: ao-bank@c1108030 {
- reg = <0xc8100014 0x4>,
- <0xc810002c 0x4>,
- <0xc8100024 0x8>;
- reg-names = "mux", "pull", "gpio";
+ gpio: banks@80b0 {
+ reg = <0x80b0 0x28>,
+ <0x80e8 0x18>,
+ <0x8120 0x18>,
+ <0x8030 0x30>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_aobus 0 120 16>;
+ gpio-ranges = <&pinctrl_cbus 0 0 120>;
};
- uart_ao_a_pins: uart_ao_a {
+ sd_a_pins: sd-a {
mux {
- groups = "uart_tx_ao_a", "uart_rx_ao_a";
- function = "uart_ao";
+ groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+ "sd_d3_a", "sd_clk_a", "sd_cmd_a";
+ function = "sd_a";
};
};
- i2c_ao_pins: i2c_mst_ao {
+ sd_b_pins: sd-b {
mux {
- groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
- function = "i2c_mst_ao";
+ groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+ "sd_d3_b", "sd_clk_b", "sd_cmd_b";
+ function = "sd_b";
+ };
+ };
+
+ sd_c_pins: sd-c {
+ mux {
+ groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+ "sd_d3_c", "sd_clk_c", "sd_cmd_c";
+ function = "sd_c";
+ };
+ };
+
+ spi_nor_pins: nor {
+ mux {
+ groups = "nor_d", "nor_q", "nor_c", "nor_cs";
+ function = "nor";
+ };
+ };
+
+ eth_pins: ethernet {
+ mux {
+ groups = "eth_tx_clk_50m", "eth_tx_en",
+ "eth_txd1", "eth_txd0",
+ "eth_rx_clk_in", "eth_rx_dv",
+ "eth_rxd1", "eth_rxd0", "eth_mdio",
+ "eth_mdc";
+ function = "ethernet";
+ };
+ };
+
+ pwm_e_pins: pwm-e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
};
};
};
-}; /* end of / */
+};
+
+&ethmac {
+ clocks = <&clkc CLKID_ETH>;
+ clock-names = "stmmaceth";
+};
+
+&hwrng {
+ compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&i2c_AO {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&L2 {
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
+&saradc {
+ compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+ clocks = <&clkc CLKID_XTAL>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>;
+ clock-names = "clkin", "core", "sana";
+};
+
+&spifc {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_AO {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_A {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_B {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_C {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&usb0 {
+ compatible = "amlogic,meson8-usb", "snps,dwc2";
+ clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+ clock-names = "otg";
+};
+
+&usb1 {
+ compatible = "amlogic,meson8-usb", "snps,dwc2";
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "otg";
+};
+
+&usb0_phy {
+ compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+ clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+ compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+ clock-names = "usb_general", "usb";
+};
diff --git a/dts/src/arm/meson8b.dtsi b/dts/src/arm/meson8b.dtsi
index 828aa49c67..72e4f425f1 100644
--- a/dts/src/arm/meson8b.dtsi
+++ b/dts/src/arm/meson8b.dtsi
@@ -47,11 +47,9 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
-#include "skeleton.dtsi"
+#include "meson.dtsi"
/ {
- interrupt-parent = <&gic>;
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,146 +83,162 @@
};
};
- soc {
- compatible = "simple-bus";
+ scu@c4300000 {
+ compatible = "arm,cortex-a5-scu";
+ reg = <0xc4300000 0x100>;
+ };
+}; /* end of / */
+
+&aobus {
+ pinctrl_aobus: pinctrl@84 {
+ compatible = "amlogic,meson8b-aobus-pinctrl";
+ reg = <0x84 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- L2: l2-cache-controller@c4200000 {
- compatible = "arm,pl310-cache";
- reg = <0xc4200000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- gic: interrupt-controller@c4301000 {
- compatible = "arm,cortex-a9-gic";
- reg = <0xc4301000 0x1000>,
- <0xc4300100 0x0100>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- reset: reset-controller@c1104404 {
- compatible = "amlogic,meson8b-reset";
- reg = <0xc1104404 0x20>;
- #reset-cells = <1>;
- };
-
- wdt: watchdog@c1109900 {
- compatible = "amlogic,meson8b-wdt";
- reg = <0xc1109900 0x8>;
- interrupts = <0 0 1>;
+ gpio_ao: ao-bank@14 {
+ reg = <0x14 0x4>,
+ <0x2c 0x4>,
+ <0x24 0x8>;
+ reg-names = "mux", "pull", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_aobus 0 130 16>;
};
- timer@c1109940 {
- compatible = "amlogic,meson6-timer";
- reg = <0xc1109940 0x18>;
- interrupts = <0 10 1>;
- };
-
- uart_AO: serial@c81004c0 {
- compatible = "amlogic,meson-uart";
- reg = <0xc81004c0 0x18>;
- interrupts = <0 90 1>;
- clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
- };
-
- uart_A: serial@c11084c0 {
- compatible = "amlogic,meson-uart";
- reg = <0xc11084c0 0x18>;
- interrupts = <0 26 1>;
- clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
- };
-
- uart_B: serial@c11084dc {
- compatible = "amlogic,meson-uart";
- reg = <0xc11084dc 0x18>;
- interrupts = <0 75 1>;
- clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
+ };
};
+ };
+};
- uart_C: serial@c1108700 {
- compatible = "amlogic,meson-uart";
- reg = <0xc1108700 0x18>;
- interrupts = <0 93 1>;
- clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
- };
+&cbus {
+ clkc: clock-controller@4000 {
+ #clock-cells = <1>;
+ compatible = "amlogic,meson8b-clkc";
+ reg = <0x8000 0x4>, <0x4000 0x460>;
+ };
- clkc: clock-controller@c1104000 {
- #clock-cells = <1>;
- compatible = "amlogic,meson8b-clkc";
- reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
- };
+ reset: reset-controller@4404 {
+ compatible = "amlogic,meson8b-reset";
+ reg = <0x4404 0x20>;
+ #reset-cells = <1>;
+ };
- pwm_ab: pwm@8550 {
- compatible = "amlogic,meson8b-pwm";
- reg = <0xc1108550 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
+ pwm_ab: pwm@8550 {
+ compatible = "amlogic,meson8b-pwm";
+ reg = <0x8550 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
- pwm_cd: pwm@8650 {
- compatible = "amlogic,meson8b-pwm";
- reg = <0xc1108650 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
+ pwm_cd: pwm@8650 {
+ compatible = "amlogic,meson8b-pwm";
+ reg = <0x8650 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
- pwm_ef: pwm@86c0 {
- compatible = "amlogic,meson8b-pwm";
- reg = <0xc11086c0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
+ pwm_ef: pwm@86c0 {
+ compatible = "amlogic,meson8b-pwm";
+ reg = <0x86c0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
- pinctrl_cbus: pinctrl@c1109880 {
- compatible = "amlogic,meson8b-cbus-pinctrl";
- reg = <0xc1109880 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio: banks@c11080b0 {
- reg = <0xc11080b0 0x28>,
- <0xc11080e8 0x18>,
- <0xc1108120 0x18>,
- <0xc1108030 0x38>;
- reg-names = "mux", "pull", "pull-enable", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_cbus 0 0 130>;
- };
- };
+ wdt: watchdog@9900 {
+ compatible = "amlogic,meson8b-wdt";
+ reg = <0x9900 0x8>;
+ interrupts = <0 0 1>;
+ };
- pinctrl_aobus: pinctrl@c8100084 {
- compatible = "amlogic,meson8b-aobus-pinctrl";
- reg = <0xc8100084 0xc>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio_ao: ao-bank@c1108030 {
- reg = <0xc8100014 0x4>,
- <0xc810002c 0x4>,
- <0xc8100024 0x8>;
- reg-names = "mux", "pull", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_aobus 0 130 16>;
- };
+ pinctrl_cbus: pinctrl@9880 {
+ compatible = "amlogic,meson8b-cbus-pinctrl";
+ reg = <0x9880 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- uart_ao_a_pins: uart_ao_a {
- mux {
- groups = "uart_tx_ao_a", "uart_rx_ao_a";
- function = "uart_ao";
- };
- };
+ gpio: banks@80b0 {
+ reg = <0x80b0 0x28>,
+ <0x80e8 0x18>,
+ <0x8120 0x18>,
+ <0x8030 0x38>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_cbus 0 0 130>;
};
};
-}; /* end of / */
+};
+
+&ethmac {
+ clocks = <&clkc CLKID_ETH>;
+ clock-names = "stmmaceth";
+};
+
+&hwrng {
+ compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&L2 {
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
+&saradc {
+ compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+ clocks = <&clkc CLKID_XTAL>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>;
+ clock-names = "clkin", "core", "sana";
+};
+
+&uart_AO {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_A {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_B {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&uart_C {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&usb0 {
+ compatible = "amlogic,meson8b-usb", "snps,dwc2";
+ clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+ clock-names = "otg";
+};
+
+&usb1 {
+ compatible = "amlogic,meson8b-usb", "snps,dwc2";
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "otg";
+};
+
+&usb0_phy {
+ compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+ clock-names = "usb_general", "usb";
+ resets = <&reset RESET_USB_OTG>;
+};
+
+&usb1_phy {
+ compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+ clock-names = "usb_general", "usb";
+ resets = <&reset RESET_USB_OTG>;
+};
diff --git a/dts/src/arm/motorola-cpcap-mapphone.dtsi b/dts/src/arm/motorola-cpcap-mapphone.dtsi
index f5aeb3959a..1eb5da1dc8 100644
--- a/dts/src/arm/motorola-cpcap-mapphone.dtsi
+++ b/dts/src/arm/motorola-cpcap-mapphone.dtsi
@@ -26,6 +26,22 @@
#io-channel-cells = <1>;
};
+ cpcap_battery: battery {
+ compatible = "motorola,cpcap-battery";
+ interrupts-extended = <
+ &cpcap 6 0 &cpcap 5 0 &cpcap 3 0
+ &cpcap 20 0 &cpcap 54 0
+ >;
+ interrupt-names =
+ "eol", "lowbph", "lowbpl",
+ "chrgcurr1", "battdetb";
+ io-channels = <&cpcap_adc 0 &cpcap_adc 1
+ &cpcap_adc 5 &cpcap_adc 6>;
+ io-channel-names = "battdetb", "battp",
+ "chg_isense", "batti";
+ power-supplies = <&cpcap_charger>;
+ };
+
cpcap_charger: charger {
compatible = "motorola,mapphone-cpcap-charger";
interrupts-extended = <
diff --git a/dts/src/arm/moxart.dtsi b/dts/src/arm/moxart.dtsi
index e86f8c905a..1f4c795d3f 100644
--- a/dts/src/arm/moxart.dtsi
+++ b/dts/src/arm/moxart.dtsi
@@ -58,10 +58,11 @@
};
timer: timer@98400000 {
- compatible = "moxa,moxart-timer";
+ compatible = "moxa,moxart-timer", "faraday,fttmr010";
reg = <0x98400000 0x42>;
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk_apb>;
+ clock-names = "PCLK";
};
gpio: gpio@98700000 {
diff --git a/dts/src/arm/mt2701-evb.dts b/dts/src/arm/mt2701-evb.dts
index a4837985b7..f484973542 100644
--- a/dts/src/arm/mt2701-evb.dts
+++ b/dts/src/arm/mt2701-evb.dts
@@ -22,13 +22,95 @@
memory {
reg = <0 0x80000000 0 0x40000000>;
};
+
+ sound:sound {
+ compatible = "mediatek,mt2701-cs42448-machine";
+ mediatek,platform = <&afe>;
+ /* CS42448 Machine name */
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "AMIC",
+ "AIN1R", "AMIC",
+ "AIN2L", "Tuner In",
+ "AIN2R", "Tuner In",
+ "AIN3L", "Satellite Tuner In",
+ "AIN3R", "Satellite Tuner In",
+ "AIN3L", "AUX In",
+ "AIN3R", "AUX In";
+ mediatek,audio-codec = <&cs42448>;
+ mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&aud_pins_default>;
+ i2s1-in-sel-gpio1 = <&pio 53 0>;
+ i2s1-in-sel-gpio2 = <&pio 54 0>;
+ status = "okay";
+ };
+
+ bt_sco_codec:bt_sco_codec {
+ compatible = "linux,bt-sco";
+ };
};
&auxadc {
status = "okay";
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+ cs42448: cs42448@48 {
+ compatible = "cirrus,cs42448";
+ reg = <0x48>;
+ clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
+ clock-names = "mclk";
+ };
+};
+
&pio {
+ i2c0_pins_a: i2c0@0 {
+ pins1 {
+ pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>,
+ <MT2701_PIN_76_SCL0__FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins1 {
+ pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>,
+ <MT2701_PIN_58_SCL1__FUNC_SCL1>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ pins1 {
+ pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>,
+ <MT2701_PIN_78_SCL2__FUNC_SCL2>;
+ bias-disable;
+ };
+ };
+
spi_pins_a: spi0@0 {
pins_spi {
pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
@@ -39,6 +121,31 @@
};
};
+ aud_pins_default: audiodefault {
+ pins_cmd_dat {
+ pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>,
+ <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>,
+ <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>,
+ <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>,
+ <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>,
+ <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>,
+ <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>,
+ <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>,
+ <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>,
+ <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>,
+ <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>,
+ <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>,
+ <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>,
+ <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>,
+ <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>,
+ <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>,
+ <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>,
+ <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>;
+ drive-strength = <MTK_DRIVE_12mA>;
+ bias-pull-down;
+ };
+ };
+
spi_pins_b: spi1@0 {
pins_spi {
pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
@@ -78,6 +185,31 @@
status = "disabled";
};
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
+&pio {
+ nor_pins_default: nor {
+ pins1 {
+ pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>,
+ <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>,
+ <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>,
+ <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
+ <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
+ <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up;
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/dts/src/arm/mt2701.dtsi b/dts/src/arm/mt2701.dtsi
index 8037210501..f1efdc6365 100644
--- a/dts/src/arm/mt2701.dtsi
+++ b/dts/src/arm/mt2701.dtsi
@@ -16,13 +16,14 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
/ {
compatible = "mediatek,mt2701";
- interrupt-parent = <&sysirq>;
+ interrupt-parent = <&cirq>;
cpus {
#address-cells = <1>;
@@ -210,6 +211,16 @@
reg = <0 0x10200100 0 0x1c>;
};
+ cirq: interrupt-controller@10204000 {
+ compatible = "mediatek,mt2701-cirq",
+ "mediatek,mtk-cirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&sysirq>;
+ reg = <0 0x10204000 0 0x400>;
+ mediatek,ext-irq-range = <32 200>;
+ };
+
iommu: mmsys_iommu@10205000 {
compatible = "mediatek,mt2701-m4u";
reg = <0 0x10205000 0 0x1000>;
@@ -286,6 +297,48 @@
status = "disabled";
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt2701-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt2701-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt2701-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt2701-spi";
#address-cells = <1>;
@@ -334,6 +387,18 @@
status = "disabled";
};
+ nor_flash: spi@11014000 {
+ compatible = "mediatek,mt2701-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_FLASH>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spi1: spi@11016000 {
compatible = "mediatek,mt2701-spi";
#address-cells = <1>;
@@ -360,6 +425,104 @@
status = "disabled";
};
+ afe: audio-controller@11220000 {
+ compatible = "mediatek,mt2701-audio";
+ reg = <0 0x11220000 0 0x2000>,
+ <0 0x112a0000 0 0x20000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
+ <&topckgen CLK_TOP_APLL_SEL>,
+ <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>,
+ <&topckgen CLK_TOP_HADDS2PLL_98M>,
+ <&topckgen CLK_TOP_HADDS2PLL_294M>,
+ <&topckgen CLK_TOP_AUDPLL>,
+ <&topckgen CLK_TOP_AUDPLL_D4>,
+ <&topckgen CLK_TOP_AUDPLL_D8>,
+ <&topckgen CLK_TOP_AUDPLL_D16>,
+ <&topckgen CLK_TOP_AUDPLL_D24>,
+ <&topckgen CLK_TOP_AUDINTBUS_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
+ <&topckgen CLK_TOP_ASM_M_SEL>,
+ <&topckgen CLK_TOP_ASM_H_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_UNIVPLL2_D2>,
+ <&topckgen CLK_TOP_SYSPLL_D5>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_mux1_div",
+ "top_audio_mux2_div",
+ "top_audio_48k_timing",
+ "top_audio_44k_timing",
+ "top_audpll_mux_sel",
+ "top_apll_sel",
+ "top_aud1_pll_98M",
+ "top_aud2_pll_90M",
+ "top_hadds2_pll_98M",
+ "top_hadds2_pll_294M",
+ "top_audpll",
+ "top_audpll_d4",
+ "top_audpll_d8",
+ "top_audpll_d16",
+ "top_audpll_d24",
+ "top_audintbus_sel",
+ "clk_26m",
+ "top_syspll1_d4",
+ "top_aud_k1_src_sel",
+ "top_aud_k2_src_sel",
+ "top_aud_k3_src_sel",
+ "top_aud_k4_src_sel",
+ "top_aud_k5_src_sel",
+ "top_aud_k6_src_sel",
+ "top_aud_k1_src_div",
+ "top_aud_k2_src_div",
+ "top_aud_k3_src_div",
+ "top_aud_k4_src_div",
+ "top_aud_k5_src_div",
+ "top_aud_k6_src_div",
+ "top_aud_i2s1_mclk",
+ "top_aud_i2s2_mclk",
+ "top_aud_i2s3_mclk",
+ "top_aud_i2s4_mclk",
+ "top_aud_i2s5_mclk",
+ "top_aud_i2s6_mclk",
+ "top_asm_m_sel",
+ "top_asm_h_sel",
+ "top_univpll2_d4",
+ "top_univpll2_d2",
+ "top_syspll_d5";
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt2701-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
@@ -392,6 +555,20 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
};
+ jpegdec: jpegdec@15004000 {
+ compatible = "mediatek,mt2701-jpgdec";
+ reg = <0 0x15004000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
+ <&imgsys CLK_IMG_JPGDEC>;
+ clock-names = "jpgdec-smi",
+ "jpgdec";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
+ <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
diff --git a/dts/src/arm/mt7623.dtsi b/dts/src/arm/mt7623.dtsi
index 3a9e9b6aea..d81158b2b0 100644
--- a/dts/src/arm/mt7623.dtsi
+++ b/dts/src/arm/mt7623.dtsi
@@ -1,6 +1,7 @@
/*
- * Copyright (c) 2016 MediaTek Inc.
+ * Copyright (c) 2017 MediaTek Inc.
* Author: John Crispin <john@phrozen.org>
+ * Sean Wang <sean.wang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -14,6 +15,12 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
+#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
/ {
@@ -53,16 +60,18 @@
#clock-cells = <0>;
};
- rtc_clk: dummy32k {
+ rtc32k: oscillator@1 {
compatible = "fixed-clock";
- clock-frequency = <32000>;
#clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
};
- uart_clk: dummy26m {
+ clk26m: oscillator@0 {
compatible = "fixed-clock";
- clock-frequency = <26000000>;
#clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
};
timer {
@@ -76,6 +85,65 @@
arm,cpu-registers-not-fw-configured;
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt7623-topckgen",
+ "mediatek,mt2701-topckgen",
+ "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt7623-infracfg",
+ "mediatek,mt2701-infracfg",
+ "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt7623-pericfg",
+ "mediatek,mt2701-pericfg",
+ "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt7623-pinctrl",
+ "mediatek,mt2701-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ syscfg_pctl_a: syscfg@10005000 {
+ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt7623-scpsys",
+ "mediatek,mt2701-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "mm", "mfg", "ethif";
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt7623-wdt",
"mediatek,mt6589-wdt";
@@ -87,10 +155,32 @@
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&system_clk>, <&rtc_clk>;
+ clocks = <&system_clk>, <&rtc32k>;
clock-names = "system-clk", "rtc-clk";
};
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt7623-pwrap",
+ "mediatek,mt2701-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMICSPI>,
+ <&infracfg CLK_INFRA_PMICWRAP>;
+ clock-names = "spi", "wrap";
+ };
+
+ cir: cir@0x10013000 {
+ compatible = "mediatek,mt7623-cir";
+ reg = <0 0x10013000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt7623-sysirq",
"mediatek,mt6577-sysirq";
@@ -100,6 +190,32 @@
reg = <0 0x10200100 0 0x1c>;
};
+ efuse: efuse@10206000 {
+ compatible = "mediatek,mt7623-efuse",
+ "mediatek,mt8173-efuse";
+ reg = <0 0x10206000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ thermal_calibration_data: calib@424 {
+ reg = <0x424 0xc>;
+ };
+ };
+
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt7623-apmixedsys",
+ "mediatek,mt2701-apmixedsys",
+ "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_TRNG>;
+ clock-names = "rng";
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
@@ -111,12 +227,23 @@
<0 0x10216000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt7623-auxadc",
+ "mediatek,mt2701-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>,
+ <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -125,7 +252,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>,
+ <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -134,7 +263,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>,
+ <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -143,7 +274,402 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>,
+ <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt7623-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM>,
+ <&pericfg CLK_PERI_PWM1>,
+ <&pericfg CLK_PERI_PWM2>,
+ <&pericfg CLK_PERI_PWM3>,
+ <&pericfg CLK_PERI_PWM4>,
+ <&pericfg CLK_PERI_PWM5>;
+ clock-names = "top", "main", "pwm1", "pwm2",
+ "pwm3", "pwm4", "pwm5";
+ status = "disabled";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI0_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <1>;
+ compatible = "mediatek,mt7623-thermal",
+ "mediatek,mt2701-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
+ reset-names = "therm";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration_data>;
+ nvmem-cell-names = "calibration-data";
+ };
+
+ spi1: spi@11016000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11016000 0 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI1_SEL>,
+ <&pericfg CLK_PERI_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11017000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11017000 0 0x1000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI2_SEL>,
+ <&pericfg CLK_PERI_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7623-nfc",
+ "mediatek,mt2701-nfc";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ clocks = <&pericfg CLK_PERI_NFI>,
+ <&pericfg CLK_PERI_NFI_PAD>;
+ clock-names = "nfi_clk", "pad_clk";
+ status = "disabled";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7623-ecc",
+ "mediatek,mt2701-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ afe: audio-controller@11220000 {
+ compatible = "mediatek,mt7623-audio",
+ "mediatek,mt2701-audio";
+ reg = <0 0x11220000 0 0x2000>,
+ <0 0x112a0000 0 0x20000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
+ <&topckgen CLK_TOP_APLL_SEL>,
+ <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>,
+ <&topckgen CLK_TOP_HADDS2PLL_98M>,
+ <&topckgen CLK_TOP_HADDS2PLL_294M>,
+ <&topckgen CLK_TOP_AUDPLL>,
+ <&topckgen CLK_TOP_AUDPLL_D4>,
+ <&topckgen CLK_TOP_AUDPLL_D8>,
+ <&topckgen CLK_TOP_AUDPLL_D16>,
+ <&topckgen CLK_TOP_AUDPLL_D24>,
+ <&topckgen CLK_TOP_AUDINTBUS_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
+ <&topckgen CLK_TOP_ASM_M_SEL>,
+ <&topckgen CLK_TOP_ASM_H_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_UNIVPLL2_D2>,
+ <&topckgen CLK_TOP_SYSPLL_D5>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_mux1_div",
+ "top_audio_mux2_div",
+ "top_audio_48k_timing",
+ "top_audio_44k_timing",
+ "top_audpll_mux_sel",
+ "top_apll_sel",
+ "top_aud1_pll_98M",
+ "top_aud2_pll_90M",
+ "top_hadds2_pll_98M",
+ "top_hadds2_pll_294M",
+ "top_audpll",
+ "top_audpll_d4",
+ "top_audpll_d8",
+ "top_audpll_d16",
+ "top_audpll_d24",
+ "top_audintbus_sel",
+ "clk_26m",
+ "top_syspll1_d4",
+ "top_aud_k1_src_sel",
+ "top_aud_k2_src_sel",
+ "top_aud_k3_src_sel",
+ "top_aud_k4_src_sel",
+ "top_aud_k5_src_sel",
+ "top_aud_k6_src_sel",
+ "top_aud_k1_src_div",
+ "top_aud_k2_src_div",
+ "top_aud_k3_src_div",
+ "top_aud_k4_src_div",
+ "top_aud_k5_src_div",
+ "top_aud_k6_src_div",
+ "top_aud_i2s1_mclk",
+ "top_aud_i2s2_mclk",
+ "top_aud_i2s3_mclk",
+ "top_aud_i2s4_mclk",
+ "top_aud_i2s5_mclk",
+ "top_aud_i2s6_mclk",
+ "top_asm_m_sel",
+ "top_asm_h_sel",
+ "top_univpll2_d4",
+ "top_univpll2_d2",
+ "top_syspll_d5";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7623-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt7623-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ usb1: usb@1a1c0000 {
+ compatible = "mediatek,mt7623-xhci",
+ "mediatek,mt8173-xhci";
+ reg = <0 0x1a1c0000 0 0x1000>,
+ <0 0x1a1c4700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "free_ck";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a1c4000 {
+ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
+ reg = <0 0x1a1c4000 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0 0x1a1c4800 0 0x0100>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0 0x1a1c4900 0 0x0700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb2: usb@1a240000 {
+ compatible = "mediatek,mt7623-xhci",
+ "mediatek,mt8173-xhci";
+ reg = <0 0x1a240000 0 0x1000>,
+ <0 0x1a244700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "free_ck";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy2: usb-phy@1a244000 {
+ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
+ reg = <0 0x1a244000 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port1: usb-phy@1a244800 {
+ reg = <0 0x1a244800 0 0x0100>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb-phy@1a244900 {
+ reg = <0 0x1a244900 0 0x0700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt7623-ethsys",
+ "mediatek,mt2701-ethsys",
+ "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt2701-eth", "syscon";
+ reg = <0 0x1b100000 0 0x20000>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&ethsys CLK_ETHSYS_ESW>,
+ <&ethsys CLK_ETHSYS_GP1>,
+ <&ethsys CLK_ETHSYS_GP2>,
+ <&apmixedsys CLK_APMIXED_TRGPLL>;
+ clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,pctl = <&syscfg_pctl_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ crypto: crypto@1b240000 {
+ compatible = "mediatek,mt7623-crypto";
+ reg = <0 0x1b240000 0 0x20000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&ethsys CLK_ETHSYS_CRYPTO>;
+ clock-names = "ethif","cryp";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
status = "disabled";
};
};
diff --git a/dts/src/arm/omap3-cm-t3x.dtsi b/dts/src/arm/omap3-cm-t3x.dtsi
index 57b9a028a4..fccd538324 100644
--- a/dts/src/arm/omap3-cm-t3x.dtsi
+++ b/dts/src/arm/omap3-cm-t3x.dtsi
@@ -188,7 +188,7 @@
clock-frequency = <400000>;
at24@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
diff --git a/dts/src/arm/omap3-devkit8000-common.dtsi b/dts/src/arm/omap3-devkit8000-common.dtsi
index f330c69cc6..82aa9c4a0f 100644
--- a/dts/src/arm/omap3-devkit8000-common.dtsi
+++ b/dts/src/arm/omap3-devkit8000-common.dtsi
@@ -201,7 +201,8 @@
};
&gpmc {
- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
+ ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
+ 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */
nand@0,0 {
compatible = "ti,omap2-nand";
@@ -256,12 +257,8 @@
reg = <0x680000 0xf980000>;
};
};
-};
-
-&gpmc {
- ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */
- ethernet@0,0 {
+ ethernet@6,0 {
compatible = "davicom,dm9000";
reg = <6 0x000 2
6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */
diff --git a/dts/src/arm/omap3-evm-37xx.dts b/dts/src/arm/omap3-evm-37xx.dts
index 4f9a765446..c963b31ec3 100644
--- a/dts/src/arm/omap3-evm-37xx.dts
+++ b/dts/src/arm/omap3-evm-37xx.dts
@@ -34,7 +34,15 @@
>;
};
+&hsusb2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehci_phy_pins>;
+};
+
&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
+
dss_dpi_pins1: pinmux_dss_dpi_pins2 {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
@@ -98,6 +106,37 @@
>;
};
+ /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
+ on_board_gpio_61: pinmux_ehci_port_select_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
+ >;
+ };
+
+ /* Used by OHCI and EHCI. OHCI won't work without external phy */
+ hsusb2_pins: pinmux_hsusb2_pins {
+ pinctrl-single,pins = <
+
+ /* mcspi1_cs3.hsusb2_data2 */
+ OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* mcspi2_clk.hsusb2_data7 */
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* mcspi2_simo.hsusb2_data4 */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* mcspi2_somi.hsusb2_data5 */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* mcspi2_cs0.hsusb2_data6 */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* mcspi2_cs1.hsusb2_data3 */
+ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
@@ -112,6 +151,46 @@
};
};
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_2_pins>;
+
+ ehci_phy_pins: pinmux_ehci_phy_pins {
+ pinctrl-single,pins = <
+
+ /* EHCI PHY reset GPIO etk_d7.gpio_21 */
+ OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
+
+ /* EHCI VBUS etk_d8.gpio_22 */
+ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
+ >;
+ };
+
+ /* Used by OHCI and EHCI. OHCI won't work without external phy */
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+
+ /* etk_d10.hsusb2_clk */
+ OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
+
+ /* etk_d11.hsusb2_stp */
+ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
+
+ /* etk_d12.hsusb2_dir */
+ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* etk_d13.hsusb2_nxt */
+ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* etk_d14.hsusb2_data0 */
+ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+ /* etk_d15.hsusb2_data1 */
+ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+};
+
&omap3_pmx_wkup {
dss_dpi_pins2: pinmux_dss_dpi_pins1 {
pinctrl-single,pins = <
@@ -153,6 +232,29 @@
pinctrl-0 = <&uart3_pins>;
};
+/*
+ * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
+ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
+ */
+&gpio2 {
+ en_usb2_port {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
+ output-low;
+ line-name = "enable usb2 port";
+ };
+};
+
+/* T2_GPIO_2 low to route GPIO_61 to on-board devices */
+&twl_gpio {
+ en_on_board_gpio_61 {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "en_hsusb2_clk";
+ };
+};
+
&gpmc {
ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
<5 0 0x2c000000 0x01000000>;
diff --git a/dts/src/arm/omap3-evm-common.dtsi b/dts/src/arm/omap3-evm-common.dtsi
index 090475083c..2b1d6977a5 100644
--- a/dts/src/arm/omap3-evm-common.dtsi
+++ b/dts/src/arm/omap3-evm-common.dtsi
@@ -12,6 +12,24 @@
};
};
+ /* HS USB Port 2 Power */
+ hsusb2_power: hsusb2_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb2_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 2 */
+ hsusb2_phy: hsusb2_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
+ vcc-supply = <&hsusb2_power>;
+ };
+
leds {
compatible = "gpio-leds";
ledb {
@@ -76,7 +94,6 @@
&lcd_3v3 {
gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */
- enable-active-low;
};
&lcd0 {
@@ -143,6 +160,14 @@
>;
};
+&usbhshost {
+ port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <0 &hsusb2_phy>;
+};
+
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
@@ -159,3 +184,10 @@
reg = <5 0 0xff>;
};
};
+
+&vaux2 {
+ regulator-name = "usb_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi
index 9ec7370693..4504908c23 100644
--- a/dts/src/arm/omap3-gta04.dtsi
+++ b/dts/src/arm/omap3-gta04.dtsi
@@ -419,7 +419,7 @@
/* RFID EEPROM */
m24lr64@50 {
- compatible = "at,24c64";
+ compatible = "atmel,24c64";
reg = <0x50>;
};
};
diff --git a/dts/src/arm/omap3-overo-base.dtsi b/dts/src/arm/omap3-overo-base.dtsi
index 401fae838f..cd220342a8 100644
--- a/dts/src/arm/omap3-overo-base.dtsi
+++ b/dts/src/arm/omap3-overo-base.dtsi
@@ -74,16 +74,6 @@
gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */
startup-delay-us = <10000>;
};
-
- /* Regulator to trigger the nReset signal of the Bluetooth module */
- w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
- compatible = "regulator-fixed";
- regulator-name = "regulator-w3cbw003c-bt-nreset";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */
- startup-delay-us = <10000>;
- };
};
&omap3_pmx_core {
@@ -191,7 +181,6 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&w3cbw003c_npoweron>;
- vqmmc-supply = <&w3cbw003c_bt_nreset>;
vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
bus-width = <4>;
cap-sdio-irq;
diff --git a/dts/src/arm/omap3-sb-t35.dtsi b/dts/src/arm/omap3-sb-t35.dtsi
index 73643fabde..4476fb685a 100644
--- a/dts/src/arm/omap3-sb-t35.dtsi
+++ b/dts/src/arm/omap3-sb-t35.dtsi
@@ -50,7 +50,6 @@
pinctrl-names = "default";
pinctrl-0 = <&sb_t35_audio_amp>;
gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */
- enable-active-low;
regulator-always-on;
};
};
@@ -90,7 +89,7 @@
clock-frequency = <400000>;
at24@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
diff --git a/dts/src/arm/omap3-tao3530.dtsi b/dts/src/arm/omap3-tao3530.dtsi
index dc80886b53..06ac0f80bc 100644
--- a/dts/src/arm/omap3-tao3530.dtsi
+++ b/dts/src/arm/omap3-tao3530.dtsi
@@ -63,7 +63,6 @@
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
- enable-active-low;
startup-delay-us = <10000>;
};
};
diff --git a/dts/src/arm/omap4-droid4-xt894.dts b/dts/src/arm/omap4-droid4-xt894.dts
index 89eb607f4a..10ca1c1749 100644
--- a/dts/src/arm/omap4-droid4-xt894.dts
+++ b/dts/src/arm/omap4-droid4-xt894.dts
@@ -301,7 +301,7 @@
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
- compatible = "ti,wl1283";
+ compatible = "ti,wl1285", "ti,wl1283";
reg = <2>;
interrupt-parent = <&gpio4>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */
@@ -348,6 +348,17 @@
interrupt-names = "irq", "wakeup";
wakeup-source;
};
+
+ isl29030@44 {
+ compatible = "isil,isl29030";
+ reg = <0x44>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&als_proximity_pins>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
+ };
};
&omap4_pmx_core {
@@ -395,6 +406,12 @@
>;
};
+ als_proximity_pins: pinmux_als_proximity_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
usb_ulpi_pins: pinmux_usb_ulpi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -453,6 +470,15 @@
OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
>;
};
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */
+ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */
+ OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */
+ OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
+ >;
+ };
};
&omap4_pmx_wkup {
@@ -469,6 +495,17 @@
&omap4_pmx_core 0x17c>;
};
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+
+ bluetooth {
+ compatible = "ti,wl1285-st";
+ enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */
+ max-speed = <3686400>;
+ };
+};
+
&usbhsehci {
phys = <&hsusb1_phy>;
};
diff --git a/dts/src/arm/omap4-duovero.dtsi b/dts/src/arm/omap4-duovero.dtsi
index ec0bd9779e..6e6810c258 100644
--- a/dts/src/arm/omap4-duovero.dtsi
+++ b/dts/src/arm/omap4-duovero.dtsi
@@ -12,6 +12,10 @@
model = "Gumstix Duovero";
compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
+ chosen {
+ stdout-path = &uart3;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/dts/src/arm/omap4-var-som-om44.dtsi b/dts/src/arm/omap4-var-som-om44.dtsi
index 758b6eb7ae..6500bfc8d1 100644
--- a/dts/src/arm/omap4-var-som-om44.dtsi
+++ b/dts/src/arm/omap4-var-som-om44.dtsi
@@ -241,7 +241,7 @@
};
eeprom@50 {
- compatible = "microchip,24c32";
+ compatible = "microchip,24c32", "atmel,24c32";
reg = <0x50>;
};
};
diff --git a/dts/src/arm/omap4.dtsi b/dts/src/arm/omap4.dtsi
index 578c53f083..64d00f5893 100644
--- a/dts/src/arm/omap4.dtsi
+++ b/dts/src/arm/omap4.dtsi
@@ -900,15 +900,24 @@
ctrl-module = <&omap_control_usbotg>;
};
- aes: aes@4b501000 {
+ aes1: aes@4b501000 {
compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
+ ti,hwmods = "aes1";
reg = <0x4b501000 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
+ aes2: aes@4b701000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes2";
+ reg = <0x4b701000 0xa0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 114>, <&sdma 113>;
+ dma-names = "tx", "rx";
+ };
+
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
@@ -918,6 +927,15 @@
dma-names = "tx", "rx";
};
+ sham: sham@4b100000 {
+ compatible = "ti,omap4-sham";
+ ti,hwmods = "sham";
+ reg = <0x4b100000 0x300>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 119>;
+ dma-names = "rx";
+ };
+
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v2";
regulator-name = "abb_mpu";
diff --git a/dts/src/arm/omap44xx-clocks.dtsi b/dts/src/arm/omap44xx-clocks.dtsi
index 9573b37fba..05732ed4f5 100644
--- a/dts/src/arm/omap44xx-clocks.dtsi
+++ b/dts/src/arm/omap44xx-clocks.dtsi
@@ -357,6 +357,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <931200000>;
};
dpll_iva_x2_ck: dpll_iva_x2_ck {
@@ -374,6 +376,8 @@
reg = <0x01b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m4x2_ck>;
+ assigned-clock-rates = <465600000>;
};
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
@@ -385,6 +389,8 @@
reg = <0x01bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m5x2_ck>;
+ assigned-clock-rates = <266100000>;
};
dpll_mpu_ck: dpll_mpu_ck@160 {
@@ -969,22 +975,6 @@
ti,max-div = <2>;
};
- aes1_fck: aes1_fck@15a0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3_div_ck>;
- ti,bit-shift = <1>;
- reg = <0x15a0>;
- };
-
- aes2_fck: aes2_fck@15a8 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3_div_ck>;
- ti,bit-shift = <1>;
- reg = <0x15a8>;
- };
-
dss_sys_clk: dss_sys_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
diff --git a/dts/src/arm/omap5-cm-t54.dts b/dts/src/arm/omap5-cm-t54.dts
index b153f60493..78397f66d0 100644
--- a/dts/src/arm/omap5-cm-t54.dts
+++ b/dts/src/arm/omap5-cm-t54.dts
@@ -404,7 +404,7 @@
clock-frequency = <400000>;
at24@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
diff --git a/dts/src/arm/omap5-sbc-t54.dts b/dts/src/arm/omap5-sbc-t54.dts
index 337bbbc01a..7b8810d132 100644
--- a/dts/src/arm/omap5-sbc-t54.dts
+++ b/dts/src/arm/omap5-sbc-t54.dts
@@ -44,7 +44,7 @@
clock-frequency = <400000>;
at24@50 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
diff --git a/dts/src/arm/omap5-uevm.dts b/dts/src/arm/omap5-uevm.dts
index 0d42c46f13..ec2c8baef6 100644
--- a/dts/src/arm/omap5-uevm.dts
+++ b/dts/src/arm/omap5-uevm.dts
@@ -137,6 +137,13 @@
};
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+
+ cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
+};
+
&omap5_pmx_core {
evm_keys_pins: pinmux_evm_keys_gpio_pins {
pinctrl-single,pins = <
@@ -150,6 +157,12 @@
OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
>;
};
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
+ >;
+ };
};
&tpd12s015 {
diff --git a/dts/src/arm/omap54xx-clocks.dtsi b/dts/src/arm/omap54xx-clocks.dtsi
index 4899c2359d..5291934426 100644
--- a/dts/src/arm/omap54xx-clocks.dtsi
+++ b/dts/src/arm/omap54xx-clocks.dtsi
@@ -315,6 +315,8 @@
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <1165000000>;
};
dpll_iva_x2_ck: dpll_iva_x2_ck {
@@ -330,6 +332,8 @@
ti,max-div = <63>;
reg = <0x01b8>;
ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h11x2_ck>;
+ assigned-clock-rates = <465920000>;
};
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
@@ -339,6 +343,8 @@
ti,max-div = <63>;
reg = <0x01bc>;
ti,index-starts-at-one;
+ assigned-clocks = <&dpll_iva_h12x2_ck>;
+ assigned-clock-rates = <388300000>;
};
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
diff --git a/dts/src/arm/owl-s500-guitar-bb-rev-b.dts b/dts/src/arm/owl-s500-guitar-bb-rev-b.dts
new file mode 100644
index 0000000000..521463d4ca
--- /dev/null
+++ b/dts/src/arm/owl-s500-guitar-bb-rev-b.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "owl-s500-guitar.dtsi"
+
+/ {
+ compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500";
+ model = "LeMaker Guitar Base Board rev. B";
+
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/dts/src/arm/owl-s500-guitar.dtsi b/dts/src/arm/owl-s500-guitar.dtsi
new file mode 100644
index 0000000000..079b2c02cc
--- /dev/null
+++ b/dts/src/arm/owl-s500-guitar.dtsi
@@ -0,0 +1,22 @@
+/*
+ * LeMaker Guitar SoM
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "owl-s500.dtsi"
+
+/ {
+ compatible = "lemaker,guitar", "actions,s500";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&timer {
+ clocks = <&hosc>;
+};
diff --git a/dts/src/arm/owl-s500.dtsi b/dts/src/arm/owl-s500.dtsi
new file mode 100644
index 0000000000..51a48741d4
--- /dev/null
+++ b/dts/src/arm/owl-s500.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Actions Semi S500 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "actions,s500";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x0>;
+ enable-method = "actions,s500-smp";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x1>;
+ enable-method = "actions,s500-smp";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x2>;
+ enable-method = "actions,s500-smp";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x3>;
+ enable-method = "actions,s500-smp";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ hosc: hosc {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ scu: scu@b0020000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xb0020000 0x100>;
+ };
+
+ global_timer: timer@b0020200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xb0020200 0x100>;
+ interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ status = "disabled";
+ };
+
+ twd_timer: timer@b0020600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xb0020600 0x20>;
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ status = "disabled";
+ };
+
+ twd_wdt: wdt@b0020620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0xb0020620 0xe0>;
+ interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@b0021000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0xb0021000 0x1000>,
+ <0xb0020100 0x0100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ l2: cache-controller@b0022000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xb0022000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ arm,tag-latency = <3 3 2>;
+ arm,data-latency = <5 3 3>;
+ };
+
+ uart0: serial@b0120000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0120000 0x2000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: serial@b0122000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0122000 0x2000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@b0124000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0124000 0x2000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: serial@b0126000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0126000 0x2000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@b0128000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0128000 0x2000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart5: serial@b012a000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb012a000 0x2000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart6: serial@b012c000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb012c000 0x2000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer: timer@b0168000 {
+ compatible = "actions,s500-timer";
+ reg = <0xb0168000 0x8000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
+ };
+
+ sps: power-controller@b01b0100 {
+ compatible = "actions,s500-sps";
+ reg = <0xb01b0100 0x100>;
+ #power-domain-cells = <1>;
+ };
+ };
+};
diff --git a/dts/src/arm/pm9g45.dts b/dts/src/arm/pm9g45.dts
index 0abd7bf175..3139221737 100644
--- a/dts/src/arm/pm9g45.dts
+++ b/dts/src/arm/pm9g45.dts
@@ -37,12 +37,10 @@
};
pinctrl@fffff200 {
-
- board {
- pinctrl_board_nand: nand0-board {
+ nand {
+ pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
- <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD3 gpio RDY pin pull_up*/
- AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
+ <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
@@ -71,50 +69,61 @@
phy-mode = "rmii";
status = "okay";
};
-
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- pinctrl-0 = <&pinctrl_board_nand>;
-
- gpios = <&pioD 3 GPIO_ACTIVE_HIGH
- &pioC 14 GPIO_ACTIVE_HIGH
- 0
- >;
-
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x1A0000>;
- };
-
- kernel@200000 {
- label = "bareboxenv2";
- reg = <0x200000 0x300000>;
- };
-
- kernel@500000 {
- label = "root";
- reg = <0x500000 0x400000>;
- };
-
- data@900000 {
- label = "data";
- reg = <0x900000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x1A0000>;
+ };
+
+ kernel@200000 {
+ label = "bareboxenv2";
+ reg = <0x200000 0x300000>;
+ };
+
+ kernel@500000 {
+ label = "root";
+ reg = <0x500000 0x400000>;
+ };
+
+ data@900000 {
+ label = "data";
+ reg = <0x900000 0x8340000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/pxa25x.dtsi b/dts/src/arm/pxa25x.dtsi
index f9f4726396..95d59be972 100644
--- a/dts/src/arm/pxa25x.dtsi
+++ b/dts/src/arm/pxa25x.dtsi
@@ -93,22 +93,22 @@
pxa250_opp_table: opp_table0 {
compatible = "operating-points-v2";
- opp@99532800 {
+ opp-99532800 {
opp-hz = /bits/ 64 <99532800>;
opp-microvolt = <1000000 950000 1650000>;
clock-latency-ns = <20>;
};
- opp@199065600 {
+ opp-199065600 {
opp-hz = /bits/ 64 <199065600>;
opp-microvolt = <1000000 950000 1650000>;
clock-latency-ns = <20>;
};
- opp@298598400 {
+ opp-298598400 {
opp-hz = /bits/ 64 <298598400>;
opp-microvolt = <1100000 1045000 1650000>;
clock-latency-ns = <20>;
};
- opp@398131200 {
+ opp-398131200 {
opp-hz = /bits/ 64 <398131200>;
opp-microvolt = <1300000 1235000 1650000>;
clock-latency-ns = <20>;
diff --git a/dts/src/arm/pxa27x.dtsi b/dts/src/arm/pxa27x.dtsi
index e0fab48ba6..5f1d6da02a 100644
--- a/dts/src/arm/pxa27x.dtsi
+++ b/dts/src/arm/pxa27x.dtsi
@@ -141,37 +141,37 @@
pxa270_opp_table: opp_table0 {
compatible = "operating-points-v2";
- opp@104000000 {
+ opp-104000000 {
opp-hz = /bits/ 64 <104000000>;
opp-microvolt = <900000 900000 1705000>;
clock-latency-ns = <20>;
};
- opp@156000000 {
+ opp-156000000 {
opp-hz = /bits/ 64 <156000000>;
opp-microvolt = <1000000 1000000 1705000>;
clock-latency-ns = <20>;
};
- opp@208000000 {
+ opp-208000000 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <1180000 1180000 1705000>;
clock-latency-ns = <20>;
};
- opp@312000000 {
+ opp-312000000 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <1250000 1250000 1705000>;
clock-latency-ns = <20>;
};
- opp@416000000 {
+ opp-416000000 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <1350000 1350000 1705000>;
clock-latency-ns = <20>;
};
- opp@520000000 {
+ opp-520000000 {
opp-hz = /bits/ 64 <520000000>;
opp-microvolt = <1450000 1450000 1705000>;
clock-latency-ns = <20>;
};
- opp@624000000 {
+ opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <1550000 1550000 1705000>;
clock-latency-ns = <20>;
diff --git a/dts/src/arm/qcom-apq8060-dragonboard.dts b/dts/src/arm/qcom-apq8060-dragonboard.dts
index 2da1413f57..9d725f9832 100644
--- a/dts/src/arm/qcom-apq8060-dragonboard.dts
+++ b/dts/src/arm/qcom-apq8060-dragonboard.dts
@@ -23,6 +23,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include "qcom-msm8660.dtsi"
/ {
@@ -83,6 +84,25 @@
};
};
+ /*
+ * Capella CM3605 light and proximity sensor mounted directly
+ * on the sensor board.
+ */
+ cm3605 {
+ compatible = "capella,cm3605";
+ vdd-supply = <&pm8058_l14>; // 2.85V
+ aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>;
+ capella,aset-resistance-ohms = <100000>;
+ /* GPIO34 has interrupt 225 on the PM8058 */
+ /* Trig on both edges - getting close or far away */
+ interrupts-extended = <&pm8058 225 IRQ_TYPE_EDGE_BOTH>;
+ /* MPP05 analog input to the XOADC */
+ io-channels = <&xoadc 0x00 0x05>;
+ io-channel-names = "aout";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>;
+ };
+
soc {
pinctrl@800000 {
/* eMMMC pins, all 8 data lines connected */
@@ -160,6 +180,19 @@
};
};
+ dragon_gsbi8_i2c_pins: gsbi8_i2c {
+ mux {
+ pins = "gpio64", "gpio65";
+ function = "gsbi8";
+ };
+ pinconf {
+ pins = "gpio64", "gpio65";
+ drive-strength = <16>;
+ /* These have external pull-up 2.2kOhm to 1.8V */
+ bias-disable;
+ };
+ };
+
dragon_gsbi12_i2c_pins: gsbi12_i2c {
mux {
pins = "gpio115", "gpio116";
@@ -317,6 +350,24 @@
power-source = <PM8058_GPIO_S3>;
};
};
+ dragon_cm3605_gpios: cm3605-gpios {
+ /* Pin 34 connected to the proxy IRQ */
+ pinconf_gpio34 {
+ pins = "gpio34";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ /* Pin 35 connected to ASET */
+ pinconf_gpio35 {
+ pins = "gpio35";
+ function = "normal";
+ output-high;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
dragon_veth_gpios: veth-gpios {
pinconf {
pins = "gpio40";
@@ -327,6 +378,47 @@
};
};
+ mpps@50 {
+ dragon_cm3605_mpps: cm3605-mpps {
+ pinconf {
+ pins = "mpp5";
+ function = "analog";
+ input-enable;
+ bias-high-impedance;
+ /* Let's use channel 5 */
+ qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ };
+
+ xoadc@197 {
+ /* Reference voltage 2.2 V */
+ xoadc-ref-supply = <&pm8058_l18>;
+
+ /* Board-specific channels */
+ mpp5@05 {
+ /* Connected to AOUT of ALS sensor */
+ reg = <0x00 0x05>;
+ };
+ mpp6@06 {
+ /* Connected to test point TP43 */
+ reg = <0x00 0x06>;
+ };
+ mpp7@07 {
+ /* Connected to battery thermistor */
+ reg = <0x00 0x07>;
+ };
+ mpp8@08 {
+ /* Connected to battery ID detector */
+ reg = <0x00 0x08>;
+ };
+ mpp9@09 {
+ /* Connected to XO thermistor */
+ reg = <0x00 0x09>;
+ };
+ };
+
led@48 {
/*
* The keypad LED @0x48 is routed to
@@ -340,6 +432,7 @@
reg = <0x48>;
label = "pm8058:infrared:proximitysensor";
default-state = "off";
+ linux,default-trigger = "cm3605";
};
led@131 {
compatible = "qcom,pm8058-led";
@@ -368,6 +461,42 @@
};
};
+ gsbi@19800000 {
+ status = "ok";
+ qcom,mode = <GSBI_PROT_I2C>;
+
+ i2c@19880000 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_gsbi8_i2c_pins>;
+
+ eeprom@52 {
+ /* A 16KiB Platform ID EEPROM on the CPU carrier board */
+ compatible = "atmel,24c128";
+ reg = <0x52>;
+ vcc-supply = <&pm8058_s3>;
+ pagesize = <64>;
+ };
+ wm8903: wm8903@1a {
+ /* This Woolfson Micro device has an unrouted interrupt line */
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ AVDD-supply = <&pm8058_l16>;
+ CPVDD-supply = <&pm8058_l16>;
+ DBVDD-supply = <&pm8058_s3>;
+ DCVDD-supply = <&pm8058_l0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+ };
+ };
+
gsbi@19c00000 {
status = "ok";
qcom,mode = <GSBI_PROT_I2C_UART>;
diff --git a/dts/src/arm/qcom-apq8064-arrow-sd-600eval.dts b/dts/src/arm/qcom-apq8064-arrow-sd-600eval.dts
index 8f5de029bc..f245064f32 100644
--- a/dts/src/arm/qcom-apq8064-arrow-sd-600eval.dts
+++ b/dts/src/arm/qcom-apq8064-arrow-sd-600eval.dts
@@ -320,43 +320,37 @@
};
/* OTG */
- phy@12500000 {
- status = "okay";
- dr_mode = "peripheral";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
-
- phy@12520000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- phy@12530000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- gadget@12500000 {
- status = "okay";
- };
-
- /* OTG */
usb@12500000 {
status = "okay";
+ dr_mode = "peripheral";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+ };
+ };
};
usb@12520000 {
status = "okay";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
usb@12530000 {
status = "okay";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
amba {
diff --git a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
index e39440a867..3483a66e44 100644
--- a/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
+++ b/dts/src/arm/qcom-apq8064-asus-nexus7-flo.dts
@@ -321,21 +321,15 @@
};
/* OTG */
- phy@12500000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- dr_mode = "otg";
- };
-
- gadget@12500000 {
- status = "okay";
- };
-
- /* OTG */
usb@12500000 {
status = "okay";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+ };
+ };
};
amba {
diff --git a/dts/src/arm/qcom-apq8064-cm-qs600.dts b/dts/src/arm/qcom-apq8064-cm-qs600.dts
index 35f1d46edd..5b151e4255 100644
--- a/dts/src/arm/qcom-apq8064-cm-qs600.dts
+++ b/dts/src/arm/qcom-apq8064-cm-qs600.dts
@@ -150,42 +150,37 @@
};
/* OTG */
- usb1_phy: phy@12500000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
-
- usb3_phy: phy@12520000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- usb4_phy: phy@12530000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- gadget1: gadget@12500000 {
- status = "ok";
- };
-
- /* OTG */
- usb1: usb@12500000 {
+ usb@12500000 {
status = "ok";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+ };
+ };
};
- usb3: usb@12520000 {
+ usb@12520000 {
status = "okay";
+ dr_mode = "host";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
- usb4: usb@12530000 {
+ usb@12530000 {
status = "okay";
+ dr_mode = "host";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
/* on board fixed 3.3v supply */
diff --git a/dts/src/arm/qcom-apq8064-ifc6410.dts b/dts/src/arm/qcom-apq8064-ifc6410.dts
index 881ce70731..053b5bdd78 100644
--- a/dts/src/arm/qcom-apq8064-ifc6410.dts
+++ b/dts/src/arm/qcom-apq8064-ifc6410.dts
@@ -244,42 +244,37 @@
};
/* OTG */
- usb1_phy: phy@12500000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
-
- usb3_phy: phy@12520000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- usb4_phy: phy@12530000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
-
- gadget1: gadget@12500000 {
- status = "okay";
- };
-
- /* OTG */
- usb1: usb@12500000 {
+ usb@12500000 {
status = "okay";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+ };
+ };
};
- usb3: usb@12520000 {
+ usb@12520000 {
status = "okay";
+ dr_mode = "host";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
- usb4: usb@12530000 {
+ usb@12530000 {
status = "okay";
+ dr_mode = "host";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+ };
+ };
};
pci@1b500000 {
diff --git a/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts b/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
index a34ba35554..88a9aff41e 100644
--- a/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
+++ b/dts/src/arm/qcom-apq8064-sony-xperia-yuga.dts
@@ -349,15 +349,15 @@
};
};
- phy@12500000 {
- status = "okay";
- vddcx-supply = <&pm8921_s3>;
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
-
- gadget@12500000 {
+ usb@12500000 {
status = "okay";
+ dr_mode = "otg";
+ ulpi {
+ phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+ };
+ };
};
gsbi@1a200000 {
diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi
index 14a6f5ed02..f3db185a68 100644
--- a/dts/src/arm/qcom-apq8064.dtsi
+++ b/dts/src/arm/qcom-apq8064.dtsi
@@ -197,7 +197,7 @@
clock-frequency = <27000000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -884,81 +884,97 @@
};
};
- usb1_phy: phy@12500000 {
- compatible = "qcom,usb-otg-ci";
- reg = <0x12500000 0x400>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
- status = "disabled";
-
- clocks = <&gcc USB_HS1_XCVR_CLK>,
- <&gcc USB_HS1_H_CLK>;
- clock-names = "core", "iface";
-
- resets = <&gcc USB_HS1_RESET>;
- reset-names = "link";
- };
-
- usb3_phy: phy@12520000 {
- compatible = "qcom,usb-otg-ci";
- reg = <0x12520000 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
- status = "disabled";
- dr_mode = "host";
-
- clocks = <&gcc USB_HS3_XCVR_CLK>,
- <&gcc USB_HS3_H_CLK>;
- clock-names = "core", "iface";
-
- resets = <&gcc USB_HS3_RESET>;
- reset-names = "link";
- };
-
- usb4_phy: phy@12530000 {
- compatible = "qcom,usb-otg-ci";
- reg = <0x12530000 0x400>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
- status = "disabled";
- dr_mode = "host";
-
- clocks = <&gcc USB_HS4_XCVR_CLK>,
- <&gcc USB_HS4_H_CLK>;
- clock-names = "core", "iface";
-
- resets = <&gcc USB_HS4_RESET>;
- reset-names = "link";
- };
-
- gadget1: gadget@12500000 {
- compatible = "qcom,ci-hdrc";
- reg = <0x12500000 0x400>;
- status = "disabled";
- dr_mode = "peripheral";
- interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
- usb-phy = <&usb1_phy>;
- };
-
usb1: usb@12500000 {
- compatible = "qcom,ehci-host";
- reg = <0x12500000 0x400>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
- status = "disabled";
- usb-phy = <&usb1_phy>;
+ compatible = "qcom,ci-hdrc";
+ reg = <0x12500000 0x200>,
+ <0x12500200 0x200>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
+ clock-names = "core", "iface";
+ assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
+ assigned-clock-rates = <60000000>;
+ resets = <&gcc USB_HS1_RESET>;
+ reset-names = "core";
+ phy_type = "ulpi";
+ ahb-burst-config = <0>;
+ phys = <&usb_hs1_phy>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ #reset-cells = <1>;
+
+ ulpi {
+ usb_hs1_phy: phy {
+ compatible = "qcom,usb-hs-phy-apq8064",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&sleep_clk>, <&cxo_board>;
+ clock-names = "sleep", "ref";
+ resets = <&usb1 0>;
+ reset-names = "por";
+ };
+ };
};
usb3: usb@12520000 {
- compatible = "qcom,ehci-host";
- reg = <0x12520000 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
- status = "disabled";
- usb-phy = <&usb3_phy>;
+ compatible = "qcom,ci-hdrc";
+ reg = <0x12520000 0x200>,
+ <0x12520200 0x200>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
+ clock-names = "core", "iface";
+ assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
+ assigned-clock-rates = <60000000>;
+ resets = <&gcc USB_HS3_RESET>;
+ reset-names = "core";
+ phy_type = "ulpi";
+ ahb-burst-config = <0>;
+ phys = <&usb_hs3_phy>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ #reset-cells = <1>;
+
+ ulpi {
+ usb_hs3_phy: phy {
+ compatible = "qcom,usb-hs-phy-apq8064",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&sleep_clk>, <&cxo_board>;
+ clock-names = "sleep", "ref";
+ resets = <&usb3 0>;
+ reset-names = "por";
+ };
+ };
};
usb4: usb@12530000 {
- compatible = "qcom,ehci-host";
- reg = <0x12530000 0x400>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
- status = "disabled";
- usb-phy = <&usb4_phy>;
+ compatible = "qcom,ci-hdrc";
+ reg = <0x12530000 0x200>,
+ <0x12530200 0x200>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
+ clock-names = "core", "iface";
+ assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
+ assigned-clock-rates = <60000000>;
+ resets = <&gcc USB_HS4_RESET>;
+ reset-names = "core";
+ phy_type = "ulpi";
+ ahb-burst-config = <0>;
+ phys = <&usb_hs4_phy>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ #reset-cells = <1>;
+
+ ulpi {
+ usb_hs4_phy: phy {
+ compatible = "qcom,usb-hs-phy-apq8064",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&sleep_clk>, <&cxo_board>;
+ clock-names = "sleep", "ref";
+ resets = <&usb4 0>;
+ reset-names = "por";
+ };
+ };
};
sata_phy0: phy@1b400000 {
diff --git a/dts/src/arm/qcom-apq8074-dragonboard.dts b/dts/src/arm/qcom-apq8074-dragonboard.dts
index ad51df27df..32f3b81f60 100644
--- a/dts/src/arm/qcom-apq8074-dragonboard.dts
+++ b/dts/src/arm/qcom-apq8074-dragonboard.dts
@@ -44,6 +44,26 @@
vqmmc-supply = <&pm8941_l13>;
};
+ usb@f9a55000 {
+ status = "ok";
+ phys = <&usb_hs2_phy>;
+ phy-select = <&tcsr 0xb000 1>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ ulpi {
+ phy@b {
+ status = "ok";
+ v3p3-supply = <&pm8941_l24>;
+ v1p8-supply = <&pm8941_l6>;
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x63>;
+ };
+ };
+ };
+
pinctrl@fd510000 {
i2c11_pins: i2c11 {
diff --git a/dts/src/arm/qcom-ipq4019.dtsi b/dts/src/arm/qcom-ipq4019.dtsi
index b7a24af8f4..4b7d97275c 100644
--- a/dts/src/arm/qcom-ipq4019.dtsi
+++ b/dts/src/arm/qcom-ipq4019.dtsi
@@ -154,10 +154,10 @@
i2c_0: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78b7000 0x6000>;
+ reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/qcom-ipq8064.dtsi b/dts/src/arm/qcom-ipq8064.dtsi
index 76f4e8921d..f1fbffe59b 100644
--- a/dts/src/arm/qcom-ipq8064.dtsi
+++ b/dts/src/arm/qcom-ipq8064.dtsi
@@ -284,6 +284,29 @@
};
};
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <7>;
+ reg = <0x16600000 0x100>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ syscon-tcsr = <&tcsr>;
+
+ gsbi7_serial: serial@16640000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16640000 0x1000>,
+ <0x16600000 0x1000>;
+ interrupts = <0 158 0x0>;
+ clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+ };
+
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;
diff --git a/dts/src/arm/qcom-msm8660.dtsi b/dts/src/arm/qcom-msm8660.dtsi
index 747669a62a..1b5d31b33b 100644
--- a/dts/src/arm/qcom-msm8660.dtsi
+++ b/dts/src/arm/qcom-msm8660.dtsi
@@ -63,6 +63,22 @@
};
};
+ /*
+ * These channels from the ADC are simply hardware monitors.
+ * That is why the ADC is referred to as "HKADC" - HouseKeeping
+ * ADC.
+ */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&xoadc 0x00 0x01>, /* Battery */
+ <&xoadc 0x00 0x02>, /* DC in (charger) */
+ <&xoadc 0x00 0x04>, /* VPH the main system voltage */
+ <&xoadc 0x00 0x0b>, /* Die temperature */
+ <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+ <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+ <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -107,6 +123,31 @@
reg = <0x900000 0x4000>;
};
+
+ gsbi8: gsbi@19800000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <12>;
+ reg = <0x19800000 0x100>;
+ clocks = <&gcc GSBI8_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi8_i2c: i2c@19880000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x19880000 0x1000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
+ clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
gsbi12: gsbi@19c00000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <12>;
@@ -267,6 +308,49 @@
row-hold = <91500>;
};
+ xoadc: xoadc@197 {
+ compatible = "qcom,pm8058-adc";
+ reg = <0x197>;
+ interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@00 {
+ reg = <0x00 0x00>;
+ };
+ vbat: adc-channel@01 {
+ reg = <0x00 0x01>;
+ };
+ dcin: adc-channel@02 {
+ reg = <0x00 0x02>;
+ };
+ ichg: adc-channel@03 {
+ reg = <0x00 0x03>;
+ };
+ vph_pwr: adc-channel@04 {
+ reg = <0x00 0x04>;
+ };
+ usb_vbus: adc-channel@0a {
+ reg = <0x00 0x0a>;
+ };
+ die_temp: adc-channel@0b {
+ reg = <0x00 0x0b>;
+ };
+ ref_625mv: adc-channel@0c {
+ reg = <0x00 0x0c>;
+ };
+ ref_1250mv: adc-channel@0d {
+ reg = <0x00 0x0d>;
+ };
+ ref_325mv: adc-channel@0e {
+ reg = <0x00 0x0e>;
+ };
+ ref_muxoff: adc-channel@0f {
+ reg = <0x00 0x0f>;
+ };
+ };
+
rtc@1e8 {
compatible = "qcom,pm8058-rtc";
reg = <0x1e8>;
diff --git a/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts b/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts
index e7c1577d56..50966378f9 100644
--- a/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts
+++ b/dts/src/arm/qcom-msm8974-sony-xperia-honami.dts
@@ -92,7 +92,6 @@
vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
vdd_l21-supply = <&vreg_boost>;
- vin_5vs-supply = <&pm8941_5v>;
s1 {
regulator-min-microvolt = <1300000>;
diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi
index 307bf6a647..c5ee68a3f7 100644
--- a/dts/src/arm/qcom-msm8974.dtsi
+++ b/dts/src/arm/qcom-msm8974.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
@@ -551,6 +552,11 @@
reg = <0xfc400000 0x4000>;
};
+ tcsr: syscon@fd4a0000 {
+ compatible = "syscon";
+ reg = <0xfd4a0000 0x10000>;
+ };
+
tcsr_mutex_block: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
@@ -620,6 +626,50 @@
status = "disabled";
};
+ otg: usb@f9a55000 {
+ compatible = "qcom,ci-hdrc";
+ reg = <0xf9a55000 0x200>,
+ <0xf9a55200 0x200>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ clock-names = "iface", "core";
+ assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <75000000>;
+ resets = <&gcc GCC_USB_HS_BCR>;
+ reset-names = "core";
+ phy_type = "ulpi";
+ dr_mode = "otg";
+ ahb-burst-config = <0>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ #reset-cells = <1>;
+
+ ulpi {
+ usb_hs1_phy: phy@a {
+ compatible = "qcom,usb-hs-phy-msm8974",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+ reset-names = "phy", "por";
+ status = "disabled";
+ };
+
+ usb_hs2_phy: phy@b {
+ compatible = "qcom,usb-hs-phy-msm8974",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
+ reset-names = "phy", "por";
+ status = "disabled";
+ };
+ };
+ };
+
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
@@ -1021,7 +1071,6 @@
pm8941_s1: s1 {};
pm8941_s2: s2 {};
pm8941_s3: s3 {};
- pm8941_5v: s4 {};
pm8941_l1: l1 {};
pm8941_l2: l2 {};
@@ -1051,9 +1100,6 @@
pm8941_lvs1: lvs1 {};
pm8941_lvs2: lvs2 {};
pm8941_lvs3: lvs3 {};
-
- pm8941_5vs1: 5vs1 {};
- pm8941_5vs2: 5vs2 {};
};
};
};
diff --git a/dts/src/arm/qcom-pm8941.dtsi b/dts/src/arm/qcom-pm8941.dtsi
index f8eb5e31c9..3fc9f34f45 100644
--- a/dts/src/arm/qcom-pm8941.dtsi
+++ b/dts/src/arm/qcom-pm8941.dtsi
@@ -26,7 +26,14 @@
bias-pull-up;
};
- charger@1000 {
+ usb_id: misc@900 {
+ compatible = "qcom,pm8941-misc";
+ reg = <0x900>;
+ interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "usb_id";
+ };
+
+ smbb: charger@1000 {
compatible = "qcom,pm8941-charger";
reg = <0x1000>;
interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
@@ -45,6 +52,10 @@
"chg-gone",
"usb-valid",
"dc-valid";
+
+ usb-otg-in-supply = <&pm8941_5vs1>;
+
+ chg_otg: otg-vbus { };
};
pm8941_gpios: gpios@c000 {
@@ -171,5 +182,28 @@
status = "disabled";
};
+
+ regulators {
+ compatible = "qcom,pm8941-regulators";
+ interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>;
+ interrupt-names = "ocp-5vs1", "ocp-5vs2";
+ vin_5vs-supply = <&pm8941_5v>;
+
+ pm8941_5v: s4 {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-enable-ramp-delay = <500>;
+ };
+
+ pm8941_5vs1: 5vs1 {
+ regulator-enable-ramp-delay = <1000>;
+ regulator-pull-down;
+ regulator-over-current-protection;
+ qcom,ocp-max-retries = <10>;
+ qcom,ocp-retry-delay = <30>;
+ qcom,vs-soft-start-strength = <0>;
+ regulator-initial-mode = <1>;
+ };
+ };
};
};
diff --git a/dts/src/arm/r7s72100-gr-peach.dts b/dts/src/arm/r7s72100-gr-peach.dts
new file mode 100644
index 0000000000..a1b2aef984
--- /dev/null
+++ b/dts/src/arm/r7s72100-gr-peach.dts
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for the GR-Peach board
+ *
+ * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Renesas Electronics
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r7s72100.dtsi"
+
+/ {
+ model = "GR-Peach";
+ compatible = "renesas,gr-peach", "renesas,r7s72100";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x00a00000>;
+
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash@18000000 {
+ compatible = "mtd-rom";
+ probe-type = "map_rom";
+ reg = <0x18000000 0x00800000>;
+ bank-width = <4>;
+ device-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ rootfs@600000 {
+ label = "rootfs";
+ reg = <0x00600000 0x00200000>;
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <13333000>;
+};
+
+&usb_x1_clk {
+ clock-frequency = <48000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/r7s72100.dtsi b/dts/src/arm/r7s72100.dtsi
index 0423996e4d..5cf53e9943 100644
--- a/dts/src/arm/r7s72100.dtsi
+++ b/dts/src/arm/r7s72100.dtsi
@@ -144,9 +144,9 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
- clocks = <&b_clk>;
- clock-indices = <R7S72100_CLK_ETHER>;
- clock-output-names = "ether";
+ clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
+ clock-output-names = "ether", "usb0", "usb1";
};
mstp8_clks: mstp8_clks@fcfe0434 {
diff --git a/dts/src/arm/r8a73a4.dtsi b/dts/src/arm/r8a73a4.dtsi
index 1f5c9f6ddd..3102226345 100644
--- a/dts/src/arm/r8a73a4.dtsi
+++ b/dts/src/arm/r8a73a4.dtsi
@@ -219,7 +219,7 @@
power-domains = <&pd_c4>;
};
- pfc: pfc@e6050000 {
+ pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a73a4";
reg = <0 0xe6050000 0 0x9000>;
gpio-controller;
diff --git a/dts/src/arm/r8a7740-armadillo800eva.dts b/dts/src/arm/r8a7740-armadillo800eva.dts
index 7885075428..1788e186a5 100644
--- a/dts/src/arm/r8a7740-armadillo800eva.dts
+++ b/dts/src/arm/r8a7740-armadillo800eva.dts
@@ -266,7 +266,9 @@
lcd0_pins: lcd0 {
groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
function = "lcd0";
+ };
+ lcd0_mux {
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;
diff --git a/dts/src/arm/r8a7740.dtsi b/dts/src/arm/r8a7740.dtsi
index 34159a8349..d37d22682a 100644
--- a/dts/src/arm/r8a7740.dtsi
+++ b/dts/src/arm/r8a7740.dtsi
@@ -299,7 +299,7 @@
status = "disabled";
};
- pfc: pfc@e6050000 {
+ pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;
diff --git a/dts/src/arm/r8a7743-iwg20d-q7.dts b/dts/src/arm/r8a7743-iwg20d-q7.dts
new file mode 100644
index 0000000000..9b54783cc2
--- /dev/null
+++ b/dts/src/arm/r8a7743-iwg20d-q7.dts
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743-iwg20m.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
+
+ aliases {
+ serial0 = &scif0;
+ };
+};
+
+&scif0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/r8a7743-iwg20m.dtsi b/dts/src/arm/r8a7743-iwg20m.dtsi
new file mode 100644
index 0000000000..001ca9144f
--- /dev/null
+++ b/dts/src/arm/r8a7743-iwg20m.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Device Tree Source for the iWave-RZG1M-20M Qseven SOM
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7743.dtsi"
+
+/ {
+ compatible = "iwave,g20m", "renesas,r8a7743";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x20000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x20000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
diff --git a/dts/src/arm/r8a7778.dtsi b/dts/src/arm/r8a7778.dtsi
index 1e93c94a9e..8f3156c0e5 100644
--- a/dts/src/arm/r8a7778.dtsi
+++ b/dts/src/arm/r8a7778.dtsi
@@ -142,7 +142,7 @@
interrupt-controller;
};
- pfc: pfc@fffc0000 {
+ pfc: pin-controller@fffc0000 {
compatible = "renesas,pfc-r8a7778";
reg = <0xfffc0000 0x118>;
};
diff --git a/dts/src/arm/r8a7779.dtsi b/dts/src/arm/r8a7779.dtsi
index ae2d9a9c65..8ee0b2ca5d 100644
--- a/dts/src/arm/r8a7779.dtsi
+++ b/dts/src/arm/r8a7779.dtsi
@@ -286,7 +286,7 @@
status = "disabled";
};
- pfc: pfc@fffc0000 {
+ pfc: pin-controller@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
};
diff --git a/dts/src/arm/r8a7790.dtsi b/dts/src/arm/r8a7790.dtsi
index 99269aaca6..2805a8608d 100644
--- a/dts/src/arm/r8a7790.dtsi
+++ b/dts/src/arm/r8a7790.dtsi
@@ -614,7 +614,7 @@
max-frequency = <97500000>;
};
- pfc: pfc@e6060000 {
+ pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe6060000 0 0x250>;
};
@@ -1602,16 +1602,14 @@
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
+ usb@1,0 {
reg = <0x800 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
- usb@0,2 {
+ usb@2,0 {
reg = <0x1000 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
@@ -1658,16 +1656,14 @@
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
- reg = <0x800 0 0 0 0>;
- device_type = "pci";
+ usb@1,0 {
+ reg = <0x20800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
- usb@0,2 {
- reg = <0x1000 0 0 0 0>;
- device_type = "pci";
+ usb@2,0 {
+ reg = <0x21000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
diff --git a/dts/src/arm/r8a7791.dtsi b/dts/src/arm/r8a7791.dtsi
index 4d0c2ce599..bd93f699ad 100644
--- a/dts/src/arm/r8a7791.dtsi
+++ b/dts/src/arm/r8a7791.dtsi
@@ -562,7 +562,7 @@
status = "disabled";
};
- pfc: pfc@e6060000 {
+ pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>;
};
@@ -776,6 +776,15 @@
status = "disabled";
};
+ adc: adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0 0xe6e54000 0 64>;
+ clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
"renesas,scif";
@@ -1425,13 +1434,15 @@
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
- clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ clocks = <&p_clk>,
+ <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
clock-indices = <
+ R8A7791_CLK_GYROADC
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
@@ -1439,6 +1450,7 @@
R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
>;
clock-output-names =
+ "gyroadc",
"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
"i2c1", "i2c0";
@@ -1601,16 +1613,14 @@
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
+ usb@1,0 {
reg = <0x800 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
- usb@0,2 {
+ usb@2,0 {
reg = <0x1000 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
@@ -1636,16 +1646,14 @@
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
- reg = <0x800 0 0 0 0>;
- device_type = "pci";
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
- usb@0,2 {
- reg = <0x1000 0 0 0 0>;
- device_type = "pci";
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
diff --git a/dts/src/arm/r8a7793-gose.dts b/dts/src/arm/r8a7793-gose.dts
index 806c93f6ae..76e3aca202 100644
--- a/dts/src/arm/r8a7793-gose.dts
+++ b/dts/src/arm/r8a7793-gose.dts
@@ -253,17 +253,38 @@
};
};
+ hdmi-in {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&adv7612_in>;
+ };
+ };
+ };
+
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
- hdmi_con: endpoint {
+ hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
+ composite-in {
+ compatible = "composite-video-connector";
+
+ port {
+ composite_con_in: endpoint {
+ remote-endpoint = <&adv7180_in>;
+ };
+ };
+ };
+
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -348,16 +369,37 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
};
qspi_pins: qspi {
@@ -374,6 +416,16 @@
groups = "audio_clk_a";
function = "audio_clk";
};
+
+ vin0_pins: vin0 {
+ groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+ function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ groups = "vin1_data8", "vin1_clk";
+ function = "vin1";
+ };
};
&ether {
@@ -416,33 +468,40 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
@@ -498,6 +557,32 @@
reg = <0x12>;
};
+ composite-in@20 {
+ compatible = "adi,adv7180cp";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7180_in: endpoint {
+ remote-endpoint = <&composite_con_in>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ adv7180_out: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+ };
+
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
@@ -524,7 +609,34 @@
port@1 {
reg = <1>;
adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
};
};
};
@@ -578,3 +690,42 @@
&ssi1 {
shared-pin;
};
+
+/* HDMI video input */
+&vin0 {
+ status = "okay";
+ pinctrl-0 = <&vin0_pins>;
+ pinctrl-names = "default";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin0ep2: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ bus-width = <24>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ data-active = <1>;
+ };
+ };
+};
+
+/* composite video input */
+&vin1 {
+ pinctrl-0 = <&vin1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1ep: endpoint {
+ remote-endpoint = <&adv7180_out>;
+ bus-width = <8>;
+ };
+ };
+};
diff --git a/dts/src/arm/r8a7793.dtsi b/dts/src/arm/r8a7793.dtsi
index 4de6041d61..13b980f27b 100644
--- a/dts/src/arm/r8a7793.dtsi
+++ b/dts/src/arm/r8a7793.dtsi
@@ -529,7 +529,7 @@
status = "disabled";
};
- pfc: pfc@e6060000 {
+ pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7793";
reg = <0 0xe6060000 0 0x250>;
};
@@ -542,6 +542,7 @@
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -554,6 +555,7 @@
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -566,6 +568,7 @@
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
status = "disabled";
};
diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi
index a19b884fb2..7d9a81d970 100644
--- a/dts/src/arm/r8a7794.dtsi
+++ b/dts/src/arm/r8a7794.dtsi
@@ -820,16 +820,14 @@
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
+ usb@1,0 {
reg = <0x800 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
- usb@0,2 {
+ usb@2,0 {
reg = <0x1000 0 0 0 0>;
- device_type = "pci";
phys = <&usb0 0>;
phy-names = "usb";
};
@@ -855,16 +853,14 @@
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- usb@0,1 {
- reg = <0x800 0 0 0 0>;
- device_type = "pci";
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
- usb@0,2 {
- reg = <0x1000 0 0 0 0>;
- device_type = "pci";
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
diff --git a/dts/src/arm/r8a77xx-aa104xd12-panel.dtsi b/dts/src/arm/r8a77xx-aa104xd12-panel.dtsi
index 65cb50f0c2..238d14bb0e 100644
--- a/dts/src/arm/r8a77xx-aa104xd12-panel.dtsi
+++ b/dts/src/arm/r8a77xx-aa104xd12-panel.dtsi
@@ -10,10 +10,11 @@
/ {
panel {
- compatible = "mitsubishi,aa104xd12", "panel-dpi";
+ compatible = "mitsubishi,aa104xd12", "panel-lvds";
width-mm = <210>;
height-mm = <158>;
+ data-mapping = "jeida-18";
panel-timing {
/* 1024x768 @65Hz */
diff --git a/dts/src/arm/r8a77xx-aa121td01-panel.dtsi b/dts/src/arm/r8a77xx-aa121td01-panel.dtsi
index a07ebf8f69..04aafd4797 100644
--- a/dts/src/arm/r8a77xx-aa121td01-panel.dtsi
+++ b/dts/src/arm/r8a77xx-aa121td01-panel.dtsi
@@ -10,10 +10,11 @@
/ {
panel {
- compatible = "mitsubishi,aa121td01", "panel-dpi";
+ compatible = "mitsubishi,aa121td01", "panel-lvds";
width-mm = <261>;
height-mm = <163>;
+ data-mapping = "jeida-18";
panel-timing {
/* 1280x800 @60Hz */
diff --git a/dts/src/arm/rk3229-evb.dts b/dts/src/arm/rk3229-evb.dts
index 275092a950..1b55192b7d 100644
--- a/dts/src/arm/rk3229-evb.dts
+++ b/dts/src/arm/rk3229-evb.dts
@@ -58,6 +58,17 @@
#clock-cells = <0>;
};
+ vcc_host: vcc-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc_host";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -85,6 +96,69 @@
status = "okay";
};
+&pinctrl {
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
&uart2 {
status = "okay";
};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_ehci {
+ status = "okay";
+};
+
+&usb_host2_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
diff --git a/dts/src/arm/rk322x.dtsi b/dts/src/arm/rk322x.dtsi
index 48a0c1cf43..f3e4ffd9f8 100644
--- a/dts/src/arm/rk322x.dtsi
+++ b/dts/src/arm/rk322x.dtsi
@@ -66,10 +66,7 @@
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHz uV */
- 816000 1000000
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@@ -80,6 +77,7 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@f02 {
@@ -87,6 +85,7 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@f03 {
@@ -94,6 +93,35 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
};
};
@@ -182,8 +210,61 @@
};
grf: syscon@11000000 {
- compatible = "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@760 {
+ compatible = "rockchip,rk3228-usb2phy";
+ reg = <0x0760 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy0_host: host-port {
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy@800 {
+ compatible = "rockchip,rk3228-usb2phy";
+ reg = <0x0800 0x0c>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy1_host: host-port {
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
};
uart0: serial@11010000 {
@@ -280,6 +361,14 @@
status = "disabled";
};
+ wdt: watchdog@110a0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x110a0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_CPU>;
+ status = "disabled";
+ };
+
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
@@ -338,8 +427,18 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
+ assigned-clocks =
+ <&cru PLL_GPLL>, <&cru ARMCLK>,
+ <&cru PLL_CPLL>, <&cru ACLK_PERI>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+ <&cru PCLK_CPU>;
+ assigned-clock-rates =
+ <594000000>, <816000000>,
+ <500000000>, <150000000>,
+ <150000000>, <75000000>,
+ <150000000>, <150000000>,
+ <75000000>;
};
thermal-zones {
@@ -388,6 +487,8 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
+ assigned-clocks = <&cru SCLK_TSADC>;
+ assigned-clock-rates = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
@@ -419,6 +520,89 @@
status = "disabled";
};
+ usb_otg: usb@30040000 {
+ compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x30040000 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ g-use-dma;
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb@30080000 {
+ compatible = "generic-ehci";
+ reg = <0x30080000 0x20000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@300a0000 {
+ compatible = "generic-ohci";
+ reg = <0x300a0000 0x20000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@300c0000 {
+ compatible = "generic-ehci";
+ reg = <0x300c0000 0x20000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@300e0000 {
+ compatible = "generic-ohci";
+ reg = <0x300e0000 0x20000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host2_ehci: usb@30100000 {
+ compatible = "generic-ehci";
+ reg = <0x30100000 0x20000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ clock-names = "usbhost", "utmi";
+ status = "disabled";
+ };
+
+ usb_host2_ohci: usb@30120000 {
+ compatible = "generic-ohci";
+ reg = <0x30120000 0x20000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
@@ -621,9 +805,9 @@
<0 12 RK_FUNC_1 &pcfg_pull_none>,
<0 13 RK_FUNC_1 &pcfg_pull_none>,
<0 14 RK_FUNC_1 &pcfg_pull_none>,
- <1 2 RK_FUNC_1 &pcfg_pull_none>,
- <1 4 RK_FUNC_1 &pcfg_pull_none>,
- <1 5 RK_FUNC_1 &pcfg_pull_none>;
+ <1 2 RK_FUNC_2 &pcfg_pull_none>,
+ <1 4 RK_FUNC_2 &pcfg_pull_none>,
+ <1 5 RK_FUNC_2 &pcfg_pull_none>;
};
};
@@ -693,10 +877,15 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
<1 19 RK_FUNC_2 &pcfg_pull_none>;
};
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+ <1 9 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
uart2_cts: uart2-cts {
rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
};
diff --git a/dts/src/arm/rk3288-firefly-reload.dts b/dts/src/arm/rk3288-firefly-reload.dts
index d0b3204a47..b11a282c33 100644
--- a/dts/src/arm/rk3288-firefly-reload.dts
+++ b/dts/src/arm/rk3288-firefly-reload.dts
@@ -48,6 +48,19 @@
model = "Firefly-RK3288-reload";
compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -246,6 +259,10 @@
status = "okay";
};
+&saradc {
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/dts/src/arm/rk3288-firefly.dtsi b/dts/src/arm/rk3288-firefly.dtsi
index 10793ac185..32dabae12e 100644
--- a/dts/src/arm/rk3288-firefly.dtsi
+++ b/dts/src/arm/rk3288-firefly.dtsi
@@ -49,6 +49,19 @@
reg = <0 0x80000000>;
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
dovdd_1v8: dovdd-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "dovdd_1v8";
@@ -219,6 +232,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
diff --git a/dts/src/arm/rk3288-rock2-som.dtsi b/dts/src/arm/rk3288-rock2-som.dtsi
index f0778a46bc..749a9b86e6 100644
--- a/dts/src/arm/rk3288-rock2-som.dtsi
+++ b/dts/src/arm/rk3288-rock2-som.dtsi
@@ -113,6 +113,11 @@
tx_delay = <0x30>;
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/dts/src/arm/rk3288-rock2-square.dts b/dts/src/arm/rk3288-rock2-square.dts
index a23a94811b..8ed25e9f60 100644
--- a/dts/src/arm/rk3288-rock2-square.dts
+++ b/dts/src/arm/rk3288-rock2-square.dts
@@ -125,10 +125,6 @@
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
- /* Always on as the rockchip usb phy doesn't have a vbus-supply
- * property
- */
- regulator-always-on;
regulator-name = "vcc_host";
};
@@ -279,6 +275,10 @@
status = "okay";
};
+&usbphy1 {
+ vbus-supply = <&vcc_usb_host>;
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/dts/src/arm/rk3288-veyron.dtsi b/dts/src/arm/rk3288-veyron.dtsi
index 5d1eb0a258..d709fa1847 100644
--- a/dts/src/arm/rk3288-veyron.dtsi
+++ b/dts/src/arm/rk3288-veyron.dtsi
@@ -161,6 +161,11 @@
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi
index ad5d6022e9..2484f11761 100644
--- a/dts/src/arm/rk3288.dtsi
+++ b/dts/src/arm/rk3288.dtsi
@@ -43,6 +43,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
@@ -1125,6 +1126,48 @@
};
};
+ gpu: mali@ffa30000 {
+ compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+ reg = <0xffa30000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&cru ACLK_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3288_PD_GPU>;
+ status = "disabled";
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1250000>;
+ };
+ };
+
qos_gpu_r: qos@ffaa0000 {
compatible = "syscon";
reg = <0xffaa0000 0x20>;
diff --git a/dts/src/arm/rk1108-evb.dts b/dts/src/arm/rv1108-evb.dts
index 3956cff4ca..58cf4ac079 100644
--- a/dts/src/arm/rk1108-evb.dts
+++ b/dts/src/arm/rv1108-evb.dts
@@ -40,11 +40,11 @@
/dts-v1/;
-#include "rk1108.dtsi"
+#include "rv1108.dtsi"
/ {
- model = "Rockchip RK1108 Evaluation board";
- compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
+ model = "Rockchip RV1108 Evaluation board";
+ compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
memory@60000000 {
device_type = "memory";
diff --git a/dts/src/arm/rk1108.dtsi b/dts/src/arm/rv1108.dtsi
index 1297924db6..437098b556 100644
--- a/dts/src/arm/rk1108.dtsi
+++ b/dts/src/arm/rv1108.dtsi
@@ -47,7 +47,7 @@
#address-cells = <1>;
#size-cells = <1>;
- compatible = "rockchip,rk1108";
+ compatible = "rockchip,rv1108";
interrupt-parent = <&gic>;
@@ -113,7 +113,7 @@
};
uart2: serial@10210000 {
- compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
reg = <0x10210000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -127,7 +127,7 @@
};
uart1: serial@10220000 {
- compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
reg = <0x10220000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -141,7 +141,7 @@
};
uart0: serial@10230000 {
- compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
reg = <0x10230000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -155,17 +155,17 @@
};
grf: syscon@10300000 {
- compatible = "rockchip,rk1108-grf", "syscon";
+ compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x10300000 0x1000>;
};
pmugrf: syscon@20060000 {
- compatible = "rockchip,rk1108-pmugrf", "syscon";
+ compatible = "rockchip,rv1108-pmugrf", "syscon";
reg = <0x20060000 0x1000>;
};
cru: clock-controller@20200000 {
- compatible = "rockchip,rk1108-cru";
+ compatible = "rockchip,rv1108-cru";
reg = <0x20200000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
@@ -173,7 +173,7 @@
};
emmc: dwmmc@30110000 {
- compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
@@ -185,7 +185,7 @@
};
sdio: dwmmc@30120000 {
- compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
@@ -197,7 +197,7 @@
};
sdmmc: dwmmc@30130000 {
- compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 100000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi
index 8067c71c3a..cc06da3943 100644
--- a/dts/src/arm/sama5d2.dtsi
+++ b/dts/src/arm/sama5d2.dtsi
@@ -135,6 +135,12 @@
#size-cells = <1>;
ranges;
+ nfc_sram: sram@00100000 {
+ compatible = "mmio-sram";
+ no-memory-wc;
+ reg = <0x00100000 0x2400>;
+ };
+
usb0: gadget@00300000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -291,6 +297,32 @@
cache-level = <2>;
};
+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&hsmc>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x60000000 0x10000000
+ 0x2 0x0 0x70000000 0x10000000
+ 0x3 0x0 0x80000000 0x10000000>;
+ clocks = <&mck>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "atmel,sama5d3-nand-controller";
+ atmel,nfc-sram = <&nfc_sram>;
+ atmel,nfc-io = <&nfc_io>;
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
nand0: nand@80000000 {
compatible = "atmel,sama5d2-nand";
#address-cells = <1>;
@@ -347,6 +379,11 @@
status = "disabled";
};
+ nfc_io: nfc-io@c0000000 {
+ compatible = "atmel,sama5d3-nfc-io", "syscon";
+ reg = <0xc0000000 0x8000000>;
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -762,6 +799,18 @@
atmel,clk-output-range = <0 83000000>;
};
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ reg = <56>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ reg = <57>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
classd_clk: classd_clk {
#clock-cells = <0>;
reg = <59>;
@@ -890,6 +939,18 @@
#clock-cells = <0>;
reg = <55>;
};
+
+ can0_gclk: can0_gclk {
+ #clock-cells = <0>;
+ reg = <56>;
+ atmel,clk-output-range = <0 80000000>;
+ };
+
+ can1_gclk: can1_gclk {
+ #clock-cells = <0>;
+ reg = <57>;
+ atmel,clk-output-range = <0 80000000>;
+ };
};
};
@@ -986,6 +1047,22 @@
clock-names = "t0_clk", "slow_clk";
};
+ hsmc: hsmc@f8014000 {
+ compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
+ reg = <0xf8014000 0x1000>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
+ clocks = <&hsmc_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pmecc: ecc-engine@ffffc070 {
+ compatible = "atmel,sama5d2-pmecc";
+ reg = <0xffffc070 0x490>,
+ <0xffffc500 0x100>;
+ };
+ };
+
pdmic: pdmic@f8018000 {
compatible = "atmel,sama5d2-pdmic";
reg = <0xf8018000 0x124>;
@@ -1065,6 +1142,14 @@
status = "disabled";
};
+ pwm0: pwm@f802c000 {
+ compatible = "atmel,sama5d2-pwm";
+ reg = <0xf802c000 0x4000>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
+ #pwm-cells = <3>;
+ clocks = <&pwm_clk>;
+ };
+
sfr: sfr@f8030000 {
compatible = "atmel,sama5d2-sfr", "syscon";
reg = <0xf8030000 0x98>;
@@ -1144,6 +1229,22 @@
clocks = <&clk32k>;
};
+ can0: can@f8054000 {
+ compatible = "bosch,m_can";
+ reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
+ <64 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-names = "int0", "int1";
+ clocks = <&can0_clk>, <&can0_gclk>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&can0_gclk>;
+ assigned-clock-parents = <&utmi>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
spi1: spi@fc000000 {
compatible = "atmel,at91rm9200-spi";
reg = <0xfc000000 0x100>;
@@ -1305,6 +1406,22 @@
status = "okay";
};
+ can1: can@fc050000 {
+ compatible = "bosch,m_can";
+ reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
+ <65 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-names = "int0", "int1";
+ clocks = <&can1_clk>, <&can1_gclk>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&can1_gclk>;
+ assigned-clock-parents = <&utmi>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
sfrbu: sfr@fc05c000 {
compatible = "atmel,sama5d2-sfrbu", "syscon";
reg = <0xfc05c000 0x20>;
diff --git a/dts/src/arm/sama5d3.dtsi b/dts/src/arm/sama5d3.dtsi
index b06448ba66..554d0bdedc 100644
--- a/dts/src/arm/sama5d3.dtsi
+++ b/dts/src/arm/sama5d3.dtsi
@@ -429,6 +429,22 @@
clocks = <&trng_clk>;
};
+ hsmc: hsmc@ffffc000 {
+ compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
+ reg = <0xffffc000 0x1000>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
+ clocks = <&hsmc_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pmecc: ecc-engine@ffffc070 {
+ compatible = "atmel,at91sam9g45-pmecc";
+ reg = <0xffffc070 0x490>,
+ <0xffffc500 0x100>;
+ };
+ };
+
dma0: dma-controller@ffffe600 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffe600 0x200>;
@@ -554,6 +570,66 @@
};
};
+ ebi {
+ pinctrl_ebi_addr: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nand_addr: ebi-addr-1 {
+ atmel,pins =
+ <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs0: ebi-cs0-0 {
+ atmel,pins =
+ <AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs1: ebi-cs1-0 {
+ atmel,pins =
+ <AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs2: ebi-cs2-0 {
+ atmel,pins =
+ <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwait: ebi-nwait-0 {
+ atmel,pins =
+ <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
+ atmel,pins =
+ <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
i2c0 {
pinctrl_i2c0: i2c0-0 {
atmel,pins =
@@ -1326,6 +1402,12 @@
};
};
+ nfc_sram: sram@200000 {
+ compatible = "mmio-sram";
+ no-memory-wc;
+ reg = <0x200000 0x2400>;
+ };
+
usb0: gadget@00500000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -1461,36 +1543,35 @@
status = "disabled";
};
- nand0: nand@60000000 {
- compatible = "atmel,at91rm9200-nand";
- #address-cells = <1>;
+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
#size-cells = <1>;
- ranges;
- reg = < 0x60000000 0x01000000 /* EBI CS3 */
- 0xffffc070 0x00000490 /* SMC PMECC regs */
- 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
- 0x00110000 0x00018000 /* ROM code */
- >;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand0_ale_cle>;
- atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+ atmel,smc = <&hsmc>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x40000000 0x10000000
+ 0x2 0x0 0x50000000 0x10000000
+ 0x3 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
status = "disabled";
- nfc@70000000 {
- compatible = "atmel,sama5d3-nfc";
- #address-cells = <1>;
+ nand_controller: nand-controller {
+ compatible = "atmel,sama5d3-nand-controller";
+ atmel,nfc-sram = <&nfc_sram>;
+ atmel,nfc-io = <&nfc_io>;
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
#size-cells = <1>;
- reg = <
- 0x70000000 0x08000000 /* NFC Command Registers */
- 0xffffc000 0x00000070 /* NFC HSMC regs */
- 0x00200000 0x00100000 /* NFC SRAM banks */
- >;
- clocks = <&hsmc_clk>;
+ ranges;
+ status = "disabled";
};
};
+
+ nfc_io: nfc-io@70000000 {
+ compatible = "atmel,sama5d3-nfc-io", "syscon";
+ reg = <0x70000000 0x8000000>;
+ };
};
};
diff --git a/dts/src/arm/sama5d3xcm.dtsi b/dts/src/arm/sama5d3xcm.dtsi
index b5e111b29d..9506daf5ef 100644
--- a/dts/src/arm/sama5d3xcm.dtsi
+++ b/dts/src/arm/sama5d3xcm.dtsi
@@ -36,43 +36,82 @@
};
};
- nand0: nand@60000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
+ pinctr-name = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
+ nor: flash@0,0 {
+ compatible = "cfi-flash";
+ linux,mtd-name = "physmap-flash.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ atmel,smc-read-mode = "nrd";
+ atmel,smc-write-mode = "nwe";
+ atmel,smc-bus-width = <16>;
+ atmel,smc-ncs-rd-setup-ns = <0>;
+ atmel,smc-ncs-wr-setup-ns = <0>;
+ atmel,smc-nwe-setup-ns = <8>;
+ atmel,smc-nrd-setup-ns = <16>;
+ atmel,smc-ncs-rd-pulse-ns = <84>;
+ atmel,smc-ncs-wr-pulse-ns = <84>;
+ atmel,smc-nrd-pulse-ns = <76>;
+ atmel,smc-nwe-pulse-ns = <76>;
+ atmel,smc-nrd-cycle-ns = <107>;
+ atmel,smc-nwe-cycle-ns = <84>;
+ atmel,smc-tdf-ns = <16>;
};
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/sama5d3xcm_cmp.dtsi b/dts/src/arm/sama5d3xcm_cmp.dtsi
index dc7572bc7f..75cbf4d4ab 100644
--- a/dts/src/arm/sama5d3xcm_cmp.dtsi
+++ b/dts/src/arm/sama5d3xcm_cmp.dtsi
@@ -148,43 +148,60 @@
};
};
- nand0: nand@60000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x40000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
- };
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
- };
+ bootloaderenv@c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
- };
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
- kernel@200000 {
- label = "kernel";
- reg = <0x200000 0x600000>;
- };
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
- rootfs@800000 {
- label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/sama5d4.dtsi b/dts/src/arm/sama5d4.dtsi
index d3889c9d25..2fa36c5259 100644
--- a/dts/src/arm/sama5d4.dtsi
+++ b/dts/src/arm/sama5d4.dtsi
@@ -124,6 +124,12 @@
#size-cells = <1>;
ranges;
+ nfc_sram: sram@100000 {
+ compatible = "mmio-sram";
+ no-memory-wc;
+ reg = <0x100000 0x2400>;
+ };
+
usb0: gadget@00400000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -280,37 +286,37 @@
cache-level = <2>;
};
- nand0: nand@80000000 {
- compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
- #address-cells = <1>;
+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
#size-cells = <1>;
- ranges;
- reg = < 0x80000000 0x08000000 /* EBI CS3 */
- 0xfc05c070 0x00000490 /* SMC PMECC regs */
- 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
- >;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
- atmel,nand-addr-offset = <21>;
- atmel,nand-cmd-offset = <22>;
- atmel,nand-has-dma;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ atmel,smc = <&hsmc>;
+ reg = <0x10000000 0x10000000
+ 0x60000000 0x28000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x60000000 0x10000000
+ 0x2 0x0 0x70000000 0x10000000
+ 0x3 0x0 0x80000000 0x8000000>;
+ clocks = <&mck>;
status = "disabled";
- nfc@90000000 {
- compatible = "atmel,sama5d3-nfc";
- #address-cells = <1>;
+ nand_controller: nand-controller {
+ compatible = "atmel,sama5d3-nand-controller";
+ atmel,nfc-sram = <&nfc_sram>;
+ atmel,nfc-io = <&nfc_io>;
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
#size-cells = <1>;
- reg = <
- 0x90000000 0x08000000 /* NFC Command Registers */
- 0xfc05c000 0x00000070 /* NFC HSMC regs */
- 0x00100000 0x00100000 /* NFC SRAM banks */
- >;
- clocks = <&hsmc_clk>;
- atmel,write-by-sram;
+ ranges;
+ status = "disabled";
};
};
+ nfc_io: nfc-io@90000000 {
+ compatible = "atmel,sama5d3-nfc-io", "syscon";
+ reg = <0x90000000 0x8000000>;
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -1287,6 +1293,22 @@
status = "okay";
};
+ hsmc: smc@fc05c000 {
+ compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
+ reg = <0xfc05c000 0x1000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
+ clocks = <&hsmc_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pmecc: ecc-engine@ffffc070 {
+ compatible = "atmel,sama5d4-pmecc";
+ reg = <0xfc05c070 0x490>,
+ <0xfc05c500 0x100>;
+ };
+ };
+
rstc@fc068600 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
@@ -1447,6 +1469,113 @@
};
};
+ ebi {
+ pinctrl_ebi_addr: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nand_addr: ebi-addr-1 {
+ atmel,pins =
+ <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs0: ebi-cs0-0 {
+ atmel,pins =
+ <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs1: ebi-cs1-0 {
+ atmel,pins =
+ <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs2: ebi-cs2-0 {
+ atmel,pins =
+ <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs3: ebi-cs3-0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_data_8_15: ebi-data-msb-0 {
+ atmel,pins =
+ <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
+ atmel,pins =
+ <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwait: ebi-nwait-0 {
+ atmel,pins =
+ <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
+ atmel,pins =
+ <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
+ atmel,pins =
+ <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
i2c0 {
pinctrl_i2c0: i2c0-0 {
atmel,pins =
diff --git a/dts/src/arm/sh73a0.dtsi b/dts/src/arm/sh73a0.dtsi
index 6b01ab354e..4ea5c5a16c 100644
--- a/dts/src/arm/sh73a0.dtsi
+++ b/dts/src/arm/sh73a0.dtsi
@@ -444,7 +444,7 @@
status = "disabled";
};
- pfc: pfc@e6050000 {
+ pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
diff --git a/dts/src/arm/socfpga.dtsi b/dts/src/arm/socfpga.dtsi
index b2674bdb8e..7e24dc8e82 100644
--- a/dts/src/arm/socfpga.dtsi
+++ b/dts/src/arm/socfpga.dtsi
@@ -557,7 +557,7 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
+ clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
@@ -575,7 +575,7 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
+ clocks = <&emac_1_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
diff --git a/dts/src/arm/socfpga_arria10_socdk.dtsi b/dts/src/arm/socfpga_arria10_socdk.dtsi
index 94e0884738..3a32de9ded 100644
--- a/dts/src/arm/socfpga_arria10_socdk.dtsi
+++ b/dts/src/arm/socfpga_arria10_socdk.dtsi
@@ -130,13 +130,13 @@
};
&i2c1 {
- speed-mode = <0>;
status = "okay";
/*
* adjust the falling times to decrease the i2c frequency to 50Khz
* because the LCD module does not work at the standard 100Khz
*/
+ clock-frequency = <100000>;
i2c-sda-falling-time-ns = <6000>;
i2c-scl-falling-time-ns = <6000>;
diff --git a/dts/src/arm/socfpga_cyclone5_de0_sockit.dts b/dts/src/arm/socfpga_cyclone5_de0_sockit.dts
index 7b49395452..b280e64941 100644
--- a/dts/src/arm/socfpga_cyclone5_de0_sockit.dts
+++ b/dts/src/arm/socfpga_cyclone5_de0_sockit.dts
@@ -86,7 +86,7 @@
&i2c0 {
status = "okay";
- speed-mode = <0>;
+ clock-frequency = <100000>;
adxl345: adxl345@0 {
compatible = "adi,adxl345";
diff --git a/dts/src/arm/socfpga_cyclone5_mcvevk.dts b/dts/src/arm/socfpga_cyclone5_mcvevk.dts
index 21e397287e..c2eb88aab8 100644
--- a/dts/src/arm/socfpga_cyclone5_mcvevk.dts
+++ b/dts/src/arm/socfpga_cyclone5_mcvevk.dts
@@ -58,7 +58,7 @@
&i2c0 {
status = "okay";
- speed-mode = <0>;
+ clock-frequency = <100000>;
stmpe1: stmpe811@41 {
compatible = "st,stmpe811";
diff --git a/dts/src/arm/socfpga_cyclone5_vining_fpga.dts b/dts/src/arm/socfpga_cyclone5_vining_fpga.dts
index 8931980493..655fe87e27 100644
--- a/dts/src/arm/socfpga_cyclone5_vining_fpga.dts
+++ b/dts/src/arm/socfpga_cyclone5_vining_fpga.dts
@@ -69,34 +69,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
- };
-
- leds {
- compatible = "gpio-leds";
-
- hps_led0 {
- label = "hps:green:led0"; /* ALIVE_LED_GR */
- gpios = <&portb 19 0>; /* HPS_GPIO48 */
- linux,default-trigger = "heartbeat";
- };
-
- hps_led1 {
- label = "hps:red:led0"; /* ALIVE_LED_RD */
- gpios = <&portb 24 0>; /* HPS_GPIO53 */
- linux,default-trigger = "none";
- };
-
- hps_led2 {
- label = "hps:green:led1"; /* LINK2HOST_LED_GR */
- gpios = <&portb 25 0>; /* HPS_GPIO54 */
- linux,default-trigger = "heartbeat";
- };
-
- hps_led3 {
- label = "hps:red:led1"; /* LINK2HOST_LED_RD */
- gpios = <&portc 7 0>; /* HPS_GPIO65 */
- linux,default-trigger = "none";
- };
+ ethernet1 = &gmac0;
};
gpio-keys {
@@ -203,69 +176,39 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
- i2c@6 {
+ i2c@6 { /* Backplane EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
@@ -276,7 +219,7 @@
};
};
- i2c@7 {
+ i2c@7 { /* Power board EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
@@ -300,6 +243,44 @@
};
};
+&qspi {
+ status = "okay";
+
+ n25q128@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+
+ n25q00@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <1>; /* chip select */
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
+
&usb0 {
dr_mode = "host";
status = "okay";
diff --git a/dts/src/arm/stm32429i-eval.dts b/dts/src/arm/stm32429i-eval.dts
index b6331146aa..dcda0bbefe 100644
--- a/dts/src/arm/stm32429i-eval.dts
+++ b/dts/src/arm/stm32429i-eval.dts
@@ -48,6 +48,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32429i-EVAL board";
@@ -66,6 +67,14 @@
serial0 = &usart1;
};
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -124,6 +133,16 @@
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
+
+ panel_rgb: panel-rgb {
+ compatible = "ampire,am-480272h3tmqw-t01h";
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <&ltdc_out_rgb>;
+ };
+ };
+ };
};
&adc {
@@ -141,10 +160,79 @@
clock-frequency = <25000000>;
};
+&crc {
+ status = "okay";
+};
+
+&dcmi {
+ status = "okay";
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov2640_0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
+
+ ov2640: camera@30 {
+ compatible = "ovti,ov2640";
+ reg = <0x30>;
+ resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xvclk";
+ status = "okay";
+
+ port {
+ ov2640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ };
+ };
+ };
+
+ stmpe1600: stmpe1600@42 {
+ compatible = "st,stmpe1600";
+ reg = <0x42>;
+ irq-gpio = <&gpioi 8 0>;
+ irq-trigger = <3>;
+ interrupts = <8 3>;
+ interrupt-parent = <&exti>;
+ interrupt-controller;
+ wakeup-source;
+
+ stmpegpio: stmpe_gpio {
+ compatible = "st,stmpe-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
+
+&iwdg {
+ status = "okay";
+ timeout-sec = <32>;
+};
+
+&ltdc {
+ status = "okay";
+ pinctrl-0 = <&ltdc_pins>;
+ pinctrl-names = "default";
+ dma-ranges;
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
};
&mac {
diff --git a/dts/src/arm/stm32f429-disco.dts b/dts/src/arm/stm32f429-disco.dts
index 191fa50e34..ae47cde795 100644
--- a/dts/src/arm/stm32f429-disco.dts
+++ b/dts/src/arm/stm32f429-disco.dts
@@ -102,6 +102,10 @@
clock-frequency = <8000000>;
};
+&crc {
+ status = "okay";
+};
+
&rtc {
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSI>;
diff --git a/dts/src/arm/stm32f429.dtsi b/dts/src/arm/stm32f429.dtsi
index b2a2b5c38c..a8113dc879 100644
--- a/dts/src/arm/stm32f429.dtsi
+++ b/dts/src/arm/stm32f429.dtsi
@@ -65,7 +65,7 @@
clock-frequency = <32768>;
};
- clk-lsi {
+ clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
@@ -307,6 +307,13 @@
status = "disabled";
};
+ iwdg: watchdog@40003000 {
+ compatible = "st,stm32-iwdg";
+ reg = <0x40003000 0x400>;
+ clocks = <&clk_lsi>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
@@ -549,7 +556,17 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -561,6 +578,8 @@
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
@@ -569,6 +588,8 @@
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
@@ -577,6 +598,8 @@
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
@@ -585,6 +608,8 @@
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
@@ -593,6 +618,8 @@
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
@@ -601,6 +628,8 @@
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
@@ -609,6 +638,8 @@
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
@@ -617,6 +648,8 @@
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
@@ -625,6 +658,8 @@
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
@@ -633,6 +668,8 @@
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
@@ -641,6 +678,8 @@
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
@@ -764,6 +803,70 @@
slew-rate = <3>;
};
};
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
+ <STM32F429_PI13_FUNC_LCD_VSYNC>,
+ <STM32F429_PI14_FUNC_LCD_CLK>,
+ <STM32F429_PI15_FUNC_LCD_R0>,
+ <STM32F429_PJ0_FUNC_LCD_R1>,
+ <STM32F429_PJ1_FUNC_LCD_R2>,
+ <STM32F429_PJ2_FUNC_LCD_R3>,
+ <STM32F429_PJ3_FUNC_LCD_R4>,
+ <STM32F429_PJ4_FUNC_LCD_R5>,
+ <STM32F429_PJ5_FUNC_LCD_R6>,
+ <STM32F429_PJ6_FUNC_LCD_R7>,
+ <STM32F429_PJ7_FUNC_LCD_G0>,
+ <STM32F429_PJ8_FUNC_LCD_G1>,
+ <STM32F429_PJ9_FUNC_LCD_G2>,
+ <STM32F429_PJ10_FUNC_LCD_G3>,
+ <STM32F429_PJ11_FUNC_LCD_G4>,
+ <STM32F429_PJ12_FUNC_LCD_B0>,
+ <STM32F429_PJ13_FUNC_LCD_B1>,
+ <STM32F429_PJ14_FUNC_LCD_B2>,
+ <STM32F429_PJ15_FUNC_LCD_B3>,
+ <STM32F429_PK0_FUNC_LCD_G5>,
+ <STM32F429_PK1_FUNC_LCD_G6>,
+ <STM32F429_PK2_FUNC_LCD_G7>,
+ <STM32F429_PK3_FUNC_LCD_B4>,
+ <STM32F429_PK4_FUNC_LCD_B5>,
+ <STM32F429_PK5_FUNC_LCD_B6>,
+ <STM32F429_PK6_FUNC_LCD_B7>,
+ <STM32F429_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
+
+ dcmi_pins: dcmi@0 {
+ pins {
+ pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
+ <STM32F429_PB7_FUNC_DCMI_VSYNC>,
+ <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
+ <STM32F429_PC6_FUNC_DCMI_D0>,
+ <STM32F429_PC7_FUNC_DCMI_D1>,
+ <STM32F429_PC8_FUNC_DCMI_D2>,
+ <STM32F429_PC9_FUNC_DCMI_D3>,
+ <STM32F429_PC11_FUNC_DCMI_D4>,
+ <STM32F429_PD3_FUNC_DCMI_D5>,
+ <STM32F429_PB8_FUNC_DCMI_D6>,
+ <STM32F429_PE6_FUNC_DCMI_D7>,
+ <STM32F429_PC10_FUNC_DCMI_D8>,
+ <STM32F429_PC12_FUNC_DCMI_D9>,
+ <STM32F429_PD6_FUNC_DCMI_D10>,
+ <STM32F429_PD2_FUNC_DCMI_D11>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+ };
+
+ crc: crc@40023000 {
+ compatible = "st,stm32f4-crc";
+ reg = <0x40023000 0x400>;
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+ status = "disabled";
};
rcc: rcc@40023810 {
@@ -842,6 +945,20 @@
status = "disabled";
};
+ dcmi: dcmi@50050000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x50050000 0x400>;
+ interrupts = <78>;
+ resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
+ clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
+ clock-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcmi_pins>;
+ dmas = <&dma2 1 1 0x414 0x3>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
diff --git a/dts/src/arm/stm32f746-disco.dts b/dts/src/arm/stm32f746-disco.dts
new file mode 100644
index 0000000000..18f6560744
--- /dev/null
+++ b/dts/src/arm/stm32f746-disco.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32F746-DISCO board";
+ compatible = "st,stm32f746-disco", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x800000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/src/arm/stm32f746.dtsi b/dts/src/arm/stm32f746.dtsi
index c2765ce12e..4506eb97a4 100644
--- a/dts/src/arm/stm32f746.dtsi
+++ b/dts/src/arm/stm32f746.dtsi
@@ -229,6 +229,8 @@
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
@@ -237,6 +239,8 @@
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
@@ -245,6 +249,8 @@
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
@@ -253,6 +259,8 @@
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
@@ -261,6 +269,8 @@
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
@@ -269,6 +279,8 @@
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
@@ -277,6 +289,8 @@
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
@@ -285,6 +299,8 @@
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
@@ -293,6 +309,8 @@
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
@@ -301,6 +319,8 @@
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
@@ -309,6 +329,8 @@
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
@@ -326,6 +348,19 @@
bias-disable;
};
};
+
+ usart1_pins_b: usart1@1 {
+ pins1 {
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
};
crc: crc@40023000 {
@@ -336,6 +371,7 @@
};
rcc: rcc@40023800 {
+ #reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
diff --git a/dts/src/arm/stm32f769-disco.dts b/dts/src/arm/stm32f769-disco.dts
new file mode 100644
index 0000000000..166728aeb1
--- /dev/null
+++ b/dts/src/arm/stm32f769-disco.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "STMicroelectronics STM32F769-DISCO board";
+ compatible = "st,stm32f769-disco", "st,stm32f7";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x1000000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ };
+
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/src/arm/stm32h743-pinctrl.dtsi b/dts/src/arm/stm32h743-pinctrl.dtsi
index fcc1e06402..76bbd6575f 100644
--- a/dts/src/arm/stm32h743-pinctrl.dtsi
+++ b/dts/src/arm/stm32h743-pinctrl.dtsi
@@ -151,6 +151,19 @@
bias-disable;
};
};
+
+ usart2_pins: usart2@0 {
+ pins1 {
+ pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
+ bias-disable;
+ };
+ };
};
};
};
diff --git a/dts/src/arm/stm32h743.dtsi b/dts/src/arm/stm32h743.dtsi
index 46856298ee..36a99db0a3 100644
--- a/dts/src/arm/stm32h743.dtsi
+++ b/dts/src/arm/stm32h743.dtsi
@@ -68,6 +68,14 @@
};
+ usart2: serial@40004400 {
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ status = "disabled";
+ clocks = <&timer_clk>;
+ };
+
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
diff --git a/dts/src/arm/stm32h743i-disco.dts b/dts/src/arm/stm32h743i-disco.dts
new file mode 100644
index 0000000000..79e841d940
--- /dev/null
+++ b/dts/src/arm/stm32h743i-disco.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2017 - Patrice Chotard <patrice.chotard@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32h743.dtsi"
+#include "stm32h743-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32H743i-Discovery board";
+ compatible = "st,stm32h743i-disco", "st,stm32h743";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xd0000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &usart2;
+ };
+};
+
+&clk_hse {
+ clock-frequency = <125000000>;
+};
+
+&usart2 {
+ pinctrl-0 = <&usart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/src/arm/sun4i-a10-a1000.dts b/dts/src/arm/sun4i-a10-a1000.dts
index f2a01fe2be..f80d37ddc4 100644
--- a/dts/src/arm/sun4i-a10-a1000.dts
+++ b/dts/src/arm/sun4i-a10-a1000.dts
@@ -171,7 +171,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-ba10-tvbox.dts b/dts/src/arm/sun4i-a10-ba10-tvbox.dts
index 942d739a43..6b02de592a 100644
--- a/dts/src/arm/sun4i-a10-ba10-tvbox.dts
+++ b/dts/src/arm/sun4i-a10-ba10-tvbox.dts
@@ -109,7 +109,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts b/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts
index 17f8c5ec01..a7d61994b8 100644
--- a/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts
@@ -128,7 +128,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-cubieboard.dts b/dts/src/arm/sun4i-a10-cubieboard.dts
index d844938e2a..404ce76948 100644
--- a/dts/src/arm/sun4i-a10-cubieboard.dts
+++ b/dts/src/arm/sun4i-a10-cubieboard.dts
@@ -142,7 +142,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -182,6 +182,10 @@
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
diff --git a/dts/src/arm/sun4i-a10-dserve-dsrv9703c.dts b/dts/src/arm/sun4i-a10-dserve-dsrv9703c.dts
index aad3bec1cb..e0777ae808 100644
--- a/dts/src/arm/sun4i-a10-dserve-dsrv9703c.dts
+++ b/dts/src/arm/sun4i-a10-dserve-dsrv9703c.dts
@@ -163,7 +163,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-gemei-g9.dts b/dts/src/arm/sun4i-a10-gemei-g9.dts
index 9616cdecce..d8bfd7b749 100644
--- a/dts/src/arm/sun4i-a10-gemei-g9.dts
+++ b/dts/src/arm/sun4i-a10-gemei-g9.dts
@@ -146,7 +146,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
diff --git a/dts/src/arm/sun4i-a10-hackberry.dts b/dts/src/arm/sun4i-a10-hackberry.dts
index a1a7282199..856cfc9128 100644
--- a/dts/src/arm/sun4i-a10-hackberry.dts
+++ b/dts/src/arm/sun4i-a10-hackberry.dts
@@ -107,7 +107,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-hyundai-a7hd.dts b/dts/src/arm/sun4i-a10-hyundai-a7hd.dts
index 85dcf81ab6..6506595268 100644
--- a/dts/src/arm/sun4i-a10-hyundai-a7hd.dts
+++ b/dts/src/arm/sun4i-a10-hyundai-a7hd.dts
@@ -79,7 +79,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -120,10 +120,6 @@
status = "okay";
};
-&usb2_vbus_pin_a {
- pins = "PH6";
-};
-
&usb_otg {
dr_mode = "otg";
status = "okay";
diff --git a/dts/src/arm/sun4i-a10-inet1.dts b/dts/src/arm/sun4i-a10-inet1.dts
index b8923b92cb..d51d8c302d 100644
--- a/dts/src/arm/sun4i-a10-inet1.dts
+++ b/dts/src/arm/sun4i-a10-inet1.dts
@@ -161,7 +161,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-inet97fv2.dts b/dts/src/arm/sun4i-a10-inet97fv2.dts
index a1a2bbb3f9..a8e479fe43 100644
--- a/dts/src/arm/sun4i-a10-inet97fv2.dts
+++ b/dts/src/arm/sun4i-a10-inet97fv2.dts
@@ -147,7 +147,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-inet9f-rev03.dts b/dts/src/arm/sun4i-a10-inet9f-rev03.dts
index 4a27eb9102..2acb89a87d 100644
--- a/dts/src/arm/sun4i-a10-inet9f-rev03.dts
+++ b/dts/src/arm/sun4i-a10-inet9f-rev03.dts
@@ -305,7 +305,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-itead-iteaduino-plus.dts b/dts/src/arm/sun4i-a10-itead-iteaduino-plus.dts
index 4e798f014c..92e3e030ce 100644
--- a/dts/src/arm/sun4i-a10-itead-iteaduino-plus.dts
+++ b/dts/src/arm/sun4i-a10-itead-iteaduino-plus.dts
@@ -100,7 +100,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-jesurun-q5.dts b/dts/src/arm/sun4i-a10-jesurun-q5.dts
index 308dc15130..92b2d4af3d 100644
--- a/dts/src/arm/sun4i-a10-jesurun-q5.dts
+++ b/dts/src/arm/sun4i-a10-jesurun-q5.dts
@@ -140,7 +140,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-marsboard.dts b/dts/src/arm/sun4i-a10-marsboard.dts
index 98a5f7258d..0f927da28e 100644
--- a/dts/src/arm/sun4i-a10-marsboard.dts
+++ b/dts/src/arm/sun4i-a10-marsboard.dts
@@ -141,7 +141,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-mini-xplus.dts b/dts/src/arm/sun4i-a10-mini-xplus.dts
index 484c57493b..a5ed9e4e22 100644
--- a/dts/src/arm/sun4i-a10-mini-xplus.dts
+++ b/dts/src/arm/sun4i-a10-mini-xplus.dts
@@ -97,7 +97,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-mk802.dts b/dts/src/arm/sun4i-a10-mk802.dts
index 2b75745cd2..81db6824a2 100644
--- a/dts/src/arm/sun4i-a10-mk802.dts
+++ b/dts/src/arm/sun4i-a10-mk802.dts
@@ -72,7 +72,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-mk802ii.dts b/dts/src/arm/sun4i-a10-mk802ii.dts
index c861fa7e35..e74a881fd9 100644
--- a/dts/src/arm/sun4i-a10-mk802ii.dts
+++ b/dts/src/arm/sun4i-a10-mk802ii.dts
@@ -83,7 +83,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-olinuxino-lime.dts b/dts/src/arm/sun4i-a10-olinuxino-lime.dts
index 3a2522a941..462412ee90 100644
--- a/dts/src/arm/sun4i-a10-olinuxino-lime.dts
+++ b/dts/src/arm/sun4i-a10-olinuxino-lime.dts
@@ -145,7 +145,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-pcduino.dts b/dts/src/arm/sun4i-a10-pcduino.dts
index 83596fd2cc..84f55e76df 100644
--- a/dts/src/arm/sun4i-a10-pcduino.dts
+++ b/dts/src/arm/sun4i-a10-pcduino.dts
@@ -147,7 +147,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10-pov-protab2-ips9.dts b/dts/src/arm/sun4i-a10-pov-protab2-ips9.dts
index a68c7cc53b..c0f8c88b5a 100644
--- a/dts/src/arm/sun4i-a10-pov-protab2-ips9.dts
+++ b/dts/src/arm/sun4i-a10-pov-protab2-ips9.dts
@@ -149,7 +149,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun4i-a10.dtsi b/dts/src/arm/sun4i-a10.dtsi
index b63668ece1..41c2579143 100644
--- a/dts/src/arm/sun4i-a10.dtsi
+++ b/dts/src/arm/sun4i-a10.dtsi
@@ -1030,12 +1030,6 @@
bias-pull-up;
};
- mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
- pins = "PH1";
- function = "gpio_in";
- bias-pull-up;
- };
-
ps20_pins_a: ps20@0 {
pins = "PI20", "PI21";
function = "ps2";
diff --git a/dts/src/arm/sun5i-a10s-auxtek-t003.dts b/dts/src/arm/sun5i-a10s-auxtek-t003.dts
index c6f742a7e6..d2dee8d434 100644
--- a/dts/src/arm/sun5i-a10s-auxtek-t003.dts
+++ b/dts/src/arm/sun5i-a10s-auxtek-t003.dts
@@ -136,14 +136,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG13";
-};
-
-&usb1_vbus_pin_a {
- pins = "PB10";
-};
-
&usb_otg {
dr_mode = "host";
status = "okay";
diff --git a/dts/src/arm/sun5i-a10s-auxtek-t004.dts b/dts/src/arm/sun5i-a10s-auxtek-t004.dts
index a27c3fa587..16f839df42 100644
--- a/dts/src/arm/sun5i-a10s-auxtek-t004.dts
+++ b/dts/src/arm/sun5i-a10s-auxtek-t004.dts
@@ -168,10 +168,6 @@
status = "okay";
};
-&usb1_vbus_pin_a {
- pins = "PG13";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/dts/src/arm/sun5i-a10s-olinuxino-micro.dts b/dts/src/arm/sun5i-a10s-olinuxino-micro.dts
index 894f874a5b..da95118af4 100644
--- a/dts/src/arm/sun5i-a10s-olinuxino-micro.dts
+++ b/dts/src/arm/sun5i-a10s-olinuxino-micro.dts
@@ -63,6 +63,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -76,6 +87,10 @@
};
};
+&be0 {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -91,6 +106,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -248,6 +273,10 @@
status = "okay";
};
+&tcon0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -271,10 +300,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG11";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/dts/src/arm/sun5i-a10s-wobo-i5.dts b/dts/src/arm/sun5i-a10s-wobo-i5.dts
index ea3e5655a6..5482be174e 100644
--- a/dts/src/arm/sun5i-a10s-wobo-i5.dts
+++ b/dts/src/arm/sun5i-a10s-wobo-i5.dts
@@ -216,10 +216,6 @@
status = "okay";
};
-&usb1_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
diff --git a/dts/src/arm/sun5i-a10s.dtsi b/dts/src/arm/sun5i-a10s.dtsi
index 1e38ff8036..18f25c5e75 100644
--- a/dts/src/arm/sun5i-a10s.dtsi
+++ b/dts/src/arm/sun5i-a10s.dtsi
@@ -71,7 +71,46 @@
};
};
+ display-engine {
+ compatible = "allwinner,sun5i-a10s-display-engine";
+ allwinner,pipelines = <&fe0>;
+ };
+
soc@01c00000 {
+ hdmi: hdmi@01c16000 {
+ compatible = "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu 9>,
+ <&ccu 16>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -128,3 +167,11 @@
&sram_a {
};
+
+&tcon0_out {
+ tcon0_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+};
diff --git a/dts/src/arm/sun5i-a13-empire-electronix-d709.dts b/dts/src/arm/sun5i-a13-empire-electronix-d709.dts
index 34411d27aa..3dbb0d7c2f 100644
--- a/dts/src/arm/sun5i-a13-empire-electronix-d709.dts
+++ b/dts/src/arm/sun5i-a13-empire-electronix-d709.dts
@@ -207,10 +207,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/dts/src/arm/sun5i-a13-hsg-h702.dts b/dts/src/arm/sun5i-a13-hsg-h702.dts
index 2489c16f7e..584fa579de 100644
--- a/dts/src/arm/sun5i-a13-hsg-h702.dts
+++ b/dts/src/arm/sun5i-a13-hsg-h702.dts
@@ -186,7 +186,6 @@
};
&reg_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_a>;
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
status = "okay";
};
@@ -202,10 +201,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/dts/src/arm/sun5i-a13-olinuxino.dts b/dts/src/arm/sun5i-a13-olinuxino.dts
index 95f591bb8c..38072c7e10 100644
--- a/dts/src/arm/sun5i-a13-olinuxino.dts
+++ b/dts/src/arm/sun5i-a13-olinuxino.dts
@@ -269,10 +269,6 @@
status = "okay";
};
-&usb0_vbus_pin_a {
- pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/dts/src/arm/sun5i-r8-chip.dts b/dts/src/arm/sun5i-r8-chip.dts
index d078560266..879a4b0f3b 100644
--- a/dts/src/arm/sun5i-r8-chip.dts
+++ b/dts/src/arm/sun5i-r8-chip.dts
@@ -132,6 +132,10 @@
status = "okay";
};
+&battery_power_supply {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
diff --git a/dts/src/arm/sun5i.dtsi b/dts/src/arm/sun5i.dtsi
index 5175f9cc9b..98cc00341b 100644
--- a/dts/src/arm/sun5i.dtsi
+++ b/dts/src/arm/sun5i.dtsi
@@ -272,6 +272,7 @@
tcon0_out_tve0: endpoint@1 {
reg = <1>;
remote-endpoint = <&tve0_in_tcon0>;
+ allwinner,tcon-channel = <1>;
};
};
};
@@ -355,6 +356,15 @@
status = "disabled";
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun5i-a13-crypto",
+ "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <54>;
+ clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
+ clock-names = "ahb", "mod";
+ };
+
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
diff --git a/dts/src/arm/sun6i-a31-hummingbird.dts b/dts/src/arm/sun6i-a31-hummingbird.dts
index d4f74f476f..9ecb5f0b3f 100644
--- a/dts/src/arm/sun6i-a31-hummingbird.dts
+++ b/dts/src/arm/sun6i-a31-hummingbird.dts
@@ -253,6 +253,10 @@
#include "axp22x.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
&reg_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -319,7 +323,6 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rgb888_pins>;
- status = "okay";
};
&tcon0_out {
@@ -344,11 +347,6 @@
status = "okay";
};
-&usb1_vbus_pin_a {
- /* different pin from sunxi-common-regulators */
- pins = "PH24";
-};
-
&usbphy {
usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi
index 9c999d3788..aebc3f9dc7 100644
--- a/dts/src/arm/sun6i-a31.dtsi
+++ b/dts/src/arm/sun6i-a31.dtsi
@@ -232,7 +232,7 @@
de: display-engine {
compatible = "allwinner,sun6i-a31-display-engine";
- allwinner,pipelines = <&fe0>;
+ allwinner,pipelines = <&fe0>, <&fe1>;
status = "disabled";
};
@@ -264,7 +264,6 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
- status = "disabled";
ports {
#address-cells = <1>;
@@ -289,6 +288,43 @@
};
};
+ tcon1: lcd-controller@01c0d000 {
+ compatible = "allwinner,sun6i-a31-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_AHB1_LCD1>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB1_LCD1>,
+ <&ccu CLK_LCD1_CH0>,
+ <&ccu CLK_LCD1_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon1-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -780,7 +816,8 @@
};
crypto: crypto-engine@01c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ compatible = "allwinner,sun6i-a31-crypto",
+ "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
@@ -896,6 +933,130 @@
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
+
+ fe0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe0>;
+ };
+ };
+ };
+ };
+
+ fe1: display-frontend@01e20000 {
+ compatible = "allwinner,sun6i-a31-display-frontend";
+ reg = <0x01e20000 0x20000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
+ <&ccu CLK_DRAM_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_FE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe1>;
+ };
+
+ fe1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@01e40000 {
+ compatible = "allwinner,sun6i-a31-display-backend";
+ reg = <0x01e40000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
+ <&ccu CLK_DRAM_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_BE1>;
+
+ assigned-clocks = <&ccu CLK_BE1>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be1>;
+ };
+
+ be1_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_in_be1>;
+ };
+ };
+ };
+ };
+
+ drc1: drc@01e50000 {
+ compatible = "allwinner,sun6i-a31-drc";
+ reg = <0x01e50000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
+ <&ccu CLK_DRAM_DRC1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_DRC1>;
+
+ assigned-clocks = <&ccu CLK_IEP_DRC1>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc1_in_be1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be1_out_drc1>;
+ };
+ };
+
+ drc1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc1_out_tcon1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_in_drc1>;
+ };
};
};
};
@@ -926,6 +1087,11 @@
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
+
+ be0_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be0>;
+ };
};
be0_out: port@1 {
diff --git a/dts/src/arm/sun6i-a31s-primo81.dts b/dts/src/arm/sun6i-a31s-primo81.dts
index f3712753fa..4c10123509 100644
--- a/dts/src/arm/sun6i-a31s-primo81.dts
+++ b/dts/src/arm/sun6i-a31s-primo81.dts
@@ -158,11 +158,16 @@
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en;
};
};
#include "axp22x.dtsi"
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
@@ -226,6 +231,11 @@
regulator-name = "vddio-csi";
};
+&reg_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
&reg_eldo3 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
@@ -238,12 +248,18 @@
};
&usb_otg {
- /* otg support requires support for AXP221 usb-power-supply and GPIO */
- dr_mode = "host";
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
status = "okay";
};
&usbphy {
+ usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_dldo1>;
status = "okay";
};
diff --git a/dts/src/arm/sun6i-a31s-sinovoip-bpi-m2.dts b/dts/src/arm/sun6i-a31s-sinovoip-bpi-m2.dts
index bdfdce8ca6..51e6f1d21c 100644
--- a/dts/src/arm/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/dts/src/arm/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -138,7 +138,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
diff --git a/dts/src/arm/sun7i-a20-bananapi-m1-plus.dts b/dts/src/arm/sun7i-a20-bananapi-m1-plus.dts
index 08e776ae09..eb55e74232 100644
--- a/dts/src/arm/sun7i-a20-bananapi-m1-plus.dts
+++ b/dts/src/arm/sun7i-a20-bananapi-m1-plus.dts
@@ -144,6 +144,10 @@
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pins_a>;
@@ -172,7 +176,7 @@
wakeup-source;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
diff --git a/dts/src/arm/sun7i-a20-bananapi.dts b/dts/src/arm/sun7i-a20-bananapi.dts
index ed2f35adf5..88a1c2363c 100644
--- a/dts/src/arm/sun7i-a20-bananapi.dts
+++ b/dts/src/arm/sun7i-a20-bananapi.dts
@@ -177,6 +177,57 @@
};
&pio {
+ gpio-line-names =
+ /* PA */
+ "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",
+ "ETXD2", "ETXD1", "ETXD0",
+ "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO",
+ "ETXEN", "ETXCK", "ECRS",
+ "ECOL", "ETXERR", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PB */
+ "PMU-SCK", "PMU-SDA", "", "", "", "", "", "",
+ "", "USB0-DRV", "", "", "", "", "", "",
+ "", "", "", "", "SCL", "SDA", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PC */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PD */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PE */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PF */
+ "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
+ "SD0-D2", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PG */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PH */
+ "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "",
+ "", "", "SD0-DET", "", "", "", "", "",
+ "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN",
+ "LED1", "", "", "", "", "", "", "",
+ /* PI */
+ "", "", "", "IO-GCLK", "", "", "", "",
+ "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
+ "SPI-MISO", "SPI-CE1", "",
+ "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PH4";
function = "gpio_in";
diff --git a/dts/src/arm/sun7i-a20-bananapro.dts b/dts/src/arm/sun7i-a20-bananapro.dts
index 83516bc812..e7af1b7c33 100644
--- a/dts/src/arm/sun7i-a20-bananapro.dts
+++ b/dts/src/arm/sun7i-a20-bananapro.dts
@@ -172,7 +172,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
diff --git a/dts/src/arm/sun7i-a20-cubieboard2.dts b/dts/src/arm/sun7i-a20-cubieboard2.dts
index a2eab7aa80..2a50207618 100644
--- a/dts/src/arm/sun7i-a20-cubieboard2.dts
+++ b/dts/src/arm/sun7i-a20-cubieboard2.dts
@@ -137,7 +137,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -174,13 +174,12 @@
status = "okay";
};
-&usb_otg {
- dr_mode = "otg";
+#include "axp209.dtsi"
+
+&ac_power_supply {
status = "okay";
};
-#include "axp209.dtsi"
-
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -220,6 +219,11 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/dts/src/arm/sun7i-a20-cubietruck.dts b/dts/src/arm/sun7i-a20-cubietruck.dts
index 102903e83b..bb51018760 100644
--- a/dts/src/arm/sun7i-a20-cubietruck.dts
+++ b/dts/src/arm/sun7i-a20-cubietruck.dts
@@ -178,7 +178,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -195,7 +195,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
@@ -336,6 +336,7 @@
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/dts/src/arm/sun7i-a20-hummingbird.dts b/dts/src/arm/sun7i-a20-hummingbird.dts
index 99c00b9a15..6e6264cd69 100644
--- a/dts/src/arm/sun7i-a20-hummingbird.dts
+++ b/dts/src/arm/sun7i-a20-hummingbird.dts
@@ -160,7 +160,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-i12-tvbox.dts b/dts/src/arm/sun7i-a20-i12-tvbox.dts
index 4da49717da..55809973a5 100644
--- a/dts/src/arm/sun7i-a20-i12-tvbox.dts
+++ b/dts/src/arm/sun7i-a20-i12-tvbox.dts
@@ -157,7 +157,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -173,7 +173,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
diff --git a/dts/src/arm/sun7i-a20-icnova-swac.dts b/dts/src/arm/sun7i-a20-icnova-swac.dts
index 28d3abbdc2..794e7617f5 100644
--- a/dts/src/arm/sun7i-a20-icnova-swac.dts
+++ b/dts/src/arm/sun7i-a20-icnova-swac.dts
@@ -104,7 +104,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
diff --git a/dts/src/arm/sun7i-a20-itead-ibox.dts b/dts/src/arm/sun7i-a20-itead-ibox.dts
index d52222c82c..8a8a6dbcd4 100644
--- a/dts/src/arm/sun7i-a20-itead-ibox.dts
+++ b/dts/src/arm/sun7i-a20-itead-ibox.dts
@@ -121,7 +121,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-lamobo-r1.dts b/dts/src/arm/sun7i-a20-lamobo-r1.dts
index 96bb0bc198..004b6ddac8 100644
--- a/dts/src/arm/sun7i-a20-lamobo-r1.dts
+++ b/dts/src/arm/sun7i-a20-lamobo-r1.dts
@@ -85,10 +85,6 @@
};
};
-&ahci_pwr_pin_a {
- pins = "PB3";
-};
-
&ahci {
target-supply = <&reg_ahci_5v>;
status = "okay";
@@ -319,10 +315,6 @@
status = "okay";
};
-&usb2_vbus_pin_a {
- pins = "PH12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
diff --git a/dts/src/arm/sun7i-a20-m3.dts b/dts/src/arm/sun7i-a20-m3.dts
index 86f6981368..43c94787ef 100644
--- a/dts/src/arm/sun7i-a20-m3.dts
+++ b/dts/src/arm/sun7i-a20-m3.dts
@@ -117,7 +117,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-mk808c.dts b/dts/src/arm/sun7i-a20-mk808c.dts
index c4ee30709f..f741309418 100644
--- a/dts/src/arm/sun7i-a20-mk808c.dts
+++ b/dts/src/arm/sun7i-a20-mk808c.dts
@@ -109,7 +109,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-olimex-som-evb.dts b/dts/src/arm/sun7i-a20-olimex-som-evb.dts
index 1af5b46862..64c8ef9a27 100644
--- a/dts/src/arm/sun7i-a20-olimex-som-evb.dts
+++ b/dts/src/arm/sun7i-a20-olimex-som-evb.dts
@@ -187,7 +187,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-olinuxino-lime.dts b/dts/src/arm/sun7i-a20-olinuxino-lime.dts
index dcd0f7a0df..2ce1a9f13a 100644
--- a/dts/src/arm/sun7i-a20-olinuxino-lime.dts
+++ b/dts/src/arm/sun7i-a20-olinuxino-lime.dts
@@ -130,7 +130,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
index e7d4542575..097bd75576 100644
--- a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
+++ b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
@@ -131,7 +131,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-olinuxino-micro.dts b/dts/src/arm/sun7i-a20-olinuxino-micro.dts
index def0ad8395..0b7403e4d6 100644
--- a/dts/src/arm/sun7i-a20-olinuxino-micro.dts
+++ b/dts/src/arm/sun7i-a20-olinuxino-micro.dts
@@ -198,7 +198,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-pcduino3-nano.dts b/dts/src/arm/sun7i-a20-pcduino3-nano.dts
index f47a5c46bc..39bc73db72 100644
--- a/dts/src/arm/sun7i-a20-pcduino3-nano.dts
+++ b/dts/src/arm/sun7i-a20-pcduino3-nano.dts
@@ -130,7 +130,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-pcduino3.dts b/dts/src/arm/sun7i-a20-pcduino3.dts
index 7c96b53b76..777152a3df 100644
--- a/dts/src/arm/sun7i-a20-pcduino3.dts
+++ b/dts/src/arm/sun7i-a20-pcduino3.dts
@@ -106,10 +106,6 @@
status = "okay";
};
-&ahci_pwr_pin_a {
- pins = "PH2";
-};
-
&codec {
status = "okay";
};
@@ -160,7 +156,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-wexler-tab7200.dts b/dts/src/arm/sun7i-a20-wexler-tab7200.dts
index e19f171777..f8d0aafb9f 100644
--- a/dts/src/arm/sun7i-a20-wexler-tab7200.dts
+++ b/dts/src/arm/sun7i-a20-wexler-tab7200.dts
@@ -151,7 +151,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
diff --git a/dts/src/arm/sun7i-a20-wits-pro-a20-dkt.dts b/dts/src/arm/sun7i-a20-wits-pro-a20-dkt.dts
index c3078d4f10..7f8405a0dd 100644
--- a/dts/src/arm/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/dts/src/arm/sun7i-a20-wits-pro-a20-dkt.dts
@@ -120,7 +120,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
@@ -137,7 +137,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi
index 93aa55970b..96bee776e1 100644
--- a/dts/src/arm/sun7i-a20.dtsi
+++ b/dts/src/arm/sun7i-a20.dtsi
@@ -1019,7 +1019,8 @@
};
crypto: crypto-engine@01c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ compatible = "allwinner,sun7i-a20-crypto",
+ "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 5>, <&ss_clk>;
@@ -1190,12 +1191,6 @@
bias-pull-up;
};
- mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
- pins = "PH1";
- function = "gpio_in";
- bias-pull-up;
- };
-
mmc2_pins_a: mmc2@0 {
pins = "PC6", "PC7", "PC8",
"PC9", "PC10", "PC11";
diff --git a/dts/src/arm/sun8i-a33-sinlinx-sina33.dts b/dts/src/arm/sun8i-a33-sinlinx-sina33.dts
index 9b620cc1d5..433cf2a2a9 100644
--- a/dts/src/arm/sun8i-a33-sinlinx-sina33.dts
+++ b/dts/src/arm/sun8i-a33-sinlinx-sina33.dts
@@ -88,13 +88,13 @@
};
&cpu0_opp_table {
- opp@1104000000 {
+ opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
@@ -196,6 +196,10 @@
status = "okay";
};
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
diff --git a/dts/src/arm/sun8i-a33.dtsi b/dts/src/arm/sun8i-a33.dtsi
index 0139782593..22660919bd 100644
--- a/dts/src/arm/sun8i-a33.dtsi
+++ b/dts/src/arm/sun8i-a33.dtsi
@@ -50,73 +50,73 @@
compatible = "operating-points-v2";
opp-shared;
- opp@120000000 {
+ opp-120000000 {
opp-hz = /bits/ 64 <120000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@240000000 {
+ opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@312000000 {
+ opp-312000000 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@408000000 {
+ opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@480000000 {
+ opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@504000000 {
+ opp-504000000 {
opp-hz = /bits/ 64 <504000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@648000000 {
+ opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1040000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@720000000 {
+ opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@816000000 {
+ opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@912000000 {
+ opp-912000000 {
opp-hz = /bits/ 64 <912000000>;
opp-microvolt = <1200000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@1008000000 {
+ opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000>;
clock-latency-ns = <244144>; /* 8 32k periods */
@@ -164,15 +164,15 @@
mali_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
- opp@144000000 {
+ opp-144000000 {
opp-hz = /bits/ 64 <144000000>;
};
- opp@240000000 {
+ opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
};
- opp@384000000 {
+ opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
};
};
diff --git a/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts b/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d33fa..aecdeeb368 100644
--- a/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/dts/src/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -59,6 +59,6 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/dts/src/arm/sun8i-a83t-cubietruck-plus.dts b/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
index 88b1e0970b..cff33454fc 100644
--- a/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
+++ b/dts/src/arm/sun8i-a83t-cubietruck-plus.dts
@@ -45,6 +45,8 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Cubietech Cubietruck Plus";
compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
@@ -56,10 +58,56 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "cubietruck-plus:blue:usr";
+ gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
+ };
+
+ orange {
+ label = "cubietruck-plus:orange:usr";
+ gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */
+ };
+
+ white {
+ label = "cubietruck-plus:white:usr";
+ gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */
+ };
+
+ green {
+ label = "cubietruck-plus:green:usr";
+ gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&spdif {
+ status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/dts/src/arm/sun8i-a83t.dtsi b/dts/src/arm/sun8i-a83t.dtsi
index 0ec143773e..8923ba625b 100644
--- a/dts/src/arm/sun8i-a83t.dtsi
+++ b/dts/src/arm/sun8i-a83t.dtsi
@@ -40,15 +40,22 @@
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
-
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ };
+
+ chosen {
+ };
cpus {
#address-cells = <1>;
@@ -121,6 +128,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
@@ -146,25 +154,55 @@
};
};
+ memory {
+ reg = <0x40000000 0x80000000>;
+ device_type = "memory";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pio: pinctrl@01c20800 {
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-a83t-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-a83t-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 21>;
+ resets = <&ccu 7>;
+ #dma-cells = <1>;
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun8i-a83t-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c20800 0x400>;
- clocks = <&osc24M>;
+ clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- mmc0_pins_a: mmc0@0 {
+ mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
@@ -172,18 +210,23 @@
bias-pull-up;
};
- uart0_pins_a: uart0@0 {
- pins = "PF2", "PF4";
- function = "uart0";
+ spdif_tx_pin: spdif-tx-pin {
+ pins = "PE18";
+ function = "spdif";
};
- uart0_pins_b: uart0@1 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
};
+
+ uart0_pf_pins: uart0-pf-pins {
+ pins = "PF2", "PF4";
+ function = "uart0";
+ };
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -191,24 +234,41 @@
clocks = <&osc24M>;
};
- watchdog@01c20ca0 {
+ watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
+ spdif: spdif@1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-spdif",
+ "allwinner,sun8i-h3-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 44>, <&ccu 76>;
+ resets = <&ccu 32>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ status = "disabled";
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&ccu 53>;
+ resets = <&ccu 40>;
status = "disabled";
};
- gic: interrupt-controller@01c81000 {
+ gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
@@ -218,5 +278,28 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ r_ccu: clock@1f01400 {
+ compatible = "allwinner,sun8i-a83t-r-ccu";
+ reg = <0x01f01400 0x400>;
+ clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
+ <&ccu 6>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ r_pio: pinctrl@1f02c00 {
+ compatible = "allwinner,sun8i-a83t-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
+ <&osc16Md512>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
diff --git a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
index 9e8b082c13..6713d0f2b3 100644
--- a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
+++ b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
@@ -57,6 +57,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -103,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
@@ -143,6 +151,19 @@
status = "okay";
};
+&spi0 {
+ /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts
index 52acbe111c..d756ff8251 100644
--- a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts
+++ b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -84,6 +85,16 @@
};
};
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -92,6 +103,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -100,12 +115,30 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
@@ -126,7 +159,7 @@
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
@@ -145,6 +178,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
@@ -170,6 +207,11 @@
};
};
+&reg_usb0_vbus {
+ gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -182,7 +224,14 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- /* USB VBUS is on as long as VCC-IO is on */
+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ /* USB host VBUS is on as long as VCC-IO is on */
status = "okay";
};
diff --git a/dts/src/arm/sun8i-h3-nanopi-m1-plus.dts b/dts/src/arm/sun8i-h3-nanopi-m1-plus.dts
new file mode 100644
index 0000000000..8ddd1b2cc0
--- /dev/null
+++ b/dts/src/arm/sun8i-h3-nanopi-m1-plus.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyArm NanoPi M1 Plus";
+ compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
diff --git a/dts/src/arm/sun8i-h3-nanopi-neo.dts b/dts/src/arm/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a0..78f6c24952 100644
--- a/dts/src/arm/sun8i-h3-nanopi-neo.dts
+++ b/dts/src/arm/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/dts/src/arm/sun8i-h3-orangepi-2.dts b/dts/src/arm/sun8i-h3-orangepi-2.dts
index 5b6d14555b..17cdeae19c 100644
--- a/dts/src/arm/sun8i-h3-orangepi-2.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -104,10 +105,26 @@
};
};
+&codec {
+ allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+ allwinner,audio-routing =
+ "Speaker", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -195,10 +212,6 @@
status = "disabled";
};
-&usb1_vbus_pin_a {
- pins = "PG13";
-};
-
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
diff --git a/dts/src/arm/sun8i-h3-orangepi-one.dts b/dts/src/arm/sun8i-h3-orangepi-one.dts
index 5fea430e0e..6880268e8b 100644
--- a/dts/src/arm/sun8i-h3-orangepi-one.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts
index 8b93f5c781..a10281b455 100644
--- a/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts
@@ -53,6 +53,11 @@
};
};
+&emac {
+ /* LEDs changed to active high on the plus */
+ /delete-property/ allwinner,leds-active-low;
+};
+
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
diff --git a/dts/src/arm/sun8i-h3-orangepi-pc.dts b/dts/src/arm/sun8i-h3-orangepi-pc.dts
index f148111c32..998b60f8d2 100644
--- a/dts/src/arm/sun8i-h3-orangepi-pc.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-pc.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,10 @@
status = "okay";
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -109,6 +114,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -125,6 +137,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
@@ -156,6 +172,11 @@
};
};
+&reg_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -180,7 +201,14 @@
status = "disabled";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
- /* USB VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ /* VBUS on USB host ports are always on */
status = "okay";
};
diff --git a/dts/src/arm/sun8i-h3-orangepi-plus.dts b/dts/src/arm/sun8i-h3-orangepi-plus.dts
index 8c40ab7bfa..331ed683ac 100644
--- a/dts/src/arm/sun8i-h3-orangepi-plus.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-plus.dts
@@ -47,6 +47,20 @@
model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -64,6 +78,24 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
diff --git a/dts/src/arm/sun8i-h3-orangepi-plus2e.dts b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts
index 5851a47a30..80026f3caa 100644
--- a/dts/src/arm/sun8i-h3-orangepi-plus2e.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts
@@ -50,4 +50,30 @@
/ {
model = "Xunlong Orange Pi Plus 2E";
compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
diff --git a/dts/src/arm/sun8i-v3s-licheepi-zero-dock.dts b/dts/src/arm/sun8i-v3s-licheepi-zero-dock.dts
new file mode 100644
index 0000000000..d1311098ea
--- /dev/null
+++ b/dts/src/arm/sun8i-v3s-licheepi-zero-dock.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-v3s-licheepi-zero.dts"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Lichee Pi Zero with Dock";
+ compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
+ "allwinner,sun8i-v3s";
+
+ leds {
+ /* The LEDs use PG0~2 pins, which conflict with MMC1 */
+ status = "disbaled";
+ };
+};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <&reg_vcc3v3>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button@600 {
+ label = "Select";
+ linux,code = <KEY_SELECT>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Start";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
diff --git a/dts/src/arm/sun8i-v3s.dtsi b/dts/src/arm/sun8i-v3s.dtsi
index 71075969e5..3a06dc5b37 100644
--- a/dts/src/arm/sun8i-v3s.dtsi
+++ b/dts/src/arm/sun8i-v3s.dtsi
@@ -41,6 +41,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
/ {
#address-cells = <1>;
@@ -55,10 +57,16 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clocks = <&ccu 14>;
+ clocks = <&ccu CLK_CPU>;
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-v3s-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -93,18 +101,95 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock@1000000 {
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@1100000 {
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks 0>,
+ <&display_clocks 6>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks 0>;
+ assigned-clocks = <&display_clocks 6>;
+ assigned-clock-rates = <150000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>,
+ <&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ccu 22>,
- <&ccu 45>,
- <&ccu 47>,
- <&ccu 46>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 7>;
+ resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -115,17 +200,19 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ccu 23>,
- <&ccu 48>,
- <&ccu 50>,
- <&ccu 49>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 8>;
+ resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -134,15 +221,15 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ccu 24>,
- <&ccu 51>,
- <&ccu 53>,
- <&ccu 52>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ccu 9>;
+ resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -153,8 +240,8 @@
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
- clocks = <&ccu 29>;
- resets = <&ccu 17>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
@@ -169,9 +256,9 @@
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
- clocks = <&ccu 56>;
+ clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
- resets = <&ccu 0>;
+ resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
@@ -198,7 +285,7 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@@ -222,6 +309,19 @@
drive-strength = <30>;
bias-pull-up;
};
+
+ mmc1_pins: mmc1 {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ spi0_pins: spi0 {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
};
timer@01c20c00 {
@@ -238,14 +338,21 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
+ lradc: lradc@1c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 40>;
- resets = <&ccu 49>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -255,8 +362,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 41>;
- resets = <&ccu 50>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -266,8 +373,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 42>;
- resets = <&ccu 51>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@@ -275,8 +382,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 38>;
- resets = <&ccu 46>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
@@ -288,8 +395,22 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 39>;
- resets = <&ccu 47>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@1c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/sunxi-common-regulators.dtsi b/dts/src/arm/sunxi-common-regulators.dtsi
index ce5c53e445..d8e5826fb3 100644
--- a/dts/src/arm/sunxi-common-regulators.dtsi
+++ b/dts/src/arm/sunxi-common-regulators.dtsi
@@ -44,33 +44,9 @@
#include <dt-bindings/gpio/gpio.h>
-&pio {
- ahci_pwr_pin_a: ahci_pwr_pin@0 {
- pins = "PB8";
- function = "gpio_out";
- };
-
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- pins = "PB9";
- function = "gpio_out";
- };
-
- usb1_vbus_pin_a: usb1_vbus_pin@0 {
- pins = "PH6";
- function = "gpio_out";
- };
-
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- pins = "PH3";
- function = "gpio_out";
- };
-};
-
/ {
reg_ahci_5v: ahci-5v {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&ahci_pwr_pin_a>;
regulator-name = "ahci-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -82,8 +58,6 @@
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_vbus_pin_a>;
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -94,8 +68,6 @@
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_a>;
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -107,8 +79,6 @@
reg_usb2_vbus: usb2-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_pin_a>;
regulator-name = "usb2-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
diff --git a/dts/src/arm/sunxi-h3-h5.dtsi b/dts/src/arm/sunxi-h3-h5.dtsi
index d4f600dbb7..6f21626080 100644
--- a/dts/src/arm/sunxi-h3-h5.dtsi
+++ b/dts/src/arm/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
*/
#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -83,6 +85,12 @@
#size-cells = <1>;
ranges;
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>;
@@ -279,6 +287,14 @@
interrupt-controller;
#interrupt-cells = <3>;
+ emac_rgmii_pins: emac0 {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD7", "PD8", "PD9", "PD10",
+ "PD12", "PD13", "PD15", "PD16", "PD17";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
i2c0_pins: i2c0 {
pins = "PA11", "PA12";
function = "i2c0";
@@ -375,6 +391,32 @@
clocks = <&osc24M>;
};
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+ };
+
spi0: spi@01c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
@@ -574,9 +616,9 @@
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
- clocks = <&r_ccu 4>, <&r_ccu 11>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
- resets = <&r_ccu 0>;
+ resets = <&r_ccu RST_APB0_IR>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -586,7 +628,7 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
diff --git a/dts/src/arm/tegra124-apalis-eval.dts b/dts/src/arm/tegra124-apalis-eval.dts
index 5b860ad5cb..ecffcd115f 100644
--- a/dts/src/arm/tegra124-apalis-eval.dts
+++ b/dts/src/arm/tegra124-apalis-eval.dts
@@ -63,7 +63,7 @@
stdout-path = "serial0:115200n8";
};
- pcie-controller@01003000 {
+ pcie@1003000 {
pci@1,0 {
status = "okay";
};
diff --git a/dts/src/arm/tegra124-apalis.dtsi b/dts/src/arm/tegra124-apalis.dtsi
index f9e623bdd5..5d9b18ef5a 100644
--- a/dts/src/arm/tegra124-apalis.dtsi
+++ b/dts/src/arm/tegra124-apalis.dtsi
@@ -54,7 +54,7 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05>;
diff --git a/dts/src/arm/tegra124-jetson-tk1.dts b/dts/src/arm/tegra124-jetson-tk1.dts
index 53994f9fbb..7bacb2954f 100644
--- a/dts/src/arm/tegra124-jetson-tk1.dts
+++ b/dts/src/arm/tegra124-jetson-tk1.dts
@@ -27,7 +27,7 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
diff --git a/dts/src/arm/tegra124.dtsi b/dts/src/arm/tegra124.dtsi
index 187a36c6d0..1b10b14a6a 100644
--- a/dts/src/arm/tegra124.dtsi
+++ b/dts/src/arm/tegra124.dtsi
@@ -14,7 +14,7 @@
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -54,6 +54,7 @@
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -67,6 +68,7 @@
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
diff --git a/dts/src/arm/tegra20-harmony.dts b/dts/src/arm/tegra20-harmony.dts
index d4fb4d39ed..41749693ec 100644
--- a/dts/src/arm/tegra20-harmony.dts
+++ b/dts/src/arm/tegra20-harmony.dts
@@ -566,7 +566,7 @@
nvidia,sys-clock-req-active-high;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
diff --git a/dts/src/arm/tegra20-tamonten.dtsi b/dts/src/arm/tegra20-tamonten.dtsi
index 27d2bbbf1e..7361f4a82e 100644
--- a/dts/src/arm/tegra20-tamonten.dtsi
+++ b/dts/src/arm/tegra20-tamonten.dtsi
@@ -478,7 +478,7 @@
nvidia,sys-clock-req-active-high;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
avdd-pex-supply = <&pci_vdd_reg>;
vdd-pex-supply = <&pci_vdd_reg>;
avdd-pex-pll-supply = <&pci_vdd_reg>;
diff --git a/dts/src/arm/tegra20-tec.dts b/dts/src/arm/tegra20-tec.dts
index c12d8bead2..9cb534f444 100644
--- a/dts/src/arm/tegra20-tec.dts
+++ b/dts/src/arm/tegra20-tec.dts
@@ -32,7 +32,7 @@
};
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
pci@1,0 {
diff --git a/dts/src/arm/tegra20-trimslice.dts b/dts/src/arm/tegra20-trimslice.dts
index 87b07fbadb..b902ab594a 100644
--- a/dts/src/arm/tegra20-trimslice.dts
+++ b/dts/src/arm/tegra20-trimslice.dts
@@ -321,7 +321,7 @@
nvidia,sys-clock-req-active-high;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
diff --git a/dts/src/arm/tegra20-whistler.dts b/dts/src/arm/tegra20-whistler.dts
deleted file mode 100644
index 1e06f854c8..0000000000
--- a/dts/src/arm/tegra20-whistler.dts
+++ /dev/null
@@ -1,636 +0,0 @@
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "tegra20.dtsi"
-
-/ {
- model = "NVIDIA Tegra20 Whistler evaluation board";
- compatible = "nvidia,whistler", "nvidia,tegra20";
-
- aliases {
- rtc0 = "/i2c@7000d000/max8907@3c";
- rtc1 = "/rtc@7000e000";
- serial0 = &uarta;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- reg = <0x00000000 0x20000000>;
- };
-
- host1x@50000000 {
- hdmi@54280000 {
- status = "okay";
-
- vdd-supply = <&hdmi_vdd_reg>;
- pll-supply = <&hdmi_pll_reg>;
-
- nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
- GPIO_ACTIVE_HIGH>;
- };
- };
-
- pinmux@70000014 {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinmux {
- ata {
- nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
- "gmc", "gmd", "gpu";
- nvidia,function = "gmi";
- };
- atc {
- nvidia,pins = "atc", "atd";
- nvidia,function = "sdio4";
- };
- cdev1 {
- nvidia,pins = "cdev1";
- nvidia,function = "plla_out";
- };
- cdev2 {
- nvidia,pins = "cdev2";
- nvidia,function = "osc";
- };
- crtp {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- };
- csus {
- nvidia,pins = "csus";
- nvidia,function = "vi_sensor_clk";
- };
- dap1 {
- nvidia,pins = "dap1";
- nvidia,function = "dap1";
- };
- dap2 {
- nvidia,pins = "dap2";
- nvidia,function = "dap2";
- };
- dap3 {
- nvidia,pins = "dap3";
- nvidia,function = "dap3";
- };
- dap4 {
- nvidia,pins = "dap4";
- nvidia,function = "dap4";
- };
- ddc {
- nvidia,pins = "ddc";
- nvidia,function = "i2c2";
- };
- dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd";
- nvidia,function = "vi";
- };
- dte {
- nvidia,pins = "dte";
- nvidia,function = "rsvd1";
- };
- dtf {
- nvidia,pins = "dtf";
- nvidia,function = "i2c3";
- };
- gme {
- nvidia,pins = "gme";
- nvidia,function = "dap5";
- };
- gpu7 {
- nvidia,pins = "gpu7";
- nvidia,function = "rtck";
- };
- gpv {
- nvidia,pins = "gpv";
- nvidia,function = "pcie";
- };
- hdint {
- nvidia,pins = "hdint", "pta";
- nvidia,function = "hdmi";
- };
- i2cp {
- nvidia,pins = "i2cp";
- nvidia,function = "i2cp";
- };
- irrx {
- nvidia,pins = "irrx", "irtx";
- nvidia,function = "uartb";
- };
- kbca {
- nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
- nvidia,function = "kbc";
- };
- kbcb {
- nvidia,pins = "kbcb", "kbcd";
- nvidia,function = "sdio2";
- };
- lcsn {
- nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
- "spia", "spib", "spic";
- nvidia,function = "spi3";
- };
- ld0 {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
- "ld5", "ld6", "ld7", "ld8", "ld9",
- "ld10", "ld11", "ld12", "ld13", "ld14",
- "ld15", "ld16", "ld17", "ldc", "ldi",
- "lhp0", "lhp1", "lhp2", "lhs", "lm0",
- "lm1", "lpp", "lpw0", "lpw1", "lpw2",
- "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
- "lvs";
- nvidia,function = "displaya";
- };
- owc {
- nvidia,pins = "owc", "uac";
- nvidia,function = "owr";
- };
- pmc {
- nvidia,pins = "pmc";
- nvidia,function = "pwr_on";
- };
- rm {
- nvidia,pins = "rm";
- nvidia,function = "i2c1";
- };
- sdb {
- nvidia,pins = "sdb", "sdc", "sdd", "slxa",
- "slxc", "slxd", "slxk";
- nvidia,function = "sdio3";
- };
- sdio1 {
- nvidia,pins = "sdio1";
- nvidia,function = "sdio1";
- };
- spdi {
- nvidia,pins = "spdi", "spdo";
- nvidia,function = "rsvd2";
- };
- spid {
- nvidia,pins = "spid", "spie", "spig", "spih";
- nvidia,function = "spi2_alt";
- };
- spif {
- nvidia,pins = "spif";
- nvidia,function = "spi2";
- };
- uaa {
- nvidia,pins = "uaa", "uab";
- nvidia,function = "uarta";
- };
- uad {
- nvidia,pins = "uad";
- nvidia,function = "irda";
- };
- uca {
- nvidia,pins = "uca", "ucb";
- nvidia,function = "uartc";
- };
- uda {
- nvidia,pins = "uda";
- nvidia,function = "spi1";
- };
- conf_ata {
- nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
- "gmb", "gmc", "gmd", "irrx", "irtx",
- "kbca", "kbcb", "kbcc", "kbcd", "kbce",
- "kbcf", "sdc", "sdd", "spie", "spig",
- "spih", "uaa", "uab", "uad", "uca",
- "ucb";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
- conf_atd {
- nvidia,pins = "atd", "ate", "cdev1", "csus",
- "dap1", "dap2", "dap3", "dap4", "dte",
- "dtf", "gpu", "gpu7", "gpv", "i2cp",
- "rm", "sdio1", "slxa", "slxc", "slxd",
- "slxk", "spdi", "spdo", "uac", "uda";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
- conf_cdev2 {
- nvidia,pins = "cdev2", "spia", "spib";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- };
- conf_ck32 {
- nvidia,pins = "ck32", "ddrc", "lc", "pmca",
- "pmcb", "pmcc", "pmcd", "xm2c",
- "xm2d";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- };
- conf_crtp {
- nvidia,pins = "crtp";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- };
- conf_dta {
- nvidia,pins = "dta", "dtb", "dtc", "dtd",
- "spid", "spif";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
- conf_gme {
- nvidia,pins = "gme", "owc", "pta", "spic";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- };
- conf_ld17_0 {
- nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
- "ld23_22";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- };
- conf_ls {
- nvidia,pins = "ls", "pmce";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- };
- drive_dap1 {
- nvidia,pins = "drive_dap1";
- nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
- nvidia,schmitt = <TEGRA_PIN_ENABLE>;
- nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
- nvidia,pull-down-strength = <0>;
- nvidia,pull-up-strength = <0>;
- nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
- nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
- };
- };
- };
-
- i2s@70002800 {
- status = "okay";
- };
-
- serial@70006000 {
- status = "okay";
- };
-
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@7000d000 {
- status = "okay";
- clock-frequency = <100000>;
-
- codec: codec@1a {
- compatible = "wlf,wm8753";
- reg = <0x1a>;
- };
-
- tca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max8907@3c {
- compatible = "maxim,max8907";
- reg = <0x3c>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-
- maxim,system-power-controller;
-
- mbatt-supply = <&usb0_vbus_reg>;
- in-v1-supply = <&mbatt_reg>;
- in-v2-supply = <&mbatt_reg>;
- in-v3-supply = <&mbatt_reg>;
- in1-supply = <&mbatt_reg>;
- in2-supply = <&nvvdd_sv3_reg>;
- in3-supply = <&mbatt_reg>;
- in4-supply = <&mbatt_reg>;
- in5-supply = <&mbatt_reg>;
- in6-supply = <&mbatt_reg>;
- in7-supply = <&mbatt_reg>;
- in8-supply = <&mbatt_reg>;
- in9-supply = <&mbatt_reg>;
- in10-supply = <&mbatt_reg>;
- in11-supply = <&mbatt_reg>;
- in12-supply = <&mbatt_reg>;
- in13-supply = <&mbatt_reg>;
- in14-supply = <&mbatt_reg>;
- in15-supply = <&mbatt_reg>;
- in16-supply = <&mbatt_reg>;
- in17-supply = <&nvvdd_sv3_reg>;
- in18-supply = <&nvvdd_sv3_reg>;
- in19-supply = <&mbatt_reg>;
- in20-supply = <&mbatt_reg>;
-
- regulators {
- mbatt_reg: mbatt {
- regulator-name = "vbat_pmu";
- regulator-always-on;
- };
-
- sd1 {
- regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- sd2 {
- regulator-name = "nvvdd_sv2,vdd_core";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- nvvdd_sv3_reg: sd3 {
- regulator-name = "nvvdd_sv3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo1 {
- regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo2 {
- regulator-name = "nvvdd_ldo2,avdd_pll*";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo3 {
- regulator-name = "nvvdd_ldo3,vcom_1v8b";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo4 {
- regulator-name = "nvvdd_ldo4,avdd_usb*";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ldo5 {
- regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- hdmi_pll_reg: ldo6 {
- regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo7 {
- regulator-name = "nvvdd_ldo7,avddio_audio";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo8 {
- regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo9 {
- regulator-name = "nvvdd_ldo9,avdd_cam*";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo10 {
- regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- hdmi_vdd_reg: ldo11 {
- regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo12 {
- regulator-name = "nvvdd_ldo12,vddio_sdio";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo13 {
- regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo14 {
- regulator-name = "nvvdd_ldo14,avdd_vdac";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo15 {
- regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo16 {
- regulator-name = "nvvdd_ldo16,vdd_dbrtr";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- ldo17 {
- regulator-name = "nvvdd_ldo17,vddio_mipi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo18 {
- regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo19 {
- regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo20 {
- regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- out5v {
- regulator-name = "usb0_vbus_reg";
- };
-
- out33v {
- regulator-name = "pmu_out3v3";
- };
-
- bbat {
- regulator-name = "pmu_bbat";
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <2400000>;
- regulator-always-on;
- };
-
- sdby {
- regulator-name = "vdd_aon";
- regulator-always-on;
- };
-
- vrtc {
- regulator-name = "vrtc,pmu_vccadc";
- regulator-always-on;
- };
- };
- };
- };
-
- kbc@7000e200 {
- status = "okay";
- nvidia,debounce-delay-ms = <20>;
- nvidia,repeat-delay-ms = <160>;
- nvidia,kbc-row-pins = <0 1 2>;
- nvidia,kbc-col-pins = <16 17>;
- wakeup-source;
- linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
- MATRIX_KEY(0x01, 0x00, KEY_HOME)
- MATRIX_KEY(0x01, 0x01, KEY_BACK)
- MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
- };
-
- pmc@7000e400 {
- nvidia,invert-interrupt;
- nvidia,suspend-mode = <1>;
- nvidia,cpu-pwr-good-time = <2000>;
- nvidia,cpu-pwr-off-time = <1000>;
- nvidia,core-pwr-good-time = <0 3845>;
- nvidia,core-pwr-off-time = <93727>;
- nvidia,core-power-req-active-high;
- nvidia,sys-clock-req-active-high;
- nvidia,combined-power-req;
- };
-
- usb@c5000000 {
- status = "okay";
- };
-
- usb-phy@c5000000 {
- status = "okay";
- vbus-supply = <&vbus1_reg>;
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5008000 {
- status = "okay";
- vbus-supply = <&vbus3_reg>;
- };
-
- sdhci@c8000400 {
- status = "okay";
- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
- bus-width = <8>;
- };
-
- sdhci@c8000600 {
- status = "okay";
- bus-width = <8>;
- non-removable;
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb0_vbus_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb0_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vbus1_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vbus1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
- regulator-always-on;
- regulator-boot-on;
- };
-
- vbus3_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vbus3";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
- regulator-always-on;
- regulator-boot-on;
- };
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8753-whistler",
- "nvidia,tegra-audio-wm8753";
- nvidia,model = "NVIDIA Tegra Whistler";
-
- nvidia,audio-routing =
- "Headphone Jack", "LOUT1",
- "Headphone Jack", "ROUT1",
- "MIC2", "Mic Jack",
- "MIC2N", "Mic Jack";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&codec>;
-
- clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA20_CLK_CDEV1>;
- clock-names = "pll_a", "pll_a_out0", "mclk";
- };
-};
diff --git a/dts/src/arm/tegra20.dtsi b/dts/src/arm/tegra20.dtsi
index e8807503f8..7c85f97f72 100644
--- a/dts/src/arm/tegra20.dtsi
+++ b/dts/src/arm/tegra20.dtsi
@@ -586,7 +586,7 @@
reset-names = "fuse";
};
- pcie-controller@80003000 {
+ pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
@@ -625,6 +625,7 @@
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -638,6 +639,7 @@
device_type = "pci";
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
diff --git a/dts/src/arm/tegra30-apalis-eval.dts b/dts/src/arm/tegra30-apalis-eval.dts
index 99a69457db..fc530e4a96 100644
--- a/dts/src/arm/tegra30-apalis-eval.dts
+++ b/dts/src/arm/tegra30-apalis-eval.dts
@@ -21,7 +21,7 @@
stdout-path = "serial0:115200n8";
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
pci@1,0 {
diff --git a/dts/src/arm/tegra30-apalis.dtsi b/dts/src/arm/tegra30-apalis.dtsi
index f6c7c3e958..7a6a1a0146 100644
--- a/dts/src/arm/tegra30-apalis.dtsi
+++ b/dts/src/arm/tegra30-apalis.dtsi
@@ -9,7 +9,7 @@
model = "Toradex Apalis T30";
compatible = "toradex,apalis_t30", "nvidia,tegra30";
- pcie-controller@00003000 {
+ pcie@3000 {
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
avdd-pexb-supply = <&vdd2_reg>;
diff --git a/dts/src/arm/tegra30-beaver.dts b/dts/src/arm/tegra30-beaver.dts
index 0350002849..4f41b18d95 100644
--- a/dts/src/arm/tegra30-beaver.dts
+++ b/dts/src/arm/tegra30-beaver.dts
@@ -20,7 +20,7 @@
reg = <0x80000000 0x7ff00000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;
diff --git a/dts/src/arm/tegra30-cardhu.dtsi b/dts/src/arm/tegra30-cardhu.dtsi
index f11012bb58..83dc14a9b3 100644
--- a/dts/src/arm/tegra30-cardhu.dtsi
+++ b/dts/src/arm/tegra30-cardhu.dtsi
@@ -43,7 +43,7 @@
reg = <0x80000000 0x40000000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
diff --git a/dts/src/arm/tegra30.dtsi b/dts/src/arm/tegra30.dtsi
index bbb1c002e7..13960fda74 100644
--- a/dts/src/arm/tegra30.dtsi
+++ b/dts/src/arm/tegra30.dtsi
@@ -10,7 +10,7 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
- pcie-controller@00003000 {
+ pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
@@ -51,6 +51,7 @@
device_type = "pci";
assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -64,6 +65,7 @@
device_type = "pci";
assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -77,6 +79,7 @@
device_type = "pci";
assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
reg = <0x001800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
diff --git a/dts/src/arm/tny_a9260_common.dtsi b/dts/src/arm/tny_a9260_common.dtsi
index f9dc463b9e..5d83df4675 100644
--- a/dts/src/arm/tny_a9260_common.dtsi
+++ b/dts/src/arm/tny_a9260_common.dtsi
@@ -32,50 +32,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/tny_a9263.dts b/dts/src/arm/tny_a9263.dts
index 9161cd9889..8cf0a9e085 100644
--- a/dts/src/arm/tny_a9263.dts
+++ b/dts/src/arm/tny_a9263.dts
@@ -42,50 +42,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi0: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
};
diff --git a/dts/src/arm/twl4030.dtsi b/dts/src/arm/twl4030.dtsi
index 36ae9160b5..16533b62b0 100644
--- a/dts/src/arm/twl4030.dtsi
+++ b/dts/src/arm/twl4030.dtsi
@@ -23,6 +23,8 @@
compatible = "ti,twl4030-bci";
interrupts = <9>, <2>;
bci3v1-supply = <&vusb3v1>;
+ io-channels = <&twl_madc 11>;
+ io-channel-names = "vac";
};
watchdog {
diff --git a/dts/src/arm/uniphier-ld4-ref.dts b/dts/src/arm/uniphier-ld4-ref.dts
index e0da4ee21c..4817ebb28e 100644
--- a/dts/src/arm/uniphier-ld4-ref.dts
+++ b/dts/src/arm/uniphier-ld4-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-ld4.dtsi b/dts/src/arm/uniphier-ld4.dtsi
index 4f5fe15eae..fb2fd9605b 100644
--- a/dts/src/arm/uniphier-ld4.dtsi
+++ b/dts/src/arm/uniphier-ld4.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -201,7 +165,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-ld6b-ref.dts b/dts/src/arm/uniphier-ld6b-ref.dts
index a397a8811c..96db4abc02 100644
--- a/dts/src/arm/uniphier-ld6b-ref.dts
+++ b/dts/src/arm/uniphier-ld6b-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-ld6b.dtsi b/dts/src/arm/uniphier-ld6b.dtsi
index 905c77d499..8b9a79731b 100644
--- a/dts/src/arm/uniphier-ld6b.dtsi
+++ b/dts/src/arm/uniphier-ld6b.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/*
diff --git a/dts/src/arm/uniphier-pro4-ace.dts b/dts/src/arm/uniphier-pro4-ace.dts
index fefc891492..11690b5793 100644
--- a/dts/src/arm/uniphier-pro4-ace.dts
+++ b/dts/src/arm/uniphier-pro4-ace.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -88,7 +52,7 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
diff --git a/dts/src/arm/uniphier-pro4-ref.dts b/dts/src/arm/uniphier-pro4-ref.dts
index 6077e634d1..4cf539245f 100644
--- a/dts/src/arm/uniphier-pro4-ref.dts
+++ b/dts/src/arm/uniphier-pro4-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-pro4-sanji.dts b/dts/src/arm/uniphier-pro4-sanji.dts
index 6c63c8bad8..2763cebcd7 100644
--- a/dts/src/arm/uniphier-pro4-sanji.dts
+++ b/dts/src/arm/uniphier-pro4-sanji.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -83,7 +47,7 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
diff --git a/dts/src/arm/uniphier-pro4.dtsi b/dts/src/arm/uniphier-pro4.dtsi
index 794a85a706..37400becf4 100644
--- a/dts/src/arm/uniphier-pro4.dtsi
+++ b/dts/src/arm/uniphier-pro4.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -233,7 +197,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi
index df07b555cb..9577769a0a 100644
--- a/dts/src/arm/uniphier-pro5.dtsi
+++ b/dts/src/arm/uniphier-pro5.dtsi
@@ -77,67 +77,67 @@
compatible = "operating-points-v2";
opp-shared;
- opp@100000000 {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
- opp@116667000 {
+ opp-116667000 {
opp-hz = /bits/ 64 <116667000>;
clock-latency-ns = <300>;
};
- opp@150000000 {
+ opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
- opp@175000000 {
+ opp-175000000 {
opp-hz = /bits/ 64 <175000000>;
clock-latency-ns = <300>;
};
- opp@200000000 {
+ opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
- opp@233334000 {
+ opp-233334000 {
opp-hz = /bits/ 64 <233334000>;
clock-latency-ns = <300>;
};
- opp@300000000 {
+ opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
};
- opp@350000000 {
+ opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
clock-latency-ns = <300>;
};
- opp@400000000 {
+ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <300>;
};
- opp@466667000 {
+ opp-466667000 {
opp-hz = /bits/ 64 <466667000>;
clock-latency-ns = <300>;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
clock-latency-ns = <300>;
};
- opp@700000000 {
+ opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
clock-latency-ns = <300>;
};
- opp@800000000 {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <300>;
};
- opp@933334000 {
+ opp-933334000 {
opp-hz = /bits/ 64 <933334000>;
clock-latency-ns = <300>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <300>;
};
- opp@1400000000 {
+ opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
clock-latency-ns = <300>;
};
@@ -320,7 +320,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-pxs2-gentil.dts b/dts/src/arm/uniphier-pxs2-gentil.dts
index cccc86658d..81560f75bf 100644
--- a/dts/src/arm/uniphier-pxs2-gentil.dts
+++ b/dts/src/arm/uniphier-pxs2-gentil.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -80,7 +44,7 @@
status = "okay";
eeprom@54 {
- compatible = "st,24c64";
+ compatible = "st,24c64", "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
};
diff --git a/dts/src/arm/uniphier-pxs2-vodka.dts b/dts/src/arm/uniphier-pxs2-vodka.dts
index 803a39aa39..dc2d0579c6 100644
--- a/dts/src/arm/uniphier-pxs2-vodka.dts
+++ b/dts/src/arm/uniphier-pxs2-vodka.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-pxs2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi
index 58c3e2f357..bace751d40 100644
--- a/dts/src/arm/uniphier-pxs2.dtsi
+++ b/dts/src/arm/uniphier-pxs2.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -97,35 +61,35 @@
compatible = "operating-points-v2";
opp-shared;
- opp@100000000 {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
- opp@150000000 {
+ opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
- opp@200000000 {
+ opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
- opp@300000000 {
+ opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
};
- opp@400000000 {
+ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <300>;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
clock-latency-ns = <300>;
};
- opp@800000000 {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <300>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <300>;
};
@@ -304,7 +268,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-ref-daughter.dtsi b/dts/src/arm/uniphier-ref-daughter.dtsi
index c62ae1a81f..7a1c29b558 100644
--- a/dts/src/arm/uniphier-ref-daughter.dtsi
+++ b/dts/src/arm/uniphier-ref-daughter.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&i2c0 {
diff --git a/dts/src/arm/uniphier-sld3-ref.dts b/dts/src/arm/uniphier-sld3-ref.dts
index eb63dcca92..70cda39a3d 100644
--- a/dts/src/arm/uniphier-sld3-ref.dts
+++ b/dts/src/arm/uniphier-sld3-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-sld3.dtsi b/dts/src/arm/uniphier-sld3.dtsi
index 01d77edac0..4082879366 100644
--- a/dts/src/arm/uniphier-sld3.dtsi
+++ b/dts/src/arm/uniphier-sld3.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -216,7 +180,7 @@
#size-cells = <1>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-sld8-ref.dts b/dts/src/arm/uniphier-sld8-ref.dts
index 737d276349..4536d5b712 100644
--- a/dts/src/arm/uniphier-sld8-ref.dts
+++ b/dts/src/arm/uniphier-sld8-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm/uniphier-sld8.dtsi b/dts/src/arm/uniphier-sld8.dtsi
index eb06fdc04b..9fb9167f2d 100644
--- a/dts/src/arm/uniphier-sld8.dtsi
+++ b/dts/src/arm/uniphier-sld8.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/ {
@@ -201,7 +165,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/dts/src/arm/uniphier-support-card.dtsi b/dts/src/arm/uniphier-support-card.dtsi
index f61dfec280..6c825f192e 100644
--- a/dts/src/arm/uniphier-support-card.dtsi
+++ b/dts/src/arm/uniphier-support-card.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&system_bus {
@@ -53,14 +17,14 @@
#size-cells = <1>;
ranges = <0x00000000 1 0x01f00000 0x00100000>;
- ethsc: ethernet@00000000 {
+ ethsc: ethernet@0 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <0x00000000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
};
- serialsc: uart@000b0000 {
+ serialsc: uart@b0000 {
compatible = "ns16550a";
reg = <0x000b0000 0x20>;
clock-frequency = <12288000>;
diff --git a/dts/src/arm/usb_a9260_common.dtsi b/dts/src/arm/usb_a9260_common.dtsi
index 7514b347cd..34a49995ed 100644
--- a/dts/src/arm/usb_a9260_common.dtsi
+++ b/dts/src/arm/usb_a9260_common.dtsi
@@ -34,50 +34,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/usb_a9263.dts b/dts/src/arm/usb_a9263.dts
index bfc48a2724..482381c1c9 100644
--- a/dts/src/arm/usb_a9263.dts
+++ b/dts/src/arm/usb_a9263.dts
@@ -62,50 +62,69 @@
};
};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
+ ebi0: ebi@10000000 {
status = "okay";
- at91bootstrap@0 {
- label = "at91bootstrap";
- reg = <0x0 0x20000>;
- };
-
- barebox@20000 {
- label = "barebox";
- reg = <0x20000 0x40000>;
- };
-
- bareboxenv@60000 {
- label = "bareboxenv";
- reg = <0x60000 0x20000>;
- };
-
- bareboxenv2@80000 {
- label = "bareboxenv2";
- reg = <0x80000 0x20000>;
- };
-
- oftree@80000 {
- label = "oftree";
- reg = <0xa0000 0x20000>;
- };
-
- kernel@a0000 {
- label = "kernel";
- reg = <0xc0000 0x400000>;
- };
-
- rootfs@4a0000 {
- label = "rootfs";
- reg = <0x4c0000 0x7800000>;
- };
-
- data@7ca0000 {
- label = "data";
- reg = <0x7cc0000 0x8340000>;
+ nand_controller: nand-controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ barebox@20000 {
+ label = "barebox";
+ reg = <0x20000 0x40000>;
+ };
+
+ bareboxenv@60000 {
+ label = "bareboxenv";
+ reg = <0x60000 0x20000>;
+ };
+
+ bareboxenv2@80000 {
+ label = "bareboxenv2";
+ reg = <0x80000 0x20000>;
+ };
+
+ oftree@80000 {
+ label = "oftree";
+ reg = <0xa0000 0x20000>;
+ };
+
+ kernel@a0000 {
+ label = "kernel";
+ reg = <0xc0000 0x400000>;
+ };
+
+ rootfs@4a0000 {
+ label = "rootfs";
+ reg = <0x4c0000 0x7800000>;
+ };
+
+ data@7ca0000 {
+ label = "data";
+ reg = <0x7cc0000 0x8340000>;
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm/vf610-zii-dev-rev-b.dts b/dts/src/arm/vf610-zii-dev-rev-b.dts
index 37f9542761..acdf12ad06 100644
--- a/dts/src/arm/vf610-zii-dev-rev-b.dts
+++ b/dts/src/arm/vf610-zii-dev-rev-b.dts
@@ -78,6 +78,7 @@
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
+ eeprom-length = <512>;
ports {
#address-cells = <1>;
@@ -163,6 +164,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
+ eeprom-length = <512>;
ports {
#address-cells = <1>;
diff --git a/dts/src/arm64/actions/s900-bubblegum-96.dts b/dts/src/arm64/actions/s900-bubblegum-96.dts
new file mode 100644
index 0000000000..a0c3484dbd
--- /dev/null
+++ b/dts/src/arm64/actions/s900-bubblegum-96.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s900.dtsi"
+
+/ {
+ compatible = "ucrobotics,bubblegum-96", "actions,s900";
+ model = "Bubblegum-96";
+
+ aliases {
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&timer {
+ clocks = <&hosc>;
+};
+
+&uart5 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/actions/s900.dtsi b/dts/src/arm64/actions/s900.dtsi
new file mode 100644
index 0000000000..11406f6d3a
--- /dev/null
+++ b/dts/src/arm64/actions/s900.dtsi
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "actions,s900";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secmon@1f000000 {
+ reg = <0x0 0x1f000000 0x0 0x1000000>;
+ no-map;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ hosc: hosc {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@e00f1000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe00f1000 0x0 0x1000>,
+ <0x0 0xe00f2000 0x0 0x2000>,
+ <0x0 0xe00f4000 0x0 0x2000>,
+ <0x0 0xe00f6000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ uart0: serial@e0120000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe0120000 0x0 0x2000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: serial@e0122000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe0122000 0x0 0x2000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@e0124000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe0124000 0x0 0x2000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: serial@e0126000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe0126000 0x0 0x2000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@e0128000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe0128000 0x0 0x2000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart5: serial@e012a000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe012a000 0x0 0x2000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart6: serial@e012c000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe012c000 0x0 0x2000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer: timer@e0228000 {
+ compatible = "actions,s900-timer";
+ reg = <0x0 0xe0228000 0x0 0x8000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "timer1";
+ };
+ };
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
index 6872135d7f..0d1f026d83 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts
@@ -67,6 +67,14 @@
};
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -77,6 +85,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/dts/src/arm64/allwinner/sun50i-a64-orangepi-win.dts b/dts/src/arm64/allwinner/sun50i-a64-orangepi-win.dts
new file mode 100644
index 0000000000..5f8ff4017d
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-orangepi-win.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Win/Win Plus";
+ compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
index 790d14daaa..24f1aac366 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
@@ -46,5 +46,20 @@
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
- /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
+ /* TODO: Camera, touchscreen, etc. */
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
index c680ed385d..08cda24ea1 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts
@@ -52,6 +52,10 @@
aliases {
serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
};
chosen {
@@ -66,10 +70,23 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ status = "okay";
+
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -80,6 +97,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -91,16 +115,49 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
+/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+/* On Wifi/BT connector, with RTS/CTS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ status = "disabled";
+};
+
+/* On Pi-2 connector */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+/* On Euler connector */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";
+};
+
+/* On Euler connector, RTS/CTS optional */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "disabled";
+};
+
&usb_otg {
dr_mode = "host";
status = "okay";
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
new file mode 100644
index 0000000000..17eb1cc5bf
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun50i-a64-pine64.dts, which is:
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-sopine.dtsi"
+
+/ {
+ model = "SoPine with baseboard";
+ compatible = "pine64,sopine-baseboard", "pine64,sopine",
+ "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc1v8: vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc1v8>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi
new file mode 100644
index 0000000000..475518b031
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun50i-a64-pine64.dts, which is:
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun50i-a64.dtsi"
+
+/ {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ non-removable;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi
index 166c9ef884..9d00622ce8 100644
--- a/dts/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi
@@ -43,6 +43,7 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
@@ -129,6 +130,12 @@
#size-cells = <1>;
ranges;
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun50i-a64-system-controller",
+ "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -204,6 +211,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
@@ -281,6 +310,21 @@
bias-pull-up;
};
+ rmii_pins: rmii_pins {
+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+ "PD18", "PD19", "PD20", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
+ rgmii_pins: rgmii_pins {
+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+ "PD13", "PD15", "PD16", "PD17", "PD18",
+ "PD19", "PD20", "PD21", "PD22", "PD23";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
@@ -295,6 +339,26 @@
pins = "PG8", "PG9";
function = "uart1";
};
+
+ uart2_pins: uart2-pins {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
+
+ uart3_pins: uart3-pins {
+ pins = "PD0", "PD1";
+ function = "uart3";
+ };
+
+ uart4_pins: uart4-pins {
+ pins = "PD2", "PD3";
+ function = "uart4";
+ };
+
+ uart4_rts_cts_pins: uart4-rts-cts-pins {
+ pins = "PD4", "PD5";
+ function = "uart4";
+ };
};
uart0: serial@1c28000 {
@@ -303,8 +367,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 67>;
- resets = <&ccu 46>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -314,8 +378,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 68>;
- resets = <&ccu 47>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -325,8 +389,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 69>;
- resets = <&ccu 48>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@@ -336,8 +400,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 70>;
- resets = <&ccu 49>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
@@ -347,8 +411,8 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 71>;
- resets = <&ccu 50>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
@@ -356,8 +420,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 63>;
- resets = <&ccu 42>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -367,8 +431,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 64>;
- resets = <&ccu 43>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -378,11 +442,31 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu 65>;
- resets = <&ccu 44>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun50i-a64-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x100>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
gic: interrupt-controller@1c81000 {
@@ -417,12 +501,31 @@
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_rsb_pins: rsb@0 {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ };
+ };
+
+ r_rsb: rsb@1f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 6>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts b/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts
new file mode 100644
index 0000000000..9689087611
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO 2";
+ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
index dfecc17dcc..a8296feee8 100644
--- a/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -59,6 +59,7 @@
};
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -91,6 +92,16 @@
};
};
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
@@ -126,12 +137,28 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts
new file mode 100644
index 0000000000..d906b302cb
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun50i-h5-orangepi-pc2.dts, which is:
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Xunlong Orange Pi Prime";
+ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
+ };
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A ports' VBUS is always on */
+ usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts
new file mode 100644
index 0000000000..b6b7a561df
--- /dev/null
+++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Zero Plus2";
+ compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
index a84e276226..dc478d094c 100644
--- a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
@@ -121,19 +121,42 @@
};
};
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ethmac {
status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -154,7 +177,7 @@
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@@ -198,32 +221,9 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&ethmac {
- status = "okay";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&hdmi_tx {
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi
index 436b875060..35b8c88c32 100644
--- a/dts/src/arm64/amlogic/meson-gx.dtsi
+++ b/dts/src/arm64/amlogic/meson-gx.dtsi
@@ -200,7 +200,7 @@
};
scpi_sensors: sensors {
- compatible = "arm,scpi-sensors";
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
@@ -304,6 +304,15 @@
status = "disabled";
};
+ spicc: spi@8d80 {
+ compatible = "amlogic,meson-gx-spicc";
+ reg = <0x0 0x08d80 0x0 0x80>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
diff --git a/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts
new file mode 100644
index 0000000000..fa462831cc
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ stat {
+ label = "nanopi-k2:blue:stat";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ vdd_5v: regulator-vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vddio_ao18: regulator-vddio-ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddio_ao3v3: regulator-vddio-ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_tf: regulator-vddio-tf {
+ compatible = "regulator-gpio";
+
+ regulator-name = "VDDIO_TF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ wifi_32k: wifi-32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi_32k>;
+ clock-names = "ext_clock";
+ };
+
+ vcc1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ethmac {
+ status = "okay";
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&eth_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ };
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <200000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddio_ao3v3>;
+ vqmmc-supply = <&vddio_ao18>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+/* SD */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vddio_ao3v3>;
+ vqmmc-supply = <&vddio_tf>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "disabled";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc3v3>;
+ vqmmc-supply = <&vcc1v8>;
+};
+
+/* DBG_UART */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* Bluetooth on AP6212 */
+&uart_A {
+ status = "disabled";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+};
+
+/* 40-pin CON1 */
+&uart_C {
+ status = "disabled";
+ pinctrl-0 = <&uart_c_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&vdd_5v>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
index 87198eafb0..a1078b3e1c 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -165,10 +165,10 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
&ethmac {
@@ -195,12 +195,32 @@
};
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -260,28 +280,8 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&hdmi_tx {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts
index 54a9c6a6b3..d147c853ab 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts
@@ -137,16 +137,6 @@
};
};
-&scpi_clocks {
- status = "disabled";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
@@ -172,6 +162,33 @@
};
};
+&gpio_ao {
+ /*
+ * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
&pinctrl_aobus {
gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
"USB HUB nRESET", "USB OTG Power En",
@@ -223,55 +240,15 @@
"";
};
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&i2c_A {
- status = "okay";
- pinctrl-0 = <&i2c_a_pins>;
- pinctrl-names = "default";
-};
-
-&gpio_ao {
- /*
- * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub {
- gpio-hog;
- gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_otg_pwr>;
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
&saradc {
status = "okay";
vref-supply = <&vcc1v8>;
};
+&scpi_clocks {
+ status = "disabled";
+};
+
/* SD */
&sd_emmc_b {
status = "okay";
@@ -309,3 +286,26 @@
vmmc-supply = <&vcc3v3>;
vqmmc-supply = <&vcc1v8>;
};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
index 3c6c0b7f41..d904deb101 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi
@@ -126,7 +126,7 @@
clock-names = "ext_clock";
};
- cvbs-connector {
+ cvbs_connector: cvbs-connector {
compatible = "composite-video-connector";
port {
@@ -148,34 +148,36 @@
};
};
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
-&ir {
+&hdmi_tx {
status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_pwr>;
-};
-
-&usb1_phy {
- status = "okay";
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
};
-&usb0 {
+&ir {
status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
};
-&usb1 {
+&pwm_ef {
status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
};
/* Wireless SDIO Module */
@@ -198,7 +200,7 @@
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@@ -242,28 +244,26 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
};
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
};
-&hdmi_tx {
+&usb1_phy {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
};
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
index aefa66dff7..346753fb63 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
@@ -111,18 +111,6 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
@@ -149,21 +137,18 @@
};
};
-&usb0_phy {
- status = "okay";
- phy-supply = <&usb_vbus>;
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
+&ir {
status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
};
-&usb1 {
+&pwm_ef {
status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
};
/* Wireless SDIO Module */
@@ -186,7 +171,7 @@
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@@ -229,10 +214,25 @@
vmmcq-sumpply = <&vcc_1v8>;
};
-&pwm_ef {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_vbus>;
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
};
diff --git a/dts/src/arm64/amlogic/meson-gxbb-wetek-hub.dts b/dts/src/arm64/amlogic/meson-gxbb-wetek-hub.dts
index f057fb48fe..1878ac2b2b 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-wetek-hub.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-wetek-hub.dts
@@ -59,10 +59,10 @@
panic-indicator;
};
};
+};
- cvbs-connector {
- status = "disabled";
- };
+&cvbs_connector {
+ status = "disabled";
};
&ethmac {
diff --git a/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts b/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
index 743acb5f5d..e76ac313fe 100644
--- a/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
+++ b/dts/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
@@ -85,6 +85,34 @@
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
};
};
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
&ethmac {
@@ -113,6 +141,18 @@
};
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
diff --git a/dts/src/arm64/amlogic/meson-gxbb.dtsi b/dts/src/arm64/amlogic/meson-gxbb.dtsi
index 86105a6969..17d3efdf14 100644
--- a/dts/src/arm64/amlogic/meson-gxbb.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxbb.dtsi
@@ -97,13 +97,6 @@
};
};
-&ethmac {
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
-};
-
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
@@ -249,9 +242,119 @@
function = "spdif_out_ao";
};
};
+
+ ao_cec_pins: ao_cec {
+ mux {
+ groups = "ao_cec";
+ function = "cec_ao";
+ };
+ };
+
+ ee_cec_pins: ee_cec {
+ mux {
+ groups = "ee_cec";
+ function = "cec_ao";
+ };
+ };
+ };
+};
+
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>; /* Do Nothing */
+ };
+};
+
+&cbus {
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
+};
+
+&ethmac {
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+};
+
+&hdmi_tx {
+ compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_HDMI_TX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI_PCLK>,
+ <&clkc CLKID_CLK81>,
+ <&clkc CLKID_GCLK_VENCI_INT0>;
+ clock-names = "isfr", "iahb", "venci";
+};
+
+&hiubus {
+ clkc: clock-controller@0 {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
};
};
+&hwrng {
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_AO {
+ clocks = <&clkc CLKID_AO_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
@@ -262,7 +365,7 @@
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
- <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
@@ -290,6 +393,22 @@
};
};
+ spi_pins: spi {
+ mux {
+ groups = "spi_miso",
+ "spi_mosi",
+ "spi_sclk";
+ function = "spi";
+ };
+ };
+
+ spi_ss0_pins: spi-ss0 {
+ mux {
+ groups = "spi_ss0";
+ function = "spi";
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@@ -521,67 +640,6 @@
};
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
- };
-};
-
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>; /* Do Nothing */
- };
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_AO {
- clocks = <&clkc CLKID_AO_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
-};
-
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
@@ -613,6 +671,13 @@
clock-names = "core", "clkin0", "clkin1";
};
+&spicc {
+ clocks = <&clkc CLKID_SPICC>;
+ clock-names = "core";
+ resets = <&reset RESET_PERIPHS_SPICC>;
+ num-cs = <1>;
+};
+
&spifc {
clocks = <&clkc CLKID_SPI>;
};
@@ -620,20 +685,3 @@
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
-
-&hwrng {
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
-};
-
-&hdmi_tx {
- compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMI_SYSTEM_RESET>,
- <&reset RESET_HDMI_TX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
- clock-names = "isfr", "iahb", "venci";
-};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts b/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
index f9fbfdad8d..3e0c023d6a 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905d-p230.dts
@@ -84,6 +84,17 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
};
/* P230 has exclusive choice between internal or external PHY */
@@ -113,6 +124,19 @@
};
};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
index 3c8b0b51ef..72c5a9f64c 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -54,6 +54,29 @@
linux,default-trigger = "default-on";
};
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
};
&i2c_A {
@@ -95,7 +118,7 @@
};
&sd_emmc_a {
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts
new file mode 100644
index 0000000000..890821d6e5
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "meson-gxl-s905x-p212.dtsi"
+
+/ {
+ compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "Libre Technology CC";
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ system {
+ label = "librecomputer:system-status";
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+
+ blue {
+ label = "librecomputer:blue";
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/*
+ * The following devices exists but are exposed on the general
+ * purpose GPIO header. End user may well decide to use those pins
+ * for another purpose
+ */
+
+&sd_emmc_a {
+ status = "disabled";
+};
+
+&uart_A {
+ status = "disabled";
+};
+
+&wifi32k {
+ status = "disabled";
+};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 8873c058fa..6633a5d8fd 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -140,10 +140,10 @@
};
};
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
&ethmac {
@@ -152,12 +152,32 @@
phy-handle = <&internal_phy>;
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@@ -217,28 +237,8 @@
vqmmc-supply = <&vddio_boot>;
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&hdmi_tx {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
index db31e093f4..6ab17c1eee 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dts
@@ -58,6 +58,17 @@
};
};
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
};
&cvbs_vdac_port {
@@ -66,6 +77,18 @@
};
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x.dtsi b/dts/src/arm64/amlogic/meson-gxl-s905x.dtsi
index 0f78d836ed..3314a0b3da 100644
--- a/dts/src/arm64/amlogic/meson-gxl-s905x.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl-s905x.dtsi
@@ -48,7 +48,7 @@
compatible = "amlogic,s905x", "amlogic,meson-gxl";
};
-/* S905X Only has access to its internal PHY */
+/* S905X only has access to its internal PHY */
&ethmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
diff --git a/dts/src/arm64/amlogic/meson-gxl.dtsi b/dts/src/arm64/amlogic/meson-gxl.dtsi
index d8e096dff1..8d4f3160a0 100644
--- a/dts/src/arm64/amlogic/meson-gxl.dtsi
+++ b/dts/src/arm64/amlogic/meson-gxl.dtsi
@@ -190,9 +190,59 @@
function = "spdif_out_ao";
};
};
+
+ ao_cec_pins: ao_cec {
+ mux {
+ groups = "ao_cec";
+ function = "cec_ao";
+ };
+ };
+
+ ee_cec_pins: ee_cec {
+ mux {
+ groups = "ee_cec";
+ function = "cec_ao";
+ };
+ };
};
};
+&hdmi_tx {
+ compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_HDMI_TX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI_PCLK>,
+ <&clkc CLKID_CLK81>,
+ <&clkc CLKID_GCLK_VENCI_INT0>;
+ clock-names = "isfr", "iahb", "venci";
+};
+
+&hiubus {
+ clkc: clock-controller@0 {
+ compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_AO {
+ clocks = <&clkc CLKID_AO_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxl-periphs-pinctrl";
@@ -203,12 +253,12 @@
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
- <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_periphs 0 14 101>;
+ gpio-ranges = <&pinctrl_periphs 0 10 101>;
};
emmc_pins: emmc {
@@ -231,6 +281,22 @@
};
};
+ spi_pins: spi {
+ mux {
+ groups = "spi_miso",
+ "spi_mosi",
+ "spi_sclk";
+ function = "spi";
+ };
+ };
+
+ spi_ss0_pins: spi-ss0 {
+ mux {
+ groups = "spi_ss0";
+ function = "spi";
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@@ -354,6 +420,20 @@
};
};
+ eth_link_led_pins: eth_link_led {
+ mux {
+ groups = "eth_link_led";
+ function = "eth_led";
+ };
+ };
+
+ eth_act_led_pins: eth_act_led {
+ mux {
+ groups = "eth_act_led";
+ function = "eth_led";
+ };
+ };
+
pwm_a_pins: pwm_a {
mux {
groups = "pwm_a";
@@ -501,30 +581,6 @@
};
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
- };
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_AO {
- clocks = <&clkc CLKID_AO_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
-};
-
&saradc {
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
@@ -556,6 +612,13 @@
clock-names = "core", "clkin0", "clkin1";
};
+&spicc {
+ clocks = <&clkc CLKID_SPICC>;
+ clock-names = "core";
+ resets = <&reset RESET_PERIPHS_SPICC>;
+ num-cs = <1>;
+};
+
&spifc {
clocks = <&clkc CLKID_SPI>;
};
@@ -563,15 +626,3 @@
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
-
-&hdmi_tx {
- compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMI_SYSTEM_RESET>,
- <&reset RESET_HDMI_TX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
- clock-names = "isfr", "iahb", "venci";
-};
diff --git a/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts b/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
index 11b0bf46a9..5f626d6830 100644
--- a/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
+++ b/dts/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
@@ -113,11 +113,49 @@
};
};
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ethmac {
status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
+
+ pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ amlogic,tx-delay-ns = <2>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
};
&ir {
@@ -164,47 +202,8 @@
vqmmc-supply = <&vddio_boot>;
};
-&ethmac {
- status = "okay";
-
- pinctrl-0 = <&eth_pins>;
- pinctrl-names = "default";
-
- /* Select external PHY by default */
- phy-handle = <&external_phy>;
-
- amlogic,tx-delay-ns = <2>;
-
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
- /* External PHY is in RGMII */
- phy-mode = "rgmii";
-};
-
-&external_mdio {
- external_phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- max-speed = <1000>;
- };
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&hdmi_tx {
+&uart_AO {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
diff --git a/dts/src/arm64/amlogic/meson-gxm-rbox-pro.dts b/dts/src/arm64/amlogic/meson-gxm-rbox-pro.dts
new file mode 100644
index 0000000000..08f1dd69b6
--- /dev/null
+++ b/dts/src/arm64/amlogic/meson-gxm-rbox-pro.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * Based on nexbox-a1:
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+
+/ {
+ compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
+ model = "R-Box Pro";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "rbox-pro:blue:on";
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ red {
+ label = "rbox-pro:red:standby";
+ gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ retain-state-suspended;
+ panic-indicator;
+ };
+ };
+
+ vddio_boot: regulator-vddio-boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+&ethmac {
+ status = "okay";
+
+ pinctrl-0 = <&eth_pins>;
+ pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ amlogic,tx-delay-ns = <2>;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: brcmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi
index bfe7d683a4..e8b7413ec8 100644
--- a/dts/src/arm64/arm/juno-base.dtsi
+++ b/dts/src/arm64/arm/juno-base.dtsi
@@ -53,7 +53,6 @@
#global-interrupts = <1>;
dma-coherent;
power-domains = <&scpi_devpd 0>;
- status = "disabled";
};
gic: interrupt-controller@2c010000 {
@@ -202,6 +201,15 @@
};
};
+ cpu_debug0: cpu_debug@22010000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x22010000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>;
@@ -252,6 +260,15 @@
};
};
+ cpu_debug1: cpu_debug@22110000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x22110000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm1: etm@22140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22140000 0 0x1000>;
@@ -266,6 +283,15 @@
};
};
+ cpu_debug2: cpu_debug@23010000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23010000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm2: etm@23040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23040000 0 0x1000>;
@@ -330,6 +356,15 @@
};
};
+ cpu_debug3: cpu_debug@23110000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23110000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm3: etm@23140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23140000 0 0x1000>;
@@ -344,6 +379,15 @@
};
};
+ cpu_debug4: cpu_debug@23210000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23210000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm4: etm@23240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23240000 0 0x1000>;
@@ -358,6 +402,15 @@
};
};
+ cpu_debug5: cpu_debug@23310000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0x23310000 0x0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+ };
+
etm5: etm@23340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23340000 0 0x1000>;
@@ -546,7 +599,6 @@
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
- status = "disabled";
};
smmu_hdlcd0: iommu@7fb20000 {
@@ -556,7 +608,6 @@
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
- status = "disabled";
};
smmu_usb: iommu@7fb30000 {
@@ -567,7 +618,6 @@
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
- status = "disabled";
};
dma@7ff00000 {
diff --git a/dts/src/arm64/arm/juno-r1.dts b/dts/src/arm64/arm/juno-r1.dts
index 0e8943ab94..aed6389468 100644
--- a/dts/src/arm64/arm/juno-r1.dts
+++ b/dts/src/arm64/arm/juno-r1.dts
@@ -281,3 +281,27 @@
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
+
+&cpu_debug0 {
+ cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+ cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+ cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+ cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+ cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+ cpu = <&A53_3>;
+};
diff --git a/dts/src/arm64/arm/juno-r2.dts b/dts/src/arm64/arm/juno-r2.dts
index 405e2fba02..b39b6d6ec5 100644
--- a/dts/src/arm64/arm/juno-r2.dts
+++ b/dts/src/arm64/arm/juno-r2.dts
@@ -281,3 +281,27 @@
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
+
+&cpu_debug0 {
+ cpu = <&A72_0>;
+};
+
+&cpu_debug1 {
+ cpu = <&A72_1>;
+};
+
+&cpu_debug2 {
+ cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+ cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+ cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+ cpu = <&A53_3>;
+};
diff --git a/dts/src/arm64/arm/juno.dts b/dts/src/arm64/arm/juno.dts
index 0220494c9b..c9236c4b96 100644
--- a/dts/src/arm64/arm/juno.dts
+++ b/dts/src/arm64/arm/juno.dts
@@ -268,3 +268,27 @@
};
};
};
+
+&cpu_debug0 {
+ cpu = <&A57_0>;
+};
+
+&cpu_debug1 {
+ cpu = <&A57_1>;
+};
+
+&cpu_debug2 {
+ cpu = <&A53_0>;
+};
+
+&cpu_debug3 {
+ cpu = <&A53_1>;
+};
+
+&cpu_debug4 {
+ cpu = <&A53_2>;
+};
+
+&cpu_debug5 {
+ cpu = <&A53_3>;
+};
diff --git a/dts/src/arm64/broadcom/bcm2835-rpi.dtsi b/dts/src/arm64/broadcom/bcm2835-rpi.dtsi
index a7b5ce1337..e55b362b9d 100644
--- a/dts/src/arm64/broadcom/bcm2835-rpi.dtsi
+++ b/dts/src/arm64/broadcom/bcm2835-rpi.dtsi
@@ -65,13 +65,13 @@
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
- status = "okay";
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
bus-width = <4>;
};
diff --git a/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts b/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
index c309633a1e..972f14db28 100644
--- a/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
+++ b/dts/src/arm64/broadcom/bcm2837-rpi-3-b.dts
@@ -22,3 +22,20 @@
&uart1 {
status = "okay";
};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
+ bus-width = <4>;
+};
diff --git a/dts/src/arm64/broadcom/bcm2837.dtsi b/dts/src/arm64/broadcom/bcm2837.dtsi
index 19f2fe620a..2d5de6f0f7 100644
--- a/dts/src/arm64/broadcom/bcm2837.dtsi
+++ b/dts/src/arm64/broadcom/bcm2837.dtsi
@@ -75,6 +75,10 @@
interrupts = <8>;
};
+&cpu_thermal {
+ coefficients = <(-538) 412000>;
+};
+
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2837-thermal";
diff --git a/dts/src/arm64/broadcom/bcm283x.dtsi b/dts/src/arm64/broadcom/bcm283x.dtsi
index 9444a9a9ba..431dcfc900 100644
--- a/dts/src/arm64/broadcom/bcm283x.dtsi
+++ b/dts/src/arm64/broadcom/bcm283x.dtsi
@@ -24,6 +24,26 @@
bootargs = "earlyprintk console=ttyAMA0";
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <80000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -435,6 +455,7 @@
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
status = "disabled";
};
@@ -573,6 +594,8 @@
#size-cells = <0>;
clocks = <&clk_usb>;
clock-names = "otg";
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
};
v3d: v3d@7ec00000 {
@@ -608,4 +631,8 @@
clock-frequency = <480000000>;
};
};
+
+ usbphy: phy {
+ compatible = "usb-nop-xceiv";
+ };
};
diff --git a/dts/src/arm64/broadcom/ns2.dtsi b/dts/src/arm64/broadcom/ns2.dtsi
index 35a309ae3e..35c8457e3d 100644
--- a/dts/src/arm64/broadcom/ns2.dtsi
+++ b/dts/src/arm64/broadcom/ns2.dtsi
@@ -460,6 +460,20 @@
};
};
+ usbdrd_phy: phy@66000960 {
+ #phy-cells = <0>;
+ compatible = "brcm,ns2-drd-phy";
+ reg = <0x66000960 0x24>,
+ <0x67012800 0x4>,
+ <0x6501d148 0x4>,
+ <0x664d0700 0x4>;
+ reg-names = "icfg", "rst-ctrl",
+ "crmu-ctrl", "usb2-strap";
+ id-gpios = <&gpio_g 30 0>;
+ vbus-gpios = <&gpio_g 31 0>;
+ status = "disabled";
+ };
+
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi b/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi
new file mode 100644
index 0000000000..5dca7d1025
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi
@@ -0,0 +1,131 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "stingray.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
+ compatible = "regulator-gpio";
+ regulator-name = "sdio0_vddo_ctrl_reg";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pca9505 18 0>;
+ states = <3300000 0x0
+ 1800000 0x1>;
+ };
+
+ sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
+ compatible = "regulator-gpio";
+ regulator-name = "sdio1_vddo_ctrl_reg";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pca9505 19 0>;
+ states = <3300000 0x0
+ 1800000 0x1>;
+ };
+};
+
+&memory { /* Default DRAM banks */
+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
+ <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9505: pca9505@20 {
+ compatible = "nxp,pca9505";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ pcf8574: pcf8574@20 {
+ compatible = "nxp,pcf8574a";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x27>;
+ };
+};
+
+&nand {
+ status = "ok";
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <16>;
+ brcm,nand-oob-sector-size = <16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&sdio0 {
+ vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
+ non-removable;
+ full-pwr-cycle;
+ status = "okay";
+};
+
+&sdio1 {
+ vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
+ full-pwr-cycle;
+ status = "okay";
+};
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742k.dts b/dts/src/arm64/broadcom/stingray/bcm958742k.dts
new file mode 100644
index 0000000000..5671669ba3
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/bcm958742k.dts
@@ -0,0 +1,78 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm958742-base.dtsi"
+
+/ {
+ compatible = "brcm,bcm958742k", "brcm,stingray";
+ model = "Stingray Combo SVK (BCM958742K)";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&ssp0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio_hsls 34 0>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&ssp1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio_hsls 96 0>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/dts/src/arm64/broadcom/stingray/bcm958742t.dts b/dts/src/arm64/broadcom/stingray/bcm958742t.dts
new file mode 100644
index 0000000000..6ebe399fda
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/bcm958742t.dts
@@ -0,0 +1,40 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm958742-base.dtsi"
+
+/ {
+ compatible = "brcm,bcm958742t", "brcm,stingray";
+ model = "Stingray SST100 (BCM958742T)";
+};
diff --git a/dts/src/arm64/broadcom/stingray/stingray-clock.dtsi b/dts/src/arm64/broadcom/stingray/stingray-clock.dtsi
new file mode 100644
index 0000000000..cbc43376e2
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/stingray-clock.dtsi
@@ -0,0 +1,170 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/clock/bcm-sr.h>
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ crmu_ref25m: crmu_ref25m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&osc>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ genpll0: genpll0@0001d104 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll0";
+ reg = <0x0001d104 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll0", "clk_125", "clk_scr",
+ "clk_250", "clk_pcie_axi",
+ "clk_paxc_axi_x2",
+ "clk_paxc_axi";
+ };
+
+ genpll3: genpll3@0001d1e0 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll3";
+ reg = <0x0001d1e0 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll3", "clk_hsls",
+ "clk_sdio";
+ };
+
+ genpll4: genpll4@0001d214 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll4";
+ reg = <0x0001d214 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll4", "clk_ccn",
+ "clk_tpiu_pll", "noc_clk",
+ "pll_chclk_fs4",
+ "clk_bridge_fscpu";
+ };
+
+ genpll5: genpll5@0001d248 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll5";
+ reg = <0x0001d248 0x32>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll5", "fs4_hf_clk",
+ "crypto_ae_clk", "raid_ae_clk";
+ };
+
+ lcpll0: lcpll0@0001d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-lcpll0";
+ reg = <0x0001d0c4 0x3c>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "clk_sata_refp",
+ "clk_sata_refn", "clk_sata_350",
+ "clk_sata_500";
+ };
+
+ lcpll1: lcpll1@0001d138 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-lcpll1";
+ reg = <0x0001d138 0x3c>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll1", "clk_wanpn",
+ "clk_usb_ref",
+ "timesync_evt_clk";
+ };
+
+ hsls_clk: hsls_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 1>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+
+ hsls_div2_clk: hsls_div2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+
+ };
+
+ hsls_div4_clk: hsls_div4_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsls_25m_clk: hsls_25m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&crmu_ref25m>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+
+ hsls_25m_div2_clk: hsls_25m_div2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hsls_25m_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ sdio0_clk: sdio0_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+
+ sdio1_clk: sdio1_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
diff --git a/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi b/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi
new file mode 100644
index 0000000000..15214d05fe
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi
@@ -0,0 +1,345 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
+
+ pinconf: pinconf@00140000 {
+ compatible = "pinconf-single";
+ reg = <0x00140000 0x250>;
+ pinctrl-single,register-width = <32>;
+
+ /* pinconf functions */
+ };
+
+ pinmux: pinmux@0014029c {
+ compatible = "pinctrl-single";
+ reg = <0x0014029c 0x250>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xf>;
+ pinctrl-single,gpio-range = <
+ &range 0 154 MODE_GPIO
+ >;
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+ /* pinctrl functions */
+ tsio_pins: pinmux_gpio_14 {
+ pinctrl-single,pins = <
+ 0x038 MODE_NITRO /* tsio_0 */
+ 0x03c MODE_NITRO /* tsio_1 */
+ >;
+ };
+
+ nor_pins: pinmux_pnor_adv_n {
+ pinctrl-single,pins = <
+ 0x0ac MODE_PNOR /* nand_ce1_n */
+ 0x0b0 MODE_PNOR /* nand_ce0_n */
+ 0x0b4 MODE_PNOR /* nand_we_n */
+ 0x0b8 MODE_PNOR /* nand_wp_n */
+ 0x0bc MODE_PNOR /* nand_re_n */
+ 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
+ 0x0c4 MODE_PNOR /* nand_io0_0 */
+ 0x0c8 MODE_PNOR /* nand_io1_0 */
+ 0x0cc MODE_PNOR /* nand_io2_0 */
+ 0x0d0 MODE_PNOR /* nand_io3_0 */
+ 0x0d4 MODE_PNOR /* nand_io4_0 */
+ 0x0d8 MODE_PNOR /* nand_io5_0 */
+ 0x0dc MODE_PNOR /* nand_io6_0 */
+ 0x0e0 MODE_PNOR /* nand_io7_0 */
+ 0x0e4 MODE_PNOR /* nand_io8_0 */
+ 0x0e8 MODE_PNOR /* nand_io9_0 */
+ 0x0ec MODE_PNOR /* nand_io10_0 */
+ 0x0f0 MODE_PNOR /* nand_io11_0 */
+ 0x0f4 MODE_PNOR /* nand_io12_0 */
+ 0x0f8 MODE_PNOR /* nand_io13_0 */
+ 0x0fc MODE_PNOR /* nand_io14_0 */
+ 0x100 MODE_PNOR /* nand_io15_0 */
+ 0x104 MODE_PNOR /* nand_ale_0 */
+ 0x108 MODE_PNOR /* nand_cle_0 */
+ 0x040 MODE_PNOR /* pnor_adv_n */
+ 0x044 MODE_PNOR /* pnor_baa_n */
+ 0x048 MODE_PNOR /* pnor_bls_0_n */
+ 0x04c MODE_PNOR /* pnor_bls_1_n */
+ 0x050 MODE_PNOR /* pnor_cre */
+ 0x054 MODE_PNOR /* pnor_cs_2_n */
+ 0x058 MODE_PNOR /* pnor_cs_1_n */
+ 0x05c MODE_PNOR /* pnor_cs_0_n */
+ 0x060 MODE_PNOR /* pnor_we_n */
+ 0x064 MODE_PNOR /* pnor_oe_n */
+ 0x068 MODE_PNOR /* pnor_intr */
+ 0x06c MODE_PNOR /* pnor_dat_0 */
+ 0x070 MODE_PNOR /* pnor_dat_1 */
+ 0x074 MODE_PNOR /* pnor_dat_2 */
+ 0x078 MODE_PNOR /* pnor_dat_3 */
+ 0x07c MODE_PNOR /* pnor_dat_4 */
+ 0x080 MODE_PNOR /* pnor_dat_5 */
+ 0x084 MODE_PNOR /* pnor_dat_6 */
+ 0x088 MODE_PNOR /* pnor_dat_7 */
+ 0x08c MODE_PNOR /* pnor_dat_8 */
+ 0x090 MODE_PNOR /* pnor_dat_9 */
+ 0x094 MODE_PNOR /* pnor_dat_10 */
+ 0x098 MODE_PNOR /* pnor_dat_11 */
+ 0x09c MODE_PNOR /* pnor_dat_12 */
+ 0x0a0 MODE_PNOR /* pnor_dat_13 */
+ 0x0a4 MODE_PNOR /* pnor_dat_14 */
+ 0x0a8 MODE_PNOR /* pnor_dat_15 */
+ >;
+ };
+
+ nand_pins: pinmux_nand_ce1_n {
+ pinctrl-single,pins = <
+ 0x0ac MODE_NAND /* nand_ce1_n */
+ 0x0b0 MODE_NAND /* nand_ce0_n */
+ 0x0b4 MODE_NAND /* nand_we_n */
+ 0x0b8 MODE_NAND /* nand_wp_n */
+ 0x0bc MODE_NAND /* nand_re_n */
+ 0x0c0 MODE_NAND /* nand_rdy_bsy_n */
+ 0x0c4 MODE_NAND /* nand_io0_0 */
+ 0x0c8 MODE_NAND /* nand_io1_0 */
+ 0x0cc MODE_NAND /* nand_io2_0 */
+ 0x0d0 MODE_NAND /* nand_io3_0 */
+ 0x0d4 MODE_NAND /* nand_io4_0 */
+ 0x0d8 MODE_NAND /* nand_io5_0 */
+ 0x0dc MODE_NAND /* nand_io6_0 */
+ 0x0e0 MODE_NAND /* nand_io7_0 */
+ 0x0e4 MODE_NAND /* nand_io8_0 */
+ 0x0e8 MODE_NAND /* nand_io9_0 */
+ 0x0ec MODE_NAND /* nand_io10_0 */
+ 0x0f0 MODE_NAND /* nand_io11_0 */
+ 0x0f4 MODE_NAND /* nand_io12_0 */
+ 0x0f8 MODE_NAND /* nand_io13_0 */
+ 0x0fc MODE_NAND /* nand_io14_0 */
+ 0x100 MODE_NAND /* nand_io15_0 */
+ 0x104 MODE_NAND /* nand_ale_0 */
+ 0x108 MODE_NAND /* nand_cle_0 */
+ >;
+ };
+
+ pwm0_pins: pinmux_pwm_0 {
+ pinctrl-single,pins = <
+ 0x10c MODE_NITRO
+ >;
+ };
+
+ pwm1_pins: pinmux_pwm_1 {
+ pinctrl-single,pins = <
+ 0x110 MODE_NITRO
+ >;
+ };
+
+ pwm2_pins: pinmux_pwm_2 {
+ pinctrl-single,pins = <
+ 0x114 MODE_NITRO
+ >;
+ };
+
+ pwm3_pins: pinmux_pwm_3 {
+ pinctrl-single,pins = <
+ 0x118 MODE_NITRO
+ >;
+ };
+
+ dbu_rxd_pins: pinmux_uart1_sin_nitro {
+ pinctrl-single,pins = <
+ 0x11c MODE_NITRO /* dbu_rxd */
+ 0x120 MODE_NITRO /* dbu_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_sin_nand {
+ pinctrl-single,pins = <
+ 0x11c MODE_NAND /* uart1_sin */
+ 0x120 MODE_NAND /* uart1_out */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_sin {
+ pinctrl-single,pins = <
+ 0x124 MODE_NITRO /* uart2_sin */
+ 0x128 MODE_NITRO /* uart2_out */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_sin {
+ pinctrl-single,pins = <
+ 0x12c MODE_NITRO /* uart3_sin */
+ 0x130 MODE_NITRO /* uart3_out */
+ >;
+ };
+
+ i2s_pins: pinmux_i2s_bitclk {
+ pinctrl-single,pins = <
+ 0x134 MODE_NITRO /* i2s_bitclk */
+ 0x138 MODE_NITRO /* i2s_sdout */
+ 0x13c MODE_NITRO /* i2s_sdin */
+ 0x140 MODE_NITRO /* i2s_ws */
+ 0x144 MODE_NITRO /* i2s_mclk */
+ 0x148 MODE_NITRO /* i2s_spdif_out */
+ >;
+ };
+
+ qspi_pins: pinumx_qspi_hold_n {
+ pinctrl-single,pins = <
+ 0x14c MODE_NAND /* qspi_hold_n */
+ 0x150 MODE_NAND /* qspi_wp_n */
+ 0x154 MODE_NAND /* qspi_sck */
+ 0x158 MODE_NAND /* qspi_cs_n */
+ 0x15c MODE_NAND /* qspi_mosi */
+ 0x160 MODE_NAND /* qspi_miso */
+ >;
+ };
+
+ mdio_pins: pinumx_ext_mdio {
+ pinctrl-single,pins = <
+ 0x164 MODE_NITRO /* ext_mdio */
+ 0x168 MODE_NITRO /* ext_mdc */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_sda {
+ pinctrl-single,pins = <
+ 0x16c MODE_NITRO /* i2c0_sda */
+ 0x170 MODE_NITRO /* i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_sda {
+ pinctrl-single,pins = <
+ 0x174 MODE_NITRO /* i2c1_sda */
+ 0x178 MODE_NITRO /* i2c1_scl */
+ >;
+ };
+
+ sdio0_pins: pinmux_sdio0_cd_l {
+ pinctrl-single,pins = <
+ 0x17c MODE_NITRO /* sdio0_cd_l */
+ 0x180 MODE_NITRO /* sdio0_clk_sdcard */
+ 0x184 MODE_NITRO /* sdio0_data0 */
+ 0x188 MODE_NITRO /* sdio0_data1 */
+ 0x18c MODE_NITRO /* sdio0_data2 */
+ 0x190 MODE_NITRO /* sdio0_data3 */
+ 0x194 MODE_NITRO /* sdio0_data4 */
+ 0x198 MODE_NITRO /* sdio0_data5 */
+ 0x19c MODE_NITRO /* sdio0_data6 */
+ 0x1a0 MODE_NITRO /* sdio0_data7 */
+ 0x1a4 MODE_NITRO /* sdio0_cmd */
+ 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
+ 0x1ac MODE_NITRO /* sdio0_led_on */
+ 0x1b0 MODE_NITRO /* sdio0_wp */
+ >;
+ };
+
+ sdio1_pins: pinmux_sdio1_cd_l {
+ pinctrl-single,pins = <
+ 0x1b4 MODE_NITRO /* sdio1_cd_l */
+ 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
+ 0x1bc MODE_NITRO /* sdio1_data0 */
+ 0x1c0 MODE_NITRO /* sdio1_data1 */
+ 0x1c4 MODE_NITRO /* sdio1_data2 */
+ 0x1c8 MODE_NITRO /* sdio1_data3 */
+ 0x1cc MODE_NITRO /* sdio1_data4 */
+ 0x1d0 MODE_NITRO /* sdio1_data5 */
+ 0x1d4 MODE_NITRO /* sdio1_data6 */
+ 0x1d8 MODE_NITRO /* sdio1_data7 */
+ 0x1dc MODE_NITRO /* sdio1_cmd */
+ 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
+ 0x1e4 MODE_NITRO /* sdio1_led_on */
+ 0x1e8 MODE_NITRO /* sdio1_wp */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_sck_nand {
+ pinctrl-single,pins = <
+ 0x1ec MODE_NITRO /* spi0_sck */
+ 0x1f0 MODE_NITRO /* spi0_rxd */
+ 0x1f4 MODE_NITRO /* spi0_fss */
+ 0x1f8 MODE_NITRO /* spi0_txd */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_sck_nand {
+ pinctrl-single,pins = <
+ 0x1fc MODE_NITRO /* spi1_sck */
+ 0x200 MODE_NITRO /* spi1_rxd */
+ 0x204 MODE_NITRO /* spi1_fss */
+ 0x208 MODE_NITRO /* spi1_txd */
+ >;
+ };
+
+ nuart_pins: pinmux_uart0_sin_nitro {
+ pinctrl-single,pins = <
+ 0x20c MODE_NITRO /* nuart_rxd */
+ 0x210 MODE_NITRO /* nuart_txd */
+ >;
+ };
+
+ uart0_pins: pinumux_uart0_sin_nand {
+ pinctrl-single,pins = <
+ 0x20c MODE_NAND /* uart0_sin */
+ 0x210 MODE_NAND /* uart0_out */
+ 0x214 MODE_NAND /* uart0_rts */
+ 0x218 MODE_NAND /* uart0_cts */
+ 0x21c MODE_NAND /* uart0_dtr */
+ 0x220 MODE_NAND /* uart0_dcd */
+ 0x224 MODE_NAND /* uart0_dsr */
+ 0x228 MODE_NAND /* uart0_ri */
+ >;
+ };
+
+ drdu2_pins: pinmux_drdu2_overcurrent {
+ pinctrl-single,pins = <
+ 0x22c MODE_NITRO /* drdu2_overcurrent */
+ 0x230 MODE_NITRO /* drdu2_vbus_ppc */
+ 0x234 MODE_NITRO /* drdu2_vbus_present */
+ 0x238 MODE_NITRO /* drdu2_id */
+ >;
+ };
+
+ drdu3_pins: pinmux_drdu3_overcurrent {
+ pinctrl-single,pins = <
+ 0x23c MODE_NITRO /* drdu3_overcurrent */
+ 0x240 MODE_NITRO /* drdu3_vbus_ppc */
+ 0x244 MODE_NITRO /* drdu3_vbus_present */
+ 0x248 MODE_NITRO /* drdu3_id */
+ >;
+ };
+
+ usb3h_pins: pinmux_usb3h_overcurrent {
+ pinctrl-single,pins = <
+ 0x24c MODE_NITRO /* usb3h_overcurrent */
+ 0x250 MODE_NITRO /* usb3h_vbus_ppc */
+ >;
+ };
+ };
diff --git a/dts/src/arm64/broadcom/stingray/stingray.dtsi b/dts/src/arm64/broadcom/stingray/stingray.dtsi
new file mode 100644
index 0000000000..49933cf16c
--- /dev/null
+++ b/dts/src/arm64/broadcom/stingray/stingray.dtsi
@@ -0,0 +1,460 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,stingray";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x301>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
+ CLUSTER0_L2: l2-cache@000 {
+ compatible = "cache";
+ };
+
+ CLUSTER1_L2: l2-cache@100 {
+ compatible = "cache";
+ };
+
+ CLUSTER2_L2: l2-cache@200 {
+ compatible = "cache";
+ };
+
+ CLUSTER3_L2: l2-cache@300 {
+ compatible = "cache";
+ };
+ };
+
+ memory: memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ scr {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x61000000 0x05000000>;
+
+ gic: interrupt-controller@02c00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ reg = <0x02c00000 0x010000>, /* GICD */
+ <0x02e00000 0x600000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: gic-its@63c20000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x02c20000 0x10000>;
+ };
+ };
+
+ smmu: mmu@03000000 {
+ compatible = "arm,mmu-500";
+ reg = <0x03000000 0x80000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <2>;
+ };
+ };
+
+ crmu: crmu {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x66400000 0x100000>;
+
+ #include "stingray-clock.dtsi"
+
+ gpio_crmu: gpio@00024800 {
+ compatible = "brcm,iproc-gpio";
+ reg = <0x00024800 0x4c>;
+ ngpios = <6>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ hsls {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x68900000 0x17700000>;
+
+ #include "stingray-pinctrl.dtsi"
+
+ pwm: pwm@00010000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x00010000 0x1000>;
+ clocks = <&crmu_ref25m>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@000b0000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x000b0000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@000c0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x000c0000 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
+ clock-names = "wdogclk", "apb_pclk";
+ };
+
+ gpio_hsls: gpio@000d0000 {
+ compatible = "brcm,iproc-gpio";
+ reg = <0x000d0000 0x864>;
+ ngpios = <151>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinmux 0 0 16>,
+ <&pinmux 16 71 2>,
+ <&pinmux 18 131 8>,
+ <&pinmux 26 83 6>,
+ <&pinmux 32 123 4>,
+ <&pinmux 36 43 24>,
+ <&pinmux 60 89 2>,
+ <&pinmux 62 73 4>,
+ <&pinmux 66 95 28>,
+ <&pinmux 94 127 4>,
+ <&pinmux 98 139 10>,
+ <&pinmux 108 16 27>,
+ <&pinmux 135 77 6>,
+ <&pinmux 141 67 4>,
+ <&pinmux 145 149 6>,
+ <&pinmux 151 91 4>;
+ };
+
+ i2c1: i2c@000e0000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x000e0000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ uart0: uart@00100000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00100000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: uart@00110000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00110000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: uart@00120000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00120000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: uart@00130000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00130000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ssp0: ssp@00180000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x00180000 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
+ clock-names = "spiclk", "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp1: ssp@00190000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x00190000 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
+ clock-names = "spiclk", "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ hwrng: hwrng@00220000 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x00220000 0x28>;
+ };
+
+ dma0: dma@00310000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x00310000 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&hsls_div2_clk>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu 0x6000 0x0000>;
+ };
+
+ nand: nand@00360000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
+ reg = <0x00360000 0x600>,
+ <0x0050a408 0x600>,
+ <0x00360f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcm,nand-has-wp;
+ status = "disabled";
+ };
+
+ sdio0: sdhci@003f1000 {
+ compatible = "brcm,sdhci-iproc";
+ reg = <0x003f1000 0x100>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ clocks = <&sdio0_clk>;
+ iommus = <&smmu 0x6002 0x0000>;
+ status = "disabled";
+ };
+
+ sdio1: sdhci@003f2000 {
+ compatible = "brcm,sdhci-iproc";
+ reg = <0x003f2000 0x100>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ clocks = <&sdio1_clk>;
+ iommus = <&smmu 0x6003 0x0000>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/src/arm64/exynos/exynos5433-tm2.dts b/dts/src/arm64/exynos/exynos5433-tm2.dts
index 3ff95277a8..23191eb939 100644
--- a/dts/src/arm64/exynos/exynos5433-tm2.dts
+++ b/dts/src/arm64/exynos/exynos5433-tm2.dts
@@ -60,7 +60,6 @@
vci-supply = <&ldo28_reg>;
reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
- te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/dts/src/arm64/freescale/fsl-ls1012a-frdm.dts b/dts/src/arm64/freescale/fsl-ls1012a-frdm.dts
index 17fae8112e..7286b1ebfd 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a-frdm.dts
+++ b/dts/src/arm64/freescale/fsl-ls1012a-frdm.dts
@@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A Freedom Board.
*
- * Copyright 2016, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
diff --git a/dts/src/arm64/freescale/fsl-ls1012a-qds.dts b/dts/src/arm64/freescale/fsl-ls1012a-qds.dts
index e2a93d53d3..8c013b54db 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1012a-qds.dts
@@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A QDS Board.
*
- * Copyright 2016, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@@ -97,6 +97,14 @@
status = "okay";
};
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/dts/src/arm64/freescale/fsl-ls1012a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1012a-rdb.dts
index ed77f6b093..c1a119effa 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1012a-rdb.dts
@@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A RDB Board.
*
- * Copyright 2016, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@@ -54,6 +54,19 @@
status = "okay";
};
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
index b497ac196c..b1554cbd2c 100644
--- a/dts/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
*
- * Copyright 2016, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@@ -76,10 +76,17 @@
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ clock-frequency = <125000000>;
clock-output-names = "sysclk";
};
+ coreclk: coreclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "coreclk";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
@@ -117,12 +124,37 @@
#size-cells = <2>;
ranges;
+ esdhc0: esdhc@1560000 {
+ compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ clocks = <&clockgen 4 0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
scfg: scfg@1570000 {
compatible = "fsl,ls1012a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
};
+ esdhc1: esdhc@1580000 {
+ compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1580000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clocks = <&clockgen 4 0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ broken-cd;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
@@ -223,7 +255,8 @@
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
- clocks = <&sysclk>;
+ clocks = <&sysclk &coreclk>;
+ clock-names = "sysclk", "coreclk";
};
tmu: tmu@1f00000 {
diff --git a/dts/src/arm64/freescale/fsl-ls1043-post.dtsi b/dts/src/arm64/freescale/fsl-ls1043-post.dtsi
new file mode 100644
index 0000000000..169e171407
--- /dev/null
+++ b/dts/src/arm64/freescale/fsl-ls1043-post.dtsi
@@ -0,0 +1,45 @@
+/*
+ * QorIQ FMan v3 device tree nodes for ls1043
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+
+};
+
+&fman0 {
+ /* these aliases provide the FMan ports mapping */
+ enet0: ethernet@e0000 {
+ };
+
+ enet1: ethernet@e2000 {
+ };
+
+ enet2: ethernet@e4000 {
+ };
+
+ enet3: ethernet@e6000 {
+ };
+
+ enet4: ethernet@e8000 {
+ };
+
+ enet5: ethernet@ea000 {
+ };
+
+ enet6: ethernet@f0000 {
+ };
+};
diff --git a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
index 0989d635b5..6341281485 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1043a-qds.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
- * Copyright 2014-2015, Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@@ -181,3 +181,5 @@
reg = <0>;
};
};
+
+#include "fsl-ls1043-post.dtsi"
diff --git a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
index c37110bc15..3dc0c8e966 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
- * Copyright 2014-2015, Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@@ -75,11 +75,11 @@
reg = <0x4c>;
};
eeprom@52 {
- compatible = "at24,24c512";
+ compatible = "atmel,24c512";
reg = <0x52>;
};
eeprom@53 {
- compatible = "at24,24c512";
+ compatible = "atmel,24c512";
reg = <0x53>;
};
rtc@68 {
@@ -139,3 +139,76 @@
&duart1 {
status = "okay";
};
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy1>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii_phy2>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-txid";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-txid";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&qsgmii_phy3>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii_phy4>;
+ phy-connection-type = "qsgmii";
+ };
+
+ ethernet@f0000 { /* 10GEC1 */
+ phy-handle = <&aqr105_phy>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio@fc000 {
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ qsgmii_phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ qsgmii_phy2: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ qsgmii_phy3: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ qsgmii_phy4: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+ };
+
+ mdio@fd000 {
+ aqr105_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 132 4>;
+ reg = <0x1>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
index 45cface08c..31fd77f82c 100644
--- a/dts/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
- * Copyright 2014-2015, Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@@ -45,6 +45,7 @@
*/
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1043a";
@@ -52,6 +53,17 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ fman0 = &fman0;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ ethernet6 = &enet6;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -106,6 +118,33 @@
/* DRAM space 1, size: 2GiB DRAM */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ compatible = "shared-dma-pool";
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ no-map;
+ };
+
+ qman_fqd: qman-fqd {
+ compatible = "shared-dma-pool";
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ no-map;
+ };
+
+ qman_pfdr: qman-pfdr {
+ compatible = "shared-dma-pool";
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ no-map;
+ };
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -152,7 +191,7 @@
interrupts = <1 9 0xf08>;
};
- soc {
+ soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -223,6 +262,7 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
+ big-endian;
interrupts = <0 43 0x4>;
};
@@ -333,6 +373,28 @@
};
};
+ qman: qman@1880000 {
+ compatible = "fsl,qman";
+ reg = <0x0 0x1880000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+ };
+
+ bman: bman@1890000 {
+ compatible = "fsl,bman";
+ reg = <0x0 0x1890000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&bman_fbpr>;
+ };
+
+ bportals: bman-portals@508000000 {
+ ranges = <0x0 0x5 0x08000000 0x8000000>;
+ };
+
+ qportals: qman-portals@500000000 {
+ ranges = <0x0 0x5 0x00000000 0x8000000>;
+ };
+
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -688,3 +750,6 @@
};
};
+
+#include "qoriq-qman-portals.dtsi"
+#include "qoriq-bman-portals.dtsi"
diff --git a/dts/src/arm64/freescale/fsl-ls1046-post.dtsi b/dts/src/arm64/freescale/fsl-ls1046-post.dtsi
new file mode 100644
index 0000000000..f5017dba0f
--- /dev/null
+++ b/dts/src/arm64/freescale/fsl-ls1046-post.dtsi
@@ -0,0 +1,48 @@
+/*
+ * QorIQ FMan v3 device tree nodes for ls1046
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+#include "qoriq-fman3-0-10g-1.dtsi"
+};
+
+&fman0 {
+ /* these aliases provide the FMan ports mapping */
+ enet0: ethernet@e0000 {
+ };
+
+ enet1: ethernet@e2000 {
+ };
+
+ enet2: ethernet@e4000 {
+ };
+
+ enet3: ethernet@e6000 {
+ };
+
+ enet4: ethernet@e8000 {
+ };
+
+ enet5: ethernet@ea000 {
+ };
+
+ enet6: ethernet@f0000 {
+ };
+
+ enet7: ethernet@f2000 {
+ };
+};
diff --git a/dts/src/arm64/freescale/fsl-ls1046a-qds.dts b/dts/src/arm64/freescale/fsl-ls1046a-qds.dts
index 290e5b0144..434383bade 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1046a-qds.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
- * Copyright 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*
@@ -210,3 +210,5 @@
reg = <0>;
};
};
+
+#include "fsl-ls1046-post.dtsi"
diff --git a/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts
index d1ccc000d0..5dc2782e2a 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
- * Copyright 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
@@ -72,6 +72,14 @@
status = "okay";
};
+&esdhc {
+ mmc-hs200-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+};
+
&i2c0 {
status = "okay";
@@ -148,3 +156,63 @@
reg = <1>;
};
};
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* 10GEC1 */
+ phy-handle = <&aqr106_phy>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* 10GEC2 */
+ fixed-link = <0 1 1000 0 0>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio@fc000 {
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sgmii_phy1: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ sgmii_phy2: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+
+ mdio@fd000 {
+ aqr106_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 131 4>;
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
index f4b8b7edaf..dc1640be03 100644
--- a/dts/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
- * Copyright 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
@@ -55,6 +55,15 @@
aliases {
crypto = &crypto;
+ fman0 = &fman0;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ ethernet6 = &enet6;
+ ethernet7 = &enet7;
};
cpus {
@@ -174,7 +183,7 @@
IRQ_TYPE_LEVEL_LOW)>;
};
- soc {
+ soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -190,6 +199,7 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
+ big-endian;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -209,10 +219,10 @@
};
esdhc: esdhc@1560000 {
- compatible = "fsl,esdhc";
+ compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <0>;
+ clocks = <&clockgen 2 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
big-endian;
@@ -268,6 +278,30 @@
};
};
+ qman: qman@1880000 {
+ compatible = "fsl,qman";
+ reg = <0x0 0x1880000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+
+ };
+
+ bman: bman@1890000 {
+ compatible = "fsl,bman";
+ reg = <0x0 0x1890000 0x0 0x10000>;
+ interrupts = <0 45 0x4>;
+ memory-region = <&bman_fbpr>;
+
+ };
+
+ qportals: qman-portals@500000000 {
+ ranges = <0x0 0x5 0x00000000 0x8000000>;
+ };
+
+ bportals: bman-portals@508000000 {
+ ranges = <0x0 0x5 0x08000000 0x8000000>;
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
@@ -567,6 +601,7 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
};
usb1: usb@3000000 {
@@ -575,6 +610,7 @@
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
};
usb2: usb@3100000 {
@@ -583,6 +619,7 @@
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
};
sata: sata@3200000 {
@@ -594,4 +631,34 @@
clocks = <&clockgen 4 1>;
};
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ compatible = "shared-dma-pool";
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ no-map;
+ };
+
+ qman_fqd: qman-fqd {
+ compatible = "shared-dma-pool";
+ size = <0 0x800000>;
+ alignment = <0 0x800000>;
+ no-map;
+ };
+
+ qman_pfdr: qman-pfdr {
+ compatible = "shared-dma-pool";
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ no-map;
+ };
+ };
};
+
+#include "qoriq-qman-portals.dtsi"
+#include "qoriq-bman-portals.dtsi"
diff --git a/dts/src/arm64/freescale/fsl-ls1088a-qds.dts b/dts/src/arm64/freescale/fsl-ls1088a-qds.dts
index 8c3cae530f..30128051d0 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls1088a-qds.dts
@@ -110,6 +110,30 @@
};
};
+&ifc {
+ ranges = <0 0 0x5 0x80000000 0x08000000
+ 2 0 0x5 0x30000000 0x00010000
+ 3 0 0x5 0x20000000 0x00010000>;
+ status = "okay";
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0x0 0x0000100>;
+ };
+};
+
&duart0 {
status = "okay";
};
@@ -118,6 +142,10 @@
status = "okay";
};
+&esdhc {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
index 8a04fbb25c..213abb72de 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls1088a-rdb.dts
@@ -94,6 +94,22 @@
};
};
+&ifc {
+ ranges = <0 0 0x5 0x30000000 0x00010000
+ 2 0 0x5 0x20000000 0x00010000>;
+ status = "okay";
+
+ nand@0,0 {
+ compatible = "fsl,ifc-nand";
+ reg = <0x0 0x0 0x10000>;
+ };
+
+ fpga: board-control@2,0 {
+ compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
&duart0 {
status = "okay";
};
@@ -102,6 +118,10 @@
status = "okay";
};
+&esdhc {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
index 2946fd7971..c144d06a6e 100644
--- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -44,6 +44,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1088a";
@@ -61,6 +62,7 @@
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen 1 0>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -89,6 +91,7 @@
compatible = "arm,cortex-a53";
reg = <0x100>;
clocks = <&clockgen 1 1>;
+ #cooling-cells = <2>;
};
cpu5: cpu@101 {
@@ -153,6 +156,91 @@
clocks = <&sysclk>;
};
+ tmu: tmu@1f80000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f80000 0x0 0x10000>;
+ interrupts = <0 23 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1 */
+ <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+ /* Calibration data group 2 */
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+ /* Calibration data group 3 */
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+ /* Calibration data group 4 */
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ little-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu4 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
@@ -216,10 +304,6 @@
little-endian;
#address-cells = <2>;
#size-cells = <1>;
-
- ranges = <0 0 0x5 0x80000000 0x08000000
- 2 0 0x5 0x30000000 0x00010000
- 3 0 0x5 0x20000000 0x00010000>;
status = "disabled";
};
@@ -263,11 +347,26 @@
status = "disabled";
};
+ esdhc: esdhc@2140000 {
+ compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
sata: sata@3200000 {
- compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ compatible = "fsl,ls1088a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
+ dma-coherent;
status = "disabled";
};
};
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
index c1e76dfca4..ed209cd572 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-qds.dts
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080a QDS Board.
*
- * Copyright (C) 2015-17, Freescale Semiconductor
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
index 18ad195873..67ec3f9c81 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-rdb.dts
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080a RDB Board.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
diff --git a/dts/src/arm64/freescale/fsl-ls2080a-simu.dts b/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
index 290604b0a6..3ee718f0aa 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
+++ b/dts/src/arm64/freescale/fsl-ls2080a-simu.dts
@@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS2080a software Simulator model
*
- * Copyright (C) 2014-2015, Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
diff --git a/dts/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
index 46a26c0214..d789c6814e 100644
--- a/dts/src/arm64/freescale/fsl-ls2080a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2080a.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
- * Copyright (C) 2014-2016, Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
diff --git a/dts/src/arm64/freescale/fsl-ls2088a-qds.dts b/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
index ebcd6ee4da..4a1df5ce32 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
+++ b/dts/src/arm64/freescale/fsl-ls2088a-qds.dts
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2088A QDS Board.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
diff --git a/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts b/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
index 5992dc130f..a76d4b4deb 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
+++ b/dts/src/arm64/freescale/fsl-ls2088a-rdb.dts
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2088A RDB Board.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
diff --git a/dts/src/arm64/freescale/fsl-ls2088a.dtsi b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
index 33ce404cf7..5c695c6580 100644
--- a/dts/src/arm64/freescale/fsl-ls2088a.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls2088a.dtsi
@@ -1,7 +1,8 @@
/*
* Device Tree Include file for Freescale Layerscape-2088A family SoC.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
diff --git a/dts/src/arm64/freescale/fsl-ls208xa-qds.dtsi b/dts/src/arm64/freescale/fsl-ls208xa-qds.dtsi
index 8b62048459..b2374469a8 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa-qds.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa-qds.dtsi
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080A QDS Board.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@@ -45,6 +46,7 @@
*/
&esdhc {
+ mmc-hs200-1_8v;
status = "okay";
};
diff --git a/dts/src/arm64/freescale/fsl-ls208xa-rdb.dtsi b/dts/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
index 3737587ffb..9a1d0d2ab1 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
@@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080A RDB Board.
*
- * Copyright (C) 2016-17, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
diff --git a/dts/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
index abb2fff7d1..94cdd30450 100644
--- a/dts/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -1,7 +1,8 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
- * Copyright (C) 2016-2017, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@@ -471,7 +472,7 @@
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
- clock-frequency = <0>; /* Updated by bootloader */
+ clocks = <&clockgen 4 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
diff --git a/dts/src/arm64/freescale/qoriq-bman-portals.dtsi b/dts/src/arm64/freescale/qoriq-bman-portals.dtsi
new file mode 100644
index 0000000000..c3c2be4f50
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-bman-portals.dtsi
@@ -0,0 +1,71 @@
+/*
+ * QorIQ BMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&bportals {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+
+ bman-portal@0 {
+ /*
+ * bootloader fix-ups are expected to provide the
+ * "fsl,bman-portal-<hardware revision>" compatible
+ */
+ compatible = "fsl,bman-portal";
+ reg = <0x0 0x4000>, <0x4000000 0x4000>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@10000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x10000 0x4000>, <0x4010000 0x4000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@20000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x20000 0x4000>, <0x4020000 0x4000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@30000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x30000 0x4000>, <0x4030000 0x4000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@40000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x40000 0x4000>, <0x4040000 0x4000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@50000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x50000 0x4000>, <0x4050000 0x4000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@60000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x60000 0x4000>, <0x4060000 0x4000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@70000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x70000 0x4000>, <0x4070000 0x4000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ bman-portal@80000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x80000 0x4000>, <0x4080000 0x4000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi
new file mode 100644
index 0000000000..ecdffe731b
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi
@@ -0,0 +1,42 @@
+/*
+ * QorIQ FMan v3 10g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x10: port@90000 {
+ cell-index = <0x10>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x90000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x30: port@b0000 {
+ cell-index = <0x30>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ ethernet@f0000 {
+ cell-index = <0x8>;
+ compatible = "fsl,fman-memac";
+ reg = <0xf0000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
+ pcsphy-handle = <&pcsphy6>;
+ };
+
+ mdio@f1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+
+ pcsphy6: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi
new file mode 100644
index 0000000000..a7f6af56b6
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi
@@ -0,0 +1,42 @@
+/*
+ * QorIQ FMan v3 10g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x11: port@91000 {
+ cell-index = <0x11>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x91000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ fman0_tx_0x31: port@b1000 {
+ cell-index = <0x31>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xb1000 0x1000>;
+ fsl,fman-10g-port;
+ };
+
+ ethernet@f2000 {
+ cell-index = <0x9>;
+ compatible = "fsl,fman-memac";
+ reg = <0xf2000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
+ pcsphy-handle = <&pcsphy7>;
+ };
+
+ mdio@f3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xf3000 0x1000>;
+
+ pcsphy7: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi
new file mode 100644
index 0000000000..d600786719
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #0 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x08: port@88000 {
+ cell-index = <0x8>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman0_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+ ethernet@e0000 {
+ cell-index = <0>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe0000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy0>;
+ };
+
+ mdio@e1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xe1000 0x1000>;
+
+ pcsphy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi
new file mode 100644
index 0000000000..3c0b76d430
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #1 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x09: port@89000 {
+ cell-index = <0x9>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x89000 0x1000>;
+ };
+
+ fman0_tx_0x29: port@a9000 {
+ cell-index = <0x29>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xa9000 0x1000>;
+ };
+
+ ethernet@e2000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe2000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy1>;
+ };
+
+ mdio@e3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xe3000 0x1000>;
+
+ pcsphy1: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi
new file mode 100644
index 0000000000..89633afca2
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #2 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x0a: port@8a000 {
+ cell-index = <0xa>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x8a000 0x1000>;
+ };
+
+ fman0_tx_0x2a: port@aa000 {
+ cell-index = <0x2a>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xaa000 0x1000>;
+ };
+
+ ethernet@e4000 {
+ cell-index = <2>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe4000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy2>;
+ };
+
+ mdio@e5000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xe5000 0x1000>;
+
+ pcsphy2: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi
new file mode 100644
index 0000000000..87c2b705b1
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x0b: port@8b000 {
+ cell-index = <0xb>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x8b000 0x1000>;
+ };
+
+ fman0_tx_0x2b: port@ab000 {
+ cell-index = <0x2b>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xab000 0x1000>;
+ };
+
+ ethernet@e6000 {
+ cell-index = <3>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe6000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy3>;
+ };
+
+ mdio@e7000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xe7000 0x1000>;
+
+ pcsphy3: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi
new file mode 100644
index 0000000000..8f4d74b96b
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #4 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x0c: port@8c000 {
+ cell-index = <0xc>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x8c000 0x1000>;
+ };
+
+ fman0_tx_0x2c: port@ac000 {
+ cell-index = <0x2c>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xac000 0x1000>;
+ };
+
+ ethernet@e8000 {
+ cell-index = <4>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe8000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy4>;
+ };
+
+ mdio@e9000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xe9000 0x1000>;
+
+ pcsphy4: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi
new file mode 100644
index 0000000000..d534f770f7
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ FMan v3 1g port #5 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+ fman0_rx_0x0d: port@8d000 {
+ cell-index = <0xd>;
+ compatible = "fsl,fman-v3-port-rx";
+ reg = <0x8d000 0x1000>;
+ };
+
+ fman0_tx_0x2d: port@ad000 {
+ cell-index = <0x2d>;
+ compatible = "fsl,fman-v3-port-tx";
+ reg = <0xad000 0x1000>;
+ };
+
+ ethernet@ea000 {
+ cell-index = <5>;
+ compatible = "fsl,fman-memac";
+ reg = <0xea000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy5>;
+ };
+
+ mdio@eb000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xeb000 0x1000>;
+
+ pcsphy5: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-fman3-0.dtsi b/dts/src/arm64/freescale/qoriq-fman3-0.dtsi
new file mode 100644
index 0000000000..4dd06767f8
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-fman3-0.dtsi
@@ -0,0 +1,81 @@
+/*
+ * QorIQ FMan v3 device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman0: fman@1a00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ compatible = "fsl,fman";
+ ranges = <0x0 0x0 0x1a00000 0x100000>;
+ reg = <0x0 0x1a00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 3 0>;
+ clock-names = "fmanclk";
+ fsl,qman-channel-range = <0x800 0x10>;
+
+ muram@0 {
+ compatible = "fsl,fman-muram";
+ reg = <0x0 0x60000>;
+ };
+
+ fman0_oh_0x2: port@82000 {
+ cell-index = <0x2>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x82000 0x1000>;
+ };
+
+ fman0_oh_0x3: port@83000 {
+ cell-index = <0x3>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x83000 0x1000>;
+ };
+
+ fman0_oh_0x4: port@84000 {
+ cell-index = <0x4>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x84000 0x1000>;
+ };
+
+ fman0_oh_0x5: port@85000 {
+ cell-index = <0x5>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x85000 0x1000>;
+ };
+
+ fman0_oh_0x6: port@86000 {
+ cell-index = <0x6>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x86000 0x1000>;
+ };
+
+ fman0_oh_0x7: port@87000 {
+ cell-index = <0x7>;
+ compatible = "fsl,fman-v3-port-oh";
+ reg = <0x87000 0x1000>;
+ };
+
+ mdio0: mdio@fc000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xfc000 0x1000>;
+ };
+
+ xmdio0: mdio@fd000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ reg = <0xfd000 0x1000>;
+ };
+
+ ptp_timer0: ptp-timer@fe000 {
+ compatible = "fsl,fman-ptp-timer";
+ reg = <0xfe000 0x1000>;
+ };
+};
diff --git a/dts/src/arm64/freescale/qoriq-qman-portals.dtsi b/dts/src/arm64/freescale/qoriq-qman-portals.dtsi
new file mode 100644
index 0000000000..2a9aa060ef
--- /dev/null
+++ b/dts/src/arm64/freescale/qoriq-qman-portals.dtsi
@@ -0,0 +1,80 @@
+/*
+ * QorIQ QMan Portals device tree
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&qportals {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+
+ qportal0: qman-portal@0 {
+ /*
+ * bootloader fix-ups are expected to provide the
+ * "fsl,bman-portal-<hardware revision>" compatible
+ */
+ compatible = "fsl,qman-portal";
+ reg = <0x0 0x4000>, <0x4000000 0x4000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <0>;
+ };
+
+ qportal1: qman-portal@10000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x10000 0x4000>, <0x4010000 0x4000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <1>;
+ };
+
+ qportal2: qman-portal@20000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x20000 0x4000>, <0x4020000 0x4000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <2>;
+ };
+
+ qportal3: qman-portal@30000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x30000 0x4000>, <0x4030000 0x4000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <3>;
+ };
+
+ qportal4: qman-portal@40000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x40000 0x4000>, <0x4040000 0x4000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <4>;
+ };
+
+ qportal5: qman-portal@50000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x50000 0x4000>, <0x4050000 0x4000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <5>;
+ };
+
+ qportal6: qman-portal@60000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x60000 0x4000>, <0x4060000 0x4000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <6>;
+ };
+
+ qportal7: qman-portal@70000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x70000 0x4000>, <0x4070000 0x4000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <7>;
+ };
+
+ qportal8: qman-portal@80000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x80000 0x4000>, <0x4080000 0x4000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <8>;
+ };
+};
diff --git a/dts/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
index 186251ffc6..6609b0fe7a 100644
--- a/dts/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/dts/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -9,17 +9,28 @@
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "HiKey960";
- compatible = "hisilicon,hi3660";
+ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases {
- serial5 = &uart5; /* console UART */
+ mshc1 = &dwmmc1;
+ mshc2 = &dwmmc2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
};
chosen {
- stdout-path = "serial5:115200n8";
+ stdout-path = "serial6:115200n8";
};
memory@0 {
@@ -27,8 +38,206 @@
/* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>;
};
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
+
+ power {
+ wakeup-source;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led1 {
+ label = "user_led1";
+ /* gpio_150_user_led1 */
+ gpios = <&gpio18 6 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "user_led2";
+ /* gpio_151_user_led2 */
+ gpios = <&gpio18 7 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led3 {
+ label = "user_led3";
+ /* gpio_189_user_led3 */
+ gpios = <&gpio23 5 0>;
+ default-state = "off";
+ };
+
+ user_led4 {
+ label = "user_led4";
+ /* gpio_190_user_led4 */
+ gpios = <&gpio23 6 0>;
+ linux,default-trigger = "cpu0";
+ };
+
+ wlan_active_led {
+ label = "wifi_active";
+ /* gpio_205_wifi_active */
+ gpios = <&gpio25 5 0>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "bt_active";
+ gpios = <&gpio25 7 0>;
+ /* gpio_207_user_led1 */
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+
+ pmic: pmic@fff34000 {
+ compatible = "hisilicon,hi6421v530-pmic";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ ldo3: LDO3 { /* HDMI */
+ regulator-name = "VOUT3_1V85";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo9: LDO9 { /* SDCARD I/O */
+ regulator-name = "VOUT9_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo11: LDO11 { /* Low Speed Connector */
+ regulator-name = "VOUT11_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo15: LDO15 { /* UFS VCC */
+ regulator-name = "VOUT15_3V0";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo16: LDO16 { /* SD VDD */
+ regulator-name = "VOUT16_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <360>;
+ };
+ };
+ };
+
+ wlan_en: wlan-en-1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ /* GPIO_051_WIFI_EN */
+ gpio = <&gpio6 3 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+};
+
+&i2c0 {
+ /* On Low speed expansion */
+ label = "LS-I2C0";
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ adv7533: adv7533@39 {
+ status = "ok";
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ };
+};
+
+&i2c7 {
+ /* On Low speed expansion */
+ label = "LS-I2C1";
+ status = "okay";
+};
+
+&uart3 {
+ /* On Low speed expansion */
+ label = "LS-UART0";
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1837-st";
+ enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
+ max-speed = <921600>;
+ };
};
-&uart5 {
+&uart6 {
+ /* On Low speed expansion */
+ label = "LS-UART1";
status = "okay";
};
+
+&spi2 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
+&spi3 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
+
+&dwmmc1 {
+ vmmc-supply = <&ldo16>;
+ vqmmc-supply = <&ldo9>;
+ status = "okay";
+};
+
+&dwmmc2 { /* WIFI */
+ broken-cd;
+ /* WL_EN */
+ vmmc-supply = <&wlan_en>;
+ ti,non-removable;
+ non-removable;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "ok";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>; /* sdio func num */
+ /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
+ interrupt-parent = <&gpio22>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index 3983086bd6..c6a1961e8d 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3660-clock.h>
/ {
compatible = "hisilicon,hi3660";
@@ -141,19 +142,710 @@
#size-cells = <2>;
ranges;
- fixed_uart5: fixed_19_2M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- clock-output-names = "fixed:uart5";
+ crg_ctrl: crg_ctrl@fff35000 {
+ compatible = "hisilicon,hi3660-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
};
- uart5: uart@fdf05000 {
+ crg_rst: crg_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <2>;
+ hisi,rst-syscon = <&crg_ctrl>;
+ };
+
+
+ pctrl: pctrl@e8a09000 {
+ compatible = "hisilicon,hi3660-pctrl", "syscon";
+ reg = <0x0 0xe8a09000 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ pmuctrl: crg_ctrl@fff34000 {
+ compatible = "hisilicon,hi3660-pmuctrl", "syscon";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sctrl: sctrl@fff0a000 {
+ compatible = "hisilicon,hi3660-sctrl", "syscon";
+ reg = <0x0 0xfff0a000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ #clock-cells = <1>;
+
+ };
+
+ iomcu_rst: reset {
+ compatible = "hisilicon,hi3660-reset";
+ hisi,rst-syscon = <&iomcu>;
+ #reset-cells = <2>;
+ };
+
+ dual_timer0: timer@fff14000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfff14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
+ i2c0: i2c@ffd71000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd71000 0x0 0x1000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
+ resets = <&iomcu_rst 0x20 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffd72000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd72000 0x0 0x1000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
+ resets = <&iomcu_rst 0x20 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fdf0c000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
+ resets = <&crg_rst 0x78 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@fdf0b000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
+ resets = <&crg_rst 0x60 14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
+ status = "disabled";
+ };
+
+ uart0: serial@fdf02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf02000 0x0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+ status = "disabled";
+ };
+
+ uart1: serial@fdf00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
+ <&crg_ctrl HI3660_CLK_GATE_UART1>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+ status = "disabled";
+ };
+
+ uart2: serial@fdf03000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf03000 0x0 0x1000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffd74000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xffd74000 0x0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "disabled";
+ };
+
+ uart4: serial@fdf01000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf01000 0x0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
+ <&crg_ctrl HI3660_CLK_GATE_UART4>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "disabled";
+ };
+
+ uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&fixed_uart5 &fixed_uart5>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
+ <&crg_ctrl HI3660_CLK_GATE_UART5>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
+ status = "disabled";
+ };
+
+ uart6: serial@fff32000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfff32000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_UART6>,
+ <&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
+ status = "disabled";
+ };
+
+ rtc0: rtc@fff04000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0Xfff04000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio0: gpio@e8a0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0b000 0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 0 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio1: gpio@e8a0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0c000 0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 7 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio2: gpio@e8a0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0d000 0 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 14 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio3: gpio@e8a0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0e000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 22 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio4: gpio@e8a0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0f000 0 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 30 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio5: gpio@e8a10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a10000 0 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 38 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio6: gpio@e8a11000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a11000 0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 46 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio7: gpio@e8a12000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a12000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 54 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio8: gpio@e8a13000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a13000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 62 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio9: gpio@e8a14000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a14000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 70 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio10: gpio@e8a15000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a15000 0 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 78 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio11: gpio@e8a16000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a16000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 86 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio12: gpio@e8a17000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a17000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio13: gpio@e8a18000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a18000 0 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 102 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio14: gpio@e8a19000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a19000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 110 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio15: gpio@e8a1a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1a000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 118 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio16: gpio@e8a1b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1b000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio17: gpio@e8a1c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1c000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio18: gpio@ff3b4000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b4000 0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio19: gpio@ff3b5000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b5000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 8 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio20: gpio@e8a1f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1f000 0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 0 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio21: gpio@e8a20000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a20000 0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&pmx3 0 0 6>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio22: gpio@fff0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0b000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO176 */
+ gpio-ranges = <&pmx4 2 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio23: gpio@fff0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0c000 0 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO184 */
+ gpio-ranges = <&pmx4 0 6 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio24: gpio@fff0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0d000 0 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO192 */
+ gpio-ranges = <&pmx4 0 13 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio25: gpio@fff0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0e000 0 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO200 */
+ gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio26: gpio@fff0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0f000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO208 */
+ gpio-ranges = <&pmx4 0 28 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio27: gpio@fff10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff10000 0 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO216 */
+ gpio-ranges = <&pmx4 0 36 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio28: gpio@fff1d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff1d000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ spi2: spi@ffd68000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xffd68000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio27 2 0>;
+ status = "disabled";
+ };
+
+ spi3: spi@ff3b3000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xff3b3000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio18 5 0>;
+ status = "disabled";
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
+
+ /* SD */
+ dwmmc1: dwmmc1@ff37f000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cd-inverted;
+ compatible = "hisilicon,hi3660-dw-mshc";
+ num-slots = <1>;
+ bus-width = <0x4>;
+ disable-wp;
+ cap-sd-highspeed;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ reg = <0x0 0xff37f000 0x0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
+ <&crg_ctrl HI3660_HCLK_GATE_SD>;
+ clock-names = "ciu", "biu";
+ clock-frequency = <3200000>;
+ resets = <&crg_rst 0x94 18>;
+ cd-gpios = <&gpio25 3 0>;
+ hisilicon,peripheral-syscon = <&sctrl>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pmx_func
+ &sd_clk_cfg_func
+ &sd_cfg_func>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "disabled";
+
+ slot@0 {
+ reg = <0x0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+ /* SDIO */
+ dwmmc2: dwmmc2@ff3ff000 {
+ compatible = "hisilicon,hi3660-dw-mshc";
+ reg = <0x0 0xff3ff000 0x0 0x1000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ num-slots = <1>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
+ <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
+ clock-names = "ciu", "biu";
+ resets = <&crg_rst 0x94 20>;
+ card-detect-delay = <200>;
+ supports-highspeed;
+ keep-power-in-suspend;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pmx_func
+ &sdio_clk_cfg_func
+ &sdio_cfg_func>;
status = "disabled";
};
};
diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts
index 49f6a6242c..2b526304ed 100644
--- a/dts/src/arm64/hisilicon/hi6220-hikey.dts
+++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts
@@ -141,6 +141,8 @@
bluetooth {
compatible = "ti,wl1835-st";
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ clocks = <&pmic>;
+ clock-names = "ext_clock";
};
};
@@ -466,6 +468,11 @@
method = "smc";
};
};
+
+ sound_card {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_port0>;
+ };
};
&uart2 {
@@ -506,10 +513,33 @@
interrupts = <1 2>;
pd-gpio = <&gpio0 4 0>;
adi,dsi-lanes = <4>;
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ adv7533_in: endpoint {
+ remote-endpoint = <&dsi_out0>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
+ };
+ };
+};
- port {
- adv7533_in: endpoint {
- remote-endpoint = <&dsi_out0>;
+&i2s0 {
+
+ ports {
+ i2s0_port0: port@0 {
+ i2s0_cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ dai-format = "i2s";
};
};
};
diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi
index 5013e4b2ea..eacbe0db5b 100644
--- a/dts/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/src/arm64/hisilicon/hi6220.dtsi
@@ -332,6 +332,19 @@
status = "disabled";
};
+ dma0: dma@f7370000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0x0 0xf7370000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ dma-requests = <32>;
+ interrupts = <0 84 4>;
+ clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
+ dma-no-cci;
+ dma-type = "hi6220_dma";
+ status = "ok";
+ };
+
dual_timer0: timer@f8008000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xf8008000 0x0 0x1000>;
@@ -805,6 +818,19 @@
#thermal-sensor-cells = <1>;
};
+ i2s0: i2s@f7118000{
+ compatible = "hisilicon,hi6210-i2s";
+ reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
+ clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
+ <&sys_ctrl HI6220_BBPPLL0_DIV>;
+ clock-names = "dacodec", "i2s-base";
+ dmas = <&dma0 15 &dma0 14>;
+ dma-names = "rx", "tx";
+ hisilicon,sysctrl-syscon = <&sys_ctrl>;
+ #sound-dai-cells = <1>;
+ };
+
thermal-zones {
cls0: cls0 {
@@ -887,5 +913,69 @@
};
};
};
+
+ debug@f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ debug@f6592000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6592000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ debug@f6594000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6594000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ debug@f6596000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6596000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
+ debug@f65d0000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d0000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ };
+
+ debug@f65d2000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d2000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ };
+
+ debug@f65d4000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d4000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ };
+
+ debug@f65d6000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d6000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ };
};
};
diff --git a/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi b/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
index 719c4bc937..7e542d28da 100644
--- a/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
+++ b/dts/src/arm64/hisilicon/hikey960-pinctrl.dtsi
@@ -24,6 +24,27 @@
&range 0 7 0
&range 8 116 0>;
+ pmu_pmx_func: pmu_pmx_func {
+ pinctrl-single,pins = <
+ 0x008 MUX_M1 /* PMU1_SSI */
+ 0x00c MUX_M1 /* PMU2_SSI */
+ 0x010 MUX_M1 /* PMU_CLKOUT */
+ 0x100 MUX_M1 /* PMU_HKADC_SSI */
+ >;
+ };
+
+ csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x044 MUX_M0 /* CSI0_PWD_N */
+ >;
+ };
+
+ csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x04c MUX_M0 /* CSI1_PWD_N */
+ >;
+ };
+
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
@@ -40,6 +61,12 @@
>;
};
+ pwr_key_pmx_func: pwr_key_pmx_func {
+ pinctrl-single,pins = <
+ 0x080 MUX_M0 /* GPIO_034 */
+ >;
+ };
+
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */
@@ -67,21 +94,10 @@
>;
};
- spi1_pmx_func: spi1_pmx_func {
- pinctrl-single,pins = <
- 0x034 MUX_M1 /* SPI1_CLK */
- 0x038 MUX_M1 /* SPI1_DI */
- 0x03c MUX_M1 /* SPI1_DO */
- 0x040 MUX_M1 /* SPI1_CS_N */
- >;
- };
-
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */
- 0x0d4 MUX_M2 /* UART0_RXD_M */
- 0x0d8 MUX_M2 /* UART0_TXD_M */
>;
};
@@ -138,6 +154,18 @@
0x0d8 MUX_M1 /* UART6_TXD */
>;
};
+
+ cam0_rst_pmx_func: cam0_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x0c8 MUX_M0 /* CAM0_RST */
+ >;
+ };
+
+ cam1_rst_pmx_func: cam1_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x124 MUX_M0 /* CAM1_RST */
+ >;
+ };
};
/* [IOMG_MMC0_000, IOMG_MMC0_005] */
@@ -174,6 +202,13 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
+ ufs_pmx_func: ufs_pmx_func {
+ pinctrl-single,pins = <
+ 0x000 MUX_M1 /* UFS_REF_CLK */
+ 0x004 MUX_M1 /* UFS_RST_N */
+ >;
+ };
+
spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */
@@ -248,17 +283,17 @@
>;
};
- i2c2_pmx_func: i2c2_pmx_func {
+ i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = <
- 0x024 MUX_M1 /* I2C2_SCL */
- 0x028 MUX_M1 /* I2C2_SDA */
+ 0x024 MUX_M3 /* I2C7_SCL */
+ 0x028 MUX_M3 /* I2C7_SDA */
>;
};
- i2c7_pmx_func: i2c7_pmx_func {
+ pcie_pmx_func: pcie_pmx_func {
pinctrl-single,pins = <
- 0x024 MUX_M3 /* I2C7_SCL */
- 0x028 MUX_M3 /* I2C7_SDA */
+ 0x084 MUX_M1 /* PCIE_CLKREQ_N */
+ 0x088 MUX_M1 /* PCIE_WAKE_N */
>;
};
@@ -271,15 +306,6 @@
>;
};
- spi4_pmx_func: spi4_pmx_func {
- pinctrl-single,pins = <
- 0x08c MUX_M4 /* SPI4_CLK */
- 0x090 MUX_M4 /* SPI4_DI */
- 0x094 MUX_M4 /* SPI4_DO */
- 0x098 MUX_M4 /* SPI4_CS0_N */
- >;
- };
-
i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
@@ -290,13 +316,433 @@
};
};
- pmx5: pinmux@ff3fd800 {
+ pmx5: pinmux@e896c800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xe896c800 0x0 0x200>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ pmu_cfg_func: pmu_cfg_func {
+ pinctrl-single,pins = <
+ 0x010 0x0 /* PMU1_SSI */
+ 0x014 0x0 /* PMU2_SSI */
+ 0x018 0x0 /* PMU_CLKOUT */
+ 0x10c 0x0 /* PMU_HKADC_SSI */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_06MA DRIVE6_MASK
+ >;
+ };
+
+ i2c3_cfg_func: i2c3_cfg_func {
+ pinctrl-single,pins = <
+ 0x038 0x0 /* I2C3_SCL */
+ 0x03c 0x0 /* I2C3_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* CSI0_PWD_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x058 0x0 /* CSI1_PWD_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ isp0_cfg_func: isp0_cfg_func {
+ pinctrl-single,pins = <
+ 0x064 0x0 /* ISP_CLK0 */
+ 0x070 0x0 /* ISP_SCL0 */
+ 0x074 0x0 /* ISP_SDA0 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK>;
+ };
+
+ isp1_cfg_func: isp1_cfg_func {
+ pinctrl-single,pins = <
+ 0x068 0x0 /* ISP_CLK1 */
+ 0x078 0x0 /* ISP_SCL1 */
+ 0x07c 0x0 /* ISP_SDA1 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ pwr_key_cfg_func: pwr_key_cfg_func {
+ pinctrl-single,pins = <
+ 0x08c 0x0 /* GPIO_034 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart1_cfg_func: uart1_cfg_func {
+ pinctrl-single,pins = <
+ 0x0b4 0x0 /* UART1_RXD */
+ 0x0b8 0x0 /* UART1_TXD */
+ 0x0bc 0x0 /* UART1_CTS_N */
+ 0x0c0 0x0 /* UART1_RTS_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART2_CTS_N */
+ 0x0cc 0x0 /* UART2_RTS_N */
+ 0x0d0 0x0 /* UART2_TXD */
+ 0x0d4 0x0 /* UART2_RXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart5_cfg_func: uart5_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART5_RXD */
+ 0x0cc 0x0 /* UART5_TXD */
+ 0x0d0 0x0 /* UART5_CTS_N */
+ 0x0d4 0x0 /* UART5_RTS_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam0_rst_cfg_func: cam0_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d4 0x0 /* CAM0_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart0_cfg_func: uart0_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART0_RXD */
+ 0x0dc 0x0 /* UART0_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart6_cfg_func: uart6_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART6_CTS_N */
+ 0x0dc 0x0 /* UART6_RTS_N */
+ 0x0e0 0x0 /* UART6_RXD */
+ 0x0e4 0x0 /* UART6_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x0e8 0x0 /* UART3_CTS_N */
+ 0x0ec 0x0 /* UART3_RTS_N */
+ 0x0f0 0x0 /* UART3_RXD */
+ 0x0f4 0x0 /* UART3_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x0f8 0x0 /* UART4_CTS_N */
+ 0x0fc 0x0 /* UART4_RTS_N */
+ 0x100 0x0 /* UART4_RXD */
+ 0x104 0x0 /* UART4_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam1_rst_cfg_func: cam1_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x130 0x0 /* CAM1_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx6: pinmux@ff3b6800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff3b6800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ ufs_cfg_func: ufs_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* UFS_REF_CLK */
+ 0x004 0x0 /* UFS_RST_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_08MA DRIVE6_MASK
+ >;
+ };
+
+ spi3_cfg_func: spi3_cfg_func {
+ pinctrl-single,pins = <
+ 0x008 0x0 /* SPI3_CLK */
+ 0x0 /* SPI3_DI */
+ 0x010 0x0 /* SPI3_DO */
+ 0x014 0x0 /* SPI3_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx7: pinmux@ff3fd800 {
compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>;
#pinctrl-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-single,register-width = <32>;
+ pinctrl-single,register-width = <0x20>;
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
@@ -315,8 +761,7 @@
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_32MA
- DRIVE6_MASK
+ DRIVE6_32MA DRIVE6_MASK
>;
};
@@ -341,19 +786,16 @@
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_19MA
- DRIVE6_MASK
+ DRIVE6_19MA DRIVE6_MASK
>;
};
};
- pmx6: pinmux@ff37e800 {
+ pmx8: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x18>;
#pinctrl-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-single,register-width = <32>;
+ pinctrl-single,register-width = <0x20>;
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
@@ -403,5 +845,215 @@
>;
};
};
+
+ pmx9: pinmux@fff11800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xfff11800 0x0 0xbc>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ i2c0_cfg_func: i2c0_cfg_func {
+ pinctrl-single,pins = <
+ 0x01c 0x0 /* I2C0_SCL */
+ 0x020 0x0 /* I2C0_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c1_cfg_func: i2c1_cfg_func {
+ pinctrl-single,pins = <
+ 0x024 0x0 /* I2C1_SCL */
+ 0x028 0x0 /* I2C1_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c7_cfg_func: i2c7_cfg_func {
+ pinctrl-single,pins = <
+ 0x02c 0x0 /* I2C7_SCL */
+ 0x030 0x0 /* I2C7_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ slimbus_cfg_func: slimbus_cfg_func {
+ pinctrl-single,pins = <
+ 0x034 0x0 /* SLIMBUS_CLK */
+ 0x038 0x0 /* SLIMBUS_DATA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s0_cfg_func: i2s0_cfg_func {
+ pinctrl-single,pins = <
+ 0x040 0x0 /* I2S0_DI */
+ 0x044 0x0 /* I2S0_DO */
+ 0x048 0x0 /* I2S0_XCLK */
+ 0x04c 0x0 /* I2S0_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s2_cfg_func: i2s2_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* I2S2_DI */
+ 0x054 0x0 /* I2S2_DO */
+ 0x058 0x0 /* I2S2_XCLK */
+ 0x05c 0x0 /* I2S2_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ pcie_cfg_func: pcie_cfg_func {
+ pinctrl-single,pins = <
+ 0x094 0x0 /* PCIE_CLKREQ_N */
+ 0x098 0x0 /* PCIE_WAKE_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ spi2_cfg_func: spi2_cfg_func {
+ pinctrl-single,pins = <
+ 0x09c 0x0 /* SPI2_CLK */
+ 0x0a0 0x0 /* SPI2_DI */
+ 0x0a4 0x0 /* SPI2_DO */
+ 0x0a8 0x0 /* SPI2_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ usb_cfg_func: usb_cfg_func {
+ pinctrl-single,pins = <
+ 0x0ac 0x0 /* GPIO_219 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+ };
};
};
diff --git a/dts/src/arm64/marvell/armada-3720-db.dts b/dts/src/arm64/marvell/armada-3720-db.dts
index a89855f570..9df0f06ce6 100644
--- a/dts/src/arm64/marvell/armada-3720-db.dts
+++ b/dts/src/arm64/marvell/armada-3720-db.dts
@@ -42,6 +42,10 @@
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is compatible with the version 1.4 and the version 2.0 of
+ * the board, however the CON numbers are different between the 2
+ * version
*/
/dts-v1/;
@@ -76,6 +80,36 @@
compatible = "usb-nop-xceiv";
vcc-supply = <&exp_usb3_vbus>;
};
+
+ vcc_sd_reg1: regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+};
+
+/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
+&eth0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
+&eth1 {
+ phy-mode = "sgmii";
+ phy = <&phy1>;
+ status = "okay";
};
&i2c0 {
@@ -108,11 +142,46 @@
};
};
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
+&pcie0 {
+ status = "okay";
+};
+
/* CON3 */
&sata {
status = "okay";
};
+&sdhci0 {
+ non-removable;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,pad-type = "fixed-1-8v";
+ status = "okay";
+};
+
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+ wp-inverted;
+ cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vcc_sd_reg1>;
+ status = "okay";
+};
+
&spi0 {
status = "okay";
pinctrl-names = "default";
@@ -145,60 +214,23 @@
};
};
-/* Exported on the micro USB connector CON32 through an FTDI */
+/*
+ * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
+ * an FTDI
+ */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
-&sdhci0 {
- non-removable;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- marvell,pad-type = "fixed-1-8v";
+/* CON27(V2.0)/CON29(V1.4) */
+&usb2 {
status = "okay";
};
-/* CON31 */
+/* CON29(V2.0)/CON31(V1.4) */
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
};
-
-/* CON17 (PCIe) / CON12 (mini-PCIe) */
-&pcie0 {
- status = "okay";
-};
-
-/* CON27 */
-&usb2 {
- status = "okay";
-};
-
-
-&mdio {
- status = "okay";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-&eth0 {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
- phy = <&phy0>;
- status = "okay";
-};
-
-&eth1 {
- phy-mode = "sgmii";
- phy = <&phy1>;
- status = "okay";
-};
diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi
index 4d495ec392..dbcc3d4e2e 100644
--- a/dts/src/arm64/marvell/armada-37xx.dtsi
+++ b/dts/src/arm64/marvell/armada-37xx.dtsi
@@ -75,14 +75,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
@@ -163,7 +159,7 @@
pinctrl_nb: pinctrl@13800 {
compatible = "marvell,armada3710-nb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
gpionb: gpio {
#gpio-cells = <2>;
@@ -219,7 +215,7 @@
pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpio {
#gpio-cells = <2>;
@@ -281,8 +277,8 @@
xor@60900 {
compatible = "marvell,armada-3700-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
+ reg = <0x60900 0x100>,
+ <0x60b00 0x100>;
xor10 {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -292,11 +288,22 @@
};
};
+ sdhci1: sdhci@d0000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
- "marvell,sdhci-xenon";
- reg = <0xd8000 0x300
- 0x17808 0x4>;
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300>,
+ <0x17808 0x4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 0>;
clock-names = "core";
diff --git a/dts/src/arm64/marvell/armada-7020.dtsi b/dts/src/arm64/marvell/armada-7020.dtsi
index 975e733027..4ab012991d 100644
--- a/dts/src/arm64/marvell/armada-7020.dtsi
+++ b/dts/src/arm64/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7020";
diff --git a/dts/src/arm64/marvell/armada-7040-db.dts b/dts/src/arm64/marvell/armada-7040-db.dts
index 12442329b8..92c761c380 100644
--- a/dts/src/arm64/marvell/armada-7040-db.dts
+++ b/dts/src/arm64/marvell/armada-7040-db.dts
@@ -162,6 +162,8 @@
};
&cpm_mdio {
+ status = "okay";
+
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -185,7 +187,3 @@
phy = <&phy1>;
phy-mode = "rgmii-id";
};
-
-&cpm_crypto {
- status = "okay";
-};
diff --git a/dts/src/arm64/marvell/armada-7040.dtsi b/dts/src/arm64/marvell/armada-7040.dtsi
index 78d995d627..cbe460b8fc 100644
--- a/dts/src/arm64/marvell/armada-7040.dtsi
+++ b/dts/src/arm64/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7040";
diff --git a/dts/src/arm64/marvell/armada-70x0.dtsi b/dts/src/arm64/marvell/armada-70x0.dtsi
new file mode 100644
index 0000000000..860b6ae9dc
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-70x0.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+/ {
+ aliases {
+ gpio1 = &cpm_gpio1;
+ gpio2 = &cpm_gpio2;
+ };
+};
+
+&cpm_gpio1 {
+ status = "okay";
+};
+
+&cpm_gpio2 {
+ status = "okay";
+};
+
+&cpm_syscon0 {
+ cpm_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+ };
+};
diff --git a/dts/src/arm64/marvell/armada-8020.dtsi b/dts/src/arm64/marvell/armada-8020.dtsi
index 7c08f1f28d..0ba0bc9425 100644
--- a/dts/src/arm64/marvell/armada-8020.dtsi
+++ b/dts/src/arm64/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8020";
diff --git a/dts/src/arm64/marvell/armada-8040-db.dts b/dts/src/arm64/marvell/armada-8040-db.dts
index dc0d084005..1e8f7242ed 100644
--- a/dts/src/arm64/marvell/armada-8040-db.dts
+++ b/dts/src/arm64/marvell/armada-8040-db.dts
@@ -125,6 +125,8 @@
};
&cpm_mdio {
+ status = "okay";
+
phy1: ethernet-phy@1 {
reg = <1>;
};
@@ -140,10 +142,6 @@
phy-mode = "rgmii-id";
};
-&cpm_crypto {
- status = "okay";
-};
-
/* CON5 on CP1 expansion */
&cps_pcie2 {
status = "okay";
@@ -169,6 +167,24 @@
status = "okay";
};
+&cps_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cps_ethernet {
+ status = "okay";
+};
+
+&cps_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
diff --git a/dts/src/arm64/marvell/armada-8040-mcbin.dts b/dts/src/arm64/marvell/armada-8040-mcbin.dts
index f7bb0cc031..4968e731de 100644
--- a/dts/src/arm64/marvell/armada-8040-mcbin.dts
+++ b/dts/src/arm64/marvell/armada-8040-mcbin.dts
@@ -95,16 +95,47 @@
status = "okay";
};
+&ap_sdhci0 {
+ bus-width = <8>;
+ /*
+ * Not stable in HS modes - phy needs "more calibration", so add
+ * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
+ */
+ marvell,xenon-phy-slow-mode;
+ no-1-8-v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+ vqmmc-supply = <&v_vddo_h>;
+};
+
&cpm_i2c0 {
clock-frequency = <100000>;
status = "okay";
};
+&cpm_mdio {
+ status = "okay";
+
+ ge_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&cpm_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
};
+&cpm_sdhci0 {
+ /* U6 */
+ broken-cd;
+ bus-width = <4>;
+ status = "okay";
+ vqmmc-supply = <&v_3_3>;
+};
+
&cpm_usb3_0 {
/* J38? - USB2.0 only */
status = "okay";
@@ -115,6 +146,17 @@
status = "okay";
};
+&cps_ethernet {
+ status = "okay";
+};
+
+&cps_eth1 {
+ /* CPS Lane 0 - J5 (Gigabit RJ45) */
+ status = "okay";
+ phy = <&ge_phy>;
+ phy-mode = "sgmii";
+};
+
&cps_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
diff --git a/dts/src/arm64/marvell/armada-8040.dtsi b/dts/src/arm64/marvell/armada-8040.dtsi
index 33813a75bc..60fe84f5cb 100644
--- a/dts/src/arm64/marvell/armada-8040.dtsi
+++ b/dts/src/arm64/marvell/armada-8040.dtsi
@@ -46,8 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8040";
diff --git a/dts/src/arm64/marvell/armada-80x0.dtsi b/dts/src/arm64/marvell/armada-80x0.dtsi
new file mode 100644
index 0000000000..666ebe96ba
--- /dev/null
+++ b/dts/src/arm64/marvell/armada-80x0.dtsi
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 80x0 SoC family
+ */
+
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+ aliases {
+ gpio1 = &cps_gpio1;
+ gpio2 = &cpm_gpio2;
+ };
+};
+
+/* The 80x0 has two CP blocks, but uses only one block from each. */
+&cps_gpio1 {
+ status = "okay";
+};
+
+&cpm_gpio2 {
+ status = "okay";
+};
+
+&cpm_syscon0 {
+ cpm_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cpm-pinctrl";
+ };
+};
+
+&cps_syscon0 {
+ cps_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cps-pinctrl";
+ };
+};
diff --git a/dts/src/arm64/marvell/armada-ap806.dtsi b/dts/src/arm64/marvell/armada-ap806.dtsi
index fe41bf9c30..1eb1f1e9aa 100644
--- a/dts/src/arm64/marvell/armada-ap806.dtsi
+++ b/dts/src/arm64/marvell/armada-ap806.dtsi
@@ -57,6 +57,7 @@
aliases {
serial0 = &uart0;
serial1 = &uart1;
+ gpio0 = &ap_gpio;
};
psci {
@@ -146,6 +147,13 @@
marvell,spi-base = <128>, <136>, <144>, <152>;
};
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
@@ -159,6 +167,7 @@
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
dma-coherent;
};
@@ -167,6 +176,7 @@
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
dma-coherent;
};
@@ -175,6 +185,7 @@
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
dma-coherent;
};
@@ -183,6 +194,7 @@
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
dma-coherent;
};
@@ -193,7 +205,7 @@
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ap_syscon 3>;
+ clocks = <&ap_clk 3>;
status = "disabled";
};
@@ -204,7 +216,7 @@
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
- clocks = <&ap_syscon 3>;
+ clocks = <&ap_clk 3>;
status = "disabled";
};
@@ -214,7 +226,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
+ clocks = <&ap_clk 3>;
status = "disabled";
};
@@ -224,7 +236,7 @@
reg-shift = <2>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
+ clocks = <&ap_clk 3>;
status = "disabled";
};
@@ -234,21 +246,33 @@
reg = <0x6e0000 0x300>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
- clocks = <&ap_syscon 4>;
+ clocks = <&ap_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller",
- "syscon";
- #clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0",
- "ap-cpu-cluster-1",
- "ap-fixed", "ap-mss",
- "ap-emmc";
+ compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+ };
+
+ ap_gpio: gpio {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <19>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 19>;
+ };
};
};
};
diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi
index b4bc42ece7..726528ce54 100644
--- a/dts/src/arm64/marvell/armada-cp110-master.dtsi
+++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi
@@ -44,45 +44,46 @@
* Device Tree file for Marvell Armada CP110 Master.
*/
+#define ICU_GRP_NSR 0x0
+
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cpm_icu>;
ranges;
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
+ clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cpm_eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -94,41 +95,70 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
+ status = "disabled";
+ };
+
+ cpm_xmdio: mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ status = "disabled";
+ };
+
+ cpm_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
};
cpm_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cpm-apll", "cpm-ppv2-core", "cpm-eip",
- "cpm-core", "cpm-nand-core";
- gate-clock-output-names =
- "cpm-audio", "cpm-communit", "cpm-nand",
- "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
- "cpm-mg-core", "cpm-xor1", "cpm-xor0",
- "cpm-gop-dp", "none", "cpm-pcie_x10",
- "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
- "cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-sd-mmc-gop", "none", "none",
- "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
- "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
+
+ cpm_gpio1: gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ status = "disabled";
+
+ };
+
+ cpm_gpio2: gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cpm_pinctrl 0 32 31>;
+ status = "disabled";
+ };
};
cpm_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 15>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 15>;
status = "disabled";
};
@@ -137,8 +167,8 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 22>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 22>;
status = "disabled";
};
@@ -147,8 +177,8 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 23>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 23>;
status = "disabled";
};
@@ -158,7 +188,7 @@
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&cpm_syscon0 1 8>;
+ clocks = <&cpm_clk 1 8>;
};
cpm_xor1: xor@6c0000 {
@@ -167,7 +197,7 @@
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&cpm_syscon0 1 7>;
+ clocks = <&cpm_clk 1 7>;
};
cpm_spi0: spi@700600 {
@@ -176,7 +206,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
- clocks = <&cpm_syscon0 1 21>;
+ clocks = <&cpm_clk 1 21>;
status = "disabled";
};
@@ -186,7 +216,7 @@
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
- clocks = <&cpm_syscon0 1 21>;
+ clocks = <&cpm_clk 1 21>;
status = "disabled";
};
@@ -195,8 +225,8 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 21>;
status = "disabled";
};
@@ -205,25 +235,25 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 25>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_clk 1 25>;
status = "okay";
};
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
- clocks = <&cpm_syscon0 1 4>;
+ clocks = <&cpm_clk 1 4>;
dma-coherent;
status = "disabled";
};
@@ -231,16 +261,15 @@
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
- clocks = <&cpm_syscon0 1 26>;
- status = "disabled";
+ clocks = <&cpm_clk 1 26>;
};
};
@@ -263,10 +292,10 @@
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cpm_syscon0 1 13>;
+ clocks = <&cpm_clk 1 13>;
status = "disabled";
};
@@ -289,11 +318,11 @@
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cpm_syscon0 1 11>;
+ clocks = <&cpm_clk 1 11>;
status = "disabled";
};
@@ -316,11 +345,11 @@
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cpm_syscon0 1 12>;
+ clocks = <&cpm_clk 1 12>;
status = "disabled";
};
};
diff --git a/dts/src/arm64/marvell/armada-cp110-slave.dtsi b/dts/src/arm64/marvell/armada-cp110-slave.dtsi
index 6e2058847d..95f8e5f607 100644
--- a/dts/src/arm64/marvell/armada-cp110-slave.dtsi
+++ b/dts/src/arm64/marvell/armada-cp110-slave.dtsi
@@ -44,19 +44,20 @@
* Device Tree file for Marvell Armada CP110 Slave.
*/
+#define ICU_GRP_NSR 0x0
+
/ {
cp110-slave {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cps_icu>;
ranges;
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_rtc: rtc@284000 {
@@ -69,27 +70,27 @@
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
+ clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cps_eth0: eth0 {
- interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -101,34 +102,64 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
+ status = "disabled";
+ };
+
+ cps_xmdio: mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ status = "disabled";
+ };
+
+ cps_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
};
cps_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cps-apll", "cps-ppv2-core", "cps-eip",
- "cps-core", "cps-nand-core";
- gate-clock-output-names =
- "cps-audio", "cps-communit", "cps-nand",
- "cps-ppv2", "cps-sdio", "cps-mg-domain",
- "cps-mg-core", "cps-xor1", "cps-xor0",
- "cps-gop-dp", "none", "cps-pcie_x10",
- "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
- "cps-sata", "cps-sata-usb", "cps-main",
- "cps-sd-mmc-gop", "none", "none",
- "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
- "cps-usb3dev", "cps-eip150", "cps-eip197";
+
+ cps_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
+
+ cps_gpio1: gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cps_pinctrl 0 0 32>;
+ status = "disabled";
+
+ };
+
+ cps_gpio2: gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cps_pinctrl 0 32 31>;
+ status = "disabled";
+ };
+
};
cps_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 15>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 15>;
status = "disabled";
};
@@ -137,8 +168,8 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 22>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 22>;
status = "disabled";
};
@@ -147,8 +178,8 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 23>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 23>;
status = "disabled";
};
@@ -158,7 +189,7 @@
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 8>;
+ clocks = <&cps_clk 1 8>;
};
cps_xor1: xor@6c0000 {
@@ -167,7 +198,7 @@
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 7>;
+ clocks = <&cps_clk 1 7>;
};
cps_spi0: spi@700600 {
@@ -176,7 +207,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <3>;
- clocks = <&cps_syscon0 1 21>;
+ clocks = <&cps_clk 1 21>;
status = "disabled";
};
@@ -186,7 +217,7 @@
#address-cells = <1>;
#size-cells = <0>;
cell-index = <4>;
- clocks = <&cps_syscon0 1 21>;
+ clocks = <&cps_clk 1 21>;
status = "disabled";
};
@@ -195,8 +226,8 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 21>;
status = "disabled";
};
@@ -205,31 +236,38 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 25>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_clk 1 25>;
status = "okay";
};
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
- clocks = <&cps_syscon0 1 26>;
+ clocks = <&cps_clk 1 26>;
+ /*
+ * The cryptographic engine found on the cp110
+ * master is enabled by default at the SoC
+ * level. Because it is not possible as of now
+ * to enable two cryptographic engines in
+ * parallel, disable this one by default.
+ */
status = "disabled";
};
};
@@ -253,10 +291,10 @@
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cps_syscon0 1 13>;
+ clocks = <&cps_clk 1 13>;
status = "disabled";
};
@@ -279,11 +317,11 @@
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cps_syscon0 1 11>;
+ clocks = <&cps_clk 1 11>;
status = "disabled";
};
@@ -306,11 +344,11 @@
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&cps_syscon0 1 12>;
+ clocks = <&cps_clk 1 12>;
status = "disabled";
};
};
diff --git a/dts/src/arm64/mediatek/mt6797-evb.dts b/dts/src/arm64/mediatek/mt6797-evb.dts
new file mode 100644
index 0000000000..c79109c654
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt6797-evb.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Mars.C <mars.cheng@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt6797.dtsi"
+
+/ {
+ model = "MediaTek MT6797 Evaluation Board";
+ compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {};
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/mediatek/mt6797.dtsi b/dts/src/arm64/mediatek/mt6797.dtsi
new file mode 100644
index 0000000000..31088a9f71
--- /dev/null
+++ b/dts/src/arm64/mediatek/mt6797.dtsi
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Mars.C <mars.cheng@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/mt6797-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt6797";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x001>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x002>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x003>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x102>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x201>;
+ };
+ };
+
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ topckgen: topckgen@10000000 {
+ compatible = "mediatek,mt6797-topckgen";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infrasys: infracfg_ao@10001000 {
+ compatible = "mediatek,mt6797-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt6797-scpsys";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_VDEC>;
+ clock-names = "mfg", "mm", "vdec";
+ infracfg = <&infrasys>;
+ };
+
+ apmixedsys: apmixed@1000c000 {
+ compatible = "mediatek,mt6797-apmixedsys";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: intpol-controller@10200620 {
+ compatible = "mediatek,mt6797-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10220620 0 0x20>,
+ <0 0x10220690 0 0x10>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6797-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infrasys CLK_INFRA_UART0>,
+ <&infrasys CLK_INFRA_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6797-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infrasys CLK_INFRA_UART1>,
+ <&infrasys CLK_INFRA_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt6797-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infrasys CLK_INFRA_UART2>,
+ <&infrasys CLK_INFRA_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt6797-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infrasys CLK_INFRA_UART3>,
+ <&infrasys CLK_INFRA_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmsys: mmsys_config@14000000 {
+ compatible = "mediatek,mt6797-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: imgsys_config@15000000 {
+ compatible = "mediatek,mt6797-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: vdec_gcon@16000000 {
+ compatible = "mediatek,mt6797-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: venc_gcon@17000000 {
+ compatible = "mediatek,mt6797-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@19000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ reg = <0 0x19000000 0 0x10000>, /* GICD */
+ <0 0x19200000 0 0x200000>, /* GICR */
+ <0 0x10240000 0 0x2000>; /* GICC */
+ };
+};
diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi
index 6922252f31..b99a273729 100644
--- a/dts/src/arm64/mediatek/mt8173.dtsi
+++ b/dts/src/arm64/mediatek/mt8173.dtsi
@@ -731,8 +731,9 @@
<0 0x11280700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
<&clk26m>,
@@ -763,21 +764,31 @@
u3phy: usb-phy@11290000 {
compatible = "mediatek,mt8173-u3phy";
reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
- phy_port0: port@11290800 {
- reg = <0 0x11290800 0 0x800>;
+ u2port0: usb-phy@11290800 {
+ reg = <0 0x11290800 0 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
- phy_port1: port@11291000 {
- reg = <0 0x11291000 0 0x800>;
+ u3port0: usb-phy@11290900 {
+ reg = <0 0x11290900 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: usb-phy@11291000 {
+ reg = <0 0x11291000 0 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
@@ -792,80 +803,74 @@
#clock-cells = <1>;
};
- mdp {
- compatible = "mediatek,mt8173-mdp";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ mdp_rdma0: rdma@14001000 {
+ compatible = "mediatek,mt8173-mdp-rdma",
+ "mediatek,mt8173-mdp";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
+ };
- mdp_rdma0: rdma@14001000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14001000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_rdma1: rdma@14002000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14002000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
- };
+ mdp_rdma1: rdma@14002000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ };
- mdp_rsz0: rsz@14003000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14003000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
+ mdp_rsz0: rsz@14003000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
- mdp_rsz1: rsz@14004000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14004000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
+ mdp_rsz1: rsz@14004000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
- mdp_rsz2: rsz@14005000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14005000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
+ mdp_rsz2: rsz@14005000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
- mdp_wdma0: wdma@14006000 {
- compatible = "mediatek,mt8173-mdp-wdma";
- reg = <0 0x14006000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WDMA>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
- };
+ mdp_wdma0: wdma@14006000 {
+ compatible = "mediatek,mt8173-mdp-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
- mdp_wrot0: wrot@14007000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14007000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
- };
+ mdp_wrot0: wrot@14007000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
- mdp_wrot1: wrot@14008000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14008000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
- };
+ mdp_wrot1: wrot@14008000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14008000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
+ mediatek,larb = <&larb4>;
};
ovl0: ovl@1400c000 {
diff --git a/dts/src/arm64/nvidia/tegra132.dtsi b/dts/src/arm64/nvidia/tegra132.dtsi
index 2b17936ac5..c2f0f27435 100644
--- a/dts/src/arm64/nvidia/tegra132.dtsi
+++ b/dts/src/arm64/nvidia/tegra132.dtsi
@@ -12,7 +12,7 @@
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -55,6 +55,7 @@
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -68,6 +69,7 @@
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi
index 5e62e68ac0..0b0552c9f7 100644
--- a/dts/src/arm64/nvidia/tegra186.dtsi
+++ b/dts/src/arm64/nvidia/tegra186.dtsi
@@ -348,6 +348,13 @@
reg-names = "pmc", "wake", "aotag", "scratch";
};
+ ccplex@e000000 {
+ compatible = "nvidia,tegra186-ccplex-cluster";
+ reg = <0x0 0x0e000000 0x0 0x3fffff>;
+
+ nvidia,bpmp = <&bpmp>;
+ };
+
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
diff --git a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
index 4c1ea7a08d..7cb95e0421 100644
--- a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
+++ b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts
@@ -7,7 +7,7 @@
model = "NVIDIA Jetson TX1 Developer Kit";
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
diff --git a/dts/src/arm64/nvidia/tegra210.dtsi b/dts/src/arm64/nvidia/tegra210.dtsi
index 8f26c4d440..29f471e0f2 100644
--- a/dts/src/arm64/nvidia/tegra210.dtsi
+++ b/dts/src/arm64/nvidia/tegra210.dtsi
@@ -11,7 +11,7 @@
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -51,6 +51,7 @@
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@@ -64,6 +65,7 @@
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi
index a17f5b9a5d..bd310ac196 100644
--- a/dts/src/arm64/qcom/apq8016-sbc.dtsi
+++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi
@@ -178,7 +178,7 @@
led@5 {
label = "apq8016-sbc:yellow:wlan";
gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "wlan";
+ linux,default-trigger = "phy0tx";
default-state = "off";
};
@@ -215,22 +215,16 @@
usb@78d9000 {
extcon = <&usb_id>, <&usb_id>;
status = "okay";
- };
-
- ehci@78d9000 {
- status = "okay";
- };
-
- phy@78d9000 {
- v1p8-supply = <&pm8916_l7>;
- v3p3-supply = <&pm8916_l13>;
- vddcx-supply = <&pm8916_s1>;
- extcon = <&usb_id>, <&usb_id>;
- dr_mode = "otg";
- status = "okay";
- switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_sw_sel_pm>;
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ ulpi {
+ phy {
+ v1p8-supply = <&pm8916_l7>;
+ v3p3-supply = <&pm8916_l13>;
+ extcon = <&usb_id>;
+ };
+ };
};
lpass@07708000 {
@@ -348,6 +342,14 @@
pinctrl-0 = <&usb_id_default>;
};
+ usb-switch {
+ compatible = "toshiba,tc7usb40mu";
+ switch-gpios = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
+ extcon = <&usb_id>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_sw_sel_pm>;
+ };
+
hdmi-out {
compatible = "hdmi-connector";
type = "a";
diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi
index ab3093995d..039991f808 100644
--- a/dts/src/arm64/qcom/msm8916.dtsi
+++ b/dts/src/arm64/qcom/msm8916.dtsi
@@ -546,44 +546,40 @@
status = "disabled";
};
- usb_dev: usb@78d9000 {
+ otg: usb@78d9000 {
compatible = "qcom,ci-hdrc";
- reg = <0x78d9000 0x400>;
- dr_mode = "peripheral";
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- usb-phy = <&usb_otg>;
- status = "disabled";
- };
-
- usb_host: ehci@78d9000 {
- compatible = "qcom,ehci-host";
- reg = <0x78d9000 0x400>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- usb-phy = <&usb_otg>;
- status = "disabled";
- };
-
- usb_otg: phy@78d9000 {
- compatible = "qcom,usb-otg-snps";
- reg = <0x78d9000 0x400>;
+ reg = <0x78d9000 0x200>,
+ <0x78d9200 0x200>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-
- qcom,vdd-levels = <500000 1000000 1320000>;
- qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
- dr_mode = "peripheral";
- qcom,otg-control = <2>; // PMIC
- qcom,manual-pullup;
-
clocks = <&gcc GCC_USB_HS_AHB_CLK>,
- <&gcc GCC_USB_HS_SYSTEM_CLK>,
- <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
- clock-names = "iface", "core", "sleep";
-
- resets = <&gcc GCC_USB2A_PHY_BCR>,
- <&gcc GCC_USB_HS_BCR>;
- reset-names = "phy", "link";
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ clock-names = "iface", "core";
+ assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <80000000>;
+ resets = <&gcc GCC_USB_HS_BCR>;
+ reset-names = "core";
+ phy_type = "ulpi";
+ dr_mode = "otg";
+ ahb-burst-config = <0>;
+ phy-names = "usb-phy";
+ phys = <&usb_hs_phy>;
status = "disabled";
+ #reset-cells = <1>;
+
+ ulpi {
+ usb_hs_phy: phy {
+ compatible = "qcom,usb-hs-phy-msm8916",
+ "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+ reset-names = "phy", "por";
+ qcom,init-seq = /bits/ 8 <0x0 0x44
+ 0x1 0x6b 0x2 0x24 0x3 0x13>;
+ };
+ };
};
intc: interrupt-controller@b000000 {
@@ -1116,6 +1112,38 @@
};
};
+ debug@850000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x850000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU0>;
+ };
+
+ debug@852000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x852000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU1>;
+ };
+
+ debug@854000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x854000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU2>;
+ };
+
+ debug@856000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x856000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU3>;
+ };
+
etm@85c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85c000 0x1000>;
diff --git a/dts/src/arm64/qcom/msm8992.dtsi b/dts/src/arm64/qcom/msm8992.dtsi
index 44b2d37d8c..171578747e 100644
--- a/dts/src/arm64/qcom/msm8992.dtsi
+++ b/dts/src/arm64/qcom/msm8992.dtsi
@@ -68,6 +68,30 @@
clock-frequency = <32768>;
};
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ status = "okay";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
+
+ sfpb_mutex: hwmutex {
+ compatible = "qcom,sfpb-mutex";
+ syscon = <&sfpb_mutex_regs 0x0 0x100>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ hwlocks = <&sfpb_mutex 3>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -82,6 +106,11 @@
<0xf9002000 0x1000>;
};
+ apcs: syscon@f900d000 {
+ compatible = "syscon";
+ reg = <0xf900d000 0x2000>;
+ };
+
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -172,12 +201,36 @@
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
+
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+
+ sfpb_mutex_regs: syscon@fd484000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "syscon";
+ reg = <0xfd484000 0x400>;
+ };
};
memory {
device_type = "memory";
reg = <0 0 0 0>; // bootloader will update
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_region: smem@6a00000 {
+ reg = <0x0 0x6a00000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
};
diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi
index 9bc9c857a0..8f085716e2 100644
--- a/dts/src/arm64/qcom/msm8996.dtsi
+++ b/dts/src/arm64/qcom/msm8996.dtsi
@@ -311,6 +311,12 @@
reg = <0x300000 0x90000>;
};
+ kryocc: clock-controller@6400000 {
+ compatible = "qcom,apcc-msm8996";
+ reg = <0x6400000 0x90000>;
+ #clock-cells = <1>;
+ };
+
blsp1_spi0: spi@07575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
diff --git a/dts/src/arm64/realtek/rtd1295-zidoo-x9s.dts b/dts/src/arm64/realtek/rtd1295-zidoo-x9s.dts
new file mode 100644
index 0000000000..6efa8091bb
--- /dev/null
+++ b/dts/src/arm64/realtek/rtd1295-zidoo-x9s.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x0000000000000000 0x0000000000030000;
+/memreserve/ 0x000000000001f000 0x0000000000001000;
+/memreserve/ 0x0000000000030000 0x00000000000d0000;
+/memreserve/ 0x0000000001b00000 0x00000000004be000;
+/memreserve/ 0x0000000001ffe000 0x0000000000004000;
+
+#include "rtd1295.dtsi"
+
+/ {
+ compatible = "zidoo,x9s", "realtek,rtd1295";
+ model = "Zidoo X9S";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/realtek/rtd1295.dtsi b/dts/src/arm64/realtek/rtd1295.dtsi
new file mode 100644
index 0000000000..d8f84666c8
--- /dev/null
+++ b/dts/src/arm64/realtek/rtd1295.dtsi
@@ -0,0 +1,131 @@
+/*
+ * Realtek RTD1295 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "realtek,rtd1295";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ tee@10100000 {
+ reg = <0x10100000 0xf00000>;
+ no-map;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Exclude up to 2 GiB of RAM */
+ ranges = <0x80000000 0x80000000 0x80000000>;
+
+ uart0: serial@98007800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x98007800 0x400>,
+ <0x98007000 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <27000000>;
+ status = "disabled";
+ };
+
+ uart1: serial@9801b200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x9801b200 0x100>,
+ <0x9801b00c 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <432000000>;
+ status = "disabled";
+ };
+
+ uart2: serial@9801b400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x9801b400 0x100>,
+ <0x9801b00c 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <432000000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@ff011000 {
+ compatible = "arm,gic-400";
+ reg = <0xff011000 0x1000>,
+ <0xff012000 0x2000>,
+ <0xff014000 0x2000>,
+ <0xff016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
diff --git a/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts b/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts
new file mode 100644
index 0000000000..95fe207cb6
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts
@@ -0,0 +1,42 @@
+/*
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
+/dts-v1/;
+#include "r8a7795-es1.dtsi"
+#include "ulcb.dtsi"
+
+/ {
+ model = "Renesas H3ULCB board based on r8a7795 ES1.x";
+ compatible = "renesas,h3ulcb", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
+ };
+};
diff --git a/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts b/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts
new file mode 100644
index 0000000000..b84c156ed6
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree Source for the Salvator-X board
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
+/dts-v1/;
+#include "r8a7795-es1.dtsi"
+#include "salvator-x.dtsi"
+
+/ {
+ model = "Renesas Salvator-X board based on r8a7795 ES1.x";
+ compatible = "renesas,salvator-x", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&x21_clk>,
+ <&x22_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
+
+&hdmi1 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi1_out: endpoint {
+ remote-endpoint = <&hdmi1_con>;
+ };
+ };
+ };
+};
+
+&hdmi1_con {
+ remote-endpoint = <&rcar_dw_hdmi1_out>;
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&pfc {
+ usb2_pins: usb2 {
+ groups = "usb2";
+ function = "usb2";
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&usb2_phy2 {
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/dts/src/arm64/renesas/r8a7795-es1.dtsi b/dts/src/arm64/renesas/r8a7795-es1.dtsi
new file mode 100644
index 0000000000..a0ba7bd21e
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a7795-es1.dtsi
@@ -0,0 +1,84 @@
+/*
+ * Device Tree Source for the r8a7795 ES1.x SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795.dtsi"
+
+&soc {
+ xhci1: usb@ee0400000 {
+ compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
+ reg = <0 0xee040000 0 0xc00>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 327>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 327>;
+ status = "disabled";
+ };
+
+ fcpf2: fcp@fe952000 {
+ compatible = "renesas,fcpf";
+ reg = <0 0xfe952000 0 0x200>;
+ clocks = <&cpg CPG_MOD 613>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 613>;
+ };
+
+ vspi2: vsp@fe9c0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe9c0000 0 0x8000>;
+ interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 629>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 629>;
+
+ renesas,fcp = <&fcpvi2>;
+ };
+
+ fcpvi2: fcp@fe9cf000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9cf000 0 0x200>;
+ clocks = <&cpg CPG_MOD 609>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 609>;
+ };
+
+ vspd3: vsp@fea38000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea38000 0 0x4000>;
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 620>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 620>;
+
+ renesas,fcp = <&fcpvd3>;
+ };
+
+ fcpvd3: fcp@fea3f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea3f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 600>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 600>;
+ };
+
+ fdp1@fe948000 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe948000 0 0x2400>;
+ interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 117>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 117>;
+ renesas,fcp = <&fcpf2>;
+ };
+};
+
+&du {
+ compatible = "renesas,du-r8a7795";
+ vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+};
diff --git a/dts/src/arm64/renesas/r8a7795-h3ulcb.dts b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
index ab352159de..0426f41765 100644
--- a/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
+++ b/dts/src/arm64/renesas/r8a7795-h3ulcb.dts
@@ -9,24 +9,16 @@
* kind, whether express or implied.
*/
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
/dts-v1/;
#include "r8a7795.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "ulcb.dtsi"
/ {
- model = "Renesas H3ULCB board based on r8a7795";
+ model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- aliases {
- serial0 = &scif2;
- ethernet0 = &avb;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@@ -47,330 +39,4 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
-
- leds {
- compatible = "gpio-leds";
-
- led5 {
- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
- };
- led6 {
- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- key-1 {
- linux,code = <KEY_1>;
- label = "SW3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- };
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- reg_1p8v: regulator0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- rsnd_ak4613: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcpu>;
- simple-audio-card,frame-master = <&sndcpu>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4613>;
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- avb_pins: avb {
- groups = "avb_mdc";
- function = "avb";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound-clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
- };
-
- cs2000: clk-multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A7795_CLK_S0D4>;
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0 &src0 &dvc0>;
- capture = <&ssi1 &src1 &dvc1>;
- };
- };
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
};
diff --git a/dts/src/arm64/renesas/r8a7795-salvator-x.dts b/dts/src/arm64/renesas/r8a7795-salvator-x.dts
index 639aa085d9..684fb3b9d1 100644
--- a/dts/src/arm64/renesas/r8a7795-salvator-x.dts
+++ b/dts/src/arm64/renesas/r8a7795-salvator-x.dts
@@ -8,577 +8,108 @@
* kind, whether express or implied.
*/
-/*
- * SSI-AK4613
- *
- * This command is required when Playback/Capture
- *
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
-#include <dt-bindings/gpio/gpio.h>
+#include "salvator-x.dtsi"
/ {
- model = "Renesas Salvator-X board based on r8a7795";
+ model = "Renesas Salvator-X board based on r8a7795 ES2.0+";
compatible = "renesas,salvator-x", "renesas,r8a7795";
- aliases {
- serial0 = &scif2;
- serial1 = &scif1;
- ethernet0 = &avb;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
- stdout-path = "serial0:115200n8";
- };
-
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- reg_1p8v: regulator0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-
- vcc_sdhi3: regulator-vcc-sdhi3 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI3 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi3: regulator-vccq-sdhi3 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI3 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
};
- vbus0_usb2: regulator-vbus0-usb2 {
- compatible = "regulator-fixed";
-
- regulator-name = "USB20_VBUS0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
};
- audio_clkout: audio_clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
};
+};
- rsnd_ak4613: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcpu>;
- simple-audio-card,frame-master = <&sndcpu>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4613>;
- };
- };
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&versaclock5 1>,
+ <&x21_clk>,
+ <&x22_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
+};
- vga-encoder {
- compatible = "adi,adv7123";
+&ehci2 {
+ status = "okay";
+};
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+&hdmi0 {
+ status = "okay";
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
};
};
};
+};
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
};
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
+&hdmi1 {
status = "okay";
ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- port@3 {
- lvds_connector: endpoint {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi1_out: endpoint {
+ remote-endpoint = <&hdmi1_con>;
};
};
};
};
-&extal_clk {
- clock-frequency = <16666666>;
+&hdmi1_con {
+ remote-endpoint = <&rcar_dw_hdmi1_out>;
};
-&extalr_clk {
- clock-frequency = <32768>;
+&ohci2 {
+ status = "okay";
};
&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- scif1_pins: scif1 {
- groups = "scif1_data_a", "scif1_ctrl";
- function = "scif1";
- };
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- avb_pins: avb {
- mux {
- groups = "avb_link", "avb_phy_int", "avb_mdc",
- "avb_mii";
- function = "avb";
- };
-
- pins_mdc {
- groups = "avb_mdc";
- drive-strength = <24>;
- };
-
- pins_mii_tx {
- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
- drive-strength = <12>;
- };
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
- function = "du";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <3300>;
- };
-
- sdhi3_pins_uhs: sd3_uhs {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- mux {
- groups = "usb1";
- function = "usb1";
- };
-
- ovc {
- pins = "GP_6_27";
- bias-pull-up;
- };
-
- pwen {
- pins = "GP_6_26";
- bias-pull-down;
- };
- };
-
usb2_pins: usb2 {
groups = "usb2";
function = "usb2";
};
};
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
- };
-
- cs2000: clk_multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A7795_CLK_S0D4>;
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0 &src0 &dvc0>;
- capture = <&ssi1 &src1 &dvc1>;
- };
- };
-};
-
&sata {
status = "okay";
};
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&sdhi3 {
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi3>;
- vqmmc-supply = <&vccq_sdhi3>;
- cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&i2c_dvfs {
- status = "okay";
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&xhci0 {
- status = "okay";
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&vbus0_usb2>;
- status = "okay";
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";
status = "okay";
};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&ehci2 {
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&hsusb {
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec0 {
- status = "okay";
-};
-
-&pciec1 {
- status = "okay";
-};
diff --git a/dts/src/arm64/renesas/r8a7795-salvator-xs.dts b/dts/src/arm64/renesas/r8a7795-salvator-xs.dts
new file mode 100644
index 0000000000..de35495714
--- /dev/null
+++ b/dts/src/arm64/renesas/r8a7795-salvator-xs.dts
@@ -0,0 +1,109 @@
+/*
+ * Device Tree Source for the Salvator-X 2nd version board
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
+
+/dts-v1/;
+#include "r8a7795.dtsi"
+#include "salvator-xs.dtsi"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+";
+ compatible = "renesas,salvator-xs", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&x21_clk>,
+ <&x22_clk>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ "dclkin.1", "dclkin.2";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi0_con {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+};
+
+&hdmi1 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi1_out: endpoint {
+ remote-endpoint = <&hdmi1_con>;
+ };
+ };
+ };
+};
+
+&hdmi1_con {
+ remote-endpoint = <&rcar_dw_hdmi1_out>;
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&pfc {
+ usb2_pins: usb2 {
+ groups = "usb2";
+ function = "usb2";
+ };
+};
+
+&usb2_phy2 {
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/dts/src/arm64/renesas/r8a7795.dtsi b/dts/src/arm64/renesas/r8a7795.dtsi
index e99d6443b3..e31c1b660b 100644
--- a/dts/src/arm64/renesas/r8a7795.dtsi
+++ b/dts/src/arm64/renesas/r8a7795.dtsi
@@ -182,7 +182,7 @@
clock-frequency = <0>;
};
- soc {
+ soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -398,7 +398,7 @@
#power-domain-cells = <1>;
};
- pfc: pfc@e6060000 {
+ pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0 0xe6060000 0 0x50c>;
};
@@ -883,6 +883,8 @@
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 926>;
+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1118,6 +1120,16 @@
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
status = "disabled";
rcar_sound,dvc {
@@ -1274,16 +1286,6 @@
status = "disabled";
};
- xhci1: usb@ee0400000 {
- compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
- reg = <0 0xee040000 0 0xc00>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 327>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 327>;
- status = "disabled";
- };
-
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
@@ -1568,14 +1570,6 @@
resets = <&cpg 614>;
};
- fcpf2: fcp@fe952000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe952000 0 0x200>;
- clocks = <&cpg CPG_MOD 613>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 613>;
- };
-
vspbd: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
@@ -1633,25 +1627,6 @@
resets = <&cpg 610>;
};
- vspi2: vsp@fe9c0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9c0000 0 0x8000>;
- interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 629>;
-
- renesas,fcp = <&fcpvi2>;
- };
-
- fcpvi2: fcp@fe9cf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9cf000 0 0x200>;
- clocks = <&cpg CPG_MOD 609>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 609>;
- };
-
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
@@ -1709,25 +1684,6 @@
resets = <&cpg 601>;
};
- vspd3: vsp@fea38000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea38000 0 0x4000>;
- interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 620>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 620>;
-
- renesas,fcp = <&fcpvd3>;
- };
-
- fcpvd3: fcp@fea3f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea3f000 0 0x200>;
- clocks = <&cpg CPG_MOD 600>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 600>;
- };
-
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
@@ -1748,18 +1704,57 @@
renesas,fcp = <&fcpf1>;
};
- fdp1@fe948000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe948000 0 0x2400>;
- interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 117>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 117>;
- renesas,fcp = <&fcpf2>;
+ hdmi0: hdmi0@fead0000 {
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0 0xfead0000 0 0x10000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 729>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi1: hdmi1@feae0000 {
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
+ reg = <0 0xfeae0000 0 0x10000>;
+ interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
+ clock-names = "iahb", "isfr";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 728>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dw_hdmi1_in: endpoint {
+ remote-endpoint = <&du_out_hdmi1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
};
du: display@feb00000 {
- compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
@@ -1775,8 +1770,6 @@
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
status = "disabled";
- vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1789,11 +1782,13 @@
port@1 {
reg = <1>;
du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
du_out_hdmi1: endpoint {
+ remote-endpoint = <&dw_hdmi1_in>;
};
};
port@3 {
diff --git a/dts/src/arm64/renesas/r8a7796-m3ulcb.dts b/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
index 372b2a9447..38b58b7fca 100644
--- a/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
+++ b/dts/src/arm64/renesas/r8a7796-m3ulcb.dts
@@ -9,180 +9,24 @@
* kind, whether express or implied.
*/
+#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
+
/dts-v1/;
#include "r8a7796.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "ulcb.dtsi"
/ {
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
- aliases {
- serial0 = &scif2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
- leds {
- compatible = "gpio-leds";
-
- led5 {
- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
- };
- led6 {
- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- key-1 {
- linux,code = <KEY_1>;
- label = "SW3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- };
- };
-
- reg_1p8v: regulator0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};
diff --git a/dts/src/arm64/renesas/r8a7796-salvator-x.dts b/dts/src/arm64/renesas/r8a7796-salvator-x.dts
index c9f59b6ce3..db4f162d6b 100644
--- a/dts/src/arm64/renesas/r8a7796-salvator-x.dts
+++ b/dts/src/arm64/renesas/r8a7796-salvator-x.dts
@@ -8,25 +8,16 @@
* kind, whether express or implied.
*/
+#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
+
/dts-v1/;
#include "r8a7796.dtsi"
-#include <dt-bindings/gpio/gpio.h>
+#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a7796";
compatible = "renesas,salvator-x", "renesas,r8a7796";
- aliases {
- serial0 = &scif2;
- serial1 = &scif1;
- ethernet0 = &avb;
- };
-
- chosen {
- bootargs = "ignore_loglevel";
- stdout-path = "serial0:115200n8";
- };
-
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@@ -37,233 +28,4 @@
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
-
- reg_1p8v: regulator0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-
- vcc_sdhi3: regulator-vcc-sdhi3 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI3 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi3: regulator-vccq-sdhi3 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI3 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb {
- groups = "avb_mdc";
- function = "avb";
- };
-
- scif1_pins: scif1 {
- groups = "scif1_data_a", "scif1_ctrl";
- function = "scif1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <3300>;
- };
-
- sdhi3_pins_uhs: sd3_uhs {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <1800>;
- };
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&sdhi3 {
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi3>;
- vqmmc-supply = <&vccq_sdhi3>;
- cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&i2c_dvfs {
- status = "okay";
};
diff --git a/dts/src/arm64/renesas/r8a7796.dtsi b/dts/src/arm64/renesas/r8a7796.dtsi
index 2ec1ed5f49..1f67109120 100644
--- a/dts/src/arm64/renesas/r8a7796.dtsi
+++ b/dts/src/arm64/renesas/r8a7796.dtsi
@@ -120,6 +120,29 @@
clock-frequency = <0>;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@@ -134,6 +157,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -362,6 +392,78 @@
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 926>;
+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ resets = <&cpg 523>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -931,6 +1033,106 @@
dma-channels = <16>;
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7796",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7796",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ hsusb: usb@e6590000 {
+ /* placeholder */
+ };
+
+ xhci0: usb@ee000000 {
+ /* placeholder */
+ };
+
+ ohci0: usb@ee080000 {
+ /* placeholder */
+ };
+
+ ehci0: usb@ee080100 {
+ /* placeholder */
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ /* placeholder */
+ };
+
+ ohci1: usb@ee0a0000 {
+ /* placeholder */
+ };
+
+ ehci1: usb@ee0a0100 {
+ /* placeholder */
+ };
+
+ usb2_phy1: usb-phy@ee0a0200 {
+ /* placeholder */
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee100000 0 0x2000>;
@@ -1033,5 +1235,224 @@
};
};
};
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required for audio_clkout0/1/2/3
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7796_CLK_S0D4>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+
+ pciec0: pcie@fe000000 {
+ /* placeholder */
+ };
+
+ pciec1: pcie@ee800000 {
+ /* placeholder */
+ };
+
+ du: display@feb00000 {
+ /* placeholder */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ };
+ };
};
};
diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi
new file mode 100644
index 0000000000..aef35e0b68
--- /dev/null
+++ b/dts/src/arm64/renesas/salvator-common.dtsi
@@ -0,0 +1,629 @@
+/*
+ * Device Tree Source for common parts of Salvator-X board variants
+ *
+ * Copyright (C) 2015-2016 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/*
+ * SSI-AK4613
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &scif2;
+ serial1 = &scif1;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ audio_clkout: audio_clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>;
+
+ brightness-levels = <256 128 64 16 8 4 0>;
+ default-brightness-level = <6>;
+
+ enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcpu>;
+ simple-audio-card,frame-master = <&sndcpu>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4613>;
+ };
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi3: regulator-vcc-sdhi3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI3 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi3: regulator-vccq-sdhi3 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI3 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ label = "HDMI0 OUT";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ };
+ };
+ };
+
+ hdmi1-out {
+ compatible = "hdmi-connector";
+ label = "HDMI1 OUT";
+ type = "a";
+
+ port {
+ hdmi1_con: endpoint {
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ /* External DU dot clocks */
+ x21_clk: x21-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33000000>;
+ };
+
+ x22_clk: x22-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33000000>;
+ };
+
+ x23_clk: x23-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ port@3 {
+ lvds_connector: endpoint {
+ };
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&hsusb {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk_multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ csa_vdd: adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+
+ shunt-resistor-micro-ohms = <5000>;
+ };
+
+ csa_dvfs: adc@7f {
+ compatible = "maxim,max9611";
+ reg = <0x7f>;
+
+ shunt-resistor-micro-ohms = <5000>;
+ };
+};
+
+&i2c_dvfs {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ status = "okay";
+};
+
+&pciec1 {
+ status = "okay";
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_phy_int", "avb_mdc",
+ "avb_mii";
+ function = "avb";
+ };
+
+ pins_mdc {
+ groups = "avb_mdc";
+ drive-strength = <24>;
+ };
+
+ pins_mii_tx {
+ pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+ "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+ drive-strength = <12>;
+ };
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
+ function = "du";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2_a";
+ function = "i2c2";
+ };
+
+ pwm1_pins: pwm1 {
+ groups = "pwm1_a";
+ function = "pwm1";
+ };
+
+ scif1_pins: scif1 {
+ groups = "scif1_data_a", "scif1_ctrl";
+ function = "scif1";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_a";
+ function = "scif_clk";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <3300>;
+ };
+
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout3_a";
+ function = "audio_clk";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ mux {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ ovc {
+ pins = "GP_6_27";
+ bias-pull-up;
+ };
+
+ pwen {
+ pins = "GP_6_26";
+ bias-pull-down;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <11289600 12288000>;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&sdhi2 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdhi3 {
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi3>;
+ vqmmc-supply = <&vccq_sdhi3>;
+ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&wdt0 {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/renesas/salvator-x.dtsi b/dts/src/arm64/renesas/salvator-x.dtsi
new file mode 100644
index 0000000000..468868c8ed
--- /dev/null
+++ b/dts/src/arm64/renesas/salvator-x.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Device Tree Source for the Salvator-X board
+ *
+ * Copyright (C) 2015-2016 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "salvator-common.dtsi"
+
+/ {
+ model = "Renesas Salvator-X board";
+ compatible = "renesas,salvator-x";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&i2c4 {
+ versaclock5: clock-generator@6a {
+ compatible = "idt,5p49v5923";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ clocks = <&x23_clk>;
+ clock-names = "xin";
+ };
+};
diff --git a/dts/src/arm64/renesas/salvator-xs.dtsi b/dts/src/arm64/renesas/salvator-xs.dtsi
new file mode 100644
index 0000000000..81227e3c2c
--- /dev/null
+++ b/dts/src/arm64/renesas/salvator-xs.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Source for the Salvator-X 2nd version board
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "salvator-common.dtsi"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board";
+ compatible = "renesas,salvator-xs";
+};
+
+&extal_clk {
+ clock-frequency = <16640000>;
+};
diff --git a/dts/src/arm64/renesas/ulcb.dtsi b/dts/src/arm64/renesas/ulcb.dtsi
new file mode 100644
index 0000000000..b5c6ee07d7
--- /dev/null
+++ b/dts/src/arm64/renesas/ulcb.dtsi
@@ -0,0 +1,367 @@
+/*
+ * Device Tree Source for the R-Car Gen3 ULCB board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Renesas R-Car Gen3 ULCB board";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ key-1 {
+ linux,code = <KEY_1>;
+ label = "SW3";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led5 {
+ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+ };
+ led6 {
+ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcpu>;
+ simple-audio-card,frame-master = <&sndcpu>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4613>;
+ };
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_phy_int", "avb_mdc",
+ "avb_mii";
+ function = "avb";
+ };
+
+ pins_mdc {
+ groups = "avb_mdc";
+ drive-strength = <24>;
+ };
+
+ pins_mii_tx {
+ pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+ "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+ drive-strength = <12>;
+ };
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2_a";
+ function = "i2c2";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_a";
+ function = "scif_clk";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound-clk {
+ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout3_a";
+ function = "audio_clk";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <11289600 12288000>;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&sdhi2 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&wdt0 {
+ timeout-sec = <60>;
+ status = "okay";
+};
diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi
index 7e69f1fe78..0be96cee27 100644
--- a/dts/src/arm64/rockchip/rk3328.dtsi
+++ b/dts/src/arm64/rockchip/rk3328.dtsi
@@ -372,6 +372,39 @@
<32768>;
};
+ sdmmc: dwmmc@ff500000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff500000 0x0 0x4000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@ff510000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff510000 0x0 0x4000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ emmc: dwmmc@ff520000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff520000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
gmac2io: ethernet@ff540000 {
compatible = "rockchip,rk3328-gmac";
reg = <0x0 0xff540000 0x0 0x10000>;
diff --git a/dts/src/arm64/rockchip/rk3399-firefly.dts b/dts/src/arm64/rockchip/rk3399-firefly.dts
new file mode 100644
index 0000000000..ba1d9810ad
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-firefly.dts
@@ -0,0 +1,718 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+
+/ {
+ model = "Firefly-RK3399 Board";
+ compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm0 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ rt5640-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,rt5640-codec";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Mic Jack", "MICBIAS1",
+ "IN1P", "Mic Jack",
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rt5640>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG2 {
+ regulator-name = "vcc2v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <0>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+
+ rt5640: rt5640@1c {
+ compatible = "realtek,rt5640";
+ reg = <0x1c>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ realtek,in1-differential;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rt5640_hpcon>;
+ };
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ accelerometer@68 {
+ compatible = "invensense,mpu6500";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&i2s2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc1v8_dvp>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ lcd-panel {
+ lcd_panel_reset: lcd-panel-reset {
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_3g_drv: pcie-3g-drv {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rt5640 {
+ rt5640_hpcon: rt5640-hpcon {
+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ keep-power-in-suspend;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/dts/src/arm64/rockchip/rk3399-gru.dtsi b/dts/src/arm64/rockchip/rk3399-gru.dtsi
index 0d960b7f76..eb50593440 100644
--- a/dts/src/arm64/rockchip/rk3399-gru.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-gru.dtsi
@@ -44,7 +44,7 @@
#include <dt-bindings/input/input.h>
#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
+#include "rk3399-op1-opp.dtsi"
/ {
chosen {
diff --git a/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi b/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi
new file mode 100644
index 0000000000..be7fe635f7
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3399-op1-opp.dtsi
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <825000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <900000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <975000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <900000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <975000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1150000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1250000>;
+ };
+ };
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+};
diff --git a/dts/src/arm64/rockchip/rk3399-opp.dtsi b/dts/src/arm64/rockchip/rk3399-opp.dtsi
index dd82e16236..c83460db13 100644
--- a/dts/src/arm64/rockchip/rk3399-opp.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-opp.dtsi
@@ -56,22 +56,18 @@
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <800000>;
+ opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <875000>;
+ opp-microvolt = <925000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <925000>;
+ opp-microvolt = <1000000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1050000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1125000>;
};
};
@@ -107,15 +103,11 @@
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <1075000>;
+ opp-microvolt = <1100000>;
};
opp07 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1150000>;
- };
- opp08 {
- opp-hz = /bits/ 64 <2016000000>;
- opp-microvolt = <1250000>;
+ opp-microvolt = <1200000>;
};
};
};
diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi
index f4f3c96c79..69c56f7316 100644
--- a/dts/src/arm64/rockchip/rk3399.dtsi
+++ b/dts/src/arm64/rockchip/rk3399.dtsi
@@ -56,6 +56,7 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -220,7 +221,7 @@
#size-cells = <2>;
#interrupt-cells = <1>;
aspm-no-l0s;
- bus-range = <0x0 0x1>;
+ bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
@@ -239,8 +240,8 @@
msi-map = <0x0 &its 0x0 0x1000>;
phys = <&pcie_phy>;
phy-names = "pcie-phy";
- ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
- 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+ ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
+ 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
@@ -769,11 +770,6 @@
status = "disabled";
};
- qos_sd: qos@ffa74000 {
- compatible = "syscon";
- reg = <0x0 0xffa74000 0x0 0x20>;
- };
-
qos_emmc: qos@ffa58000 {
compatible = "syscon";
reg = <0x0 0xffa58000 0x0 0x20>;
@@ -784,6 +780,41 @@
reg = <0x0 0xffa5c000 0x0 0x20>;
};
+ qos_pcie: qos@ffa60080 {
+ compatible = "syscon";
+ reg = <0x0 0xffa60080 0x0 0x20>;
+ };
+
+ qos_usb_host0: qos@ffa60100 {
+ compatible = "syscon";
+ reg = <0x0 0xffa60100 0x0 0x20>;
+ };
+
+ qos_usb_host1: qos@ffa60180 {
+ compatible = "syscon";
+ reg = <0x0 0xffa60180 0x0 0x20>;
+ };
+
+ qos_usb_otg0: qos@ffa70000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa70000 0x0 0x20>;
+ };
+
+ qos_usb_otg1: qos@ffa70080 {
+ compatible = "syscon";
+ reg = <0x0 0xffa70080 0x0 0x20>;
+ };
+
+ qos_sd: qos@ffa74000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa74000 0x0 0x20>;
+ };
+
+ qos_sdioaudio: qos@ffa76000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa76000 0x0 0x20>;
+ };
+
qos_hdcp: qos@ffa90000 {
compatible = "syscon";
reg = <0x0 0xffa90000 0x0 0x20>;
@@ -854,6 +885,11 @@
reg = <0x0 0xffad0000 0x0 0x20>;
};
+ qos_perihp: qos@ffad8080 {
+ compatible = "syscon";
+ reg = <0x0 0xffad8080 0x0 0x20>;
+ };
+
qos_gpu: qos@ffae0000 {
compatible = "syscon";
reg = <0x0 0xffae0000 0x0 0x20>;
@@ -1676,6 +1712,91 @@
};
};
+ sdio0 {
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins =
+ <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins =
+ <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins =
+ <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins =
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cd: sdio0-cd {
+ rockchip,pins =
+ <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins =
+ <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bkpwr: sdio0-bkpwr {
+ rockchip,pins =
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_wp: sdio0-wp {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_int: sdio0-int {
+ rockchip,pins =
+ <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins =
+ <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
+ <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
+ <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
+ <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_cd: sdmcc-cd {
+ rockchip,pins =
+ <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_wp: sdmmc-wp {
+ rockchip,pins =
+ <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
sleep {
ap_pwroff: ap-pwroff {
rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
@@ -1691,6 +1812,11 @@
rockchip,pins =
<4 21 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ spdif_bus_1: spdif-bus-1 {
+ rockchip,pins =
+ <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+ };
};
spi0 {
@@ -1950,6 +2076,19 @@
};
};
+ hdmi {
+ hdmi_i2c_xfer: hdmi-i2c-xfer {
+ rockchip,pins =
+ <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
+ <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ rockchip,pins =
+ <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pcie {
pcie_clkreqn: pci-clkreqn {
rockchip,pins =
@@ -1960,6 +2099,16 @@
rockchip,pins =
<4 24 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ pcie_clkreqn_cpm: pci-clkreqn-cpm {
+ rockchip,pins =
+ <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
+ rockchip,pins =
+ <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
};
diff --git a/dts/src/arm64/socionext/uniphier-ld11-global.dts b/dts/src/arm64/socionext/uniphier-ld11-global.dts
new file mode 100644
index 0000000000..115357018e
--- /dev/null
+++ b/dts/src/arm64/socionext/uniphier-ld11-global.dts
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Source for UniPhier LD11 Global Board
+ *
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld11.dtsi"
+
+/ {
+ model = "UniPhier LD11 Global Board (REF_LD11_GP)";
+ compatible = "socionext,uniphier-ld11-global",
+ "socionext,uniphier-ld11";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "st,24c64", "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/socionext/uniphier-ld11-ref.dts b/dts/src/arm64/socionext/uniphier-ld11-ref.dts
index 0173e93ab1..cc8ebe34c2 100644
--- a/dts/src/arm64/socionext/uniphier-ld11-ref.dts
+++ b/dts/src/arm64/socionext/uniphier-ld11-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm64/socionext/uniphier-ld11.dtsi b/dts/src/arm64/socionext/uniphier-ld11.dtsi
index 151c043b48..bdce5b89ba 100644
--- a/dts/src/arm64/socionext/uniphier-ld11.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ld11.dtsi
@@ -4,46 +4,10 @@
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
/ {
compatible = "socionext,uniphier-ld11";
@@ -89,31 +53,31 @@
compatible = "operating-points-v2";
opp-shared;
- opp@245000000 {
+ opp-245000000 {
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
- opp@250000000 {
+ opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
- opp@490000000 {
+ opp-490000000 {
opp-hz = /bits/ 64 <490000000>;
clock-latency-ns = <300>;
};
- opp@500000000 {
+ opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
- opp@653334000 {
+ opp-653334000 {
opp-hz = /bits/ 64 <653334000>;
clock-latency-ns = <300>;
};
- opp@666667000 {
+ opp-666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
- opp@980000000 {
+ opp-980000000 {
opp-hz = /bits/ 64 <980000000>;
clock-latency-ns = <300>;
};
@@ -268,7 +232,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
@@ -310,6 +274,11 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-mmc-highspeed = <2>;
+ cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
usb0: usb@5a800100 {
diff --git a/dts/src/arm64/socionext/uniphier-ld20-global.dts b/dts/src/arm64/socionext/uniphier-ld20-global.dts
new file mode 100644
index 0000000000..9f620d4101
--- /dev/null
+++ b/dts/src/arm64/socionext/uniphier-ld20-global.dts
@@ -0,0 +1,52 @@
+/*
+ * Device Tree Source for UniPhier LD20 Global Board
+ *
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld20.dtsi"
+
+/ {
+ model = "UniPhier LD20 Global Board (REF_LD20_GP)";
+ compatible = "socionext,uniphier-ld20-global",
+ "socionext,uniphier-ld20";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/dts/src/arm64/socionext/uniphier-ld20-ref.dts b/dts/src/arm64/socionext/uniphier-ld20-ref.dts
index fca4c479b4..494166aee2 100644
--- a/dts/src/arm64/socionext/uniphier-ld20-ref.dts
+++ b/dts/src/arm64/socionext/uniphier-ld20-ref.dts
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/dts/src/arm64/socionext/uniphier-ld20.dtsi b/dts/src/arm64/socionext/uniphier-ld20.dtsi
index 6193f11acb..de1e753628 100644
--- a/dts/src/arm64/socionext/uniphier-ld20.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ld20.dtsi
@@ -4,46 +4,10 @@
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
/ {
compatible = "socionext,uniphier-ld20";
@@ -116,35 +80,35 @@
compatible = "operating-points-v2";
opp-shared;
- opp@250000000 {
+ opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
- opp@275000000 {
+ opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
- opp@500000000 {
+ opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
- opp@550000000 {
+ opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
- opp@666667000 {
+ opp-666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
- opp@733334000 {
+ opp-733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
- opp@1100000000 {
+ opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
@@ -154,35 +118,35 @@
compatible = "operating-points-v2";
opp-shared;
- opp@250000000 {
+ opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
- opp@275000000 {
+ opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
- opp@500000000 {
+ opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
- opp@550000000 {
+ opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
- opp@666667000 {
+ opp-666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
- opp@733334000 {
+ opp-733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
- opp@1100000000 {
+ opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
@@ -337,7 +301,7 @@
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
@@ -384,6 +348,11 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-mmc-highspeed = <2>;
+ cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
soc-glue@5f800000 {
diff --git a/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi b/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
index c62ae1a81f..7a1c29b558 100644
--- a/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
+++ b/dts/src/arm64/socionext/uniphier-ref-daughter.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&i2c0 {
diff --git a/dts/src/arm64/socionext/uniphier-support-card.dtsi b/dts/src/arm64/socionext/uniphier-support-card.dtsi
index f61dfec280..6c825f192e 100644
--- a/dts/src/arm64/socionext/uniphier-support-card.dtsi
+++ b/dts/src/arm64/socionext/uniphier-support-card.dtsi
@@ -4,43 +4,7 @@
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&system_bus {
@@ -53,14 +17,14 @@
#size-cells = <1>;
ranges = <0x00000000 1 0x01f00000 0x00100000>;
- ethsc: ethernet@00000000 {
+ ethsc: ethernet@0 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <0x00000000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
};
- serialsc: uart@000b0000 {
+ serialsc: uart@b0000 {
compatible = "ns16550a";
reg = <0x000b0000 0x20>;
clock-frequency = <12288000>;
diff --git a/dts/src/arm64/zte/zx296718.dtsi b/dts/src/arm64/zte/zx296718.dtsi
index 316dc71326..d83bf789c8 100644
--- a/dts/src/arm64/zte/zx296718.dtsi
+++ b/dts/src/arm64/zte/zx296718.dtsi
@@ -118,27 +118,27 @@
compatible = "operating-points-v2";
opp-shared;
- opp@500000000 {
+ opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <500000>;
};
- opp@648000000 {
+ opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
clock-latency-ns = <500000>;
};
- opp@800000000 {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <500000>;
};
- opp@1000000000 {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <500000>;
};
- opp@1188000000 {
+ opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
clock-latency-ns = <500000>;
};
diff --git a/dts/src/mips/img/boston.dts b/dts/src/mips/img/boston.dts
new file mode 100644
index 0000000000..53bfa29a70
--- /dev/null
+++ b/dts/src/mips/img/boston.dts
@@ -0,0 +1,224 @@
+/dts-v1/;
+
+#include <dt-bindings/clock/boston-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "img,boston";
+
+ chosen {
+ stdout-path = "uart0:115200";
+ };
+
+ aliases {
+ uart0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "img,mips";
+ reg = <0>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ pci0: pci@10000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x10000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x40000000
+ 0x40000000 0 0x40000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci0_intc 1>,
+ <0 0 0 2 &pci0_intc 2>,
+ <0 0 0 3 &pci0_intc 3>,
+ <0 0 0 4 &pci0_intc 4>;
+
+ pci0_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci1: pci@12000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x12000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x20000000
+ 0x20000000 0 0x20000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci1_intc 1>,
+ <0 0 0 2 &pci1_intc 2>,
+ <0 0 0 3 &pci1_intc 3>,
+ <0 0 0 4 &pci1_intc 4>;
+
+ pci1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci2: pci@14000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x14000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x16000000
+ 0x16000000 0 0x100000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci2_intc 1>,
+ <0 0 0 2 &pci2_intc 2>,
+ <0 0 0 3 &pci2_intc 3>,
+ <0 0 0 4 &pci2_intc 4>;
+
+ pci2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ pci2_root@0,0,0 {
+ compatible = "pci10ee,7021";
+ reg = <0x00000000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_bridge@1,0,0 {
+ compatible = "pci8086,8800";
+ reg = <0x00010000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_mac@2,0,1 {
+ compatible = "pci8086,8802";
+ reg = <0x00020100 0 0 0 0>;
+ phy-reset-gpios = <&eg20t_gpio 6
+ GPIO_ACTIVE_LOW>;
+ };
+
+ eg20t_gpio: eg20t_gpio@2,0,2 {
+ compatible = "pci8086,8803";
+ reg = <0x00020200 0 0 0 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eg20t_i2c@2,12,2 {
+ compatible = "pci8086,8817";
+ reg = <0x00026200 0 0 0 0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@0x68 {
+ compatible = "st,m41t81s";
+ reg = <0x68>;
+ };
+ };
+ };
+ };
+ };
+
+ gic: interrupt-controller@16120000 {
+ compatible = "mti,gic";
+ reg = <0x16120000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ cdmm@16140000 {
+ compatible = "mti,mips-cdmm";
+ reg = <0x16140000 0x8000>;
+ };
+
+ cpc@16200000 {
+ compatible = "mti,mips-cpc";
+ reg = <0x16200000 0x8000>;
+ };
+
+ plat_regs: system-controller@17ffd000 {
+ compatible = "img,boston-platform-regs", "syscon";
+ reg = <0x17ffd000 0x1000>;
+
+ clk_boston: clock {
+ compatible = "img,boston-clock";
+ #clock-cells = <1>;
+ };
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&plat_regs>;
+ offset = <0x10>;
+ mask = <0x10>;
+ };
+
+ uart0: uart@17ffe000 {
+ compatible = "ns16550a";
+ reg = <0x17ffe000 0x1000>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clk_boston BOSTON_CLK_SYS>;
+ };
+
+ lcd: lcd@17fff000 {
+ compatible = "img,boston-lcd";
+ reg = <0x17fff000 0x8>;
+ };
+};
diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts
index 1652d8d60b..fd138d9978 100644
--- a/dts/src/mips/ingenic/ci20.dts
+++ b/dts/src/mips/ingenic/ci20.dts
@@ -29,18 +29,30 @@
&uart0 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
};
&uart1 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart1>;
};
&uart3 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2>;
};
&uart4 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart4>;
};
&nemc {
@@ -61,6 +73,13 @@
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
+ /*
+ * Only CLE/ALE are needed for the devices that are connected, rather
+ * than the full address line set.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
nand@1 {
reg = <1>;
@@ -69,6 +88,9 @@
nand-ecc-mode = "hw";
nand-on-flash-bbt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
@@ -106,3 +128,41 @@
&bch {
status = "okay";
};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+
+ pins_uart1: uart1 {
+ function = "uart1";
+ groups = "uart1-data";
+ bias-disable;
+ };
+
+ pins_uart2: uart2 {
+ function = "uart2";
+ groups = "uart2-data", "uart2-hwflow";
+ bias-disable;
+ };
+
+ pins_uart4: uart4 {
+ function = "uart4";
+ groups = "uart4-data";
+ bias-disable;
+ };
+
+ pins_nemc: nemc {
+ function = "nemc";
+ groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
+ bias-disable;
+ };
+
+ pins_nemc_cs1: nemc-cs1 {
+ function = "nemc-cs1";
+ groups = "nemc-cs1";
+ bias-disable;
+ };
+};
diff --git a/dts/src/mips/ingenic/jz4740.dtsi b/dts/src/mips/ingenic/jz4740.dtsi
index 3e1587f1f7..2ca7ce7481 100644
--- a/dts/src/mips/ingenic/jz4740.dtsi
+++ b/dts/src/mips/ingenic/jz4740.dtsi
@@ -55,6 +55,74 @@
clock-names = "rtc";
};
+ pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <26>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <25>;
+ };
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
diff --git a/dts/src/mips/ingenic/jz4780.dtsi b/dts/src/mips/ingenic/jz4780.dtsi
index b868b429ad..4853ef67b3 100644
--- a/dts/src/mips/ingenic/jz4780.dtsi
+++ b/dts/src/mips/ingenic/jz4780.dtsi
@@ -44,6 +44,104 @@
#clock-cells = <1>;
};
+ pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4780-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+ };
+
+ gpe: gpio@4 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <4>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <13>;
+ };
+
+ gpf: gpio@5 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <5>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+ };
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;
diff --git a/dts/src/mips/ingenic/qi_lb60.dts b/dts/src/mips/ingenic/qi_lb60.dts
index be1a7d3a3e..b715ee2ac2 100644
--- a/dts/src/mips/ingenic/qi_lb60.dts
+++ b/dts/src/mips/ingenic/qi_lb60.dts
@@ -17,3 +17,16 @@
&rtc_dev {
system-power-controller;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
+};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+};
diff --git a/dts/src/mips/mti/sead3.dts b/dts/src/mips/mti/sead3.dts
index b112879a5d..4f8bc83c29 100644
--- a/dts/src/mips/mti/sead3.dts
+++ b/dts/src/mips/mti/sead3.dts
@@ -11,15 +11,14 @@
#size-cells = <1>;
compatible = "mti,sead-3";
model = "MIPS SEAD-3";
- interrupt-parent = <&gic>;
chosen {
- stdout-path = "uart1:115200";
+ stdout-path = "serial1:115200";
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
+ serial0 = &uart0;
+ serial1 = &uart1;
};
cpus {
@@ -54,18 +53,14 @@
* controller & should be probed first.
*/
interrupt-parent = <&cpu_intc>;
-
- timer {
- compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- };
};
ehci@1b200000 {
compatible = "generic-ehci";
reg = <0x1b200000 0x1000>;
- interrupts = <0>; /* GIC 0 or CPU 6 */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
has-transaction-translator;
};
@@ -227,7 +222,8 @@
clock-frequency = <14745600>;
- interrupts = <3>; /* GIC 3 or CPU 4 */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
no-loopback-test;
};
@@ -241,7 +237,8 @@
clock-frequency = <14745600>;
- interrupts = <2>; /* GIC 2 or CPU 4 */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
no-loopback-test;
};
@@ -251,7 +248,8 @@
reg = <0x1f010000 0x10000>;
reg-io-width = <4>;
- interrupts = <0>; /* GIC 0 or CPU 6 */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
phy-mode = "mii";
smsc,irq-push-pull;
diff --git a/dts/src/powerpc/ac14xx.dts b/dts/src/powerpc/ac14xx.dts
index 27fcabc2f8..83bcfd8651 100644
--- a/dts/src/powerpc/ac14xx.dts
+++ b/dts/src/powerpc/ac14xx.dts
@@ -10,7 +10,7 @@
*/
-#include <mpc5121.dtsi>
+#include "mpc5121.dtsi"
/ {
model = "ac14xx";
diff --git a/dts/src/powerpc/digsy_mtc.dts b/dts/src/powerpc/digsy_mtc.dts
index 955bff629d..c280e75c86 100644
--- a/dts/src/powerpc/digsy_mtc.dts
+++ b/dts/src/powerpc/digsy_mtc.dts
@@ -73,7 +73,7 @@
i2c@3d00 {
eeprom@50 {
- compatible = "at,24c08";
+ compatible = "atmel,24c08";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/fsl/b4qds.dtsi b/dts/src/powerpc/fsl/b4qds.dtsi
index 3785ef826d..999efd3bc1 100644
--- a/dts/src/powerpc/fsl/b4qds.dtsi
+++ b/dts/src/powerpc/fsl/b4qds.dtsi
@@ -166,19 +166,19 @@
reg = <0>;
eeprom@50 {
- compatible = "at24,24c64";
+ compatible = "atmel,24c64";
reg = <0x50>;
};
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@53 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x53>;
};
eeprom@57 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x57>;
};
rtc@68 {
diff --git a/dts/src/powerpc/fsl/c293pcie.dts b/dts/src/powerpc/fsl/c293pcie.dts
index 6670978842..5e905e0857 100644
--- a/dts/src/powerpc/fsl/c293pcie.dts
+++ b/dts/src/powerpc/fsl/c293pcie.dts
@@ -153,7 +153,7 @@
&soc {
i2c@3000 {
eeprom@50 {
- compatible = "st,24c1024";
+ compatible = "st,24c1024", "atmel,24c1024";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/fsl/kmcent2.dts b/dts/src/powerpc/fsl/kmcent2.dts
index 47afa43860..5922c1ea0e 100644
--- a/dts/src/powerpc/fsl/kmcent2.dts
+++ b/dts/src/powerpc/fsl/kmcent2.dts
@@ -293,9 +293,7 @@
compatible = "fsl,ucc-hdlc";
rx-clock-name = "clk9";
tx-clock-name = "clk9";
- fsl,tx-timeslot-mask = <0xfffffffe>;
- fsl,rx-timeslot-mask = <0xfffffffe>;
- fsl,siram-entry-id = <0>;
+ fsl,hdlc-bus;
};
};
};
diff --git a/dts/src/powerpc/fsl/p1010rdb.dtsi b/dts/src/powerpc/fsl/p1010rdb.dtsi
index a8e4ba0701..2ca9cee2dd 100644
--- a/dts/src/powerpc/fsl/p1010rdb.dtsi
+++ b/dts/src/powerpc/fsl/p1010rdb.dtsi
@@ -89,7 +89,7 @@
&board_soc {
i2c@3000 {
eeprom@50 {
- compatible = "st,24c256";
+ compatible = "st,24c256", "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/fsl/p1023rdb.dts b/dts/src/powerpc/fsl/p1023rdb.dts
index 9716ca6465..ead928364b 100644
--- a/dts/src/powerpc/fsl/p1023rdb.dts
+++ b/dts/src/powerpc/fsl/p1023rdb.dts
@@ -79,7 +79,7 @@
i2c@3000 {
eeprom@53 {
- compatible = "at24,24c04";
+ compatible = "atmel,24c04";
reg = <0x53>;
};
diff --git a/dts/src/powerpc/fsl/p2041rdb.dts b/dts/src/powerpc/fsl/p2041rdb.dts
index e50fea95a8..950816b9d6 100644
--- a/dts/src/powerpc/fsl/p2041rdb.dts
+++ b/dts/src/powerpc/fsl/p2041rdb.dts
@@ -127,7 +127,7 @@
reg = <0x48>;
};
eeprom@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
rtc@68 {
@@ -142,7 +142,7 @@
i2c@118100 {
eeprom@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
};
diff --git a/dts/src/powerpc/fsl/p3041ds.dts b/dts/src/powerpc/fsl/p3041ds.dts
index 40748e415a..6f5f7283c5 100644
--- a/dts/src/powerpc/fsl/p3041ds.dts
+++ b/dts/src/powerpc/fsl/p3041ds.dts
@@ -124,11 +124,11 @@
i2c@118100 {
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
};
diff --git a/dts/src/powerpc/fsl/p4080ds.dts b/dts/src/powerpc/fsl/p4080ds.dts
index 816b9788d5..65e20152e2 100644
--- a/dts/src/powerpc/fsl/p4080ds.dts
+++ b/dts/src/powerpc/fsl/p4080ds.dts
@@ -125,11 +125,11 @@
i2c@118100 {
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
rtc@68 {
diff --git a/dts/src/powerpc/fsl/p5020ds.dts b/dts/src/powerpc/fsl/p5020ds.dts
index cd6f373861..b24adf902d 100644
--- a/dts/src/powerpc/fsl/p5020ds.dts
+++ b/dts/src/powerpc/fsl/p5020ds.dts
@@ -124,11 +124,11 @@
i2c@118100 {
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
};
diff --git a/dts/src/powerpc/fsl/p5040ds.dts b/dts/src/powerpc/fsl/p5040ds.dts
index 45084738cf..30850b3228 100644
--- a/dts/src/powerpc/fsl/p5040ds.dts
+++ b/dts/src/powerpc/fsl/p5040ds.dts
@@ -133,11 +133,11 @@
i2c@118100 {
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
};
diff --git a/dts/src/powerpc/fsl/t208xqds.dtsi b/dts/src/powerpc/fsl/t208xqds.dtsi
index ec080bd01b..db4139999b 100644
--- a/dts/src/powerpc/fsl/t208xqds.dtsi
+++ b/dts/src/powerpc/fsl/t208xqds.dtsi
@@ -147,17 +147,17 @@
reg = <0x0>;
eeprom@50 {
- compatible = "at24,24c512";
+ compatible = "atmel,24c512";
reg = <0x50>;
};
eeprom@51 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
reg = <0x51>;
};
eeprom@57 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
reg = <0x57>;
};
@@ -174,7 +174,7 @@
reg = <0x1>;
eeprom@55 {
- compatible = "at24,24c02";
+ compatible = "atmel,24c02";
reg = <0x55>;
};
};
diff --git a/dts/src/powerpc/fsl/t4240qds.dts b/dts/src/powerpc/fsl/t4240qds.dts
index 9573ceada0..c0913ac5aa 100644
--- a/dts/src/powerpc/fsl/t4240qds.dts
+++ b/dts/src/powerpc/fsl/t4240qds.dts
@@ -377,27 +377,27 @@
reg = <0>;
eeprom@51 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x51>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
eeprom@53 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x53>;
};
eeprom@54 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x54>;
};
eeprom@55 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x55>;
};
eeprom@56 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x56>;
};
rtc@68 {
diff --git a/dts/src/powerpc/fsl/t4240rdb.dts b/dts/src/powerpc/fsl/t4240rdb.dts
index 8166c66071..15eb0a3f72 100644
--- a/dts/src/powerpc/fsl/t4240rdb.dts
+++ b/dts/src/powerpc/fsl/t4240rdb.dts
@@ -130,15 +130,15 @@
reg = <0x2f>;
};
eeprom@52 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x52>;
};
eeprom@54 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x54>;
};
eeprom@56 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x56>;
};
rtc@68 {
diff --git a/dts/src/powerpc/fsp2.dts b/dts/src/powerpc/fsp2.dts
new file mode 100644
index 0000000000..475953ada7
--- /dev/null
+++ b/dts/src/powerpc/fsp2.dts
@@ -0,0 +1,608 @@
+/*
+ * Device Tree Source for FSP2
+ *
+ * Copyright 2010,2012 IBM Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,fsp2";
+ compatible = "ibm,fsp2";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC, 476FSP2";
+ reg = <0x0>;
+ clock-frequency = <0>; /* Filled in by cuboot */
+ timebase-frequency = <0>; /* Filled in by cuboot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by
+ cuboot */
+ };
+
+ clocks {
+ mmc_clk: mmc_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "mmc_clk";
+ };
+ };
+
+ UIC0: uic0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x2c0 0x8>;
+ };
+
+ /* "interrupts" field is <bit level bit level>
+ first pair is non-critical, second is critical */
+ UIC1_0: uic1_0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x2c8 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <21 0x4 4 0x84>;
+ };
+
+ /* PSI and DMA */
+ UIC1_1: uic1_1 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x350 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <22 0x4 5 0x84>;
+ };
+
+ /* Ethernet and USB */
+ UIC1_2: uic1_2 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x358 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <23 0x4 6 0x84>;
+ };
+
+ /* PLB Errors */
+ UIC1_3: uic1_3 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <4>;
+ dcr-reg = <0x360 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <24 0x4 7 0x84>;
+ };
+
+ UIC1_4: uic1_4 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <5>;
+ dcr-reg = <0x368 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <25 0x4 8 0x84>;
+ };
+
+ UIC1_5: uic1_5 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <6>;
+ dcr-reg = <0x370 0x8>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <26 0x4 9 0x84>;
+ };
+
+ /* 2nd level UICs for FSI */
+ UIC2_0: uic2_0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <7>;
+ dcr-reg = <0x2d0 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <16 0x4 0 0x84>;
+ };
+
+ UIC2_1: uic2_1 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <8>;
+ dcr-reg = <0x2d8 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <17 0x4 1 0x84>;
+ };
+
+ UIC2_2: uic2_2 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <9>;
+ dcr-reg = <0x2e0 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <18 0x4 2 0x84>;
+ };
+
+ UIC2_3: uic2_3 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <10>;
+ dcr-reg = <0x2e8 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <19 0x4 3 0x84>;
+ };
+
+ UIC2_4: uic2_4 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <11>;
+ dcr-reg = <0x2f0 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <20 0x4 4 0x84>;
+ };
+
+ UIC2_5: uic2_5 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <12>;
+ dcr-reg = <0x2f8 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <21 0x4 5 0x84>;
+ };
+
+ UIC2_6: uic2_6 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <13>;
+ dcr-reg = <0x300 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <22 0x4 6 0x84>;
+ };
+
+ UIC2_7: uic2_7 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <14>;
+ dcr-reg = <0x308 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <23 0x4 7 0x84>;
+ };
+
+ UIC2_8: uic2_8 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <15>;
+ dcr-reg = <0x310 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <24 0x4 8 0x84>;
+ };
+
+ UIC2_9: uic2_9 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <16>;
+ dcr-reg = <0x318 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <25 0x4 9 0x84>;
+ };
+
+ UIC2_10: uic2_10 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <17>;
+ dcr-reg = <0x320 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <26 0x4 10 0x84>;
+ };
+
+ UIC2_11: uic2_11 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <18>;
+ dcr-reg = <0x328 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <27 0x4 11 0x84>;
+ };
+
+ UIC2_12: uic2_12 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <19>;
+ dcr-reg = <0x330 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <28 0x4 12 0x84>;
+ };
+
+ UIC2_13: uic2_13 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <20>;
+ dcr-reg = <0x338 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <29 0x4 13 0x84>;
+ };
+
+ UIC2_14: uic2_14 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <21>;
+ dcr-reg = <0x340 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <30 0x4 14 0x84>;
+ };
+
+ UIC2_15: uic2_15 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <22>;
+ dcr-reg = <0x348 0x8>;
+ interrupt-parent = <&UIC1_0>;
+ interrupts = <31 0x4 15 0x84>;
+ };
+
+ mmc0: sdhci@020c0000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ status = "disabled";
+ reg = <0x020c0000 0x20000>;
+ reg-names = "mmc";
+ interrupt-parent = <&UIC1_3>;
+ interrupts = <21 0x4 22 0x4>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ clock-names = "mmc";
+ clocks = <&mmc_clk>;
+ };
+
+ plb6 {
+ compatible = "ibm,plb6";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ MCW0: memory-controller-wrapper {
+ compatible = "ibm,cw-476fsp2";
+ dcr-reg = <0x11111800 0x40>;
+ };
+
+ MCIF0: memory-controller {
+ compatible = "ibm,sdram-476fsp2", "ibm,sdram-4xx-ddr3";
+ dcr-reg = <0x11120000 0x10000>;
+ mcer-device = <&MCW0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <10 0x84 /* ECC UE */
+ 11 0x84>; /* ECC CE */
+ };
+ };
+
+ plb4 {
+ compatible = "ibm,plb4";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000010 0x00000000 0x80000000
+ 0x80000000 0x00000010 0x80000000 0x80000000>;
+ clock-frequency = <333333334>;
+
+ plb6-system-hung-irq {
+ compatible = "ibm,bus-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 0x84>;
+ };
+
+ l2-error-irq {
+ compatible = "ibm,bus-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <20 0x84>;
+ };
+
+ plb6-plb4-irq {
+ compatible = "ibm,bus-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 0x84>;
+ };
+
+ plb4-ahb-irq {
+ compatible = "ibm,bus-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC1_3>;
+ interrupts = <20 0x84>;
+ };
+
+ opbd-error-irq {
+ compatible = "ibm,opbd-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC1_4>;
+ interrupts = <5 0x84>;
+ };
+
+ cmu-error-irq {
+ compatible = "ibm,cmu-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <28 0x84>;
+ };
+
+ conf-error-irq {
+ compatible = "ibm,conf-error-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC1_4>;
+ interrupts = <11 0x84>;
+ };
+
+ mc-ue-irq {
+ compatible = "ibm,mc-ue-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <10 0x84>;
+ };
+
+ reset-warning-irq {
+ compatible = "ibm,reset-warning-irq";
+ #interrupt-cells = <2>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <17 0x84>;
+ };
+
+ MAL0: mcmal0 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ compatible = "ibm,mcmal";
+ dcr-reg = <0x80 0x80>;
+ num-tx-chans = <1>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ /* index interrupt-parent interrupt# type */
+ interrupt-map = </*TXEOB*/ 0 &UIC1_2 4 0x4
+ /*RXEOB*/ 1 &UIC1_2 3 0x4
+ /*SERR*/ 2 &UIC1_2 7 0x4
+ /*TXDE*/ 3 &UIC1_2 6 0x4
+ /*RXDE*/ 4 &UIC1_2 5 0x4>;
+ };
+
+ MAL1: mcmal1 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ compatible = "ibm,mcmal";
+ dcr-reg = <0x100 0x80>;
+ num-tx-chans = <1>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&MAL1>;
+ interrupts = <0 1 2 3 4>;
+ /* index interrupt-parent interrupt# type */
+ interrupt-map = </*TXEOB*/ 0 &UIC1_2 12 0x4
+ /*RXEOB*/ 1 &UIC1_2 11 0x4
+ /*SERR*/ 2 &UIC1_2 15 0x4
+ /*TXDE*/ 3 &UIC1_2 14 0x4
+ /*RXDE*/ 4 &UIC1_2 13 0x4>;
+ };
+
+ opb {
+ compatible = "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges; // pass-thru to parent bus
+ clock-frequency = <83333334>;
+
+ EMAC0: ethernet@b0000000 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac4sync";
+ has-inverted-stacr-oc;
+ interrupt-parent = <&UIC1_2>;
+ interrupts = <1 0x4 0 0x4>;
+ reg = <0xb0000000 0x100>;
+ local-mac-address = [000000000000]; /* Filled in by
+ cuboot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <1500>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <4096>;
+ rx-fifo-size-gige = <16384>;
+ tx-fifo-size-gige = <8192>;
+ phy-address = <1>;
+ phy-mode = "rgmii";
+ phy-map = <00000003>;
+ rgmii-device = <&RGMII>;
+ rgmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@b0000100 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac4sync";
+ has-inverted-stacr-oc;
+ interrupt-parent = <&UIC1_2>;
+ interrupts = <9 0x4 8 0x4>;
+ reg = <0xb0000100 0x100>;
+ local-mac-address = [000000000000]; /* Filled in by
+ cuboot */
+ mal-device = <&MAL1>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <1>;
+ max-frame-size = <1500>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <4096>;
+ rx-fifo-size-gige = <16384>;
+ tx-fifo-size-gige = <8192>;
+ phy-address = <2>;
+ phy-mode = "rgmii";
+ phy-map = <00000003>;
+ rgmii-device = <&RGMII>;
+ rgmii-channel = <1>;
+ };
+
+ RGMII: rgmii@b0000600 {
+ compatible = "ibm,rgmii";
+ has-mdio;
+ reg = <0xb0000600 0x8>;
+ };
+
+ UART0: serial@b0020000 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0xb0020000 0x8>;
+ virtual-reg = <0xb0020000>;
+ clock-frequency = <20833333>;
+ current-speed = <115200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <31 0x4>;
+ };
+ };
+
+ OHCI1: ohci@02040000 {
+ compatible = "ohci-le";
+ reg = <0x02040000 0xa0>;
+ interrupt-parent = <&UIC1_3>;
+ interrupts = <28 0x8 29 0x8>;
+ };
+
+ OHCI2: ohci@02080000 {
+ compatible = "ohci-le";
+ reg = <0x02080000 0xa0>;
+ interrupt-parent = <&UIC1_3>;
+ interrupts = <30 0x8 31 0x8>;
+ };
+
+ EHCI: ehci@02000000 {
+ compatible = "usb-ehci";
+ reg = <0x02000000 0xa4>;
+ interrupt-parent = <&UIC1_3>;
+ interrupts = <23 0x4>;
+ };
+
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@b0020000";
+ bootargs = "console=ttyS0,115200 rw log_buf_len=32768 debug";
+ };
+};
diff --git a/dts/src/powerpc/mpc5121ads.dts b/dts/src/powerpc/mpc5121ads.dts
index 75888ce2c7..1e81a7e32d 100644
--- a/dts/src/powerpc/mpc5121ads.dts
+++ b/dts/src/powerpc/mpc5121ads.dts
@@ -9,7 +9,7 @@
* option) any later version.
*/
-#include <mpc5121.dtsi>
+#include "mpc5121.dtsi"
/ {
model = "mpc5121ads";
@@ -94,7 +94,7 @@
};
eeprom@50 {
- compatible = "at,24c32";
+ compatible = "atmel,24c32";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/mpc8308_p1m.dts b/dts/src/powerpc/mpc8308_p1m.dts
index 57f86cdf9f..cab933b395 100644
--- a/dts/src/powerpc/mpc8308_p1m.dts
+++ b/dts/src/powerpc/mpc8308_p1m.dts
@@ -123,7 +123,7 @@
interrupt-parent = <&ipic>;
dfsrr;
fram@50 {
- compatible = "ramtron,24c64";
+ compatible = "ramtron,24c64", "atmel,24c64";
reg = <0x50>;
};
};
diff --git a/dts/src/powerpc/mpc8349emitx.dts b/dts/src/powerpc/mpc8349emitx.dts
index 90aed3ac2f..648a85858e 100644
--- a/dts/src/powerpc/mpc8349emitx.dts
+++ b/dts/src/powerpc/mpc8349emitx.dts
@@ -92,7 +92,7 @@
dfsrr;
eeprom: at24@50 {
- compatible = "st,24c256";
+ compatible = "st,24c256", "atmel,24c256";
reg = <0x50>;
};
@@ -130,7 +130,7 @@
};
spd: at24@51 {
- compatible = "at24,spd";
+ compatible = "atmel,spd";
reg = <0x51>;
};
diff --git a/dts/src/powerpc/mpc8377_rdb.dts b/dts/src/powerpc/mpc8377_rdb.dts
index e32613963a..5e85d8c93b 100644
--- a/dts/src/powerpc/mpc8377_rdb.dts
+++ b/dts/src/powerpc/mpc8377_rdb.dts
@@ -150,7 +150,7 @@
};
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/mpc8377_wlan.dts b/dts/src/powerpc/mpc8377_wlan.dts
index c0c790168b..fee15fcbb4 100644
--- a/dts/src/powerpc/mpc8377_wlan.dts
+++ b/dts/src/powerpc/mpc8377_wlan.dts
@@ -135,7 +135,7 @@
dfsrr;
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/mpc8378_rdb.dts b/dts/src/powerpc/mpc8378_rdb.dts
index 71842fcd62..e973d61956 100644
--- a/dts/src/powerpc/mpc8378_rdb.dts
+++ b/dts/src/powerpc/mpc8378_rdb.dts
@@ -150,7 +150,7 @@
};
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/mpc8379_rdb.dts b/dts/src/powerpc/mpc8379_rdb.dts
index e442a29b2f..ed5d12ff2e 100644
--- a/dts/src/powerpc/mpc8379_rdb.dts
+++ b/dts/src/powerpc/mpc8379_rdb.dts
@@ -148,7 +148,7 @@
};
at24@50 {
- compatible = "at24,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
};
diff --git a/dts/src/powerpc/pcm030.dts b/dts/src/powerpc/pcm030.dts
index 192e66af00..836e47cc4b 100644
--- a/dts/src/powerpc/pcm030.dts
+++ b/dts/src/powerpc/pcm030.dts
@@ -71,7 +71,7 @@
reg = <0x51>;
};
eeprom@52 {
- compatible = "catalyst,24c32";
+ compatible = "catalyst,24c32", "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
diff --git a/dts/src/powerpc/pcm032.dts b/dts/src/powerpc/pcm032.dts
index 96b139bf50..576249bf2f 100644
--- a/dts/src/powerpc/pcm032.dts
+++ b/dts/src/powerpc/pcm032.dts
@@ -75,7 +75,7 @@
reg = <0x51>;
};
eeprom@52 {
- compatible = "catalyst,24c32";
+ compatible = "catalyst,24c32", "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
diff --git a/dts/src/powerpc/pdm360ng.dts b/dts/src/powerpc/pdm360ng.dts
index 0cec7244ab..445b881140 100644
--- a/dts/src/powerpc/pdm360ng.dts
+++ b/dts/src/powerpc/pdm360ng.dts
@@ -13,7 +13,7 @@
* option) any later version.
*/
-#include <mpc5121.dtsi>
+#include "mpc5121.dtsi"
/ {
model = "pdm360ng";
diff --git a/dts/src/powerpc/sequoia.dts b/dts/src/powerpc/sequoia.dts
index b1d329246b..e41b88a5ea 100644
--- a/dts/src/powerpc/sequoia.dts
+++ b/dts/src/powerpc/sequoia.dts
@@ -229,7 +229,7 @@
};
partition@84000 {
label = "user";
- reg = <0x00000000 0x01f7c000>;
+ reg = <0x00084000 0x01f7c000>;
};
};
};
diff --git a/dts/src/powerpc/warp.dts b/dts/src/powerpc/warp.dts
index e576ee85c4..ea9053ef48 100644
--- a/dts/src/powerpc/warp.dts
+++ b/dts/src/powerpc/warp.dts
@@ -238,7 +238,7 @@
/* This will create 52 and 53 */
at24@52 {
- compatible = "at,24c04";
+ compatible = "atmel,24c04";
reg = <0x52>;
};
};