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authorSascha Hauer <s.hauer@pengutronix.de>2022-06-08 09:15:32 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-06-08 10:41:39 +0200
commite54923b76e345080b73f3ae7f508657e5c63a9eb (patch)
tree8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts
parentd4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff)
downloadbarebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz
barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/arm/arm,corstone1000.yaml45
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4708.yaml10
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm63138.txt2
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcmbca.yaml33
-rw-r--r--dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt19
-rw-r--r--dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt19
-rw-r--r--dts/Bindings/arm/fsl.yaml119
-rw-r--r--dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml5
-rw-r--r--dts/Bindings/arm/hpe,gxp.yaml27
-rw-r--r--dts/Bindings/arm/intel,socfpga.yaml1
-rw-r--r--dts/Bindings/arm/mediatek.yaml5
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt35
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,infracfg.txt42
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,infracfg.yaml81
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.yaml32
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml42
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml50
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml56
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml54
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,pericfg.yaml1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,topckgen.txt35
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.yaml2
-rw-r--r--dts/Bindings/arm/omap/prcm.txt7
-rw-r--r--dts/Bindings/arm/qcom.yaml21
-rw-r--r--dts/Bindings/arm/renesas.yaml20
-rw-r--r--dts/Bindings/arm/rockchip.yaml23
-rw-r--r--dts/Bindings/arm/sp810.txt46
-rw-r--r--dts/Bindings/arm/sp810.yaml80
-rw-r--r--dts/Bindings/arm/spe-pmu.txt20
-rw-r--r--dts/Bindings/arm/stm32/stm32.yaml63
-rw-r--r--dts/Bindings/arm/sunxi.yaml5
-rw-r--r--dts/Bindings/arm/syna.txt4
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml52
-rw-r--r--dts/Bindings/arm/ux500.yaml5
-rw-r--r--dts/Bindings/arm/vexpress-config.yaml285
-rw-r--r--dts/Bindings/arm/vexpress-sysreg.txt103
-rw-r--r--dts/Bindings/arm/vexpress-sysreg.yaml90
-rw-r--r--dts/Bindings/ata/renesas,rcar-sata.yaml1
-rw-r--r--dts/Bindings/bus/qcom,ssc-block-bus.yaml147
-rw-r--r--dts/Bindings/clock/airoha,en7523-scu.yaml58
-rw-r--r--dts/Bindings/clock/clock-bindings.txt188
-rw-r--r--dts/Bindings/clock/mediatek,apmixedsys.yaml61
-rw-r--r--dts/Bindings/clock/mediatek,topckgen.yaml61
-rw-r--r--dts/Bindings/clock/qcom,gcc-apq8064.yaml4
-rw-r--r--dts/Bindings/clock/qcom,gcc-apq8084.yaml42
-rw-r--r--dts/Bindings/clock/qcom,gcc-sc8280xp.yaml128
-rw-r--r--dts/Bindings/clock/qcom,mmcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,rpmcc.txt63
-rw-r--r--dts/Bindings/clock/qcom,rpmcc.yaml75
-rw-r--r--dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml172
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.yaml1
-rw-r--r--dts/Bindings/clock/renesas,h8300-div-clock.txt24
-rw-r--r--dts/Bindings/clock/renesas,h8s2678-pll-clock.txt23
-rw-r--r--dts/Bindings/clock/renesas,r9a06g032-sysctrl.yaml11
-rw-r--r--dts/Bindings/clock/renesas,rzg2l-cpg.yaml20
-rw-r--r--dts/Bindings/clock/rockchip,px30-cru.txt70
-rw-r--r--dts/Bindings/clock/rockchip,px30-cru.yaml119
-rw-r--r--dts/Bindings/clock/rockchip,rk3036-cru.txt56
-rw-r--r--dts/Bindings/clock/rockchip,rk3036-cru.yaml72
-rw-r--r--dts/Bindings/clock/rockchip,rk3188-cru.txt61
-rw-r--r--dts/Bindings/clock/rockchip,rk3188-cru.yaml78
-rw-r--r--dts/Bindings/clock/rockchip,rk3228-cru.txt58
-rw-r--r--dts/Bindings/clock/rockchip,rk3228-cru.yaml74
-rw-r--r--dts/Bindings/clock/rockchip,rk3288-cru.txt67
-rw-r--r--dts/Bindings/clock/rockchip,rk3288-cru.yaml85
-rw-r--r--dts/Bindings/clock/rockchip,rk3308-cru.txt60
-rw-r--r--dts/Bindings/clock/rockchip,rk3308-cru.yaml76
-rw-r--r--dts/Bindings/clock/rockchip,rk3368-cru.txt61
-rw-r--r--dts/Bindings/clock/rockchip,rk3368-cru.yaml78
-rw-r--r--dts/Bindings/clock/rockchip,rk3399-cru.yaml33
-rw-r--r--dts/Bindings/clock/rockchip,rk3568-cru.yaml13
-rw-r--r--dts/Bindings/clock/rockchip,rv1108-cru.txt59
-rw-r--r--dts/Bindings/clock/rockchip,rv1108-cru.yaml75
-rw-r--r--dts/Bindings/clock/samsung,exynos4412-isp-clock.yaml1
-rw-r--r--dts/Bindings/clock/samsung,exynosautov9-clock.yaml219
-rw-r--r--dts/Bindings/clock/st,stm32mp1-rcc.yaml43
-rw-r--r--dts/Bindings/clock/stericsson,u8500-clks.yaml57
-rw-r--r--dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml1
-rw-r--r--dts/Bindings/clock/ti-clkctrl.txt4
-rw-r--r--dts/Bindings/clock/ti/clockdomain.txt3
-rw-r--r--dts/Bindings/clock/ti/composite.txt3
-rw-r--r--dts/Bindings/clock/ti/fixed-factor-clock.txt1
-rw-r--r--dts/Bindings/clock/ti/gate.txt1
-rw-r--r--dts/Bindings/clock/ti/interface.txt1
-rw-r--r--dts/Bindings/clock/ti/mux.txt1
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt7
-rw-r--r--dts/Bindings/crypto/allwinner,sun8i-ce.yaml1
-rw-r--r--dts/Bindings/crypto/ti,sa2ul.yaml1
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt212
-rw-r--r--dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml1
-rw-r--r--dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml2
-rw-r--r--dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml2
-rw-r--r--dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml133
-rw-r--r--dts/Bindings/display/amlogic,meson-dw-hdmi.yaml1
-rw-r--r--dts/Bindings/display/arm,hdlcd.txt79
-rw-r--r--dts/Bindings/display/arm,hdlcd.yaml89
-rw-r--r--dts/Bindings/display/arm,komeda.txt78
-rw-r--r--dts/Bindings/display/arm,komeda.yaml130
-rw-r--r--dts/Bindings/display/arm,malidp.txt68
-rw-r--r--dts/Bindings/display/arm,malidp.yaml124
-rw-r--r--dts/Bindings/display/arm,pl11x.txt110
-rw-r--r--dts/Bindings/display/arm,pl11x.yaml183
-rw-r--r--dts/Bindings/display/bridge/chipone,icn6211.yaml18
-rw-r--r--dts/Bindings/display/bridge/fsl,ldb.yaml92
-rw-r--r--dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml1
-rw-r--r--dts/Bindings/display/bridge/ite,it66121.yaml3
-rw-r--r--dts/Bindings/display/bridge/lontium,lt9211.yaml117
-rw-r--r--dts/Bindings/display/bridge/ps8640.yaml1
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358767.yaml22
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358768.yaml1
-rw-r--r--dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml1
-rw-r--r--dts/Bindings/display/mediatek/mediatek,aal.yaml11
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ccorr.yaml5
-rw-r--r--dts/Bindings/display/mediatek/mediatek,color.yaml7
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dither.yaml4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.yaml1
-rw-r--r--dts/Bindings/display/mediatek/mediatek,gamma.yaml4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,merge.yaml1
-rw-r--r--dts/Bindings/display/mediatek/mediatek,mutex.yaml25
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,ovl.yaml8
-rw-r--r--dts/Bindings/display/mediatek/mediatek,postmask.yaml4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,rdma.yaml7
-rw-r--r--dts/Bindings/display/msm/dpu-qcm2290.yaml4
-rw-r--r--dts/Bindings/display/msm/dpu-sc7180.yaml4
-rw-r--r--dts/Bindings/display/msm/dpu-sc7280.yaml4
-rw-r--r--dts/Bindings/display/msm/dpu-sdm845.yaml4
-rw-r--r--dts/Bindings/display/panel/ilitek,ili9341.yaml1
-rw-r--r--dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml59
-rw-r--r--dts/Bindings/display/panel/orisetech,otm8009a.yaml1
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml4
-rw-r--r--dts/Bindings/display/panel/panel-timing.yaml5
-rw-r--r--dts/Bindings/display/panel/raydium,rm67191.yaml1
-rw-r--r--dts/Bindings/display/panel/samsung,s6e8aa0.yaml1
-rw-r--r--dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml46
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop2.yaml146
-rw-r--r--dts/Bindings/display/sitronix,st7735r.yaml6
-rw-r--r--dts/Bindings/display/solomon,ssd1307fb.yaml95
-rw-r--r--dts/Bindings/display/sprd/sprd,display-subsystem.yaml1
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.yaml1
-rw-r--r--dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml9
-rw-r--r--dts/Bindings/dma/altr,msgdma.yaml2
-rw-r--r--dts/Bindings/dma/arm,pl330.yaml3
-rw-r--r--dts/Bindings/dma/fsl-imx-dma.txt8
-rw-r--r--dts/Bindings/dma/mmp-dma.txt10
-rw-r--r--dts/Bindings/dma/nvidia,tegra186-gpc-dma.yaml110
-rw-r--r--dts/Bindings/dma/qcom,gpi.yaml3
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.yaml10
-rw-r--r--dts/Bindings/dma/renesas,rzn1-dmamux.yaml51
-rw-r--r--dts/Bindings/dma/sifive,fu540-c000-pdma.yaml19
-rw-r--r--dts/Bindings/dma/snps,dma-spear1340.yaml8
-rw-r--r--dts/Bindings/dma/sprd-dma.txt7
-rw-r--r--dts/Bindings/dma/st,stm32-dmamux.yaml1
-rw-r--r--dts/Bindings/dma/st,stm32-mdma.yaml1
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_dma.txt6
-rw-r--r--dts/Bindings/dsp/mediatek,mt8195-dsp.yaml105
-rw-r--r--dts/Bindings/eeprom/at24.txt1
-rw-r--r--dts/Bindings/eeprom/at24.yaml4
-rw-r--r--dts/Bindings/example-schema.yaml14
-rw-r--r--dts/Bindings/extcon/siliconmitus,sm5502-muic.yaml5
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt3
-rw-r--r--dts/Bindings/gnss/brcm,bcm4751.yaml69
-rw-r--r--dts/Bindings/gnss/mediatek.txt35
-rw-r--r--dts/Bindings/gnss/mediatek.yaml59
-rw-r--r--dts/Bindings/gpio/fairchild,74hc595.yaml1
-rw-r--r--dts/Bindings/gpio/gpio-altera.txt5
-rw-r--r--dts/Bindings/gpio/gpio-consumer-common.yaml64
-rw-r--r--dts/Bindings/gpio/gpio-pca95xx.yaml1
-rw-r--r--dts/Bindings/gpio/realtek,otto-gpio.yaml34
-rw-r--r--dts/Bindings/gpio/renesas,rcar-gpio.yaml5
-rw-r--r--dts/Bindings/gpio/socionext,uniphier-gpio.yaml17
-rw-r--r--dts/Bindings/gpu/samsung-rotator.yaml1
-rw-r--r--dts/Bindings/h8300/cpu.txt13
-rw-r--r--dts/Bindings/hwmon/adt7475.yaml23
-rw-r--r--dts/Bindings/hwmon/lm75.yaml1
-rw-r--r--dts/Bindings/hwmon/microchip,lan966x.yaml53
-rw-r--r--dts/Bindings/hwmon/national,lm90.yaml20
-rw-r--r--dts/Bindings/hwmon/nuvoton,nct6775.yaml57
-rw-r--r--dts/Bindings/hwmon/ti,tmp401.yaml105
-rw-r--r--dts/Bindings/i2c/i2c-gate.yaml1
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.txt53
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.yaml118
-rw-r--r--dts/Bindings/i2c/i2c-mux-gpmux.yaml1
-rw-r--r--dts/Bindings/i2c/qcom,i2c-geni-qcom.yaml100
-rw-r--r--dts/Bindings/i2c/qcom,i2c-qup.txt40
-rw-r--r--dts/Bindings/i2c/qcom,i2c-qup.yaml89
-rw-r--r--dts/Bindings/i2c/renesas,rcar-i2c.yaml2
-rw-r--r--dts/Bindings/i2c/renesas,riic.yaml2
-rw-r--r--dts/Bindings/i2c/samsung,s3c2410-i2c.yaml2
-rw-r--r--dts/Bindings/i3c/cdns,i3c-master.txt43
-rw-r--r--dts/Bindings/i3c/cdns,i3c-master.yaml60
-rw-r--r--dts/Bindings/i3c/snps,dw-i3c-master.txt41
-rw-r--r--dts/Bindings/i3c/snps,dw-i3c-master.yaml52
-rw-r--r--dts/Bindings/iio/adc/adi,ad7291.yaml1
-rw-r--r--dts/Bindings/iio/adc/renesas,rzg2l-adc.yaml3
-rw-r--r--dts/Bindings/iio/adc/sprd,sc2720-adc.yaml60
-rw-r--r--dts/Bindings/iio/adc/ti,ads1015.yaml7
-rw-r--r--dts/Bindings/iio/dac/adi,ad3552r.yaml2
-rw-r--r--dts/Bindings/iio/dac/lltc,ltc1660.yaml2
-rw-r--r--dts/Bindings/iio/dac/lltc,ltc2632.yaml2
-rw-r--r--dts/Bindings/iio/imu/invensense,mpu6050.yaml34
-rw-r--r--dts/Bindings/iio/imu/st,lsm6dsx.yaml38
-rw-r--r--dts/Bindings/iio/light/stk33xx.yaml6
-rw-r--r--dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml2
-rw-r--r--dts/Bindings/iio/st,st-sensors.yaml1
-rw-r--r--dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml22
-rw-r--r--dts/Bindings/input/azoteq,iqs7222.yaml960
-rw-r--r--dts/Bindings/input/google,cros-ec-keyb.yaml37
-rw-r--r--dts/Bindings/input/ilitek,ili2xxx.txt27
-rw-r--r--dts/Bindings/input/touchscreen/ilitek_ts_i2c.yaml7
-rw-r--r--dts/Bindings/interconnect/qcom,bcm-voter.yaml8
-rw-r--r--dts/Bindings/interconnect/qcom,osm-l3.yaml2
-rw-r--r--dts/Bindings/interconnect/qcom,rpmh.yaml18
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.yaml8
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-extirq.txt53
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-extirq.yaml118
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt6
-rw-r--r--dts/Bindings/interrupt-controller/renesas,h8300h-intc.txt22
-rw-r--r--dts/Bindings/interrupt-controller/renesas,h8s-intc.txt22
-rw-r--r--dts/Bindings/iommu/apple,sart.yaml52
-rw-r--r--dts/Bindings/iommu/arm,smmu-v3.yaml16
-rw-r--r--dts/Bindings/iommu/arm,smmu.yaml25
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.yaml34
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.yaml11
-rw-r--r--dts/Bindings/leds/backlight/qcom-wled.yaml2
-rw-r--r--dts/Bindings/leds/kinetic,ktd2692.yaml87
-rw-r--r--dts/Bindings/leds/leds-class-multicolor.yaml2
-rw-r--r--dts/Bindings/leds/leds-ktd2692.txt50
-rw-r--r--dts/Bindings/leds/leds-mt6360.yaml2
-rw-r--r--dts/Bindings/leds/leds-pwm-multicolor.yaml79
-rw-r--r--dts/Bindings/leds/leds-qcom-lpg.yaml174
-rw-r--r--dts/Bindings/leds/regulator-led.yaml55
-rw-r--r--dts/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml1
-rw-r--r--dts/Bindings/mailbox/mtk,adsp-mbox.yaml7
-rw-r--r--dts/Bindings/mailbox/nvidia,tegra186-hsp.yaml9
-rw-r--r--dts/Bindings/mailbox/qcom-ipcc.yaml30
-rw-r--r--dts/Bindings/mailbox/st,stm32-ipcc.yaml11
-rw-r--r--dts/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt127
-rw-r--r--dts/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml140
-rw-r--r--dts/Bindings/media/i2c/adv7604.yaml3
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9807-vcm.txt9
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9807-vcm.yaml41
-rw-r--r--dts/Bindings/media/i2c/sony,imx412.yaml9
-rw-r--r--dts/Bindings/media/mediatek,vcodec-encoder.yaml3
-rw-r--r--dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml4
-rw-r--r--dts/Bindings/media/microchip,xisc.yaml3
-rw-r--r--dts/Bindings/media/rockchip,vdec.yaml4
-rw-r--r--dts/Bindings/media/rockchip-vpu.yaml1
-rw-r--r--dts/Bindings/media/video-interfaces.yaml1
-rw-r--r--dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml6
-rw-r--r--dts/Bindings/memory-controllers/ingenic,nemc-peripherals.yaml46
-rw-r--r--dts/Bindings/memory-controllers/ingenic,nemc.yaml32
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra186-mc.yaml80
-rw-r--r--dts/Bindings/memory-controllers/renesas,h8300-bsc.yaml35
-rw-r--r--dts/Bindings/memory-controllers/renesas,rpc-if.yaml6
-rw-r--r--dts/Bindings/memory-controllers/rockchip,rk3399-dmc.yaml384
-rw-r--r--dts/Bindings/mfd/da9063.txt9
-rw-r--r--dts/Bindings/mfd/google,cros-ec.yaml2
-rw-r--r--dts/Bindings/mfd/mediatek,mt6360.yaml256
-rw-r--r--dts/Bindings/mfd/qcom,spmi-pmic.txt2
-rw-r--r--dts/Bindings/mfd/rk808.txt465
-rw-r--r--dts/Bindings/mfd/rockchip,rk805.yaml219
-rw-r--r--dts/Bindings/mfd/rockchip,rk808.yaml257
-rw-r--r--dts/Bindings/mfd/rockchip,rk809.yaml284
-rw-r--r--dts/Bindings/mfd/rockchip,rk817.yaml330
-rw-r--r--dts/Bindings/mfd/rockchip,rk818.yaml282
-rw-r--r--dts/Bindings/mfd/samsung,exynos5433-lpass.yaml4
-rw-r--r--dts/Bindings/mfd/syscon.yaml8
-rw-r--r--dts/Bindings/mfd/wlf,arizona.yaml1
-rw-r--r--dts/Bindings/mmc/brcm,sdhci-brcmstb.yaml20
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.yaml31
-rw-r--r--dts/Bindings/mmc/marvell,dove-sdhci.yaml44
-rw-r--r--dts/Bindings/mmc/marvell,orion-sdio.yaml44
-rw-r--r--dts/Bindings/mmc/marvell,xenon-sdhci.txt173
-rw-r--r--dts/Bindings/mmc/marvell,xenon-sdhci.yaml275
-rw-r--r--dts/Bindings/mmc/mmc-controller.yaml5
-rw-r--r--dts/Bindings/mmc/mtk-sd.yaml15
-rw-r--r--dts/Bindings/mmc/orion-sdio.txt16
-rw-r--r--dts/Bindings/mmc/sdhci-am654.yaml7
-rw-r--r--dts/Bindings/mmc/sdhci-dove.txt14
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-rw-r--r--dts/src/mips/mscc/jaguar2_pcb118.dts6
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi4
-rw-r--r--dts/src/mips/mscc/ocelot_pcb120.dts6
-rw-r--r--dts/src/mips/mscc/serval_common.dtsi14
-rw-r--r--dts/src/mips/ralink/gardena_smart_gateway_mt7688.dts2
-rw-r--r--dts/src/mips/ralink/mt7621-gnubee-gb-pc1.dts26
-rw-r--r--dts/src/mips/ralink/mt7621-gnubee-gb-pc2.dts30
-rw-r--r--dts/src/mips/ralink/mt7621.dtsi4
-rw-r--r--dts/src/powerpc/fsl/p2020si-post.dtsi5
-rw-r--r--dts/src/powerpc/microwatt.dts2
-rw-r--r--dts/src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi (renamed from dts/src/riscv/microchip/microchip-mpfs-fabric.dtsi)2
-rw-r--r--dts/src/riscv/microchip/mpfs-icicle-kit.dts (renamed from dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts)105
-rw-r--r--dts/src/riscv/microchip/mpfs-polarberry-fabric.dtsi16
-rw-r--r--dts/src/riscv/microchip/mpfs-polarberry.dts99
-rw-r--r--dts/src/riscv/microchip/mpfs.dtsi (renamed from dts/src/riscv/microchip/microchip-mpfs.dtsi)11
-rw-r--r--dts/src/riscv/sifive/fu540-c000.dtsi3
1355 files changed, 68187 insertions, 19001 deletions
diff --git a/dts/Bindings/arm/arm,corstone1000.yaml b/dts/Bindings/arm/arm,corstone1000.yaml
new file mode 100644
index 0000000000..a77f882238
--- /dev/null
+++ b/dts/Bindings/arm/arm,corstone1000.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Corstone1000 Device Tree Bindings
+
+maintainers:
+ - Vishnu Banavath <vishnu.banavath@arm.com>
+ - Rui Miguel Silva <rui.silva@linaro.org>
+
+description: |+
+ ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
+ provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
+ processors.
+
+ Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
+ systems for M-Class (or other) processors for adding sensors, connectivity,
+ video, audio and machine learning at the edge System and security IPs to build
+ a secure SoC for a range of rich IoT applications, for example gateways, smart
+ cameras and embedded systems.
+
+ Integrated Secure Enclave providing hardware Root of Trust and supporting
+ seamless integration of the optional CryptoCell™-312 cryptographic
+ accelerator.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
+ implementation of the Corstone1000 in the MPS3 prototyping board. See
+ ARM document DAI0550.
+ items:
+ - const: arm,corstone1000-mps3
+ - description: Corstone1000 FVP is the Fixed Virtual Platform
+ implementation of this system. See ARM ecosystems FVP's.
+ items:
+ - const: arm,corstone1000-fvp
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4708.yaml b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
index 434d3c6db6..8b7e87fb6c 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
+++ b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
@@ -64,6 +64,7 @@ properties:
- description: BCM47094 based boards
items:
- enum:
+ - asus,rt-ac88u
- dlink,dir-885l
- linksys,panamera
- luxul,abr-4500-v1
@@ -83,9 +84,14 @@ properties:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
+ - const: brcm,bcm53012
+ - const: brcm,bcm4708
+
+ - description: BCM53016 based boards
+ items:
+ - enum:
- meraki,mr32
- - const: brcm,brcm53012
- - const: brcm,brcm53016
+ - const: brcm,bcm53016
- const: brcm,bcm4708
additionalProperties: true
diff --git a/dts/Bindings/arm/bcm/brcm,bcm63138.txt b/dts/Bindings/arm/bcm/brcm,bcm63138.txt
index 8c7a4908a8..a8866c6e9d 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm63138.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm63138.txt
@@ -30,7 +30,7 @@ Example:
cpus {
cpu@0 {
- compatible = "arm,cotex-a9";
+ compatible = "arm,cortex-a9";
reg = <0>;
...
enable-method = "brcm,bcm63138";
diff --git a/dts/Bindings/arm/bcm/brcm,bcmbca.yaml b/dts/Bindings/arm/bcm/brcm,bcmbca.yaml
new file mode 100644
index 0000000000..5fb4558404
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcmbca.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC device tree bindings
+
+description:
+ Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
+ chips that can be used as home gateway, router and WLAN AP for residential,
+ enterprise and carrier applications.
+
+maintainers:
+ - William Zhang <william.zhang@broadcom.com>
+ - Anand Gore <anand.gore@broadcom.com>
+ - Kursad Oney <kursad.oney@broadcom.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: BCM47622 based boards
+ items:
+ - enum:
+ - brcm,bcm947622
+ - const: brcm,bcm47622
+ - const: brcm,bcmbca
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt b/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt
deleted file mode 100644
index 10a91cc8b9..0000000000
--- a/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Freescale DCFG
-
-DCFG is the device configuration unit, that provides general purpose
-configuration and status for the device. Such as setting the secondary
-core start address and release the secondary core from holdoff and startup.
-
-Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-dcfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
-
- - reg : should contain base address and length of DCFG memory-mapped registers
-
-Example:
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1021a-dcfg";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
- };
diff --git a/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt b/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt
deleted file mode 100644
index 0ab67b0b21..0000000000
--- a/dts/Bindings/arm/freescale/fsl,layerscape-scfg.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Freescale SCFG
-
-SCFG is the supplemental configuration unit, that provides SoC specific
-configuration and status registers for the chip. Such as getting PEX port
-status.
-
-Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-scfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
-
- - reg: should contain base address and length of SCFG memory-mapped registers
-
-Example:
- scfg: scfg@1570000 {
- compatible = "fsl,ls1021a-scfg";
- reg = <0x0 0x1570000 0x0 0x10000>;
- };
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 08bdd30e51..ef524378d4 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -172,7 +172,7 @@ properties:
- karo,tx53 # Ka-Ro electronics TX53 module
- kiebackpeter,imx53-ddc # K+P imx53 DDC
- kiebackpeter,imx53-hsc # K+P imx53 HSC
- - menlo,m53menlo
+ - menlo,m53menlo # i.MX53 Menlo board
- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
- const: fsl,imx53
@@ -192,6 +192,7 @@ properties:
items:
- enum:
- auvidea,h100 # Auvidea H100
+ - bosch,imx6q-acc # Bosch ACC i.MX6 Dual
- boundary,imx6q-nitrogen6_max
- boundary,imx6q-nitrogen6_som2
- boundary,imx6q-nitrogen6x
@@ -411,7 +412,6 @@ properties:
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Modules
- - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
@@ -488,17 +488,13 @@ properties:
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
items:
- enum:
+ - toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
+ - toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board
+ - toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2
- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
- const: fsl,imx6dl
- - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
- items:
- - enum:
- - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
- - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
- - const: fsl,imx6dl
-
- description: i.MX6S DHCOM DRC02 Board
items:
- const: dh,imx6s-dhcom-drc02
@@ -613,6 +609,28 @@ properties:
- const: kontron,imx6ul-n6310-som
- const: fsl,imx6ul
+ - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board
+ items:
+ - enum:
+ - tq,imx6ul-tqma6ul1-mba6ulx
+ - const: tq,imx6ul-tqma6ul1 # MCIMX6G1
+ - const: fsl,imx6ul
+
+ - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board
+ items:
+ - enum:
+ - tq,imx6ul-tqma6ul2-mba6ulx
+ - const: tq,imx6ul-tqma6ul2 # MCIMX6G2
+ - const: fsl,imx6ul
+
+ - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board
+ items:
+ - enum:
+ - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter
+ - tq,imx6ul-tqma6ul2l-mba6ulxl
+ - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant
+ - const: fsl,imx6ul
+
- description: i.MX6ULL based Boards
items:
- enum:
@@ -640,26 +658,44 @@ properties:
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
+ - description: i.MX6ULL PHYTEC phyGATE-Tauri
+ items:
+ - enum:
+ - phytec,imx6ull-phygate-tauri-emmc
+ - phytec,imx6ull-phygate-tauri-nand
+ - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL
+ - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
+ - const: fsl,imx6ull
+
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
- - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
+ - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
+ - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3
+ - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
+ - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- - const: fsl,imx6dl
+ - const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
- - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- - const: fsl,imx6dl
+ - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
+ - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
+ - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
+ - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
+ - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
+ - const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
- - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- - const: fsl,imx6dl
+ - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
+ - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
+ - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
+ - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
+ - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
+ - const: fsl,imx6ull
- description: Kontron N6411 S Board
items:
@@ -667,6 +703,21 @@ properties:
- const: kontron,imx6ull-n6411-som
- const: fsl,imx6ull
+ - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
+ items:
+ - enum:
+ - tq,imx6ull-tqma6ull2-mba6ulx
+ - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
+ - const: fsl,imx6ull
+
+ - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
+ items:
+ - enum:
+ - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
+ - tq,imx6ull-tqma6ull2l-mba6ulxl
+ - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
+ - const: fsl,imx6ull
+
- description: i.MX6ULZ based Boards
items:
- enum:
@@ -707,6 +758,7 @@ properties:
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
+ - storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
@@ -762,6 +814,7 @@ properties:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
+ - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
@@ -772,6 +825,7 @@ properties:
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
+ - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
@@ -834,6 +888,7 @@ properties:
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
+ - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
@@ -860,6 +915,17 @@ properties:
items:
- enum:
- fsl,imx8mp-evk # i.MX8MP EVK Board
+ - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
+ - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
+ - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
+ - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
+ - const: fsl,imx8mp
+
+ - description: Engicam i.Core MX8M Plus SoM based boards
+ items:
+ - enum:
+ - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
+ - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
- const: fsl,imx8mp
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
@@ -868,6 +934,24 @@ properties:
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp
+ - description: Toradex Boards with Verdin iMX8M Plus Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
+ - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
+ - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
+ - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
+ - const: fsl,imx8mp
+
+ - description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
+ - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
+ - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
+ - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
+ - const: fsl,imx8mp
+
- description: i.MX8MQ based Boards
items:
- enum:
@@ -999,6 +1083,7 @@ properties:
- description: LS1021A based Boards
items:
- enum:
+ - fsl,ls1021a-iot
- fsl,ls1021a-moxa-uc-8410a
- fsl,ls1021a-qds
- fsl,ls1021a-tsn
diff --git a/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
index 7378159e61..483caf0ce2 100644
--- a/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
+++ b/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
@@ -17,14 +17,15 @@ properties:
- const: hisilicon,hip04-bootwrapper
boot-method:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
- minItems: 1
- maxItems: 2
+ minItems: 2
+ maxItems: 4
required:
- compatible
diff --git a/dts/Bindings/arm/hpe,gxp.yaml b/dts/Bindings/arm/hpe,gxp.yaml
new file mode 100644
index 0000000000..224bbcb93f
--- /dev/null
+++ b/dts/Bindings/arm/hpe,gxp.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HPE BMC GXP platforms
+
+maintainers:
+ - Nick Hawkins <nick.hawkins@hpe.com>
+ - Jean-Marie Verdun <verdun@hpe.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: GXP Based Boards
+ items:
+ - enum:
+ - hpe,gxp-dl360gen10
+ - const: hpe,gxp
+
+required:
+ - compatible
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/intel,socfpga.yaml b/dts/Bindings/arm/intel,socfpga.yaml
index 6e043459fc..61a454a40e 100644
--- a/dts/Bindings/arm/intel,socfpga.yaml
+++ b/dts/Bindings/arm/intel,socfpga.yaml
@@ -18,6 +18,7 @@ properties:
items:
- enum:
- intel,n5x-socdk
+ - intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml
index ab0593c773..4a2bd9759c 100644
--- a/dts/Bindings/arm/mediatek.yaml
+++ b/dts/Bindings/arm/mediatek.yaml
@@ -133,6 +133,11 @@ properties:
- const: mediatek,mt8183
- items:
- enum:
+ - mediatek,mt8192-evb
+ - const: mediatek,mt8192
+ - items:
+ - enum:
+ - mediatek,mt8195-demo
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
deleted file mode 100644
index 3fa7558665..0000000000
--- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Mediatek apmixedsys controller
-==============================
-
-The Mediatek apmixedsys controller provides the PLLs to the system.
-
-Required Properties:
-
-- compatible: Should be one of:
- - "mediatek,mt2701-apmixedsys"
- - "mediatek,mt2712-apmixedsys", "syscon"
- - "mediatek,mt6765-apmixedsys", "syscon"
- - "mediatek,mt6779-apmixedsys", "syscon"
- - "mediatek,mt6797-apmixedsys"
- - "mediatek,mt7622-apmixedsys"
- - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- - "mediatek,mt7629-apmixedsys"
- - "mediatek,mt7986-apmixedsys"
- - "mediatek,mt8135-apmixedsys"
- - "mediatek,mt8167-apmixedsys", "syscon"
- - "mediatek,mt8173-apmixedsys"
- - "mediatek,mt8183-apmixedsys", "syscon"
- - "mediatek,mt8516-apmixedsys"
-- #clock-cells: Must be 1
-
-The apmixedsys controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-apmixedsys: clock-controller@10209000 {
- compatible = "mediatek,mt8173-apmixedsys";
- reg = <0 0x10209000 0 0x1000>;
- #clock-cells = <1>;
-};
diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
deleted file mode 100644
index f66bd72057..0000000000
--- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek infracfg controller
-============================
-
-The Mediatek infracfg controller provides various clocks and reset
-outputs to the system.
-
-Required Properties:
-
-- compatible: Should be one of:
- - "mediatek,mt2701-infracfg", "syscon"
- - "mediatek,mt2712-infracfg", "syscon"
- - "mediatek,mt6765-infracfg", "syscon"
- - "mediatek,mt6779-infracfg_ao", "syscon"
- - "mediatek,mt6797-infracfg", "syscon"
- - "mediatek,mt7622-infracfg", "syscon"
- - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- - "mediatek,mt7629-infracfg", "syscon"
- - "mediatek,mt7986-infracfg", "syscon"
- - "mediatek,mt8135-infracfg", "syscon"
- - "mediatek,mt8167-infracfg", "syscon"
- - "mediatek,mt8173-infracfg", "syscon"
- - "mediatek,mt8183-infracfg", "syscon"
- - "mediatek,mt8516-infracfg", "syscon"
-- #clock-cells: Must be 1
-- #reset-cells: Must be 1
-
-The infracfg controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-Also it uses the common reset controller binding from
-Documentation/devicetree/bindings/reset/reset.txt.
-The available reset outputs are defined in
-dt-bindings/reset/mt*-resets.h
-
-Example:
-
-infracfg: power-controller@10001000 {
- compatible = "mediatek,mt8173-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-};
diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml
new file mode 100644
index 0000000000..8681b785ed
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Infrastructure System Configuration Controller
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description:
+ The Mediatek infracfg controller provides various clocks and reset outputs
+ to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
+ and reset values in <dt-bindings/reset/mt*-reset.h> and
+ <dt-bindings/reset/mt*-resets.h>.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-infracfg
+ - mediatek,mt2712-infracfg
+ - mediatek,mt6765-infracfg
+ - mediatek,mt6779-infracfg_ao
+ - mediatek,mt6797-infracfg
+ - mediatek,mt7622-infracfg
+ - mediatek,mt7629-infracfg
+ - mediatek,mt7986-infracfg
+ - mediatek,mt8135-infracfg
+ - mediatek,mt8167-infracfg
+ - mediatek,mt8173-infracfg
+ - mediatek,mt8183-infracfg
+ - mediatek,mt8516-infracfg
+ - const: syscon
+ - items:
+ - const: mediatek,mt7623-infracfg
+ - const: mediatek,mt2701-infracfg
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt2701-infracfg
+ - mediatek,mt2712-infracfg
+ - mediatek,mt7622-infracfg
+ - mediatek,mt7986-infracfg
+ - mediatek,mt8135-infracfg
+ - mediatek,mt8173-infracfg
+ - mediatek,mt8183-infracfg
+then:
+ required:
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt8173-infracfg", "syscon";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9e..6ad023eec1 100644
--- a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
+ - mediatek,mt8195-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
@@ -41,6 +42,30 @@ properties:
reg:
maxItems: 1
+ power-domains:
+ description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mboxes:
+ description:
+ Using mailbox to communicate with GCE, it should have this
+ property and list of phandle, mailbox specifiers. See
+ Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mediatek,gce-client-reg:
+ description:
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each subsys id is mapping to a base address of display function blocks
+ register which is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
"#clock-cells":
const: 1
@@ -56,9 +81,16 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
new file mode 100644
index 0000000000..9fbeb626ab
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek PCIE Mirror Controller for MT7622
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+ - Felix Fietkau <nbd@nbd.name>
+
+description:
+ The mediatek PCIE mirror provides a configuration interface for PCIE
+ controller on MT7622 soc.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt7622-pcie-mirror
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie_mirror: pcie-mirror@10000400 {
+ compatible = "mediatek,mt7622-pcie-mirror", "syscon";
+ reg = <0 0x10000400 0 0x10>;
+ };
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
new file mode 100644
index 0000000000..787d6673f9
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+ - Felix Fietkau <nbd@nbd.name>
+
+description:
+ The mediatek wireless ethernet dispatch controller can be configured to
+ intercept and handle access to the WLAN DMA queues and PCIe interrupts
+ and implement hardware flow offloading from ethernet to WLAN.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt7622-wed
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ wed0: wed@1020a000 {
+ compatible = "mediatek,mt7622-wed","syscon";
+ reg = <0 0x1020a000 0 0x1000>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
new file mode 100644
index 0000000000..cf1002c3ef
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Functional Clock Controller for MT8186
+
+maintainers:
+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8186-imp_iic_wrap
+ - mediatek,mt8186-mfgsys
+ - mediatek,mt8186-wpesys
+ - mediatek,mt8186-imgsys1
+ - mediatek,mt8186-imgsys2
+ - mediatek,mt8186-vdecsys
+ - mediatek,mt8186-vencsys
+ - mediatek,mt8186-camsys
+ - mediatek,mt8186-camsys_rawa
+ - mediatek,mt8186-camsys_rawb
+ - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-ipesys
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ imp_iic_wrap: clock-controller@11017000 {
+ compatible = "mediatek,mt8186-imp_iic_wrap";
+ reg = <0x11017000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
new file mode 100644
index 0000000000..0886e2e335
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek System Clock Controller for MT8186
+
+maintainers:
+ - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The apmixedsys provides most of PLLs which generated from SoC 26m.
+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+ The mcusys provides mux control to select the clock source in AP MCU.
+ The device nodes also provide the system control capacity for configuration.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8186-mcusys
+ - mediatek,mt8186-topckgen
+ - mediatek,mt8186-infracfg_ao
+ - mediatek,mt8186-apmixedsys
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8186-topckgen", "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
index 8723dfe34b..611f666f35 100644
--- a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -26,6 +26,7 @@ properties:
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
+ - mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
- items:
diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
deleted file mode 100644
index b82422bb71..0000000000
--- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Mediatek topckgen controller
-============================
-
-The Mediatek topckgen controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be one of:
- - "mediatek,mt2701-topckgen"
- - "mediatek,mt2712-topckgen", "syscon"
- - "mediatek,mt6765-topckgen", "syscon"
- - "mediatek,mt6779-topckgen", "syscon"
- - "mediatek,mt6797-topckgen"
- - "mediatek,mt7622-topckgen"
- - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- - "mediatek,mt7629-topckgen"
- - "mediatek,mt7986-topckgen", "syscon"
- - "mediatek,mt8135-topckgen"
- - "mediatek,mt8167-topckgen", "syscon"
- - "mediatek,mt8173-topckgen"
- - "mediatek,mt8183-topckgen", "syscon"
- - "mediatek,mt8516-topckgen"
-- #clock-cells: Must be 1
-
-The topckgen controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-topckgen: power-controller@10000000 {
- compatible = "mediatek,mt8173-topckgen";
- reg = <0 0x10000000 0 0x1000>;
- #clock-cells = <1>;
-};
diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml
index 30fcbe2ad8..5ea506412b 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.yaml
+++ b/dts/Bindings/arm/msm/qcom,llcc.yaml
@@ -23,6 +23,8 @@ properties:
enum:
- qcom,sc7180-llcc
- qcom,sc7280-llcc
+ - qcom,sc8180x-llcc
+ - qcom,sc8280xp-llcc
- qcom,sdm845-llcc
- qcom,sm6350-llcc
- qcom,sm8150-llcc
diff --git a/dts/Bindings/arm/omap/prcm.txt b/dts/Bindings/arm/omap/prcm.txt
index 3eb6d7afff..431ef8c56a 100644
--- a/dts/Bindings/arm/omap/prcm.txt
+++ b/dts/Bindings/arm/omap/prcm.txt
@@ -31,12 +31,17 @@ Required properties:
(base address and length)
- clocks: clocks for this module
- clockdomains: clockdomains for this module
+- #clock-cells: From common clock binding
+- clock-output-names: From common clock binding
+
Example:
-cm: cm@48004000 {
+cm: clock@48004000 {
compatible = "ti,omap3-cm";
reg = <0x48004000 0x4000>;
+ #clock-cells = <0>;
+ clock-output-names = "cm";
cm_clocks: clocks {
#address-cells = <1>;
diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml
index 129cdd2462..5c06d1bfc0 100644
--- a/dts/Bindings/arm/qcom.yaml
+++ b/dts/Bindings/arm/qcom.yaml
@@ -39,8 +39,11 @@ description: |
msm8994
msm8996
sa8155p
+ sa8540p
sc7180
sc7280
+ sc8180x
+ sc8280xp
sdm630
sdm632
sdm660
@@ -99,6 +102,7 @@ properties:
- items:
- enum:
+ - asus,sparrow
- lg,lenok
- const: qcom,apq8026
@@ -227,6 +231,18 @@ properties:
- items:
- enum:
+ - lenovo,flex-5g
+ - microsoft,surface-prox
+ - qcom,sc8180x-primus
+ - const: qcom,sc8180x
+
+ - items:
+ - enum:
+ - qcom,sc8280xp-qrd
+ - const: qcom,sc8280xp
+
+ - items:
+ - enum:
- fairphone,fp3
- const: qcom,sdm632
@@ -260,6 +276,11 @@ properties:
- items:
- enum:
+ - qcom,sa8295p-adp
+ - const: qcom,sa8540p
+
+ - items:
+ - enum:
- fairphone,fp4
- const: qcom,sm7225
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index fa435d6fda..ff80152f09 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -327,6 +327,18 @@ properties:
- const: renesas,spider-cpu
- const: renesas,r8a779f0
+ - description: R-Car V4H (R8A779G0)
+ items:
+ - enum:
+ - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
+ - const: renesas,r8a779g0
+
+ - items:
+ - enum:
+ - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
+ - const: renesas,white-hawk-cpu
+ - const: renesas,r8a779g0
+
- description: R-Car H3e (R8A779M0)
items:
- enum:
@@ -406,6 +418,8 @@ properties:
- description: RZ/G2UL (R9A07G043)
items:
- enum:
+ - renesas,smarc-evk # SMARC EVK
+ - enum:
- renesas,r9a07g043u11 # RZ/G2UL Type-1
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
@@ -430,6 +444,12 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
+ - description: RZ/V2M (R9A09G011)
+ items:
+ - enum:
+ - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
+ - const: renesas,r9a09g011
+
additionalProperties: true
...
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index eece92f83a..cf9eb1e832 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -133,6 +133,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly Station M2
+ items:
+ - const: firefly,rk3566-roc-pc
+ - const: rockchip,rk3566
+
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
@@ -502,9 +507,18 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- - description: Pine64 Quartz64 Model A
+ - description: Pine64 Quartz64 Model A/B
items:
- - const: pine64,quartz64-a
+ - enum:
+ - pine64,quartz64-a
+ - pine64,quartz64-b
+ - const: rockchip,rk3566
+
+ - description: Pine64 SoQuartz SoM
+ items:
+ - enum:
+ - pine64,soquartz-cm4io
+ - const: pine64,soquartz
- const: rockchip,rk3566
- description: Radxa Rock
@@ -545,6 +559,11 @@ properties:
- const: radxa,rock2-square
- const: rockchip,rk3288
+ - description: Radxa ROCK3 Model A
+ items:
+ - const: radxa,rock3a
+ - const: rockchip,rk3568
+
- description: Rikomagic MK808 v1
items:
- const: rikomagic,mk808
diff --git a/dts/Bindings/arm/sp810.txt b/dts/Bindings/arm/sp810.txt
deleted file mode 100644
index 46652bf651..0000000000
--- a/dts/Bindings/arm/sp810.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SP810 System Controller
------------------------
-
-Required properties:
-
-- compatible: standard compatible string for a Primecell peripheral,
- see Documentation/devicetree/bindings/arm/primecell.yaml
- for more details
- should be: "arm,sp810", "arm,primecell"
-
-- reg: standard registers property, physical address and size
- of the control registers
-
-- clock-names: from the common clock bindings, for more details see
- Documentation/devicetree/bindings/clock/clock-bindings.txt;
- should be: "refclk", "timclk", "apb_pclk"
-
-- clocks: from the common clock bindings, phandle and clock
- specifier pairs for the entries of clock-names property
-
-- #clock-cells: from the common clock bindings;
- should be: <1>
-
-- clock-output-names: from the common clock bindings;
- should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
-
-- assigned-clocks: from the common clock binding;
- should be: clock specifier for each output clock of this
- provider node
-
-- assigned-clock-parents: from the common clock binding;
- should be: phandle of input clock listed in clocks
- property with the highest frequency
-
-Example:
- v2m_sysctl: sysctl@20000 {
- compatible = "arm,sp810", "arm,primecell";
- reg = <0x020000 0x1000>;
- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
- assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
-
- };
diff --git a/dts/Bindings/arm/sp810.yaml b/dts/Bindings/arm/sp810.yaml
new file mode 100644
index 0000000000..bc8e524aa9
--- /dev/null
+++ b/dts/Bindings/arm/sp810.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sp810.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Express SP810 System Controller bindings
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ The Arm SP810 system controller provides clocks, timers and a watchdog.
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ const: arm,sp810
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: arm,sp810
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: refclk
+ - const: timclk
+ - const: apb_pclk
+
+ clocks:
+ items:
+ - description: reference clock
+ - description: timer clock
+ - description: APB register access clock
+
+ "#clock-cells":
+ const: 1
+
+ clock-output-names:
+ maxItems: 4
+
+ assigned-clocks:
+ maxItems: 4
+
+ assigned-clock-parents:
+ maxItems: 4
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+ sysctl@20000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1",
+ "timerclken2", "timerclken3";
+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
+ <&v2m_sysctl 3>, <&v2m_sysctl 3>;
+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
+ <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
+ };
diff --git a/dts/Bindings/arm/spe-pmu.txt b/dts/Bindings/arm/spe-pmu.txt
deleted file mode 100644
index 93372f2a7d..0000000000
--- a/dts/Bindings/arm/spe-pmu.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
-
-ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
-performance sample data using an in-memory trace buffer.
-
-** SPE Required properties:
-
-- compatible : should be one of:
- "arm,statistical-profiling-extension-v1"
-
-- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
- SPE is only supported on a subset of the CPUs, please consult
- the arm,gic-v3 binding for details on describing a PPI partition.
-
-** Example:
-
-spe-pmu {
- compatible = "arm,statistical-profiling-extension-v1";
- interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;
-};
diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml
index fa0a1b8412..8b31565fee 100644
--- a/dts/Bindings/arm/stm32/stm32.yaml
+++ b/dts/Bindings/arm/stm32/stm32.yaml
@@ -14,21 +14,6 @@ properties:
const: "/"
compatible:
oneOf:
- - description: DH STM32MP1 SoM based Boards
- items:
- - enum:
- - arrow,stm32mp157a-avenger96 # Avenger96
- - dh,stm32mp153c-dhcom-drc02
- - dh,stm32mp157c-dhcom-pdk2
- - dh,stm32mp157c-dhcom-picoitx
- - enum:
- - dh,stm32mp153c-dhcom-som
- - dh,stm32mp157a-dhcor-som
- - dh,stm32mp157c-dhcom-som
- - enum:
- - st,stm32mp153
- - st,stm32mp157
-
- description: emtrion STM32MP1 Argon based Boards
items:
- const: emtrion,stm32mp157c-emsbc-argon
@@ -65,6 +50,21 @@ properties:
- enum:
- st,stm32mp135f-dk
- const: st,stm32mp135
+
+ - description: ST STM32MP151 based Boards
+ items:
+ - enum:
+ - prt,prtt1a # Protonic PRTT1A
+ - prt,prtt1c # Protonic PRTT1C
+ - prt,prtt1s # Protonic PRTT1S
+ - const: st,stm32mp151
+
+ - description: DH STM32MP153 SoM based Boards
+ items:
+ - const: dh,stm32mp153c-dhcom-drc02
+ - const: dh,stm32mp153c-dhcom-som
+ - const: st,stm32mp153
+
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box
@@ -72,13 +72,45 @@ properties:
- st,stm32mp157c-ed1
- st,stm32mp157a-dk1
- st,stm32mp157c-dk2
+ - const: st,stm32mp157
+ - items:
+ - const: st,stm32mp157a-dk1-scmi
+ - const: st,stm32mp157a-dk1
- const: st,stm32mp157
- items:
+ - const: st,stm32mp157c-dk2-scmi
+ - const: st,stm32mp157c-dk2
+ - const: st,stm32mp157
+ - items:
+ - const: st,stm32mp157c-ed1-scmi
+ - const: st,stm32mp157c-ed1
+ - const: st,stm32mp157
+ - items:
+ - const: st,stm32mp157c-ev1
+ - const: st,stm32mp157c-ed1
+ - const: st,stm32mp157
+ - items:
+ - const: st,stm32mp157c-ev1-scmi
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
+ - description: DH STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - arrow,stm32mp157a-avenger96 # Avenger96
+ - const: dh,stm32mp157a-dhcor-som
+ - const: st,stm32mp157
+
+ - description: DH STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - dh,stm32mp157c-dhcom-pdk2
+ - dh,stm32mp157c-dhcom-picoitx
+ - const: dh,stm32mp157c-dhcom-som
+ - const: st,stm32mp157
+
- description: Engicam i.Core STM32MP1 SoM based Boards
items:
- enum:
@@ -103,6 +135,7 @@ properties:
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157
+
- description: Odyssey STM32MP1 SoM based Boards
items:
- enum:
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index 086c68771d..95278a6a9a 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -391,6 +391,11 @@ properties:
- const: libretech,all-h5-cc-h5
- const: allwinner,sun50i-h5
+ - description: Lichee Pi Nano
+ items:
+ - const: licheepi,licheepi-nano
+ - const: allwinner,suniv-f1c100s
+
- description: Lichee Pi One
items:
- const: licheepi,licheepi-one
diff --git a/dts/Bindings/arm/syna.txt b/dts/Bindings/arm/syna.txt
index d8b48f2edf..851f48ead9 100644
--- a/dts/Bindings/arm/syna.txt
+++ b/dts/Bindings/arm/syna.txt
@@ -18,10 +18,6 @@ stable binding/ABI.
---------------------------------------------------------------
-Boards with the Synaptics AS370 SoC shall have the following properties:
- Required root node property:
- compatible: "syna,as370"
-
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/dts/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
new file mode 100644
index 0000000000..8c6543b5c0
--- /dev/null
+++ b/dts/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
+
+maintainers:
+ - Sumit Gupta <sumitg@nvidia.com>
+ - Mikko Perttunen <mperttunen@nvidia.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |+
+ The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
+ registers that initiate CPU frequency/voltage transitions.
+
+properties:
+ $nodename:
+ pattern: "ccplex@([0-9a-f]+)$"
+
+ compatible:
+ enum:
+ - nvidia,tegra186-ccplex-cluster
+ - nvidia,tegra234-ccplex-cluster
+
+ reg:
+ maxItems: 1
+
+ nvidia,bpmp:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Specifies the BPMP node that needs to be queried to get
+ operating point data for all CPUs.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - nvidia,bpmp
+ - status
+
+examples:
+ - |
+ ccplex@e000000 {
+ compatible = "nvidia,tegra234-ccplex-cluster";
+ reg = <0x0e000000 0x5ffff>;
+ nvidia,bpmp = <&bpmp>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/arm/ux500.yaml b/dts/Bindings/arm/ux500.yaml
index a46193ad94..17accb31bc 100644
--- a/dts/Bindings/arm/ux500.yaml
+++ b/dts/Bindings/arm/ux500.yaml
@@ -40,6 +40,11 @@ properties:
- const: samsung,codina
- const: st-ericsson,u8500
+ - description: Samsung Galaxy Exhibit (SGH-T599)
+ items:
+ - const: samsung,codina-tmo
+ - const: st-ericsson,u8500
+
- description: Samsung Galaxy Beam (GT-I8530)
items:
- const: samsung,gavini
diff --git a/dts/Bindings/arm/vexpress-config.yaml b/dts/Bindings/arm/vexpress-config.yaml
new file mode 100644
index 0000000000..09e1adf5ca
--- /dev/null
+++ b/dts/Bindings/arm/vexpress-config.yaml
@@ -0,0 +1,285 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Express configuration bus bindings
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ This is a system control register block, acting as a bridge to the
+ platform's configuration bus via "system control" interface, addressing
+ devices with site number, position in the board stack, config controller,
+ function and device numbers - see motherboard's TRM for more details.
+
+properties:
+ compatible:
+ const: arm,vexpress,config-bus
+
+ arm,vexpress,config-bridge:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the sysreg node.
+
+ muxfpga:
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-muxfpga
+
+ arm,vexpress-sysreg,func:
+ description: FPGA specifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 7
+ - description: device number
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ shutdown:
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-shutdown
+
+ arm,vexpress-sysreg,func:
+ description: shutdown identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 8
+ - description: device number
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ reboot:
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-reboot
+
+ arm,vexpress-sysreg,func:
+ description: reboot identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 9
+ - description: device number
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ dvimode:
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-dvimode
+
+ arm,vexpress-sysreg,func:
+ description: DVI mode identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 11
+ - description: device number
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+additionalProperties: false
+
+required:
+ - compatible
+ - arm,vexpress,config-bridge
+
+patternProperties:
+ 'clk[0-9]*$':
+ type: object
+ description:
+ clocks
+
+ properties:
+ compatible:
+ const: arm,vexpress-osc
+
+ arm,vexpress-sysreg,func:
+ description: clock specifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 1
+ - description: clock number
+
+ freq-range:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: minimal clock frequency
+ - description: maximum clock frequency
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+ - "#clock-cells"
+
+ "^volt-.+$":
+ $ref: /schemas/regulator/regulator.yaml#
+ properties:
+ compatible:
+ const: arm,vexpress-volt
+
+ arm,vexpress-sysreg,func:
+ description: regulator specifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 2
+ - description: device number
+
+ label:
+ maxItems: 1
+
+ unevaluatedProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ "^amp-.+$":
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-amp
+
+ arm,vexpress-sysreg,func:
+ description: current sensor identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 3
+ - description: device number
+
+ label:
+ maxItems: 1
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ "^temp-.+$":
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-temp
+
+ arm,vexpress-sysreg,func:
+ description: temperature sensor identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 4
+ - description: device number
+
+ label:
+ maxItems: 1
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ "^reset[0-9]*$":
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-reset
+
+ arm,vexpress-sysreg,func:
+ description: reset specifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 5
+ - description: reset device number
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ "^power-.+$":
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-power
+
+ arm,vexpress-sysreg,func:
+ description: power sensor identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 12
+ - description: device number
+
+ label:
+ maxItems: 1
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+ "^energy(-.+)?$":
+ type: object
+ properties:
+ compatible:
+ const: arm,vexpress-energy
+
+ arm,vexpress-sysreg,func:
+ description: energy sensor identifier
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ oneOf:
+ - items:
+ - const: 13
+ - description: device number
+ - items:
+ - const: 13
+ - description: device number
+ - const: 13
+ - description: second device number
+
+ label:
+ maxItems: 1
+
+ additionalProperties: false
+ required:
+ - compatible
+ - arm,vexpress-sysreg,func
+
+examples:
+ - |
+ mcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ clk0 {
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 0>;
+ #clock-cells = <0>;
+ };
+
+ energy {
+ compatible = "arm,vexpress-energy";
+ arm,vexpress-sysreg,func = <13 0>, <13 1>;
+ };
+ };
diff --git a/dts/Bindings/arm/vexpress-sysreg.txt b/dts/Bindings/arm/vexpress-sysreg.txt
deleted file mode 100644
index 50095802fb..0000000000
--- a/dts/Bindings/arm/vexpress-sysreg.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-ARM Versatile Express system registers
---------------------------------------
-
-This is a system control registers block, providing multiple low level
-platform functions like board detection and identification, software
-interrupt generation, MMC and NOR Flash control etc.
-
-Required node properties:
-- compatible value : = "arm,vexpress,sysreg";
-- reg : physical base address and the size of the registers window
-
-Deprecated properties, replaced by GPIO subnodes (see below):
-- gpio-controller : specifies that the node is a GPIO controller
-- #gpio-cells : size of the GPIO specifier, should be 2:
- - first cell is the pseudo-GPIO line number:
- 0 - MMC CARDIN
- 1 - MMC WPROT
- 2 - NOR FLASH WPn
- - second cell can take standard GPIO flags (currently ignored).
-
-Control registers providing pseudo-GPIO lines must be represented
-by subnodes, each of them requiring the following properties:
-- compatible value : one of
- "arm,vexpress-sysreg,sys_led"
- "arm,vexpress-sysreg,sys_mci"
- "arm,vexpress-sysreg,sys_flash"
-- gpio-controller : makes the node a GPIO controller
-- #gpio-cells : size of the GPIO specifier, must be 2:
- - first cell is the function number:
- - for sys_led : 0..7 = LED 0..7
- - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
- - for sys_flash : 0 = NOR FLASH WPn
- - second cell can take standard GPIO flags (currently ignored).
-
-Example:
- v2m_sysreg: sysreg@10000000 {
- compatible = "arm,vexpress-sysreg";
- reg = <0x10000000 0x1000>;
-
- v2m_led_gpios: sys_led@8 {
- compatible = "arm,vexpress-sysreg,sys_led";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- v2m_mmc_gpios: sys_mci@48 {
- compatible = "arm,vexpress-sysreg,sys_mci";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- v2m_flash_gpios: sys_flash@4c {
- compatible = "arm,vexpress-sysreg,sys_flash";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
-This block also can also act a bridge to the platform's configuration
-bus via "system control" interface, addressing devices with site number,
-position in the board stack, config controller, function and device
-numbers - see motherboard's TRM for more details. All configuration
-controller accessible via this interface must reference the sysreg
-node via "arm,vexpress,config-bridge" phandle and define appropriate
-topology properties - see main vexpress node documentation for more
-details. Each child of such node describes one function and must
-define the following properties:
-- compatible value : must be one of (corresponding to the TRM):
- "arm,vexpress-amp"
- "arm,vexpress-dvimode"
- "arm,vexpress-energy"
- "arm,vexpress-muxfpga"
- "arm,vexpress-osc"
- "arm,vexpress-power"
- "arm,vexpress-reboot"
- "arm,vexpress-reset"
- "arm,vexpress-scc"
- "arm,vexpress-shutdown"
- "arm,vexpress-temp"
- "arm,vexpress-volt"
-- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
- - first cell of each group defines the function number
- (eg. 1 for clock generator, 2 for voltage regulators etc.)
- - second cell of each group defines device number (eg. osc 0,
- osc 1 etc.)
- - some functions (eg. energy meter, with its 64 bit long counter)
- are using more than one function/device number pair
-
-Example:
- mcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- };
-
- energy@0 {
- compatible = "arm,vexpress-energy";
- arm,vexpress-sysreg,func = <13 0>, <13 1>;
- };
- };
diff --git a/dts/Bindings/arm/vexpress-sysreg.yaml b/dts/Bindings/arm/vexpress-sysreg.yaml
new file mode 100644
index 0000000000..b5e26e41f8
--- /dev/null
+++ b/dts/Bindings/arm/vexpress-sysreg.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Express system registers bindings
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ This is a system control registers block, providing multiple low level
+ platform functions like board detection and identification, software
+ interrupt generation, MMC and NOR Flash control, etc.
+
+properties:
+ compatible:
+ const: arm,vexpress-sysreg
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+additionalProperties: false
+
+patternProperties:
+ '^gpio@[0-9a-f]+$':
+ type: object
+ additionalProperties: false
+ description:
+ GPIO children
+
+ properties:
+ compatible:
+ enum:
+ - arm,vexpress-sysreg,sys_led
+ - arm,vexpress-sysreg,sys_mci
+ - arm,vexpress-sysreg,sys_flash
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ The first cell is the function number:
+ for sys_led : 0..7 = LED 0..7
+ for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
+ for sys_flash : 0 = NOR FLASH WPn
+ The second cell can take standard GPIO flags.
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ sysreg@0 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+
+ v2m_led_gpios: gpio@8 {
+ compatible = "arm,vexpress-sysreg,sys_led";
+ reg = <0x008 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/ata/renesas,rcar-sata.yaml b/dts/Bindings/ata/renesas,rcar-sata.yaml
index c060c7914c..c4e4a9eab6 100644
--- a/dts/Bindings/ata/renesas,rcar-sata.yaml
+++ b/dts/Bindings/ata/renesas,rcar-sata.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
- renesas,sata-r8a774b1 # RZ/G2N
+ - renesas,sata-r8a774e1 # RZ/G2H
- renesas,sata-r8a7795 # R-Car H3
- renesas,sata-r8a77965 # R-Car M3-N
- const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
diff --git a/dts/Bindings/bus/qcom,ssc-block-bus.yaml b/dts/Bindings/bus/qcom,ssc-block-bus.yaml
new file mode 100644
index 0000000000..5b97050790
--- /dev/null
+++ b/dts/Bindings/bus/qcom,ssc-block-bus.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
+
+maintainers:
+ - Michael Srba <Michael.Srba@seznam.cz>
+
+description: |
+ This binding describes the dependencies (clocks, resets, power domains) which
+ need to be turned on in a sequence before communication over the AHB bus
+ becomes possible.
+
+ Additionally, the reg property is used to pass to the driver the location of
+ two sadly undocumented registers which need to be poked as part of the sequence.
+
+ The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
+ controllers, a hexagon core, and a clock controller which provides clocks for
+ the above.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,msm8998-ssc-block-bus
+ - const: qcom,ssc-block-bus
+
+ reg:
+ description: |
+ Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
+ registers
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: mpm_sscaon_config0
+ - const: mpm_sscaon_config1
+
+ '#address-cells':
+ enum: [ 1, 2 ]
+
+ '#size-cells':
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ minItems: 6
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: xo
+ - const: aggre2
+ - const: gcc_im_sleep
+ - const: aggre2_north
+ - const: ssc_xo
+ - const: ssc_ahbs
+
+ power-domains:
+ description: Power domain phandles for the ssc_cx and ssc_mx power domains
+ minItems: 2
+ maxItems: 2
+
+ power-domain-names:
+ items:
+ - const: ssc_cx
+ - const: ssc_mx
+
+ resets:
+ description: |
+ Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
+ branch control register associated with the ssc_xo and ssc_ahbs clocks)
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: ssc_reset
+ - const: ssc_bcr
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: describes how to locate the ssc AXI halt register
+ items:
+ - items:
+ - description: Phandle reference to a syscon representing TCSR
+ - description: offset for the ssc AXI halt register
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+ - qcom,halt-regs
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
+ ssc_ahb_slave: bus@10ac008 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
+ reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
+ reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
+
+ clocks = <&xo>,
+ <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
+ <&gcc GCC_IM_SLEEP>,
+ <&gcc AGGRE2_SNOC_NORTH_AXI>,
+ <&gcc SSC_XO>,
+ <&gcc SSC_CNOC_AHBS_CLK>;
+ clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
+
+ resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
+ reset-names = "ssc_reset", "ssc_bcr";
+
+ power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
+ power-domain-names = "ssc_cx", "ssc_mx";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
+ };
+ };
diff --git a/dts/Bindings/clock/airoha,en7523-scu.yaml b/dts/Bindings/clock/airoha,en7523-scu.yaml
new file mode 100644
index 0000000000..d60e746548
--- /dev/null
+++ b/dts/Bindings/clock/airoha,en7523-scu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EN7523 Clock Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <nbd@nbd.name>
+
+description: |
+ This node defines the System Control Unit of the EN7523 SoC,
+ a collection of registers configuring many different aspects of the SoC.
+
+ The clock driver uses it to read and configure settings of the
+ PLL controller, which provides clocks for the CPU, the bus and
+ other SoC internal peripherals.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify which clock they consume.
+
+ All these identifiers can be found in:
+ [1]: <include/dt-bindings/clock/en7523-clk.h>.
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+ items:
+ - const: airoha,en7523-scu
+
+ reg:
+ maxItems: 2
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/en7523-clk.h>
+ scu: system-controller@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/clock-bindings.txt b/dts/Bindings/clock/clock-bindings.txt
index f2ea53832a..6fe5413688 100644
--- a/dts/Bindings/clock/clock-bindings.txt
+++ b/dts/Bindings/clock/clock-bindings.txt
@@ -1,186 +1,2 @@
-This binding is a work-in-progress, and are based on some experimental
-work by benh[1].
-
-Sources of clock signal can be represented by any node in the device
-tree. Those nodes are designated as clock providers. Clock consumer
-nodes use a phandle and clock specifier pair to connect clock provider
-outputs to clock inputs. Similar to the gpio specifiers, a clock
-specifier is an array of zero, one or more cells identifying the clock
-output on a device. The length of a clock specifier is defined by the
-value of a #clock-cells property in the clock provider node.
-
-[1] https://patchwork.ozlabs.org/patch/31551/
-
-==Clock providers==
-
-Required properties:
-#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
- with a single clock output and 1 for nodes with multiple
- clock outputs.
-
-Optional properties:
-clock-output-names: Recommended to be a list of strings of clock output signal
- names indexed by the first cell in the clock specifier.
- However, the meaning of clock-output-names is domain
- specific to the clock provider, and is only provided to
- encourage using the same meaning for the majority of clock
- providers. This format may not work for clock providers
- using a complex clock specifier format. In those cases it
- is recommended to omit this property and create a binding
- specific names property.
-
- Clock consumer nodes must never directly reference
- the provider's clock-output-names property.
-
-For example:
-
- oscillator {
- #clock-cells = <1>;
- clock-output-names = "ckil", "ckih";
- };
-
-- this node defines a device with two clock outputs, the first named
- "ckil" and the second named "ckih". Consumer nodes always reference
- clocks by index. The names should reflect the clock output signal
- names for the device.
-
-clock-indices: If the identifying number for the clocks in the node
- is not linear from zero, then this allows the mapping of
- identifiers into the clock-output-names array.
-
-For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
-
- oscillator {
- compatible = "myclocktype";
- #clock-cells = <1>;
- clock-indices = <1>, <3>;
- clock-output-names = "clka", "clkb";
- }
-
- This ensures we do not have any empty strings in clock-output-names
-
-
-==Clock consumers==
-
-Required properties:
-clocks: List of phandle and clock specifier pairs, one pair
- for each clock input to the device. Note: if the
- clock provider specifies '0' for #clock-cells, then
- only the phandle portion of the pair will appear.
-
-Optional properties:
-clock-names: List of clock input name strings sorted in the same
- order as the clocks property. Consumers drivers
- will use clock-names to match clock input names
- with clocks specifiers.
-clock-ranges: Empty property indicating that child nodes can inherit named
- clocks from this node. Useful for bus nodes to provide a
- clock to their children.
-
-For example:
-
- device {
- clocks = <&osc 1>, <&ref 0>;
- clock-names = "baud", "register";
- };
-
-
-This represents a device with two clock inputs, named "baud" and "register".
-The baud clock is connected to output 1 of the &osc device, and the register
-clock is connected to output 0 of the &ref.
-
-==Example==
-
- /* external oscillator */
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32678>;
- clock-output-names = "osc";
- };
-
- /* phase-locked-loop device, generates a higher frequency clock
- * from the external oscillator reference */
- pll: pll@4c000 {
- compatible = "vendor,some-pll-interface"
- #clock-cells = <1>;
- clocks = <&osc 0>;
- clock-names = "ref";
- reg = <0x4c000 0x1000>;
- clock-output-names = "pll", "pll-switched";
- };
-
- /* UART, using the low frequency oscillator for the baud clock,
- * and the high frequency switched PLL output for register
- * clocking */
- uart@a000 {
- compatible = "fsl,imx-uart";
- reg = <0xa000 0x1000>;
- interrupts = <33>;
- clocks = <&osc 0>, <&pll 1>;
- clock-names = "baud", "register";
- };
-
-This DT fragment defines three devices: an external oscillator to provide a
-low-frequency reference clock, a PLL device to generate a higher frequency
-clock signal, and a UART.
-
-* The oscillator is fixed-frequency, and provides one clock output, named "osc".
-* The PLL is both a clock provider and a clock consumer. It uses the clock
- signal generated by the external oscillator, and provides two output signals
- ("pll" and "pll-switched").
-* The UART has its baud clock connected the external oscillator and its
- register clock connected to the PLL clock (the "pll-switched" signal)
-
-==Assigned clock parents and rates==
-
-Some platforms may require initial configuration of default parent clocks
-and clock frequencies. Such a configuration can be specified in a device tree
-node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
-properties. The assigned-clock-parents property should contain a list of parent
-clocks in the form of a phandle and clock specifier pair and the
-assigned-clock-rates property should contain a list of frequencies in Hz. Both
-these properties should correspond to the clocks listed in the assigned-clocks
-property.
-
-To skip setting parent or rate of a clock its corresponding entry should be
-set to 0, or can be omitted if it is not followed by any non-zero entry.
-
- uart@a000 {
- compatible = "fsl,imx-uart";
- reg = <0xa000 0x1000>;
- ...
- clocks = <&osc 0>, <&pll 1>;
- clock-names = "baud", "register";
-
- assigned-clocks = <&clkcon 0>, <&pll 2>;
- assigned-clock-parents = <&pll 2>;
- assigned-clock-rates = <0>, <460800>;
- };
-
-In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
-the <&pll 2> clock is assigned a frequency value of 460800 Hz.
-
-Configuring a clock's parent and rate through the device node that consumes
-the clock can be done only for clocks that have a single user. Specifying
-conflicting parent or rate configuration in multiple consumer nodes for
-a shared clock is forbidden.
-
-Configuration of common clocks, which affect multiple consumer devices can
-be similarly specified in the clock provider node.
-
-==Protected clocks==
-
-Some platforms or firmwares may not fully expose all the clocks to the OS, such
-as in situations where those clks are used by drivers running in ARM secure
-execution levels. Such a configuration can be specified in device tree with the
-protected-clocks property in the form of a clock specifier list. This property should
-only be specified in the node that is providing the clocks being protected:
-
- clock-controller@a000f000 {
- compatible = "vendor,clk95;
- reg = <0xa000f000 0x1000>
- #clocks-cells = <1>;
- ...
- protected-clocks = <UART3_CLK>, <SPI5_CLK>;
- };
+This file has moved to the clock binding schema:
+https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
diff --git a/dts/Bindings/clock/mediatek,apmixedsys.yaml b/dts/Bindings/clock/mediatek,apmixedsys.yaml
new file mode 100644
index 0000000000..770546195f
--- /dev/null
+++ b/dts/Bindings/clock/mediatek,apmixedsys.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek AP Mixedsys Controller
+
+maintainers:
+ - Michael Turquette <mturquette@baylibre.com>
+ - Stephen Boyd <sboyd@kernel.org>
+
+description:
+ The Mediatek apmixedsys controller provides PLLs to the system.
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt6797-apmixedsys
+ - mediatek,mt7622-apmixedsys
+ - mediatek,mt7986-apmixedsys
+ - mediatek,mt8135-apmixedsys
+ - mediatek,mt8173-apmixedsys
+ - mediatek,mt8516-apmixedsys
+ - items:
+ - const: mediatek,mt7623-apmixedsys
+ - const: mediatek,mt2701-apmixedsys
+ - const: syscon
+ - items:
+ - enum:
+ - mediatek,mt2701-apmixedsys
+ - mediatek,mt2712-apmixedsys
+ - mediatek,mt6765-apmixedsys
+ - mediatek,mt6779-apmixedsys
+ - mediatek,mt7629-apmixedsys
+ - mediatek,mt8167-apmixedsys
+ - mediatek,mt8183-apmixedsys
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ apmixedsys: clock-controller@10209000 {
+ compatible = "mediatek,mt8173-apmixedsys";
+ reg = <0x10209000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/mediatek,topckgen.yaml b/dts/Bindings/clock/mediatek,topckgen.yaml
new file mode 100644
index 0000000000..5b8b37a2e5
--- /dev/null
+++ b/dts/Bindings/clock/mediatek,topckgen.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Top Clock Generator Controller
+
+maintainers:
+ - Michael Turquette <mturquette@baylibre.com>
+ - Stephen Boyd <sboyd@kernel.org>
+
+description:
+ The Mediatek topckgen controller provides various clocks to the system.
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt6797-topckgen
+ - mediatek,mt7622-topckgen
+ - mediatek,mt8135-topckgen
+ - mediatek,mt8173-topckgen
+ - mediatek,mt8516-topckgen
+ - items:
+ - const: mediatek,mt7623-topckgen
+ - const: mediatek,mt2701-topckgen
+ - const: syscon
+ - items:
+ - enum:
+ - mediatek,mt2701-topckgen
+ - mediatek,mt2712-topckgen
+ - mediatek,mt6765-topckgen
+ - mediatek,mt6779-topckgen
+ - mediatek,mt7629-topckgen
+ - mediatek,mt7986-topckgen
+ - mediatek,mt8167-topckgen
+ - mediatek,mt8183-topckgen
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8173-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
index 97936411b6..9fafcb0800 100644
--- a/dts/Bindings/clock/qcom,gcc-apq8064.yaml
+++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
@@ -20,12 +20,10 @@ description: |
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
- - dt-bindings/clock/qcom,gcc-apq8084.h
- - dt-bindings/reset/qcom,gcc-apq8084.h
properties:
compatible:
- const: qcom,gcc-apq8084
+ const: qcom,gcc-apq8064
nvmem-cells:
minItems: 1
diff --git a/dts/Bindings/clock/qcom,gcc-apq8084.yaml b/dts/Bindings/clock/qcom,gcc-apq8084.yaml
new file mode 100644
index 0000000000..397fb918e0
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-apq8084.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on APQ8084.
+
+ See also::
+ - dt-bindings/clock/qcom,gcc-apq8084.h
+ - dt-bindings/reset/qcom,gcc-apq8084.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,gcc-apq8084
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@fc400000 {
+ compatible = "qcom,gcc-apq8084";
+ reg = <0xfc400000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml b/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml
new file mode 100644
index 0000000000..0bcdc69c6f
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SC8280xp.
+
+ See also:
+ - include/dt-bindings/clock/qcom,gcc-sc8280xp.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sc8280xp
+
+ clocks:
+ items:
+ - description: XO reference clock
+ - description: Sleep clock
+ - description: UFS memory first RX symbol clock
+ - description: UFS memory second RX symbol clock
+ - description: UFS memory first TX symbol clock
+ - description: UFS card first RX symbol clock
+ - description: UFS card second RX symbol clock
+ - description: UFS card first TX symbol clock
+ - description: Primary USB SuperSpeed pipe clock
+ - description: USB4 PHY pipegmux clock source
+ - description: USB4 PHY DP gmux clock source
+ - description: USB4 PHY sys piegmux clock source
+ - description: USB4 PHY PCIe pipe clock
+ - description: USB4 PHY router max pipe clock
+ - description: Primary USB4 RX0 clock
+ - description: Primary USB4 RX1 clock
+ - description: Secondary USB SuperSpeed pipe clock
+ - description: Second USB4 PHY pipegmux clock source
+ - description: Second USB4 PHY DP gmux clock source
+ - description: Second USB4 PHY sys pipegmux clock source
+ - description: Second USB4 PHY PCIe pipe clock
+ - description: Second USB4 PHY router max pipe clock
+ - description: Secondary USB4 RX0 clock
+ - description: Secondary USB4 RX1 clock
+ - description: Multiport USB first SupserSpeed pipe clock
+ - description: Multiport USB second SuperSpeed pipe clock
+ - description: PCIe 2a pipe clock
+ - description: PCIe 2b pipe clock
+ - description: PCIe 3a pipe clock
+ - description: PCIe 3b pipe clock
+ - description: PCIe 4 pipe clock
+ - description: First EMAC controller reference clock
+ - description: Second EMAC controller reference clock
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ maxItems: 389
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sc8280xp";
+ reg = <0x00100000 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&ufs_card_rx_symbol_0_clk>,
+ <&ufs_card_rx_symbol_1_clk>,
+ <&ufs_card_tx_symbol_0_clk>,
+ <&usb_0_ssphy>,
+ <&gcc_usb4_phy_pipegmux_clk_src>,
+ <&gcc_usb4_phy_dp_gmux_clk_src>,
+ <&gcc_usb4_phy_sys_pipegmux_clk_src>,
+ <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
+ <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
+ <&qusb4phy_gcc_usb4_rx0_clk>,
+ <&qusb4phy_gcc_usb4_rx1_clk>,
+ <&usb_1_ssphy>,
+ <&gcc_usb4_1_phy_pipegmux_clk_src>,
+ <&gcc_usb4_1_phy_dp_gmux_clk_src>,
+ <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
+ <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
+ <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
+ <&qusb4phy_1_gcc_usb4_rx0_clk>,
+ <&qusb4phy_1_gcc_usb4_rx1_clk>,
+ <&usb_2_ssphy>,
+ <&usb_3_ssphy>,
+ <&pcie2a_lane>,
+ <&pcie2b_lane>,
+ <&pcie3a_lane>,
+ <&pcie3b_lane>,
+ <&pcie4_lane>,
+ <&rxc0_ref_clk>,
+ <&rxc1_ref_clk>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,mmcc.yaml b/dts/Bindings/clock/qcom,mmcc.yaml
index 4b79e89fd1..32e87014bb 100644
--- a/dts/Bindings/clock/qcom,mmcc.yaml
+++ b/dts/Bindings/clock/qcom,mmcc.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Multimedia Clock & Reset Controller Binding
maintainers:
- - Jeffrey Hugo <jhugo@codeaurora.org>
+ - Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
description: |
diff --git a/dts/Bindings/clock/qcom,rpmcc.txt b/dts/Bindings/clock/qcom,rpmcc.txt
deleted file mode 100644
index da295c3c00..0000000000
--- a/dts/Bindings/clock/qcom,rpmcc.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-Qualcomm RPM Clock Controller Binding
-------------------------------------------------
-The RPM is a dedicated hardware engine for managing the shared
-SoC resources in order to keep the lowest power profile. It
-communicates with other hardware subsystems via shared memory
-and accepts clock requests, aggregates the requests and turns
-the clocks on/off or scales them on demand.
-
-Required properties :
-- compatible : shall contain only one of the following. The generic
- compatible "qcom,rpmcc" should be also included.
-
- "qcom,rpmcc-mdm9607", "qcom,rpmcc"
- "qcom,rpmcc-msm8660", "qcom,rpmcc"
- "qcom,rpmcc-apq8060", "qcom,rpmcc"
- "qcom,rpmcc-msm8226", "qcom,rpmcc"
- "qcom,rpmcc-msm8916", "qcom,rpmcc"
- "qcom,rpmcc-msm8936", "qcom,rpmcc"
- "qcom,rpmcc-msm8953", "qcom,rpmcc"
- "qcom,rpmcc-msm8974", "qcom,rpmcc"
- "qcom,rpmcc-msm8976", "qcom,rpmcc"
- "qcom,rpmcc-apq8064", "qcom,rpmcc"
- "qcom,rpmcc-ipq806x", "qcom,rpmcc"
- "qcom,rpmcc-msm8992",·"qcom,rpmcc"
- "qcom,rpmcc-msm8994",·"qcom,rpmcc"
- "qcom,rpmcc-msm8996", "qcom,rpmcc"
- "qcom,rpmcc-msm8998", "qcom,rpmcc"
- "qcom,rpmcc-qcm2290", "qcom,rpmcc"
- "qcom,rpmcc-qcs404", "qcom,rpmcc"
- "qcom,rpmcc-sdm660", "qcom,rpmcc"
- "qcom,rpmcc-sm6115", "qcom,rpmcc"
- "qcom,rpmcc-sm6125", "qcom,rpmcc"
-
-- #clock-cells : shall contain 1
-
-The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
-and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
-is an "active" clock, which means that the consumer only care that the
-clock is available when the apps CPU subsystem is active, i.e. not
-suspended or in deep idle. If it is important that the clock keeps running
-during system suspend, you need to specify the non-active clock, the one
-not containing *_A_* in the enumerator name.
-
-Example:
- smd {
- compatible = "qcom,smd";
-
- rpm {
- interrupts = <0 168 1>;
- qcom,ipc = <&apcs 8 0>;
- qcom,smd-edge = <15>;
-
- rpm_requests {
- compatible = "qcom,rpm-msm8916";
- qcom,smd-channels = "rpm_requests";
-
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
- #clock-cells = <1>;
- };
- };
- };
- };
diff --git a/dts/Bindings/clock/qcom,rpmcc.yaml b/dts/Bindings/clock/qcom,rpmcc.yaml
new file mode 100644
index 0000000000..9d296b89a8
--- /dev/null
+++ b/dts/Bindings/clock/qcom,rpmcc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPM Clock Controller
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description: |
+ The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
+ come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
+ an "active" clock, which means that the consumer only care that the clock is
+ available when the apps CPU subsystem is active, i.e. not suspended or in
+ deep idle. If it is important that the clock keeps running during system
+ suspend, you need to specify the non-active clock, the one not containing
+ *_A_* in the enumerator name.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,rpmcc-apq8060
+ - qcom,rpmcc-apq8064
+ - qcom,rpmcc-ipq806x
+ - qcom,rpmcc-mdm9607
+ - qcom,rpmcc-msm8226
+ - qcom,rpmcc-msm8660
+ - qcom,rpmcc-msm8916
+ - qcom,rpmcc-msm8936
+ - qcom,rpmcc-msm8953
+ - qcom,rpmcc-msm8974
+ - qcom,rpmcc-msm8976
+ - qcom,rpmcc-msm8992
+ - qcom,rpmcc-msm8994
+ - qcom,rpmcc-msm8996
+ - qcom,rpmcc-msm8998
+ - qcom,rpmcc-qcm2290
+ - qcom,rpmcc-qcs404
+ - qcom,rpmcc-sdm660
+ - qcom,rpmcc-sm6115
+ - qcom,rpmcc-sm6125
+ - const: qcom,rpmcc
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xo
+
+required:
+ - compatible
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ rpm {
+ rpm-requests {
+ compatible = "qcom,rpm-msm8916";
+ qcom,smd-channels = "rpm_requests";
+
+ clock-controller {
+ compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
new file mode 100644
index 0000000000..bad9135489
--- /dev/null
+++ b/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm LPASS core and audio clock control module which supports the
+ clocks and power domains on SC7280.
+
+ See also:
+ - dt-bindings/clock/qcom,lpasscorecc-sc7280.h
+ - dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
+
+properties:
+ clocks: true
+
+ clock-names: true
+
+ compatible:
+ enum:
+ - qcom,sc7280-lpassaoncc
+ - qcom,sc7280-lpassaudiocc
+ - qcom,sc7280-lpasscorecc
+ - qcom,sc7280-lpasshm
+
+ power-domains:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7280-lpassaudiocc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: lpass_aon_cc_main_rcg_clk_src
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-lpassaoncc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board XO active only source
+ - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: iface
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-lpasshm
+ - qcom,sc7280-lpasscorecc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
+ lpass_audiocc: clock-controller@3300000 {
+ compatible = "qcom,sc7280-lpassaudiocc";
+ reg = <0x3300000 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
+ clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
+ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
+ lpass_hm: clock-controller@3c00000 {
+ compatible = "qcom,sc7280-lpasshm";
+ reg = <0x3c00000 0x28>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
+ lpasscore: clock-controller@3900000 {
+ compatible = "qcom,sc7280-lpasscorecc";
+ reg = <0x3900000 0x50000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
+ lpass_aon: clock-controller@3380000 {
+ compatible = "qcom,sc7280-lpassaoncc";
+ reg = <0x3380000 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
+ <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml
index e0b86214f0..e57bc40d30 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.yaml
+++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml
@@ -49,6 +49,7 @@ properties:
- renesas,r8a77995-cpg-mssr # R-Car D3
- renesas,r8a779a0-cpg-mssr # R-Car V3U
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
+ - renesas,r8a779g0-cpg-mssr # R-Car V4H
reg:
maxItems: 1
diff --git a/dts/Bindings/clock/renesas,h8300-div-clock.txt b/dts/Bindings/clock/renesas,h8300-div-clock.txt
deleted file mode 100644
index 399e0da223..0000000000
--- a/dts/Bindings/clock/renesas,h8300-div-clock.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Renesas H8/300 divider clock
-
-Required Properties:
-
- - compatible: Must be "renesas,h8300-div-clock"
-
- - clocks: Reference to the parent clocks ("extal1" and "extal2")
-
- - #clock-cells: Must be 1
-
- - reg: Base address and length of the divide rate selector
-
- - renesas,width: bit width of selector
-
-Example
--------
-
- cclk: cclk {
- compatible = "renesas,h8300-div-clock";
- clocks = <&xclk>;
- #clock-cells = <0>;
- reg = <0xfee01b 2>;
- renesas,width = <2>;
- };
diff --git a/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt b/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt
deleted file mode 100644
index 500cdadbce..0000000000
--- a/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Renesas H8S2678 PLL clock
-
-This device is Clock multiplyer
-
-Required Properties:
-
- - compatible: Must be "renesas,h8s2678-pll-clock"
-
- - clocks: Reference to the parent clocks
-
- - #clock-cells: Must be 0
-
- - reg: Two rate selector (Multiply / Divide) register address
-
-Example
--------
-
- pllclk: pllclk {
- compatible = "renesas,h8s2678-pll-clock";
- clocks = <&xclk>;
- #clock-cells = <0>;
- reg = <0xfee03b 2>, <0xfee045 2>;
- };
diff --git a/dts/Bindings/clock/renesas,r9a06g032-sysctrl.yaml b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
index 25dbb0fac0..95bf485c6c 100644
--- a/dts/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
+++ b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
@@ -39,6 +39,17 @@ properties:
'#power-domain-cells':
const: 0
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^dma-router@[a-f0-9]+$":
+ type: object
+ $ref: "../dma/renesas,rzn1-dmamux.yaml#"
+
required:
- compatible
- reg
diff --git a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc61..8880b834f2 100644
--- a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,14 +4,15 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
- On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
- Standby Mode share the same register block.
+ On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
+ Standby Mode share the same register block. On RZ/V2M, the functionality is
+ similar, but does not have Clock Monitor Registers.
They provide the following functionalities:
- The CPG block generates various core clocks,
@@ -23,8 +24,10 @@ description: |
properties:
compatible:
enum:
- - renesas,r9a07g044-cpg # RZ/G2{L,LC}
- - renesas,r9a07g054-cpg # RZ/V2L
+ - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L
+ - renesas,r9a09g011-cpg # RZ/V2M
reg:
maxItems: 1
@@ -42,9 +45,10 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/r9a07g*-cpg.h>
+ <dt-bindings/clock/r9a0*-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
+ a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
+ <dt-bindings/clock/r9a09g011-cpg.h>.
const: 2
'#power-domain-cells':
@@ -58,7 +62,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
- the <dt-bindings/clock/r9a07g0*-cpg.h>.
+ the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
const: 1
required:
diff --git a/dts/Bindings/clock/rockchip,px30-cru.txt b/dts/Bindings/clock/rockchip,px30-cru.txt
deleted file mode 100644
index 55e78cddec..0000000000
--- a/dts/Bindings/clock/rockchip,px30-cru.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-* Rockchip PX30 Clock and Reset Unit
-
-The PX30 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
-- compatible: CRU should be "rockchip,px30-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed
- in clock-names
-- clock-names: Should contain the following:
- - "xin24m" for both PMUCRU and CRU
- - "gpll" for CRU (sourced from PMUCRU)
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "i2sx_clkin" - external I2S clock - optional,
- - "gmac_clkin" - external GMAC clock - optional
-
-Example: Clock controller node:
-
- pmucru: clock-controller@ff2bc000 {
- compatible = "rockchip,px30-pmucru";
- reg = <0x0 0xff2bc000 0x0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@ff2b0000 {
- compatible = "rockchip,px30-cru";
- reg = <0x0 0xff2b0000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@ff030000 {
- compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff030000 0x0 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- };
diff --git a/dts/Bindings/clock/rockchip,px30-cru.yaml b/dts/Bindings/clock/rockchip,px30-cru.yaml
new file mode 100644
index 0000000000..3eec381c7c
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,px30-cru.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip PX30 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The PX30 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "xin32k" - rtc clock - optional
+ - "i2sx_clkin" - external I2S clock - optional
+ - "gmac_clkin" - external GMAC clock - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-cru
+ - rockchip,px30-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: Clock for both PMUCRU and CRU
+ - description: Clock for CRU (sourced from PMUCRU)
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: xin24m
+ - const: gpll
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,px30-cru
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ clock-names:
+ minItems: 2
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/px30-cru.h>
+
+ pmucru: clock-controller@ff2bc000 {
+ compatible = "rockchip,px30-pmucru";
+ reg = <0xff2bc000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff2b0000 {
+ compatible = "rockchip,px30-cru";
+ reg = <0xff2b0000 0x1000>;
+ clocks = <&xin24m>, <&pmucru PLL_GPLL>;
+ clock-names = "xin24m", "gpll";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3036-cru.txt b/dts/Bindings/clock/rockchip,rk3036-cru.txt
deleted file mode 100644
index 20df350b9e..0000000000
--- a/dts/Bindings/clock/rockchip,rk3036-cru.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* Rockchip RK3036 Clock and Reset Unit
-
-The RK3036 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3036-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_i2s" - external I2S clock - optional,
- - "rmii_clkin" - external EMAC clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3036-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@20060000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rk3036-cru.yaml b/dts/Bindings/clock/rockchip,rk3036-cru.yaml
new file mode 100644
index 0000000000..1376230fed
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3036-cru.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3036 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3036 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "ext_i2s" - external I2S clock - optional
+ - "rmii_clkin" - external EMAC clock - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3036-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3188-cru.txt b/dts/Bindings/clock/rockchip,rk3188-cru.txt
deleted file mode 100644
index 7f368530a2..0000000000
--- a/dts/Bindings/clock/rockchip,rk3188-cru.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Rockchip RK3188/RK3066 Clock and Reset Unit
-
-The RK3188/RK3066 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
- "rockchip,rk3066a-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
-dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
-Similar macros exist for the reset sources in these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "xin27m" - 27mhz crystal input on rk3066 - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_cif0" - external camera clock - optional,
- - "ext_rmii" - external RMII clock - optional,
- - "ext_jtag" - externalJTAG clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3188-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rk3188-cru.yaml b/dts/Bindings/clock/rockchip,rk3188-cru.yaml
new file mode 100644
index 0000000000..ddd7e46af0
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3188-cru.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3188/RK3066 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
+ dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
+ Similar macros exist for the reset sources in these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "xin32k" - RTC clock - optional
+ - "xin27m" - 27mhz crystal input on RK3066 - optional
+ - "ext_hsadc" - external HSADC clock - optional
+ - "ext_cif0" - external camera clock - optional
+ - "ext_rmii" - external RMII clock - optional
+ - "ext_jtag" - external JTAG clock - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3066a-cru
+ - rockchip,rk3188-cru
+ - rockchip,rk3188a-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3188-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3228-cru.txt b/dts/Bindings/clock/rockchip,rk3228-cru.txt
deleted file mode 100644
index f323048127..0000000000
--- a/dts/Bindings/clock/rockchip,rk3228-cru.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Rockchip RK3228 Clock and Reset Unit
-
-The RK3228 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3228-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_gmac" - external GMAC clock - optional
- - "ext_hsadc" - external HSADC clock - optional
- - "phy_50m_out" - output clock of the pll in the mac phy
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3228-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10110000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10110000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rk3228-cru.yaml b/dts/Bindings/clock/rockchip,rk3228-cru.yaml
new file mode 100644
index 0000000000..cf7dc01d94
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3228-cru.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3228 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3228 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "ext_i2s" - external I2S clock - optional
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3228-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3228-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3288-cru.txt b/dts/Bindings/clock/rockchip,rk3288-cru.txt
deleted file mode 100644
index bf3a9ec192..0000000000
--- a/dts/Bindings/clock/rockchip,rk3288-cru.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Rockchip RK3288 Clock and Reset Unit
-
-The RK3288 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-A revision of this SoC is available: rk3288w. The clock tree is a bit
-different so another dt-compatible is available. Noticed that it is only
-setting the difference but there is no automatic revision detection. This
-should be performed by bootloaders.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
- case of this revision of Rockchip rk3288.
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_edp_24m" - external display port clock - optional,
- - "ext_vip" - external VIP clock - optional,
- - "ext_isp" - external ISP clock - optional,
- - "ext_jtag" - external JTAG clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3188-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rk3288-cru.yaml b/dts/Bindings/clock/rockchip,rk3288-cru.yaml
new file mode 100644
index 0000000000..96bc05749e
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3288-cru.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3288 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3288 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+
+ A revision of this SoC is available: rk3288w. The clock tree is a bit
+ different so another dt-compatible is available. Noticed that it is only
+ setting the difference but there is no automatic revision detection. This
+ should be performed by boot loaders.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_edp_24m" - external display port clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3288-cru
+ - rockchip,rk3288w-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3288-cru";
+ reg = <0xff760000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3308-cru.txt b/dts/Bindings/clock/rockchip,rk3308-cru.txt
deleted file mode 100644
index 9b151c5b0c..0000000000
--- a/dts/Bindings/clock/rockchip,rk3308-cru.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-* Rockchip RK3308 Clock and Reset Unit
-
-The RK3308 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: CRU should be "rockchip,rk3308-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
- "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
- "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
- - "mac_clkin" - external MAC clock - optional
-
-Example: Clock controller node:
-
- cru: clock-controller@ff500000 {
- compatible = "rockchip,rk3308-cru";
- reg = <0x0 0xff500000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@ff0a0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0a0000 0x0 0x100>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
diff --git a/dts/Bindings/clock/rockchip,rk3308-cru.yaml b/dts/Bindings/clock/rockchip,rk3308-cru.yaml
new file mode 100644
index 0000000000..523ee578a5
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3308-cru.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3308 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3308 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "xin32k" - rtc clock - optional
+ - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
+ "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
+ "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
+ SPDIF clock - optional
+ - "mac_clkin" - external MAC clock - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3308-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff500000 {
+ compatible = "rockchip,rk3308-cru";
+ reg = <0xff500000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3368-cru.txt b/dts/Bindings/clock/rockchip,rk3368-cru.txt
deleted file mode 100644
index 7c8bbcfed8..0000000000
--- a/dts/Bindings/clock/rockchip,rk3368-cru.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Rockchip RK3368 Clock and Reset Unit
-
-The RK3368 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3368-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_gmac" - external GMAC clock - optional
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_isp" - external ISP clock - optional,
- - "ext_jtag" - external JTAG clock - optional
- - "ext_vip" - external VIP clock - optional,
- - "usbotg_out" - output clock of the pll in the otg phy
-
-Example: Clock controller node:
-
- cru: clock-controller@ff760000 {
- compatible = "rockchip,rk3368-cru";
- reg = <0x0 0xff760000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rk3368-cru.yaml b/dts/Bindings/clock/rockchip,rk3368-cru.yaml
new file mode 100644
index 0000000000..adb6787772
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3368-cru.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3368 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3368 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "xin32k" - rtc clock - optional
+ - "ext_i2s" - external I2S clock - optional
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional
+ - "ext_isp" - external ISP clock - optional
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3368-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3368-cru";
+ reg = <0xff760000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/rockchip,rk3399-cru.yaml b/dts/Bindings/clock/rockchip,rk3399-cru.yaml
index 72b286a1be..54da1e31ea 100644
--- a/dts/Bindings/clock/rockchip,rk3399-cru.yaml
+++ b/dts/Bindings/clock/rockchip,rk3399-cru.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3399 Clock and Reset Unit
maintainers:
- - Xing Zheng <zhengxing@rock-chips.com>
+ - Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
@@ -22,11 +22,11 @@ description: |
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "clkin_gmac" - external GMAC clock - optional,
- - "clkin_i2s" - external I2S clock - optional,
- - "pclkin_cif" - external ISP clock - optional,
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "clkin_gmac" - external GMAC clock - optional,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "pclkin_cif" - external ISP clock - optional,
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
@@ -46,24 +46,15 @@ properties:
const: 1
clocks:
- minItems: 1
-
- assigned-clocks:
- minItems: 1
- maxItems: 64
-
- assigned-clock-parents:
- minItems: 1
- maxItems: 64
+ maxItems: 1
- assigned-clock-rates:
- minItems: 1
- maxItems: 64
+ clock-names:
+ const: xin24m
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
- description: >
- phandle to the syscon managing the "general register files". It is used
+ description:
+ Phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.
@@ -77,7 +68,7 @@ additionalProperties: false
examples:
- |
- pmucru: pmu-clock-controller@ff750000 {
+ pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0xff750000 0x1000>;
#clock-cells = <1>;
diff --git a/dts/Bindings/clock/rockchip,rk3568-cru.yaml b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
index b2c2609782..fc7546f521 100644
--- a/dts/Bindings/clock/rockchip,rk3568-cru.yaml
+++ b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
@@ -34,6 +34,19 @@ properties:
"#reset-cells":
const: 1
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
required:
- compatible
- reg
diff --git a/dts/Bindings/clock/rockchip,rv1108-cru.txt b/dts/Bindings/clock/rockchip,rv1108-cru.txt
deleted file mode 100644
index 161326a4f9..0000000000
--- a/dts/Bindings/clock/rockchip,rv1108-cru.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Rockchip RV1108 Clock and Reset Unit
-
-The RV1108 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rv1108-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_vip" - external VIP clock - optional
- - "ext_i2s" - external I2S clock - optional
- - "ext_gmac" - external GMAC clock - optional
- - "hdmiphy" - external clock input derived from HDMI PHY - optional
- - "usbphy" - external clock input derived from USB PHY - optional
-
-Example: Clock controller node:
-
- cru: cru@20200000 {
- compatible = "rockchip,rv1108-cru";
- reg = <0x20200000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10230000 {
- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
- reg = <0x10230000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/dts/Bindings/clock/rockchip,rv1108-cru.yaml b/dts/Bindings/clock/rockchip,rv1108-cru.yaml
new file mode 100644
index 0000000000..20421c22f1
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rv1108-cru.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1108 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RV1108 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required
+ - "ext_vip" - external VIP clock - optional
+ - "ext_i2s" - external I2S clock - optional
+ - "ext_gmac" - external GMAC clock - optional
+ - "hdmiphy" - external clock input derived from HDMI PHY - optional
+ - "usbphy" - external clock input derived from USB PHY - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1108-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rv1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/samsung,exynos4412-isp-clock.yaml b/dts/Bindings/clock/samsung,exynos4412-isp-clock.yaml
index b644bbd0df..bee13436d1 100644
--- a/dts/Bindings/clock/samsung,exynos4412-isp-clock.yaml
+++ b/dts/Bindings/clock/samsung,exynos4412-isp-clock.yaml
@@ -61,4 +61,3 @@ examples:
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
clock-names = "aclk200", "aclk400_mcuisp";
};
-
diff --git a/dts/Bindings/clock/samsung,exynosautov9-clock.yaml b/dts/Bindings/clock/samsung,exynosautov9-clock.yaml
new file mode 100644
index 0000000000..eafc715d2d
--- /dev/null
+++ b/dts/Bindings/clock/samsung,exynosautov9-clock.yaml
@@ -0,0 +1,219 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Auto v9 SoC clock controller
+
+maintainers:
+ - Chanho Park <chanho61.park@samsung.com>
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzk@kernel.org>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Exynos Auto v9 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. Root clocks in that clock tree are
+ two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
+ The external OSCCLK must be defined as fixed-rate clock in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other clocks of function blocks (other CMUs) are usually
+ derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'include/dt-bindings/clock/samsung,exynosautov9.h' header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynosautov9-cmu-top
+ - samsung,exynosautov9-cmu-busmc
+ - samsung,exynosautov9-cmu-core
+ - samsung,exynosautov9-cmu-fsys2
+ - samsung,exynosautov9-cmu-peric0
+ - samsung,exynosautov9-cmu-peric1
+ - samsung,exynosautov9-cmu-peris
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-busmc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_BUSMC bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_busmc_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_CORE bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_core_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-fsys2
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_FSYS2 bus clock (from CMU_TOP)
+ - description: UFS clock (from CMU_TOP)
+ - description: Ethernet clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_fsys2_bus
+ - const: dout_fsys2_clkcmu_ufs_embd
+ - const: dout_fsys2_clkcmu_ethernet
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-peric0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERIC0 bus clock (from CMU_TOP)
+ - description: PERIC0 IP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_peric0_bus
+ - const: dout_clkcmu_peric0_ip
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-peric1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERIC1 bus clock (from CMU_TOP)
+ - description: PERIC1 IP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_peric1_bus
+ - const: dout_clkcmu_peric1_ip
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov9-cmu-peris
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERIS bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_peris_bus
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS2
+ - |
+ #include <dt-bindings/clock/samsung,exynosautov9.h>
+
+ cmu_fsys2: clock-controller@17c00000 {
+ compatible = "samsung,exynosautov9-cmu-fsys2";
+ reg = <0x17c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
+ <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
+ clock-names = "oscclk",
+ "dout_clkcmu_fsys2_bus",
+ "dout_fsys2_clkcmu_ufs_embd",
+ "dout_fsys2_clkcmu_ethernet";
+ };
+
+...
diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.yaml b/dts/Bindings/clock/st,stm32mp1-rcc.yaml
index a0ae4867ed..f8c4742278 100644
--- a/dts/Bindings/clock/st,stm32mp1-rcc.yaml
+++ b/dts/Bindings/clock/st,stm32mp1-rcc.yaml
@@ -41,6 +41,7 @@ description: |
The list of valid indices for STM32MP1 is available in:
include/dt-bindings/reset-controller/stm32mp1-resets.h
+ include/dt-bindings/reset-controller/stm32mp13-resets.h
This file implements defines like:
#define LTDC_R 3072
@@ -57,7 +58,10 @@ properties:
- enum:
- st,stm32mp1-rcc-secure
- st,stm32mp1-rcc
+ - st,stm32mp13-rcc
- const: syscon
+ clocks: true
+ clock-names: true
reg:
maxItems: 1
@@ -68,14 +72,53 @@ required:
- compatible
- reg
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp1-rcc-secure
+then:
+ properties:
+ clocks:
+ description: Specifies oscillators.
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: hse
+ - const: hsi
+ - const: csi
+ - const: lse
+ - const: lsi
+ required:
+ - clocks
+ - clock-names
+else:
+ properties:
+ clocks:
+ description:
+ Specifies the external RX clock for ethernet MAC.
+ maxItems: 1
+
+ clock-names:
+ const: ETH_RX_CLK/ETH_REF_CLK
+
additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc-secure", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
};
...
diff --git a/dts/Bindings/clock/stericsson,u8500-clks.yaml b/dts/Bindings/clock/stericsson,u8500-clks.yaml
index 9bc95a3084..2150307219 100644
--- a/dts/Bindings/clock/stericsson,u8500-clks.yaml
+++ b/dts/Bindings/clock/stericsson,u8500-clks.yaml
@@ -109,6 +109,25 @@ properties:
additionalProperties: false
+ clkout-clock:
+ description: A subnode with three clock cells for externally routed clocks,
+ output clocks. These are two PRCMU-internal clocks that can be divided and
+ muxed out on the pads of the DB8500 SoC.
+ type: object
+
+ properties:
+ '#clock-cells':
+ description:
+ The first cell indicates which output clock we are using,
+ possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
+ The second cell indicates which clock we want to use as source,
+ possible values are 0 thru 7, see the defines for the different
+ source clocks.
+ The third cell is a divider, legal values are 1 thru 63.
+ const: 3
+
+ additionalProperties: false
+
required:
- compatible
- reg
@@ -119,3 +138,41 @@ required:
- smp-twd-clock
additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ste-db8500-clkout.h>
+ clocks@8012 {
+ compatible = "stericsson,u8500-clks";
+ reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
+ <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
+ <0xa03cf000 0x1000>;
+
+ prcmu_clk: prcmu-clock {
+ #clock-cells = <1>;
+ };
+
+ prcc_pclk: prcc-periph-clock {
+ #clock-cells = <2>;
+ };
+
+ prcc_kclk: prcc-kernel-clock {
+ #clock-cells = <2>;
+ };
+
+ prcc_reset: prcc-reset-controller {
+ #reset-cells = <2>;
+ };
+
+ rtc_clk: rtc32k-clock {
+ #clock-cells = <0>;
+ };
+
+ smp_twd_clk: smp-twd-clock {
+ #clock-cells = <0>;
+ };
+
+ clkout_clk: clkout-clock {
+ #clock-cells = <3>;
+ };
+ };
diff --git a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
index 9b537bc876..66765116af 100644
--- a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
+++ b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -15,6 +15,7 @@ properties:
- enum:
- ti,am654-ehrpwm-tbclk
- ti,am64-epwm-tbclk
+ - ti,am62-epwm-tbclk
- const: syscon
"#clock-cells":
diff --git a/dts/Bindings/clock/ti-clkctrl.txt b/dts/Bindings/clock/ti-clkctrl.txt
index 18af6b9409..d20db7974a 100644
--- a/dts/Bindings/clock/ti-clkctrl.txt
+++ b/dts/Bindings/clock/ti-clkctrl.txt
@@ -21,6 +21,7 @@ Required properties :
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
+- clock-output-names : from common clock binding
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
clock index
@@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430:
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_per";
reg = <0x20 0x1b0>;
#clock-cells = <2>;
};
diff --git a/dts/Bindings/clock/ti/clockdomain.txt b/dts/Bindings/clock/ti/clockdomain.txt
index cb76b3f2b3..9c6199249c 100644
--- a/dts/Bindings/clock/ti/clockdomain.txt
+++ b/dts/Bindings/clock/ti/clockdomain.txt
@@ -17,6 +17,9 @@ Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain
+Optional properties:
+- clock-output-names : from common clock binding.
+
Examples:
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
diff --git a/dts/Bindings/clock/ti/composite.txt b/dts/Bindings/clock/ti/composite.txt
index 5f43c4706b..33ac7c9ad0 100644
--- a/dts/Bindings/clock/ti/composite.txt
+++ b/dts/Bindings/clock/ti/composite.txt
@@ -27,6 +27,9 @@ Required properties:
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.
+Optional properties:
+- clock-output-names : from common clock binding.
+
Examples:
usb_l4_gate_ick: usb_l4_gate_ick {
diff --git a/dts/Bindings/clock/ti/fixed-factor-clock.txt b/dts/Bindings/clock/ti/fixed-factor-clock.txt
index 662b36d53b..518e3c1422 100644
--- a/dts/Bindings/clock/ti/fixed-factor-clock.txt
+++ b/dts/Bindings/clock/ti/fixed-factor-clock.txt
@@ -16,6 +16,7 @@ Required properties:
- clocks: parent clock.
Optional properties:
+- clock-output-names : from common clock binding.
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
see [2]
- reg: offset for the autoidle register of this clock, see [2]
diff --git a/dts/Bindings/clock/ti/gate.txt b/dts/Bindings/clock/ti/gate.txt
index 56d603c1f7..b4820b1de4 100644
--- a/dts/Bindings/clock/ti/gate.txt
+++ b/dts/Bindings/clock/ti/gate.txt
@@ -36,6 +36,7 @@ Required properties:
ti,clkdm-gate-clock type
Optional properties:
+- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for programming the clock gate, invalid for
ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
diff --git a/dts/Bindings/clock/ti/interface.txt b/dts/Bindings/clock/ti/interface.txt
index 3f47040401..94ec77dc3c 100644
--- a/dts/Bindings/clock/ti/interface.txt
+++ b/dts/Bindings/clock/ti/interface.txt
@@ -28,6 +28,7 @@ Required properties:
- reg : base address for the control register
Optional properties:
+- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
Examples:
diff --git a/dts/Bindings/clock/ti/mux.txt b/dts/Bindings/clock/ti/mux.txt
index eec8994b9b..e17425a586 100644
--- a/dts/Bindings/clock/ti/mux.txt
+++ b/dts/Bindings/clock/ti/mux.txt
@@ -42,6 +42,7 @@ Required properties:
- reg : register offset for register controlling adjustable mux
Optional properties:
+- clock-output-names : from common clock binding.
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
index b8233ec91d..e0a4ba599a 100644
--- a/dts/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -20,6 +20,13 @@ Optional properties:
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
+- mediatek,cci:
+ Used to confirm the link status between cpufreq and mediatek cci. Because
+ cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
+ To prevent the issue of high frequency and low voltage, we need to use this
+ property to make sure mediatek cci is ready.
+ For details of mediatek cci, please refer to
+ Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
diff --git a/dts/Bindings/crypto/allwinner,sun8i-ce.yaml b/dts/Bindings/crypto/allwinner,sun8i-ce.yaml
index 00648f9d92..026a9f9e1a 100644
--- a/dts/Bindings/crypto/allwinner,sun8i-ce.yaml
+++ b/dts/Bindings/crypto/allwinner,sun8i-ce.yaml
@@ -82,4 +82,3 @@ examples:
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CE>;
};
-
diff --git a/dts/Bindings/crypto/ti,sa2ul.yaml b/dts/Bindings/crypto/ti,sa2ul.yaml
index a410d2cedd..02f47c2e79 100644
--- a/dts/Bindings/crypto/ti,sa2ul.yaml
+++ b/dts/Bindings/crypto/ti,sa2ul.yaml
@@ -15,6 +15,7 @@ properties:
- ti,j721e-sa2ul
- ti,am654-sa2ul
- ti,am64-sa2ul
+ - ti,am62-sa3ul
reg:
maxItems: 1
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
deleted file mode 100644
index 58fc8a6ceb..0000000000
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ /dev/null
@@ -1,212 +0,0 @@
-* Rockchip rk3399 DMC (Dynamic Memory Controller) device
-
-Required properties:
-- compatible: Must be "rockchip,rk3399-dmc".
-- devfreq-events: Node to get DDR loading, Refer to
- Documentation/devicetree/bindings/devfreq/event/
- rockchip-dfi.txt
-- clocks: Phandles for clock specified in "clock-names" property
-- clock-names : The name of clock used by the DFI, must be
- "pclk_ddr_mon";
-- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
- for details.
-- center-supply: DMC supply node.
-- status: Marks the node enabled/disabled.
-- rockchip,pmu: Phandle to the syscon managing the "PMU general register
- files".
-
-Optional properties:
-- interrupts: The CPU interrupt number. The interrupt specifier
- format depends on the interrupt controller.
- It should be a DCF interrupt. When DDR DVFS finishes
- a DCF interrupt is triggered.
-- rockchip,pmu: Phandle to the syscon managing the "PMU general register
- files".
-
-Following properties relate to DDR timing:
-
-- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
- it selects the DDR3 cl-trp-trcd type. It must be
- set according to "Speed Bin" in DDR3 datasheet,
- DO NOT use a smaller "Speed Bin" than specified
- for the DDR3 being used.
-
-- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
- power-down idle period in which memories are
- placed into power-down mode if bus is idle
- for PD_IDLE DFI clock cycles.
-
-- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
- self-refresh idle period in which memories are
- placed into self-refresh mode if bus is idle
- for SR_IDLE * 1024 DFI clock cycles (DFI
- clocks freq is half of DRAM clock), default
- value is "0".
-
-- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
- clock gating idle period. Memories are placed
- into self-refresh mode and memory controller
- clock arg gating started if bus is idle for
- sr_mc_gate_idle*1024 DFI clock cycles.
-
-- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
- period in which memories are placed into
- self-refresh power down mode if bus is idle
- for srpd_lite_idle * 1024 DFI clock cycles.
- This parameter is for LPDDR4 only.
-
-- rockchip,standby_idle : Defines the standby idle period in which
- memories are placed into self-refresh mode.
- The controller, pi, PHY and DRAM clock will
- be gated if bus is idle for standby_idle * DFI
- clock cycles.
-
-- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
- When DDR frequency is less than DRAM_DLL_DISB_FREQ,
- DDR3 DLL will be bypassed. Note: if DLL was bypassed,
- the odt will also stop working.
-
-- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
- MHz (Mega Hz). When DDR frequency is less than
- DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
- Note: PHY DLL and PHY ODT are independent.
-
-- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
- the ODT disable frequency in MHz (Mega Hz).
- when the DDR frequency is less then ddr3_odt_dis_freq,
- the ODT on the DRAM side and controller side are
- both disabled.
-
-- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 40.
-
-- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the DRAM side ODT strength in ohms. Default value
- is 120.
-
-- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
- the phy side CA line (incluing command line,
- address line and clock line) driver strength.
- Default value is 40.
-
-- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 40.
-
-- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the PHY side ODT strength. Default value is 240.
-
-- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
- then ODT disable frequency in MHz (Mega Hz).
- When DDR frequency is less then ddr3_odt_dis_freq,
- the ODT on the DRAM side and controller side are
- both disabled.
-
-- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 34.
-
-- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
- the DRAM side ODT strength in ohms. Default value
- is 240.
-
-- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
- the PHY side CA line (including command line,
- address line and clock line) driver strength.
- Default value is 40.
-
-- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 40.
-
-- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
- the phy side odt strength, default value is 240.
-
-- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
- defines the ODT disable frequency in
- MHz (Mega Hz). When the DDR frequency is less then
- ddr3_odt_dis_freq, the ODT on the DRAM side and
- controller side are both disabled.
-
-- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 60.
-
-- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side ODT on DQS/DQ line strength in ohms.
- Default value is 40.
-
-- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side ODT on CA line strength in ohms.
- Default value is 40.
-
-- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side CA line (including command address
- line) driver strength. Default value is 40.
-
-- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side clock line and CS line driver
- strength. Default value is 80.
-
-- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 80.
-
-- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
- the PHY side ODT strength. Default value is 60.
-
-Example:
- dmc_opp_table: dmc_opp_table {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <666000000>;
- opp-microvolt = <900000>;
- };
- };
-
- dmc: dmc {
- compatible = "rockchip,rk3399-dmc";
- devfreq-events = <&dfi>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_DDRC>;
- clock-names = "dmc_clk";
- operating-points-v2 = <&dmc_opp_table>;
- center-supply = <&ppvar_centerlogic>;
- upthreshold = <15>;
- downdifferential = <10>;
- rockchip,ddr3_speed_bin = <21>;
- rockchip,pd_idle = <0x40>;
- rockchip,sr_idle = <0x2>;
- rockchip,sr_mc_gate_idle = <0x3>;
- rockchip,srpd_lite_idle = <0x4>;
- rockchip,standby_idle = <0x2000>;
- rockchip,dram_dll_dis_freq = <300>;
- rockchip,phy_dll_dis_freq = <125>;
- rockchip,auto_pd_dis_freq = <666>;
- rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,ddr3_drv = <40>;
- rockchip,ddr3_odt = <120>;
- rockchip,phy_ddr3_ca_drv = <40>;
- rockchip,phy_ddr3_dq_drv = <40>;
- rockchip,phy_ddr3_odt = <240>;
- rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_drv = <34>;
- rockchip,lpddr3_odt = <240>;
- rockchip,phy_lpddr3_ca_drv = <40>;
- rockchip,phy_lpddr3_dq_drv = <40>;
- rockchip,phy_lpddr3_odt = <240>;
- rockchip,lpddr4_odt_dis_freq = <333>;
- rockchip,lpddr4_drv = <60>;
- rockchip,lpddr4_dq_odt = <40>;
- rockchip,lpddr4_ca_odt = <40>;
- rockchip,phy_lpddr4_ca_drv = <40>;
- rockchip,phy_lpddr4_ck_cs_drv = <80>;
- rockchip,phy_lpddr4_dq_drv = <80>;
- rockchip,phy_lpddr4_odt = <60>;
- };
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
index d4412aea7b..c388ae5da1 100644
--- a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
+++ b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml
@@ -62,6 +62,7 @@ properties:
- allwinner,sun8i-r40-display-engine
- allwinner,sun8i-v3s-display-engine
- allwinner,sun9i-a80-display-engine
+ - allwinner,sun20i-d1-display-engine
- allwinner,sun50i-a64-display-engine
- allwinner,sun50i-h6-display-engine
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
index 3a7d5d7317..4a92a4c7dc 100644
--- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
+++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
@@ -33,6 +33,8 @@ properties:
- const: allwinner,sun8i-v3s-tcon
- const: allwinner,sun9i-a80-tcon-lcd
- const: allwinner,sun9i-a80-tcon-tv
+ - const: allwinner,sun20i-d1-tcon-lcd
+ - const: allwinner,sun20i-d1-tcon-tv
- items:
- enum:
diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
index 4f91eec26d..cb243bc58e 100644
--- a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+++ b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
@@ -19,6 +19,8 @@ properties:
- allwinner,sun8i-r40-de2-mixer-0
- allwinner,sun8i-r40-de2-mixer-1
- allwinner,sun8i-v3s-de2-mixer
+ - allwinner,sun20i-d1-de2-mixer-0
+ - allwinner,sun20i-d1-de2-mixer-1
- allwinner,sun50i-a64-de2-mixer-0
- allwinner,sun50i-a64-de2-mixer-1
- allwinner,sun50i-h6-de3-mixer-0
diff --git a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
index 61ef7b3372..845e226d7a 100644
--- a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
+++ b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
@@ -41,6 +41,7 @@ properties:
compatible:
enum:
- allwinner,sun8i-r40-tcon-top
+ - allwinner,sun20i-d1-tcon-top
- allwinner,sun50i-h6-tcon-top
reg:
@@ -48,31 +49,15 @@ properties:
clocks:
minItems: 2
- items:
- - description: The TCON TOP interface clock
- - description: The TCON TOP TV0 clock
- - description: The TCON TOP TVE0 clock
- - description: The TCON TOP TV1 clock
- - description: The TCON TOP TVE1 clock
- - description: The TCON TOP MIPI DSI clock
+ maxItems: 6
clock-names:
minItems: 2
- items:
- - const: bus
- - const: tcon-tv0
- - const: tve0
- - const: tcon-tv1
- - const: tve1
- - const: dsi
+ maxItems: 6
clock-output-names:
minItems: 1
maxItems: 3
- description: >
- The first item is the name of the clock created for the TV0
- channel, the second item is the name of the TCON TV1 channel
- clock and the third one is the name of the DSI channel clock.
resets:
maxItems: 1
@@ -129,32 +114,92 @@ required:
additionalProperties: false
-if:
- properties:
- compatible:
- contains:
- const: allwinner,sun50i-h6-tcon-top
-
-then:
- properties:
- clocks:
- maxItems: 2
-
- clock-output-names:
- maxItems: 1
-
-else:
- properties:
- clocks:
- minItems: 6
-
- clock-output-names:
- minItems: 3
-
- ports:
- required:
- - port@2
- - port@3
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun8i-r40-tcon-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: The TCON TOP interface clock
+ - description: The TCON TOP TV0 clock
+ - description: The TCON TOP TVE0 clock
+ - description: The TCON TOP TV1 clock
+ - description: The TCON TOP TVE1 clock
+ - description: The TCON TOP MIPI DSI clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: tcon-tv0
+ - const: tve0
+ - const: tcon-tv1
+ - const: tve1
+ - const: dsi
+
+ clock-output-names:
+ items:
+ - description: TCON TV0 output clock name
+ - description: TCON TV1 output clock name
+ - description: DSI output clock name
+
+ ports:
+ required:
+ - port@2
+ - port@3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun20i-d1-tcon-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: The TCON TOP interface clock
+ - description: The TCON TOP TV0 clock
+ - description: The TCON TOP TVE0 clock
+ - description: The TCON TOP MIPI DSI clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: tcon-tv0
+ - const: tve0
+ - const: dsi
+
+ clock-output-names:
+ items:
+ - description: TCON TV0 output clock name
+ - description: DSI output clock name
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-tcon-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: The TCON TOP interface clock
+ - description: The TCON TOP TV0 clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: tcon-tv0
+
+ clock-output-names:
+ items:
+ - description: TCON TV0 output clock name
examples:
- |
diff --git a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml
index 343598c9f4..2e208d2fc9 100644
--- a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -150,4 +150,3 @@ examples:
};
};
};
-
diff --git a/dts/Bindings/display/arm,hdlcd.txt b/dts/Bindings/display/arm,hdlcd.txt
deleted file mode 100644
index 78bc24296f..0000000000
--- a/dts/Bindings/display/arm,hdlcd.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-ARM HDLCD
-
-This is a display controller found on several development platforms produced
-by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
-streamer that reads the data from a framebuffer and sends it to a single
-digital encoder (DVI or HDMI).
-
-Required properties:
- - compatible: "arm,hdlcd"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: One interrupt used by the display controller to notify the
- interrupt controller when any of the interrupt sources programmed in
- the interrupt mask register have activated.
- - clocks: A list of phandle + clock-specifier pairs, one for each
- entry in 'clock-names'.
- - clock-names: A list of clock names. For HDLCD it should contain:
- - "pxlclk" for the clock feeding the output PLL of the controller.
-
-Required sub-nodes:
- - port: The HDLCD connection to an encoder chip. The connection is modeled
- using the OF graph bindings specified in
- Documentation/devicetree/bindings/graph.txt.
-
-Optional properties:
- - memory-region: phandle to a node describing memory (see
- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
- used for the framebuffer; if not present, the framebuffer may be located
- anywhere in memory.
-
-
-Example:
-
-/ {
- ...
-
- hdlcd@2b000000 {
- compatible = "arm,hdlcd";
- reg = <0 0x2b000000 0 0x1000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&oscclk5>;
- clock-names = "pxlclk";
- port {
- hdlcd_output: endpoint@0 {
- remote-endpoint = <&hdmi_enc_input>;
- };
- };
- };
-
- /* HDMI encoder on I2C bus */
- i2c@7ffa0000 {
- ....
- hdmi-transmitter@70 {
- compatible = ".....";
- reg = <0x70>;
- port@0 {
- hdmi_enc_input: endpoint {
- remote-endpoint = <&hdlcd_output>;
- };
-
- hdmi_enc_output: endpoint {
- remote-endpoint = <&hdmi_1_port>;
- };
- };
- };
-
- };
-
- hdmi1: connector@1 {
- compatible = "hdmi-connector";
- type = "a";
- port {
- hdmi_1_port: endpoint {
- remote-endpoint = <&hdmi_enc_output>;
- };
- };
- };
-
- ...
-};
diff --git a/dts/Bindings/display/arm,hdlcd.yaml b/dts/Bindings/display/arm,hdlcd.yaml
new file mode 100644
index 0000000000..a2670258c4
--- /dev/null
+++ b/dts/Bindings/display/arm,hdlcd.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm HDLCD display controller binding
+
+maintainers:
+ - Liviu Dudau <Liviu.Dudau@arm.com>
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ The Arm HDLCD is a display controller found on several development platforms
+ produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
+ RGB streamer that reads the data from a framebuffer and sends it to a single
+ digital encoder (DVI or HDMI).
+
+properties:
+ compatible:
+ const: arm,hdlcd
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ const: pxlclk
+
+ clocks:
+ maxItems: 1
+ description: The input reference for the pixel clock.
+
+ memory-region:
+ maxItems: 1
+ description:
+ Phandle to a node describing memory to be used for the framebuffer.
+ If not present, the framebuffer may be located anywhere in memory.
+
+ iommus:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+ description:
+ Output endpoint of the controller, connecting the LCD panel signals.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - port
+
+examples:
+ - |
+ hdlcd@2b000000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2b000000 0x1000>;
+ interrupts = <0 85 4>;
+ clocks = <&oscclk5>;
+ clock-names = "pxlclk";
+ port {
+ hdlcd_output: endpoint {
+ remote-endpoint = <&hdmi_enc_input>;
+ };
+ };
+ };
+
+ /* HDMI encoder on I2C bus */
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi-transmitter@70 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
+ port {
+ hdmi_enc_input: endpoint {
+ remote-endpoint = <&hdlcd_output>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/arm,komeda.txt b/dts/Bindings/display/arm,komeda.txt
deleted file mode 100644
index 8513695ee4..0000000000
--- a/dts/Bindings/display/arm,komeda.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-Device Tree bindings for Arm Komeda display driver
-
-Required properties:
-- compatible: Should be "arm,mali-d71"
-- reg: Physical base address and length of the registers in the system
-- interrupts: the interrupt line number of the device in the system
-- clocks: A list of phandle + clock-specifier pairs, one for each entry
- in 'clock-names'
-- clock-names: A list of clock names. It should contain:
- - "aclk": for the main processor clock
-- #address-cells: Must be 1
-- #size-cells: Must be 0
-- iommus: configure the stream id to IOMMU, Must be configured if want to
- enable iommu in display. for how to configure this node please reference
- devicetree/bindings/iommu/arm,smmu-v3.txt,
- devicetree/bindings/iommu/iommu.txt
-
-Required properties for sub-node: pipeline@nq
-Each device contains one or two pipeline sub-nodes (at least one), each
-pipeline node should provide properties:
-- reg: Zero-indexed identifier for the pipeline
-- clocks: A list of phandle + clock-specifier pairs, one for each entry
- in 'clock-names'
-- clock-names: should contain:
- - "pxclk": pixel clock
-
-- port: each pipeline connect to an encoder input port. The connection is
- modeled using the OF graph bindings specified in
- Documentation/devicetree/bindings/graph.txt
-
-Optional properties:
- - memory-region: phandle to a node describing memory (see
- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
- to be used for the framebuffer; if not present, the framebuffer may
- be located anywhere in memory.
-
-Example:
-/ {
- ...
-
- dp0: display@c00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "arm,mali-d71";
- reg = <0xc00000 0x20000>;
- interrupts = <0 168 4>;
- clocks = <&dpu_aclk>;
- clock-names = "aclk";
- iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
- <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
- <&smmu 8>, <&smmu 9>;
-
- dp0_pipe0: pipeline@0 {
- clocks = <&fpgaosc2>;
- clock-names = "pxclk";
- reg = <0>;
-
- port {
- dp0_pipe0_out: endpoint {
- remote-endpoint = <&db_dvi0_in>;
- };
- };
- };
-
- dp0_pipe1: pipeline@1 {
- clocks = <&fpgaosc2>;
- clock-names = "pxclk";
- reg = <1>;
-
- port {
- dp0_pipe1_out: endpoint {
- remote-endpoint = <&db_dvi1_in>;
- };
- };
- };
- };
- ...
-};
diff --git a/dts/Bindings/display/arm,komeda.yaml b/dts/Bindings/display/arm,komeda.yaml
new file mode 100644
index 0000000000..9f4aade97f
--- /dev/null
+++ b/dts/Bindings/display/arm,komeda.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Komeda display processor
+
+maintainers:
+ - Liviu Dudau <Liviu.Dudau@arm.com>
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ The Arm Mali D71 display processor supports up to two displays with up
+ to a 4K resolution each. Each pipeline can be composed of up to four
+ layers. It is typically connected to a digital display connector like HDMI.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,mali-d32
+ - const: arm,mali-d71
+ - const: arm,mali-d71
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ const: aclk
+
+ clocks:
+ maxItems: 1
+ description: The main DPU processor clock
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ memory-region:
+ maxItems: 1
+ description:
+ Phandle to a node describing memory to be used for the framebuffer.
+ If not present, the framebuffer may be located anywhere in memory.
+
+ iommus:
+ description:
+ The stream IDs for each of the used pipelines, each four IDs for the
+ four layers, plus one for the write-back stream.
+ minItems: 5
+ maxItems: 10
+
+patternProperties:
+ '^pipeline@[01]$':
+ type: object
+ description:
+ clocks
+
+ properties:
+ reg:
+ enum: [ 0, 1 ]
+
+ clock-names:
+ const: pxclk
+
+ clocks:
+ maxItems: 1
+ description: The input reference for the pixel clock.
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+additionalProperties: false
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+ - pipeline@0
+
+examples:
+ - |
+ display@c00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "arm,mali-d71";
+ reg = <0xc00000 0x20000>;
+ interrupts = <168>;
+ clocks = <&dpu_aclk>;
+ clock-names = "aclk";
+ iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
+ <&smmu 8>,
+ <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
+ <&smmu 9>;
+
+ dp0_pipe0: pipeline@0 {
+ clocks = <&fpgaosc2>;
+ clock-names = "pxclk";
+ reg = <0>;
+
+ port {
+ dp0_pipe0_out: endpoint {
+ remote-endpoint = <&db_dvi0_in>;
+ };
+ };
+ };
+
+ dp0_pipe1: pipeline@1 {
+ clocks = <&fpgaosc2>;
+ clock-names = "pxclk";
+ reg = <1>;
+
+ port {
+ dp0_pipe1_out: endpoint {
+ remote-endpoint = <&db_dvi1_in>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/arm,malidp.txt b/dts/Bindings/display/arm,malidp.txt
deleted file mode 100644
index 7a97a2b48c..0000000000
--- a/dts/Bindings/display/arm,malidp.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-ARM Mali-DP
-
-The following bindings apply to a family of Display Processors sold as
-licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
-DP650 processors that offer multiple composition layers, support for
-rotation and scaling output.
-
-Required properties:
- - compatible: should be one of
- "arm,mali-dp500"
- "arm,mali-dp550"
- "arm,mali-dp650"
- depending on the particular implementation present in the hardware
- - reg: Physical base address and size of the block of registers used by
- the processor.
- - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
- interrupt client nodes.
- - interrupt-names: name of the engine inside the processor that will
- use the corresponding interrupt. Should be one of "DE" or "SE".
- - clocks: A list of phandle + clock-specifier pairs, one for each entry
- in 'clock-names'
- - clock-names: A list of clock names. It should contain:
- - "pclk": for the APB interface clock
- - "aclk": for the AXI interface clock
- - "mclk": for the main processor clock
- - "pxlclk": for the pixel clock feeding the output PLL of the processor.
- - arm,malidp-output-port-lines: Array of u8 values describing the number
- of output lines per channel (R, G and B).
-
-Required sub-nodes:
- - port: The Mali DP connection to an encoder input port. The connection
- is modelled using the OF graph bindings specified in
- Documentation/devicetree/bindings/graph.txt
-
-Optional properties:
- - memory-region: phandle to a node describing memory (see
- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
- to be used for the framebuffer; if not present, the framebuffer may
- be located anywhere in memory.
- - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
- levels of DP500's QoS signaling.
-
-
-Example:
-
-/ {
- ...
-
- dp0: malidp@6f200000 {
- compatible = "arm,mali-dp650";
- reg = <0 0x6f200000 0 0x20000>;
- memory-region = <&display_reserved>;
- interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
- <0 168 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "DE", "SE";
- clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
- clock-names = "pxlclk", "mclk", "aclk", "pclk";
- arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
- arm,malidp-arqos-high-level = <0xd000d000>;
- port {
- dp0_output: endpoint {
- remote-endpoint = <&tda998x_2_input>;
- };
- };
- };
-
- ...
-};
diff --git a/dts/Bindings/display/arm,malidp.yaml b/dts/Bindings/display/arm,malidp.yaml
new file mode 100644
index 0000000000..795a08ac9f
--- /dev/null
+++ b/dts/Bindings/display/arm,malidp.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/arm,malidp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Mali Display Processor (Mali-DP) binding
+
+maintainers:
+ - Liviu Dudau <Liviu.Dudau@arm.com>
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ The following bindings apply to a family of Display Processors sold as
+ licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
+ DP650 processors that offer multiple composition layers, support for
+ rotation and scaling output.
+
+properties:
+ compatible:
+ enum:
+ - arm,mali-dp500
+ - arm,mali-dp550
+ - arm,mali-dp650
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description:
+ The interrupt used by the Display Engine (DE). Can be shared with
+ the interrupt for the Scaling Engine (SE), but it will have to be
+ listed individually.
+ - description:
+ The interrupt used by the Scaling Engine (SE). Can be shared with
+ the interrupt for the Display Engine (DE), but it will have to be
+ listed individually.
+
+ interrupt-names:
+ items:
+ - const: DE
+ - const: SE
+
+ clock-names:
+ items:
+ - const: pxlclk
+ - const: mclk
+ - const: aclk
+ - const: pclk
+
+ clocks:
+ items:
+ - description: the pixel clock feeding the output PLL of the processor
+ - description: the main processor clock
+ - description: the AXI interface clock
+ - description: the APB interface clock
+
+ memory-region:
+ maxItems: 1
+ description:
+ Phandle to a node describing memory to be used for the framebuffer.
+ If not present, the framebuffer may be located anywhere in memory.
+
+ arm,malidp-output-port-lines:
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ description:
+ Number of output lines/bits for each colour channel.
+ items:
+ - description: number of output lines for the red channel (R)
+ - description: number of output lines for the green channel (G)
+ - description: number of output lines for the blue channel (B)
+
+ arm,malidp-arqos-high-level:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ integer describing the ARQoS levels of DP500's QoS signaling
+
+ arm,malidp-arqos-value:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Quality-of-Service value for the display engine FIFOs, to write
+ into the RQOS register of the DP500.
+ See the ARM Mali-DP500 TRM for details on the encoding.
+ If omitted, the RQOS register will not be changed.
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+ description:
+ Output endpoint of the controller, connecting the LCD panel signals.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - port
+ - arm,malidp-output-port-lines
+
+examples:
+ - |
+ dp0: malidp@6f200000 {
+ compatible = "arm,mali-dp650";
+ reg = <0x6f200000 0x20000>;
+ memory-region = <&display_reserved>;
+ interrupts = <168>, <168>;
+ interrupt-names = "DE", "SE";
+ clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-high-level = <0xd000d000>;
+
+ port {
+ dp0_output: endpoint {
+ remote-endpoint = <&tda998x_2_input>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/arm,pl11x.txt b/dts/Bindings/display/arm,pl11x.txt
deleted file mode 100644
index 3f977e72a2..0000000000
--- a/dts/Bindings/display/arm,pl11x.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-* ARM PrimeCell Color LCD Controller PL110/PL111
-
-See also Documentation/devicetree/bindings/arm/primecell.yaml
-
-Required properties:
-
-- compatible: must be one of:
- "arm,pl110", "arm,primecell"
- "arm,pl111", "arm,primecell"
-
-- reg: base address and size of the control registers block
-
-- interrupt-names: either the single entry "combined" representing a
- combined interrupt output (CLCDINTR), or the four entries
- "mbe", "vcomp", "lnbu", "fuf" representing the individual
- CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
-
-- interrupts: contains an interrupt specifier for each entry in
- interrupt-names
-
-- clock-names: should contain "clcdclk" and "apb_pclk"
-
-- clocks: contains phandle and clock specifier pairs for the entries
- in the clock-names property. See
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Optional properties:
-
-- memory-region: phandle to a node describing memory (see
- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
- to be used for the framebuffer; if not present, the framebuffer
- may be located anywhere in the memory
-
-- max-memory-bandwidth: maximum bandwidth in bytes per second that the
- cell's memory interface can handle; if not present, the memory
- interface is fast enough to handle all possible video modes
-
-Required sub-nodes:
-
-- port: describes LCD panel signals, following the common binding
- for video transmitter interfaces; see
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Deprecated properties:
- The port's endbpoint subnode had this, now deprecated property
- in the past. Drivers should be able to survive without it:
-
- - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
- defining the way CLD pads are wired up; first value
- contains index of the "CLD" external pin (pad) used
- as R0 (first bit of the red component), second value
- index of the pad used as G0, third value index of the
- pad used as B0, see also "LCD panel signal multiplexing
- details" paragraphs in the PL110/PL111 Technical
- Reference Manuals; this implicitly defines available
- color modes, for example:
- - PL111 TFT 4:4:4 panel:
- arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- - PL110 TFT (1:)5:5:5 panel:
- arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- - PL111 TFT (1:)5:5:5 panel:
- arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- - PL111 TFT 5:6:5 panel:
- arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- - PL110 and PL111 TFT 8:8:8 panel:
- arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
- arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
-
-
-Example:
-
- clcd@10020000 {
- compatible = "arm,pl111", "arm,primecell";
- reg = <0x10020000 0x1000>;
- interrupt-names = "combined";
- interrupts = <0 44 4>;
- clocks = <&oscclk1>, <&oscclk2>;
- clock-names = "clcdclk", "apb_pclk";
- max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
-
- port {
- clcd_pads: endpoint {
- remote-endpoint = <&clcd_panel>;
- };
- };
-
- };
-
- panel {
- compatible = "panel-dpi";
-
- port {
- clcd_panel: endpoint {
- remote-endpoint = <&clcd_pads>;
- };
- };
-
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- hback-porch = <40>;
- hfront-porch = <24>;
- hsync-len = <96>;
- vactive = <480>;
- vback-porch = <32>;
- vfront-porch = <11>;
- vsync-len = <2>;
- };
- };
diff --git a/dts/Bindings/display/arm,pl11x.yaml b/dts/Bindings/display/arm,pl11x.yaml
new file mode 100644
index 0000000000..b545c6d203
--- /dev/null
+++ b/dts/Bindings/display/arm,pl11x.yaml
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm PrimeCell Color LCD Controller PL110/PL111
+
+maintainers:
+ - Liviu Dudau <Liviu.Dudau@arm.com>
+ - Andre Przywara <andre.przywara@arm.com>
+
+description:
+ The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
+ a framebuffer region in system memory, and creates timed signals for
+ a variety of LCD panels.
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,pl110
+ - arm,pl111
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,pl110
+ - arm,pl111
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupt-names:
+ oneOf:
+ - const: combined
+ description:
+ The IP provides four individual interrupt lines, but also one
+ combined line. If the integration only connects this line to the
+ interrupt controller, this single interrupt is noted here.
+ - items:
+ - const: mbe # CLCDMBEINTR
+ - const: vcomp # CLCDVCOMPINTR
+ - const: lnbu # CLCDLNBUINTR
+ - const: fuf # CLCDFUFINTR
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: clcdclk
+ - const: apb_pclk
+
+ clocks:
+ items:
+ - description: The CLCDCLK reference clock for the controller.
+ - description: The HCLK AHB slave clock for the register access.
+
+ memory-region:
+ maxItems: 1
+ description:
+ Phandle to a node describing memory to be used for the framebuffer.
+ If not present, the framebuffer may be located anywhere in memory.
+
+ max-memory-bandwidth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Maximum bandwidth in bytes per second that the cell's memory interface
+ can handle.
+ If not present, the memory interface is fast enough to handle all
+ possible video modes.
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ description:
+ Output endpoint of the controller, connecting the LCD panel signals.
+
+ properties:
+ endpoint:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+
+ properties:
+ arm,pl11x,tft-r0g0b0-pads:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: index of CLD pad used for first red bit (R0)
+ - description: index of CLD pad used for first green bit (G0)
+ - description: index of CLD pad used for first blue bit (G0)
+ deprecated: true
+ description: |
+ DEPRECATED. An array of three 32-bit values, defining the way
+ CLD[23:0] pads are wired up.
+ The first value contains the index of the "CLD" external pin (pad)
+ used as R0 (first bit of the red component), the second value for
+ green, the third value for blue.
+ See also "LCD panel signal multiplexing details" paragraphs in the
+ PL110/PL111 Technical Reference Manuals.
+ This implicitly defines available color modes, for example:
+ - PL111 TFT 4:4:4 panel:
+ arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
+ - PL110 TFT (1:)5:5:5 panel:
+ arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
+ - PL111 TFT (1:)5:5:5 panel:
+ arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
+ - PL111 TFT 5:6:5 panel:
+ arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
+ - PL110 and PL111 TFT 8:8:8 panel:
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
+ arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - port
+
+allOf:
+ - if:
+ properties:
+ interrupts:
+ minItems: 2
+ required:
+ - interrupts
+ then:
+ required:
+ - interrupt-names
+
+examples:
+ - |
+ clcd@10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupt-names = "combined";
+ interrupts = <44>;
+ clocks = <&oscclk1>, <&oscclk2>;
+ clock-names = "clcdclk", "apb_pclk";
+ max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
+
+ port {
+ clcd_pads: endpoint {
+ remote-endpoint = <&clcd_panel>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "arm,rtsm-display", "panel-dpi";
+ power-supply = <&vcc_supply>;
+
+ port {
+ clcd_panel: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ hback-porch = <40>;
+ hfront-porch = <24>;
+ hsync-len = <96>;
+ vactive = <480>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ vsync-len = <2>;
+ };
+ };
+...
diff --git a/dts/Bindings/display/bridge/chipone,icn6211.yaml b/dts/Bindings/display/bridge/chipone,icn6211.yaml
index 7257fd0ae4..4f0b7c7131 100644
--- a/dts/Bindings/display/bridge/chipone,icn6211.yaml
+++ b/dts/Bindings/display/bridge/chipone,icn6211.yaml
@@ -41,10 +41,26 @@ properties:
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description:
Video port for MIPI DSI input
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: array of physical DSI data lane indexes.
+ minItems: 1
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
diff --git a/dts/Bindings/display/bridge/fsl,ldb.yaml b/dts/Bindings/display/bridge/fsl,ldb.yaml
new file mode 100644
index 0000000000..77f174eee4
--- /dev/null
+++ b/dts/Bindings/display/bridge/fsl,ldb.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP DPI to LVDS bridge chip
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ The i.MX8MP mediamix contains two registers which are responsible
+ for configuring the on-SoC DPI-to-LVDS serializer. This describes
+ those registers as bridge within the DT.
+
+properties:
+ compatible:
+ const: fsl,imx8mp-ldb
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ldb
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for DPI input.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for LVDS Channel-A output (panel or bridge).
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for LVDS Channel-B output (panel or bridge).
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - clocks
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+
+ blk-ctrl {
+ bridge {
+ compatible = "fsl,imx8mp-ldb";
+ clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+ clock-names = "ldb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ldb_from_lcdif2: endpoint {
+ remote-endpoint = <&lcdif2_to_ldb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&ldb_to_lvdsx4panel>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ldb_lvds_ch1: endpoint {
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml b/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml
index a88a5d8c7b..a44d025d33 100644
--- a/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml
+++ b/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml
@@ -78,4 +78,3 @@ examples:
};
};
};
-
diff --git a/dts/Bindings/display/bridge/ite,it66121.yaml b/dts/Bindings/display/bridge/ite,it66121.yaml
index 6ec1d5fbb8..c6e81f5322 100644
--- a/dts/Bindings/display/bridge/ite,it66121.yaml
+++ b/dts/Bindings/display/bridge/ite,it66121.yaml
@@ -38,6 +38,9 @@ properties:
interrupts:
maxItems: 1
+ "#sound-dai-cells":
+ const: 0
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
diff --git a/dts/Bindings/display/bridge/lontium,lt9211.yaml b/dts/Bindings/display/bridge/lontium,lt9211.yaml
new file mode 100644
index 0000000000..9a6e9b25d1
--- /dev/null
+++ b/dts/Bindings/display/bridge/lontium,lt9211.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/lontium,lt9211.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
+ or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
+
+properties:
+ compatible:
+ enum:
+ - lontium,lt9211
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active high RESET pin.
+
+ vccio-supply:
+ description: Regulator for 1.8V IO power.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Primary MIPI DSI port-1 for MIPI input or
+ LVDS port-1 for LVDS input or DPI input.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Additional MIPI port-2 for MIPI input or LVDS port-2
+ for LVDS input. Used in combination with primary
+ port-1 to drive higher resolution displays
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Primary MIPI DSI port-1 for MIPI output or
+ LVDS port-1 for LVDS output or DPI output.
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Additional MIPI port-2 for MIPI output or LVDS port-2
+ for LVDS output. Used in combination with primary
+ port-1 to drive higher resolution displays.
+
+ required:
+ - port@0
+ - port@2
+
+required:
+ - compatible
+ - reg
+ - vccio-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi-bridge@3b {
+ compatible = "lontium,lt9211";
+ reg = <0x3b>;
+
+ reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
+ interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
+
+ vccio-supply = <&lt9211_1v8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml
index 186e17be51..8ab156e0a8 100644
--- a/dts/Bindings/display/bridge/ps8640.yaml
+++ b/dts/Bindings/display/bridge/ps8640.yaml
@@ -119,4 +119,3 @@ examples:
};
};
};
-
diff --git a/dts/Bindings/display/bridge/toshiba,tc358767.yaml b/dts/Bindings/display/bridge/toshiba,tc358767.yaml
index f1541cc052..ed280053ec 100644
--- a/dts/Bindings/display/bridge/toshiba,tc358767.yaml
+++ b/dts/Bindings/display/bridge/toshiba,tc358767.yaml
@@ -53,16 +53,32 @@ properties:
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description: |
DSI input port. The remote endpoint phandle should be a
reference to a valid DSI output endpoint node
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: array of physical DSI data lane indexes.
+ minItems: 1
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
- DPI input port. The remote endpoint phandle should be a
- reference to a valid DPI output endpoint node
+ DPI input/output port. The remote endpoint phandle should be a
+ reference to a valid DPI output or input endpoint node.
port@2:
$ref: /schemas/graph.yaml#/properties/port
diff --git a/dts/Bindings/display/bridge/toshiba,tc358768.yaml b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
index 3bd670b8e5..0b6f5bef12 100644
--- a/dts/Bindings/display/bridge/toshiba,tc358768.yaml
+++ b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
@@ -58,6 +58,7 @@ properties:
properties:
data-lines:
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [ 16, 18, 24 ]
port@1:
diff --git a/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml
index 0091df9dd7..989ab312c1 100644
--- a/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml
+++ b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -105,4 +105,3 @@ examples:
};
};
};
-
diff --git a/dts/Bindings/display/mediatek/mediatek,aal.yaml b/dts/Bindings/display/mediatek/mediatek,aal.yaml
index 61f0ed1e38..d4d585485e 100644
--- a/dts/Bindings/display/mediatek/mediatek,aal.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,aal.yaml
@@ -21,16 +21,19 @@ description: |
properties:
compatible:
oneOf:
+ - enum:
+ - mediatek,mt8173-disp-aal
+ - mediatek,mt8183-disp-aal
- items:
+ - enum:
+ - mediatek,mt2712-disp-aal
- const: mediatek,mt8173-disp-aal
- items:
- enum:
- - mediatek,mt2712-disp-aal
- - mediatek,mt8183-disp-aal
+ - mediatek,mt8186-disp-aal
- mediatek,mt8192-disp-aal
- mediatek,mt8195-disp-aal
- - enum:
- - mediatek,mt8173-disp-aal
+ - const: mediatek,mt8183-disp-aal
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,ccorr.yaml b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml
index 0ed53b6238..63fb02014a 100644
--- a/dts/Bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,ccorr.yaml
@@ -28,8 +28,11 @@ properties:
- items:
- enum:
- mediatek,mt8195-disp-ccorr
+ - const: mediatek,mt8192-disp-ccorr
+ - items:
- enum:
- - mediatek,mt8192-disp-ccorr
+ - mediatek,mt8186-disp-ccorr
+ - const: mediatek,mt8183-disp-ccorr
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,color.yaml b/dts/Bindings/display/mediatek/mediatek,color.yaml
index 3ad842eb56..d2f89ee799 100644
--- a/dts/Bindings/display/mediatek/mediatek,color.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,color.yaml
@@ -32,15 +32,14 @@ properties:
- enum:
- mediatek,mt7623-disp-color
- mediatek,mt2712-disp-color
- - enum:
- - mediatek,mt2701-disp-color
+ - const: mediatek,mt2701-disp-color
- items:
- enum:
- mediatek,mt8183-disp-color
+ - mediatek,mt8186-disp-color
- mediatek,mt8192-disp-color
- mediatek,mt8195-disp-color
- - enum:
- - mediatek,mt8173-disp-color
+ - const: mediatek,mt8173-disp-color
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,dither.yaml b/dts/Bindings/display/mediatek/mediatek,dither.yaml
index 6657549af1..8ad8187c02 100644
--- a/dts/Bindings/display/mediatek/mediatek,dither.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,dither.yaml
@@ -26,10 +26,10 @@ properties:
- const: mediatek,mt8183-disp-dither
- items:
- enum:
+ - mediatek,mt8186-disp-dither
- mediatek,mt8192-disp-dither
- mediatek,mt8195-disp-dither
- - enum:
- - mediatek,mt8183-disp-dither
+ - const: mediatek,mt8183-disp-dither
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
index 843f89d605..77ee1b9239 100644
--- a/dts/Bindings/display/mediatek/mediatek,dpi.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
+ - mediatek,mt8186-dpi
- mediatek,mt8192-dpi
reg:
diff --git a/dts/Bindings/display/mediatek/mediatek,gamma.yaml b/dts/Bindings/display/mediatek/mediatek,gamma.yaml
index 7844233931..a89ea0ea75 100644
--- a/dts/Bindings/display/mediatek/mediatek,gamma.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,gamma.yaml
@@ -27,10 +27,10 @@ properties:
- const: mediatek,mt8183-disp-gamma
- items:
- enum:
+ - mediatek,mt8186-disp-gamma
- mediatek,mt8192-disp-gamma
- mediatek,mt8195-disp-gamma
- - enum:
- - mediatek,mt8183-disp-gamma
+ - const: mediatek,mt8183-disp-gamma
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,merge.yaml b/dts/Bindings/display/mediatek/mediatek,merge.yaml
index d635c5dcb6..69ba75777d 100644
--- a/dts/Bindings/display/mediatek/mediatek,merge.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,merge.yaml
@@ -102,4 +102,3 @@ examples:
clock-names = "merge";
};
};
-
diff --git a/dts/Bindings/display/mediatek/mediatek,mutex.yaml b/dts/Bindings/display/mediatek/mediatek,mutex.yaml
index 00e6a1041a..3fdad71210 100644
--- a/dts/Bindings/display/mediatek/mediatek,mutex.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,mutex.yaml
@@ -23,21 +23,16 @@ description: |
properties:
compatible:
- oneOf:
- - items:
- - const: mediatek,mt2701-disp-mutex
- - items:
- - const: mediatek,mt2712-disp-mutex
- - items:
- - const: mediatek,mt8167-disp-mutex
- - items:
- - const: mediatek,mt8173-disp-mutex
- - items:
- - const: mediatek,mt8183-disp-mutex
- - items:
- - const: mediatek,mt8192-disp-mutex
- - items:
- - const: mediatek,mt8195-disp-mutex
+ enum:
+ - mediatek,mt2701-disp-mutex
+ - mediatek,mt2712-disp-mutex
+ - mediatek,mt8167-disp-mutex
+ - mediatek,mt8173-disp-mutex
+ - mediatek,mt8183-disp-mutex
+ - mediatek,mt8186-disp-mutex
+ - mediatek,mt8192-disp-mutex
+ - mediatek,mt8195-disp-mutex
+
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml
index da999ba53b..4e94f4e947 100644
--- a/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -25,6 +25,10 @@ properties:
- const: mediatek,mt8183-disp-ovl-2l
- items:
- const: mediatek,mt8192-disp-ovl-2l
+ - items:
+ - enum:
+ - mediatek,mt8186-disp-ovl-2l
+ - const: mediatek,mt8192-disp-ovl-2l
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/Bindings/display/mediatek/mediatek,ovl.yaml
index f77094e614..a2a27d0ca0 100644
--- a/dts/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -33,13 +33,15 @@ properties:
- enum:
- mediatek,mt7623-disp-ovl
- mediatek,mt2712-disp-ovl
- - enum:
- - mediatek,mt2701-disp-ovl
+ - const: mediatek,mt2701-disp-ovl
- items:
- enum:
- mediatek,mt8195-disp-ovl
+ - const: mediatek,mt8183-disp-ovl
+ - items:
- enum:
- - mediatek,mt8183-disp-ovl
+ - mediatek,mt8186-disp-ovl
+ - const: mediatek,mt8192-disp-ovl
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,postmask.yaml b/dts/Bindings/display/mediatek/mediatek,postmask.yaml
index 2d769422e2..654080bfbd 100644
--- a/dts/Bindings/display/mediatek/mediatek,postmask.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,postmask.yaml
@@ -23,6 +23,10 @@ properties:
oneOf:
- items:
- const: mediatek,mt8192-disp-postmask
+ - items:
+ - enum:
+ - mediatek,mt8186-disp-postmask
+ - const: mediatek,mt8192-disp-postmask
reg:
maxItems: 1
diff --git a/dts/Bindings/display/mediatek/mediatek,rdma.yaml b/dts/Bindings/display/mediatek/mediatek,rdma.yaml
index e8c72afa06..0882ae86e6 100644
--- a/dts/Bindings/display/mediatek/mediatek,rdma.yaml
+++ b/dts/Bindings/display/mediatek/mediatek,rdma.yaml
@@ -35,13 +35,12 @@ properties:
- enum:
- mediatek,mt7623-disp-rdma
- mediatek,mt2712-disp-rdma
- - enum:
- - mediatek,mt2701-disp-rdma
+ - const: mediatek,mt2701-disp-rdma
- items:
- enum:
+ - mediatek,mt8186-disp-rdma
- mediatek,mt8192-disp-rdma
- - enum:
- - mediatek,mt8183-disp-rdma
+ - const: mediatek,mt8183-disp-rdma
reg:
maxItems: 1
diff --git a/dts/Bindings/display/msm/dpu-qcm2290.yaml b/dts/Bindings/display/msm/dpu-qcm2290.yaml
index 6fb7e321f0..734d14de96 100644
--- a/dts/Bindings/display/msm/dpu-qcm2290.yaml
+++ b/dts/Bindings/display/msm/dpu-qcm2290.yaml
@@ -66,6 +66,10 @@ properties:
interconnect-names:
const: mdp0-mem
+ resets:
+ items:
+ - description: MDSS_CORE reset
+
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
diff --git a/dts/Bindings/display/msm/dpu-sc7180.yaml b/dts/Bindings/display/msm/dpu-sc7180.yaml
index 12a86b1ec1..b41991eaa4 100644
--- a/dts/Bindings/display/msm/dpu-sc7180.yaml
+++ b/dts/Bindings/display/msm/dpu-sc7180.yaml
@@ -65,6 +65,10 @@ properties:
interconnect-names:
const: mdp0-mem
+ resets:
+ items:
+ - description: MDSS_CORE reset
+
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
diff --git a/dts/Bindings/display/msm/dpu-sc7280.yaml b/dts/Bindings/display/msm/dpu-sc7280.yaml
index fbeb931a02..6e417d06fc 100644
--- a/dts/Bindings/display/msm/dpu-sc7280.yaml
+++ b/dts/Bindings/display/msm/dpu-sc7280.yaml
@@ -64,6 +64,10 @@ properties:
interconnect-names:
const: mdp0-mem
+ resets:
+ items:
+ - description: MDSS_CORE reset
+
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
diff --git a/dts/Bindings/display/msm/dpu-sdm845.yaml b/dts/Bindings/display/msm/dpu-sdm845.yaml
index 0dca4b3d66..1a42491efd 100644
--- a/dts/Bindings/display/msm/dpu-sdm845.yaml
+++ b/dts/Bindings/display/msm/dpu-sdm845.yaml
@@ -57,6 +57,10 @@ properties:
ranges: true
+ resets:
+ items:
+ - description: MDSS_CORE reset
+
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
diff --git a/dts/Bindings/display/panel/ilitek,ili9341.yaml b/dts/Bindings/display/panel/ilitek,ili9341.yaml
index 20ce88ab4b..6058948a97 100644
--- a/dts/Bindings/display/panel/ilitek,ili9341.yaml
+++ b/dts/Bindings/display/panel/ilitek,ili9341.yaml
@@ -75,4 +75,3 @@ examples:
};
};
...
-
diff --git a/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml
new file mode 100644
index 0000000000..817a9bed7d
--- /dev/null
+++ b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/leadtek,ltk035c5444t.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Leadtek ltk035c5444t 3.5" (640x480 pixels) 24-bit IPS LCD panel
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+ - Christophe Branchereau <cbranchereau@gmail.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ const: leadtek,ltk035c5444t
+
+ backlight: true
+ port: true
+ power-supply: true
+ reg: true
+ reset-gpios: true
+
+required:
+ - compatible
+ - power-supply
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "leadtek,ltk035c5444t";
+ reg = <0>;
+
+ spi-3wire;
+ spi-max-frequency = <3125000>;
+
+ reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
+
+ backlight = <&backlight>;
+ power-supply = <&vcc>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&panel_output>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.yaml b/dts/Bindings/display/panel/orisetech,otm8009a.yaml
index 17cbd0ad32..ad7d357519 100644
--- a/dts/Bindings/display/panel/orisetech,otm8009a.yaml
+++ b/dts/Bindings/display/panel/orisetech,otm8009a.yaml
@@ -50,4 +50,3 @@ examples:
};
};
...
-
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index 1eb9dd4f8f..21ba90c9fe 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -105,6 +105,8 @@ properties:
- chunghwa,claa101wb01
# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
- chunghwa,claa101wb03
+ # DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit parallel interface.
+ - dataimage,fg040346dsswbg04
# DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
- dataimage,scf0700c48ggu18
# DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
@@ -294,6 +296,8 @@ properties:
- starry,kr070pe2t
# Starry 12.2" (1920x1200 pixels) TFT LCD panel
- starry,kr122ea0sra
+ # Startek KD070WVFPA043-C069A 7" TFT LCD panel
+ - startek,kd070wvfpa
# Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel
- team-source-display,tst043015cmhx
# Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
diff --git a/dts/Bindings/display/panel/panel-timing.yaml b/dts/Bindings/display/panel/panel-timing.yaml
index 7749de95ee..229e3b36ee 100644
--- a/dts/Bindings/display/panel/panel-timing.yaml
+++ b/dts/Bindings/display/panel/panel-timing.yaml
@@ -146,6 +146,7 @@ properties:
Horizontal sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
vsync-active:
@@ -153,6 +154,7 @@ properties:
Vertical sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
de-active:
@@ -160,6 +162,7 @@ properties:
Data enable.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
pixelclk-active:
@@ -169,6 +172,7 @@ properties:
sample data on rising edge.
Use 1 to drive pixel data on rising edge and
sample data on falling edge
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
syncclk-active:
@@ -179,6 +183,7 @@ properties:
sample sync on rising edge of pixel clock.
Use 1 to drive sync on rising edge and
sample sync on falling edge of pixel clock
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
interlaced:
diff --git a/dts/Bindings/display/panel/raydium,rm67191.yaml b/dts/Bindings/display/panel/raydium,rm67191.yaml
index 745dd247c4..617aa8c8c0 100644
--- a/dts/Bindings/display/panel/raydium,rm67191.yaml
+++ b/dts/Bindings/display/panel/raydium,rm67191.yaml
@@ -24,6 +24,7 @@ properties:
dsi-lanes:
description: Number of DSI lanes to be used must be <3> or <4>
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [3, 4]
v3p3-supply:
diff --git a/dts/Bindings/display/panel/samsung,s6e8aa0.yaml b/dts/Bindings/display/panel/samsung,s6e8aa0.yaml
index ca95945155..1cdc91b343 100644
--- a/dts/Bindings/display/panel/samsung,s6e8aa0.yaml
+++ b/dts/Bindings/display/panel/samsung,s6e8aa0.yaml
@@ -36,6 +36,7 @@ properties:
init-delay:
description: delay after initialization sequence [ms]
+ $ref: /schemas/types.yaml#/definitions/uint32
panel-width-mm:
description: physical panel width [mm]
diff --git a/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
index da3b889ad8..7e59dee15a 100644
--- a/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -23,10 +23,22 @@ properties:
- rockchip,rk3288-dw-hdmi
- rockchip,rk3328-dw-hdmi
- rockchip,rk3399-dw-hdmi
+ - rockchip,rk3568-dw-hdmi
reg-io-width:
const: 4
+ avdd-0v9-supply:
+ description:
+ A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
+ varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
+ HDMI_AVDD_1V0.
+
+ avdd-1v8-supply:
+ description:
+ A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
+ SoC usually is HDMI_TX_AVDD_1V8.
+
clocks:
minItems: 2
items:
@@ -36,7 +48,8 @@ properties:
# order when present.
- description: The HDMI CEC controller main clock
- description: Power for GRF IO
- - description: External clock for some HDMI PHY
+ - description: External clock for some HDMI PHY (old clock name, deprecated)
+ - description: External clock for some HDMI PHY (new name)
clock-names:
minItems: 2
@@ -47,10 +60,14 @@ properties:
- cec
- grf
- vpll
+ - ref
- enum:
- grf
- vpll
- - const: vpll
+ - ref
+ - enum:
+ - vpll
+ - ref
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -72,6 +89,7 @@ properties:
The unwedge pinctrl entry shall drive the DDC SDA line low. This is
intended to work around a hardware errata that can cause the DDC I2C
bus to be wedged.
+ minItems: 1
items:
- const: default
- const: unwedge
@@ -79,27 +97,21 @@ properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
- properties:
- port:
- $ref: /schemas/graph.yaml#/$defs/port-base
- unevaluatedProperties: false
+ patternProperties:
+ "^port(@0)?$":
+ $ref: /schemas/graph.yaml#/properties/port
description: Input of the DWC HDMI TX
-
properties:
+ endpoint:
+ description: Connection to the VOP
endpoint@0:
- $ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPB
-
endpoint@1:
- $ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPL
-
- required:
- - endpoint@0
- - endpoint@1
-
- required:
- - port
+ properties:
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output of the DWC HDMI TX
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
diff --git a/dts/Bindings/display/rockchip/rockchip-vop2.yaml b/dts/Bindings/display/rockchip/rockchip-vop2.yaml
new file mode 100644
index 0000000000..fba45091d9
--- /dev/null
+++ b/dts/Bindings/display/rockchip/rockchip-vop2.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC display controller (VOP2)
+
+description:
+ VOP2 (Video Output Processor v2) is the display controller for the Rockchip
+ series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+maintainers:
+ - Sandy Huang <hjc@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3566-vop
+ - rockchip,rk3568-vop
+
+ reg:
+ items:
+ - description:
+ Must contain one entry corresponding to the base address and length
+ of the register space.
+ - description:
+ Can optionally contain a second entry corresponding to
+ the CRTC gamma LUT address.
+
+ reg-names:
+ items:
+ - const: vop
+ - const: gamma-lut
+
+ interrupts:
+ maxItems: 1
+ description:
+ The VOP interrupt is shared by several interrupt sources, such as
+ frame start (VSYNC), line flag and other status interrupts.
+
+ clocks:
+ items:
+ - description: Clock for ddr buffer transfer.
+ - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Pixel clock for video port 0.
+ - description: Pixel clock for video port 1.
+ - description: Pixel clock for video port 2.
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: hclk
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to GRF regs used for misc control
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP0
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP1
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP2
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3568-power.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ vop: vop@fe040000 {
+ compatible = "rockchip,rk3568-vop";
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+ reg-names = "vop", "gamma-lut";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
+ power-domains = <&power RK3568_PD_VO>;
+ iommus = <&vop_mmu>;
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vp0: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ vp1: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ vp2: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/sitronix,st7735r.yaml b/dts/Bindings/display/sitronix,st7735r.yaml
index 0cebaaefda..157b1a7b18 100644
--- a/dts/Bindings/display/sitronix,st7735r.yaml
+++ b/dts/Bindings/display/sitronix,st7735r.yaml
@@ -32,15 +32,13 @@ properties:
- okaya,rh128128t
- const: sitronix,st7715r
- spi-max-frequency:
- maximum: 32000000
-
dc-gpios:
maxItems: 1
description: Display data/command selection (D/CX)
backlight: true
reg: true
+ spi-max-frequency: true
reset-gpios: true
rotation: true
@@ -48,7 +46,6 @@ required:
- compatible
- reg
- dc-gpios
- - reset-gpios
additionalProperties: false
@@ -72,6 +69,7 @@ examples:
dc-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
rotation = <270>;
+ backlight = <&backlight>;
};
};
diff --git a/dts/Bindings/display/solomon,ssd1307fb.yaml b/dts/Bindings/display/solomon,ssd1307fb.yaml
index 9baafd0c42..3fbd87c2c1 100644
--- a/dts/Bindings/display/solomon,ssd1307fb.yaml
+++ b/dts/Bindings/display/solomon,ssd1307fb.yaml
@@ -12,11 +12,22 @@ maintainers:
properties:
compatible:
- enum:
- - solomon,ssd1305fb-i2c
- - solomon,ssd1306fb-i2c
- - solomon,ssd1307fb-i2c
- - solomon,ssd1309fb-i2c
+ oneOf:
+ # Deprecated compatible strings
+ - items:
+ - enum:
+ - solomon,ssd1305fb-i2c
+ - solomon,ssd1306fb-i2c
+ - solomon,ssd1307fb-i2c
+ - solomon,ssd1309fb-i2c
+ deprecated: true
+ - items:
+ - enum:
+ - sinowealth,sh1106
+ - solomon,ssd1305
+ - solomon,ssd1306
+ - solomon,ssd1307
+ - solomon,ssd1309
reg:
maxItems: 1
@@ -27,9 +38,20 @@ properties:
reset-gpios:
maxItems: 1
+ # Only required for SPI
+ dc-gpios:
+ description:
+ GPIO connected to the controller's D/C# (Data/Command) pin,
+ that is needed for 4-wire SPI to tell the controller if the
+ data sent is for a command register or the display data RAM
+ maxItems: 1
+
vbat-supply:
description: The supply for VBAT
+ # Only required for SPI
+ spi-max-frequency: true
+
solomon,height:
$ref: /schemas/types.yaml#/definitions/uint32
default: 16
@@ -135,7 +157,21 @@ allOf:
properties:
compatible:
contains:
- const: solomon,ssd1305fb-i2c
+ const: sinowealth,sh1106
+ then:
+ properties:
+ solomon,dclk-div:
+ default: 1
+ solomon,dclk-frq:
+ default: 5
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - solomon,ssd1305-i2c
+ - solomon,ssd1305
then:
properties:
solomon,dclk-div:
@@ -147,7 +183,9 @@ allOf:
properties:
compatible:
contains:
- const: solomon,ssd1306fb-i2c
+ enum:
+ - solomon,ssd1306-i2c
+ - solomon,ssd1306
then:
properties:
solomon,dclk-div:
@@ -159,7 +197,9 @@ allOf:
properties:
compatible:
contains:
- const: solomon,ssd1307fb-i2c
+ enum:
+ - solomon,ssd1307-i2c
+ - solomon,ssd1307
then:
properties:
solomon,dclk-div:
@@ -173,7 +213,9 @@ allOf:
properties:
compatible:
contains:
- const: solomon,ssd1309fb-i2c
+ enum:
+ - solomon,ssd1309-i2c
+ - solomon,ssd1309
then:
properties:
solomon,dclk-div:
@@ -189,15 +231,15 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- ssd1307: oled@3c {
- compatible = "solomon,ssd1307fb-i2c";
+ ssd1307_i2c: oled@3c {
+ compatible = "solomon,ssd1307";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
};
- ssd1306: oled@3d {
- compatible = "solomon,ssd1306fb-i2c";
+ ssd1306_i2c: oled@3d {
+ compatible = "solomon,ssd1306";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
@@ -207,3 +249,30 @@ examples:
solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
};
};
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307_spi: oled@0 {
+ compatible = "solomon,ssd1307";
+ reg = <0x0>;
+ pwms = <&pwm 4 3000>;
+ reset-gpios = <&gpio2 7>;
+ dc-gpios = <&gpio2 8>;
+ spi-max-frequency = <10000000>;
+ };
+
+ ssd1306_spi: oled@1 {
+ compatible = "solomon,ssd1306";
+ reg = <0x1>;
+ pwms = <&pwm 4 3000>;
+ reset-gpios = <&gpio2 7>;
+ dc-gpios = <&gpio2 8>;
+ spi-max-frequency = <10000000>;
+ solomon,com-lrremap;
+ solomon,com-invdir;
+ solomon,com-offset = <32>;
+ solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
+ };
+ };
diff --git a/dts/Bindings/display/sprd/sprd,display-subsystem.yaml b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
index d0a5592bd8..b3d5e1b96f 100644
--- a/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
+++ b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml
@@ -63,4 +63,3 @@ examples:
compatible = "sprd,display-subsystem";
ports = <&dpu_out>;
};
-
diff --git a/dts/Bindings/display/st,stm32-ltdc.yaml b/dts/Bindings/display/st,stm32-ltdc.yaml
index 01e2da2379..d6ea4d62a2 100644
--- a/dts/Bindings/display/st,stm32-ltdc.yaml
+++ b/dts/Bindings/display/st,stm32-ltdc.yaml
@@ -75,4 +75,3 @@ examples:
};
...
-
diff --git a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
index b6e1ebfaf3..ff0a5c58d7 100644
--- a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
+++ b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
@@ -20,9 +20,11 @@ properties:
compatible:
oneOf:
- - const: allwinner,sun50i-a64-dma
- - const: allwinner,sun50i-a100-dma
- - const: allwinner,sun50i-h6-dma
+ - enum:
+ - allwinner,sun20i-d1-dma
+ - allwinner,sun50i-a64-dma
+ - allwinner,sun50i-a100-dma
+ - allwinner,sun50i-h6-dma
- items:
- const: allwinner,sun8i-r40-dma
- const: allwinner,sun50i-a64-dma
@@ -58,6 +60,7 @@ if:
properties:
compatible:
enum:
+ - allwinner,sun20i-d1-dma
- allwinner,sun50i-a100-dma
- allwinner,sun50i-h6-dma
diff --git a/dts/Bindings/dma/altr,msgdma.yaml b/dts/Bindings/dma/altr,msgdma.yaml
index b193ee2db4..b53ac7631a 100644
--- a/