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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-24 08:43:05 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-24 08:43:05 +0200 |
commit | e5511bc1720ecfe006ece9d24033a6007abbec04 (patch) | |
tree | 3d43982f5f27d5a16c1662271206d67a32b5bc51 /dts | |
parent | fce0d30e07df009edb2aceace22a490a04a5a2c9 (diff) | |
download | barebox-e5511bc1720ecfe006ece9d24033a6007abbec04.tar.gz barebox-e5511bc1720ecfe006ece9d24033a6007abbec04.tar.xz |
dts: update to v5.19-rc7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r-- | dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/net/wireless/qca,ath9k.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/net/wireless/qcom,ath11k.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/sound/qcom,lpass-cpu.yaml | 8 | ||||
-rw-r--r-- | dts/src/arm/imx6qdl-ts7970.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm/imx6ull-colibri.dtsi | 9 | ||||
-rw-r--r-- | dts/src/arm/lan966x-kontron-kswitch-d10-mmt.dtsi | 8 | ||||
-rw-r--r-- | dts/src/arm/qcom-msm8974.dtsi | 30 | ||||
-rw-r--r-- | dts/src/arm/sama5d2.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm/sun8i-h2-plus-orangepi-zero.dts | 2 | ||||
-rw-r--r-- | dts/src/arm64/broadcom/bcm4908/bcm4906.dtsi | 8 | ||||
-rw-r--r-- | dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi | 2 | ||||
-rw-r--r-- | dts/src/arm64/freescale/fsl-ls1028a.dtsi | 5 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi | 4 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3399.dtsi | 6 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3566-quartz64-a.dts | 1 | ||||
-rw-r--r-- | dts/src/arm64/rockchip/rk3566-quartz64-b.dts | 2 | ||||
-rw-r--r-- | dts/src/riscv/microchip/mpfs.dtsi | 4 |
18 files changed, 74 insertions, 24 deletions
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml index c388ae5da1..c9c346e622 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -94,6 +94,7 @@ if: - allwinner,sun8i-a83t-display-engine - allwinner,sun8i-r40-display-engine - allwinner,sun9i-a80-display-engine + - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine then: diff --git a/dts/Bindings/net/wireless/qca,ath9k.yaml b/dts/Bindings/net/wireless/qca,ath9k.yaml index 8cd0adbf70..7029cb1f38 100644 --- a/dts/Bindings/net/wireless/qca,ath9k.yaml +++ b/dts/Bindings/net/wireless/qca,ath9k.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Atheros ath9k wireless devices Generic Binding maintainers: - - Kalle Valo <kvalo@codeaurora.org> + - Toke Høiland-Jørgensen <toke@toke.dk> description: | This node provides properties for configuring the ath9k wireless device. diff --git a/dts/Bindings/net/wireless/qcom,ath11k.yaml b/dts/Bindings/net/wireless/qcom,ath11k.yaml index 8c01fdba13..a677b056f1 100644 --- a/dts/Bindings/net/wireless/qcom,ath11k.yaml +++ b/dts/Bindings/net/wireless/qcom,ath11k.yaml @@ -9,7 +9,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies ath11k wireless devices Generic Binding maintainers: - - Kalle Valo <kvalo@codeaurora.org> + - Kalle Valo <kvalo@kernel.org> description: | These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax diff --git a/dts/Bindings/sound/qcom,lpass-cpu.yaml b/dts/Bindings/sound/qcom,lpass-cpu.yaml index e9a533080b..ef18a572a1 100644 --- a/dts/Bindings/sound/qcom,lpass-cpu.yaml +++ b/dts/Bindings/sound/qcom,lpass-cpu.yaml @@ -25,12 +25,12 @@ properties: - qcom,sc7280-lpass-cpu reg: - minItems: 2 + minItems: 1 maxItems: 6 description: LPAIF core registers reg-names: - minItems: 2 + minItems: 1 maxItems: 6 clocks: @@ -42,12 +42,12 @@ properties: maxItems: 10 interrupts: - minItems: 2 + minItems: 1 maxItems: 4 description: LPAIF DMA buffer interrupt interrupt-names: - minItems: 2 + minItems: 1 maxItems: 4 qcom,adsp: diff --git a/dts/src/arm/imx6qdl-ts7970.dtsi b/dts/src/arm/imx6qdl-ts7970.dtsi index fded07f370..d6ba4b2a60 100644 --- a/dts/src/arm/imx6qdl-ts7970.dtsi +++ b/dts/src/arm/imx6qdl-ts7970.dtsi @@ -226,7 +226,7 @@ reg = <0x28>; #gpio-cells = <2>; gpio-controller; - ngpio = <32>; + ngpios = <62>; }; sgtl5000: codec@a { diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi index 15621e03fa..2c3ae715c6 100644 --- a/dts/src/arm/imx6ull-colibri.dtsi +++ b/dts/src/arm/imx6ull-colibri.dtsi @@ -166,7 +166,7 @@ atmel_mxt_ts: touchscreen@4a { compatible = "atmel,maxtouch"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_atmel_conn>; + pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; reg = <0x4a>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ @@ -331,7 +331,6 @@ pinctrl_atmel_conn: atmelconngrp { fsl,pins = < MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ >; }; @@ -684,6 +683,12 @@ }; &iomuxc_snvs { + pinctrl_atmel_snvs_conn: atmelsnvsconngrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + >; + }; + pinctrl_snvs_gpio1: snvsgpio1grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ diff --git a/dts/src/arm/lan966x-kontron-kswitch-d10-mmt.dtsi b/dts/src/arm/lan966x-kontron-kswitch-d10-mmt.dtsi index 4cab1b3b3b..725dcf707b 100644 --- a/dts/src/arm/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/dts/src/arm/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -87,22 +87,22 @@ phy4: ethernet-phy@5 { reg = <5>; - coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy5: ethernet-phy@6 { reg = <6>; - coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy6: ethernet-phy@7 { reg = <7>; - coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy7: ethernet-phy@8 { reg = <8>; - coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; }; diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi index 814ad0b462..c3b8a6d630 100644 --- a/dts/src/arm/qcom-msm8974.dtsi +++ b/dts/src/arm/qcom-msm8974.dtsi @@ -506,6 +506,8 @@ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; status = "disabled"; }; @@ -581,6 +583,9 @@ interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>; clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_default>; + pinctrl-1 = <&blsp2_uart1_sleep>; status = "disabled"; }; @@ -599,6 +604,8 @@ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart4_default>; status = "disabled"; }; @@ -639,6 +646,9 @@ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -1256,7 +1266,7 @@ }; }; - blsp1_uart2_active: blsp1-uart2-active { + blsp1_uart2_default: blsp1-uart2-default { rx { pins = "gpio5"; function = "blsp_uart2"; @@ -1272,7 +1282,7 @@ }; }; - blsp2_uart1_active: blsp2-uart1-active { + blsp2_uart1_default: blsp2-uart1-default { tx-rts { pins = "gpio41", "gpio44"; function = "blsp_uart7"; @@ -1295,7 +1305,7 @@ bias-pull-down; }; - blsp2_uart4_active: blsp2-uart4-active { + blsp2_uart4_default: blsp2-uart4-default { tx-rts { pins = "gpio53", "gpio56"; function = "blsp_uart10"; @@ -1406,7 +1416,19 @@ bias-pull-up; }; - /* BLSP2_I2C6 info is missing - nobody uses it though? */ + blsp2_i2c6_default: blsp2-i2c6-default { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-pull-up; + }; spi8_default: spi8_default { mosi { diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi index 89c71d419f..659a17fc75 100644 --- a/dts/src/arm/sama5d2.dtsi +++ b/dts/src/arm/sama5d2.dtsi @@ -1124,7 +1124,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; clock-names = "pclk", "gclk"; assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; - assigned-parrents = <&pmc PMC_TYPE_GCK 55>; + assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; status = "disabled"; }; diff --git a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts index f19ed981da..3706216ffb 100644 --- a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts +++ b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts @@ -169,7 +169,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; }; diff --git a/dts/src/arm64/broadcom/bcm4908/bcm4906.dtsi b/dts/src/arm64/broadcom/bcm4908/bcm4906.dtsi index 66023d5535..d084c33d5c 100644 --- a/dts/src/arm64/broadcom/bcm4908/bcm4906.dtsi +++ b/dts/src/arm64/broadcom/bcm4908/bcm4906.dtsi @@ -9,6 +9,14 @@ /delete-node/ cpu@3; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi b/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi index a4be040a00..967d2cd3c3 100644 --- a/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi +++ b/dts/src/arm64/broadcom/bcm4908/bcm4908.dtsi @@ -29,6 +29,8 @@ device_type = "cpu"; compatible = "brcm,brahma-b53"; reg = <0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; next-level-cache = <&l2>; }; diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi index 92465f7776..d5cdd77e5a 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi @@ -224,9 +224,12 @@ little-endian; }; - efuse@1e80000 { + sfp: efuse@1e80000 { compatible = "fsl,ls1028a-sfp"; reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi index 913d845eb5..1977103a5e 100644 --- a/dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi +++ b/dts/src/arm64/rockchip/rk3399-gru-scarlet.dtsi @@ -376,7 +376,8 @@ camera: &i2c7 { <&cru ACLK_VIO>, <&cru ACLK_GIC_PRE>, <&cru PCLK_DDR>, - <&cru ACLK_HDCP>; + <&cru ACLK_HDCP>, + <&cru ACLK_VDU>; assigned-clock-rates = <600000000>, <1600000000>, <1000000000>, @@ -388,6 +389,7 @@ camera: &i2c7 { <400000000>, <200000000>, <200000000>, + <400000000>, <400000000>; }; diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi index fbd0346624..9d5b0e8c9c 100644 --- a/dts/src/arm64/rockchip/rk3399.dtsi +++ b/dts/src/arm64/rockchip/rk3399.dtsi @@ -1462,7 +1462,8 @@ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, <&cru ACLK_VIO>, <&cru ACLK_HDCP>, <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; + <&cru PCLK_DDR>, + <&cru ACLK_VDU>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1473,7 +1474,8 @@ <100000000>, <50000000>, <400000000>, <400000000>, <200000000>, - <200000000>; + <200000000>, + <400000000>; }; grf: syscon@ff770000 { diff --git a/dts/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/src/arm64/rockchip/rk3566-quartz64-a.dts index 1534e11a9a..fa953b7366 100644 --- a/dts/src/arm64/rockchip/rk3566-quartz64-a.dts +++ b/dts/src/arm64/rockchip/rk3566-quartz64-a.dts @@ -687,6 +687,7 @@ }; &usb_host0_xhci { + dr_mode = "host"; status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3566-quartz64-b.dts b/dts/src/arm64/rockchip/rk3566-quartz64-b.dts index 7bdcecc0df..02d5f5a8ca 100644 --- a/dts/src/arm64/rockchip/rk3566-quartz64-b.dts +++ b/dts/src/arm64/rockchip/rk3566-quartz64-b.dts @@ -133,7 +133,7 @@ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; clock_in_out = "input"; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim diff --git a/dts/src/riscv/microchip/mpfs.dtsi b/dts/src/riscv/microchip/mpfs.dtsi index 3095d08453..496d3b7642 100644 --- a/dts/src/riscv/microchip/mpfs.dtsi +++ b/dts/src/riscv/microchip/mpfs.dtsi @@ -50,6 +50,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu1_intc: interrupt-controller { @@ -77,6 +78,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu2_intc: interrupt-controller { @@ -104,6 +106,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu3_intc: interrupt-controller { @@ -131,6 +134,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; |