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authorSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-10-06 06:12:41 +0200
commitebde8820a04dd73a09f50ba84b8cf8ec3773d6ba (patch)
tree031d15dcd26f5b737adddc5042a3ddabbb6051f7 /dts
parent15af9fc8cc9e18409893d2375271d64cac76924a (diff)
downloadbarebox-ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba.tar.gz
dts: update to v4.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts')
-rw-r--r--dts/Bindings/arc/hsdk.txt7
-rw-r--r--dts/Bindings/arm/amlogic.txt41
-rw-r--r--dts/Bindings/arm/arch_timer.txt1
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--dts/Bindings/arm/bhf.txt6
-rw-r--r--dts/Bindings/arm/coresight.txt4
-rw-r--r--dts/Bindings/arm/cpus.txt1
-rw-r--r--dts/Bindings/arm/marvell/armada-8kp.txt15
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller0.txt1
-rw-r--r--dts/Bindings/arm/mediatek.txt18
-rw-r--r--dts/Bindings/arm/omap/omap.txt9
-rw-r--r--dts/Bindings/arm/pmu.txt2
-rw-r--r--dts/Bindings/arm/qcom.txt2
-rw-r--r--dts/Bindings/arm/rockchip.txt12
-rw-r--r--dts/Bindings/arm/shmobile.txt8
-rw-r--r--dts/Bindings/ata/ahci-mtk.txt51
-rw-r--r--dts/Bindings/ata/apm-xgene.txt2
-rw-r--r--dts/Bindings/ata/imx-pata.txt1
-rw-r--r--dts/Bindings/bus/mvebu-mbus.txt3
-rw-r--r--dts/Bindings/bus/nvidia,tegra20-gmi.txt2
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.txt1
-rw-r--r--dts/Bindings/chosen.txt26
-rw-r--r--dts/Bindings/clock/alphascale,acc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-aoclkc.txt23
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-clkc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,meson8b-clkc.txt10
-rw-r--r--dts/Bindings/clock/at91-clock.txt10
-rw-r--r--dts/Bindings/clock/brcm,kona-ccu.txt1
-rw-r--r--dts/Bindings/clock/exynos5433-clock.txt1
-rw-r--r--dts/Bindings/clock/hi3660-clock.txt1
-rw-r--r--dts/Bindings/clock/hix5hd2-clock.txt1
-rw-r--r--dts/Bindings/clock/idt,versaclock5.txt30
-rw-r--r--dts/Bindings/clock/imx21-clock.txt1
-rw-r--r--dts/Bindings/clock/imx23-clock.txt1
-rw-r--r--dts/Bindings/clock/imx25-clock.txt1
-rw-r--r--dts/Bindings/clock/imx27-clock.txt1
-rw-r--r--dts/Bindings/clock/imx28-clock.txt1
-rw-r--r--dts/Bindings/clock/imx31-clock.txt1
-rw-r--r--dts/Bindings/clock/imx5-clock.txt1
-rw-r--r--dts/Bindings/clock/imx6q-clock.txt1
-rw-r--r--dts/Bindings/clock/mt8173-cpu-dvfs.txt83
-rw-r--r--dts/Bindings/clock/nvidia,tegra124-dfll.txt1
-rw-r--r--dts/Bindings/clock/pxa-clock.txt1
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt4
-rw-r--r--dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt55
-rw-r--r--dts/Bindings/clock/renesas,rz-cpg-clocks.txt1
-rw-r--r--dts/Bindings/clock/rockchip,rk3128-cru.txt8
-rw-r--r--dts/Bindings/clock/samsung,s3c2410-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c2412-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c2443-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s3c64xx-clock.txt1
-rw-r--r--dts/Bindings/clock/samsung,s5pv210-clock.txt1
-rw-r--r--dts/Bindings/clock/silabs,si5351.txt6
-rw-r--r--dts/Bindings/clock/snps,hsdk-pll-clock.txt28
-rw-r--r--dts/Bindings/clock/snps,pll-clock.txt28
-rw-r--r--dts/Bindings/clock/st,stm32h7-rcc.txt71
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt6
-rw-r--r--dts/Bindings/clock/ti,sci-clk.txt7
-rw-r--r--dts/Bindings/clock/ti/dra7-atl.txt2
-rw-r--r--dts/Bindings/clock/uniphier-clock.txt8
-rw-r--r--dts/Bindings/clock/zx296702-clk.txt1
-rw-r--r--dts/Bindings/clock/zx296718-clk.txt1
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt247
-rw-r--r--dts/Bindings/crypto/artpec6-crypto.txt16
-rw-r--r--dts/Bindings/crypto/atmel-crypto.txt13
-rw-r--r--dts/Bindings/crypto/fsl-dcp.txt1
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt1
-rw-r--r--dts/Bindings/crypto/marvell-cesa.txt1
-rw-r--r--dts/Bindings/crypto/mv_cesa.txt1
-rw-r--r--dts/Bindings/crypto/rockchip-crypto.txt1
-rw-r--r--dts/Bindings/crypto/st,stm32-hash.txt30
-rw-r--r--dts/Bindings/devfreq/event/rockchip-dfi.txt1
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt1
-rw-r--r--dts/Bindings/display/atmel,lcdc.txt1
-rw-r--r--dts/Bindings/display/atmel/hlcdc-dc.txt1
-rw-r--r--dts/Bindings/display/bridge/dw_mipi_dsi.txt32
-rw-r--r--dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt1
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt2
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt12
-rw-r--r--dts/Bindings/display/fsl,tcon.txt1
-rw-r--r--dts/Bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt1
-rw-r--r--dts/Bindings/display/panel/innolux,p079zca.txt1
-rw-r--r--dts/Bindings/display/renesas,du.txt51
-rw-r--r--dts/Bindings/display/repaper.txt52
-rw-r--r--dts/Bindings/display/rockchip/analogix_dp-rockchip.txt1
-rw-r--r--dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt8
-rw-r--r--dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt2
-rw-r--r--dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt1
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop.txt4
-rw-r--r--dts/Bindings/display/simple-framebuffer-sunxi.txt1
-rw-r--r--dts/Bindings/display/sitronix,st7586.txt22
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.txt105
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt37
-rw-r--r--dts/Bindings/dma/fsl-edma.txt1
-rw-r--r--dts/Bindings/dma/mv-xor.txt1
-rw-r--r--dts/Bindings/dma/qcom_adm.txt1
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps-dma.txt1
-rw-r--r--dts/Bindings/dma/st_fdma.txt1
-rw-r--r--dts/Bindings/dma/ste-dma40.txt1
-rw-r--r--dts/Bindings/dma/sun4i-dma.txt1
-rw-r--r--dts/Bindings/dma/sun6i-dma.txt1
-rw-r--r--dts/Bindings/dma/ti-dma-crossbar.txt1
-rw-r--r--dts/Bindings/dma/ti-edma.txt96
-rw-r--r--dts/Bindings/eeprom/eeprom.txt6
-rw-r--r--dts/Bindings/extcon/extcon-usbc-cros-ec.txt24
-rw-r--r--dts/Bindings/fpga/altera-passive-serial.txt29
-rw-r--r--dts/Bindings/fpga/xilinx-pr-decoupler.txt36
-rw-r--r--dts/Bindings/fpga/xilinx-slave-serial.txt1
-rw-r--r--dts/Bindings/gpio/gpio-74x164.txt3
-rw-r--r--dts/Bindings/gpio/gpio-aspeed.txt2
-rw-r--r--dts/Bindings/gpio/gpio-davinci.txt91
-rw-r--r--dts/Bindings/gpio/gpio-mpc8xxx.txt1
-rw-r--r--dts/Bindings/gpio/gpio-vf610.txt4
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt16
-rw-r--r--dts/Bindings/gpio/spear_spics.txt1
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.txt1
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.txt5
-rw-r--r--dts/Bindings/gpu/nvidia,gk20a.txt3
-rw-r--r--dts/Bindings/gpu/samsung-g2d.txt1
-rw-r--r--dts/Bindings/hsi/omap-ssi.txt1
-rw-r--r--dts/Bindings/hwmon/aspeed-pwm-tacho.txt9
-rw-r--r--dts/Bindings/hwmon/ibm,cffps1.txt21
-rw-r--r--dts/Bindings/hwmon/ltq-cputemp.txt10
-rw-r--r--dts/Bindings/i2c/i2c-altera.txt39
-rw-r--r--dts/Bindings/i2c/i2c-cbus-gpio.txt4
-rw-r--r--dts/Bindings/i2c/i2c-demux-pinctrl.txt1
-rw-r--r--dts/Bindings/i2c/i2c-efm32.txt1
-rw-r--r--dts/Bindings/i2c/i2c-mtk.txt15
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt5
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.txt1
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt5
-rw-r--r--dts/Bindings/i2c/i2c-sprd.txt31
-rw-r--r--dts/Bindings/i2c/i2c-stm32.txt29
-rw-r--r--dts/Bindings/i2c/nvidia,tegra20-i2c.txt1
-rw-r--r--dts/Bindings/iio/adc/at91-sama5d2_adc.txt6
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/lpc1850-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/mt6577_auxadc.txt1
-rw-r--r--dts/Bindings/iio/adc/rockchip-saradc.txt1
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt5
-rw-r--r--dts/Bindings/iio/counter/stm32-lptimer-cnt.txt27
-rw-r--r--dts/Bindings/iio/dac/lpc1850-dac.txt1
-rw-r--r--dts/Bindings/iio/dac/st,stm32-dac.txt4
-rw-r--r--dts/Bindings/iio/humidity/hdc100x.txt17
-rw-r--r--dts/Bindings/iio/humidity/hts221.txt11
-rw-r--r--dts/Bindings/iio/humidity/htu21.txt13
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt8
-rw-r--r--dts/Bindings/iio/pressure/ms5637.txt17
-rw-r--r--dts/Bindings/iio/st-sensors.txt3
-rw-r--r--dts/Bindings/iio/temperature/tsys01.txt19
-rw-r--r--dts/Bindings/iio/timer/stm32-lptimer-trigger.txt23
-rw-r--r--dts/Bindings/iio/timer/stm32-timer-trigger.txt6
-rw-r--r--dts/Bindings/input/atmel,maxtouch.txt2
-rw-r--r--dts/Bindings/input/brcm,bcm-keypad.txt1
-rw-r--r--dts/Bindings/input/pwm-vibrator.txt66
-rw-r--r--dts/Bindings/input/ti,drv260x.txt2
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/imx6ul_tsc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt8
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt1
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--dts/Bindings/iommu/qcom,iommu.txt121
-rw-r--r--dts/Bindings/iommu/rockchip,iommu.txt5
-rw-r--r--dts/Bindings/leds/ams,as3645a.txt71
-rw-r--r--dts/Bindings/leds/irled/gpio-ir-tx.txt14
-rw-r--r--dts/Bindings/leds/irled/pwm-ir-tx.txt13
-rw-r--r--dts/Bindings/leds/leds-gpio.txt3
-rw-r--r--dts/Bindings/leds/leds-pca955x.txt88
-rw-r--r--dts/Bindings/media/i2c/adv748x.txt95
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9714.txt9
-rw-r--r--dts/Bindings/media/meson-ao-cec.txt28
-rw-r--r--dts/Bindings/media/mtk-cir.txt8
-rw-r--r--dts/Bindings/media/pxa-camera.txt1
-rw-r--r--dts/Bindings/media/qcom,camss.txt197
-rw-r--r--dts/Bindings/media/renesas,drif.txt1
-rw-r--r--dts/Bindings/media/s5p-cec.txt1
-rw-r--r--dts/Bindings/media/samsung-fimc.txt2
-rw-r--r--dts/Bindings/media/stih407-c8sectpfe.txt1
-rw-r--r--dts/Bindings/media/ti,da850-vpif.txt1
-rw-r--r--dts/Bindings/media/video-interfaces.txt8
-rw-r--r--dts/Bindings/media/zx-irdec.txt14
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt15
-rw-r--r--dts/Bindings/memory-controllers/mvebu-devbus.txt1
-rw-r--r--dts/Bindings/mfd/act8945a.txt2
-rw-r--r--dts/Bindings/mfd/atmel-hlcdc.txt1
-rw-r--r--dts/Bindings/mfd/atmel-smc.txt1
-rw-r--r--dts/Bindings/mfd/axp20x.txt50
-rw-r--r--dts/Bindings/mfd/bd9571mwv.txt49
-rw-r--r--dts/Bindings/mfd/da9052-i2c.txt9
-rw-r--r--dts/Bindings/mfd/mc13xxx.txt1
-rw-r--r--dts/Bindings/mfd/mxs-lradc.txt2
-rw-r--r--dts/Bindings/mfd/retu.txt25
-rw-r--r--dts/Bindings/mfd/rk808.txt22
-rw-r--r--dts/Bindings/mfd/samsung,exynos5433-lpass.txt2
-rw-r--r--dts/Bindings/mfd/stm32-lptimer.txt48
-rw-r--r--dts/Bindings/mfd/tps6105x.txt17
-rw-r--r--dts/Bindings/mfd/wm831x.txt1
-rw-r--r--dts/Bindings/mfd/zii,rave-sp.txt39
-rw-r--r--dts/Bindings/mips/lantiq/fpi-bus.txt31
-rw-r--r--dts/Bindings/mips/lantiq/rcu-gphy.txt36
-rw-r--r--dts/Bindings/mips/lantiq/rcu.txt89
-rw-r--r--dts/Bindings/mips/ni.txt7
-rw-r--r--dts/Bindings/mips/ralink.txt1
-rw-r--r--dts/Bindings/misc/atmel-ssc.txt1
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt1
-rw-r--r--dts/Bindings/mmc/davinci_mmc.txt1
-rw-r--r--dts/Bindings/mmc/fsl-imx-mmc.txt1
-rw-r--r--dts/Bindings/mmc/mmc-card.txt1
-rw-r--r--dts/Bindings/mmc/mmc.txt1
-rw-r--r--dts/Bindings/mmc/orion-sdio.txt1
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt4
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--dts/Bindings/mmc/sdhci-st.txt3
-rw-r--r--dts/Bindings/mmc/sunxi-mmc.txt1
-rw-r--r--dts/Bindings/mmc/ti-omap-hsmmc.txt52
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt8
-rw-r--r--dts/Bindings/mmc/zx-dw-mshc.txt1
-rw-r--r--dts/Bindings/mtd/atmel-quadspi.txt1
-rw-r--r--dts/Bindings/mtd/mtk-quadspi.txt1
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt65
-rw-r--r--dts/Bindings/mtd/st-fsm.txt1
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt1
-rw-r--r--dts/Bindings/net/anarion-gmac.txt25
-rw-r--r--dts/Bindings/net/brcm,amac.txt1
-rw-r--r--dts/Bindings/net/broadcom-bluetooth.txt35
-rw-r--r--dts/Bindings/net/btusb.txt1
-rw-r--r--dts/Bindings/net/can/c_can.txt13
-rw-r--r--dts/Bindings/net/can/m_can.txt1
-rw-r--r--dts/Bindings/net/dsa/ksz.txt2
-rw-r--r--dts/Bindings/net/dsa/lan9303.txt3
-rw-r--r--dts/Bindings/net/ethernet.txt4
-rw-r--r--dts/Bindings/net/ftgmac100.txt1
-rw-r--r--dts/Bindings/net/marvell-armada-370-neta.txt1
-rw-r--r--dts/Bindings/net/marvell-bt-8xxx.txt2
-rw-r--r--dts/Bindings/net/marvell-neta-bm.txt2
-rw-r--r--dts/Bindings/net/marvell-pp2.txt32
-rw-r--r--dts/Bindings/net/mediatek-net.txt18
-rw-r--r--dts/Bindings/net/meson-dwmac.txt1
-rw-r--r--dts/Bindings/net/micrel-ksz90x1.txt1
-rw-r--r--dts/Bindings/net/microchip,enc28j60.txt1
-rw-r--r--dts/Bindings/net/nfc/nfcmrvl.txt2
-rw-r--r--dts/Bindings/net/nfc/nxp-nci.txt1
-rw-r--r--dts/Bindings/net/nfc/pn533-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/pn544.txt1
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt1
-rw-r--r--dts/Bindings/net/nfc/st21nfca.txt1
-rw-r--r--dts/Bindings/net/nfc/st95hf.txt2
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt2
-rw-r--r--dts/Bindings/net/oxnas-dwmac.txt1
-rw-r--r--dts/Bindings/net/phy.txt15
-rw-r--r--dts/Bindings/net/qca,qca7000.txt2
-rw-r--r--dts/Bindings/net/renesas,ravb.txt30
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt2
-rw-r--r--dts/Bindings/net/sff,sfp.txt76
-rw-r--r--dts/Bindings/net/smsc-lan87xx.txt1
-rw-r--r--dts/Bindings/net/socfpga-dwmac.txt1
-rw-r--r--dts/Bindings/net/sti-dwmac.txt1
-rw-r--r--dts/Bindings/net/stm32-dwmac.txt1
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt1
-rw-r--r--dts/Bindings/net/wireless/esp,esp8089.txt1
-rw-r--r--dts/Bindings/net/wireless/marvell-8xxx.txt1
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore.txt1
-rw-r--r--dts/Bindings/net/xilinx_axienet.txt55
-rw-r--r--dts/Bindings/nvmem/mtk-efuse.txt5
-rw-r--r--dts/Bindings/nvmem/mxs-ocotp.txt1
-rw-r--r--dts/Bindings/opp/opp.txt1
-rw-r--r--dts/Bindings/pci/83xx-512x-pci.txt6
-rw-r--r--dts/Bindings/pci/aardvark-pci.txt1
-rw-r--r--dts/Bindings/pci/altera-pcie.txt18
-rw-r--r--dts/Bindings/pci/axis,artpec6-pcie.txt2
-rw-r--r--dts/Bindings/pci/designware-pcie.txt24
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt2
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt6
-rw-r--r--dts/Bindings/pci/kirin-pcie.txt8
-rw-r--r--dts/Bindings/pci/layerscape-pci.txt4
-rw-r--r--dts/Bindings/pci/mediatek,mt7623-pcie.txt130
-rw-r--r--dts/Bindings/pci/mediatek-pcie.txt284
-rw-r--r--dts/Bindings/pci/mvebu-pci.txt15
-rw-r--r--dts/Bindings/pci/pci-armada8k.txt3
-rw-r--r--dts/Bindings/pci/pci-keystone.txt15
-rw-r--r--dts/Bindings/pci/pci-rcar-gen2.txt7
-rw-r--r--dts/Bindings/pci/pci.txt4
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt27
-rw-r--r--dts/Bindings/pci/ralink,rt3883-pci.txt2
-rw-r--r--dts/Bindings/pci/rcar-pci.txt8
-rw-r--r--dts/Bindings/pci/rockchip-pcie.txt28
-rw-r--r--dts/Bindings/pci/samsung,exynos5440-pcie.txt22
-rw-r--r--dts/Bindings/pci/spear13xx-pcie.txt6
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-rw-r--r--dts/src/arm64/broadcom/northstar2/ns2-clock.dtsi (renamed from dts/src/arm64/broadcom/ns2-clock.dtsi)0
-rw-r--r--dts/src/arm64/broadcom/northstar2/ns2-svk.dts (renamed from dts/src/arm64/broadcom/ns2-svk.dts)0
-rw-r--r--dts/src/arm64/broadcom/northstar2/ns2-xmc.dts (renamed from dts/src/arm64/broadcom/ns2-xmc.dts)0
-rw-r--r--dts/src/arm64/broadcom/northstar2/ns2.dtsi (renamed from dts/src/arm64/broadcom/ns2.dtsi)0
-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742-base.dtsi78
-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742k.dts4
-rw-r--r--dts/src/arm64/broadcom/stingray/bcm958742t.dts4
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray-fs4.dtsi118
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray-sata.dtsi278
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi136
-rw-r--r--dts/src/arm64/exynos/exynos5433-tm2-common.dtsi25
-rw-r--r--dts/src/arm64/exynos/exynos5433.dtsi4
-rw-r--r--dts/src/arm64/exynos/exynos7-espresso.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1012a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls1043a.dtsi12
-rw-r--r--dts/src/arm64/freescale/fsl-ls1046a.dtsi31
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a-rdb.dts2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a.dtsi65
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-qds.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-rdb.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a-simu.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2080a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a-qds.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a-rdb.dts5
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a.dtsi17
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi51
-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts37
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi130
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi9
-rw-r--r--dts/src/arm64/hisilicon/hip07-d05.dts4
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi22
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin.dts30
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi11
-rw-r--r--dts/src/arm64/marvell/armada-7040-db.dts39
-rw-r--r--dts/src/arm64/marvell/armada-8040-db.dts65
-rw-r--r--dts/src/arm64/marvell/armada-8040-mcbin.dts124
-rw-r--r--dts/src/arm64/marvell/armada-8080-db.dts67
-rw-r--r--dts/src/arm64/marvell/armada-8080.dtsi53
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi104
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0.dtsi163
-rw-r--r--dts/src/arm64/marvell/armada-cp110-master.dtsi83
-rw-r--r--dts/src/arm64/marvell/armada-cp110-slave.dtsi83
-rw-r--r--dts/src/arm64/mediatek/mt2712-evb.dts32
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi171
-rw-r--r--dts/src/arm64/mediatek/mt6797.dtsi12
-rw-r--r--dts/src/arm64/mediatek/mt7622-rfb1.dts27
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi110
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi1
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi17
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi24
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi198
-rw-r--r--dts/src/arm64/qcom/ipq8074-hk01.dts52
-rw-r--r--dts/src/arm64/qcom/ipq8074.dtsi194
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi120
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi314
-rw-r--r--dts/src/arm64/qcom/pmi8994.dtsi17
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1.dtsi9
-rw-r--r--dts/src/arm64/renesas/r8a7795-h3ulcb.dts16
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-x.dts2
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-xs.dts8
-rw-r--r--dts/src/arm64/renesas/r8a7795.dtsi314
-rw-r--r--dts/src/arm64/renesas/r8a7796-m3ulcb.dts14
-rw-r--r--dts/src/arm64/renesas/r8a7796-salvator-x.dts31
-rw-r--r--dts/src/arm64/renesas/r8a7796.dtsi414
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts46
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi155
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi4
-rw-r--r--dts/src/arm64/renesas/salvator-xs.dtsi10
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi51
-rw-r--r--dts/src/arm64/rockchip/rk3328-evb.dts181
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts333
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi437
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3368-geekbox.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3368-px5-evb.dts3
-rw-r--r--dts/src/arm64/rockchip/rk3368-r88.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi140
-rw-r--r--dts/src/arm64/rockchip/rk3399-evb.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts16
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts44
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi132
-rw-r--r--dts/src/arm64/rockchip/rk3399-op1-opp.dtsi33
-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi33
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts228
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi547
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts240
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi644
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi292
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-ref.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi35
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts6
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi37
-rw-r--r--dts/src/arm64/socionext/uniphier-pinctrl.dtsi142
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts62
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi367
-rw-r--r--dts/src/arm64/socionext/uniphier-ref-daughter.dtsi17
-rw-r--r--dts/src/arm64/socionext/uniphier-support-card.dtsi35
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi50
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts18
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi277
-rw-r--r--dts/src/arm64/zte/zx296718-evb.dts68
-rw-r--r--dts/src/arm64/zte/zx296718-pcbox.dts143
-rw-r--r--dts/src/arm64/zte/zx296718.dtsi171
-rw-r--r--dts/src/mips/ingenic/ci20.dts37
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi11
-rw-r--r--dts/src/mips/ni/169445.dts100
-rw-r--r--dts/src/mips/ralink/mt7628a.dtsi126
-rw-r--r--dts/src/mips/ralink/omega2p.dts18
-rw-r--r--dts/src/mips/ralink/vocore2.dts18
-rw-r--r--dts/src/nios2/3c120_devboard.dts3
-rw-r--r--dts/src/powerpc/fsp2.dts33
981 files changed, 29785 insertions, 4030 deletions
diff --git a/dts/Bindings/arc/hsdk.txt b/dts/Bindings/arc/hsdk.txt
new file mode 100644
index 0000000..be50654
--- /dev/null
+++ b/dts/Bindings/arc/hsdk.txt
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
+---------------------------------------------------------------------------
+
+ARC HSDK Board with quad-core ARC HS38x4 in silicon.
+
+Required root node properties:
+ - compatible = "snps,hsdk";
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 0fff40a..4e4bc0b 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -1,6 +1,18 @@
Amlogic MesonX device tree bindings
-------------------------------------------
+Work in progress statement:
+
+Device tree files and bindings applying to Amlogic SoCs and boards are
+considered "unstable". Any Amlogic device tree binding may change at
+any time. Be sure to use a device tree binary and a kernel image
+generated from the same source tree.
+
+Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
+stable binding/ABI.
+
+---------------------------------------------------------------
+
Boards with the Amlogic Meson6 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson6"
@@ -61,3 +73,32 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,q201" (Meson gxm s912)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
+
+Amlogic Meson Firmware registers Interface
+------------------------------------------
+
+The Meson SoCs have a register bank with status and data shared with the
+secure firmware.
+
+Required properties:
+ - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
+
+Properties should indentify components of this register interface :
+
+Meson GX SoC Information
+------------------------
+A firmware register encodes the SoC type, package and revision information on
+the Meson GX SoCs.
+If present, the following property should be added :
+
+Optional properties:
+ - amlogic,has-chip-id: If present, the interface gives the current SoC version.
+
+Example
+-------
+
+ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+};
diff --git a/dts/Bindings/arm/arch_timer.txt b/dts/Bindings/arm/arch_timer.txt
index e926aea..68301b7 100644
--- a/dts/Bindings/arm/arch_timer.txt
+++ b/dts/Bindings/arm/arch_timer.txt
@@ -108,6 +108,5 @@ Example:
frame-number = <1>
interrupts = <0 15 0x8>;
reg = <0xf0003000 0x1000>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 9c97de2..3e3efa0 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -42,6 +42,10 @@ Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
+Raspberry Pi Zero W
+Required root node properties:
+compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";
diff --git a/dts/Bindings/arm/bhf.txt b/dts/Bindings/arm/bhf.txt
new file mode 100644
index 0000000..886b503
--- /dev/null
+++ b/dts/Bindings/arm/bhf.txt
@@ -0,0 +1,6 @@
+Beckhoff Automation Platforms Device Tree Bindings
+--------------------------------------------------
+
+CX9020 Embedded PC
+Required root node properties:
+ - compatible = "bhf,cx9020", "fsl,imx53";
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index fcbae6a..15ac8e8 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -34,8 +34,8 @@ its hardware characteristcs.
- Embedded Trace Macrocell (version 4.x):
"arm,coresight-etm4x", "arm,primecell";
- - Qualcomm Configurable Replicator (version 1.x):
- "qcom,coresight-replicator1x", "arm,primecell";
+ - Coresight programmable Replicator :
+ "arm,coresight-dynamic-replicator", "arm,primecell";
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index a44253c..b92f12b 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -200,6 +200,7 @@ described below.
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
+ "brcm,bcm2836-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
diff --git a/dts/Bindings/arm/marvell/armada-8kp.txt b/dts/Bindings/arm/marvell/armada-8kp.txt
new file mode 100644
index 0000000..f3e9624
--- /dev/null
+++ b/dts/Bindings/arm/marvell/armada-8kp.txt
@@ -0,0 +1,15 @@
+Marvell Armada 8KPlus Platforms Device Tree Bindings
+----------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 8KP families must carry
+the following root node property:
+
+ - compatible, with one of the following values:
+
+ - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
+ when the SoC being used is the Armada 8080
+
+Example:
+
+compatible = "marvell,armada-8080-db", "marvell,armada-8080",
+ "marvell,armada-ap810-octa", "marvell,armada-ap810"
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
index 171d02c..29cdbae 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -183,7 +183,6 @@ cpm_syscon0: system-controller@440000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index da7bd13..91d5178 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -1,12 +1,12 @@
-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
+MediaTek SoC based Platforms Device Tree Bindings
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
-following property:
+Boards with a MediaTek SoC shall have the following property:
Required root node property:
compatible: Must contain one of
"mediatek,mt2701"
+ "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -14,7 +14,8 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
- "mediatek,mt7623"
+ "mediatek,mt7623" which is referred to MT7623N SoC
+ "mediatek,mt7623a"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -25,6 +26,9 @@ Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+ Required root node properties:
+ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
@@ -46,9 +50,11 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-- Evaluation board for MT7623:
+- Reference board for MT7623n with NAND:
Required root node properties:
- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+ - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt
index 8219b2c..2ecc712 100644
--- a/dts/Bindings/arm/omap/omap.txt
+++ b/dts/Bindings/arm/omap/omap.txt
@@ -80,6 +80,9 @@ SoCs:
- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
+- DRA762
+ compatible = "ti,dra762", "ti,dra7"
+
- DRA742
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
@@ -154,6 +157,9 @@ Boards:
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
+- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
@@ -184,6 +190,9 @@ Boards:
- AM5718 IDK
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
+- DRA762 EVM: Software Development Board for DRA762
+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 61c8b46..13611a8 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -9,9 +9,11 @@ Required properties:
- compatible : should be one of
"apm,potenza-pmu"
"arm,armv8-pmuv3"
+ "arm,cortex-a73-pmu"
"arm,cortex-a72-pmu"
"arm,cortex-a57-pmu"
"arm,cortex-a53-pmu"
+ "arm,cortex-a35-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
diff --git a/dts/Bindings/arm/qcom.txt b/dts/Bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a/dts/Bindings/arm/qcom.txt
+++ b/dts/Bindings/arm/qcom.txt
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
+ ipq8074
The 'board' element must be one of the following strings:
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
+ hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 11c0ac4..b003148 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
+- Pine64 Rock64 board:
+ Required root node properties:
+ - compatible = "pine64,rock64", "rockchip,rk3328";
+
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire Excavator board:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+
+- Theobroma Systems RK3399-Q7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
+
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 1a671e3..ae75cb3 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car D3 (R8A77995)
+ compatible = "renesas,r8a77995"
Boards:
@@ -53,6 +55,8 @@ Boards:
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Draak (RTP0RC77995SEB0010S)
+ compatible = "renesas,draak", "renesas,r8a77995"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- GR-Peach (X28A-M01-E/F)
@@ -64,6 +68,10 @@ Boards:
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
+ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+ compatible = "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
diff --git a/dts/Bindings/ata/ahci-mtk.txt b/dts/Bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000..d2aa696
--- /dev/null
+++ b/dts/Bindings/ata/ahci-mtk.txt
@@ -0,0 +1,51 @@
+MediaTek Serial ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
+ When using "mediatek,mtk-ahci" compatible strings, you
+ need SoC specific ones in addition, one of:
+ - "mediatek,mt7622-ahci"
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : See ./ahci-platform.txt for details.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi", "sw", "reg".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
diff --git a/dts/Bindings/ata/apm-xgene.txt b/dts/Bindings/ata/apm-xgene.txt
index a668f0e..02e690a 100644
--- a/dts/Bindings/ata/apm-xgene.txt
+++ b/dts/Bindings/ata/apm-xgene.txt
@@ -57,7 +57,6 @@ Example:
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
@@ -72,7 +71,6 @@ Example:
<0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";
diff --git a/dts/Bindings/ata/imx-pata.txt b/dts/Bindings/ata/imx-pata.txt
index e38d734..f1172f0 100644
--- a/dts/Bindings/ata/imx-pata.txt
+++ b/dts/Bindings/ata/imx-pata.txt
@@ -13,5 +13,4 @@ Example:
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 161>;
- status = "disabled";
};
diff --git a/dts/Bindings/bus/mvebu-mbus.txt b/dts/Bindings/bus/mvebu-mbus.txt
index fa6cde4..f2ab7fd 100644
--- a/dts/Bindings/bus/mvebu-mbus.txt
+++ b/dts/Bindings/bus/mvebu-mbus.txt
@@ -227,7 +227,6 @@ See the example below, where a more complete device tree is shown:
};
devbus-bootcs {
- status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
@@ -240,7 +239,6 @@ See the example below, where a more complete device tree is shown:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
- status = "okay";
device_type = "pci";
#address-cells = <3>;
@@ -258,7 +256,6 @@ See the example below, where a more complete device tree is shown:
pcie@1,0 {
/* Port 0, Lane 0 */
- status = "okay";
};
};
diff --git a/dts/Bindings/bus/nvidia,tegra20-gmi.txt b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
index 83b0e54..3e21eb8 100644
--- a/dts/Bindings/bus/nvidia,tegra20-gmi.txt
+++ b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
bus@4,0 {
compatible = "simple-bus";
@@ -121,7 +120,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
can@4,0 {
reg = <4 0 0x100>;
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
index 7ff13be..3108d03 100644
--- a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
+++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
@@ -33,7 +33,6 @@ Example:
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
- status = "disabled";
child1 {
...
diff --git a/dts/Bindings/chosen.txt b/dts/Bindings/chosen.txt
index dee3f5d..e3b13ea 100644
--- a/dts/Bindings/chosen.txt
+++ b/dts/Bindings/chosen.txt
@@ -5,9 +5,31 @@ The chosen node does not represent a real device, but serves as a place
for passing data between firmware and the operating system, like boot
arguments. Data in the chosen node does not represent the hardware.
+The following properties are recognized:
-stdout-path property
---------------------
+
+kaslr-seed
+-----------
+
+This property is used when booting with CONFIG_RANDOMIZE_BASE as the
+entropy used to randomize the kernel image base address location. Since
+it is used directly, this value is intended only for KASLR, and should
+not be used for other purposes (as it may leak information about KASLR
+offsets). It is parsed as a u64 value, e.g.
+
+/ {
+ chosen {
+ kaslr-seed = <0xfeedbeef 0xc0def00d>;
+ };
+};
+
+Note that if this property is set from UEFI (or a bootloader in EFI
+mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by
+the Linux EFI stub (which will populate the property itself, using
+EFI_RNG_PROTOCOL).
+
+stdout-path
+-----------
Device trees may specify the device to be used for boot console output
with a stdout-path property under /chosen, as described in the Devicetree
diff --git a/dts/Bindings/clock/alphascale,acc.txt b/dts/Bindings/clock/alphascale,acc.txt
index 62e67e8..b3205b2 100644
--- a/dts/Bindings/clock/alphascale,acc.txt
+++ b/dts/Bindings/clock/alphascale,acc.txt
@@ -102,7 +102,6 @@ uart4: serial@80010000 {
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
- status = "disabled";
};
Clock consumer with only one, _AHB_ sink.
diff --git a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
index a55d31b..786dc39 100644
--- a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
Required Properties:
-- compatible: should be "amlogic,gxbb-aoclkc"
-- reg: physical base address of the clock controller and length of memory
- mapped region.
+- compatible: value should be different for each SoC family as :
+ - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
+ - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
+ - GXM (S912) : "amlogic,meson-gxm-aoclkc"
+ followed by the common "amlogic,meson-gx-aoclkc"
- #clock-cells: should be 1.
@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
Example: AO Clock controller node:
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x040 0x0 0x4>;
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
+};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
@@ -41,5 +51,4 @@ Example: UART controller node that consumes the clock and reset generated
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
index a09d627..9240407 100644
--- a/dts/Bindings/clock/amlogic,gxbb-clkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -33,5 +33,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/amlogic,meson8b-clkc.txt b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
index 606da38..b455c5a 100644
--- a/dts/Bindings/clock/amlogic,meson8b-clkc.txt
+++ b/dts/Bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
mapped region.
- #clock-cells: should be 1.
+- #reset-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
Example: Clock controller node:
clkc: clock-controller@c1104000 {
- #clock-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
@@ -39,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 5f3ad65..51c259a 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -81,6 +81,16 @@ Required properties:
"atmel,sama5d2-clk-generated":
at91 generated clock
+ "atmel,sama5d2-clk-audio-pll-frac":
+ at91 audio fractional pll
+
+ "atmel,sama5d2-clk-audio-pll-pad":
+ at91 audio pll CLK_AUDIO output pin
+
+ "atmel,sama5d2-clk-audio-pll-pmc"
+ at91 audio pll output on AUDIOPLLCLK that feeds the PMC
+ and can be used by peripheral clock or generic clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
diff --git a/dts/Bindings/clock/brcm,kona-ccu.txt b/dts/Bindings/clock/brcm,kona-ccu.txt
index 5286e26..8e5a7d8 100644
--- a/dts/Bindings/clock/brcm,kona-ccu.txt
+++ b/dts/Bindings/clock/brcm,kona-ccu.txt
@@ -46,7 +46,6 @@ Device tree example:
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
- status = "disabled";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/Bindings/clock/exynos5433-clock.txt b/dts/Bindings/clock/exynos5433-clock.txt
index 1dc80f8..fe885ab 100644
--- a/dts/Bindings/clock/exynos5433-clock.txt
+++ b/dts/Bindings/clock/exynos5433-clock.txt
@@ -465,5 +465,4 @@ Example 3: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/hi3660-clock.txt b/dts/Bindings/clock/hi3660-clock.txt
index cc9b86c..0035a7e 100644
--- a/dts/Bindings/clock/hi3660-clock.txt
+++ b/dts/Bindings/clock/hi3660-clock.txt
@@ -38,5 +38,4 @@ Examples:
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/hix5hd2-clock.txt b/dts/Bindings/clock/hix5hd2-clock.txt
index 7894a64..4733e58 100644
--- a/dts/Bindings/clock/hix5hd2-clock.txt
+++ b/dts/Bindings/clock/hix5hd2-clock.txt
@@ -27,5 +27,4 @@ Examples:
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/idt,versaclock5.txt b/dts/Bindings/clock/idt,versaclock5.txt
index 53d7e50..05a245c 100644
--- a/dts/Bindings/clock/idt,versaclock5.txt
+++ b/dts/Bindings/clock/idt,versaclock5.txt
@@ -1,24 +1,32 @@
-Binding for IDT VersaClock5 programmable i2c clock generator.
+Binding for IDT VersaClock 5,6 programmable i2c clock generators.
-The IDT VersaClock5 are programmable i2c clock generators providing
-from 3 to 12 output clocks.
+The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
+generators providing from 3 to 12 output clocks.
==I2C device node==
Required properties:
-- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
- "idt,5p49v5935".
+- compatible: shall be one of
+ "idt,5p49v5923"
+ "idt,5p49v5925"
+ "idt,5p49v5933"
+ "idt,5p49v5935"
+ "idt,5p49v6901"
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- - 5p49v5923: (required) either or both of XTAL or CLKIN
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
- 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- - 5p49v5923: (required) either or both of "xin", "clkin".
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
+5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1
@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
3 -- OUT3
4 -- OUT4
+5P49V6901:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+ 3 -- OUT3
+ 4 -- OUT4
+
==Example==
/* 25MHz reference crystal */
diff --git a/dts/Bindings/clock/imx21-clock.txt b/dts/Bindings/clock/imx21-clock.txt
index c3b0db4..806f63d 100644
--- a/dts/Bindings/clock/imx21-clock.txt
+++ b/dts/Bindings/clock/imx21-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx23-clock.txt b/dts/Bindings/clock/imx23-clock.txt
index 5083c0b..8385348 100644
--- a/dts/Bindings/clock/imx23-clock.txt
+++ b/dts/Bindings/clock/imx23-clock.txt
@@ -67,5 +67,4 @@ auart0: serial@8006c000 {
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx25-clock.txt b/dts/Bindings/clock/imx25-clock.txt
index ba6b312..f8135ea 100644
--- a/dts/Bindings/clock/imx25-clock.txt
+++ b/dts/Bindings/clock/imx25-clock.txt
@@ -157,5 +157,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx27-clock.txt b/dts/Bindings/clock/imx27-clock.txt
index cc05de9..4c95c04 100644
--- a/dts/Bindings/clock/imx27-clock.txt
+++ b/dts/Bindings/clock/imx27-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx28-clock.txt b/dts/Bindings/clock/imx28-clock.txt
index e6587af..d84a37d 100644
--- a/dts/Bindings/clock/imx28-clock.txt
+++ b/dts/Bindings/clock/imx28-clock.txt
@@ -90,5 +90,4 @@ auart0: serial@8006a000 {
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx31-clock.txt b/dts/Bindings/clock/imx31-clock.txt
index 8163d56..0a29109 100644
--- a/dts/Bindings/clock/imx31-clock.txt
+++ b/dts/Bindings/clock/imx31-clock.txt
@@ -87,5 +87,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx5-clock.txt b/dts/Bindings/clock/imx5-clock.txt
index cadc4d2..a24ca9e 100644
--- a/dts/Bindings/clock/imx5-clock.txt
+++ b/dts/Bindings/clock/imx5-clock.txt
@@ -25,5 +25,4 @@ can1: can@53fc8000 {
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/imx6q-clock.txt b/dts/Bindings/clock/imx6q-clock.txt
index 9252912..aa0a4d4 100644
--- a/dts/Bindings/clock/imx6q-clock.txt
+++ b/dts/Bindings/clock/imx6q-clock.txt
@@ -27,5 +27,4 @@ uart1: serial@02020000 {
interrupts = <0 26 0x04>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/dts/Bindings/clock/mt8173-cpu-dvfs.txt b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
deleted file mode 100644
index 52b457c..0000000
--- a/dts/Bindings/clock/mt8173-cpu-dvfs.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
-
-Required properties:
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-- clock-names: Should contain the following:
- "cpu" - The multiplexer for clock input of CPU cluster.
- "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
- source (usually MAINPLL) when the original CPU PLL is under
- transition and not stable yet.
- Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
- generic clock consumer properties.
-- proc-supply: Regulator for Vproc of CPU cluster.
-
-Optional properties:
-- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
- needs to do "voltage tracking" to step by step scale up/down Vproc and
- Vsram to fit SoC specific needs. When absent, the voltage scaling
- flow is handled by hardware, hence no software "voltage tracking" is
- needed.
-
-Example:
---------
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- &cpu0 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu1 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu2 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
-
- &cpu3 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
diff --git a/dts/Bindings/clock/nvidia,tegra124-dfll.txt b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
index 63f9d82..dff236f 100644
--- a/dts/Bindings/clock/nvidia,tegra124-dfll.txt
+++ b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -66,7 +66,6 @@ clock@70110000 {
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
- status = "okay";
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
diff --git a/dts/Bindings/clock/pxa-clock.txt b/dts/Bindings/clock/pxa-clock.txt
index 4b4a902..8f67239 100644
--- a/dts/Bindings/clock/pxa-clock.txt
+++ b/dts/Bindings/clock/pxa-clock.txt
@@ -12,5 +12,4 @@ Examples:
pxa2xx_clks: pxa2xx_clks@41300004 {
compatible = "marvell,pxa-clocks";
#clock-cells = <1>;
- status = "okay";
};
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index 0cd894f..316e136 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
@@ -30,7 +31,7 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796)
+ r8a7795, r8a7796, r8a77995)
- "extalr" (r8a7795, r8a7796)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
@@ -81,5 +82,4 @@ Examples
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg 310>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
index e4cdaf1..7cc4c03 100644
--- a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -44,5 +44,4 @@ Examples
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
new file mode 100644
index 0000000..e96e085
--- /dev/null
+++ b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -0,0 +1,55 @@
+* Renesas R-Car USB 2.0 clock selector
+
+This file provides information on what the device node for the R-Car USB 2.0
+clock selector.
+
+If you connect an external clock to the USB_EXTAL pin only, you should set
+the clock rate to "usb_extal" node only.
+If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
+is not needed because this is default setting. (Of course, you can set the
+clock rates to both "usb_extal" and "usb_xtal" nodes.
+
+Case 1: An external clock connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |External |---|USB_EXTAL ---> all usb channels|
+ |clock | |USB_XTAL |
+ +----------+ +-------------------------------+
+In this case, we need this driver with "usb_extal" clock.
+
+Case 2: An oscillator connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |Oscillator|---|USB_EXTAL -+-> all usb channels|
+ | |---|USB_XTAL --+ |
+ +----------+ +-------------------------------+
+In this case, we don't need this selector.
+
+Required properties:
+- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
+ an R8A7795 SoC.
+ "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
+ an R8A7796 SoC.
+ "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
+ compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: offset and length of the USB 2.0 clock selector register block.
+- clocks: A list of phandles and specifier pairs.
+- clock-names: Name of the clocks.
+ - The functional clock must be "ehci_ohci"
+ - The USB_EXTAL clock pin must be "usb_extal"
+ - The USB_XTAL clock pin must be "usb_xtal"
+- #clock-cells: Must be 0
+
+Example (R-Car H3):
+
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ };
diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
index bb51a33..bb5d942 100644
--- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
@@ -50,5 +50,4 @@ Examples
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/rockchip,rk3128-cru.txt b/dts/Bindings/clock/rockchip,rk3128-cru.txt
index 455a9a0..6f8744f 100644
--- a/dts/Bindings/clock/rockchip,rk3128-cru.txt
+++ b/dts/Bindings/clock/rockchip,rk3128-cru.txt
@@ -1,12 +1,14 @@
-* Rockchip RK3128 Clock and Reset Unit
+* Rockchip RK3126/RK3128 Clock and Reset Unit
-The RK3128 clock controller generates and supplies clock to various
+The RK3126/RK3128 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
-- compatible: should be "rockchip,rk3128-cru"
+- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
+ "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
+ "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
diff --git a/dts/Bindings/clock/samsung,s3c2410-clock.txt b/dts/Bindings/clock/samsung,s3c2410-clock.txt
index 822505e..2632d3f 100644
--- a/dts/Bindings/clock/samsung,s3c2410-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2410-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c2412-clock.txt b/dts/Bindings/clock/samsung,s3c2412-clock.txt
index 2b43096..21a8c23 100644
--- a/dts/Bindings/clock/samsung,s3c2412-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2412-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c2443-clock.txt b/dts/Bindings/clock/samsung,s3c2443-clock.txt
index e67bb05..985c0f5 100644
--- a/dts/Bindings/clock/samsung,s3c2443-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c2443-clock.txt
@@ -52,5 +52,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s3c64xx-clock.txt b/dts/Bindings/clock/samsung,s3c64xx-clock.txt
index fa171dc..872ee8e 100644
--- a/dts/Bindings/clock/samsung,s3c64xx-clock.txt
+++ b/dts/Bindings/clock/samsung,s3c64xx-clock.txt
@@ -73,5 +73,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/samsung,s5pv210-clock.txt b/dts/Bindings/clock/samsung,s5pv210-clock.txt
index effd940..15b48e2 100644
--- a/dts/Bindings/clock/samsung,s5pv210-clock.txt
+++ b/dts/Bindings/clock/samsung,s5pv210-clock.txt
@@ -74,5 +74,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/silabs,si5351.txt b/dts/Bindings/clock/silabs,si5351.txt
index 28b2830..a6c4ef3 100644
--- a/dts/Bindings/clock/silabs,si5351.txt
+++ b/dts/Bindings/clock/silabs,si5351.txt
@@ -12,7 +12,11 @@ generators can be found in [1].
==I2C device node==
Required properties:
-- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
+- compatible: shall be one of the following:
+ "silabs,si5351a" - Si5351a, QFN20 package
+ "silabs,si5351a-msop" - Si5351a, MSOP10 package
+ "silabs,si5351b" - Si5351b, QFN20 package
+ "silabs,si5351c" - Si5351c, QFN20 package
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
diff --git a/dts/Bindings/clock/snps,hsdk-pll-clock.txt b/dts/Bindings/clock/snps,hsdk-pll-clock.txt
new file mode 100644
index 0000000..c56c755
--- /dev/null
+++ b/dts/Bindings/clock/snps,hsdk-pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the HSDK Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-<name>-pll-clock"
+ "snps,hsdk-core-pll-clock"
+ "snps,hsdk-gp-pll-clock"
+ "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input_clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpu_clk: cpu-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
diff --git a/dts/Bindings/clock/snps,pll-clock.txt b/dts/Bindings/clock/snps,pll-clock.txt
new file mode 100644
index 0000000..11fe487
--- /dev/null
+++ b/dts/Bindings/clock/snps,pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the AXS10X Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-<name>-pll-clock"
+ "snps,axs10x-arc-pll-clock"
+ "snps,axs10x-pgu-pll-clock"
+- reg: should always contain 2 pairs address - length: first for PLL config
+registers and second for corresponding LOCK CGU register.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input-clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ core-clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input-clk>;
+ };
diff --git a/dts/Bindings/clock/st,stm32h7-rcc.txt b/dts/Bindings/clock/st,stm32h7-rcc.txt
new file mode 100644
index 0000000..a135504
--- /dev/null
+++ b/dts/Bindings/clock/st,stm32h7-rcc.txt
@@ -0,0 +1,71 @@
+STMicroelectronics STM32H7 Reset and Clock Controller
+=====================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please refer to clock-bindings.txt for common clock controller binding usage.
+Please also refer to reset.txt for common reset controller binding usage.
+
+Required properties:
+- compatible: Should be:
+ "st,stm32h743-rcc"
+
+- reg: should be register base and length as documented in the
+ datasheet
+
+- #reset-cells: 1, see below
+
+- #clock-cells : from common clock binding; shall be set to 1
+
+- clocks: External oscillator clock phandle
+ - high speed external clock signal (HSE)
+ - low speed external clock signal (LSE)
+ - external I2S clock (I2S_CKIN)
+
+Optional properties:
+- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
+ write protection (RTC clock).
+
+Example:
+
+ rcc: reset-clock-controller@58024400 {
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
+
+ st,syscfg = <&pwrcfg>;
+};
+
+The peripheral clock consumer should specify the desired clock by
+having the clock ID in its "clocks" phandle cell.
+
+Example:
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc TIM5_CK>;
+ };
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example, for CRC reset:
+ crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
+
+Example:
+
+ timer2 {
+ resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
+ };
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index df9fad5..7eda08e 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatibles:
+ - "allwinner,sun4i-a10-ccu"
+ - "allwinner,sun5i-a10s-ccu"
+ - "allwinner,sun5i-a13-ccu"
- "allwinner,sun6i-a31-ccu"
+ - "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
- "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
++ - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/dts/Bindings/clock/ti,sci-clk.txt b/dts/Bindings/clock/ti,sci-clk.txt
index 1e884c4..4e59dc6 100644
--- a/dts/Bindings/clock/ti,sci-clk.txt
+++ b/dts/Bindings/clock/ti,sci-clk.txt
@@ -14,10 +14,9 @@ Required properties:
- compatible: Must be "ti,k2g-sci-clk"
- #clock-cells: Shall be 2.
In clock consumers, this cell represents the device ID and clock ID
- exposed by the PM firmware. The assignments can be found in the header
- files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
- <dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
- is the SoC involved, for example 'k2g'.
+ exposed by the PM firmware. The list of valid values for the device IDs
+ and clocks IDs for 66AK2G SoC are documented at
+ http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
Examples:
--------
diff --git a/dts/Bindings/clock/ti/dra7-atl.txt b/dts/Bindings/clock/ti/dra7-atl.txt
index 585e8c1..10f7047 100644
--- a/dts/Bindings/clock/ti/dra7-atl.txt
+++ b/dts/Bindings/clock/ti/dra7-atl.txt
@@ -81,13 +81,11 @@ atl: atl@4843c000 {
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
- status = "disabled";
};
#include <dt-bindings/clk/ti-dra7-atl.h>
&atl {
- status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
diff --git a/dts/Bindings/clock/uniphier-clock.txt b/dts/Bindings/clock/uniphier-clock.txt
index 8121630..7b5f602 100644
--- a/dts/Bindings/clock/uniphier-clock.txt
+++ b/dts/Bindings/clock/uniphier-clock.txt
@@ -6,7 +6,6 @@ System clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
@@ -14,6 +13,7 @@ Required properties:
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
@@ -56,6 +55,7 @@ Required properties:
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -82,11 +82,9 @@ Provided clocks:
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
-11: USB2 ch3 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
-15: USB2 ch3 PHY
Peripheral clock
@@ -94,7 +92,6 @@ Peripheral clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
@@ -102,6 +99,7 @@ Required properties:
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
diff --git a/dts/Bindings/clock/zx296702-clk.txt b/dts/Bindings/clock/zx296702-clk.txt
index 750442b..e85ecb5 100644
--- a/dts/Bindings/clock/zx296702-clk.txt
+++ b/dts/Bindings/clock/zx296702-clk.txt
@@ -31,5 +31,4 @@ uart0: serial@0x09405000 {
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
- status = "disabled";
};
diff --git a/dts/Bindings/clock/zx296718-clk.txt b/dts/Bindings/clock/zx296718-clk.txt
index 4ad7038..3a46bf0 100644
--- a/dts/Bindings/clock/zx296718-clk.txt
+++ b/dts/Bindings/clock/zx296718-clk.txt
@@ -34,5 +34,4 @@ usbphy0:usb-phy0 {
#phy-cells = <0>;
clocks = <&topclk USB20_PHY_CLK>;
clock-names = "phyclk";
- status = "okay";
};
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
new file mode 100644
index 0000000..f640308
--- /dev/null
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -0,0 +1,247 @@
+Binding for MediaTek's CPUFreq driver
+=====================================
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
+ for detail.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+- #cooling-cells:
+- cooling-min-level:
+- cooling-max-level:
+ Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
+ for detail.
+
+Example 1 (MT7623 SoC):
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-747500000 {
+ opp-hz = /bits/ 64 <747500000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-1040000000 {
+ opp-hz = /bits/ 64 <1040000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+Example 2 (MT8173 SoC):
+ cpu_opp_table_a: opp_table_a {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <859000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <908000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <983000>;
+ };
+
+ opp-1105000000 {
+ opp-hz = /bits/ 64 <1105000000>;
+ opp-microvolt = <1009000>;
+ };
+
+ opp-1183000000 {
+ opp-hz = /bits/ 64 <1183000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <1083000>;
+ };
+
+ opp-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <1109000>;
+ };
+
+ opp-1573000000 {
+ opp-hz = /bits/ 64 <1573000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu_opp_table_b: opp_table_b {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <828000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <867000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <927000>;
+ };
+
+ opp-1209000000 {
+ opp-hz = /bits/ 64 <1209000000>;
+ opp-microvolt = <968000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1007000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1612000000 {
+ opp-hz = /bits/ 64 <1612000000>;
+ opp-microvolt = <1049000>;
+ };
+
+ opp-1807000000 {
+ opp-hz = /bits/ 64 <1807000000>;
+ opp-microvolt = <1089000>;
+ };
+
+ opp-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
diff --git a/dts/Bindings/crypto/artpec6-crypto.txt b/dts/Bindings/crypto/artpec6-crypto.txt
new file mode 100644
index 0000000..d9cca48
--- /dev/null
+++ b/dts/Bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+ "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+ "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+ compatible = "axis,artpec6-crypto";
+ reg = <0xf4264000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/Bindings/crypto/atmel-crypto.txt b/dts/Bindings/crypto/atmel-crypto.txt
index f2aab3d..7de1a96 100644
--- a/dts/Bindings/crypto/atmel-crypto.txt
+++ b/dts/Bindings/crypto/atmel-crypto.txt
@@ -66,3 +66,16 @@ sha@f8034000 {
dmas = <&dma1 2 17>;
dma-names = "tx";
};
+
+* Eliptic Curve Cryptography (I2C)
+
+Required properties:
+- compatible : must be "atmel,atecc508a".
+- reg: I2C bus address of the device.
+- clock-frequency: must be present in the i2c controller node.
+
+Example:
+atecc508a@C0 {
+ compatible = "atmel,atecc508a";
+ reg = <0xC0>;
+};
diff --git a/dts/Bindings/crypto/fsl-dcp.txt b/dts/Bindings/crypto/fsl-dcp.txt
index 6949e50..76a0b4e 100644
--- a/dts/Bindings/crypto/fsl-dcp.txt
+++ b/dts/Bindings/crypto/fsl-dcp.txt
@@ -13,5 +13,4 @@ dcp@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 941bb6a..fbc07d1 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -23,5 +23,4 @@ Example:
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
"eip";
clocks = <&cpm_syscon0 1 26>;
- status = "disabled";
};
diff --git a/dts/Bindings/crypto/marvell-cesa.txt b/dts/Bindings/crypto/marvell-cesa.txt
index c6c6a4a..28d3f24 100644
--- a/dts/Bindings/crypto/marvell-cesa.txt
+++ b/dts/Bindings/crypto/marvell-cesa.txt
@@ -41,5 +41,4 @@ Examples:
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/mv_cesa.txt b/dts/Bindings/crypto/mv_cesa.txt
index c0c35f0..d9b92e2 100644
--- a/dts/Bindings/crypto/mv_cesa.txt
+++ b/dts/Bindings/crypto/mv_cesa.txt
@@ -29,5 +29,4 @@ Examples:
interrupts = <22>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/dts/Bindings/crypto/rockchip-crypto.txt b/dts/Bindings/crypto/rockchip-crypto.txt
index 096df34..5e2ba38 100644
--- a/dts/Bindings/crypto/rockchip-crypto.txt
+++ b/dts/Bindings/crypto/rockchip-crypto.txt
@@ -25,5 +25,4 @@ Examples:
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
resets = <&cru SRST_CRYPTO>;
reset-names = "crypto-rst";
- status = "okay";
};
diff --git a/dts/Bindings/crypto/st,stm32-hash.txt b/dts/Bindings/crypto/st,stm32-hash.txt
new file mode 100644
index 0000000..04fc246
--- /dev/null
+++ b/dts/Bindings/crypto/st,stm32-hash.txt
@@ -0,0 +1,30 @@
+* STMicroelectronics STM32 HASH
+
+Required properties:
+- compatible: Should contain entries for this and backward compatible
+ HASH versions:
+ - "st,stm32f456-hash" for stm32 F456.
+ - "st,stm32f756-hash" for stm32 F756.
+- reg: The address and length of the peripheral registers space
+- interrupts: the interrupt specifier for the HASH
+- clocks: The input clock of the HASH instance
+
+Optional properties:
+- resets: The input reset of the HASH instance
+- dmas: DMA specifiers for the HASH. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be "in" if a dma is present.
+- dma-maxburst: Set number of maximum dma burst supported
+
+Example:
+
+hash1: hash@50060400 {
+ compatible = "st,stm32f756-hash";
+ reg = <0x50060400 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
+ resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
+ dmas = <&dma2 7 2 0x400 0x0>;
+ dma-names = "in";
+ dma-maxburst = <0>;
+};
diff --git a/dts/Bindings/devfreq/event/rockchip-dfi.txt b/dts/Bindings/devfreq/event/rockchip-dfi.txt
index f223313..001dd63 100644
--- a/dts/Bindings/devfreq/event/rockchip-dfi.txt
+++ b/dts/Bindings/devfreq/event/rockchip-dfi.txt
@@ -15,5 +15,4 @@ Example:
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
- status = "disabled";
};
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
index 7a9e860..d6d2833 100644
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ b/dts/Bindings/devfreq/rk3399_dmc.txt
@@ -205,5 +205,4 @@ Example:
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
- status = "disabled";
};
diff --git a/dts/Bindings/display/atmel,lcdc.txt b/dts/Bindings/display/atmel,lcdc.txt
index ecb8da0..1a21202 100644
--- a/dts/Bindings/display/atmel,lcdc.txt
+++ b/dts/Bindings/display/atmel,lcdc.txt
@@ -34,7 +34,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
display = <&display0>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/display/atmel/hlcdc-dc.txt b/dts/Bindings/display/atmel/hlcdc-dc.txt
index ec94468..82f2acb 100644
--- a/dts/Bindings/display/atmel/hlcdc-dc.txt
+++ b/dts/Bindings/display/atmel/hlcdc-dc.txt
@@ -23,7 +23,6 @@ Example:
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/dts/Bindings/display/bridge/dw_mipi_dsi.txt b/dts/Bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 0000000..b13adf3
--- /dev/null
+++ b/dts/Bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare MIPI DSI host controller
+============================================
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each optional property is used or not.
+
+- reg: Memory mapped base address and length of the DesignWare MIPI DSI
+ host controller registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+ as specified in [1]. (mandatory)
+
+- clock-names:
+ - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
+ - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
+
+- resets: References to all the resets specified in the reset-names property
+ as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
index 7baa658..aacc8b9 100644
--- a/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
+++ b/dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
@@ -33,7 +33,6 @@ stdp2690-ge-b850v3-fw required properties:
Example:
&mux2_i2c2 {
- status = "okay";
clock-frequency = <100000>;
stdp4028@73 {
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
index 81b6858..b1a8929 100644
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
+ - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
When compatible with generic versions, nodes must list the SoC-specific
@@ -43,7 +44,6 @@ Example:
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/exynos/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
index 549c538..fc25882 100644
--- a/dts/Bindings/display/exynos/exynos5433-decon.txt
+++ b/dts/Bindings/display/exynos/exynos5433-decon.txt
@@ -25,12 +25,6 @@ Required properties:
size-cells must 1 and 0, respectively.
- port: contains an endpoint node which is connected to the endpoint in the mic
node. The reg value muset be 0.
-- i80-if-timings: specify whether the panel which is connected to decon uses
- i80 lcd interface or mipi video interface. This node contains
- no timing information as that of fimd does. Because there is
- no register in decon to specify i80 interface timing value,
- it is not needed, but make it remain to use same kind of node
- in fimd and exynos7 decon.
Example:
SoC specific DT entry:
@@ -59,9 +53,3 @@ decon: decon@13800000 {
};
};
};
-
-Board specific DT entry:
-&decon {
- i80-if-timings {
- };
-};
diff --git a/dts/Bindings/display/fsl,tcon.txt b/dts/Bindings/display/fsl,tcon.txt
index 6fa4ab6..4750087 100644
--- a/dts/Bindings/display/fsl,tcon.txt
+++ b/dts/Bindings/display/fsl,tcon.txt
@@ -14,5 +14,4 @@ timing-controller@4003d000 {
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
- status = "okay";
};
diff --git a/dts/Bindings/display/imx/fsl-imx-drm.txt b/dts/Bindings/display/imx/fsl-imx-drm.txt
index fa01db7..f798547 100644
--- a/dts/Bindings/display/imx/fsl-imx-drm.txt
+++ b/dts/Bindings/display/imx/fsl-imx-drm.txt
@@ -116,7 +116,7 @@ Parallel display support
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
-- interface_pix_fmt: How this display is connected to the
+- interface-pix-fmt: How this display is connected to the
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
and "lvds666".
- edid: verbatim EDID data block describing attached display.
diff --git a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
index 309c47f..f79641b 100644
--- a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
+++ b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
@@ -23,7 +23,6 @@ Example:
reg = <0x44000000 0x10000>;
interrupts = <17>;
clocks = <&clks CLK_LCD>;
- status = "okay";
port {
lcdc_out: endpoint {
diff --git a/dts/Bindings/display/panel/innolux,p079zca.txt b/dts/Bindings/display/panel/innolux,p079zca.txt
index 5c70a83..d0f5516 100644
--- a/dts/Bindings/display/panel/innolux,p079zca.txt
+++ b/dts/Bindings/display/panel/innolux,p079zca.txt
@@ -18,6 +18,5 @@ Example:
power-supply = <...>;
backlight = <&backlight>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- status = "okay";
};
};
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index c6cb96a..4bbd1e9 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -36,8 +36,10 @@ Required Properties:
When supplied they must be named "dclkin.x" with "x" being the input
clock numerical index.
- - vsps: A list of phandles to the VSP nodes that handle the memory
- interfaces for the DU channels.
+ - vsps: A list of phandle and channel index tuples to the VSPs that handle
+ the memory interfaces for the DU channels. The phandle identifies the VSP
+ instance that serves the DU channel, and the channel index identifies the
+ LIF instance in that VSP.
Required nodes:
@@ -59,24 +61,24 @@ corresponding to each DU output.
R8A7796 (M3-W) DPAD HDMI LVDS -
-Example: R8A7790 (R-Car H2) DU
+Example: R8A7795 (R-Car H3) ES2.0 DU
- du: du@feb00000 {
- compatible = "renesas,du-r8a7790";
- reg = <0 0xfeb00000 0 0x70000>,
- <0 0xfeb90000 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
- reg-names = "du", "lvds.0", "lvds.1";
- interrupt-parent = <&gic>;
- interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
- <0 268 IRQ_TYPE_LEVEL_HIGH>,
- <0 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp7_clks R8A7790_CLK_DU0>,
- <&mstp7_clks R8A7790_CLK_DU1>,
- <&mstp7_clks R8A7790_CLK_DU2>,
- <&mstp7_clks R8A7790_CLK_LVDS0>,
- <&mstp7_clks R8A7790_CLK_LVDS1>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7795";
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfeb90000 0 0x14>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
#address-cells = <1>;
@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
};
port@1 {
reg = <1>;
- du_out_lvds0: endpoint {
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
- du_out_lvds1: endpoint {
+ du_out_hdmi1: endpoint {
+ remote-endpoint = <&dw_hdmi1_in>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ du_out_lvds0: endpoint {
};
};
};
diff --git a/dts/Bindings/display/repaper.txt b/dts/Bindings/display/repaper.txt
new file mode 100644
index 0000000..f5f9f9c
--- /dev/null
+++ b/dts/Bindings/display/repaper.txt
@@ -0,0 +1,52 @@
+Pervasive Displays RePaper branded e-ink displays
+
+Required properties:
+- compatible: "pervasive,e1144cs021" for 1.44" display
+ "pervasive,e1190cs021" for 1.9" display
+ "pervasive,e2200cs021" for 2.0" display
+ "pervasive,e2271cs021" for 2.7" display
+
+- panel-on-gpios: Timing controller power control
+- discharge-gpios: Discharge control
+- reset-gpios: RESET pin
+- busy-gpios: BUSY pin
+
+Required property for e2271cs021:
+- border-gpios: Border control
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional property:
+- pervasive,thermal-zone: name of thermometer's thermal zone
+
+Example:
+
+ display_temp: lm75@48 {
+ compatible = "lm75b";
+ reg = <0x48>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ display {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&display_temp>;
+ };
+ };
+
+ papirus27@0{
+ compatible = "pervasive,e2271cs021";
+ reg = <0>;
+
+ spi-max-frequency = <8000000>;
+
+ panel-on-gpios = <&gpio 23 0>;
+ border-gpios = <&gpio 14 0>;
+ discharge-gpios = <&gpio 15 0>;
+ reset-gpios = <&gpio 24 0>;
+ busy-gpios = <&gpio 25 0>;
+
+ pervasive,thermal-zone = "display";
+ };
diff --git a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
index 47665a1..4356158 100644
--- a/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/dts/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -59,7 +59,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
index 046076c..adc94fc 100644
--- a/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -11,7 +11,9 @@ following device-specific properties.
Required properties:
-- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
+- compatible: should be one of the following:
+ "rockchip,rk3288-dw-hdmi"
+ "rockchip,rk3399-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
- interrupts: HDMI interrupt number
@@ -30,7 +32,8 @@ Optional properties
I2C master controller.
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-
+- clock-names: May contain "grf", power for grf io.
+- clock-names: May contain "vpll", external clock for some hdmi phy.
Example:
@@ -43,7 +46,6 @@ hdmi: hdmi@ff980000 {
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
- status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 543b074..6bb59ab 100644
--- a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -36,7 +36,6 @@ Example:
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
rockchip,grf = <&grf>;
- status = "okay";
ports {
#address-cells = <1>;
@@ -65,6 +64,5 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
- status = "okay";
};
};
diff --git a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
index 8096a29..cec2171 100644
--- a/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
+++ b/dts/Bindings/display/rockchip/inno_hdmi-rockchip.txt
@@ -25,7 +25,6 @@ hdmi: hdmi@20034000 {
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
- status = "disabled";
hdmi_in: port {
#address-cells = <1>;
diff --git a/dts/Bindings/display/rockchip/rockchip-vop.txt b/dts/Bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/dts/Bindings/display/rockchip/rockchip-vop.txt
+++ b/dts/Bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+ "rockchip,rk3368-vop";
+ "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+ "rockchip,rk3228-vop";
+ "rockchip,rk3328-vop";
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier
diff --git a/dts/Bindings/display/simple-framebuffer-sunxi.txt b/dts/Bindings/display/simple-framebuffer-sunxi.txt
index c46ba64..a9168ae 100644
--- a/dts/Bindings/display/simple-framebuffer-sunxi.txt
+++ b/dts/Bindings/display/simple-framebuffer-sunxi.txt
@@ -28,6 +28,5 @@ chosen {
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/display/sitronix,st7586.txt b/dts/Bindings/display/sitronix,st7586.txt
new file mode 100644
index 0000000..1d0dad1
--- /dev/null
+++ b/dts/Bindings/display/sitronix,st7586.txt
@@ -0,0 +1,22 @@
+Sitronix ST7586 display panel
+
+Required properties:
+- compatible: "lego,ev3-lcd".
+- a0-gpios: The A0 signal (since this binding is for serial mode, this is
+ the pin labeled D1 on the controller, not the pin labeled A0)
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+
+Example:
+ display@0{
+ compatible = "lego,ev3-lcd";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt
index 8e14769..74b5ac7 100644
--- a/dts/Bindings/display/st,stm32-ltdc.txt
+++ b/dts/Bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
* STMicroelectronics STM32 lcd-tft display controller
- ltdc: lcd-tft display controller host
- must be a sub-node of st-display-subsystem
Required properties:
- compatible: "st,stm32-ltdc"
- reg: Physical base address of the IP registers and length of memory mapped region.
@@ -13,8 +12,40 @@
Required nodes:
- Video port for RGB output.
-Example:
+* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
+ DesignWare MIPI DSI host controller
+The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
+DSI host controller. For all mandatory properties & nodes, please refer
+to the related documentation in [5].
+
+Mandatory properties specific to STM32 DSI:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- clock-names:
+ - phy pll reference clock string name, must be "ref".
+- resets: see [5].
+- reset-names: see [5].
+
+Mandatory nodes specific to STM32 DSI:
+- ports: A node containing DSI input & output port nodes with endpoint
+ definitions as documented in [3] & [4].
+ - port@0: DSI input port node, connected to the ltdc rgb output port.
+ - port@1: DSI output port node, connected to a panel or a bridge input port.
+- panel or bridge node: A node containing the panel or bridge description as
+ documented in [6].
+ - port: panel or bridge port node, connected to the DSI output port (port@1).
+
+Note: You can find more documentation in the following references
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
/ {
...
soc {
@@ -34,3 +65,73 @@ Example:
};
};
};
+
+Example 2: DSI panel
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+
+
+ dsi: dsi@40016c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-dsi";
+ reg = <0x40016c00 0x800>;
+ clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+ clock-names = "ref", "pclk";
+ resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+ reset-names = "apb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in_panel>;
+ };
+ };
+
+ };
+
+ panel-dsi@0 {
+ reg = <0>; /* dsi virtual channel (0..3) */
+ compatible = ...;
+ enable-gpios = ...;
+
+ port {
+ dsi_in_panel: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ };
+
+ };
+
+ };
+};
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index b83e601..9244108 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -4,15 +4,33 @@ Allwinner A10 Display Pipeline
The Allwinner A10 Display pipeline is composed of several components
that are going to be documented below:
-For the input port of all components up to the TCON in the display
-pipeline, if there are multiple components, the local endpoint IDs
-must correspond to the index of the upstream block. For example, if
-the remote endpoint is Frontend 1, then the local endpoint ID must
-be 1.
-
-Conversely, for the output ports of the same group, the remote endpoint
-ID must be the index of the local hardware block. If the local backend
-is backend 1, then the remote endpoint ID must be 1.
+For all connections between components up to the TCONs in the display
+pipeline, when there are multiple components of the same type at the
+same depth, the local endpoint ID must be the same as the remote
+component's index. For example, if the remote endpoint is Frontend 1,
+then the local endpoint ID must be 1.
+
+ Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
+ [1] -- -- [1] [1] -- -- [1]
+ \ / \ /
+ X X
+ / \ / \
+ [0] -- -- [0] [0] -- -- [0]
+ Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
+
+For a two pipeline system such as the one depicted above, the lines
+represent the connections between the components, while the numbers
+within the square brackets corresponds to the ID of the local endpoint.
+
+The same rule also applies to DE 2.0 mixer-TCON connections:
+
+ Mixer 0 [0] ----------- [0] TCON 0
+ [1] ---- ---- [1]
+ \ /
+ X
+ / \
+ [0] ---- ---- [0]
+ Mixer 1 [1] ----------- [1] TCON 1
HDMI Encoder
------------
@@ -260,7 +278,6 @@ hdmi: hdmi@01c16000 {
<&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_DEDICATED 24>;
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/dts/Bindings/dma/fsl-edma.txt b/dts/Bindings/dma/fsl-edma.txt
index 191d7bd..97e213e 100644
--- a/dts/Bindings/dma/fsl-edma.txt
+++ b/dts/Bindings/dma/fsl-edma.txt
@@ -72,5 +72,4 @@ sai2: sai@40031000 {
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
- status = "disabled";
};
diff --git a/dts/Bindings/dma/mv-xor.txt b/dts/Bindings/dma/mv-xor.txt
index c075f59..0ffb4d8 100644
--- a/dts/Bindings/dma/mv-xor.txt
+++ b/dts/Bindings/dma/mv-xor.txt
@@ -30,7 +30,6 @@ xor@d0060900 {
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
clocks = <&coreclk 0>;
- status = "okay";
xor00 {
interrupts = <51>;
diff --git a/dts/Bindings/dma/qcom_adm.txt b/dts/Bindings/dma/qcom_adm.txt
index 9bcab91..9d3b2f9 100644
--- a/dts/Bindings/dma/qcom_adm.txt
+++ b/dts/Bindings/dma/qcom_adm.txt
@@ -48,7 +48,6 @@ Each dmas request consists of 3 cells:
Example:
spi4: spi@1a280000 {
- status = "ok";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 79a204d..891db41 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -25,6 +25,7 @@ Required Properties:
- "renesas,dmac-r8a7794" (R-Car E2)
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
+ - "renesas,dmac-r8a77970" (R-Car V3M)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt
index e7780a1..1be6941 100644
--- a/dts/Bindings/dma/renesas,usb-dmac.txt
+++ b/dts/Bindings/dma/renesas,usb-dmac.txt
@@ -8,6 +8,7 @@ Required Properties:
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
+ - "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/dts/Bindings/dma/snps-dma.txt b/dts/Bindings/dma/snps-dma.txt
index 4775c66..a122723 100644
--- a/dts/Bindings/dma/snps-dma.txt
+++ b/dts/Bindings/dma/snps-dma.txt
@@ -63,7 +63,6 @@ Example:
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 35 0x4>;
- status = "disabled";
dmas = <&dmahost 12 0 1>,
<&dmahost 13 0 1 0>;
dma-names = "rx", "rx";
diff --git a/dts/Bindings/dma/st_fdma.txt b/dts/Bindings/dma/st_fdma.txt
index 495d853..52cfec9 100644
--- a/dts/Bindings/dma/st_fdma.txt
+++ b/dts/Bindings/dma/st_fdma.txt
@@ -69,7 +69,6 @@ Example:
sti_uni_player2: sti-uni-player@2 {
compatible = "st,sti-uni-player";
- status = "disabled";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
diff --git a/dts/Bindings/dma/ste-dma40.txt b/dts/Bindings/dma/ste-dma40.txt
index 95800ab..aa7dbd5 100644
--- a/dts/Bindings/dma/ste-dma40.txt
+++ b/dts/Bindings/dma/ste-dma40.txt
@@ -135,5 +135,4 @@ Example:
<&dma 13 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "rx";
- status = "disabled";
};
diff --git a/dts/Bindings/dma/sun4i-dma.txt b/dts/Bindings/dma/sun4i-dma.txt
index f1634a2..3b48438 100644
--- a/dts/Bindings/dma/sun4i-dma.txt
+++ b/dts/Bindings/dma/sun4i-dma.txt
@@ -40,7 +40,6 @@ Example:
clock-names = "ahb", "mod";
dmas = <&dma 1 29>, <&dma 1 28>;
dma-names = "rx", "tx";
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/dts/Bindings/dma/sun6i-dma.txt b/dts/Bindings/dma/sun6i-dma.txt
index 6b26704..98fbe1a 100644
--- a/dts/Bindings/dma/sun6i-dma.txt
+++ b/dts/Bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
"allwinner,sun8i-a23-dma"
"allwinner,sun8i-a83t-dma"
"allwinner,sun8i-h3-dma"
+ "allwinner,sun8i-v3s-dma"
- reg: Should contain the registers base address and length
- interrupts: Should contain a reference to the interrupt used by this device
- clocks: Should contain a reference to the parent AHB clock
diff --git a/dts/Bindings/dma/ti-dma-crossbar.txt b/dts/Bindings/dma/ti-dma-crossbar.txt
index aead586..b849a1e 100644
--- a/dts/Bindings/dma/ti-dma-crossbar.txt
+++ b/dts/Bindings/dma/ti-dma-crossbar.txt
@@ -62,7 +62,6 @@ uart1: serial@4806a000 {
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
- status = "disabled";
/* Requesting crossbar input 49 and 50 */
dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 18090e7..41f0c1a 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -9,7 +9,12 @@ execute the actual DMA tansfer.
eDMA3 Channel Controller
Required properties:
-- compatible: "ti,edma3-tpcc" for the channel controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
+ channel controller(s) on 66AK2G.
- #dma-cells: Should be set to <2>. The first number is the DMA request
number and the second is the TC the channel is serviced on.
- reg: Memory map of eDMA CC
@@ -19,8 +24,19 @@ Required properties:
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
<&tptc_phandle TC_priority_number>. The highest priority is 0.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA CC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the eDMA CC
+-------------------
- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
these channels will be SW triggered channels. See example.
- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
@@ -31,17 +47,34 @@ Optional properties:
eDMA3 Transfer Controller
Required properties:
-- compatible: "ti,edma3-tptc" for the transfer controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
+ transfer controller(s) on 66AK2G.
- reg: Memory map of eDMA TC
- interrupts: Interrupt number for TCerrint.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA TC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the given eDMA TC
+-------------------
- interrupt-names: "edma3_tcerrint"
------------------------------------------------------------------------------
-Example:
+Examples:
+1.
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
@@ -102,13 +135,64 @@ mcasp0: mcasp@48038000 {
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
- status = "disabled";
/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
+2.
+edma1: edma@02728000 {
+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+ reg = <0x02728000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "edma3_ccint", "emda3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <12 13 14 15>;
+ * for example.
+ */
+
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc0: tptc@027b0000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b0000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc1: tptc@027b8000 {
+ compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b8000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+mmc0: mmc@23000000 {
+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+ reg = <0x23000000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+ dmas = <&edma1 24 0>, <&edma1 25 0>;
+ dma-names = "tx", "rx";
+ bus-width = <4>;
+ ti,needs-special-reset;
+ no-1-8-v;
+ max-frequency = <96000000>;
+ power-domains = <&k2g_pds 0xb>;
+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+ clock-names = "fck", "mmchsdb_fck";
+ status = "disabled";
+};
+
------------------------------------------------------------------------------
DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
binding.
diff --git a/dts/Bindings/eeprom/eeprom.txt b/dts/Bindings/eeprom/eeprom.txt
index 5696eb5..afc0458 100644
--- a/dts/Bindings/eeprom/eeprom.txt
+++ b/dts/Bindings/eeprom/eeprom.txt
@@ -16,8 +16,12 @@ Required properties:
"renesas,r1ex24002"
+ The following manufacturers values have been deprecated:
+ "at", "at24"
+
If there is no specific driver for <manufacturer>, a generic
- driver based on <type> is selected. Possible types are:
+ device with <type> and manufacturer "atmel" should be used.
+ Possible types are:
"24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",
"24c128", "24c256", "24c512", "24c1024", "spd"
diff --git a/dts/Bindings/extcon/extcon-usbc-cros-ec.txt b/dts/Bindings/extcon/extcon-usbc-cros-ec.txt
new file mode 100644
index 0000000..8e8625c
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-usbc-cros-ec.txt
@@ -0,0 +1,24 @@
+ChromeOS EC USB Type-C cable and accessories detection
+
+On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is
+able to detect the state of external accessories such as display adapters
+or USB devices when said accessories are attached or detached.
+
+The node for this device must be under a cros-ec node like google,cros-ec-spi
+or google,cros-ec-i2c.
+
+Required properties:
+- compatible: Should be "google,extcon-usbc-cros-ec".
+- google,usb-port-id: Specifies the USB port ID to use.
+
+Example:
+ cros-ec@0 {
+ compatible = "google,cros-ec-i2c";
+
+ ...
+
+ extcon {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <0>;
+ };
+ }
diff --git a/dts/Bindings/fpga/altera-passive-serial.txt b/dts/Bindings/fpga/altera-passive-serial.txt
new file mode 100644
index 0000000..48478bc
--- /dev/null
+++ b/dts/Bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+ "altr,fpga-passive-serial",
+ "altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+ fpga: fpga@0 {
+ compatible = "altr,fpga-passive-serial";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/Bindings/fpga/xilinx-pr-decoupler.txt b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
new file mode 100644
index 0000000..8dcfba9
--- /dev/null
+++ b/dts/Bindings/fpga/xilinx-pr-decoupler.txt
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge. The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
+ "xlnx,pr-decoupler"
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+ 1 if driver should enable bridge at startup
+ Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+ "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
diff --git a/dts/Bindings/fpga/xilinx-slave-serial.txt b/dts/Bindings/fpga/xilinx-slave-serial.txt
index 9766f74..cfa4ed4 100644
--- a/dts/Bindings/fpga/xilinx-slave-serial.txt
+++ b/dts/Bindings/fpga/xilinx-slave-serial.txt
@@ -31,7 +31,6 @@ Example for full FPGA configuration:
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
- status = "okay";
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
diff --git a/dts/Bindings/gpio/gpio-74x164.txt b/dts/Bindings/gpio/gpio-74x164.txt
index ce1b223..2a97553 100644
--- a/dts/Bindings/gpio/gpio-74x164.txt
+++ b/dts/Bindings/gpio/gpio-74x164.txt
@@ -12,6 +12,9 @@ Required properties:
1 = active low
- registers-number: Number of daisy-chained shift registers
+Optional properties:
+- enable-gpios: GPIO connected to the OE (Output Enable) pin.
+
Example:
gpio5: gpio5@0 {
diff --git a/dts/Bindings/gpio/gpio-aspeed.txt b/dts/Bindings/gpio/gpio-aspeed.txt
index c756afa..fc6378c 100644
--- a/dts/Bindings/gpio/gpio-aspeed.txt
+++ b/dts/Bindings/gpio/gpio-aspeed.txt
@@ -18,7 +18,7 @@ Required properties:
Optional properties:
- interrupt-parent : The parent interrupt controller, optional if inherited
-- clocks : A phandle to the HPLL clock node for debounce timings
+- clocks : A phandle to the clock to use for debounce timings
The gpio and interrupt properties are further described in their respective
bindings documentation:
diff --git a/dts/Bindings/gpio/gpio-davinci.txt b/dts/Bindings/gpio/gpio-davinci.txt
index 5079ba7..8beb053 100644
--- a/dts/Bindings/gpio/gpio-davinci.txt
+++ b/dts/Bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
Davinci/Keystone GPIO controller bindings
Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+ "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+ 66AK2E SoCs
+ "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
- reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
- ti,ngpio: The number of GPIO pins supported.
- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
- line to processor.
+ line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+ the appropriate clock bindings consumer usage in,
+
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+ for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
The GPIO controller also acts as an interrupt controller. It uses the default
two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
};
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x02603000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <144>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001b 0x0>;
+ clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+ compatible = "ti,keystone-gpio";
+ reg = <0x0260bf00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* HW Interrupts mapped to GPIO pins */
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkgpio>;
+ clock-names = "gpio";
+ ti,ngpio = <32>;
+ ti,davinci-gpio-unbanked = <32>;
+};
diff --git a/dts/Bindings/gpio/gpio-mpc8xxx.txt b/dts/Bindings/gpio/gpio-mpc8xxx.txt
index 4b6cc63..69d4616 100644
--- a/dts/Bindings/gpio/gpio-mpc8xxx.txt
+++ b/dts/Bindings/gpio/gpio-mpc8xxx.txt
@@ -23,7 +23,6 @@ gpio0: gpio@1100 {
#gpio-cells = <2>;
reg = <0x1100 0x080>;
interrupts = <78 0x8>;
- status = "okay";
};
Example of gpio-controller node for a ls2080a SoC:
diff --git a/dts/Bindings/gpio/gpio-vf610.txt b/dts/Bindings/gpio/gpio-vf610.txt
index 436cc99..0ccbae4 100644
--- a/dts/Bindings/gpio/gpio-vf610.txt
+++ b/dts/Bindings/gpio/gpio-vf610.txt
@@ -5,7 +5,9 @@ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
each, and each PORT module has its own interrupt.
Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio"
+- compatible : Should be "fsl,<soc>-gpio", below is supported list:
+ "fsl,vf610-gpio"
+ "fsl,imx7ulp-gpio"
- reg : The first reg tuple represents the PORT module, the second tuple
the GPIO module.
- interrupts : Should be the port interrupt shared by all 32 pins.
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 6826a37..51c86f6 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -2,8 +2,9 @@
Required Properties:
- - compatible: should contain one of the following.
+ - compatible: should contain one or more of the following:
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+ - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
@@ -13,7 +14,14 @@ Required Properties:
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
- - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+ - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+ - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+ - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+ - "renesas,gpio-rcar": deprecated.
+
+ When compatible with the generic version nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.
- reg: Base address and length of each memory resource used by the GPIO
controller hardware module.
@@ -43,7 +51,7 @@ interrupt-controller/interrupts.txt.
Example: R8A7779 (R-Car H1) GPIO controller nodes
gpio0: gpio@ffc40000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 141 0x4>;
@@ -55,7 +63,7 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
};
...
gpio6: gpio@ffc46000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc46000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 147 0x4>;
diff --git a/dts/Bindings/gpio/spear_spics.txt b/dts/Bindings/gpio/spear_spics.txt
index 96c37eb..dd04d96 100644
--- a/dts/Bindings/gpio/spear_spics.txt
+++ b/dts/Bindings/gpio/spear_spics.txt
@@ -42,7 +42,6 @@ spics: spics@e0700000{
spi0: spi@e0100000 {
- status = "okay";
num-cs = <3>;
cs-gpios = <&gpio1 7 0>, <&spics 0>,
<&spics 1>;
diff --git a/dts/Bindings/gpu/arm,mali-midgard.txt b/dts/Bindings/gpu/arm,mali-midgard.txt
index 5aa5926..039219d 100644
--- a/dts/Bindings/gpu/arm,mali-midgard.txt
+++ b/dts/Bindings/gpu/arm,mali-midgard.txt
@@ -17,6 +17,7 @@ Required properties:
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ + "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
diff --git a/dts/Bindings/gpu/arm,mali-utgard.txt b/dts/Bindings/gpu/arm,mali-utgard.txt
index 2b6243e..b4ebd56 100644
--- a/dts/Bindings/gpu/arm,mali-utgard.txt
+++ b/dts/Bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ + allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ stericsson,db8500-mali
@@ -58,6 +59,10 @@ to specify one more vendor-specific compatible, among:
Required properties:
* resets: phandle to the reset line for the GPU
+ - allwinner,sun50i-h5-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
- stericsson,db8500-mali
Required properties:
* interrupt-names and interrupts:
diff --git a/dts/Bindings/gpu/nvidia,gk20a.txt b/dts/Bindings/gpu/nvidia,gk20a.txt
index b7e4c74..f32bbba 100644
--- a/dts/Bindings/gpu/nvidia,gk20a.txt
+++ b/dts/Bindings/gpu/nvidia,gk20a.txt
@@ -51,7 +51,6 @@ Example for GK20A:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GM20B:
@@ -70,7 +69,6 @@ Example for GM20B:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GP10B:
@@ -89,5 +87,4 @@ Example for GP10B:
reset-names = "gpu";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
- status = "disabled";
};
diff --git a/dts/Bindings/gpu/samsung-g2d.txt b/dts/Bindings/gpu/samsung-g2d.txt
index c4f358d..1e79593 100644
--- a/dts/Bindings/gpu/samsung-g2d.txt
+++ b/dts/Bindings/gpu/samsung-g2d.txt
@@ -24,5 +24,4 @@ Example:
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
- status = "disabled";
};
diff --git a/dts/Bindings/hsi/omap-ssi.txt b/dts/Bindings/hsi/omap-ssi.txt
index f26625e..b8eca3c 100644
--- a/dts/Bindings/hsi/omap-ssi.txt
+++ b/dts/Bindings/hsi/omap-ssi.txt
@@ -92,6 +92,5 @@ ssi-controller@48058000 {
interrupts = <69>,
<70>;
- status = "disabled"; /* second port is not used on N900 */
}
}
diff --git a/dts/Bindings/hwmon/aspeed-pwm-tacho.txt b/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
index cf44605..367c820 100644
--- a/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
+++ b/dts/Bindings/hwmon/aspeed-pwm-tacho.txt
@@ -11,6 +11,8 @@ Required properties for pwm-tacho node:
- #size-cells : should be 1.
+- #cooling-cells: should be 2.
+
- reg : address and length of the register set for the device.
- pinctrl-names : a pinctrl state named "default" must be defined.
@@ -28,12 +30,17 @@ fan subnode format:
Under fan subnode there can upto 8 child nodes, with each child node
representing a fan. If there are 8 fans each fan can have one PWM port and
one/two Fan tach inputs.
+For PWM port can be configured cooling-levels to create cooling device.
+Cooling device could be bound to a thermal zone for the thermal control.
Required properties for each child node:
- reg : should specify PWM source port.
integer value in the range 0 to 7 with 0 indicating PWM port A and
7 indicating PWM port H.
+- cooling-levels: PWM duty cycle values in a range from 0 to 255
+ which correspond to thermal cooling states.
+
- aspeed,fan-tach-ch : should specify the Fan tach input channel.
integer value in the range 0 through 15, with 0 indicating
Fan tach channel 0 and 15 indicating Fan tach channel 15.
@@ -50,6 +57,7 @@ pwm_tacho_fixed_clk: fixedclk {
pwm_tacho: pwmtachocontroller@1e786000 {
#address-cells = <1>;
#size-cells = <1>;
+ #cooling-cells = <2>;
reg = <0x1E786000 0x1000>;
compatible = "aspeed,ast2500-pwm-tacho";
clocks = <&pwm_tacho_fixed_clk>;
@@ -58,6 +66,7 @@ pwm_tacho: pwmtachocontroller@1e786000 {
fan@0 {
reg = <0x00>;
+ cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
diff --git a/dts/Bindings/hwmon/ibm,cffps1.txt b/dts/Bindings/hwmon/ibm,cffps1.txt
new file mode 100644
index 0000000..f68a0a6
--- /dev/null
+++ b/dts/Bindings/hwmon/ibm,cffps1.txt
@@ -0,0 +1,21 @@
+Device-tree bindings for IBM Common Form Factor Power Supply Version 1
+----------------------------------------------------------------------
+
+Required properties:
+ - compatible = "ibm,cffps1";
+ - reg = < I2C bus address >; : Address of the power supply on the
+ I2C bus.
+
+Example:
+
+ i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ < more properties >
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/ltq-cputemp.txt b/dts/Bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index 0000000..33fd00a
--- /dev/null
+++ b/dts/Bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor
+
+Requires node properties:
+- compatible value :
+ "lantiq,cputemp"
+
+Example:
+ cputemp@0 {
+ compatible = "lantiq,cputemp";
+ };
diff --git a/dts/Bindings/i2c/i2c-altera.txt b/dts/Bindings/i2c/i2c-altera.txt
new file mode 100644
index 0000000..767664f
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-altera.txt
@@ -0,0 +1,39 @@
+* Altera I2C Controller
+* This is Altera's synthesizable logic block I2C Controller for use
+* in Altera's FPGAs.
+
+Required properties :
+ - compatible : should be "altr,softip-i2c-v1.0"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+ - clocks : phandle to input clock.
+ - #address-cells = <1>;
+ - #size-cells = <0>;
+
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties :
+ - fifo-size : Size of the RX and TX FIFOs in bytes.
+ - Child nodes conforming to i2c bus binding
+
+Example :
+
+ i2c@100080000 {
+ compatible = "altr,softip-i2c-v1.0";
+ reg = <0x00000001 0x00080000 0x00000040>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 43 4>;
+ clocks = <&clk_0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fifo-size = <4>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+ };
+
diff --git a/dts/Bindings/i2c/i2c-cbus-gpio.txt b/dts/Bindings/i2c/i2c-cbus-gpio.txt
index 8ce9cd2..c143948 100644
--- a/dts/Bindings/i2c/i2c-cbus-gpio.txt
+++ b/dts/Bindings/i2c/i2c-cbus-gpio.txt
@@ -20,8 +20,8 @@ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
- retu-mfd: retu@1 {
- compatible = "retu-mfd";
+ retu: retu@1 {
+ compatible = "nokia,retu";
reg = <0x1>;
};
};
diff --git a/dts/Bindings/i2c/i2c-demux-pinctrl.txt b/dts/Bindings/i2c/i2c-demux-pinctrl.txt
index 7ce23ac..81b5d55 100644
--- a/dts/Bindings/i2c/i2c-demux-pinctrl.txt
+++ b/dts/Bindings/i2c/i2c-demux-pinctrl.txt
@@ -102,7 +102,6 @@ And for clarification, here are the snipplets for the i2c-parents:
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- status = "disabled";
gpios = <&gpio5 6 GPIO_ACTIVE_HIGH /* sda */
&gpio5 5 GPIO_ACTIVE_HIGH /* scl */
>;
diff --git a/dts/Bindings/i2c/i2c-efm32.txt b/dts/Bindings/i2c/i2c-efm32.txt
index 50b25c3..3b30e54 100644
--- a/dts/Bindings/i2c/i2c-efm32.txt
+++ b/dts/Bindings/i2c/i2c-efm32.txt
@@ -22,7 +22,6 @@ Example:
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
- status = "ok";
energymicro,location = <3>;
eeprom@50 {
diff --git a/dts/Bindings/i2c/i2c-mtk.txt b/dts/Bindings/i2c/i2c-mtk.txt
index bd5a7be..ff7bf37 100644
--- a/dts/Bindings/i2c/i2c-mtk.txt
+++ b/dts/Bindings/i2c/i2c-mtk.txt
@@ -1,14 +1,15 @@
-* Mediatek's I2C controller
+* MediaTek's I2C controller
-The Mediatek's I2C controller is used to interface with I2C devices.
+The MediaTek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
- "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
- "mediatek,mt6577-i2c": for i2c compatible with mt6577.
- "mediatek,mt6589-i2c": for i2c compatible with mt6589.
- "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
- "mediatek,mt8173-i2c": for i2c compatible with mt8173.
+ "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
+ "mediatek,mt6577-i2c": for MediaTek MT6577
+ "mediatek,mt6589-i2c": for MediaTek MT6589
+ "mediatek,mt7622-i2c": for MediaTek MT7622
+ "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
+ "mediatek,mt8173-i2c": for MediaTek MT8173
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index 2b8bd33..cad39ae 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -2,6 +2,8 @@ I2C for R-Car platforms
Required properties:
- compatible:
+ "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
+ "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
@@ -12,7 +14,8 @@ Required properties:
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ device.
"renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
"renesas,i2c-rcar" (deprecated)
diff --git a/dts/Bindings/i2c/i2c-rk3x.txt b/dts/Bindings/i2c/i2c-rk3x.txt
index e18445d..22f2eeb 100644
--- a/dts/Bindings/i2c/i2c-rk3x.txt
+++ b/dts/Bindings/i2c/i2c-rk3x.txt
@@ -7,6 +7,7 @@ Required properties :
- reg : Offset and length of the register set for the device
- compatible: should be one of the following:
+ - "rockchip,rv1108-i2c": for rv1108
- "rockchip,rk3066-i2c": for rk3066
- "rockchip,rk3188-i2c": for rk3188
- "rockchip,rk3228-i2c": for rk3228
diff --git a/dts/Bindings/i2c/i2c-sh_mobile.txt b/dts/Bindings/i2c/i2c-sh_mobile.txt
index ae9c2a7..2243909 100644
--- a/dts/Bindings/i2c/i2c-sh_mobile.txt
+++ b/dts/Bindings/i2c/i2c-sh_mobile.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible :
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
+ - "renesas,iic-r8a7743" (RZ/G1M)
+ - "renesas,iic-r8a7745" (RZ/G1E)
- "renesas,iic-r8a7790" (R-Car H2)
- "renesas,iic-r8a7791" (R-Car M2-W)
- "renesas,iic-r8a7792" (R-Car V2H)
@@ -12,7 +14,8 @@ Required properties:
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
+ - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
+ compatible device)
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
- "renesas,rmobile-iic" (generic device)
diff --git a/dts/Bindings/i2c/i2c-sprd.txt b/dts/Bindings/i2c/i2c-sprd.txt
new file mode 100644
index 0000000..60b7cda
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-sprd.txt
@@ -0,0 +1,31 @@
+I2C for Spreadtrum platforms
+
+Required properties:
+- compatible: Should be "sprd,sc9860-i2c".
+- reg: Specify the physical base address of the controller and length
+ of memory mapped region.
+- interrupts: Should contain I2C interrupt.
+- clock-names: Should contain following entries:
+ "i2c" for I2C clock,
+ "source" for I2C source (parent) clock,
+ "enable" for I2C module enable clock.
+- clocks: Should contain a clock specifier for each entry in clock-names.
+- clock-frequency: Constains desired I2C bus clock frequency in Hz.
+- #address-cells: Should be 1 to describe address cells for I2C device address.
+- #size-cells: Should be 0 means no size cell for I2C device address.
+
+Optional properties:
+- Child nodes conforming to I2C bus binding
+
+Examples:
+i2c0: i2c@70500000 {
+ compatible = "sprd,sc9860-i2c";
+ reg = <0 0x70500000 0 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c", "source", "enable";
+ clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
diff --git a/dts/Bindings/i2c/i2c-stm32.txt b/dts/Bindings/i2c/i2c-stm32.txt
index 78eaf7b..3b54899 100644
--- a/dts/Bindings/i2c/i2c-stm32.txt
+++ b/dts/Bindings/i2c/i2c-stm32.txt
@@ -1,7 +1,9 @@
* I2C controller embedded in STMicroelectronics STM32 I2C platform
Required properties :
-- compatible : Must be "st,stm32f4-i2c"
+- compatible : Must be one of the following
+ - "st,stm32f4-i2c"
+ - "st,stm32f7-i2c"
- reg : Offset and length of the register set for the device
- interrupts : Must contain the interrupt id for I2C event and then the
interrupt id for I2C error.
@@ -14,8 +16,16 @@ Required properties :
Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
- the default 100 kHz frequency will be used. As only Normal and Fast modes
- are supported, possible values are 100000 and 400000.
+ the default 100 kHz frequency will be used.
+ For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
+ 100000 and 400000.
+ For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
+ possible values are 100000, 400000 and 1000000.
+- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
+ (default: 25)
+- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
+ (default: 10)
+ I2C Timings are derived from these 2 values
Example :
@@ -31,3 +41,16 @@ Example :
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
pinctrl-names = "default";
};
+
+ i2c@40005400 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+ clocks = <&rcc 1 CLK_I2C1>;
+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+ pinctrl-names = "default";
+ };
diff --git a/dts/Bindings/i2c/nvidia,tegra20-i2c.txt b/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
index 656716b..f64064f 100644
--- a/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/dts/Bindings/i2c/nvidia,tegra20-i2c.txt
@@ -71,5 +71,4 @@ Example:
reset-names = "i2c";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
index 3223684..552e7a8 100644
--- a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
@@ -11,6 +11,11 @@ Required properties:
- atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
- atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
- atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
+ - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
+ trigger pin. When the specific edge type is detected, the conversion will
+ start. Possible values are rising, falling, or both.
+ This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
+ IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
Example:
@@ -25,4 +30,5 @@ adc: adc@fc030000 {
atmel,startup-time-ms = <4>;
vddana-supply = <&vdd_3v3_lp_reg>;
vref-supply = <&vdd_3v3_lp_reg>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
}
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
index caaaed7..7b1b1e4 100644
--- a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
+++ b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
@@ -37,5 +37,4 @@ For example:
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/lpc1850-adc.txt b/dts/Bindings/iio/adc/lpc1850-adc.txt
index 0bcae51..9ada5ab 100644
--- a/dts/Bindings/iio/adc/lpc1850-adc.txt
+++ b/dts/Bindings/iio/adc/lpc1850-adc.txt
@@ -17,5 +17,4 @@ adc0: adc@400e3000 {
clocks = <&ccu1 CLK_APB3_ADC0>;
vref-supply = <&reg_vdda>;
resets = <&rgu 40>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/adc/mt6577_auxadc.txt b/dts/Bindings/iio/adc/mt6577_auxadc.txt
index 68c45cb..64dc484 100644
--- a/dts/Bindings/iio/adc/mt6577_auxadc.txt
+++ b/dts/Bindings/iio/adc/mt6577_auxadc.txt
@@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+ - "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
diff --git a/dts/Bindings/iio/adc/rockchip-saradc.txt b/dts/Bindings/iio/adc/rockchip-saradc.txt
index e0a9b9d..c2c50b5 100644
--- a/dts/Bindings/iio/adc/rockchip-saradc.txt
+++ b/dts/Bindings/iio/adc/rockchip-saradc.txt
@@ -6,6 +6,7 @@ Required properties:
- "rockchip,rk3066-tsadc": for rk3036
- "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328
- "rockchip,rk3399-saradc": for rk3399
+ - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/iio/adc/st,stm32-adc.txt b/dts/Bindings/iio/adc/st,stm32-adc.txt
index 8310073..48bfcaa 100644
--- a/dts/Bindings/iio/adc/st,stm32-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-adc.txt
@@ -74,6 +74,11 @@ Optional properties:
* can be 6, 8, 10 or 12 on stm32f4
* can be 8, 10, 12, 14 or 16 on stm32h7
Default is maximum resolution if unset.
+- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
+ Depending on hardware (board) e.g. high/low analog input source impedance,
+ fine tune of ADC sampling time may be recommended.
+ This can be either one value or an array that matches 'st,adc-channels' list,
+ to set sample time resp. for all channels, or independently for each channel.
Example:
adc: adc@40012000 {
diff --git a/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt b/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt
new file mode 100644
index 0000000..a04aa5c
--- /dev/null
+++ b/dts/Bindings/iio/counter/stm32-lptimer-cnt.txt
@@ -0,0 +1,27 @@
+STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
+
+STM32 Low-Power Timer provides several counter modes. It can be used as:
+- quadrature encoder to detect angular position and direction of rotary
+ elements, from IN1 and IN2 input signals.
+- simple counter from IN1 input signal.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-counter".
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes,
+ to set IN1/IN2 pins in mode of operation for Low-Power
+ Timer input on external pin.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/dts/Bindings/iio/dac/lpc1850-dac.txt b/dts/Bindings/iio/dac/lpc1850-dac.txt
index 7d6647d..42db783 100644
--- a/dts/Bindings/iio/dac/lpc1850-dac.txt
+++ b/dts/Bindings/iio/dac/lpc1850-dac.txt
@@ -16,5 +16,4 @@ dac: dac@400e1000 {
clocks = <&ccu1 CLK_APB3_DAC>;
vref-supply = <&reg_vdda>;
resets = <&rgu 42>;
- status = "disabled";
};
diff --git a/dts/Bindings/iio/dac/st,stm32-dac.txt b/dts/Bindings/iio/dac/st,stm32-dac.txt
index bcee71f..bf2925c 100644
--- a/dts/Bindings/iio/dac/st,stm32-dac.txt
+++ b/dts/Bindings/iio/dac/st,stm32-dac.txt
@@ -10,7 +10,9 @@ current.
Contents of a stm32 dac root node:
-----------------------------------
Required properties:
-- compatible: Must be "st,stm32h7-dac-core".
+- compatible: Should be one of:
+ "st,stm32f4-dac-core"
+ "st,stm32h7-dac-core"
- reg: Offset and length of the device's register set.
- clocks: Must contain an entry for pclk (which feeds the peripheral bus
interface)
diff --git a/dts/Bindings/iio/humidity/hdc100x.txt b/dts/Bindings/iio/humidity/hdc100x.txt
new file mode 100644
index 0000000..c52333b
--- /dev/null
+++ b/dts/Bindings/iio/humidity/hdc100x.txt
@@ -0,0 +1,17 @@
+* HDC100x temperature + humidity sensors
+
+Required properties:
+ - compatible: Should contain one of the following:
+ ti,hdc1000
+ ti,hdc1008
+ ti,hdc1010
+ ti,hdc1050
+ ti,hdc1080
+ - reg: i2c address of the sensor
+
+Example:
+
+hdc100x@40 {
+ compatible = "ti,hdc1000";
+ reg = <0x40>;
+};
diff --git a/dts/Bindings/iio/humidity/hts221.txt b/dts/Bindings/iio/humidity/hts221.txt
index b20ab9c..10adeb0 100644
--- a/dts/Bindings/iio/humidity/hts221.txt
+++ b/dts/Bindings/iio/humidity/hts221.txt
@@ -5,9 +5,18 @@ Required properties:
- reg: i2c address of the sensor / spi cs line
Optional properties:
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
+ Refer to pinctrl/pinctrl-bindings.txt for the property description.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+ flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
+ IRQ_TYPE_EDGE_FALLING.
Refer to interrupt-controller/interrupts.txt for generic interrupt
client node bindings.
diff --git a/dts/Bindings/iio/humidity/htu21.txt b/dts/Bindings/iio/humidity/htu21.txt
new file mode 100644
index 0000000..97d7963
--- /dev/null
+++ b/dts/Bindings/iio/humidity/htu21.txt
@@ -0,0 +1,13 @@
+*HTU21 - Measurement-Specialties htu21 temperature & humidity sensor and humidity part of MS8607 sensor
+
+Required properties:
+
+ - compatible: should be "meas,htu21" or "meas,ms8607-humidity"
+ - reg: I2C address of the sensor
+
+Example:
+
+htu21@40 {
+ compatible = "meas,htu21";
+ reg = <0x40>;
+};
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
index 6f28ff5..1ff1af7 100644
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/dts/Bindings/iio/imu/st_lsm6dsx.txt
@@ -11,6 +11,14 @@ Required properties:
Optional properties:
- st,drdy-int-pin: the pin on the package that will be used to signal
"data ready" (valid values: 1 or 2).
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ (This binding is taken from pinctrl/pinctrl-bindings.txt)
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
diff --git a/dts/Bindings/iio/pressure/ms5637.txt b/dts/Bindings/iio/pressure/ms5637.txt
new file mode 100644
index 0000000..1f43ffa
--- /dev/null
+++ b/dts/Bindings/iio/pressure/ms5637.txt
@@ -0,0 +1,17 @@
+* MS5637 - Measurement-Specialties MS5637, MS5805, MS5837 and MS8607 pressure & temperature sensor
+
+Required properties:
+
+ -compatible: should be one of the following
+ meas,ms5637
+ meas,ms5805
+ meas,ms5837
+ meas,ms8607-temppressure
+ -reg: I2C address of the sensor
+
+Example:
+
+ms5637@76 {
+ compatible = "meas,ms5637";
+ reg = <0x76>;
+};
diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt
index eaa8fbb..9ec6f5c 100644
--- a/dts/Bindings/iio/st-sensors.txt
+++ b/dts/Bindings/iio/st-sensors.txt
@@ -45,6 +45,7 @@ Accelerometers:
- st,lis2dh12-accel
- st,h3lis331dl-accel
- st,lng2dm-accel
+- st,lis3l02dq
Gyroscopes:
- st,l3g4200d-gyro
@@ -52,6 +53,7 @@ Gyroscopes:
- st,lsm330dl-gyro
- st,lsm330dlc-gyro
- st,l3gd20-gyro
+- st,l3gd20h-gyro
- st,l3g4is-gyro
- st,lsm330-gyro
- st,lsm9ds0-gyro
@@ -62,6 +64,7 @@ Magnetometers:
- st,lsm303dlhc-magn
- st,lsm303dlm-magn
- st,lis3mdl-magn
+- st,lis2mdl
Pressure sensors:
- st,lps001wp-press
diff --git a/dts/Bindings/iio/temperature/tsys01.txt b/dts/Bindings/iio/temperature/tsys01.txt
new file mode 100644
index 0000000..0d5cc55
--- /dev/null
+++ b/dts/Bindings/iio/temperature/tsys01.txt
@@ -0,0 +1,19 @@
+* TSYS01 - Measurement Specialties temperature sensor
+
+Required properties:
+
+ - compatible: should be "meas,tsys01"
+ - reg: I2C address of the sensor (changeable via CSB pin)
+
+ ------------------------
+ | CSB | Device Address |
+ ------------------------
+ 1 0x76
+ 0 0x77
+
+Example:
+
+tsys01@76 {
+ compatible = "meas,tsys01";
+ reg = <0x76>;
+};
diff --git a/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt b/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt
new file mode 100644
index 0000000..85e6806
--- /dev/null
+++ b/dts/Bindings/iio/timer/stm32-lptimer-trigger.txt
@@ -0,0 +1,23 @@
+STMicroelectronics STM32 Low-Power Timer Trigger
+
+STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
+by STM32 internal ADC and/or DAC.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-trigger".
+- reg: Identify trigger hardware block. Must be 0, 1 or 2
+ respectively for lptimer1, lptimer2 or lptimer3
+ trigger output.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/iio/timer/stm32-timer-trigger.txt b/dts/Bindings/iio/timer/stm32-timer-trigger.txt
index 55a653d..b8e8c76 100644
--- a/dts/Bindings/iio/timer/stm32-timer-trigger.txt
+++ b/dts/Bindings/iio/timer/stm32-timer-trigger.txt
@@ -4,7 +4,9 @@ Must be a sub-node of an STM32 Timers device tree node.
See ../mfd/stm32-timers.txt for details about the parent node.
Required parameters:
-- compatible: Must be "st,stm32-timer-trigger".
+- compatible: Must be one of:
+ "st,stm32-timer-trigger"
+ "st,stm32h7-timer-trigger"
- reg: Identify trigger hardware block.
Example:
@@ -14,7 +16,7 @@ Example:
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 160>;
- clock-names = "clk_int";
+ clock-names = "int";
timer@0 {
compatible = "st,stm32-timer-trigger";
diff --git a/dts/Bindings/input/atmel,maxtouch.txt b/dts/Bindings/input/atmel,maxtouch.txt
index 1852906..23e3abc 100644
--- a/dts/Bindings/input/atmel,maxtouch.txt
+++ b/dts/Bindings/input/atmel,maxtouch.txt
@@ -22,6 +22,8 @@ Optional properties for main touchpad device:
experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
+
Example:
touch@4b {
diff --git a/dts/Bindings/input/brcm,bcm-keypad.txt b/dts/Bindings/input/brcm,bcm-keypad.txt
index b77f50b..262deab 100644
--- a/dts/Bindings/input/brcm,bcm-keypad.txt
+++ b/dts/Bindings/input/brcm,bcm-keypad.txt
@@ -72,7 +72,6 @@ Example:
/* Required Board specific properties */
keypad,num-rows = <5>;
keypad,num-columns = <5>;
- status = "okay";
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
diff --git a/dts/Bindings/input/pwm-vibrator.txt b/dts/Bindings/input/pwm-vibrator.txt
new file mode 100644
index 0000000..09145d1
--- /dev/null
+++ b/dts/Bindings/input/pwm-vibrator.txt
@@ -0,0 +1,66 @@
+* PWM vibrator device tree bindings
+
+Registers a PWM device as vibrator. It is expected, that the vibrator's
+strength increases based on the duty cycle of the enable PWM channel
+(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
+
+The binding supports an optional direction PWM channel, that can be
+driven at fixed duty cycle. If available this is can be used to increase
+the vibration effect of some devices.
+
+Required properties:
+- compatible: should contain "pwm-vibrator"
+- pwm-names: Should contain "enable" and optionally "direction"
+- pwms: Should contain a PWM handle for each entry in pwm-names
+
+Optional properties:
+- vcc-supply: Phandle for the regulator supplying power
+- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
+ nanoseconds, defaults to 50% of the channel's
+ period.
+
+Example from Motorola Droid 4:
+
+&omap4_pmx_core {
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+/ {
+ pwm8: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm8 0 1000000000 0>,
+ <&pwm9 0 1000000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <1000000000>;
+ };
+};
diff --git a/dts/Bindings/input/ti,drv260x.txt b/dts/Bindings/input/ti,drv260x.txt
index ee09c8f..4c5312e 100644
--- a/dts/Bindings/input/ti,drv260x.txt
+++ b/dts/Bindings/input/ti,drv260x.txt
@@ -43,7 +43,7 @@ haptics: haptics@5a {
mode = <DRV260X_LRA_MODE>;
library-sel = <DRV260X_LIB_LRA>;
vib-rated-mv = <3200>;
- vib-overdriver-mv = <3200>;
+ vib-overdrive-mv = <3200>;
}
For more product information please see the link below:
diff --git a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
index 9d9e930..df531b5 100644
--- a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
+++ b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
@@ -32,5 +32,4 @@ Example:
pinctrl-1 = <&pinctrl_touchctrl_default>;
pinctrl-2 = <&pinctrl_touchctrl_gpios>;
vf50-ts-min-pressure = <200>;
- status = "disabled";
};
diff --git a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
index d4927c2..e67e58b 100644
--- a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
+++ b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
@@ -35,5 +35,4 @@ Example:
measure-delay-time = <0xfff>;
pre-charge-time = <0xffff>;
touchscreen-average-samples = <32>;
- status = "okay";
};
diff --git a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 9e38949..49ccabb 100644
--- a/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -4,8 +4,10 @@ Required properties:
- compatible: should be "fsl,<soc-name>-msi" to identify
Layerscape PCIe MSI controller block such as:
- "fsl,1s1021a-msi"
- "fsl,1s1043a-msi"
+ "fsl,ls1021a-msi"
+ "fsl,ls1043a-msi"
+ "fsl,ls1046a-msi"
+ "fsl,ls1043a-v1.1-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +25,7 @@ MSI controller node
Examples:
msi1: msi-controller@1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>,
msi-controller;
interrupts = <0 116 0x4>;
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87a..07bf0b9 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+ "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
new file mode 100644
index 0000000..48e71d3
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
@@ -0,0 +1,32 @@
+UniPhier AIDET
+
+UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
+Interrupt Controller). GIC itself can handle only high level and rising edge
+interrupts. The AIDET provides logic inverter to support low level and falling
+edge interrupts.
+
+Required properties:
+- compatible: Should be one of the following:
+ "socionext,uniphier-ld4-aidet" - for LD4 SoC
+ "socionext,uniphier-pro4-aidet" - for Pro4 SoC
+ "socionext,uniphier-sld8-aidet" - for sLD8 SoC
+ "socionext,uniphier-pro5-aidet" - for Pro5 SoC
+ "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC
+ "socionext,uniphier-ld11-aidet" - for LD11 SoC
+ "socionext,uniphier-ld20-aidet" - for LD20 SoC
+ "socionext,uniphier-pxs3-aidet" - for PXs3 SoC
+- reg: Specifies offset and length of the register set for the device.
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an interrupt
+ source. The value should be 2. The first cell defines the interrupt number
+ (corresponds to the SPI interrupt number of GIC). The second cell specifies
+ the trigger type as defined in interrupts.txt in this directory.
+
+Example:
+
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/iommu/qcom,iommu.txt b/dts/Bindings/iommu/qcom,iommu.txt
new file mode 100644
index 0000000..b2641ce
--- /dev/null
+++ b/dts/Bindings/iommu/qcom,iommu.txt
@@ -0,0 +1,121 @@
+* QCOM IOMMU v1 Implementation
+
+Qualcomm "B" family devices which are not compatible with arm-smmu have
+a similar looking IOMMU but without access to the global register space,
+and optionally requiring additional configuration to route context irqs
+to non-secure vs secure interrupt line.
+
+** Required properties:
+
+- compatible : Should be one of:
+
+ "qcom,msm8916-iommu"
+
+ Followed by "qcom,msm-iommu-v1".
+
+- clock-names : Should be a pair of "iface" (required for IOMMUs
+ register group access) and "bus" (required for
+ the IOMMUs underlying bus access).
+
+- clocks : Phandles for respective clocks described by
+ clock-names.
+
+- #address-cells : must be 1.
+
+- #size-cells : must be 1.
+
+- #iommu-cells : Must be 1. Index identifies the context-bank #.
+
+- ranges : Base address and size of the iommu context banks.
+
+- qcom,iommu-secure-id : secure-id.
+
+- List of sub-nodes, one per translation context bank. Each sub-node
+ has the following required properties:
+
+ - compatible : Should be one of:
+ - "qcom,msm-iommu-v1-ns" : non-secure context bank
+ - "qcom,msm-iommu-v1-sec" : secure context bank
+ - reg : Base address and size of context bank within the iommu
+ - interrupts : The context fault irq.
+
+** Optional properties:
+
+- reg : Base address and size of the SMMU local base, should
+ be only specified if the iommu requires configuration
+ for routing of context bank irq's to secure vs non-
+ secure lines. (Ie. if the iommu contains secure
+ context banks)
+
+
+** Examples:
+
+ apps_iommu: iommu@1e20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1e20000 0x40000>;
+ reg = <0x1ef0000 0x3000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <17>;
+
+ // mdp_0:
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // venus_ns:
+ iommu-ctx@5000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x5000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1f08000 0x10000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <18>;
+
+ // gfx3d_user:
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // gfx3d_priv:
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ...
+
+ venus: video-codec@1d00000 {
+ ...
+ iommus = <&apps_iommu 5>;
+ };
+
+ mdp: mdp@1a01000 {
+ ...
+ iommus = <&apps_iommu 4>;
+ };
+
+ gpu@01c00000 {
+ ...
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ };
diff --git a/dts/Bindings/iommu/rockchip,iommu.txt b/dts/Bindings/iommu/rockchip,iommu.txt
index 9a55ac3..2098f77 100644
--- a/dts/Bindings/iommu/rockchip,iommu.txt
+++ b/dts/Bindings/iommu/rockchip,iommu.txt
@@ -15,6 +15,11 @@ Required properties:
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
+Optional properties:
+- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
+ Some mmu instances may produce unexpected results
+ when the reset operation is used.
+
Example:
vopl_mmu: iommu@ff940300 {
diff --git a/dts/Bindings/leds/ams,as3645a.txt b/dts/Bindings/leds/ams,as3645a.txt
new file mode 100644
index 0000000..12c5ef2
--- /dev/null
+++ b/dts/Bindings/leds/ams,as3645a.txt
@@ -0,0 +1,71 @@
+Analog devices AS3645A device tree bindings
+
+The AS3645A flash LED controller can drive two LEDs, one high current
+flash LED and one indicator LED. The high current flash LED can be
+used in torch mode as well.
+
+Ranges below noted as [a, b] are closed ranges between a and b, i.e. a
+and b are included in the range.
+
+Please also see common.txt in the same directory.
+
+
+Required properties
+===================
+
+compatible : Must be "ams,as3645a".
+reg : The I2C address of the device. Typically 0x30.
+
+
+Required properties of the "flash" child node
+=============================================
+
+flash-timeout-us: Flash timeout in microseconds. The value must be in
+ the range [100000, 850000] and divisible by 50000.
+flash-max-microamp: Maximum flash current in microamperes. Has to be
+ in the range between [200000, 500000] and
+ divisible by 20000.
+led-max-microamp: Maximum torch (assist) current in microamperes. The
+ value must be in the range between [20000, 160000] and
+ divisible by 20000.
+ams,input-max-microamp: Maximum flash controller input current. The
+ value must be in the range [1250000, 2000000]
+ and divisible by 50000.
+
+
+Optional properties of the "flash" child node
+=============================================
+
+label : The label of the flash LED.
+
+
+Required properties of the "indicator" child node
+=================================================
+
+led-max-microamp: Maximum indicator current. The allowed values are
+ 2500, 5000, 7500 and 10000.
+
+Optional properties of the "indicator" child node
+=================================================
+
+label : The label of the indicator LED.
+
+
+Example
+=======
+
+ as3645a@30 {
+ reg = <0x30>;
+ compatible = "ams,as3645a";
+ flash {
+ flash-timeout-us = <150000>;
+ flash-max-microamp = <320000>;
+ led-max-microamp = <60000>;
+ ams,input-max-microamp = <1750000>;
+ label = "as3645a:flash";
+ };
+ indicator {
+ led-max-microamp = <10000>;
+ label = "as3645a:indicator";
+ };
+ };
diff --git a/dts/Bindings/leds/irled/gpio-ir-tx.txt b/dts/Bindings/leds/irled/gpio-ir-tx.txt
new file mode 100644
index 0000000..cbe8dfd
--- /dev/null
+++ b/dts/Bindings/leds/irled/gpio-ir-tx.txt
@@ -0,0 +1,14 @@
+Device tree bindings for IR LED connected through gpio pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "gpio-ir-tx".
+ - gpios : Should specify the IR LED GPIO, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs
+ should be indicated using flags in the GPIO specifier.
+
+Example:
+ irled@0 {
+ compatible = "gpio-ir-tx";
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/leds/irled/pwm-ir-tx.txt b/dts/Bindings/leds/irled/pwm-ir-tx.txt
new file mode 100644
index 0000000..66e5672
--- /dev/null
+++ b/dts/Bindings/leds/irled/pwm-ir-tx.txt
@@ -0,0 +1,13 @@
+Device tree bindings for IR LED connected through pwm pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "pwm-ir-tx".
+ - pwms : PWM property to point to the PWM device (phandle)/port (id)
+ and to specify the period time to be used: <&phandle id period_ns>;
+
+Example:
+ irled {
+ compatible = "pwm-ir-tx";
+ pwms = <&pwm0 0 10000000>;
+ };
diff --git a/dts/Bindings/leds/leds-gpio.txt b/dts/Bindings/leds/leds-gpio.txt
index 76535ca..a48dda2 100644
--- a/dts/Bindings/leds/leds-gpio.txt
+++ b/dts/Bindings/leds/leds-gpio.txt
@@ -18,6 +18,9 @@ LED sub-node properties:
see Documentation/devicetree/bindings/leds/common.txt
- retain-state-suspended: (optional) The suspend state can be retained.Such
as charge-led gpio.
+- retain-state-shutdown: (optional) Retain the state of the LED on shutdown.
+ Useful in BMC systems, for example when the BMC is rebooted while the host
+ remains up.
- panic-indicator : (optional)
see Documentation/devicetree/bindings/leds/common.txt
diff --git a/dts/Bindings/leds/leds-pca955x.txt b/dts/Bindings/leds/leds-pca955x.txt
new file mode 100644
index 0000000..7984efb
--- /dev/null
+++ b/dts/Bindings/leds/leds-pca955x.txt
@@ -0,0 +1,88 @@
+* NXP - pca955x LED driver
+
+The PCA955x family of chips are I2C LED blinkers whose pins not used
+to control LEDs can be used as general purpose I/Os. The GPIO pins can
+be input or output, and output pins can also be pulse-width controlled.
+
+Required properties:
+- compatible : should be one of :
+ "nxp,pca9550"
+ "nxp,pca9551"
+ "nxp,pca9552"
+ "nxp,pca9553"
+- #address-cells: must be 1
+- #size-cells: must be 0
+- reg: I2C slave address. depends on the model.
+
+Optional properties:
+- gpio-controller: allows pins to be used as GPIOs.
+- #gpio-cells: must be 2.
+- gpio-line-names: define the names of the GPIO lines
+
+LED sub-node properties:
+- reg : number of LED line.
+ from 0 to 1 for the pca9550
+ from 0 to 7 for the pca9551
+ from 0 to 15 for the pca9552
+ from 0 to 3 for the pca9553
+- type: (optional) either
+ PCA9532_TYPE_NONE
+ PCA9532_TYPE_LED
+ PCA9532_TYPE_GPIO
+ see dt-bindings/leds/leds-pca955x.h (default to LED)
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Examples:
+
+pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO12", "GPIO13", "GPIO14", "GPIO15";
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@0 {
+ label = "red:power";
+ linux,default-trigger = "default-on";
+ reg = <0>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@1 {
+ label = "green:power";
+ reg = <1>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@2 {
+ label = "pca9552:yellow";
+ reg = <2>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@3 {
+ label = "pca9552:white";
+ reg = <3>;
+ type = <PCA955X_TYPE_LED>;
+ };
+};
diff --git a/dts/Bindings/media/i2c/adv748x.txt b/dts/Bindings/media/i2c/adv748x.txt
new file mode 100644
index 0000000..21ffb5e
--- /dev/null
+++ b/dts/Bindings/media/i2c/adv748x.txt
@@ -0,0 +1,95 @@
+* Analog Devices ADV748X video decoder with HDMI receiver
+
+The ADV7481 and ADV7482 are multi format video decoders with an integrated
+HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
+from three input sources HDMI, analog and TTL.
+
+Required Properties:
+
+ - compatible: Must contain one of the following
+ - "adi,adv7481" for the ADV7481
+ - "adi,adv7482" for the ADV7482
+
+ - reg: I2C slave address
+
+Optional Properties:
+
+ - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
+ "intrq3". All interrupts are optional. The "intrq3" interrupt
+ is only available on the adv7481
+ - interrupts: Specify the interrupt lines for the ADV748x
+
+The device node must contain one 'port' child node per device input and output
+port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
+are numbered as follows.
+
+ Name Type Port
+ ---------------------------------------
+ AIN0 sink 0
+ AIN1 sink 1
+ AIN2 sink 2
+ AIN3 sink 3
+ AIN4 sink 4
+ AIN5 sink 5
+ AIN6 sink 6
+ AIN7 sink 7
+ HDMI sink 8
+ TTL sink 9
+ TXA source 10
+ TXB source 11
+
+The digital output port nodes must contain at least one endpoint.
+
+Ports are optional if they are not connected to anything at the hardware level.
+
+Example:
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio6>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
+ <31 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_in>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+
+ port@11 {
+ reg = <11>;
+
+ adv7482_txb: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&csi20_in>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/i2c/dongwoon,dw9714.txt b/dts/Bindings/media/i2c/dongwoon,dw9714.txt
new file mode 100644
index 0000000..b88dcdd
--- /dev/null
+++ b/dts/Bindings/media/i2c/dongwoon,dw9714.txt
@@ -0,0 +1,9 @@
+Dongwoon Anatech DW9714 camera voice coil lens driver
+
+DW9174 is a 10-bit DAC with current sink capability. It is intended
+for driving voice coil lenses in camera modules.
+
+Mandatory properties:
+
+- compatible: "dongwoon,dw9714"
+- reg: I²C slave address
diff --git a/dts/Bindings/media/meson-ao-cec.txt b/dts/Bindings/media/meson-ao-cec.txt
new file mode 100644
index 0000000..8671bdb
--- /dev/null
+++ b/dts/Bindings/media/meson-ao-cec.txt
@@ -0,0 +1,28 @@
+* Amlogic Meson AO-CEC driver
+
+The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
+to handle communication between HDMI connected devices over the CEC bus.
+
+Required properties:
+ - compatible : value should be following
+ "amlogic,meson-gx-ao-cec"
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : AO-CEC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to AO-CEC clock.
+ - clock-names : from common clock binding: must contain "core",
+ corresponding to entry in the clocks property.
+ - hdmi-phandle: phandle to the HDMI controller
+
+Example:
+
+cec_AO: cec@100 {
+ compatible = "amlogic,meson-gx-ao-cec";
+ reg = <0x0 0x00100 0x0 0x14>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+ hdmi-phandle = <&hdmi_tx>;
+};
diff --git a/dts/Bindings/media/mtk-cir.txt b/dts/Bindings/media/mtk-cir.txt
index 2be2005..5e18087 100644
--- a/dts/Bindings/media/mtk-cir.txt
+++ b/dts/Bindings/media/mtk-cir.txt
@@ -2,10 +2,14 @@ Device-Tree bindings for Mediatek consumer IR controller
found in Mediatek SoC family
Required properties:
-- compatible : "mediatek,mt7623-cir"
+- compatible : Should be
+ "mediatek,mt7623-cir": for MT7623 SoC
+ "mediatek,mt7622-cir": for MT7622 SoC
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
-- clock-names : should contain "clk" entries;
+- clock-names : should contain
+ - "clk" entries: for MT7623 SoC
+ - "clk", "bus" entries: for MT7622 SoC
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.
diff --git a/dts/Bindings/media/pxa-camera.txt b/dts/Bindings/media/pxa-camera.txt
index 11f5b5d..bc03ec0 100644
--- a/dts/Bindings/media/pxa-camera.txt
+++ b/dts/Bindings/media/pxa-camera.txt
@@ -24,7 +24,6 @@ Example:
clock-frequency = <50000000>;
clock-output-names = "qci_mclk";
- status = "okay";
port {
#address-cells = <1>;
diff --git a/dts/Bindings/media/qcom,camss.txt b/dts/Bindings/media/qcom,camss.txt
new file mode 100644
index 0000000..cadeceb
--- /dev/null
+++ b/dts/Bindings/media/qcom,camss.txt
@@ -0,0 +1,197 @@
+Qualcomm Camera Subsystem
+
+* Properties
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain:
+ - "qcom,msm8916-camss"
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register ranges as listed in the reg-names property.
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy0_clk_mux"
+ - "csiphy1"
+ - "csiphy1_clk_mux"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "csi_clk_mux"
+ - "vfe0"
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Interrupts as listed in the interrupt-names property.
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy1"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "vfe0"
+- power-domains:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pairs to the
+ power domain which is responsible for collapsing
+ and restoring power to the peripheral.
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and clock specifier pairs as listed
+ in clock-names property.
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "camss_top_ahb"
+ - "ispif_ahb"
+ - "csiphy0_timer"
+ - "csiphy1_timer"
+ - "csi0_ahb"
+ - "csi0"
+ - "csi0_phy"
+ - "csi0_pix"
+ - "csi0_rdi"
+ - "csi1_ahb"
+ - "csi1"
+ - "csi1_phy"
+ - "csi1_pix"
+ - "csi1_rdi"
+ - "camss_ahb"
+ - "camss_vfe_vfe"
+ - "camss_csi_vfe"
+ - "iface"
+ - "bus"
+- vdda-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: A phandle to voltage supply for CSI2.
+- iommus:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and IOMMU specifier pairs.
+
+* Nodes
+
+- ports:
+ Usage: required
+ Definition: As described in video-interfaces.txt in same directory.
+ Properties:
+ - reg:
+ Usage: required
+ Value type: <u32>
+ Definition: Selects CSI2 PHY interface - PHY0 or PHY1.
+ Endpoint node properties:
+ - clock-lanes:
+ Usage: required
+ Value type: <u32>
+ Definition: The physical clock lane index. The value
+ must always be <1> as the physical clock
+ lane is lane 1.
+ - data-lanes:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported.
+
+* An Example
+
+ camss: camss@1b00000 {
+ compatible = "qcom,msm8916-camss";
+ reg = <0x1b0ac00 0x200>,
+ <0x1b00030 0x4>,
+ <0x1b0b000 0x200>,
+ <0x1b00038 0x4>,
+ <0x1b08000 0x100>,
+ <0x1b08400 0x100>,
+ <0x1b0a000 0x500>,
+ <0x1b00020 0x10>,
+ <0x1b10000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 51 0>,
+ <GIC_SPI 52 0>,
+ <GIC_SPI 55 0>,
+ <GIC_SPI 57 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0";
+ power-domains = <&gcc VFE_GDSC>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
+ clock-names = "camss_top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "camss_ahb",
+ "camss_vfe_vfe",
+ "camss_csi_vfe",
+ "iface",
+ "bus";
+ vdda-supply = <&pm8916_l2>;
+ iommus = <&apps_iommu 3>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5645_ep>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/renesas,drif.txt b/dts/Bindings/media/renesas,drif.txt
index 39516b9..0d8974a 100644
--- a/dts/Bindings/media/renesas,drif.txt
+++ b/dts/Bindings/media/renesas,drif.txt
@@ -40,6 +40,7 @@ To summarize,
Required properties of an internal channel:
-------------------------------------------
- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
+ "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/media/s5p-cec.txt b/dts/Bindings/media/s5p-cec.txt
index 1b1a10b..6f3756d 100644
--- a/dts/Bindings/media/s5p-cec.txt
+++ b/dts/Bindings/media/s5p-cec.txt
@@ -33,5 +33,4 @@ hdmicec: cec@100B0000 {
hdmi-phandle = <&hdmi>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
- status = "okay";
};
diff --git a/dts/Bindings/media/samsung-fimc.txt b/dts/Bindings/media/samsung-fimc.txt
index 922d6f8..e4e15d8 100644
--- a/dts/Bindings/media/samsung-fimc.txt
+++ b/dts/Bindings/media/samsung-fimc.txt
@@ -166,7 +166,6 @@ Example:
clock-output-names = "cam_a_clkout", "cam_b_clkout";
pinctrl-names = "default";
pinctrl-0 = <&cam_port_a_clk_active>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
@@ -189,7 +188,6 @@ Example:
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
interrupts = <0 85 0>;
- status = "okay";
};
csis_0: csis@11880000 {
diff --git a/dts/Bindings/media/stih407-c8sectpfe.txt b/dts/Bindings/media/stih407-c8sectpfe.txt
index cc51b1f..6af3fc2 100644
--- a/dts/Bindings/media/stih407-c8sectpfe.txt
+++ b/dts/Bindings/media/stih407-c8sectpfe.txt
@@ -52,7 +52,6 @@ Example:
c8sectpfe@08a20000 {
compatible = "st,stih407-c8sectpfe";
- status = "okay";
reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
reg-names = "stfe", "stfe-ram";
interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
diff --git a/dts/Bindings/media/ti,da850-vpif.txt b/dts/Bindings/media/ti,da850-vpif.txt
index df7182a..e47c7cc 100644
--- a/dts/Bindings/media/ti,da850-vpif.txt
+++ b/dts/Bindings/media/ti,da850-vpif.txt
@@ -59,7 +59,6 @@ I2C-connected TVP5147 decoder:
tvp5147@5d {
compatible = "ti,tvp5147";
reg = <0x5d>;
- status = "okay";
port {
composite_in: endpoint {
diff --git a/dts/Bindings/media/video-interfaces.txt b/dts/Bindings/media/video-interfaces.txt
index 9cd2a36..852041a 100644
--- a/dts/Bindings/media/video-interfaces.txt
+++ b/dts/Bindings/media/video-interfaces.txt
@@ -76,6 +76,11 @@ Optional endpoint properties
mode horizontal and vertical synchronization signals are provided to the
slave device (data source) by the master device (data sink). In the master
mode the data source device is also the source of the synchronization signals.
+- bus-type: data bus type. Possible values are:
+ 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
+ 1 - MIPI CSI-2 C-PHY
+ 2 - MIPI CSI1
+ 3 - CCP2
- bus-width: number of data lines actively used, valid for the parallel busses.
- data-shift: on the parallel data busses, if bus-width is used to specify the
number of data lines, data-shift can be used to specify which data lines are
@@ -112,7 +117,8 @@ Optional endpoint properties
should be the combined length of data-lanes and clock-lanes properties.
If the lane-polarities property is omitted, the value must be interpreted
as 0 (normal). This property is valid for serial busses only.
-
+- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used
+ with CCP2, for instance.
Example
-------
diff --git a/dts/Bindings/media/zx-irdec.txt b/dts/Bindings/media/zx-irdec.txt
new file mode 100644
index 0000000..295b9fa
--- /dev/null
+++ b/dts/Bindings/media/zx-irdec.txt
@@ -0,0 +1,14 @@
+IR Decoder (IRDEC) on ZTE ZX family SoCs
+
+Required properties:
+ - compatible: Should be "zte,zx296718-irdec".
+ - reg: Physical base address and length of IRDEC registers.
+ - interrupts: Interrupt number of IRDEC.
+
+Exmaples:
+
+ irdec: ir-decoder@111000 {
+ compatible = "zte,zx296718-irdec";
+ reg = <0x111000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
index 21277a5..ddf46b8 100644
--- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
@@ -15,6 +15,9 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
+Required property for mt2701:
+- mediatek,larb-id :the hardware id of this larb.
+
Example:
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
@@ -25,3 +28,15 @@ Example:
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
+
+Example for mt2701:
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
diff --git a/dts/Bindings/memory-controllers/mvebu-devbus.txt b/dts/Bindings/memory-controllers/mvebu-devbus.txt
index 1ee3bc0..8b9388c 100644
--- a/dts/Bindings/memory-controllers/mvebu-devbus.txt
+++ b/dts/Bindings/memory-controllers/mvebu-devbus.txt
@@ -130,7 +130,6 @@ The reg property implicitly specifies the chip select as this:
Example:
devbus-bootcs@d0010400 {
- status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/mfd/act8945a.txt b/dts/Bindings/mfd/act8945a.txt
index 462819a..e6f168d 100644
--- a/dts/Bindings/mfd/act8945a.txt
+++ b/dts/Bindings/mfd/act8945a.txt
@@ -12,7 +12,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
active-semi,vsel-high;
@@ -79,6 +78,5 @@ Example:
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
- status = "okay";
};
};
diff --git a/dts/Bindings/mfd/atmel-hlcdc.txt b/dts/Bindings/mfd/atmel-hlcdc.txt
index eec40be..3f643ef 100644
--- a/dts/Bindings/mfd/atmel-hlcdc.txt
+++ b/dts/Bindings/mfd/atmel-hlcdc.txt
@@ -25,7 +25,6 @@ Example:
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/dts/Bindings/mfd/atmel-smc.txt b/dts/Bindings/mfd/atmel-smc.txt
index 26eeed3..1103ce2 100644
--- a/dts/Bindings/mfd/atmel-smc.txt
+++ b/dts/Bindings/mfd/atmel-smc.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: Should be one of the following
"atmel,at91sam9260-smc", "syscon"
"atmel,sama5d3-smc", "syscon"
+ "atmel,sama5d2-smc", "syscon"
- reg: Contains offset/length value of the SMC memory
region.
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index aca09af..9455503 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -7,7 +7,14 @@ axp209 (X-Powers)
axp221 (X-Powers)
axp223 (X-Powers)
axp803 (X-Powers)
+axp806 (X-Powers)
axp809 (X-Powers)
+axp813 (X-Powers)
+
+The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything
+other than the packaging. Pins are routed separately. As such they should
+be treated as separate entities. The other half is an AC100 RTC/codec
+combo chip. Please see ./ac100.txt for its bindings.
Required properties:
- compatible: should be one of:
@@ -19,6 +26,7 @@ Required properties:
* "x-powers,axp803"
* "x-powers,axp806"
* "x-powers,axp809"
+ * "x-powers,axp813"
- reg: The I2C slave address or RSB hardware address for the AXP chip
- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
@@ -28,12 +36,14 @@ Required properties:
Optional properties:
- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz
AXP152/20X: range: 750-1875, Default: 1.5 MHz
- AXP22X/80X: range: 1800-4050, Default: 3 MHz
+ AXP22X/8XX: range: 1800-4050, Default: 3 MHz
-- x-powers,drive-vbus-en: axp221 / axp223 only boolean, set this when the
- N_VBUSEN pin is used as an output pin to control an external
- regulator to drive the OTG VBus, rather then as an input pin
- which signals whether the board is driving OTG VBus or not.
+- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is
+ used as an output pin to control an external
+ regulator to drive the OTG VBus, rather then
+ as an input pin which signals whether the
+ board is driving OTG VBus or not.
+ (axp221 / axp223 / axp813 only)
- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
wired for master mode. The default is slave mode.
@@ -171,6 +181,36 @@ LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
SW : On/Off Switch : swin-supply
+AXP813 regulators, type, and corresponding input supply names:
+
+Regulator Type Supply Name Notes
+--------- ---- ----------- -----
+DCDC1 : DC-DC buck : vin1-supply
+DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
+DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
+DCDC4 : DC-DC buck : vin4-supply
+DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
+DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
+DCDC7 : DC-DC buck : vin7-supply
+ALDO1 : LDO : aldoin-supply : shared supply
+ALDO2 : LDO : aldoin-supply : shared supply
+ALDO3 : LDO : aldoin-supply : shared supply
+DLDO1 : LDO : dldoin-supply : shared supply
+DLDO2 : LDO : dldoin-supply : shared supply
+DLDO3 : LDO : dldoin-supply : shared supply
+DLDO4 : LDO : dldoin-supply : shared supply
+ELDO1 : LDO : eldoin-supply : shared supply
+ELDO2 : LDO : eldoin-supply : shared supply
+ELDO3 : LDO : eldoin-supply : shared supply
+FLDO1 : LDO : fldoin-supply : shared supply
+FLDO2 : LDO : fldoin-supply : shared supply
+FLDO3 : LDO : fldoin-supply : shared supply
+LDO_IO0 : LDO : ips-supply : GPIO 0
+LDO_IO1 : LDO : ips-supply : GPIO 1
+RTC_LDO : LDO : ips-supply : always on
+SW : On/Off Switch : swin-supply
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
+
Example:
axp209: pmic@34 {
diff --git a/dts/Bindings/mfd/bd9571mwv.txt b/dts/Bindings/mfd/bd9571mwv.txt
new file mode 100644
index 0000000..9ab216a
--- /dev/null
+++ b/dts/Bindings/mfd/bd9571mwv.txt
@@ -0,0 +1,49 @@
+* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings
+
+Required properties:
+ - compatible : Should be "rohm,bd9571mwv".
+ - reg : I2C slave address.
+ - interrupt-parent : Phandle to the parent interrupt controller.
+ - interrupts : The interrupt line the device is connected to.
+ - interrupt-controller : Marks the device node as an interrupt controller.
+ - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as trigger
+ masks from ../interrupt-controller/interrupts.txt.
+ - gpio-controller : Marks the device node as a GPIO Controller.
+ - #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../gpio/gpio.txt for more information.
+ - regulators: : List of child nodes that specify the regulator
+ initialization data. Child nodes must be named
+ after their hardware counterparts:
+ - vd09
+ - vd18
+ - vd25
+ - vd33
+ - dvfs
+ Each child node is defined using the standard
+ binding for regulators.
+
+Example:
+
+ pmic: pmic@30 {
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ regulators {
+ dvfs: dvfs {
+ regulator-name = "dvfs";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
diff --git a/dts/Bindings/mfd/da9052-i2c.txt b/dts/Bindings/mfd/da9052-i2c.txt
index 9554292..07c69c0 100644
--- a/dts/Bindings/mfd/da9052-i2c.txt
+++ b/dts/Bindings/mfd/da9052-i2c.txt
@@ -4,6 +4,14 @@ Required properties:
- compatible : Should be "dlg,da9052", "dlg,da9053-aa",
"dlg,da9053-ab", or "dlg,da9053-bb"
+Optional properties:
+- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen
+ input lines are used as general purpose analogue
+ input.
+- tsiref-supply: Phandle to the regulator, which provides the reference
+ voltage for the TSIREF pin. Must be provided when the
+ touchscreen pins are used for ADC purposes.
+
Sub-nodes:
- regulators : Contain the regulator nodes. The DA9052/53 regulators are
bound using their names as listed below:
@@ -29,7 +37,6 @@ Sub-nodes:
Examples:
i2c@63fc8000 { /* I2C1 */
- status = "okay";
pmic: dialog@48 {
compatible = "dlg,da9053-aa";
diff --git a/dts/Bindings/mfd/mc13xxx.txt b/dts/Bindings/mfd/mc13xxx.txt
index 8aba488..39ba414 100644
--- a/dts/Bindings/mfd/mc13xxx.txt
+++ b/dts/Bindings/mfd/mc13xxx.txt
@@ -116,7 +116,6 @@ ecspi@70010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */
<&gpio4 25 0>; /* GPIO4_25 */
- status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
diff --git a/dts/Bindings/mfd/mxs-lradc.txt b/dts/Bindings/mfd/mxs-lradc.txt
index 555fb11..755cbef 100644
--- a/dts/Bindings/mfd/mxs-lradc.txt
+++ b/dts/Bindings/mfd/mxs-lradc.txt
@@ -26,7 +26,6 @@ Example for i.MX23 SoC:
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
- status = "okay";
fsl,lradc-touchscreen-wires = <4>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
@@ -39,7 +38,6 @@ Example for i.MX28 SoC:
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;
- status = "okay";
fsl,lradc-touchscreen-wires = <5>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
diff --git a/dts/Bindings/mfd/retu.txt b/dts/Bindings/mfd/retu.txt
new file mode 100644
index 0000000..8762423
--- /dev/null
+++ b/dts/Bindings/mfd/retu.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Nokia Retu and Tahvo multi-function device
+
+Retu and Tahvo are a multi-function devices found on Nokia Internet
+Tablets (770, N800 and N810). The Retu chip provides watchdog timer
+and power button control functionalities while Tahvo chip provides
+USB transceiver functionality.
+
+Required properties:
+- compatible: "nokia,retu" or "nokia,tahvo"
+- reg: Specifies the CBUS slave address of the ASIC chip
+- interrupts: The interrupt line the device is connected to
+- interrupt-parent: The parent interrupt controller
+
+Example:
+
+cbus0 {
+ compatible = "i2c-cbus-gpio";
+ ...
+ retu: retu@1 {
+ compatible = "nokia,retu";
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x1>;
+ };
+};
diff --git a/dts/Bindings/mfd/rk808.txt b/dts/Bindings/mfd/rk808.txt
index 9636ae8..91b6522 100644
--- a/dts/Bindings/mfd/rk808.txt
+++ b/dts/Bindings/mfd/rk808.txt
@@ -1,11 +1,14 @@
RK8XX Power Management Integrated Circuit
The rk8xx family current members:
+rk805
rk808
rk818
Required properties:
-- compatible: "rockchip,rk808", "rockchip,rk818"
+- compatible: "rockchip,rk805"
+- compatible: "rockchip,rk808"
+- compatible: "rockchip,rk818"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
@@ -18,6 +21,14 @@ Optional properties:
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
+Optional RK805 properties:
+- vcc1-supply: The input supply for DCDC_REG1
+- vcc2-supply: The input supply for DCDC_REG2
+- vcc3-supply: The input supply for DCDC_REG3
+- vcc4-supply: The input supply for DCDC_REG4
+- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
+- vcc6-supply: The input supply for LDO_REG3
+
Optional RK808 properties:
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
@@ -56,6 +67,15 @@ by a child node of the 'regulators' node.
/* standard regulator bindings here */
};
+Following regulators of the RK805 PMIC regulators are supported. Note that
+the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
+number as described in RK805 datasheet.
+
+ - DCDC_REGn
+ - valid values for n are 1 to 4.
+ - LDO_REGn
+ - valid values for n are 1 to 3
+
Following regulators of the RK808 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
diff --git a/dts/Bindings/mfd/samsung,exynos5433-lpass.txt b/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
index df66401..d759da6 100644
--- a/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/dts/Bindings/mfd/samsung,exynos5433-lpass.txt
@@ -57,7 +57,6 @@ audio-subsystem {
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
- status = "disabled";
};
serial_3: serial@11460000 {
@@ -69,6 +68,5 @@ audio-subsystem {
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart_aud_bus>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/mfd/stm32-lptimer.txt b/dts/Bindings/mfd/stm32-lptimer.txt
new file mode 100644
index 0000000..2a9ff29
--- /dev/null
+++ b/dts/Bindings/mfd/stm32-lptimer.txt
@@ -0,0 +1,48 @@
+STMicroelectronics STM32 Low-Power Timer
+
+The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
+functions:
+- PWM output (with programmable prescaler, configurable polarity)
+- Quadrature encoder, counter
+- Trigger source for STM32 ADC/DAC (LPTIM_OUT)
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer".
+- reg: Offset and length of the device's register set.
+- clocks: Phandle to the clock used by the LP Timer module.
+- clock-names: Must be "mux".
+- #address-cells: Should be '<1>'.
+- #size-cells: Should be '<0>'.
+
+Optional subnodes:
+- pwm: See ../pwm/pwm-stm32-lp.txt
+- counter: See ../iio/timer/stm32-lptimer-cnt.txt
+- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
+
+Example:
+
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x40002400 0x400>;
+ clocks = <&timer_clk>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lppwm1_pins>;
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/dts/Bindings/mfd/tps6105x.txt b/dts/Bindings/mfd/tps6105x.txt
new file mode 100644
index 0000000..93602c7
--- /dev/null
+++ b/dts/Bindings/mfd/tps6105x.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for TI TPS61050/61052 Boost Converters
+
+The TP61050/TPS61052 is a high-power "white LED driver". The
+device provides LED, GPIO and regulator functionalities.
+
+Required properties:
+- compatible: "ti,tps61050" or "ti,tps61052"
+- reg: Specifies the I2C slave address
+
+Example:
+
+i2c0 {
+ tps61052@33 {
+ compatible = "ti,tps61052";
+ reg = <0x33>;
+ };
+};
diff --git a/dts/Bindings/mfd/wm831x.txt b/dts/Bindings/mfd/wm831x.txt
index 9f8b743..5057094 100644
--- a/dts/Bindings/mfd/wm831x.txt
+++ b/dts/Bindings/mfd/wm831x.txt
@@ -31,6 +31,7 @@ Required properties:
../interrupt-controller/interrupts.txt
Optional sub-nodes:
+ - phys : Contains a phandle to the USB PHY.
- regulators : Contains sub-nodes for each of the regulators supplied by
the device. The regulators are bound using their names listed below:
diff --git a/dts/Bindings/mfd/zii,rave-sp.txt b/dts/Bindings/mfd/zii,rave-sp.txt
new file mode 100644
index 0000000..088eff9
--- /dev/null
+++ b/dts/Bindings/mfd/zii,rave-sp.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor
+
+RAVE Supervisory Processor communicates with SoC over UART. It is
+expected that its Device Tree node is specified as a child of a node
+corresponding to UART controller used for communication.
+
+Required parent device properties:
+
+ - compatible: Should be one of:
+ - "zii,rave-sp-niu"
+ - "zii,rave-sp-mezz"
+ - "zii,rave-sp-esb"
+ - "zii,rave-sp-rdu1"
+ - "zii,rave-sp-rdu2"
+
+ - current-speed: Should be set to baud rate SP device is using
+
+RAVE SP consists of the following sub-devices:
+
+Device Description
+------ -----------
+rave-sp-wdt : Watchdog
+rave-sp-nvmem : Interface to onborad EEPROM
+rave-sp-backlight : Display backlight
+rave-sp-hwmon : Interface to onboard hardware sensors
+rave-sp-leds : Interface to onboard LEDs
+rave-sp-input : Interface to onboard power button
+
+Example of usage:
+
+ rdu {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+ };
+
diff --git a/dts/Bindings/mips/lantiq/fpi-bus.txt b/dts/Bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 0000000..0a2df43
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,31 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200-fpi"
+- reg : The address and length of the XBAR
+ configuration register.
+ Address and length of the FPI bus itself.
+- lantiq,rcu : A phandle to the RCU syscon
+- lantiq,offset-endianness : Offset of the endianness configuration
+ register
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+ fpi@10000000 {
+ compatible = "lantiq,xrx200-fpi";
+ ranges = <0x0 0x10000000 0xf000000>;
+ reg = <0x1f400000 0x1000>,
+ <0x10000000 0xf000000>;
+ lantiq,rcu = <&rcu0>;
+ lantiq,offset-endianness = <0x4c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gptu@e100a00 {
+ ......
+ };
+ };
diff --git a/dts/Bindings/mips/lantiq/rcu-gphy.txt b/dts/Bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 0000000..a0c19bd
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,36 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200a1x-gphy"
+ "lantiq,xrx200a2x-gphy"
+ "lantiq,xrx300-gphy"
+ "lantiq,xrx330-gphy"
+- reg : Addrress of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
diff --git a/dts/Bindings/mips/lantiq/rcu.txt b/dts/Bindings/mips/lantiq/rcu.txt
new file mode 100644
index 0000000..a086f1e
--- /dev/null
+++ b/dts/Bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,89 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : The first and second values must be:
+ "lantiq,xrx200-rcu", "simple-mfd", "syscon"
+- reg : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+ rcu0: rcu@203000 {
+ compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
+ reg = <0x203000 0x100>;
+ ranges = <0x0 0x203000 0x100>;
+ big-endian;
+
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@68 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x68 0x4>;
+
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x10 4>, <0x14 4>;
+
+ #reset-cells = <2>;
+ };
+
+ reset1: reset-controller@48 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x48 4>, <0x24 4>;
+
+ #reset-cells = <2>;
+ };
+
+ usb_phy0: usb2-phy@18 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x18 4>, <0x38 4>;
+ status = "disabled";
+
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: usb2-phy@34 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x34 4>, <0x3C 4>;
+ status = "disabled";
+
+ resets = <&reset1 5 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ reboot@10 {
+ compatible = "syscon-reboot";
+ reg = <0x10 4>;
+
+ regmap = <&rcu0>;
+ offset = <0x10>;
+ mask = <0x40000000>;
+ };
+ };
diff --git a/dts/Bindings/mips/ni.txt b/dts/Bindings/mips/ni.txt
new file mode 100644
index 0000000..722bf2d
--- /dev/null
+++ b/dts/Bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+ - compatible: must be "ni,169445"
+
+CPU Nodes
+ - compatible: must be "mti,mips14KEc"
diff --git a/dts/Bindings/mips/ralink.txt b/dts/Bindings/mips/ralink.txt
index b35a8d0..a16e8d7 100644
--- a/dts/Bindings/mips/ralink.txt
+++ b/dts/Bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/dts/Bindings/misc/atmel-ssc.txt b/dts/Bindings/misc/atmel-ssc.txt
index f8629bb..f9fb412 100644
--- a/dts/Bindings/misc/atmel-ssc.txt
+++ b/dts/Bindings/misc/atmel-ssc.txt
@@ -47,5 +47,4 @@ ssc0: ssc@f0010000 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
index 49df630..60481bf 100644
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ b/dts/Bindings/mmc/arasan,sdhci.txt
@@ -74,5 +74,4 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/davinci_mmc.txt b/dts/Bindings/mmc/davinci_mmc.txt
index e5a0140..516fb01 100644
--- a/dts/Bindings/mmc/davinci_mmc.txt
+++ b/dts/Bindings/mmc/davinci_mmc.txt
@@ -24,7 +24,6 @@ mmc0: mmc@1c40000 {
compatible = "ti,da830-mmc",
reg = <0x40000 0x1000>;
interrupts = <16>;
- status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
dmas = <&edma 16
diff --git a/dts/Bindings/mmc/fsl-imx-mmc.txt b/dts/Bindings/mmc/fsl-imx-mmc.txt
index db44235..184ccff 100644
--- a/dts/Bindings/mmc/fsl-imx-mmc.txt
+++ b/dts/Bindings/mmc/fsl-imx-mmc.txt
@@ -20,5 +20,4 @@ sdhci1: sdhci@10014000 {
dma-names = "rx-tx";
bus-width = <4>;
cd-gpios = <&gpio3 29>;
- status = "okay";
};
diff --git a/dts/Bindings/mmc/mmc-card.txt b/dts/Bindings/mmc/mmc-card.txt
index a70fcd6..8d2d717 100644
--- a/dts/Bindings/mmc/mmc-card.txt
+++ b/dts/Bindings/mmc/mmc-card.txt
@@ -21,7 +21,6 @@ Example:
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
- status = "okay";
mmccard: mmccard@0 {
reg = <0>;
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index c7f4a0e..b32ade6 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -153,7 +153,6 @@ mmc3: mmc@01c12000 {
bus-width = <4>;
non-removable;
mmc-pwrseq = <&sdhci0_pwrseq>
- status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
diff --git a/dts/Bindings/mmc/orion-sdio.txt b/dts/Bindings/mmc/orion-sdio.txt
index 84f0ebd..10f0818 100644
--- a/dts/Bindings/mmc/orion-sdio.txt
+++ b/dts/Bindings/mmc/orion-sdio.txt
@@ -13,5 +13,4 @@ Example:
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
- status = "disabled";
};
diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt
index c32dc5a..5ff1e12 100644
--- a/dts/Bindings/mmc/renesas,mmcif.txt
+++ b/dts/Bindings/mmc/renesas,mmcif.txt
@@ -11,6 +11,8 @@ Required properties:
- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+ - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
+ - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
- "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
@@ -21,7 +23,7 @@ Required properties:
- interrupts: Some SoCs have only 1 shared interrupt, while others have either
2 or 3 individual interrupts (error, int, card detect). Below is the number
of interrupts for each SoC:
- 1: r8a73a4, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
+ 1: r8a73a4, r8a7743, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
2: r8a7740, sh73a0
3: r7s72100
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index 49ed3ad..c655878 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x
- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
diff --git a/dts/Bindings/mmc/sdhci-st.txt b/dts/Bindings/mmc/sdhci-st.txt
index 230fd69..e356455 100644
--- a/dts/Bindings/mmc/sdhci-st.txt
+++ b/dts/Bindings/mmc/sdhci-st.txt
@@ -63,7 +63,6 @@ Example:
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
- status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
@@ -77,7 +76,6 @@ mmc0: sdhci@fe81e000 {
mmc1: sdhci@09080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
@@ -94,7 +92,6 @@ mmc1: sdhci@09080000 {
mmc0: sdhci@09060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
diff --git a/dts/Bindings/mmc/sunxi-mmc.txt b/dts/Bindings/mmc/sunxi-mmc.txt
index 7d53a79..63b57e2 100644
--- a/dts/Bindings/mmc/sunxi-mmc.txt
+++ b/dts/Bindings/mmc/sunxi-mmc.txt
@@ -12,6 +12,7 @@ Required properties:
* "allwinner,sun4i-a10-mmc"
* "allwinner,sun5i-a13-mmc"
* "allwinner,sun7i-a20-mmc"
+ * "allwinner,sun8i-a83t-emmc"
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
diff --git a/dts/Bindings/mmc/ti-omap-hsmmc.txt b/dts/Bindings/mmc/ti-omap-hsmmc.txt
index 0e026c1..3a4ac40 100644
--- a/dts/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/dts/Bindings/mmc/ti-omap-hsmmc.txt
@@ -1,33 +1,55 @@
-* TI Highspeed MMC host controller for OMAP
+* TI Highspeed MMC host controller for OMAP and 66AK2G family.
-The Highspeed MMC Host Controller on TI OMAP family
+The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap_hsmmc driver.
Required properties:
+--------------------
- compatible:
Should be "ti,omap2-hsmmc", for OMAP2 controllers
Should be "ti,omap3-hsmmc", for OMAP3 controllers
Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
Should be "ti,omap4-hsmmc", for OMAP4 controllers
Should be "ti,am33xx-hsmmc", for AM335x controllers
-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
+
+SoC specific required properties:
+---------------------------------
+The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the MMC device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks: Must contain an entry for each entry in clock-names. Should
+ be defined as per the he appropriate clock bindings consumer
+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+- clock-names: Shall be "fck" for the functional clock,
+ and "mmchsdb_fck" for the debounce clock.
+
Optional properties:
-ti,dual-volt: boolean, supports dual voltage cards
-<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
-ti,non-removable: non-removable slot (like eMMC)
-ti,needs-special-reset: Requires a special softreset sequence
-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-dmas: List of DMA specifiers with the controller specific format
-as described in the generic DMA client binding. A tx and rx
-specifier is required.
-dma-names: List of DMA request names. These strings correspond
-1:1 with the DMA specifiers listed in dmas. The string naming is
-to be "rx" and "tx" for RX and TX DMA requests, respectively.
+--------------------
+- ti,dual-volt: boolean, supports dual voltage cards
+- <supply-name>-supply: phandle to the regulator device tree node
+ "supply-name" examples are "vmmc",
+ "vmmc_aux"(deprecated)/"vqmmc" etc
+- ti,non-removable: non-removable slot (like eMMC)
+- ti,needs-special-reset: Requires a special softreset sequence
+- ti,needs-special-hs-handling: HSMMC IP needs special setting
+ for handling High Speed
+- dmas: List of DMA specifiers with the controller specific
+ format as described in the generic DMA client
+ binding. A tx and rx specifier is required.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the DMA specifiers listed in dmas.
+ The string naming is to be "rx" and "tx" for
+ RX and TX DMA requests, respectively.
Examples:
diff --git a/dts/Bindings/mmc/tmio_mmc.txt b/dts/Bindings/mmc/tmio_mmc.txt
index 4fd8b7a..54ef642 100644
--- a/dts/Bindings/mmc/tmio_mmc.txt
+++ b/dts/Bindings/mmc/tmio_mmc.txt
@@ -15,6 +15,8 @@ Required properties:
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+ "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
+ "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
@@ -33,10 +35,8 @@ Required properties:
If 2 clocks are specified by the hardware, you must name them as
"core" and "cd". If the controller only has 1 clock, naming is not
required.
- Below is the number clocks for each supported SoC:
- 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
- R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
- 2: R7S72100
+ Devices which have more than 1 clock are listed below:
+ 2: R7S72100
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
diff --git a/dts/Bindings/mmc/zx-dw-mshc.txt b/dts/Bindings/mmc/zx-dw-mshc.txt
index 906819a..0f59bd5 100644
--- a/dts/Bindings/mmc/zx-dw-mshc.txt
+++ b/dts/Bindings/mmc/zx-dw-mshc.txt
@@ -28,5 +28,4 @@ Example:
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
- status = "disabled";
};
diff --git a/dts/Bindings/mtd/atmel-quadspi.txt b/dts/Bindings/mtd/atmel-quadspi.txt
index 4898070..b93c1e2 100644
--- a/dts/Bindings/mtd/atmel-quadspi.txt
+++ b/dts/Bindings/mtd/atmel-quadspi.txt
@@ -24,7 +24,6 @@ spi@f0020000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
- status = "okay";
m25p80@0 {
...
diff --git a/dts/Bindings/mtd/mtk-quadspi.txt b/dts/Bindings/mtd/mtk-quadspi.txt
index 5ded66a..840f940 100644
--- a/dts/Bindings/mtd/mtk-quadspi.txt
+++ b/dts/Bindings/mtd/mtk-quadspi.txt
@@ -37,7 +37,6 @@ nor_flash: spi@1100d000 {
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt
index 70dd511..73d336b 100644
--- a/dts/Bindings/mtd/qcom_nandc.txt
+++ b/dts/Bindings/mtd/qcom_nandc.txt
@@ -1,11 +1,20 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ipq806x-nand"
+- compatible: must be one of the following:
+ * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
+ SoC and it uses ADM DMA
+ * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
+ IPQ4019 SoC and it uses BAM DMA
+ * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
+ IPQ8074 SoC and it uses BAM DMA
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -16,6 +25,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -26,7 +41,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
follows.
Required properties:
-- compatible: should contain "qcom,nandcs"
- reg: a single integer representing the chip-select
number (e.g., 0, 1, 2, etc.)
- #address-cells: see partition.txt
@@ -43,8 +57,8 @@ partition.txt for more detail.
Example:
-nand@1ac00000 {
- compatible = "qcom,ebi2-nandc";
+nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
@@ -59,8 +73,7 @@ nand@1ac00000 {
#address-cells = <1>;
#size-cells = <0>;
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
@@ -84,3 +97,43 @@ nand@1ac00000 {
};
};
};
+
+nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/mtd/st-fsm.txt b/dts/Bindings/mtd/st-fsm.txt
index c248939..54cef9e 100644
--- a/dts/Bindings/mtd/st-fsm.txt
+++ b/dts/Bindings/mtd/st-fsm.txt
@@ -21,6 +21,5 @@ Example:
st,syscfg = <&syscfg_rear>;
st,boot-device-reg = <0x958>;
st,boot-device-spi = <0x1a>;
- status = "okay";
};
diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt
index f322f56..a37c67b 100644
--- a/dts/Bindings/mtd/sunxi-nand.txt
+++ b/dts/Bindings/mtd/sunxi-nand.txt
@@ -41,7 +41,6 @@ nfc: nand@01c03000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
- status = "okay";
nand@0 {
reg = <0>;
diff --git a/dts/Bindings/net/anarion-gmac.txt b/dts/Bindings/net/anarion-gmac.txt
new file mode 100644
index 0000000..fe67896
--- /dev/null
+++ b/dts/Bindings/net/anarion-gmac.txt
@@ -0,0 +1,25 @@
+* Adaptrum Anarion ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+ - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac"
+ - phy-mode: Should be "rgmii". Other modes are not currently supported.
+
+
+Examples:
+
+ gmac1: ethernet@f2014000 {
+ compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+ reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+ interrupt-parent = <&core_intc>;
+ interrupts = <21>;
+ interrupt-names = "macirq";
+
+ clocks = <&core_clk>;
+ clock-names = "stmmaceth";
+
+ phy-mode = "rgmii";
+ };
diff --git a/dts/Bindings/net/brcm,amac.txt b/dts/Bindings/net/brcm,amac.txt
index ad16c1f..0bfad65 100644
--- a/dts/Bindings/net/brcm,amac.txt
+++ b/dts/Bindings/net/brcm,amac.txt
@@ -27,5 +27,4 @@ amac0: ethernet@18022000 {
<0x18110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/dts/Bindings/net/broadcom-bluetooth.txt b/dts/Bindings/net/broadcom-bluetooth.txt
new file mode 100644
index 0000000..4194ff7
--- /dev/null
+++ b/dts/Bindings/net/broadcom-bluetooth.txt
@@ -0,0 +1,35 @@
+Broadcom Bluetooth Chips
+---------------------
+
+This documents the binding structure and common properties for serial
+attached Broadcom devices.
+
+Serial attached Broadcom devices shall be a child node of the host UART
+device the slave device is attached to.
+
+Required properties:
+
+ - compatible: should contain one of the following:
+ * "brcm,bcm43438-bt"
+
+Optional properties:
+
+ - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt
+ - shutdown-gpios: GPIO specifier, used to enable the BT module
+ - device-wakeup-gpios: GPIO specifier, used to wakeup the controller
+ - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor
+ - clocks: clock specifier if external clock provided to the controller
+ - clock-names: should be "extclk"
+
+
+Example:
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <921600>;
+ };
+};
diff --git a/dts/Bindings/net/btusb.txt b/dts/Bindings/net/btusb.txt
index 01fa2d4..9c5e663 100644
--- a/dts/Bindings/net/btusb.txt
+++ b/dts/Bindings/net/btusb.txt
@@ -29,7 +29,6 @@ Example:
Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:
&usb_host1_ehci {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/can/c_can.txt b/dts/Bindings/net/can/c_can.txt
index 5a1d8b0..2d50425 100644
--- a/dts/Bindings/net/can/c_can.txt
+++ b/dts/Bindings/net/can/c_can.txt
@@ -11,9 +11,20 @@ Required properties:
- interrupts : property with a value describing the interrupt
number
-Optional properties:
+The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only:
- ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
instance number
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+- power-domains : Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DCAN device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks : CAN functional clock phandle. This property is as per the
+ binding,
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+Optional properties:
- syscon-raminit : Handle to system control region that contains the
RAMINIT register, register offset to the RAMINIT
register and the CAN instance number (0 offset).
diff --git a/dts/Bindings/net/can/m_can.txt b/dts/Bindings/net/can/m_can.txt
index 9e33177..7813833 100644
--- a/dts/Bindings/net/can/m_can.txt
+++ b/dts/Bindings/net/can/m_can.txt
@@ -56,7 +56,6 @@ m_can1: can@020e8000 {
<&clks IMX6SX_CLK_CANFD>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
- status = "disabled";
};
Board dts:
diff --git a/dts/Bindings/net/dsa/ksz.txt b/dts/Bindings/net/dsa/ksz.txt
index 0ab8b39..fd23904 100644
--- a/dts/Bindings/net/dsa/ksz.txt
+++ b/dts/Bindings/net/dsa/ksz.txt
@@ -24,7 +24,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 0>;
id = <1>;
- status = "okay";
ksz9477: ksz9477@0 {
compatible = "microchip,ksz9477";
@@ -34,7 +33,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
spi-cpha;
spi-cpol;
- status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/dsa/lan9303.txt b/dts/Bindings/net/dsa/lan9303.txt
index 04f2965..4448d06 100644
--- a/dts/Bindings/net/dsa/lan9303.txt
+++ b/dts/Bindings/net/dsa/lan9303.txt
@@ -27,7 +27,6 @@ Example:
I2C managed mode:
master: masterdevice@X {
- status = "okay";
fixed-link { /* RMII fixed link to LAN9303 */
speed = <100>;
@@ -38,7 +37,6 @@ I2C managed mode:
switch: switch@a {
compatible = "smsc,lan9303-i2c";
reg = <0xa>;
- status = "okay";
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <200>;
@@ -67,7 +65,6 @@ I2C managed mode:
MDIO managed mode:
master: masterdevice@X {
- status = "okay";
phy-handle = <&switch>;
mdio {
diff --git a/dts/Bindings/net/ethernet.txt b/dts/Bindings/net/ethernet.txt
index 7da86f2..2974e63 100644
--- a/dts/Bindings/net/ethernet.txt
+++ b/dts/Bindings/net/ethernet.txt
@@ -1,5 +1,9 @@
The following properties are common to the Ethernet controllers:
+NOTE: All 'phy*' properties documented below are Ethernet specific. For the
+generic PHY 'phys' property, see
+Documentation/devicetree/bindings/phy/phy-bindings.txt.
+
- local-mac-address: array of 6 bytes, specifies the MAC address that was
assigned to the network device;
- mac-address: array of 6 bytes, specifies the MAC address that was last used by
diff --git a/dts/Bindings/net/ftgmac100.txt b/dts/Bindings/net/ftgmac100.txt
index c1ce168..72e7aaf 100644
--- a/dts/Bindings/net/ftgmac100.txt
+++ b/dts/Bindings/net/ftgmac100.txt
@@ -30,6 +30,5 @@ Example:
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
- status = "okay";
use-ncsi;
};
diff --git a/dts/Bindings/net/marvell-armada-370-neta.txt b/dts/Bindings/net/marvell-armada-370-neta.txt
index ae4234c..bedcfd5 100644
--- a/dts/Bindings/net/marvell-armada-370-neta.txt
+++ b/dts/Bindings/net/marvell-armada-370-neta.txt
@@ -41,7 +41,6 @@ ethernet@70000 {
interrupts = <8>;
clocks = <&gate_clk 4>;
tx-csum-limit = <9800>
- status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
buffer-manager = <&bm>;
diff --git a/dts/Bindings/net/marvell-bt-8xxx.txt b/dts/Bindings/net/marvell-bt-8xxx.txt
index 9be1059..3d27c68 100644
--- a/dts/Bindings/net/marvell-bt-8xxx.txt
+++ b/dts/Bindings/net/marvell-bt-8xxx.txt
@@ -44,7 +44,6 @@ Example for SDIO device follows (calibration data is also available in
below example).
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
@@ -70,7 +69,6 @@ below example).
Example for USB device:
&usb_host1_ohci {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/marvell-neta-bm.txt b/dts/Bindings/net/marvell-neta-bm.txt
index c1b1d7c..07b3105 100644
--- a/dts/Bindings/net/marvell-neta-bm.txt
+++ b/dts/Bindings/net/marvell-neta-bm.txt
@@ -31,7 +31,6 @@ bm: bm@c8000 {
reg = <0xc8000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
- status = "okay";
pool2,capacity = <4096>;
pool1,pkt-size = <512>;
};
@@ -45,5 +44,4 @@ bm_bppi: bm-bppi {
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
- status = "okay";
};
diff --git a/dts/Bindings/net/marvell-pp2.txt b/dts/Bindings/net/marvell-pp2.txt
index 6b4956b..7e2dad0 100644
--- a/dts/Bindings/net/marvell-pp2.txt
+++ b/dts/Bindings/net/marvell-pp2.txt
@@ -41,6 +41,11 @@ Optional properties (port):
- marvell,loopback: port is loopback mode
- phy: a phandle to a phy node defining the PHY address (as the reg
property, a single integer).
+- interrupt-names: if more than a single interrupt for rx is given, must
+ be the name associated to the interrupts listed. Valid
+ names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",
+ "rx-shared", "link".
+- marvell,system-controller: a phandle to the system controller.
Example for marvell,armada-375-pp2:
@@ -52,12 +57,10 @@ ethernet@f0000 {
<0xc5000 0x100>;
clocks = <&gateclk 3>, <&gateclk 19>;
clock-names = "pp_clk", "gop_clk";
- status = "okay";
eth0: eth0@c4000 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
- status = "okay";
phy = <&phy0>;
phy-mode = "gmii";
};
@@ -65,7 +68,6 @@ ethernet@f0000 {
eth1: eth1@c5000 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
- status = "okay";
phy = <&phy3>;
phy-mode = "gmii";
};
@@ -80,19 +82,37 @@ cpm_ethernet: ethernet@0 {
clock-names = "pp_clk", "gop_clk", "gp_clk";
eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <0>;
gop-port-id = <0>;
};
eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <1>;
gop-port-id = <2>;
};
eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared";
port-id = <2>;
gop-port-id = <3>;
};
diff --git a/dts/Bindings/net/mediatek-net.txt b/dts/Bindings/net/mediatek-net.txt
index c7194e8..214eaa9 100644
--- a/dts/Bindings/net/mediatek-net.txt
+++ b/dts/Bindings/net/mediatek-net.txt
@@ -7,24 +7,32 @@ have dual GMAC each represented by a child node..
* Ethernet controller node
Required properties:
-- compatible: Should be "mediatek,mt2701-eth"
+- compatible: Should be
+ "mediatek,mt2701-eth": for MT2701 SoC
+ "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
+ "mediatek,mt7622-eth": for MT7622 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
- "ethif", "esw", "gp2", "gp1"
+ "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
+ "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
- power-domains: phandle to the power domain that the ethernet is part of
-- resets: Should contain a phandle to the ethsys reset signal
-- reset-names: Should contain the reset signal name "eth"
+- resets: Should contain phandles to the ethsys reset signals
+- reset-names: Should contain the names of reset signal listed in the resets
+ property
+ These are "fe", "gmac" and "ppe"
- mediatek,ethsys: phandle to the syscon node that handles the port setup
+- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
+ which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
and driver current
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
-
* Ethernet MAC node
Required properties:
diff --git a/dts/Bindings/net/meson-dwmac.txt b/dts/Bindings/net/meson-dwmac.txt
index 0703ad3..354dd98 100644
--- a/dts/Bindings/net/meson-dwmac.txt
+++ b/dts/Bindings/net/meson-dwmac.txt
@@ -66,5 +66,4 @@ Example for GXBB:
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
- status = "disabled";
};
diff --git a/dts/Bindings/net/micrel-ksz90x1.txt b/dts/Bindings/net/micrel-ksz90x1.txt
index c35b5b4..42a2483 100644
--- a/dts/Bindings/net/micrel-ksz90x1.txt
+++ b/dts/Bindings/net/micrel-ksz90x1.txt
@@ -69,7 +69,6 @@ Examples:
};
};
ethernet@70000 {
- status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
diff --git a/dts/Bindings/net/microchip,enc28j60.txt b/dts/Bindings/net/microchip,enc28j60.txt
index 1dc3bc7..44dff53 100644
--- a/dts/Bindings/net/microchip,enc28j60.txt
+++ b/dts/Bindings/net/microchip,enc28j60.txt
@@ -33,7 +33,6 @@ Example (for NXP i.MX28 with pin control stuff for GPIO irq):
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;
- status = "okay";
enc28j60: ethernet@0 {
compatible = "microchip,enc28j60";
diff --git a/dts/Bindings/net/nfc/nfcmrvl.txt b/dts/Bindings/net/nfc/nfcmrvl.txt
index 76df917..c9b3525 100644
--- a/dts/Bindings/net/nfc/nfcmrvl.txt
+++ b/dts/Bindings/net/nfc/nfcmrvl.txt
@@ -25,7 +25,6 @@ Optional I2C-based chip specific properties:
Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
&uart5 {
- status = "okay";
nfcmrvluart: nfcmrvluart@5 {
compatible = "marvell,nfc-uart";
@@ -41,7 +40,6 @@ Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1):
&i2c1 {
- status = "okay";
clock-frequency = <400000>;
nfcmrvli2c0: i2c@1 {
diff --git a/dts/Bindings/net/nfc/nxp-nci.txt b/dts/Bindings/net/nfc/nxp-nci.txt
index 5b6cd9b..9248673 100644
--- a/dts/Bindings/net/nfc/nxp-nci.txt
+++ b/dts/Bindings/net/nfc/nxp-nci.txt
@@ -17,7 +17,6 @@ Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2):
&i2c2 {
- status = "okay";
npc100: npc100@29 {
diff --git a/dts/Bindings/net/nfc/pn533-i2c.txt b/dts/Bindings/net/nfc/pn533-i2c.txt
index 1aea822..122460e 100644
--- a/dts/Bindings/net/nfc/pn533-i2c.txt
+++ b/dts/Bindings/net/nfc/pn533-i2c.txt
@@ -15,7 +15,6 @@ Example (for ARM-based BeagleBone with PN532 on I2C2):
&i2c2 {
- status = "okay";
pn532: pn532@24 {
diff --git a/dts/Bindings/net/nfc/pn544.txt b/dts/Bindings/net/nfc/pn544.txt
index dab69f3..538a86f 100644
--- a/dts/Bindings/net/nfc/pn544.txt
+++ b/dts/Bindings/net/nfc/pn544.txt
@@ -17,7 +17,6 @@ Example (for ARM-based BeagleBone with PN544 on I2C2):
&i2c2 {
- status = "okay";
pn544: pn544@28 {
diff --git a/dts/Bindings/net/nfc/s3fwrn5.txt b/dts/Bindings/net/nfc/s3fwrn5.txt
index fb1e75f..ed5b3ea 100644
--- a/dts/Bindings/net/nfc/s3fwrn5.txt
+++ b/dts/Bindings/net/nfc/s3fwrn5.txt
@@ -12,7 +12,6 @@ Required properties:
Example:
&hsi2c_4 {
- status = "okay";
s3fwrn5@27 {
compatible = "samsung,s3fwrn5-i2c";
diff --git a/dts/Bindings/net/nfc/st-nci-i2c.txt b/dts/Bindings/net/nfc/st-nci-i2c.txt
index 263732e..b46d473 100644
--- a/dts/Bindings/net/nfc/st-nci-i2c.txt
+++ b/dts/Bindings/net/nfc/st-nci-i2c.txt
@@ -20,7 +20,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
&i2c2 {
- status = "okay";
st21nfcb: st21nfcb@8 {
diff --git a/dts/Bindings/net/nfc/st-nci-spi.txt b/dts/Bindings/net/nfc/st-nci-spi.txt
index 711ca85..54ce8e7 100644
--- a/dts/Bindings/net/nfc/st-nci-spi.txt
+++ b/dts/Bindings/net/nfc/st-nci-spi.txt
@@ -19,7 +19,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
&mcspi4 {
- status = "okay";
st21nfcb: st21nfcb@0 {
diff --git a/dts/Bindings/net/nfc/st21nfca.txt b/dts/Bindings/net/nfc/st21nfca.txt
index 7bb2e21..5ee9440 100644
--- a/dts/Bindings/net/nfc/st21nfca.txt
+++ b/dts/Bindings/net/nfc/st21nfca.txt
@@ -20,7 +20,6 @@ Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2):
&i2c2 {
- status = "okay";
st21nfca: st21nfca@1 {
diff --git a/dts/Bindings/net/nfc/st95hf.txt b/dts/Bindings/net/nfc/st95hf.txt
index ea3178b..08a202e 100644
--- a/dts/Bindings/net/nfc/st95hf.txt
+++ b/dts/Bindings/net/nfc/st95hf.txt
@@ -35,12 +35,10 @@ spi@9840000 {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&pio0 4>;
- status = "okay";
st95hf@0{
reg = <0>;
compatible = "st,st95hf";
- status = "okay";
spi-max-frequency = <1000000>;
enable-gpio = <&pio4 0>;
interrupt-parent = <&pio0>;
diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt
index 60c833d..5ca9362 100644
--- a/dts/Bindings/net/nfc/trf7970a.txt
+++ b/dts/Bindings/net/nfc/trf7970a.txt
@@ -23,7 +23,6 @@ Optional SoC Specific Properties:
Example (for ARM-based BeagleBone with TRF7970A on SPI1):
&spi1 {
- status = "okay";
nfc@0 {
compatible = "ti,trf7970a";
@@ -41,6 +40,5 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
irq-status-read-quirk;
en2-rf-quirk;
clock-frequency = <27120000>;
- status = "okay";
};
};
diff --git a/dts/Bindings/net/oxnas-dwmac.txt b/dts/Bindings/net/oxnas-dwmac.txt
index df0534e..d7117a2 100644
--- a/dts/Bindings/net/oxnas-dwmac.txt
+++ b/dts/Bindings/net/oxnas-dwmac.txt
@@ -35,5 +35,4 @@ etha: ethernet@40400000 {
/* Regmap for sys registers */
oxsemi,sys-ctrl = <&sys>;
- status = "disabled";
};
diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt
index b558576..77d0b2a 100644
--- a/dts/Bindings/net/phy.txt
+++ b/dts/Bindings/net/phy.txt
@@ -2,11 +2,7 @@ PHY nodes
Required properties:
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
+ - interrupts : interrupt specifier for the sole interrupt.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- reg : The ID number for the phy, usually a small integer
@@ -52,11 +48,16 @@ Optional Properties:
Mark the corresponding energy efficient ethernet mode as broken and
request the ethernet to stop advertising it.
+- phy-is-integrated: If set, indicates that the PHY is integrated into the same
+ physical package as the Ethernet MAC. If needed, muxers should be configured
+ to ensure the integrated PHY is used. The absence of this property indicates
+ the muxers should be configured so that the external PHY is used.
+
Example:
ethernet-phy@0 {
compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <40000>;
- interrupts = <35 1>;
+ interrupt-parent = <&PIC>;
+ interrupts = <35 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
};
diff --git a/dts/Bindings/net/qca,qca7000.txt b/dts/Bindings/net/qca,qca7000.txt
index 6d9efb2..3987846 100644
--- a/dts/Bindings/net/qca,qca7000.txt
+++ b/dts/Bindings/net/qca,qca7000.txt
@@ -41,7 +41,6 @@ ssp2: spi@80014000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
qca7000: ethernet@0 {
compatible = "qca,qca7000";
@@ -78,7 +77,6 @@ auart0: serial@8006a000 {
reg = <0x8006a000 0x2000>;
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
qca7000: ethernet {
compatible = "qca,qca7000";
diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt
index b519503..1672353 100644
--- a/dts/Bindings/net/renesas,ravb.txt
+++ b/dts/Bindings/net/renesas,ravb.txt
@@ -4,19 +4,25 @@ This file provides information on what the device node for the Ethernet AVB
interface contains.
Required properties:
-- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.
- "renesas,etheravb-r8a7791" if the device is a part of R8A7791 SoC.
- "renesas,etheravb-r8a7792" if the device is a part of R8A7792 SoC.
- "renesas,etheravb-r8a7793" if the device is a part of R8A7793 SoC.
- "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.
- "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.
- "renesas,etheravb-r8a7796" if the device is a part of R8A7796 SoC.
- "renesas,etheravb-rcar-gen2" for generic R-Car Gen 2 compatible interface.
- "renesas,etheravb-rcar-gen3" for generic R-Car Gen 3 compatible interface.
+- compatible: Must contain one or more of the following:
+ - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
+ - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
+ - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
+ - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
+ - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
+ - "renesas,etheravb-r8a7793" for the R8A7793 SoC.
+ - "renesas,etheravb-r8a7794" for the R8A7794 SoC.
+ - "renesas,etheravb-rcar-gen2" as a fallback for the above
+ R-Car Gen2 and RZ/G1 devices.
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
+ - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
+ - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+ - "renesas,etheravb-rcar-gen3" as a fallback for the above
+ R-Car Gen3 devices.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.
- reg: offset and length of (1) the register block and (2) the stream buffer.
- interrupts: A list of interrupt-specifiers, one for each entry in
diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt
index 8f42755..6af8eed 100644
--- a/dts/Bindings/net/rockchip-dwmac.txt
+++ b/dts/Bindings/net/rockchip-dwmac.txt
@@ -10,6 +10,7 @@ Required properties:
"rockchip,rk3366-gmac": found on RK3366 SoCs
"rockchip,rk3368-gmac": found on RK3368 SoCs
"rockchip,rk3399-gmac": found on RK3399 SoCs
+ "rockchip,rv1108-gmac": found on RV1108 SoCs
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
@@ -70,5 +71,4 @@ gmac: ethernet@ff290000 {
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
};
diff --git a/dts/Bindings/net/sff,sfp.txt b/dts/Bindings/net/sff,sfp.txt
new file mode 100644
index 0000000..60e970c
--- /dev/null
+++ b/dts/Bindings/net/sff,sfp.txt
@@ -0,0 +1,76 @@
+Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
+Transceiver
+
+Required properties:
+
+- compatible : must be "sff,sfp"
+
+Optional Properties:
+
+- i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
+ interface
+
+- mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
+ module presence input gpio signal, active (module absent) high
+
+- los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
+ Indication input gpio signal, active (signal lost) high
+
+- tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
+ Fault input gpio signal, active (fault condition) high
+
+- tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
+ output gpio signal, active (Tx disable) high
+
+- rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
+ Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
+
+- rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
+ Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
+ high Tx rate
+
+Example #1: Direct serdes to SFP connection
+
+sfp_eth3: sfp-eth3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_1g_i2c>;
+ los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
+ tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
+};
+
+&cps_emac3 {
+ phy-names = "comphy";
+ phys = <&cps_comphy5 0>;
+ sfp = <&sfp_eth3>;
+};
+
+Example #2: Serdes to PHY to SFP connection
+
+sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp0_i2c>;
+ los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_sfpp0_pins>;
+ tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
+};
+
+p0_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>;
+ reg = <0>;
+ interrupt = <&cpm_gpio2 18 IRQ_TYPE_EDGE_FALLING>;
+ sfp = <&sfp_eth0>;
+};
+
+&cpm_eth0 {
+ phy = <&p0_phy>;
+ phy-mode = "10gbase-kr";
+};
diff --git a/dts/Bindings/net/smsc-lan87xx.txt b/dts/Bindings/net/smsc-lan87xx.txt
index 974edd5..8b7c719 100644
--- a/dts/Bindings/net/smsc-lan87xx.txt
+++ b/dts/Bindings/net/smsc-lan87xx.txt
@@ -15,7 +15,6 @@ smsc phy with disabled energy detect mode on an am335x based board.
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethernetphy0: ethernet-phy@0 {
reg = <0>;
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt
index 2e68a3c..b30d04b 100644
--- a/dts/Bindings/net/socfpga-dwmac.txt
+++ b/dts/Bindings/net/socfpga-dwmac.txt
@@ -40,7 +40,6 @@ gmii_to_sgmii_converter: phy@0x100000240 {
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- status = "disabled";
reg = <0xff700000 0x2000>;
interrupts = <0 115 4>;
interrupt-names = "macirq";
diff --git a/dts/Bindings/net/sti-dwmac.txt b/dts/Bindings/net/sti-dwmac.txt
index d05c1e1..062c517 100644
--- a/dts/Bindings/net/sti-dwmac.txt
+++ b/dts/Bindings/net/sti-dwmac.txt
@@ -34,7 +34,6 @@ Example:
ethernet0: dwmac@9630000 {
device_type = "network";
- status = "disabled";
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
reg = <0x9630000 0x8000>;
reg-names = "stmmaceth";
diff --git a/dts/Bindings/net/stm32-dwmac.txt b/dts/Bindings/net/stm32-dwmac.txt
index c35afb7..489dbcb 100644
--- a/dts/Bindings/net/stm32-dwmac.txt
+++ b/dts/Bindings/net/stm32-dwmac.txt
@@ -18,7 +18,6 @@ Example:
ethernet@40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- status = "disabled";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
interrupts = <0 61 0>, <0 62 0>;
diff --git a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
index 590f622..b2bd470 100644
--- a/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
+++ b/dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
@@ -29,7 +29,6 @@ mmc3: mmc@01c12000 {
vmmc-supply = <&reg_vmmc3>;
bus-width = <4>;
non-removable;
- status = "okay";
brcmf: wifi@1 {
reg = <1>;
diff --git a/dts/Bindings/net/wireless/esp,esp8089.txt b/dts/Bindings/net/wireless/esp,esp8089.txt
index 19331bb..6830c47 100644
--- a/dts/Bindings/net/wireless/esp,esp8089.txt
+++ b/dts/Bindings/net/wireless/esp,esp8089.txt
@@ -21,7 +21,6 @@ Example:
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
- status = "okay";
esp8089: sdio_wifi@1 {
compatible = "esp,esp8089";
diff --git a/dts/Bindings/net/wireless/marvell-8xxx.txt b/dts/Bindings/net/wireless/marvell-8xxx.txt
index 0854451..59de864 100644
--- a/dts/Bindings/net/wireless/marvell-8xxx.txt
+++ b/dts/Bindings/net/wireless/marvell-8xxx.txt
@@ -48,7 +48,6 @@ IRQ pin 38 is used as system wakeup source interrupt. wakeup pin 3 is configured
so that firmware can wakeup host using this device side pin.
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
diff --git a/dts/Bindings/net/wireless/ti,wlcore.txt b/dts/Bindings/net/wireless/ti,wlcore.txt
index 7b2cbb1..f42f6b0 100644
--- a/dts/Bindings/net/wireless/ti,wlcore.txt
+++ b/dts/Bindings/net/wireless/ti,wlcore.txt
@@ -31,7 +31,6 @@ clock, new bindings (for parsing the clock nodes) have to be added.
Example:
&mmc3 {
- status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
diff --git a/dts/Bindings/net/xilinx_axienet.txt b/dts/Bindings/net/xilinx_axienet.txt
new file mode 100644
index 0000000..38f9ec0
--- /dev/null
+++ b/dts/Bindings/net/xilinx_axienet.txt
@@ -0,0 +1,55 @@
+XILINX AXI ETHERNET Device Tree Bindings
+--------------------------------------------------------
+
+Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
+provides connectivity to an external ethernet PHY supporting different
+interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+segments of memory for buffering TX and RX, as well as the capability of
+offloading TX/RX checksum calculation off the processor.
+
+Management configuration is done through the AXI interface, while payload is
+sent and received through means of an AXI DMA controller. This driver
+includes the DMA driver code, so this driver is incompatible with AXI DMA
+driver.
+
+For more details about mdio please refer phy.txt file in the same directory.
+
+Required properties:
+- compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
+ "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
+- reg : Address and length of the IO space.
+- interrupts : Should be a list of two interrupt, TX and RX.
+- phy-handle : Should point to the external phy device.
+ See ethernet.txt file in the same directory.
+- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
+
+Optional properties:
+- phy-mode : See ethernet.txt
+- xlnx,phy-type : Deprecated, do not use, but still accepted in preference
+ to phy-mode.
+- xlnx,txcsum : 0 or empty for disabling TX checksum offload,
+ 1 to enable partial TX checksum offload,
+ 2 to enable full TX checksum offload
+- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
+
+Example:
+ axi_ethernet_eth: ethernet@40c00000 {
+ compatible = "xlnx,axi-ethernet-1.00.a";
+ device_type = "network";
+ interrupt-parent = <&microblaze_0_axi_intc>;
+ interrupts = <2 0>;
+ phy-mode = "mii";
+ reg = <0x40c00000 0x40000>;
+ xlnx,rxcsum = <0x2>;
+ xlnx,rxmem = <0x800>;
+ xlnx,txcsum = <0x2>;
+ phy-handle = <&phy0>;
+ axi_ethernetlite_0_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@0 {
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/nvmem/mtk-efuse.txt b/dts/Bindings/nvmem/mtk-efuse.txt
index 74cf529..0668c45 100644
--- a/dts/Bindings/nvmem/mtk-efuse.txt
+++ b/dts/Bindings/nvmem/mtk-efuse.txt
@@ -3,7 +3,10 @@
This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
Required properties:
-- compatible: should be "mediatek,mt8173-efuse" or "mediatek,efuse"
+- compatible: should be
+ "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
+ "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
+ "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
- reg: Should contain registers location and length
= Data cells =
diff --git a/dts/Bindings/nvmem/mxs-ocotp.txt b/dts/Bindings/nvmem/mxs-ocotp.txt
index daebce9..372c72f 100644
--- a/dts/Bindings/nvmem/mxs-ocotp.txt
+++ b/dts/Bindings/nvmem/mxs-ocotp.txt
@@ -21,5 +21,4 @@ Example for i.MX28:
#size-cells = <1>;
reg = <0x8002c000 0x2000>;
clocks = <&clks 25>;
- status = "okay";
};
diff --git a/dts/Bindings/opp/opp.txt b/dts/Bindings/opp/opp.txt
index e36d261..9d733af 100644
--- a/dts/Bindings/opp/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -464,7 +464,6 @@ Example 5: opp-supported-hw
opp_table {
compatible = "operating-points-v2";
- status = "okay";
opp-shared;
opp-600000000 {
diff --git a/dts/Bindings/pci/83xx-512x-pci.txt b/dts/Bindings/pci/83xx-512x-pci.txt
index 35a4653..b9165b7 100644
--- a/dts/Bindings/pci/83xx-512x-pci.txt
+++ b/dts/Bindings/pci/83xx-512x-pci.txt
@@ -1,11 +1,11 @@
* Freescale 83xx and 512x PCI bridges
-Freescale 83xx and 512x SOCs include the same pci bridge core.
+Freescale 83xx and 512x SOCs include the same PCI bridge core.
83xx/512x specific notes:
- reg: should contain two address length tuples
- The first is for the internal pci bridge registers
- The second is for the pci config space access registers
+ The first is for the internal PCI bridge registers
+ The second is for the PCI config space access registers
Example (MPC8313ERDB)
pci0: pci@e0008500 {
diff --git a/dts/Bindings/pci/aardvark-pci.txt b/dts/Bindings/pci/aardvark-pci.txt
index bbcd9f4..310ef71 100644
--- a/dts/Bindings/pci/aardvark-pci.txt
+++ b/dts/Bindings/pci/aardvark-pci.txt
@@ -33,7 +33,6 @@ Example:
pcie0: pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
device_type = "pci";
- status = "disabled";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/dts/Bindings/pci/altera-pcie.txt b/dts/Bindings/pci/altera-pcie.txt
index 2951a6a..4958801 100644
--- a/dts/Bindings/pci/altera-pcie.txt
+++ b/dts/Bindings/pci/altera-pcie.txt
@@ -7,21 +7,21 @@ Required properties:
"Txs": TX slave port region
"Cra": Control register access region
- interrupt-parent: interrupt source phandle.
-- interrupts: specifies the interrupt source of the parent interrupt controller.
- The format of the interrupt specifier depends on the parent interrupt
- controller.
+- interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends
+ on the parent interrupt controller.
- device_type: must be "pci"
- #address-cells: set to <3>
-- #size-cells: set to <2>
+- #size-cells: set to <2>
- #interrupt-cells: set to <1>
-- ranges: describes the translation of addresses for root ports and standard
- PCI regions.
+- ranges: describes the translation of addresses for root ports and
+ standard PCI regions.
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCIe interface to interrupt numbers.
Optional properties:
-- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
- controller.
+- msi-parent: Link to the hardware entity that serves as the MSI controller
+ for this PCIe controller.
- bus-range: PCI bus numbers covered
Example
@@ -45,5 +45,5 @@ Example
<0 0 0 3 &pcie_0 3>,
<0 0 0 4 &pcie_0 4>;
ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
- 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
};
diff --git a/dts/Bindings/pci/axis,artpec6-pcie.txt b/dts/Bindings/pci/axis,artpec6-pcie.txt
index 5ecaea1..4e4aee4 100644
--- a/dts/Bindings/pci/axis,artpec6-pcie.txt
+++ b/dts/Bindings/pci/axis,artpec6-pcie.txt
@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
- reg: base addresses and lengths of the PCIe controller (DBI),
- the phy controller, and configuration address space.
+ the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
- "dbi"
- "phy"
diff --git a/dts/Bindings/pci/designware-pcie.txt b/dts/Bindings/pci/designware-pcie.txt
index b2480dd..1da7ade 100644
--- a/dts/Bindings/pci/designware-pcie.txt
+++ b/dts/Bindings/pci/designware-pcie.txt
@@ -1,4 +1,4 @@
-* Synopsys Designware PCIe interface
+* Synopsys DesignWare PCIe interface
Required properties:
- compatible: should contain "snps,dw-pcie" to identify the core.
@@ -17,29 +17,27 @@ RC mode:
properties to define the mapping of the PCIe interface to interrupt
numbers.
EP mode:
-- num-ib-windows: number of inbound address translation
- windows
-- num-ob-windows: number of outbound address translation
- windows
+- num-ib-windows: number of inbound address translation windows
+- num-ob-windows: number of outbound address translation windows
Optional properties:
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
-- reset-gpio: gpio pin number of power good signal
+- reset-gpio: GPIO pin number of power good signal
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
RC mode:
-- num-viewport: number of view ports configured in
- hardware. If a platform does not specify it, the driver assumes 2.
-- bus-range: PCI bus numbers covered (it is recommended
- for new devicetrees to specify this property, to keep backwards
- compatibility a range of 0x00-0xff is assumed if not present)
+- num-viewport: number of view ports configured in hardware. If a platform
+ does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
+ to specify this property, to keep backwards compatibility a range of
+ 0x00-0xff is assumed if not present)
+
EP mode:
-- max-functions: maximum number of functions that can be
- configured
+- max-functions: maximum number of functions that can be configured
Example configuration:
diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.txt b/dts/Bindings/pci/fsl,imx6q-pcie.txt
index cf92d3b..7b1e48b 100644
--- a/dts/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/dts/Bindings/pci/fsl,imx6q-pcie.txt
@@ -1,6 +1,6 @@
* Freescale i.MX6 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt
index a339dbb..bdb7ab3 100644
--- a/dts/Bindings/pci/hisilicon-pcie.txt
+++ b/dts/Bindings/pci/hisilicon-pcie.txt
@@ -1,7 +1,7 @@
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
-HiSilicon PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver and inherits
+HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
@@ -40,7 +40,6 @@ Hip05 Example (note that Hip06 is the same except compatible):
0x0 0 0 2 &mbigen_pcie 2 11
0x0 0 0 3 &mbigen_pcie 3 12
0x0 0 0 4 &mbigen_pcie 4 13>;
- status = "ok";
};
HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
@@ -83,5 +82,4 @@ Example:
0x0 0 0 2 &mbigen_pcie0 650 4
0x0 0 0 3 &mbigen_pcie0 650 4
0x0 0 0 4 &mbigen_pcie0 650 4>;
- status = "ok";
};
diff --git a/dts/Bindings/pci/kirin-pcie.txt b/dts/Bindings/pci/kirin-pcie.txt
index 68ffa0f..6e217c6 100644
--- a/dts/Bindings/pci/kirin-pcie.txt
+++ b/dts/Bindings/pci/kirin-pcie.txt
@@ -1,8 +1,8 @@
HiSilicon Kirin SoCs PCIe host DT description
-Kirin PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver
-and inherits common properties defined in
+Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
Additional properties are described here:
@@ -16,7 +16,7 @@ Required properties
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
-- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
diff --git a/dts/Bindings/pci/layerscape-pci.txt b/dts/Bindings/pci/layerscape-pci.txt
index ee1c72d..c0484da 100644
--- a/dts/Bindings/pci/layerscape-pci.txt
+++ b/dts/Bindings/pci/layerscape-pci.txt
@@ -15,8 +15,10 @@ Required properties:
- compatible: should contain the platform identifier such as:
"fsl,ls1021a-pcie", "snps,dw-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+ "fsl,ls2088a-pcie"
+ "fsl,ls1088a-pcie"
"fsl,ls1046a-pcie"
-- reg: base addresses and lengths of the PCIe controller
+- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
diff --git a/dts/Bindings/pci/mediatek,mt7623-pcie.txt b/dts/Bindings/pci/mediatek,mt7623-pcie.txt
deleted file mode 100644
index fe80dda..0000000
--- a/dts/Bindings/pci/mediatek,mt7623-pcie.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
-
-PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
-ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
-
-Required properties:
-- compatible: Should contain "mediatek,mt7623-pcie".
-- device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
-- #address-cells: Address representation for root ports (must be 3)
-- #size-cells: Size representation for root ports (must be 2)
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - free_ck :for reference clock of PCIe subsys
- - sys_ck0 :for clock of Port0
- - sys_ck1 :for clock of Port1
- - sys_ck2 :for clock of Port2
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - pcie-rst0 :port0 reset
- - pcie-rst1 :port1 reset
- - pcie-rst2 :port2 reset
-- phys: List of PHY specifiers (used by generic PHY framework).
-- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
- number of PHYs as specified in *phys* property.
-- power-domains: A phandle and power domain specifier pair to the power domain
- which is responsible for collapsing and restoring power to the peripheral.
-- bus-range: Range of bus numbers associated with this controller.
-- ranges: Ranges for the PCI memory and I/O regions.
-
-In addition, the device tree node must have sub-nodes describing each
-PCIe port interface, having the following mandatory properties:
-
-Required properties:
-- device_type: Must be "pci"
-- reg: Only the first four bytes are used to refer to the correct bus number
- and device number.
-- #address-cells: Must be 3
-- #size-cells: Must be 2
-- #interrupt-cells: Must be 1
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- ranges: Sub-ranges distributed from the PCIe controller node. An empty
- property is sufficient.
-- num-lanes: Number of lanes to use for this port.
-
-Examples:
-
- hifsys: syscon@1a000000 {
- compatible = "mediatek,mt7623-hifsys",
- "mediatek,mt2701-hifsys",
- "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pcie: pcie-controller@1a140000 {
- compatible = "mediatek,mt7623-pcie";
- device_type = "pci";
- reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
- <0 0x1a142000 0 0x1000>, /* Port0 registers */
- <0 0x1a143000 0 0x1000>, /* Port1 registers */
- <0 0x1a144000 0 0x1000>; /* Port2 registers */
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xf800 0 0 0>;
- interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
- <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
- <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
- <&hifsys CLK_HIFSYS_PCIE0>,
- <&hifsys CLK_HIFSYS_PCIE1>,
- <&hifsys CLK_HIFSYS_PCIE2>;
- clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
- resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
- <&hifsys MT2701_HIFSYS_PCIE1_RST>,
- <&hifsys MT2701_HIFSYS_PCIE2_RST>;
- reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
- phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
- phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
- bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
- 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
-
- pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
-
- pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
-
- pcie@2,0 {
- device_type = "pci";
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
- ranges;
- num-lanes = <1>;
- };
- };
diff --git a/dts/Bindings/pci/mediatek-pcie.txt b/dts/Bindings/pci/mediatek-pcie.txt
new file mode 100644
index 0000000..3a6ce55
--- /dev/null
+++ b/dts/Bindings/pci/mediatek-pcie.txt
@@ -0,0 +1,284 @@
+MediaTek Gen2 PCIe controller
+
+Required properties:
+- compatible: Should contain one of the following strings:
+ "mediatek,mt2701-pcie"
+ "mediatek,mt2712-pcie"
+ "mediatek,mt7622-pcie"
+ "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource lookup.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names:
+ Mandatory entries:
+ - sys_ckN :transaction layer and data link layer clock
+ Required entries for MT2701/MT7623:
+ - free_ck :for reference clock of PCIe subsys
+ Required entries for MT2712/MT7622:
+ - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+ Required entries for MT7622:
+ - axi_ckN :application layer MMIO channel operating clock
+ - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+ - obff_ckN :OBFF functional block operating clock
+ - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+ where N starting from 0 to one less than the number of root ports.
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+ which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+Required properties for MT7623/MT2701:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+ number of root ports.
+
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+ entry for each PCIe port
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+ and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+ property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples for MT7623:
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie-controller@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+ <&pcie2_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
+
+ pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+
+ pcie@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ };
+ };
+
+Examples for MT2712:
+ pcie: pcie@11700000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+ reg = <0 0x11700000 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+ reg-names = "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+ <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE0>,
+ <&pericfg CLK_PERI_PCIE1>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+Examples for MT7622:
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a143000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+ <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/pci/mvebu-pci.txt b/dts/Bindings/pci/mvebu-pci.txt
index 2de6f65..6173af6 100644
--- a/dts/Bindings/pci/mvebu-pci.txt
+++ b/dts/Bindings/pci/mvebu-pci.txt
@@ -77,7 +77,7 @@ and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
multiple lanes. If this property is not found, we assume that the
value is 0.
-- reset-gpios: optional gpio to PERST#
+- reset-gpios: optional GPIO to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion, if not
specified will default to 100ms, as required by the PCIe specification.
@@ -85,7 +85,6 @@ Example:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
- status = "disabled";
device_type = "pci";
#address-cells = <3>;
@@ -147,7 +146,6 @@ pcie-controller {
/* wait 20ms for device settle after reset deassertion */
reset-delay-us = <20000>;
clocks = <&gateclk 5>;
- status = "disabled";
};
pcie@2,0 {
@@ -164,7 +162,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
- status = "disabled";
};
pcie@3,0 {
@@ -181,7 +178,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
- status = "disabled";
};
pcie@4,0 {
@@ -198,7 +194,6 @@ pcie-controller {
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
- status = "disabled";
};
pcie@5,0 {
@@ -215,7 +210,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
- status = "disabled";
};
pcie@6,0 {
@@ -232,7 +226,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
- status = "disabled";
};
pcie@7,0 {
@@ -249,7 +242,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
- status = "disabled";
};
pcie@8,0 {
@@ -266,7 +258,6 @@ pcie-controller {
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
- status = "disabled";
};
pcie@9,0 {
@@ -283,10 +274,9 @@ pcie-controller {
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
- status = "disabled";
};
- pcie@10,0 {
+ pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
@@ -300,6 +290,5 @@ pcie-controller {
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
- status = "disabled";
};
};
diff --git a/dts/Bindings/pci/pci-armada8k.txt b/dts/Bindings/pci/pci-armada8k.txt
index 598533a..c1e4c3d 100644
--- a/dts/Bindings/pci/pci-armada8k.txt
+++ b/dts/Bindings/pci/pci-armada8k.txt
@@ -1,6 +1,6 @@
* Marvell Armada 7K/8K PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
@@ -34,5 +34,4 @@ Example:
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
- status = "disabled";
};
diff --git a/dts/Bindings/pci/pci-keystone.txt b/dts/Bindings/pci/pci-keystone.txt
index d08a4d5..7e05487 100644
--- a/dts/Bindings/pci/pci-keystone.txt
+++ b/dts/Bindings/pci/pci-keystone.txt
@@ -1,12 +1,12 @@
TI Keystone PCIe interface
-Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
-It shares common functions with PCIe Designware core driver and inherit
-common properties defined in
+Keystone PCI host Controller is based on the Synopsys DesignWare PCI
+hardware version 3.65. It shares common functions with the PCIe DesignWare
+core driver and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
-for the details of Designware DT bindings. Additional properties are
+for the details of DesignWare DT bindings. Additional properties are
described here as well as properties that are not applicable.
Required Properties:-
@@ -52,13 +52,12 @@ pcie_intc: Interrupt controller device node for Legacy IRQ chip
};
Optional properties:-
- phys: phandle to Generic Keystone SerDes phy for PCI
- phy-names: name of the Generic Keystine SerDes phy for PCI
+ phys: phandle to generic Keystone SerDes PHY for PCI
+ phy-names: name of the generic Keystone SerDes PHY for PCI
- If boot loader already does PCI link establishment, then phys and
phy-names shouldn't be present.
interrupts: platform interrupt for error interrupts.
-Designware DT Properties not applicable for Keystone PCI
+DesignWare DT Properties not applicable for Keystone PCI
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
-
diff --git a/dts/Bindings/pci/pci-rcar-gen2.txt b/dts/Bindings/pci/pci-rcar-gen2.txt
index 07a7509..3d03863 100644
--- a/dts/Bindings/pci/pci-rcar-gen2.txt
+++ b/dts/Bindings/pci/pci-rcar-gen2.txt
@@ -6,11 +6,14 @@ AHB. There is one bridge instance per USB port connected to the internal
OHCI and EHCI controllers.
Required properties:
-- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
+- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
+ "renesas,pci-r8a7745" for the R8A7745 SoC;
+ "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC;
"renesas,pci-r8a7793" for the R8A7793 SoC;
"renesas,pci-r8a7794" for the R8A7794 SoC;
- "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+ "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
+ RZ/G1 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/dts/Bindings/pci/pci.txt b/dts/Bindings/pci/pci.txt
index 50f9e2c..c77981c 100644
--- a/dts/Bindings/pci/pci.txt
+++ b/dts/Bindings/pci/pci.txt
@@ -1,12 +1,12 @@
PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994
-http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
+http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping
-http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
+http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties:
diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt
index 9d418b7..3c9d321 100644
--- a/dts/Bindings/pci/qcom,pcie.txt
+++ b/dts/Bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+ - "qcom,pcie-ipq8074" for ipq8074
- reg:
Usage: required
@@ -20,7 +21,7 @@
Value type: <stringlist>
Definition: Must include the following entries
- "parf" Qualcomm specific registers
- - "dbi" Designware PCIe registers
+ - "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "config" PCIe configuration space
@@ -105,6 +106,16 @@
- "bus_master" Master AXI clock
- "bus_slave" Slave AXI clock
+- clock-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" PCIe to SysNOC BIU clock
+ - "axi_m" AXI Master clock
+ - "axi_s" AXI Slave clock
+ - "ahb" AHB clock
+ - "aux" Auxiliary clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -144,6 +155,18 @@
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+- reset-names:
+ Usage: required for ipq8074
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "pipe" PIPE reset
+ - "sleep" Sleep reset
+ - "sticky" Core Sticky reset
+ - "axi_m" AXI Master reset
+ - "axi_s" AXI Slave reset
+ - "ahb" AHB Reset
+ - "axi_m_sticky" AXI Master Sticky reset
+
- power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: <prop-encoded-array>
@@ -180,7 +203,7 @@
- <name>-gpios:
Usage: optional
Value type: <prop-encoded-array>
- Definition: List of phandle and gpio specifier pairs. Should contain
+ Definition: List of phandle and GPIO specifier pairs. Should contain
- "perst-gpios" PCIe endpoint reset signal line
- "wake-gpios" PCIe endpoint wake signal line
diff --git a/dts/Bindings/pci/ralink,rt3883-pci.txt b/dts/Bindings/pci/ralink,rt3883-pci.txt
index 8e0a1eb..a04ab1b 100644
--- a/dts/Bindings/pci/ralink,rt3883-pci.txt
+++ b/dts/Bindings/pci/ralink,rt3883-pci.txt
@@ -71,7 +71,7 @@
- interrupt-map: standard PCI properties to define the mapping of the
PCI interface to interrupt numbers.
- The PCI host bridge node migh have additional sub-nodes representing
+ The PCI host bridge node might have additional sub-nodes representing
the onboard PCI devices/PCI slots. Each such sub-node must have the
following mandatory properties:
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index bd27428..76ba3a6 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -14,7 +14,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
SoC-specific version corresponding to the platform first
followed by the generic version.
-- reg: base address and length of the pcie controller registers.
+- reg: base address and length of the PCIe controller registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- bus-range: PCI bus numbers covered
@@ -25,15 +25,14 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
source for hardware related interrupts (e.g. link speed change).
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
- numbers.
+ to define the mapping of the PCIe interface to interrupt numbers.
- clocks: from common clock binding: clock specifiers for the PCIe controller
and PCIe bus clocks.
- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie: pcie@fe000000 {
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
@@ -54,5 +53,4 @@ SoC specific DT Entry:
interrupt-map = <0 0 0 0 &gic 0 116 4>;
clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
- status = "disabled";
};
diff --git a/dts/Bindings/pci/rockchip-pcie.txt b/dts/Bindings/pci/rockchip-pcie.txt
index 1453a73..af34c65 100644
--- a/dts/Bindings/pci/rockchip-pcie.txt
+++ b/dts/Bindings/pci/rockchip-pcie.txt
@@ -19,8 +19,6 @@ Required properties:
- "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. See ./pci-msi.txt
-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
-- phy-names: MUST be "pcie-phy".
- interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names
- "sys"
@@ -42,11 +40,24 @@ Required properties:
interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties
+Required properties for legacy PHY model (deprecated):
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names: MUST be "pcie-phy".
+
+Required properties for per-lane PHY model (preferred):
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+ them won't be used for your cases. Entries are of the form "pcie-phy-N":
+ where N ranges from 0 to 3.
+ (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+ for changing the #phy-cells of phy node to support it)
+
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
-- ep-gpios: contain the entry for pre-reset gpio
+- ep-gpios: contain the entry for pre-reset GPIO
- num-lanes: number of lanes to use
+- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 {
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
+ /* deprecated legacy PHY model */
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 {
#interrupt-cells = <1>;
};
};
+
+pcie0: pcie@f8000000 {
+ ...
+
+ /* preferred per-lane PHY model */
+ phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+
+ ...
+};
diff --git a/dts/Bindings/pci/samsung,exynos5440-pcie.txt b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
index 7d3b094..34a11bf 100644
--- a/dts/Bindings/pci/samsung,exynos5440-pcie.txt
+++ b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
@@ -1,29 +1,29 @@
* Samsung Exynos 5440 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the pcie controller,
- the phy controller, additional register for the phy controller.
- (Registers for the phy controller are DEPRECATED.
+- reg: base addresses and lengths of the PCIe controller,
+ the PHY controller, additional register for the PHY controller.
+ (Registers for the PHY controller are DEPRECATED.
Use the PHY framework.)
- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the confgiruation address space
+ And use the "config" instead of getting the configuration address space
from "ranges".
- NOTE: When use the "config" property, reg-names must be set.
+ NOTE: When using the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the Generic PHY.
+- phys: From PHY binding. Phandle for the generic PHY.
Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-Other common properties refer to
- Documentation/devicetree/binding/pci/designware-pcie.txt
+For other common properties, refer to
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
@@ -83,7 +83,7 @@ With using PHY framework:
...
};
-Board specific DT Entry:
+Board-specific DT Entry:
pcie@290000 {
reset-gpio = <&pin_ctrl 5 0>;
diff --git a/dts/Bindings/pci/spear13xx-pcie.txt b/dts/Bindings/pci/spear13xx-pcie.txt
index 49ea76d..d5a14f5 100644
--- a/dts/Bindings/pci/spear13xx-pcie.txt
+++ b/dts/Bindings/pci/spear13xx-pcie.txt
@@ -1,12 +1,12 @@
SPEAr13XX PCIe DT detail:
================================
-SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
controller.
Required properties:
-- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
-- phys : phandle to phy node associated with pcie controller
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to PHY node associated with PCIe controller
- phy-names : must be "pcie-phy"
- All other definitions as per generic PCI bindings
diff --git a/dts/Bindings/pci/ti-pci.txt b/dts/Bindings/pci/ti-pci.txt
index 6a07c96..7f7af30 100644
--- a/dts/Bindings/pci/ti-pci.txt
+++ b/dts/Bindings/pci/ti-pci.txt
@@ -1,6 +1,6 @@
TI PCI Controllers
-PCIe Designware Controller
+PCIe DesignWare Controller
- compatible: Should be "ti,dra7-pcie" for RC
Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
@@ -13,7 +13,7 @@ PCIe Designware Controller
HOST MODE
=========
- reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ - reg-names : The first entry must be "ti-conf" for the TI-specific registers
The second entry must be "rc-dbics" for the DesignWare PCIe
registers
The third entry must be "config" for the PCIe configuration space
@@ -30,7 +30,7 @@ HOST MODE
DEVICE MODE
===========
- reg : Four register ranges as listed in the reg-names property
- - reg-names : "ti-conf" for the TI specific registers
+ - reg-names : "ti-conf" for the TI-specific registers
"ep_dbics" for the standard configuration registers as
they are locally accessed within the DIF CS space
"ep_dbics2" for the standard configuration registers as
@@ -46,7 +46,7 @@ DEVICE MODE
access.
Optional Property:
- - gpios : Should be added if a gpio line is required to drive PERST# line
+ - gpios : Should be added if a GPIO line is required to drive PERST# line
NOTE: Two DT nodes may be added for each PCI controller; one for host
mode and another for device mode. So in order for PCI to
diff --git a/dts/Bindings/pci/versatile.txt b/dts/Bindings/pci/versatile.txt
index ebd1e7d..0a702b1 100644
--- a/dts/Bindings/pci/versatile.txt
+++ b/dts/Bindings/pci/versatile.txt
@@ -5,7 +5,7 @@ PCI host controller found on the ARM Versatile PB board's FPGA.
Required properties:
- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
controller.
-- reg: base addresses and lengths of the pci controller. There must be 3
+- reg: base addresses and lengths of the PCI controller. There must be 3
entries:
- Versatile-specific registers
- Self Config space
diff --git a/dts/Bindings/pci/xgene-pci-msi.txt b/dts/Bindings/pci/xgene-pci-msi.txt
index 36d881c..85d9b95 100644
--- a/dts/Bindings/pci/xgene-pci-msi.txt
+++ b/dts/Bindings/pci/xgene-pci-msi.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "apm,xgene1-msi" to identify
X-Gene v1 PCIe MSI controller block.
-- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node
+- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
- reg: physical base address (0x79000000) and length (0x900000) for controller
registers. These registers include the MSI termination address and data
registers as well as the MSI interrupt status registers.
@@ -13,7 +13,8 @@ Required properties:
interrupt number 0x10 to 0x1f.
- interrupt-names: not required
-Each PCIe node needs to have property msi-parent that points to msi controller node
+Each PCIe node needs to have property msi-parent that points to an MSI
+controller node
Examples:
@@ -44,7 +45,6 @@ SoC DTSI:
+ PCIe controller node with msi-parent property pointing to MSI node:
pcie0: pcie@1f2b0000 {
- status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
diff --git a/dts/Bindings/pci/xgene-pci.txt b/dts/Bindings/pci/xgene-pci.txt
index 1070b06..6fd2dec 100644
--- a/dts/Bindings/pci/xgene-pci.txt
+++ b/dts/Bindings/pci/xgene-pci.txt
@@ -8,7 +8,7 @@ Required properties:
property.
- reg-names: Must include the following entries:
"csr": controller configuration registers.
- "cfg": pcie configuration space registers.
+ "cfg": PCIe configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
@@ -21,11 +21,11 @@ Required properties:
Optional properties:
- status: Either "ok" or "disabled".
-- dma-coherent: Present if dma operations are coherent
+- dma-coherent: Present if DMA operations are coherent
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie0: pcie@1f2b0000 {
status = "disabled";
@@ -51,7 +51,7 @@ SoC specific DT Entry:
};
-Board specific DT Entry:
+Board-specific DT Entry:
&pcie0 {
status = "ok";
};
diff --git a/dts/Bindings/pci/xilinx-nwl-pcie.txt b/dts/Bindings/pci/xilinx-nwl-pcie.txt
index 3259798..01bf7fd 100644
--- a/dts/Bindings/pci/xilinx-nwl-pcie.txt
+++ b/dts/Bindings/pci/xilinx-nwl-pcie.txt
@@ -15,9 +15,9 @@ Required properties:
- device_type: must be "pci"
- interrupts: Should contain NWL PCIe interrupt
- interrupt-names: Must include the following entries:
- "msi1, msi0": interrupt asserted when MSI is received
+ "msi1, msi0": interrupt asserted when an MSI is received
"intx": interrupt asserted when a legacy interrupt is received
- "misc": interrupt asserted when miscellaneous is received
+ "misc": interrupt asserted when miscellaneous interrupt is received
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
@@ -26,7 +26,8 @@ Required properties:
detailed explanation
- msi-controller: indicates that this is MSI controller node
- msi-parent: MSI parent of the root complex itself
-- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
+- legacy-interrupt-controller: Interrupt controller device node for Legacy
+ interrupts
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: should be set to 1
- #address-cells: specifies the number of cells needed to encode an
diff --git a/dts/Bindings/phy/apm-xgene-phy.txt b/dts/Bindings/phy/apm-xgene-phy.txt
index 5f3a65a..e1bb127 100644
--- a/dts/Bindings/phy/apm-xgene-phy.txt
+++ b/dts/Bindings/phy/apm-xgene-phy.txt
@@ -61,19 +61,16 @@ Example:
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
#phy-cells = <1>;
- status = "disabled";
};
phy2: phy@1f22a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
- status = "ok";
};
phy3: phy@1f23a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
- status = "ok";
};
diff --git a/dts/Bindings/phy/keystone-usb-phy.txt b/dts/Bindings/phy/keystone-usb-phy.txt
index f37b3a8..300830d 100644
--- a/dts/Bindings/phy/keystone-usb-phy.txt
+++ b/dts/Bindings/phy/keystone-usb-phy.txt
@@ -16,5 +16,4 @@ usb_phy: usb_phy@2620738 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2620738 32>;
- status = "disabled";
};
diff --git a/dts/Bindings/phy/phy-bindings.txt b/dts/Bindings/phy/phy-bindings.txt
index 1293c32..a403b81 100644
--- a/dts/Bindings/phy/phy-bindings.txt
+++ b/dts/Bindings/phy/phy-bindings.txt
@@ -34,7 +34,9 @@ PHY user node
=============
Required Properties:
-phys : the phandle for the PHY device (used by the PHY subsystem)
+phys : the phandle for the PHY device (used by the PHY subsystem; not to be
+ confused with the Ethernet specific 'phy' and 'phy-handle' properties,
+ see Documentation/devicetree/bindings/net/ethernet.txt for these)
phy-names : the names of the PHY corresponding to the PHYs present in the
*phys* phandle
diff --git a/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt b/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 0000000..643948b
--- /dev/null
+++ b/dts/Bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,40 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible : Should be one of
+ "lantiq,ase-usb2-phy"
+ "lantiq,danube-usb2-phy"
+ "lantiq,xrx100-usb2-phy"
+ "lantiq,xrx200-usb2-phy"
+ "lantiq,xrx300-usb2-phy"
+- reg : Defines the following sets of registers in the parent
+ syscon device
+ - Offset of the USB PHY configuration register
+ - Offset of the USB Analog configuration
+ register (only for xrx200 and xrx200)
+- clocks : References to the (PMU) "phy" clk gate.
+- clock-names : Must be "phy"
+- resets : References to the RCU USB configuration reset bits.
+- reset-names : Must be one of the following:
+ "phy" (optional)
+ "ctrl" (shared)
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+ usb_phy0: usb2-phy@18 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x18 4>, <0x38 4>;
+
+ clocks = <&pmu PMU_GATE_USB0_PHY>;
+ clock-names = "phy";
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/phy-mt65xx-usb.txt b/dts/Bindings/phy/phy-mtk-tphy.txt
index 0acc5a9..41e09ed 100644
--- a/dts/Bindings/phy/phy-mt65xx-usb.txt
+++ b/dts/Bindings/phy/phy-mtk-tphy.txt
@@ -1,13 +1,18 @@
-mt65xx USB3.0 PHY binding
+MediaTek T-PHY binding
--------------------------
-This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
+T-phy controller supports physical layer functionality for a number of
+controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
Required properties (controller (parent) node):
- compatible : should be one of
- "mediatek,mt2701-u3phy"
- "mediatek,mt2712-u3phy"
- "mediatek,mt8173-u3phy"
+ "mediatek,generic-tphy-v1"
+ "mediatek,generic-tphy-v2"
+ "mediatek,mt2701-u3phy" (deprecated)
+ "mediatek,mt2712-u3phy" (deprecated)
+ "mediatek,mt8173-u3phy";
+ make use of "mediatek,generic-tphy-v1" on mt2701 instead and
+ "mediatek,generic-tphy-v2" on mt2712 instead.
- clocks : (deprecated, use port's clocks instead) a list of phandle +
clock-specifier pairs, one for each entry in clock-names
- clock-names : (deprecated, use port's one instead) must contain
@@ -35,6 +40,8 @@ Required properties (port (child) node):
cell after port phandle is phy type from:
- PHY_TYPE_USB2
- PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
Example:
@@ -44,14 +51,12 @@ u3phy: usb-phy@11290000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- status = "okay";
u2port0: usb-phy@11290800 {
reg = <0 0x11290800 0 0x100>;
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
u3port0: usb-phy@11290900 {
@@ -59,7 +64,6 @@ u3phy: usb-phy@11290000 {
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
u2port1: usb-phy@11291000 {
@@ -67,7 +71,6 @@ u3phy: usb-phy@11290000 {
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
clock-names = "ref";
#phy-cells = <1>;
- status = "okay";
};
};
diff --git a/dts/Bindings/phy/phy-mvebu-comphy.txt b/dts/Bindings/phy/phy-mvebu-comphy.txt
new file mode 100644
index 0000000..bfcf803
--- /dev/null
+++ b/dts/Bindings/phy/phy-mvebu-comphy.txt
@@ -0,0 +1,43 @@
+mvebu comphy driver
+-------------------
+
+A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It
+provides a number of shared PHYs used by various interfaces (network, sata,
+usb, PCIe...).
+
+Required properties:
+
+- compatible: should be "marvell,comphy-cp110"
+- reg: should contain the comphy register location and length.
+- marvell,system-controller: should contain a phandle to the
+ system controller node.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+A sub-node is required for each comphy lane provided by the comphy.
+
+Required properties (child nodes):
+
+- reg: comphy lane number.
+- #phy-cells : from the generic phy bindings, must be 1. Defines the
+ input port to use for a given comphy lane.
+
+Example:
+
+ cpm_comphy: phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&cpm_syscon0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpm_comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ cpm_comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/phy-mvebu.txt b/dts/Bindings/phy/phy-mvebu.txt
index f95b626..64afdd1 100644
--- a/dts/Bindings/phy/phy-mvebu.txt
+++ b/dts/Bindings/phy/phy-mvebu.txt
@@ -18,7 +18,6 @@ Example:
clocks = <&gate_clk 15>;
clock-names = "sata";
#phy-cells = <0>;
- status = "ok";
};
Armada 375 USB cluster
diff --git a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
index 84d59b0..074a7b3 100644
--- a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
@@ -6,6 +6,7 @@ Required properties (phy (parent) node):
* "rockchip,rk3328-usb2phy"
* "rockchip,rk3366-usb2phy"
* "rockchip,rk3399-usb2phy"
+ * "rockchip,rv1108-usb2phy"
- reg : the address offset of grf for usb-phy configuration.
- #clock-cells : should be 0.
- clock-output-names : specify the 480m output clock name.
@@ -18,6 +19,10 @@ Optional properties:
usb-phy output 480m and xin24m.
Refer to clk/clock-bindings.txt for generic clock
consumer properties.
+ - rockchip,usbgrf : phandle to the syscon managing the "usb general
+ register files". When set driver will request its
+ phandle as one companion-grf for some special SoCs
+ (e.g RV1108).
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify host or otg port,
@@ -28,10 +33,14 @@ Required nodes : a sub-node is required for each port the phy provides.
Required properties (port (child) node):
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
- interrupts : specify an interrupt for each entry in interrupt-names.
- - interrupt-names : a list which shall be the following entries:
+ - interrupt-names : a list which should be one of the following cases:
+ Regular case:
* "otg-id" : for the otg id interrupt.
* "otg-bvalid" : for the otg vbus interrupt.
* "linestate" : for the host/otg linestate interrupt.
+ Some SoCs use one interrupt with the above muxed together, so for these
+ * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate
+ to one.
Optional properties:
- phy-supply : phandle to a regulator that provides power to VBUS.
@@ -58,14 +67,12 @@ grf: syscon@ff770000 {
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-id", "otg-bvalid", "linestate";
- status = "okay";
};
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
- status = "okay";
};
};
};
diff --git a/dts/Bindings/phy/qcom-dwc3-usb-phy.txt b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
index 86f2dbe..a1697c2 100644
--- a/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
+++ b/dts/Bindings/phy/qcom-dwc3-usb-phy.txt
@@ -25,7 +25,6 @@ Example:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
phy@100f8830 {
@@ -35,5 +34,4 @@ Example:
clock-names = "ref";
#phy-cells = <0>;
- status = "ok";
};
diff --git a/dts/Bindings/phy/qcom-qmp-phy.txt b/dts/Bindings/phy/qcom-qmp-phy.txt
index e11c563..b6a9f2b 100644
--- a/dts/Bindings/phy/qcom-qmp-phy.txt
+++ b/dts/Bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
Required properties:
- compatible: compatible list, contains:
+ "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,ipq8074-qmp-pcie-phy" must contain:
+ "phy", "common".
- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -60,6 +63,13 @@ Required properties for child node:
one for each entry in clock-names.
- clock-names: Must contain following for pcie and usb qmp phys:
"pipe<lane-number>" for pipe clock specific to each lane.
+ - clock-output-names: Name of the PHY clock that will be the parent for
+ the above pipe clock.
+
+ For "qcom,ipq8074-qmp-pcie-phy":
+ - "pcie20_phy0_pipe_clk" Pipe Clock parent
+ (or)
+ "pcie20_phy1_pipe_clk"
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
@@ -96,6 +106,7 @@ Example:
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+ clock-output-names = "pcie_0_pipe_clk_src";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
diff --git a/dts/Bindings/phy/ralink-usb-phy.txt b/dts/Bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 0000000..9d2868a
--- /dev/null
+++ b/dts/Bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,23 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: "ralink,rt3352-usbphy"
+ "mediatek,mt7620-usbphy"
+ "mediatek,mt7628-usbphy"
+ - reg: required for "mediatek,mt7628-usbphy", unused otherwise
+ - #phy-cells: should be 0
+ - ralink,sysctl: a phandle to a ralink syscon register region
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x10120000 0x1000>;
+ #phy-cells = <0>;
+
+ ralink,sysctl = <&sysc>;
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
diff --git a/dts/Bindings/phy/rockchip-pcie-phy.txt b/dts/Bindings/phy/rockchip-pcie-phy.txt
index 0f6222a..b496042 100644
--- a/dts/Bindings/phy/rockchip-pcie-phy.txt
+++ b/dts/Bindings/phy/rockchip-pcie-phy.txt
@@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties:
- compatible: rockchip,rk3399-pcie-phy
- - #phy-cells: must be 0
- clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names: Must be "phy"
+Required properties for legacy PHY mode (deprecated):
+ - #phy-cells: must be 0
+
+Required properties for per-lane PHY mode (preferred):
+ - #phy-cells: must be 1
+
Example:
grf: syscon@ff770000 {
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt
index ab80bfe..1c40ccd 100644
--- a/dts/Bindings/phy/samsung-phy.txt
+++ b/dts/Bindings/phy/samsung-phy.txt
@@ -82,7 +82,6 @@ usbphy: phy@125b0000 {
reg = <0x125b0000 0x100>;
clocks = <&clock 305>, <&clock 2>;
clock-names = "phy", "ref";
- status = "okay";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sys_reg>;
samsung,pmureg-phandle = <&pmu_reg>;
diff --git a/dts/Bindings/phy/sun4i-usb-phy.txt b/dts/Bindings/phy/sun4i-usb-phy.txt
index 005bc22..cbc7847 100644
--- a/dts/Bindings/phy/sun4i-usb-phy.txt
+++ b/dts/Bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
@@ -17,18 +18,22 @@ Required properties:
* "phy_ctrl"
* "pmu0" for H3, V3s and A64
* "pmu1"
- * "pmu2" for sun4i, sun6i or sun7i
+ * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+ * "pmu3" for sun8i-h3
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clocks
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
* "usb0_phy", "usb1_phy" for sun8i
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
- * "usb2_reset" for sun4i, sun6i or sun7i
+ * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+ * "usb3_reset" for sun8i-h3
Optional properties:
- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
@@ -37,6 +42,7 @@ Optional properties:
- usb0_vbus-supply : regulator phandle for controller usb0 vbus
- usb1_vbus-supply : regulator phandle for controller usb1 vbus
- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Example:
usbphy: phy@0x01c13400 {
diff --git a/dts/Bindings/phy/sun9i-usb-phy.txt b/dts/Bindings/phy/sun9i-usb-phy.txt
index 1cca85c..f985315 100644
--- a/dts/Bindings/phy/sun9i-usb-phy.txt
+++ b/dts/Bindings/phy/sun9i-usb-phy.txt
@@ -33,6 +33,5 @@ Example:
clock-names = "hsic_480M", "hsic_12M", "phy";
resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
reset-names = "hsic", "phy";
- status = "disabled";
#phy-cells = <0>;
};
diff --git a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
index 590e603..3e23fec 100644
--- a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -148,5 +148,4 @@ dbgu: serial@fffff200 {
interrupts = <1 4 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- status = "disabled";
};
diff --git a/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt b/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt
new file mode 100644
index 0000000..61466c5
--- /dev/null
+++ b/dts/Bindings/pinctrl/cortina,gemini-pinctrl.txt
@@ -0,0 +1,59 @@
+Cortina Systems Gemini pin controller
+
+This pin controller is found in the Cortina Systems Gemini SoC family,
+see further arm/gemini.txt. It is a purely group-based multiplexing pin
+controller.
+
+The pin controller node must be a subnode of the system controller node.
+
+Required properties:
+- compatible: "cortina,gemini-pinctrl"
+
+Subnodes of the pin controller contain pin control multiplexing set-up.
+Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
+
+Example:
+
+
+syscon {
+ compatible = "cortina,gemini-syscon";
+ ...
+ pinctrl {
+ compatible = "cortina,gemini-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
+ <&vcontrol_default_pins>;
+
+ dram_default_pins: pinctrl-dram {
+ mux {
+ function = "dram";
+ groups = "dramgrp";
+ };
+ };
+ rtc_default_pins: pinctrl-rtc {
+ mux {
+ function = "rtc";
+ groups = "rtcgrp";
+ };
+ };
+ power_default_pins: pinctrl-power {
+ mux {
+ function = "power";
+ groups = "powergrp";
+ };
+ };
+ system_default_pins: pinctrl-system {
+ mux {
+ function = "system";
+ groups = "systemgrp";
+ };
+ };
+ (...)
+ uart_default_pins: pinctrl-uart {
+ mux {
+ function = "uart";
+ groups = "uartrxtxgrp";
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
index 9fde25f..42d74f8 100644
--- a/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/dts/Bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -61,7 +61,6 @@ Examples:
usdhc@0219c000 { /* uSDHC4 */
non-removable;
vmmc-supply = <&reg_3p3v>;
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
};
diff --git a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8c5d27c..6666277 100644
--- a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -61,7 +61,6 @@ iomuxc-lpsr controller and SDA pad from iomuxc controller as:
i2c1: i2c@30a20000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
- status = "okay";
};
iomuxc-lpsr@302c0000 {
diff --git a/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
new file mode 100644
index 0000000..44ad670
--- /dev/null
+++ b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
@@ -0,0 +1,61 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
+ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it only
+supports generic pin config.
+
+Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
+binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible: "fsl,imx7ulp-iomuxc1"
+- reg: Should contain the base physical address and size of the iomuxc
+ registers.
+
+=== Pin Configuration Node ===
+- pinmux: One integers array, represents a group of pins mux setting.
+ The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+ a specific function.
+
+ NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+ and config register as follows:
+ <mux_conf_reg input_reg mux_mode input_val>
+
+ Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+ available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- drive-strength Integer. Controls Drive Strength
+ 0: Standard
+ 1: Hi Driver
+- drive-push-pull Bool. Enable Pin Push-pull
+- drive-open-drain Bool. Enable Pin Open-drian
+- slew-rate: Integer. Controls Slew Rate
+ 0: Standard
+ 1: Slow
+- bias-disable: Bool. Pull disabled
+- bias-pull-down: Bool. Pull down on pin
+- bias-pull-up: Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+
+ /* Pin Configuration Node */
+ pinctrl_lpuart4: lpuart4grp {
+ pinmux = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX
+ IMX7ULP_PAD_PTC2__LPUART4_TX
+ >;
+ bias-pull-up;
+ };
+};
diff --git a/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
index f2abdae..e0e886b 100644
--- a/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
+++ b/dts/Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
@@ -56,5 +56,4 @@ Example:
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
pinctrl-names = "default", "idle";
- status = "disabled";
};
diff --git a/dts/Bindings/pinctrl/oxnas,pinctrl.txt b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
index 09e81a9..b115943 100644
--- a/dts/Bindings/pinctrl/oxnas,pinctrl.txt
+++ b/dts/Bindings/pinctrl/oxnas,pinctrl.txt
@@ -50,7 +50,6 @@ uart2: serial@900000 {
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
- status = "disabled";
resets = <&reset 22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
diff --git a/dts/Bindings/pinctrl/pinctrl-aspeed.txt b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
index ca01710..3b7266c 100644
--- a/dts/Bindings/pinctrl/pinctrl-aspeed.txt
+++ b/dts/Bindings/pinctrl/pinctrl-aspeed.txt
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
-VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
+USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
+WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
@@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
-TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
+TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
+VGAVS VPI24 VPO WDTRST1 WDTRST2
Examples
========
diff --git a/dts/Bindings/pinctrl/pinctrl-bindings.txt b/dts/Bindings/pinctrl/pinctrl-bindings.txt
index 62d0f33f..4483cc3 100644
--- a/dts/Bindings/pinctrl/pinctrl-bindings.txt
+++ b/dts/Bindings/pinctrl/pinctrl-bindings.txt
@@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
+sleep-hardware-state - indicate this is sleep related state which will be programmed
+ into the registers for the sleep state.
slew-rate - set the slew rate
For example:
diff --git a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
index 17631d0..37d7447 100644
--- a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt
@@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
+ "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
diff --git a/dts/Bindings/pinctrl/pinctrl-rk805.txt b/dts/Bindings/pinctrl/pinctrl-rk805.txt
new file mode 100644
index 0000000..eee3dc2
--- /dev/null
+++ b/dts/Bindings/pinctrl/pinctrl-rk805.txt
@@ -0,0 +1,63 @@
+Pincontrol driver for RK805 Power management IC.
+
+RK805 has 2 pins which can be configured as GPIO output only.
+
+Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
+for details of the common pinctrl bindings used by client devices,
+including the meaning of the phrase "pin configuration node".
+
+Optional Pinmux properties:
+--------------------------
+Following properties are required if default setting of pins are required
+at boot.
+- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
+ <pinctrl-binding.txt>.
+
+The pin configurations are defined as child of the pinctrl states node. Each
+sub-node have following properties:
+
+Required properties:
+------------------
+- #gpio-cells: Should be two. The first cell is the pin number and the
+ second is the GPIO flags.
+
+- gpio-controller: Marks the device node as a GPIO controller.
+
+- pins: List of pins. Valid values of pins properties are: gpio0, gpio1.
+
+First 2 properties must be added in the RK805 PMIC node, documented in
+Documentation/devicetree/bindings/mfd/rk808.txt
+
+Optional properties:
+-------------------
+Following are optional properties defined as pinmux DT binding document
+<pinctrl-bindings.txt>. Absence of properties will leave the configuration
+on default.
+ function,
+ output-low,
+ output-high.
+
+Valid values for function properties are: gpio.
+
+Theres is also not customised properties for any GPIO.
+
+Example:
+--------
+rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ ...
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&rk805_default>;
+
+ rk805_default: pinmux {
+ gpio01 {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ output-high;
+ };
+ };
+};
diff --git a/dts/Bindings/pinctrl/pinctrl-zx.txt b/dts/Bindings/pinctrl/pinctrl-zx.txt
index e219849..39170f3 100644
--- a/dts/Bindings/pinctrl/pinctrl-zx.txt
+++ b/dts/Bindings/pinctrl/pinctrl-zx.txt
@@ -81,5 +81,4 @@ pmm: pin-controller@1462000 {
&vga {
pinctrl-names = "default";
pinctrl-0 = <&vga_pins>;
- status = "okay";
};
diff --git a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
index a7bde64..a752a47 100644
--- a/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -46,7 +46,8 @@ Valid values for pins are:
gpio0-gpio89
Valid values for function are:
- cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
+ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
+ gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
diff --git a/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
index cfb8500..93374f4 100644
--- a/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
+++ b/dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -50,7 +50,11 @@ Valid values for qcom,pins are:
Supports mux, bias and drive-strength
Valid values for qcom,function are:
-gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
+aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
+blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
+jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
+mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
+smart2, smart3, tm, wifi0, wifi1
Example:
diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
index 8d893a8..5b12c57 100644
--- a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
@@ -16,6 +16,7 @@ PMIC's from Qualcomm.
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
+ "qcom,pmi8994-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
+ gpio1-gpio10 for pmi8994
- function:
Usage: required
@@ -98,7 +100,10 @@ to specify in a pin configuration subnode:
"dtest1",
"dtest2",
"dtest3",
- "dtest4"
+ "dtest4",
+ And following values are supported by LV/MV GPIO subtypes:
+ "func3",
+ "func4"
- bias-disable:
Usage: optional
@@ -183,6 +188,25 @@ to specify in a pin configuration subnode:
Value type: <none>
Definition: The specified pins are configured in open-source mode.
+- qcom,analog-pass:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in analog-pass-through mode.
+
+- qcom,atest:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects ATEST rail to route to GPIO when it's configured
+ in analog-pass-through mode.
+ Valid values are 1-4 corresponding to ATEST1 to ATEST4.
+
+- qcom,dtest-buffer:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects DTEST rail to route to GPIO when it's configured
+ as digital input.
+ Valid values are 1-4 corresponding to DTEST1 to DTEST4.
+
Example:
pm8921_gpio: gpio@150 {
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 645082f0..9b4f804 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
+ - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
@@ -111,7 +112,7 @@ Examples
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
- pfc: pfc@e6050000 {
+ pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
@@ -172,5 +173,4 @@ Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
- status = "okay";
};
diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
index ee01ab5..4864e3a 100644
--- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt
+++ b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
@@ -24,6 +24,7 @@ Required properties for iomux controller:
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
+ "rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
@@ -120,7 +121,6 @@ uart2: serial@20064000 {
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&mux_uart2>;
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
diff --git a/dts/Bindings/pinctrl/sprd,pinctrl.txt b/dts/Bindings/pinctrl/sprd,pinctrl.txt
new file mode 100644
index 0000000..b1cea7a
--- /dev/null
+++ b/dts/Bindings/pinctrl/sprd,pinctrl.txt
@@ -0,0 +1,83 @@
+* Spreadtrum Pin Controller
+
+The Spreadtrum pin controller are organized in 3 blocks (types).
+
+The first block comprises some global control registers, and each
+register contains several bit fields with one bit or several bits
+to configure for some global common configuration, such as domain
+pad driving level, system control select and so on ("domain pad
+driving level": One pin can output 3.0v or 1.8v, depending on the
+related domain pad driving selection, if the related domain pad
+slect 3.0v, then the pin can output 3.0v. "system control" is used
+to choose one function (like: UART0) for which system, since we
+have several systems (AP/CP/CM4) on one SoC.).
+
+There are too much various configuration that we can not list all
+of them, so we can not make every Spreadtrum-special configuration
+as one generic configuration, and maybe it will add more strange
+global configuration in future. Then we add one "sprd,control" to
+set these various global control configuration, and we need use
+magic number for this property.
+
+Moreover we recognise every fields comprising one bit or several
+bits in one global control register as one pin, thus we should
+record every pin's bit offset, bit width and register offset to
+configure this field (pin).
+
+The second block comprises some common registers which have unified
+register definition, and each register described one pin is used
+to configure the pin sleep mode, function select and sleep related
+configuration.
+
+Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
+PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
+related configuration are:
+- input-enable
+- input-disable
+- output-high
+- output-low
+- bias-pull-up
+- bias-pull-down
+
+In some situation we need set the pin sleep mode and pin sleep related
+configuration, to set the pin sleep related configuration automatically
+by hardware when the system specified by sleep mode goes into deep
+sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
+and set the pin sleep related configuration as "input-enable", which
+means when PUBCP system goes into deep sleep mode, this pin will be set
+input enable automatically.
+
+Moreover we can not use the "sleep" state, since some systems (like:
+PUBCP system) do not run linux kernel OS (only AP system run linux
+kernel on SC9860 platform), then we can not select "sleep" state
+when the PUBCP system goes into deep sleep mode. Thus we introduce
+"sprd,sleep-mode" property to set pin sleep mode.
+
+The last block comprises some misc registers which also have unified
+register definition, and each register described one pin is used to
+configure drive strength, pull up/down and so on. Especially for pull
+up, we have two kind pull up resistor: 20K and 4.7K.
+
+Required properties for Spreadtrum pin controller:
+- compatible: "sprd,<soc>-pinctrl"
+ Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
+- reg: The register address of pin controller device.
+- pins : An array of pin names.
+
+Optional properties:
+- function: Specified the function name.
+- drive-strength: Drive strength in mA.
+- input-schmitt-disable: Enable schmitt-trigger mode.
+- input-schmitt-enable: Disable schmitt-trigger mode.
+- bias-disable: Disable pin bias.
+- bias-pull-down: Pull down on pin.
+- bias-pull-up: Pull up on pin.
+- input-enable: Enable pin input.
+- input-disable: Enable pin output.
+- output-high: Set the pin as an output level high.
+- output-low: Set the pin as an output level low.
+- sleep-hardware-state: Indicate these configs in this state are sleep related.
+- sprd,control: Control values referring to databook for global control pins.
+- sprd,sleep-mode: Sleep mode selection.
+
+Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.
diff --git a/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt b/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt
new file mode 100644
index 0000000..5a62833
--- /dev/null
+++ b/dts/Bindings/pinctrl/sprd,sc9860-pinctrl.txt
@@ -0,0 +1,70 @@
+* Spreadtrum SC9860 Pin Controller
+
+Please refer to sprd,pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: Must be "sprd,sc9860-pinctrl".
+- reg: The register address of pin controller device.
+- pins : An array of strings, each string containing the name of a pin.
+
+Optional properties:
+- function: A string containing the name of the function, values must be
+ one of: "func1", "func2", "func3" and "func4".
+- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
+ 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
+- input-schmitt-disable: Enable schmitt-trigger mode.
+- input-schmitt-enable: Disable schmitt-trigger mode.
+- bias-disable: Disable pin bias.
+- bias-pull-down: Pull down on pin.
+- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
+ is 20K and 4700 for pull-up resistor is 4.7K.
+- input-enable: Enable pin input.
+- input-disable: Enable pin output.
+- output-high: Set the pin as an output level high.
+- output-low: Set the pin as an output level low.
+- sleep-hardware-state: Indicate these configs in this state are sleep related.
+- sprd,control: Control values referring to databook for global control pins.
+- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
+ AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.
+
+Pin sleep mode definition:
+enum pin_sleep_mode {
+ AP_SLEEP = BIT(0),
+ PUBCP_SLEEP = BIT(1),
+ TGLDSP_SLEEP = BIT(2),
+ AGDSP_SLEEP = BIT(3),
+};
+
+Example:
+pin_controller: pinctrl@402a0000 {
+ compatible = "sprd,sc9860-pinctrl";
+ reg = <0x402a0000 0x10000>;
+
+ grp1: sd0 {
+ pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
+ sprd,control = <0x1>;
+ };
+
+ grp2: rfctl_33 {
+ pins = "SC9860_RFCTL33";
+ function = "func2";
+ sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
+ grp2_sleep_mode: rfctl_33_sleep {
+ pins = "SC9860_RFCTL33";
+ sleep-hardware-state;
+ output-low;
+ }
+ };
+
+ grp3: rfctl_misc_20 {
+ pins = "SC9860_RFCTL20_MISC";
+ drive-strength = <10>;
+ bias-pull-up = <4700>;
+ grp3_sleep_mode: rfctl_misc_sleep {
+ pins = "SC9860_RFCTL20_MISC";
+ sleep-hardware-state;
+ bias-pull-up;
+ }
+ };
+};
diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
index d907a74..33e3d3c 100644
--- a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -180,5 +180,4 @@ pin-controller {
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
- status = "okay";
};
diff --git a/dts/Bindings/power/power-controller.txt b/dts/Bindings/power/power-controller.txt
index 4f7a3bc..e45affe 100644
--- a/dts/Bindings/power/power-controller.txt
+++ b/dts/Bindings/power/power-controller.txt
@@ -13,6 +13,5 @@ Example:
act8846: act8846@5 {
compatible = "active-semi,act8846";
- status = "okay";
system-power-controller;
}
diff --git a/dts/Bindings/power/renesas,apmu.txt b/dts/Bindings/power/renesas,apmu.txt
index 84404c9..af21502 100644
--- a/dts/Bindings/power/renesas,apmu.txt
+++ b/dts/Bindings/power/renesas,apmu.txt
@@ -1,12 +1,13 @@
DT bindings for the Renesas Advanced Power Management Unit
-Renesas R-Car line of SoCs utilize one or more APMU hardware units
+Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.
Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
+ - "renesas,r8a7743-apmu" (RZ/G1M)
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
diff --git a/dts/Bindings/power/renesas,rcar-sysc.txt b/dts/Bindings/power/renesas,rcar-sysc.txt
index d91715b..98cc8c0 100644
--- a/dts/Bindings/power/renesas,rcar-sysc.txt
+++ b/dts/Bindings/power/renesas,rcar-sysc.txt
@@ -17,6 +17,7 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
+ - "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/dts/Bindings/power/reset/st-reset.txt b/dts/Bindings/power/reset/st-reset.txt
index 83734dc..b639487 100644
--- a/dts/Bindings/power/reset/st-reset.txt
+++ b/dts/Bindings/power/reset/st-reset.txt
@@ -8,5 +8,4 @@ Example node:
restart {
compatible = "st,stih407-restart";
st,syscfg = <&syscfg_sbc_reg>;
- status = "okay";
};
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
index 43c21fb..4a4766e 100644
--- a/dts/Bindings/power/rockchip-io-domain.txt
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -39,6 +39,8 @@ Required properties:
- "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
- "rockchip,rk3399-io-voltage-domain" for rk3399
- "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains
+ - "rockchip,rv1108-io-voltage-domain" for rv1108
+ - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains
Deprecated properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
diff --git a/dts/Bindings/power/supply/act8945a-charger.txt b/dts/Bindings/power/supply/act8945a-charger.txt
index de78d76..b86ecad 100644
--- a/dts/Bindings/power/supply/act8945a-charger.txt
+++ b/dts/Bindings/power/supply/act8945a-charger.txt
@@ -29,7 +29,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
charger {
compatible = "active-semi,act8945a-charger";
@@ -43,6 +42,5 @@ Example:
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
- status = "okay";
};
};
diff --git a/dts/Bindings/power/supply/bq24190.txt b/dts/Bindings/power/supply/bq24190.txt
new file mode 100644
index 0000000..9e517d3
--- /dev/null
+++ b/dts/Bindings/power/supply/bq24190.txt
@@ -0,0 +1,51 @@
+TI BQ24190 Li-Ion Battery Charger
+
+Required properties:
+- compatible: contains one of the following:
+ * "ti,bq24190"
+ * "ti,bq24192i"
+- reg: integer, I2C address of the charger.
+- interrupts[-extended]: configuration for charger INT pin.
+
+Optional properties:
+- monitored-battery: phandle of battery characteristics devicetree node
+ The charger uses the following battery properties:
+ + precharge-current-microamp: maximum charge current during precharge
+ phase (typically 20% of battery capacity).
+ + charge-term-current-microamp: a charge cycle terminates when the
+ battery voltage is above recharge threshold, and the current is below
+ this setting (typically 10% of battery capacity).
+ See also Documentation/devicetree/bindings/power/supply/battery.txt
+- ti,system-minimum-microvolt: when power is connected and the battery is below
+ minimum system voltage, the system will be regulated above this setting.
+
+Notes:
+- Some circuit boards wire the chip's "OTG" pin high (enabling 500mA default
+ charge current on USB SDP ports, among other features). To simulate this on
+ boards that wire the pin to a GPIO, set a gpio-hog.
+
+Example:
+
+ bat: battery {
+ compatible = "simple-battery";
+ precharge-current-microamp = <256000>;
+ charge-term-current-microamp = <128000>;
+ // etc.
+ };
+
+ bq24190: charger@6a {
+ compatible = "ti,bq24190";
+ reg = <0x6a>;
+ interrupts-extended = <&gpiochip 10 IRQ_TYPE_EDGE_FALLING>;
+ monitored-battery = <&bat>;
+ ti,system-minimum-microvolt = <3200000>;
+ };
+
+ &twl_gpio {
+ otg {
+ gpio-hog;
+ gpios = <6 0>;
+ output-high;
+ line-name = "otg-gpio";
+ };
+ };
diff --git a/dts/Bindings/power/supply/ltc2941.txt b/dts/Bindings/power/supply/ltc2941.txt
index a9d7aa6..3b9ba14 100644
--- a/dts/Bindings/power/supply/ltc2941.txt
+++ b/dts/Bindings/power/supply/ltc2941.txt
@@ -1,13 +1,14 @@
-binding for LTC2941 and LTC2943 battery gauges
+binding for LTC2941, LTC2942, LTC2943 and LTC2944 battery gauges
-Both the LTC2941 and LTC2943 measure battery capacity.
-The LTC2943 is compatible with the LTC2941, it adds voltage and
-temperature monitoring, and uses a slightly different conversion
-formula for the charge counter.
+All chips measure battery capacity.
+The LTC2942 is pin compatible with the LTC2941, it adds voltage and
+temperature monitoring, and is runtime detected. LTC2943 and LTC2944
+is software compatible, uses a slightly different conversion formula
+for the charge counter and adds voltage, current and temperature monitoring.
Required properties:
-- compatible: Should contain "lltc,ltc2941" or "lltc,ltc2943" which also
- indicates the type of I2C chip attached.
+- compatible: Should contain "lltc,ltc2941", "lltc,ltc2942", "lltc,ltc2943"
+ or "lltc,ltc2944" which also indicates the type of I2C chip attached.
- reg: The 7-bit I2C address.
- lltc,resistor-sense: The sense resistor value in milli-ohms. Can be a 32-bit
negative value when the battery has been connected to the wrong end of the
diff --git a/dts/Bindings/power/supply/max8903-charger.txt b/dts/Bindings/power/supply/max8903-charger.txt
index f0f4e12..bab947f 100644
--- a/dts/Bindings/power/supply/max8903-charger.txt
+++ b/dts/Bindings/power/supply/max8903-charger.txt
@@ -21,5 +21,4 @@ Example:
flt-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
- status = "okay";
};
diff --git a/dts/Bindings/power/supply/maxim,max14656.txt b/dts/Bindings/power/supply/maxim,max14656.txt
index e03e85a..d6e8dfd 100644
--- a/dts/Bindings/power/supply/maxim,max14656.txt
+++ b/dts/Bindings/power/supply/maxim,max14656.txt
@@ -12,7 +12,6 @@ Example:
clock-frequency = <50000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
max14656@35 {
compatible = "maxim,max14656";
diff --git a/dts/Bindings/power/wakeup-source.txt b/dts/Bindings/power/wakeup-source.txt
index 963c6df..3c81f78 100644
--- a/dts/Bindings/power/wakeup-source.txt
+++ b/dts/Bindings/power/wakeup-source.txt
@@ -20,13 +20,12 @@ List of legacy properties and respective binding document
1. "enable-sdio-wakeup" Documentation/devicetree/bindings/mmc/mmc.txt
2. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt
3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt
-4. "isil,irq2-can-wakeup-machine" Documentation/devicetree/bindings/rtc/isil,isl12057.txt
-5. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
+4. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
Documentation/devicetree/bindings/mfd/tc3589x.txt
Documentation/devicetree/bindings/input/ads7846.txt
-6. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
-7. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
-8. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+5. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
+6. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
+7. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
Examples
--------
diff --git a/dts/Bindings/powerpc/ibm,vas.txt b/dts/Bindings/powerpc/ibm,vas.txt
new file mode 100644
index 0000000..bf11d2f
--- /dev/null
+++ b/dts/Bindings/powerpc/ibm,vas.txt
@@ -0,0 +1,22 @@
+* IBM Powerpc Virtual Accelerator Switchboard (VAS)
+
+VAS is a hardware mechanism that allows kernel subsystems and user processes
+to directly submit compression and other requests to Nest accelerators (NX)
+or other coprocessors functions.
+
+Required properties:
+- compatible : should be "ibm,vas".
+- ibm,vas-id : A unique identifier for each instance of VAS in the system
+- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor
+ window context start and length, OS/User window context start and length,
+ "Paste address" start and length, "Paste window id" start bit and number
+ of bits)
+
+Example:
+
+ vas@6019100000000 {
+ compatible = "ibm,vas", "ibm,power9-vas";
+ reg = <0x6019100000000 0x2000000 0x6019000000000 0x100000000 0x8000000000000 0x100000000 0x20 0x10>;
+ name = "vas";
+ ibm,vas-id = <0x1>;
+ };
diff --git a/dts/Bindings/powerpc/opal/sensor-groups.txt b/dts/Bindings/powerpc/opal/sensor-groups.txt
new file mode 100644
index 0000000..6ad881c
--- /dev/null
+++ b/dts/Bindings/powerpc/opal/sensor-groups.txt
@@ -0,0 +1,27 @@
+IBM OPAL Sensor Groups Binding
+-------------------------------
+
+Node: /ibm,opal/sensor-groups
+
+Description: Contains sensor groups available in the Powernv P9
+servers. Each child node indicates a sensor group.
+
+- comp