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| author | Michael Tretter <m.tretter@pengutronix.de> | 2018-12-07 11:11:56 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-10 10:13:30 +0100 |
| commit | 5ffc6f9210ffcffbd2fe494b5e8811eebad813a8 (patch) | |
| tree | 792201183c7bdab3825f55f0b7c67a9f3b4e3e61 /images/Makefile | |
| parent | be2ca38aaaac1739421588a71a6fc2c601bc7604 (diff) | |
| download | barebox-5ffc6f9210ffcffbd2fe494b5e8811eebad813a8.tar.gz barebox-5ffc6f9210ffcffbd2fe494b5e8811eebad813a8.tar.xz | |
ARM: zynqmp: add support for Xilinx ZCU104 board
Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.
Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'images/Makefile')
| -rw-r--r-- | images/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/images/Makefile b/images/Makefile index 4c6d486f08..9aaf8af6ed 100644 --- a/images/Makefile +++ b/images/Makefile @@ -104,6 +104,7 @@ include $(srctree)/images/Makefile.socfpga include $(srctree)/images/Makefile.tegra include $(srctree)/images/Makefile.vexpress include $(srctree)/images/Makefile.at91 +include $(srctree)/images/Makefile.zynqmp targets += $(image-y) pbl.lds barebox.x barebox.z targets += $(patsubst %,%.pblb,$(pblb-y)) |