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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2017-04-28 16:41:41 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-05-03 13:51:22 +0200 |
| commit | d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa (patch) | |
| tree | a3dbd48b1feef91687bd75e9227870debbbbf9cb /images | |
| parent | db3feb61d19060a0589f3906a8a081bebd934ace (diff) | |
| download | barebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.gz barebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.xz | |
ARM: socfpga: add arria10 support
Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).
As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'images')
| -rw-r--r-- | images/Makefile.socfpga | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index 21804d93df..a764b1a5fe 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -4,8 +4,11 @@ # %.socfpgaimg - convert into socfpga image # ---------------------------------------------------------------- +SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += -v1 +SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += -v0 + quiet_cmd_socfpga_image = SOCFPGA-IMG $@ - cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $< + cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $(SOCFPGA_IMAGE_ARGS-y) $< $(obj)/%.socfpgaimg: $(obj)/% FORCE $(call if_changed,socfpga_image) |