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| author | Enrik Berkhan <Enrik.Berkhan@ge.com> | 2008-01-23 12:12:01 +0100 |
|---|---|---|
| committer | Wolfram Sang <w.sang@pengutronix.de> | 2008-01-23 12:13:23 +0100 |
| commit | 35fd1e8f5bc6270b884e7728ebf255254b565cc3 (patch) | |
| tree | fa5bc8083b20c5d8158cb536aca057a036efbb9e /include/configs/ipe337.h | |
| parent | 9f27a5f0683975a1adbd0563566152c8f22a44c7 (diff) | |
| download | barebox-35fd1e8f5bc6270b884e7728ebf255254b565cc3.tar.gz barebox-35fd1e8f5bc6270b884e7728ebf255254b565cc3.tar.xz | |
Fix/Adapt settings for version 2 of IPE337
Signed-Off-By: Enrik Berkhan <Enrik.Berkhan@ge.com>
Diffstat (limited to 'include/configs/ipe337.h')
| -rw-r--r-- | include/configs/ipe337.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/include/configs/ipe337.h b/include/configs/ipe337.h index 47e4c2c2e5..9ff6297e6b 100644 --- a/include/configs/ipe337.h +++ b/include/configs/ipe337.h @@ -11,7 +11,7 @@ */ /* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 +#define CONFIG_CLKIN_HZ 40000000 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ /* 1=CLKIN/2 */ #define CONFIG_CLKIN_HALF 0 @@ -20,19 +20,23 @@ #define CONFIG_PLL_BYPASS 0 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ /* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 24 +#define CONFIG_VCO_MULT 10 /* POR default */ /* CONFIG_CCLK_DIV controls what the core clock divider is */ /* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 +#define CONFIG_CCLK_DIV 1 /* POR default */ /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ /* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 9 +#define CONFIG_SCLK_DIV 5 /* POR default */ + +/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/ #define AMGCTLVAL 0x1F -#define AMBCTL0VAL 0x14407BB0 + +/* no need for speed, currently, leave at defaults */ +#define AMBCTL0VAL 0xFFC2FFC2 #define AMBCTL1VAL 0xFFC2FFC2 #define CONFIG_MEM_MT48LC16M16A2TG_75 1 -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ #define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ |