svn_rev_002

Consider all boards containing it's own flash.c as unmaintained
and remove them.

209 files changed, 0 insertions, 77303 deletions

diff --git a/include/configs/A3000.h b/include/configs/A3000.h
deleted file mode 100644
index ca9592c23b..0000000000
--- a/include/configs/A3000.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * (C) Copyright 2001, 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-/*
- * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
- * http://artismicro.com
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_A3000		1
-
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_BOOTDELAY	5
-
-#if 0
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-				  CFG_CMD_BEDBUG | \
-				  CFG_CMD_BSP    | \
-				  CFG_CMD_ELF    | \
-				  CFG_CMD_I2C 	 | \
-				  CFG_CMD_FLASH | \
-				  CFG_CMD_BEDBUG | \
-				  CFG_CMD_NET    | \
-				  CFG_CMD_PCI )
-#endif
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
-
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI      		/* include pci support          */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW    /* print pci devices @ startup  */
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
-
-/* #define CONFIG_TULIP */
-/* #define CONFIG_EEPRO100 */
-#define CONFIG_NATSEMI
-
-#define PCI_ENET0_IOADDR		0x80000000
-#define PCI_ENET0_MEMADDR		0x80000000
-#define PCI_ENET1_IOADDR		0x81000000
-#define PCI_ENET1_MEMADDR		0x81000000
-#define PCI_ENET2_IOADDR		0x82000000
-#define PCI_ENET2_MEMADDR		0x82000000
-#define PCI_ENET3_IOADDR		0x83000000
-#define PCI_ENET3_MEMADDR		0x83000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-
-#define CFG_FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  			CFG_FLASH_BASE0_PRELIM
-#define CFG_FLASH_BANKS			{ CFG_FLASH_BASE0_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		get_bus_freq(0)
-
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CFG_MONITOR_BASE        TEXT_BASE */
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CFG_HZ		     1000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    7
-#define CFG_ROMFAL	    11
-#define CFG_DBUS_SIZE       0x3
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    121
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    8	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_ACTORW	    3		/* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
-
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	    1
-#define CFG_ENV_ADDR		0xFFFE0000
-#define CFG_ENV_SIZE		0x00020000 /* Size of the Environment		*/
-#define CFG_ENV_SECT_SIZE	0x00020000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
deleted file mode 100644
index 821efe5d48..0000000000
--- a/include/configs/ADCIOP.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
-#define CONFIG_ADCIOP		1	/* ...on a ADCIOP board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK		66
-#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_IPADDR		10.0.18.222
-#define CONFIG_SERVERIP		10.0.18.190
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_ASKENV	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0x10000000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_ENV_SIZE		0x0400		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
-
-#else /* Use FLASH for environment variables */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-#define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
-
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI			/* include pci support			*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
-
-#define CONFIG_TULIP
-
-#define CFG_ETH_DEV_FN	     0x0000
-#define CFG_ETH_IOBASE	     0x0fff0000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		2048	/* For PLX IOP480			*/
-#define CFG_CACHELINE_SIZE	16	/* For AMCC 401/403 CPUs		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFE00000	/* FLASH bank #1	*/
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
deleted file mode 100644
index 2efca1056e..0000000000
--- a/include/configs/ADNPESC1.h
+++ /dev/null
@@ -1,694 +0,0 @@
-/*
- * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************************
- * Include the whole NIOS CPU configuration.
- *
- * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
- *
- ***********************************************************************/
-
-#if	defined(CONFIG_NIOS_BASE_32)
-#include <configs/ADNPESC1_base_32.h>
-#else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
-#endif
-
-/*------------------------------------------------------------------------
- * BOARD/CPU -- TOP-LEVEL
- *----------------------------------------------------------------------*/
-#define CONFIG_NIOS		1		/* NIOS-32 core		*/
-#define	CONFIG_ADNPESC1		1		/* SSV ADNP/ESC1 board	*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
-#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
-
-/*------------------------------------------------------------------------
- * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
-
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
-
-#else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
-#endif
-
-#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
-
-#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
-
-#else
-
-#undef	CFG_SRAM_BASE
-#undef	CFG_SRAM_SIZE
-
-#endif
-
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION - For the most part, you can put things pretty
- * much anywhere. This is pretty flexible for Nios. So here we make some
- * arbitrary choices & assume that the monitor is placed at the end of
- * a memory resource (so you must make sure TEXT_BASE is chosen
- * appropriately -- this is very important if you plan to move your
- * memory to another place as configured at this time !!!).
- *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size	*/
-
-#else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-
-/* Mem addr of environment */
-#if	defined(CONFIG_NIOS_BASE_32)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-#else
-#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
-#endif
-
-#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
-
-#else
-#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
-#endif
-
-/*------------------------------------------------------------------------
- * NIOS APPLICATION CODE BASE AREA
- *----------------------------------------------------------------------*/
-#if	((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
-#define	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"0x2000100"
-#define CFG_ADNPESC1_NIOS_APPL_ENTRY	"0x1050000"
-#define CFG_ADNPESC1_NIOS_APPL_IDENT	"0x105000c"
-#define	CFG_ADNPESC1_NIOS_APPL_END	"0x11fffff"
-#define CFG_ADNPESC1_FILESYSTEM_BASE	"0x1200000"
-#define	CFG_ADNPESC1_FILESYSTEM_END	"0x17fffff"
-#else
-#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
-#endif
-#define CFG_ADNPESC1_NIOS_IDENTIFIER	"Nios"
-
-/*------------------------------------------------------------------------
- * BOOT ENVIRONMENT
- *----------------------------------------------------------------------*/
-#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_ADNPESC1_SLED_BOOT_OFF	"sled boot off; "
-#define	CFG_ADNPESC1_SLED_RED_BLINK	"sled red blink; "
-#else
-#define	CFG_ADNPESC1_SLED_BOOT_OFF
-#define	CFG_ADNPESC1_SLED_RED_BLINK
-#endif
-
-#define	CONFIG_BOOTDELAY	5
-#define	CONFIG_BOOTCOMMAND						\
-	"if itest.s *$appl_ident_addr == \"$appl_ident_str\"; "		\
-	"then "								\
-		"wd off; "						\
-		CFG_ADNPESC1_SLED_BOOT_OFF				\
-		"go $appl_entry_addr; "					\
-	"else "								\
-		CFG_ADNPESC1_SLED_RED_BLINK				\
-		"echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
-		"echo *** invalid application at $appl_entry_addr; "	\
-		"echo *** stop bootup...; "				\
-	"fi"
-
-/*------------------------------------------------------------------------
- * EXTRA ENVIRONMENT
- *----------------------------------------------------------------------*/
-#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_ADNPESC1_SLED_YELLO_ON	"sled yellow on; "
-#define	CFG_ADNPESC1_SLED_YELLO_OFF	"sled yellow off; "
-#else
-#define	CFG_ADNPESC1_SLED_YELLO_ON
-#define	CFG_ADNPESC1_SLED_YELLO_OFF
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"update_allowed=0\0"						\
-	"update_load_addr="	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"\0"	\
-	"appl_entry_addr="	CFG_ADNPESC1_NIOS_APPL_ENTRY	"\0"	\
-	"appl_end_addr="	CFG_ADNPESC1_NIOS_APPL_END	"\0"	\
-	"appl_ident_addr="	CFG_ADNPESC1_NIOS_APPL_IDENT	"\0"	\
-	"appl_ident_str="	CFG_ADNPESC1_NIOS_IDENTIFIER	"\0"	\
-	"appl_name=ADNPESC1/base32/linux.bin\0"				\
-	"appl_update="							\
-		"if itest.b $update_allowed != 0; "			\
-		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
-			"tftp $update_load_addr $appl_name; "		\
-			"protect off $appl_entry_addr $appl_end_addr; "	\
-			"era $appl_entry_addr $appl_end_addr; "		\
-			"cp.b $update_load_addr $appl_entry_addr $filesize; "\
-			CFG_ADNPESC1_SLED_YELLO_OFF			\
-		"else "							\
-			"echo *** update not allowed (update_allowed=$update_allowed); "\
-		"fi\0"							\
-	"fs_base_addr="		CFG_ADNPESC1_FILESYSTEM_BASE	"\0"	\
-	"fs_end_addr="		CFG_ADNPESC1_FILESYSTEM_END	"\0"	\
-	"fs_name=ADNPESC1/base32/romfs.img\0"				\
-	"fs_update="							\
-		"if itest.b $update_allowed != 0; "			\
-		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
-			"tftp $update_load_addr $fs_name; "		\
-			"protect off $fs_base_addr $fs_end_addr; "	\
-			"era $fs_base_addr $fs_end_addr; "		\
-			"cp.b $update_load_addr $fs_base_addr $filesize; "\
-			CFG_ADNPESC1_SLED_YELLO_OFF			\
-		"else "							\
-			"echo *** update not allowed (update_allowed=$update_allowed); "\
-		"fi\0"							\
-	"uboot_name=ADNPESC1/base32/u-boot.bin\0"			\
-	"uboot_loadnrun="						\
-		"if ping $serverip; "					\
-		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
-			"tftp $update_load_addr $uboot_name; "		\
-			"wd off; "					\
-			"go $update_load_addr; "			\
-		"else "							\
-			"echo *** missing connection to $serverip; "	\
-			"echo *** check your network and try again...; "\
-		"fi\0"
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
-
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
-
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
-#else
-#undef	CFG_NIOS_FIXEDBAUD
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
- * so an avalon bus timer is required.
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
-
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
-#endif
-
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
-#endif
-
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
-
-#else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * WATCHDOG (or better MAX823 supervisory circuite access)
- *----------------------------------------------------------------------*/
-#define	CONFIG_HW_WATCHDOG	1		/* board specific WD	*/
-
-#ifdef	CONFIG_HW_WATCHDOG
-
-/* MAX823 supervisor -- watchdog enable port at: */
-#if	(CFG_NIOS_CPU_WDENA_PIO == 0)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 1)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 2)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 3)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 4)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 5)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 6)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 7)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 8)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 9)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
-#else
-#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
-#endif
-
-/* MAX823 supervisor -- watchdog trigger port at: */
-#if	(CFG_NIOS_CPU_WDTOG_PIO == 0)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 1)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 2)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 3)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 4)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 5)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 6)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 7)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 8)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 9)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
-#else
-#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
-#endif
-
-#if	defined(CONFIG_NIOS_BASE_32)		/* NIOS CPU specifics	*/
-#define	CONFIG_HW_WDENA_BIT		0	/* WD enable  @ Bit 0	*/
-#define	CONFIG_HW_WDTOG_BIT		0	/* WD trigger @ Bit 0	*/
-#define	CONFIG_HW_WDPORT_WRONLY	1	/* each WD port wr/only*/
-#else
-#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
-#endif
-
-#endif	/* CONFIG_HW_WATCHDOG */
-
-/*------------------------------------------------------------------------
- * SERIAL PERIPHAREL INTERFACE
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SPI_NUMS == 1)
-
-#define	CONFIG_NIOS_SPI		1		/* SPI support active	*/
-#define	CFG_NIOS_SPIBASE	CFG_NIOS_CPU_SPI0
-#define	CFG_NIOS_SPIBITS	CFG_NIOS_CPU_SPI0_BITS
-
-#define	CONFIG_RTC_DS1306	1	/* Dallas 1306 real time clock	*/
-#define CFG_SPI_RTC_DEVID	0	/*        as 1st SPI device	*/
-
-#define	__SPI_CMD_OFF		0	/* allow default commands:	*/
-					/*	CFG_CMD_SPI		*/
-					/*	CFG_CMD_DATE		*/
-
-#else
-#undef	CONFIG_NIOS_SPI				/* NO SPI support	*/
-#define	__SPI_CMD_OFF	(	CFG_CMD_SPI	\
-			|	CFG_CMD_DATE	\
-			)
-#endif
-
-/*------------------------------------------------------------------------
- * Ethernet -- needs work!
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
-
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
-
-#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#define	CONFIG_SMC_USE_32_BIT	1
-#else	/* no */
-#undef	CONFIG_SMC_USE_32_BIT
-#endif
-
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
-
-	/********************************************/
-	/* !!! CS8900 is __not__ tested on NIOS !!! */
-	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
-#else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
-#endif
-
-#else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
-#endif
-
-#define CONFIG_ETHADDR		02:80:ae:20:60:6f
-#define CONFIG_NETMASK		255.255.255.248
-#define CONFIG_IPADDR		192.168.161.84
-#define CONFIG_SERVERIP		192.168.161.85
-
-#else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
-#endif
-
-/*------------------------------------------------------------------------
- * STATUS LEDs
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
-
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
-
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO0
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO0_BITS
-#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO0_TYPE == 1)
-#define	STATUS_LED_WRONLY		1
-#else
-#undef	STATUS_LED_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
-
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO1
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO1_BITS
-#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO1_TYPE == 1)
-#define	STATUS_LED_WRONLY		1
-#else
-#undef	STATUS_LED_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
-
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
-#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
-#define	STATUS_LED_WRONLY		1
-#else
-#undef	STATUS_LED_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
-
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
-
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
-
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
-
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
-
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
-
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
-
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
-
-#else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
-#endif
-
-#define	CONFIG_STATUS_LED		1 /* enable status led driver */
-
-#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
-#define	STATUS_LED_STATE		STATUS_LED_BLINKING
-#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 2)	/* ca. 1 Hz */
-#define	STATUS_LED_BOOT			0		/* boot LED */
-
-#if	(STATUS_LED_BITS > 1)
-#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
-#define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 10)	/* ca. 5 Hz */
-#define	STATUS_LED_RED			1		/* fail LED */
-#endif
-
-#if	(STATUS_LED_BITS > 2)
-#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
-#define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 2)	/* ca. 1 Hz */
-#define	STATUS_LED_YELLOW		2		/* info LED */
-#endif
-
-#if	(STATUS_LED_BITS > 3)
-#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
-#define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 2)	/* ca. 1 Hz */
-#define	STATUS_LED_GREEN		3		/* info LED */
-#endif
-
-#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
-
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
-
-/*------------------------------------------------------------------------
- * Diagnostics / Power On Self Tests
- *----------------------------------------------------------------------*/
-#define	CONFIG_POST			CFG_POST_RTC
-#define	CFG_NIOS_POST_WORD_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_CMD_ASKENV | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_BMP	| \
-				 CFG_CMD_CACHE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_DTT	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_ELF    | \
-				 CFG_CMD_FAT	| \
-				 CFG_CMD_FDC	| \
-				 CFG_CMD_FDOS	| \
-				 CFG_CMD_HWFLOW	| \
-				 CFG_CMD_IDE	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_JFFS2	| \
-				 CFG_CMD_KGDB	| \
-				 CFG_CMD_NAND	| \
-				 CFG_CMD_NFS	| \
-				 CFG_CMD_MMC	| \
-				 CFG_CMD_MII	| \
-				 CFG_CMD_PCI	| \
-				 CFG_CMD_PCMCIA | \
-				 CFG_CMD_SCSI	| \
-				 CFG_CMD_VFD	| \
-				 CFG_CMD_USB	| \
-				 CFG_CMD_XIMG	| \
-				 __SPI_CMD_OFF	) )
-
-
-#include <cmd_confdefs.h>
-
-/*------------------------------------------------------------------------
- * KGDB
- *----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	9600
-#endif
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_HUSH_PARSER		1	    /* use "hush" command parser
-					       undef to save memory	*/
-#define	CFG_PROMPT		"ADNPESC1 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		64	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
-
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"[]> "
-#endif
-
-/* Default load address	*/
-#if	(CFG_SRAM_SIZE != 0)
-
-/* default in SRAM */
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
-
-#elif	(CFG_SDRAM_SIZE != 0)
-
-/* default in SDRAM */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#if 1
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
-#else
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x400000)
-#endif
-#else
-#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
-#endif
-
-#else
-#undef	CFG_LOAD_ADDR		/* force error break */
-#endif
-
-
-/* MEM test area */
-#if	(CFG_SDRAM_SIZE != 0)
-
-/* SDRAM begin to stack area (1MB stack) */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#if 0
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
-#else
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x400000)
-#endif
-#else
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
-#endif
-
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
-
-#else
-#undef	CFG_MEMTEST_START	/* force error break */
-#undef	CFG_MEMTEST_END
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h
deleted file mode 100644
index 55210ebd3a..0000000000
--- a/include/configs/ADNPESC1_base_32.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_ADNPESC1_BASE_32_H
-#define __CONFIG_ADNPESC1_BASE_32_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/ADNPESC1.h)
- *
- * Here we must define CPU dependencies. Any unsupported option have to
- * be undefined or defined with zero, example CPU without data cache / OCI:
- *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#undef	CFG_NIOS_CPU_OCI_BASE
- *	#undef	CFG_NIOS_CPU_OCI_SIZE
- */
-
-/* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x03000000	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x02000000	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
-						/*		yes(1)	*/
-
-/* The offset address in flash to check for the Nios signature "Ni".
- * (see GM_FlashExec in germs_monitor.s) */
-#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
-
-/* on-chip extensions */
-#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
-#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
-
-#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
-
-#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
-#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
-
-/* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
-
-#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-/* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	1		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-#define	CFG_NIOS_CPU_UART1	0x00000820	/* UART1	addr	*/
-#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-/* serial peripheral i/o */
-#define	CFG_NIOS_CPU_SPI_NUMS	1		/* number of spis	*/
-
-#define	CFG_NIOS_CPU_SPI0	0x000008c0	/* SPI0		addr	*/
-#define	CFG_NIOS_CPU_SPI0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_SPI0_BITS	16		/*  data bit		*/
-#define	CFG_NIOS_CPU_SPI0_MA	1		/*  is master:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_SPI0_SLN	1		/*  num slaves		*/
-#define	CFG_NIOS_CPU_SPI0_TCLK	250000		/*  clock (Hz)		*/
-#define	CFG_NIOS_CPU_SPI0_TDELAY 2		/*  delay (usec)	*/
-#define	CFG_NIOS_CPU_SPI0_FB	0		/*  first bit	msb(0)	*/
-						/*		lsb(1)	*/
-
-/* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	14		/* number of parports	*/
-
-#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
-#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO2	0x00000880	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO4	0x000008a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO5	0x000008b0	/* PIO5		addr	*/
-#undef	CFG_NIOS_CPU_PIO5_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO6	0x00000900	/* PIO6		addr	*/
-#define	CFG_NIOS_CPU_PIO6_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO7	0x00000910	/* PIO7		addr	*/
-#define	CFG_NIOS_CPU_PIO7_IRQ	31		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO8	0x00000920	/* PIO8		addr	*/
-#define	CFG_NIOS_CPU_PIO8_IRQ	32		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO8_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO8_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO8_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO8_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO8_ITYPE	1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO9	0x00000930	/* PIO9		addr	*/
-#define	CFG_NIOS_CPU_PIO9_IRQ	33		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO9_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO9_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO9_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO9_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO9_ITYPE	1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO10	0x00000940	/* PIO10	addr	*/
-#define	CFG_NIOS_CPU_PIO10_IRQ	34		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO10_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO10_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO10_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO10_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO10_ITYPE 1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO11	0x00000950	/* PIO11	addr	*/
-#define	CFG_NIOS_CPU_PIO11_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO11_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO11_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO11_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO11_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO11_ITYPE 1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO12	0x00000960	/* PIO12	addr	*/
-#define	CFG_NIOS_CPU_PIO12_IRQ	36		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO12_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO12_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO12_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO12_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO12_ITYPE 1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO13	0x00000970	/* PIO113	addr	*/
-#define	CFG_NIOS_CPU_PIO13_IRQ	37		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO13_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO13_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO13_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO13_EDGE	2		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO13_ITYPE 1		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-/* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	2		/* number of IDE contr.	*/
-
-#define	CFG_NIOS_CPU_IDE0	0x00001000	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	36		/* 		IRQ	*/
-
-#define	CFG_NIOS_CPU_IDE1	0x00001020	/* IDE1		addr	*/
-#define	CFG_NIOS_CPU_IDE1_IRQ	37		/* 		IRQ	*/
-
-/* memory accessibility */
-#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
-#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
-
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x02000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_FLASH_BASE	0x01000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
-
-/* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
-
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	(0)		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	16		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
-						/*	cs8900(1)	*/
-						/* ex:	openmac(2)	*/
-						/* ex:	alteramac(3)	*/
-
-/* external extension */
-#define	CFG_NIOS_CPU_CS0_BASE	0x40000000	/* board EXT0	addr	*/
-#define	CFG_NIOS_CPU_CS0_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_CS1_BASE	0x41000000	/* board EXT1	addr	*/
-#define	CFG_NIOS_CPU_CS1_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_CS2_BASE	0x42000000	/* board EXT2	addr	*/
-#define	CFG_NIOS_CPU_CS2_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_CS3_BASE	0x43000000	/* board EXT3	addr	*/
-#define	CFG_NIOS_CPU_CS3_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
-
-/* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
-#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
-
-#define	CFG_NIOS_CPU_PORTA_PIO		0	/* PIO0: Port A		*/
-#define	CFG_NIOS_CPU_PORTB_PIO		1	/* PIO1: Port D		*/
-#define	CFG_NIOS_CPU_PORTC_PIO		2	/* PIO2: Port C		*/
-#define	CFG_NIOS_CPU_RCM_PIO		3	/* PIO3: RCM jumper	*/
-#define	CFG_NIOS_CPU_WDENA_PIO		4	/* PIO4: watchdog enable*/
-#define	CFG_NIOS_CPU_WDTOG_PIO		5	/* PIO5: watchdog trigg.*/
-
-/* PIOx: LED bar */
-#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_NIOS_CPU_LED_PIO		CFG_NIOS_CPU_PORTA_PIO
-#else
-#undef	CFG_NIOS_CPU_LED_PIO			/* no LED bar		*/
-#endif
-
-#endif	/* __CONFIG_ADNPESC1_BASE_32_H */
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
deleted file mode 100644
index 14d56bfd97..0000000000
--- a/include/configs/AMX860.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1
-#define CONFIG_AMX860		1
-
-#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SCC2		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#define	CONFIG_8xx_CONS_SCC2	1
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#define MPC8XX_FACT		10		/* Multiply by 10	*/
-#define MPC8XX_XIN		5000000			/* 5 MHz in	*/
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"				/* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-#endif
-
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	 	0x00100000
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR			0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * U-Boot for AMX board supports two types of memory extension
- * modules: one that provides 4 MB flash memory, and another one with
- * 16 MB EDO DRAM.
- *
- * The flash module swaps the CS0 and CS1 signals: if the module is
- * installed, CS0 is connected to Flash on the module and CS1 is
- * connected to the on-board Flash. This means that you must intall
- * U-Boot when the Flash module is plugged in, if you plan to use
- * it.
- *
- * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
- * must be defined. The DRAM module uses CS1.
- *
- * Only one of these modules may be installed at a time. If U-Boot
- * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
- * work if the Flash extension module is installed instead of the
- * DRAM module.
- */
-#define CONFIG_AMX_RAM_EXT	/* 16Mb Ext. DRAM module support */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- *
- * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
- * (CONFIG_AMX_RAM_EXT)
- */
-#ifdef CONFIG_AMX_RAM_EXT
-# define	CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
-#else
-# define	CFG_BOOTMAPSZ	(4 << 20)	/* Initial Memory map for Linux	*/
-#endif
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
-
-#define CFG_DER		0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#ifndef CONFIG_AMX_RAM_EXT
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
-#endif
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-/*				 0x00000800	0x00000400 0x00000100 0x00000030     0x00000004 */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-
-#define CFG_OR0_PRELIM	0xFFC00954	/* Real values for the board */
-#define CFG_BR0_PRELIM	0x40000001	/* Real values for the board */
-
-#ifndef CONFIG_AMX_RAM_EXT
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xFFC00954	/* Real values for the board */
-#define CFG_BR1_PRELIM	0x60000001	/* Real values for the board */
-#endif
-
-/* DSP ("Glue") Xilinx */
-#define CFG_OR6_PRELIM	0xFFFF8000	/* 32kB, 15 waits, cs after addr, no bursts */
-#define CFG_BR6_PRELIM	0x60000401	/* use GPCM for CS generation, 8 bit port */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
deleted file mode 100644
index ba4b1a2bc8..0000000000
--- a/include/configs/AP1000.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * AMIRIX.h: AMIRIX specific config options
- *
- * Author : Frank Smith (smith at amirix dot com)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#undef DEBUG
-
-#define CONFIG_405	1		/* This is a PPC405 CPU	    */
-#define CONFIG_4xx	1		/* ...member of PPC4xx family	*/
-
-#define CONFIG_AP1000	1		/* ...on an AP1000 board    */
-
-#define CONFIG_PCI	1
-
-#define CFG_HUSH_PARSER 1		/* use "hush" command parser	*/
-#define CFG_PROMPT		"0> "
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#define CONFIG_COMMAND_EDIT	1
-#define CONFIG_COMMAND_HISTORY	1
-#define CONFIG_COMPLETE_ADDRESSES 1
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_FLASH_USE_BUFFER_WRITE
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
-
-#define CONFIG_BOOTCOMMAND	""	/* autoboot command */
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-
-#define CONFIG_BOOTARGS		"console=ttyS0,57600"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MVENV	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	\
-			       )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled	    */
-
-#define CONFIG_SYS_CLK_FREQ	30000000
-
-#define CONFIG_SPD_EEPROM	1	/* use SPD EEPROM for setup    */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
-#define CFG_PBSIZE	(CFG_CBSIZE+4+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_ALT_MEMTEST		1
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01000000	/* 4 ... 16 MB in DRAM	*/
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-
-#define CFG_NS16550_CLK		40000000
-#define CFG_DUART_CHAN		0
-#define CFG_NS16550_COM1	(0x4C000000 + 0x1000)
-#define CFG_NS16550_COM2	(0x4C800000 + 0x1000)
-#define CFG_NS16550_REG_SIZE	4
-#define CFG_NS16550		1
-#define CFG_INIT_CHAN1		1
-#define CFG_INIT_CHAN2		0
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x00200000	/* default load address */
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x20000000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_FLASH_CFI		1
-#define CFG_PROGFLASH_BASE	CFG_FLASH_BASE
-#define CFG_CONFFLASH_BASE	0x24000000
-
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection	    */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x00040000 /* Offset of Environment Sector	*/
-#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE	0x20000 /* see README - env sector total size	*/
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars */
-#define CFG_ENV_ADDR	    \
-    (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR	0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CFG_INIT_RAM_ADDR	0x400000  /* inside of SDRAM			 */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS	0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* JFFS2 stuff */
-
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-#define CFG_JFFS2_FIRST_SECTOR	1
-
-#define CONFIG_NET_MULTI
-#define CONFIG_E1000
-
-#define CFG_ETH_DEV_FN		0x0800
-#define CFG_ETH_IOBASE		0x31000000
-#define CFG_ETH_MEMBASE		0x32000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
deleted file mode 100644
index 3df99a008b..0000000000
--- a/include/configs/APC405.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_APCG405		1	/* ...on a APC405 board 	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
-
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
-
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#if 1 /* test-only */
-#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
-#else
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#endif
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFF80000
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
-
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
-
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's   */
-					/* have only 8kB, 16kB is save here     */
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
-#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART0_BA       0xF0000400          /* DUART Base Address               */
-#define DUART1_BA       0xF0000408          /* DUART Base Address               */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
-#define PS2_BA          0xF0000600          /* PS/2 Base Address                */
-#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
-#define FPGA_BA         0xF0100100          /* FPGA internal Base Address       */
-#define FUJI_BA         0xF0100200          /* Fuji internal Base Address       */
-#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address       */
-#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address       */
-#define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
-
-#define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address       */
-
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP   0x92015480
-#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
-#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
-#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
-#define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 5 (Epson VGA) initialization                                     */
-#define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
-#define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-/* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x008
-#define CFG_FPGA_CTRL2          0x00a
-
-/* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET  0x0001
-#define CFG_FPGA_CTRL_WDI       0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
-#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
-
-#define CONFIG_LCD_BIG          2           /* Epson S1D13806 used              */
-
-/* Image information... */
-#define CONFIG_LCD_USED         CONFIG_LCD_BIG
-#define CFG_LCD_HEADER_NAME     "../common/s1d13806_640_480_16bpp.h"
-#define CFG_LCD_LOGO_NAME       "logo_640_480_24bpp.c"
-
-#define CFG_LCD_MEM             CFG_LCD_BIG_MEM
-#define CFG_LCD_REG             CFG_LCD_BIG_REG
-
-#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
deleted file mode 100644
index 1cd0280e21..0000000000
--- a/include/configs/AR405.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_AR405		1	/* ...on a AR405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootm fff00000" /* autoboot command	*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-#endif
-
-#if 0
-#define CONFIG_BOOTARGS		"root=/dev/nfs "			\
-    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "	\
-    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS		"root=/dev/hda1 "			\
-    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
-#endif
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_BSP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xfff00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0xFFFB0000	/* Address of Environment Sector*/
-#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-#define CFG_ENV_SIZE		0x04000	        /* Size of Environment 	        */
-
-#define CFG_ENV_ADDR_REDUND     0xFFFA0000
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
-#define CFG_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Expension Bus) initialization					*/
-#define CFG_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (16552) initialization						*/
-#define CFG_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 4 (FPGA regs) initialization					*/
-#define CFG_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
-
-/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
-#define CFG_EBC_PB5AP		0x92015480
-#define CFG_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
deleted file mode 100644
index d03c05bf34..0000000000
--- a/include/configs/ASH405.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
-#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
-#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
-#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define CFG_NAND_BASE	0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
deleted file mode 100644
index c08b2c39f8..0000000000
--- a/include/configs/Alaska8220.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220		1
-#define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
-   determine the CPU speed. */
-#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	*/
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE	1
-*/
-
-#define CONFIG_EXTUART_CONSOLE	1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-#   define CONFIG_CONS_INDEX	1
-#   define CFG_NS16550_SERIAL
-#   define CFG_NS16550
-#   define CFG_NS16550_REG_SIZE 1
-#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
-#   define CFG_NS16550_CLK	18432000
-#endif
-
-#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BOOTD	| \
-				CFG_CMD_CACHE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_NET_MULTI
-#define CONFIG_MII
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR		192.162.1.2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.162.1.1
-#define CONFIG_GATEWAYIP	192.162.1.1
-#define CONFIG_HOSTNAME		Alaska
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CFG_I2C_MODULE		1
-
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
-/*
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		256
-*/
-
-/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
-   else undefined it will boot from Intel Strata flash */
-#define CFG_AMD_BOOT		1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CFG_AMD_BOOT)
-#define CFG_CS0_BASE		0xfff0
-#define CFG_CS0_MASK		0x00080000  /* 512 KB */
-#define CFG_CS0_CTRL		0x003f0d40
-
-#define CFG_CS1_BASE		0xfe00
-#define CFG_CS1_MASK		0x01000000  /* 16 MB */
-#define CFG_CS1_CTRL		0x003f1540
-#else
-#define CFG_CS0_BASE		0xff00
-#define CFG_CS0_MASK		0x01000000  /* 16 MB */
-#define CFG_CS0_CTRL		0x003f1540
-
-#define CFG_CS1_BASE		0xfe08
-#define CFG_CS1_MASK		0x00080000  /* 512 KB */
-#define CFG_CS1_CTRL		0x003f0d40
-#endif
-
-#define CFG_CS2_BASE		0xf100
-#define CFG_CS2_MASK		0x00040000
-#define CFG_CS2_CTRL		0x003f1140
-
-#define CFG_CS3_BASE		0xf200
-#define CFG_CS3_MASK		0x00040000
-#define CFG_CS3_CTRL		0x003f1100
-
-
-#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
-
-#if defined (CFG_AMD_BOOT)
-#define CFG_AMD_BASE		CFG_FLASH0_BASE
-#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
-#define CFG_FLASH_BASE		CFG_AMD_BASE
-#else
-#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
-#define CFG_AMD_BASE		CFG_FLASH1_BASE
-#define CFG_FLASH_BASE		CFG_INTEL_BASE
-#endif
-
-#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
-#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
-
-
-#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
-
-#define CFG_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#if defined (CFG_AMD_BOOT)
-#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
-#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CFG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
-#define CFG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#else
-#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CFG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
-#define CFG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CFG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
-#define CFG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE	1
-
-#if defined CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_EEPROM
-#elif defined CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_EEPROM
-#elif defined CFG_ENV_IS_IN_EEPROM
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
-#define CFG_SRAM_SIZE		0x8000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS		2
-#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CFG_SDRAM_SPD_SIZE		0x40
-#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
-					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
-					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
-					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC	1
-#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR		0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			    /* undef to save memory	*/
-#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	    /* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
-
-#define CFG_LOAD_ADDR		0x100000    /* default load address */
-
-#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-/*
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0x00400000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-*/
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=alaska-0"
-#define MTDPARTS_DEFAULT	"mtdparts=alaska-0:4m(user)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
deleted file mode 100644
index ea50f41504..0000000000
--- a/include/configs/AmigaOneG3SE.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the AmigaOneG3SE board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_AMIGAONEG3SE	1
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_VERY_BIG_RAM	1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in Hz */
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=4096"
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_AMIGA_PARTITION
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_ASKENV | \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DHCP	| \
-				 CFG_CMD_ELF	| \
-				 CFG_CMD_NET	| \
-				 CFG_CMD_IDE	| \
-				 CFG_CMD_FDC	| \
-				 CFG_CMD_CACHE	| \
-				 CFG_CMD_CONSOLE| \
-				 CFG_CMD_USB	| \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_PCI	)
-
-/*				    CFG_CMD_MII	   | \ */
-
-#define CONFIG_PCI		1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"] "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-/* #undef CFG_HUSH_PARSER */
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define CFG_MAXARGS	64		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00500000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-#define CFG_FLASH_MAX_SIZE  0x00080000
-/* Maximum amount of RAM.
- */
-#define CFG_MAX_RAM_SIZE    0x80000000	/* 2G			*/
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (768 << 10) /* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (2500 << 10) /* Reserve 128 kB for malloc() */
-
-#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
-    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
-#define CFG_RAMBOOT
-#else
-#undef CFG_RAMBOOT
-#endif
-
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* Size in bytes reserved for initial data
- */
-/* HJF: used to be 0x400000 */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x8000
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_INIT_RAM_LOCK
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
-#define CFG_SCONSOLE_SIZE     0x0002000
-
-/* SDRAM 0 - 256MB
- */
-
-/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U*/
-
-#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-/* PCI Range
- */
-#define CFG_DBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-/* HJF:
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
-#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
-#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
-*/
-
-/* Init RAM in the CPU DCache (no backing memory)
- */
-#define CFG_DBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-/* This used to be commented out */
-#define CFG_IBAT2L	  CFG_DBAT2L
-/* This here too */
-#define CFG_IBAT2U	  CFG_DBAT2U
-
-
-/* I/O and PCI memory at 0xf0000000
- */
-#define CFG_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- */
-#define CFG_HZ		1000
-#define CFG_BUS_HZ	133000000 /* bus speed - 100 mhz		*/
-#define CFG_CPU_CLK	133000000
-#define CFG_BUS_CLK	133000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* Max number of sectors in one bank	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-/*
- * Environment is stored in NVRAM.
- */
-#define CFG_ENV_IS_IN_NVRAM	1
-#define CFG_ENV_ADDR		0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to
-					    * protect softex's settings for now.
-					    * Original 768 bytes where not enough.
-					    */
-#define CFG_ENV_SIZE		0x8000	   /* Size of the Environment. See comment above */
-
-#define CFG_CONSOLE_IS_IN_ENV	1 /* stdin/stdout/stderr are in environment */
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CONFIG_ENV_OVERWRITE 1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * L2 cache
- */
-#define CFG_L2
-#define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-/*-----------------------------------------------------------------------
- * IDE ATAPI Configuration
- */
-
-#define CONFIG_ATAPI		1
-#define CFG_IDE_MAXBUS		2
-#define CFG_IDE_MAXDEVICE	4
-#define CONFIG_ISO_PARTITION	1
-
-#define CFG_ATA_BASE_ADDR	0xFE000000  /* was: via_get_base_addr() */
-#define CFG_ATA_IDE0_OFFSET	0x1F0
-#define CFG_ATA_IDE1_OFFSET	0x170
-
-#define CFG_ATA_REG_OFFSET	0
-#define CFG_ATA_DATA_OFFSET	0
-#define CFG_ATA_ALT_OFFSET	0x0200
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-
-#define CFG_DOC_SUPPORT_2000
-#undef CFG_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
-  RTC
-*/
-#define CONFIG_RTC_MC146818
-
-/*-----------------------------------------------------------------------
- * NS16550 Configuration
- */
-
-#define CFG_NS16550
-
-#define CFG_NS16550_COM1 0xFE0003F8
-#define CFG_NS16550_COM2 0xFE0002F8
-
-#define CFG_NS16550_REG_SIZE 1
-
-/* base address for ISA I/O
- */
-#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
-
-/* ISA Interrupt stuff (taken from JWL) */
-
-#define ISA_INT1_OCW1		0x21
-#define ISA_INT2_OCW1		0xA1
-#define ISA_INT1_OCW2		0x20
-#define ISA_INT2_OCW2		0xA0
-#define ISA_INT1_OCW3		0x20
-#define ISA_INT2_OCW3		0xA0
-
-#define ISA_INT1_ICW1		0x20
-#define ISA_INT2_ICW1		0xA0
-#define ISA_INT1_ICW2		0x21
-#define ISA_INT2_ICW2		0xA1
-#define ISA_INT1_ICW3		0x21
-#define ISA_INT2_ICW3		0xA1
-#define ISA_INT1_ICW4		0x21
-#define ISA_INT2_ICW4		0xA1
-
-
-/*
- * misc
- */
-
-#define CONFIG_NET_MULTI
-#define CFG_BOARD_ASM_INIT
-#define CONFIG_LAST_STAGE_INIT
-
-/* #define CONFIG_ETHADDR	00:09:D2:10:00:76 */
-/* #define CONFIG_IPADDR	192.168.0.2 */
-/* #define CONFIG_NETMASK	255.255.255.240 */
-/* #define CONFIG_GATEWAYIP	192.168.0.3 */
-
-#define CONFIG_3COM
-/* #define CONFIG_BOOTP_RANDOM_DELAY */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE)
-
-/*
- * USB configuration
- */
-#define CONFIG_USB_UHCI		1
-#define CONFIG_USB_STORAGE	1
-#define CONFIG_USB_KEYBOARD	1
-#define CFG_DEVICE_DEREGISTER	1 /* needed by CONFIG_USB_KEYBOARD */
-
-/*
- * Autoboot stuff
- */
-#define CONFIG_BOOTDELAY	5 /* Boot automatically after five seconds */
-#define CONFIG_PREBOOT		""
-#define CONFIG_BOOTCOMMAND	"fdcboot; diskboot"
-#define CONFIG_MENUPROMPT	"Press any key to interrupt autoboot: %2d "
-#define CONFIG_MENUKEY		' '
-#define CONFIG_MENUCOMMAND	"menu"
-/* #define CONFIG_AUTOBOOT_KEYED */
-
-/*
- * Extra ENV stuff
- */
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	"stdout=vga\0"				\
-	"stdin=ps2kbd\0"			\
-	"ide_doreset=on\0"			\
-	"ide_maxbus=2\0"			\
-	"ide_cd_timeout=30\0"			\
-	"menucmd=menu\0"			\
-	"pci_irqa=9\0"				\
-	"pci_irqa_select=edge\0"		\
-	"pci_irqb=10\0"				\
-	"pci_irqb_select=edge\0"		\
-	"pci_irqc=11\0"				\
-	"pci_irqc_select=edge\0"		\
-	"pci_irqd=7\0"				\
-	"pci_irqd_select=edge\0"
-
-
-/* #define CONFIG_MII		1 */
-/* #define CONFIG_BITBANGMII	1 */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/B2.h b/include/configs/B2.h
deleted file mode 100644
index e55858d34b..0000000000
--- a/include/configs/B2.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Configuation settings for the B2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7			1	/* This is a ARM7 CPU	*/
-#define CONFIG_B2			1	/* on an B2 Board      */
-#define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
-
-#define CONFIG_S3C44B0_CLOCK_SPEED	75 /* we have a 75Mhz S3C44B0*/
-
-
-#undef CONFIG_USE_IRQ			/* don't need them anymore */
-
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_ENV_SIZE		1024		/* 1024 bytes may be used for env vars*/
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024 )
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE		0x04000300 /* base address         */
-#define CONFIG_SMC_USE_32_BIT
-#undef  CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-								CFG_CMD_DATE | \
-								CFG_CMD_ELF	| \
-								CFG_CMD_EEPROM	| \
-								CFG_CMD_I2C	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_ETHADDR	00:50:c2:1e:af:fb
-#define CONFIG_BOOTARGS  "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
-							 ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
-#define CONFIG_NETMASK  255.255.0.0
-#define CONFIG_IPADDR   192.168.0.70
-#define CONFIG_SERVERIP	192.168.0.23
-#define CONFIG_BOOTFILE	"B2-rootfs/usr/B2-zImage.u-boot"
-#define CONFIG_BOOTCOMMAND	"bootm 20000 f0000"
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=>  "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0C400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x0c700000	/* default load address	*/
-
-#define	CFG_HZ				1000		/* 1 kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x0	/* environment starts at the beginning of the EEPROM */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (STM24C02W6) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0xFE
-
-#define CFG_I2C_EEPROM_ADDR	0xA8	/* EEPROM STM24C02W6		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/* Flash banks JFFS2 should use */
-/*
-#define CFG_JFFS2_FIRST_BANK    0
-#define CFG_JFFS2_FIRST_SECTOR	2
-#define CFG_JFFS2_NUM_BANKS     1
-*/
-
-/*
-	Linux TAGs (see lib_arm/armlinux.c)
-*/
-#define CONFIG_CMDLINE_TAG
-#undef CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
deleted file mode 100644
index 46bdfa2ee6..0000000000
--- a/include/configs/BAB7xx.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef  DEBUG
-#define GTREGREAD(x) 0xffffffff         /* needed for debug */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* these hardware addresses are pretty bogus, please change them to
-   suit your needs */
-
-/* first ethernet */
-#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
-
-#define CONFIG_IPADDR           192.168.0.105
-#define CONFIG_SERVERIP         192.168.0.100
-
-#define CONFIG_BAB7xx           1       /* this is an BAB740/BAB750 board */
-
-#define CONFIG_BAUDRATE         9600    /* console baudrate */
-
-#undef  CONFIG_WATCHDOG
-
-#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef  CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                  \
-    "bootp 1000000; "                                       \
-    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
-    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
-    "${netmask}:${hostname}:eth0:none; "                    \
-    "bootm"
-
-#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
-				 CFG_CMD_SCSI   | CFG_CMD_IDE | CFG_CMD_DATE  |\
-				 CFG_CMD_FDC    | CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP                    /* undef to save memory */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
-
-/*
- * choose between COM1 and COM2 as serial console
- */
-#define CONFIG_CONS_INDEX       1
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16          /* max number of command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
-#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
-
-#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
-
-#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define CFG_BOARD_ASM_INIT
-#define CONFIG_MISC_INIT_R
-
-/*
- * Choose the address mapping scheme for the MPC106 mem controller.
- * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
- */
-#define CFG_ADDRESS_MAP_A
-#ifdef  CFG_ADDRESS_MAP_A
-
-#define CFG_PCI_MEMORY_BUS      0x80000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
-
-#define CFG_PCI_MEM_BUS         0x00000000
-#define CFG_PCI_MEM_PHYS        0xc0000000
-#define CFG_PCI_MEM_SIZE        0x3f000000
-
-#define CFG_ISA_MEM_BUS         0
-#define CFG_ISA_MEM_PHYS        0
-#define CFG_ISA_MEM_SIZE        0
-
-#define CFG_PCI_IO_BUS          0x1000
-#define CFG_PCI_IO_PHYS         0x81000000
-#define CFG_PCI_IO_SIZE         0x01000000-CFG_PCI_IO_BUS
-
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0x80000000
-#define CFG_ISA_IO_SIZE         0x00800000
-
-#else
-
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
-
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7d000000
-
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xfd000000
-#define CFG_ISA_MEM_SIZE        0x01000000
-
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xfe800000
-#define CFG_PCI_IO_SIZE         0x00400000
-
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xfe000000
-#define CFG_ISA_IO_SIZE         0x00800000
-
-#endif /*CFG_ADDRESS_MAP_A */
-
-#define CFG_60X_PCI_MEM_OFFSET  0x00000000
-
-/* driver defines FDC,IDE,... */
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE          0x00000000
-#define CFG_FLASH_BASE          0xfff00000
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CFG_INIT_RAM_END        0x4000
-#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*
- * Flash mapping/organization on the MPC10x.
- */
-#define FLASH_BASE0_PRELIM      0xff800000
-#define FLASH_BASE1_PRELIM      0xffc00000
-
-#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
-#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=bab7xx-0"
-#define MTDPARTS_DEFAULT	"mtdparts=bab7xx-0:-(jffs2)"
-*/
-
-#define CFG_MONITOR_BASE        CFG_FLASH_BASE
-#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
-#undef  CFG_MEMTEST
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
-#define CFG_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
-#define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
-/*
- * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
- * user applications can use the remaining space for other purposes.
- */
-#define CFG_ENV_ADDR            (CFG_NVRAM_SIZE +0x10 -0x800)
-#define CFG_NV_SROM_COPY_ADDR   (CFG_NVRAM_SIZE +0x10 -0x400)
-#define CFG_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
-#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
-
-/*
- * Serial devices
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK         1843200
-#define CFG_NS16550_COM1        (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2        (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI                                /* include pci support */
-#define CONFIG_PCI_PNP                            /* pci plug-and-play */
-#define CONFIG_PCI_HOST         PCI_HOST_AUTO
-#undef  CONFIG_PCI_SCAN_SHOW
-
-/*
- * Video console (graphic: SMI LynxEM, keyboard: i8042)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_I8042_KBD
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_TIME
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_CONSOLE_CURSOR
-#define CFG_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
-
-/*
- * IDE/SCSI globals
- */
-#ifndef __ASSEMBLY__
-extern unsigned int    eltec_board;
-extern unsigned int    ata_reset_time;
-extern unsigned int    scsi_reset_time;
-extern unsigned short  scsi_dev_id;
-extern unsigned int    scsi_max_scsi_id;
-extern unsigned char   scsi_sym53c8xx_ccf;
-#endif
-
-/*
- * ATAPI Support (experimental)
- */
-#define CONFIG_ATAPI
-#define CFG_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
-#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR       CFG_60X_PCI_IO_OFFSET   /* base address */
-#define CFG_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
-#define CFG_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
-#define CFG_ATA_DATA_OFFSET     0                       /* data reg offset    */
-#define CFG_ATA_REG_OFFSET      0                       /* reg offset */
-#define CFG_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
-
-#define ATA_RESET_TIME          (ata_reset_time)
-
-#undef  CONFIG_IDE_PCMCIA                               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                                  /* no led for ide supported */
-
-/*
- * SCSI support (experimental) only SYM53C8xx supported
- */
-#define CONFIG_SCSI_SYM53C8XX
-#define CONFIG_SCSI_DEV_ID      (scsi_dev_id)           /* 875 or 860 */
-#define CFG_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
-#define CFG_SCSI_MAX_LUN        8                       /* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
-#define CFG_SCSI_MAX_DEVICE     (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
-#define CFG_SCSI_SPIN_UP_TIME   (scsi_reset_time)
-
-/*
- * Partion suppport
- */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * Winbond Configuration
- */
-#define CFG_WINBOND_83C553      1                       /* has a winbond bridge */
-#define CFG_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
-
-/*
- * NS87308 Configuration
- */
-#define CFG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
-#define CFG_NS87308_BADDR_10    1
-#define CFG_NS87308_DEVS        (CFG_NS87308_UART1   | \
-				 CFG_NS87308_UART2   | \
-				 CFG_NS87308_KBC1    | \
-				 CFG_NS87308_MOUSE   | \
-				 CFG_NS87308_FDC     | \
-				 CFG_NS87308_RARP    | \
-				 CFG_NS87308_GPIO    | \
-				 CFG_NS87308_POWRMAN | \
-				 CFG_NS87308_RTC_APC )
-
-#define CFG_NS87308_PS2MOD
-#define CFG_NS87308_GPIO_BASE   0x0220
-#define CFG_NS87308_PWMAN_BASE  0x0460
-#define CFG_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
-
-/*
- * set up the NVRAM access registers
- * NVRAM's controlled by the configurable CS line from the 87308
- */
-#define CFG_NS87308_CS0_BASE    0x0076
-#define CFG_NS87308_CS0_CONF    0x40
-#define CFG_NS87308_CS1_BASE    0x0070
-#define CFG_NS87308_CS1_CONF    0x1C
-#define CFG_NS87308_CS2_BASE    0x0071
-#define CFG_NS87308_CS2_CONF    0x1C
-
-#define CONFIG_RTC_MK48T59
-
-/*
- * Initial BATs
- */
-#if 1
-
-#define CFG_IBAT0L 0
-#define CFG_IBAT0U 0
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
-
-#define CFG_IBAT1L 0
-#define CFG_IBAT1U 0
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
-
-#define CFG_IBAT2L 0
-#define CFG_IBAT2U 0
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
-
-#define CFG_IBAT3L 0
-#define CFG_IBAT3U 0
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
-
-#else
-
-/* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
-
-/* address range for flashes */
-#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
-
-/* ISA IO space */
-#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
-
-/* ISA memory space */
-#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
-
-#endif
-
-/*
- * Speed settings are board specific
- */
-#ifndef __ASSEMBLY__
-extern  unsigned long           bab7xx_get_bus_freq (void);
-extern  unsigned long           bab7xx_get_gclk_freq (void);
-#endif
-#define CFG_BUS_HZ              bab7xx_get_bus_freq()
-#define CFG_BUS_CLK             CFG_BUS_HZ
-#define CFG_CPU_CLK             bab7xx_get_gclk_freq()
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
-#endif
-
-/*
- * L2 Cache Configuration is board specific for BAB740/BAB750
- * Init values read from revision srom.
- */
-#undef  CFG_L2
-#define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-		     L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
-#define L2_ENABLE   (L2_INIT | L2CR_L2E)
-
-#define CFG_L2_BAB7xx
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM           0x02    /* Software reboot */
-
-
-#define CONFIG_NET_MULTI                /* Multi ethernet cards support */
-#define CONFIG_TULIP
-#define CONFIG_TULIP_SELECT_MEDIA
-
-#endif    /* __CONFIG_H */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
deleted file mode 100644
index 3bd43d8369..0000000000
--- a/include/configs/BMW.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_BMW		1
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
-
-#define CONFIG_BCM570x		1	/* Use Broadcom BCM570x Ethernet Driver */
-#define	CONFIG_TIGON3		1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/
-
-#define CONFIG_BOOTCOMMAND	"bootm FF820000"	/* autoboot command	*/
-#define CONFIG_BOOTDELAY	5
-
-#define CFG_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
-#define DOC_PASSIVE_PROBE       1
-#define CFG_DOC_SUPPORT_2000    1
-#define CFG_DOC_SUPPORT_MILLENNIUM 1
-#define CFG_DOC_SHORT_TIMEOUT    1
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_ELF	| \
-				0 )
-
-/* CFG_CMD_DOC required legacy NAND support */
-#define CFG_NAND_LEGACY
-
-#if 0
-#define CONFIG_COMMANDS	        (CONFIG_CMD_DFL	| CFG_CMD_DHCP | \
-				 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
-#endif
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=>"	        /* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-
-#define CFG_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  CFG_MONITOR_BASE
-#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (2048 << 10) /* Reserve 2MB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 64 MB of (S)DRAM */
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
-#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CFG_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CFG_HZ		     1000
-
-#define CFG_ETH_DEV_FN	     0x7800
-#define CFG_ETH_IOBASE	     0x00104000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    0xf
-#define CFG_ROMFAL	    0x1f
-#define CFG_DBUS_SIZE       0x3
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    0		/* FIXME: was 192 */
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_SDMODE_BURSTLEN 3	    /* SDMODE Burst length */
-#define CFG_ACTORW	    0xa		/* FIXME was 2 */
-#define CFG_REGISTERD_TYPE_BUFFER 1
-
-#define CFG_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CONFIG_PCI              1 /* Include PCI support */
-#undef CONFIG_PCI_PNP
-
-/* PCI Memory space(s) */
-#define PCI_MEM_SPACE1_START	0x80000000
-#define PCI_MEM_SPACE2_START	0xfd000000
-
-/* ROM Spaces */
-#include "../board/bmw/bmw.h"
-
-/* BAT configuration */
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	0	/* Max number of flash banks	    */
-#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per  flash */
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-/*
- * Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CFG_ENV_IS_IN_NVRAM      1
-#define CONFIG_ENV_OVERWRITE     1
-#define CFG_NVRAM_ACCESS_ROUTINE 1
-#define CFG_ENV_ADDR		0x7c004000 /* right at the start of NVRAM  */
-#define CFG_ENV_SIZE		0x1ff0	/* Size of the Environment - 8K	   */
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning */
-
-/*
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value   */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot		    */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
deleted file mode 100644
index e0262a8f67..0000000000
--- a/include/configs/CANBT.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * (C) Copyright 2001
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CANBT		1	/* ...on a CANBT board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
-	"bootm ffe00000 ffe80000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
-
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|	\
-				CFG_CMD_IRQ	|	\
-				CFG_CMD_EEPROM	    ) & \
-			       ~CFG_CMD_NET)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFE0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use FLASH for environment variables */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (CAN/USB) initialization					*/
-#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
-#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (CAN Features) initialization					*/
-#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
deleted file mode 100644
index e8994ffef7..0000000000
--- a/include/configs/CCM.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * configuration options, board specific, for Siemens Card Controller Module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef	CCM_80MHz			/* define for 80 MHz CPU only */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860           1   /* This is a MPC860 CPU ... */
-#define CONFIG_CCM              1   /* on a Card Controller Module  */
-
-#define CONFIG_8xx_CONS_SMC1    1   /* Console is on SMC1       */
-#undef  CONFIG_8xx_CONS_SMC2
-#undef  CONFIG_8xx_CONS_NONE
-
-/*  ENVIRONMENT */
-
-#define CONFIG_BAUDRATE         19200         /* console baudrate in bps    */
-#define CONFIG_BOOTDELAY        2             /* autoboot after 2 seconds   */
-
-#define CONFIG_IPADDR           192.168.0.42
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_GATEWAYIP        0.0.0.0
-#define CONFIG_SERVERIP         192.168.0.254
-
-#define CONFIG_HOSTNAME         CCM
-
-#define CONFIG_LOADADDR         40180000
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND      "setenv bootargs " \
-				"mem=${mem} " \
-				"root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
-				"wt_8xx=timeout:3600; " \
-				"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
-
-#define	CONFIG_PRAM		512	/* reserve 512kB "protected RAM"*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define	CONFIG_SPI			/* enable SPI driver		*/
-#define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CFG_SPI_INIT_OFFSET		0xB00
-
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-byte page size	*/
-
-
-#define CONFIG_MAC_PARTITION		/* nod used yet			*/
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-/* Ethernet hardware configuration done using port pins */
-#define CFG_PA_ETH_RESET 	0x0200		/* PA  6	*/
-#define CFG_PA_ETH_MDDIS	0x4000		/* PA  1	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
-#define CFG_PB_ETH_CFG1		0x00000400	/* PB 21	*/
-#define CFG_PB_ETH_CFG2		0x00000200	/* PB 22	*/
-#define CFG_PB_ETH_CFG3		0x00000100	/* PB 23	*/
-
-/* Ethernet settings:
- * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CFG_ETH_MDDIS_VALUE	0
-#define CFG_ETH_CFG1_VALUE	1
-#define CFG_ETH_CFG2_VALUE	1
-#define CFG_ETH_CFG3_VALUE	1
-
-/* PUMA configuration */
-#define CFG_PC_PUMA_PROG	0x0200		/* PC  6        */
-#define CFG_PC_PUMA_DONE	0x0008		/* PC 12	*/
-#define CFG_PC_PUMA_INIT	0x0004		/* PC 13	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define	CFG_RESET_ADDRESS	0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#if 1
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		2048
-#define CFG_ENV_SIZE		2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-						  SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * we must activate GPL5 in the SIUMCR for CAN
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3 and OR3 (CAN Controller)
- */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
-					BR_PS_8 | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- *	BR4: 0x10100801		OR4: 0xffff8520
- * - "load" mode (chip select on UPM B):
- *	BR4: 0x101004c1		OR4: 0xffff8600
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE		0x10100000	/* PUMA Config */
-#define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */
-#define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_2_CLK)
-#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_2_CLK)
-
-#define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \
-					BR_PS_8  | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD	(PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- *	BR5: 0x10200401		OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE		0x10200000	/* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */
-#define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- *	BR6: 0x10600801		OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE		0x10600000	/* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */
-#define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-
-/*
- * BR7/OR7: PUMA: external Flash
- *	BR7: 0x10a00801		OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE		0x10A00000	/* PUMA external Flash */
-#define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
-#define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
deleted file mode 100644
index 1cca2859f4..0000000000
--- a/include/configs/CMS700.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CMS700.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_NET_MULTI	1
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-#undef  CONFIG_PRAM			/* no "protected RAM"           */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR	0x68
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#define CFG_EEPROM_WREN         1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-#define CFG_PLD_BASE            0xf0000000
-#define CFG_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
-
-#define CFG_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
-#define CFG_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
deleted file mode 100644
index b882f7a9bf..0000000000
--- a/include/configs/CPC45.h
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the CPC45 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_CPC45		1
-
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_FLASH	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#if 1
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-
-#define CFG_SDRAM_BASE		0x00000000
-
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_FLASH_BASE		0xFF000000
-#else
-#define CFG_FLASH_BASE		0xFF800000
-#endif
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#define CFG_EUMB_ADDR		0xFCE00000
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-/* Maximum amount of RAM.
- */
-#define CFG_MAX_RAM_SIZE	0x10000000
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* Size in bytes reserved for initial data
- */
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		get_bus_freq(0)
-
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-#define DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ	33000000
-#define CFG_HZ			1000
-
-
-/* Bit-field values for MCCR1.
- */
-#define CFG_ROMNAL		0
-#define CFG_ROMFAL		8
-
-#define CFG_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
-#define CFG_BANK1_ROW		0
-#define CFG_BANK2_ROW		0
-#define CFG_BANK3_ROW		0
-#define CFG_BANK4_ROW		0
-#define CFG_BANK5_ROW		0
-#define CFG_BANK6_ROW		0
-#define CFG_BANK7_ROW		0
-
-/* Bit-field values for MCCR2.
- */
-
-#define CFG_REFINT		0x2ec
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CFG_BSTOPRE		160
-
-/* Bit-field values for MCCR3.
- */
-#define CFG_REFREC		2	/* Refresh to activate interval		*/
-#define CFG_RDLAT		0	/* Data latancy from read command	*/
-
-/* Bit-field values for MCCR4.
- */
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
-#define CFG_ACTORW		2
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM		0
-#define CFG_REGDIMM		0
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x3ff00000
-#define CFG_BANK4_END		0x3fffffff
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x3ff00000
-#define CFG_BANK5_END		0x3fffffff
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x3ff00000
-#define CFG_BANK6_END		0x3fffffff
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x3ff00000
-#define CFG_BANK7_END		0x3fffffff
-#define CFG_BANK7_ENABLE	0
-
-#define CFG_ODCR		0xff
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
-#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-	/* Warining: environment is not EMBEDDED in the ppcboot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	    1
-
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
-#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
-#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-#define SRAM_BASE		0x80000000	/* SRAM base address	*/
-#define SRAM_END		0x801FFFFF
-
-/*----------------------------------------------------------------------*/
-/* CPC45 Memory Map							*/
-/*----------------------------------------------------------------------*/
-#define SRAM_BASE	0x80000000	/* SRAM base address		*/
-#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
-#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
-#define BCSR_BASE	0x80600000	/* board control / status registers */
-#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
-#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
-#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
-
-
-/*---------------------------------------------------------------------*/
-/* CPC45 Control/Status Registers				       */
-/*---------------------------------------------------------------------*/
-#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
-#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
-#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
-#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
-#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
-#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
-#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
-
-/* IRQ_ENA_1 bit definitions */
-#define I_ENA_1_IERA	0x80		/* INTA enable			*/
-#define I_ENA_1_IERB	0x40		/* INTB enable			*/
-#define I_ENA_1_IERC	0x20		/* INTC enable			*/
-#define I_ENA_1_IERD	0x10		/* INTD enable			*/
-
-/* IRQ_STAT_1 bit definitions */
-#define I_STAT_1_INTA	0x80		/* INTA status			*/
-#define I_STAT_1_INTB	0x40		/* INTB status			*/
-#define I_STAT_1_INTC	0x20		/* INTC status			*/
-#define I_STAT_1_INTD	0x10		/* INTD status			*/
-
-/* IRQ_ENA_2 bit definitions */
-#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
-#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
-#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
-#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
-#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
-#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
-#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
-#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
-
-/* IRQ_STAT_2 bit definitions */
-#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
-#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
-#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
-#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
-#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
-#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
-#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
-#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
-
-/* BOARD_CTRL bit definitions */
-#define USER_LEDS		2			/* 2 user LEDs	*/
-
-#if (USER_LEDS == 4)
-#define B_CTRL_WRSE		0x80
-#define B_CTRL_KRSE		0x40
-#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
-#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
-#define B_CTRL_LED3		0x08		/* LED 3 control		*/
-#define B_CTRL_LED2		0x04		/* LED 2 control		*/
-#define B_CTRL_LED1		0x02		/* LED 1 control		*/
-#define B_CTRL_LED0		0x01		/* LED 0 control		*/
-#else
-#define B_CTRL_WRSE		0x80
-#define B_CTRL_KRSE		0x40
-#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
-#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
-#define B_CTRL_LED1		0x08		/* LED 1 control		*/
-#define B_CTRL_LED0		0x04		/* LED 0 control		*/
-#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
-#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
-#endif
-
-/* BOARD_STAT bit definitions */
-#define B_STAT_WDGE		0x80
-#define B_STAT_WDGS		0x40
-#define B_STAT_WRST		0x20
-#define B_STAT_KRST		0x10
-#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
-#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
-#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
-#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
-
-/*---------------------------------------------------------------------*/
-/* Display addresses						       */
-/*---------------------------------------------------------------------*/
-#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
-#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
-#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */
-
-#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
-#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
-
-#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
-#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
-#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
-#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
-#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
-#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
-#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
-#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#undef	CONFIG_PCI_PNP
-#undef	CONFIG_PCI_SCAN_SHOW
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
-
-#define PCI_ENET0_IOADDR	0x82000000
-#define PCI_ENET0_MEMADDR	0x82000000
-#define PCI_PLX9030_IOADDR	0x82100000
-#define PCI_PLX9030_MEMADDR	0x82100000
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_I82365
-
-#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
-#define CFG_PCMCIA_MEM_SIZE	0x1000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
-#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)
-
-#define CONFIG_DOS_PARTITION
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
deleted file mode 100644
index 56fd9a6d35..0000000000
--- a/include/configs/CPCI2DP.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_COMMANDS	      ( (CONFIG_CMD_DFL	& ~CFG_CMD_NET) | \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
-#define CFG_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
-
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
-#define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#define CFG_EEPROM_WREN         1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PB0) initialization					*/
-#define CFG_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (PB1) initialization				*/
-#define CFG_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * GPIO definitions
- */
-#define CFG_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
-#define CFG_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
-#define CFG_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
-#define CFG_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
deleted file mode 100644
index 047e2f1eef..0000000000
--- a/include/configs/CPCI405.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM) initialization						*/
-#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 5 (Quart) initialization						*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#if 1 /* test-only */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#else
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#endif
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
deleted file mode 100644
index d756f447f7..0000000000
--- a/include/configs/CPCI4052.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
-#endif
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#if 0 /* test-only */
-#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition, use whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci4052-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci4052-0:-(jffs2)"
-*/
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-#endif
-
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
-
-/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
deleted file mode 100644
index 852d94a410..0000000000
--- a/include/configs/CPCI405AB.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
-#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci405ab-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci405ab-0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC32) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last 5 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC32 is 4096 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
-#define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
-#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
-#define CFG_FPGA_MODE_1WIRE         0x1000
-#define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
-#define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000
-
-/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_1WIRE   0x1000
-#define CFG_FPGA_STATUS_SIM_OK  0x2000
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
deleted file mode 100644
index 2260327c3f..0000000000
--- a/include/configs/CPCI405DT.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
-#endif
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/* Only interrupt boot if special string is typed */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
-#undef  CONFIG_AUTOBOOT_DELAY_STR
-#undef  CONFIG_AUTOBOOT_STOP_STR        /* defined via environment var  */
-#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci405dt-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci405dt-0:-(jffs2)"
-*/
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-#endif
-
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
-
-/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
deleted file mode 100644
index 90d3a8d8fa..0000000000
--- a/include/configs/CPCI440.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * board/config_CPCI440.h - configuration for esd CPCI-440 board
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_CPCI440		1	    /* Board is ebony		*/
-#define CONFIG_440GP		1	    /* Specifc GP support	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#if 1
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
-#else
-#define CFG_MONITOR_BASE    0x01fc0000	    /* start of monitor		*/
-#endif
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
-
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN	    (192 * 1024)    /* Reserve 192 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK /*	 (1843200 * 6)	 / * Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		9600
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#if 1 /* test-only */
-
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#undef CFG_FLASH_BASE
-#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
-
-#else /* test-only */
-
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#if 0 /* test-only */
-#define CFG_ENV_IS_IN_NVRAM	1	    /* Environment uses NVRAM	*/
-#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
-#undef	CFG_ENV_IS_IN_EEPROM		    /* ... not in EEPROM	*/
-
-#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-#else
-
-#if 0 /* test-only */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x010	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-#else
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#endif
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-#define CONFIG_BAUDRATE		9600
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#if 0 /* test-only */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_KGDB	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_ELF	)
-#else
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	)
-/* test-only: support fehlt bisher... */
-/*				CFG_CMD_IDE	| \*/
-/*				CFG_CMD_PCI	| \*/
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef CONFIG_SPD_EEPROM       /* don't use SPD EEPROM for setup    */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#if 0 /* test-only */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#endif
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if 0
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR	0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS	0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
deleted file mode 100644
index 93d49f3862..0000000000
--- a/include/configs/CPCIISER4.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	"bootm fff00000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Uart 8bit) initialization					*/
-#define CFG_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Uart 32bit) initialization					*/
-#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-
-/* Memory Bank 3 (FPGA Reset) initialization					*/
-#define CFG_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
deleted file mode 100644
index 16a9ea5dd7..0000000000
--- a/include/configs/CPU86.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
-#define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef  CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	64000000	/* in Hz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT								\
-	"echo; "								\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS; "	\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define	CONFIG_SOFT_I2C			/* Software I2C support enabled	*/
-
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CFG_DPSRAM_BASE		0x40000000
-#define CFG_DPSRAM_SIZE		0x00020000
-
-/* CS4: DiskOnChip */
-#define CFG_DOC_BASE		0xF4000000
-#define CFG_DOC_SIZE		0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CFG_FDC37C78_BASE	0xF1000000
-#define CFG_FDC37C78_SIZE	0x00100000
-
-/* CS6: Board configuration registers */
-#define CFG_BCRS_BASE		0xF2000000
-#define CFG_BCRS_SIZE		0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CFG_VMEEAR_BASE		0x80000000
-#define CFG_VMEEAR_SIZE		0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CFG_VMESAR_BASE		0xFE000000
-#define CFG_VMESAR_SIZE		0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CFG_VMESIOAR_BASE	0xFD000000
-#define CFG_VMESIOAR_SIZE	0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-				 HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CFG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_BOOT_ROM
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
-# define CFG_ENV_SIZE		0x10000
-# define CFG_ENV_SECT_SIZE	0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		512
-#define CFG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
-			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR        SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-#define CFG_MIN_AM_MASK	0xC0000000
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register              10-18
- *-----------------------------------------------------------------------
- */
-#define CFG_MPTPR       0x1F00
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register                                10-16
- *-----------------------------------------------------------------------
- */
-#define CFG_PSRT        0x0f
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register                                   10-10
- *-----------------------------------------------------------------------
- */
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
-			 PSDMR_BSMA_A14_A16		|\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_1W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI0_A9		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_1W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    8  bit  Boot ROM
- *  1   60x     GPCM    64 bit  FLASH
- *  2   60x     SDRAM   64 bit  SDRAM
- *
- */
-
-#define CFG_MRS_OFFS	0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CFG_BR0_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CFG_BR1_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CFG_BR1_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
-
-#define CFG_PSDMR	 CFG_PSDMR_9COL
-#endif /* CFG_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CFG_BR3_PRELIM  ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR3_PRELIM  (P2SZ_TO_AM(CFG_DPSRAM_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CFG_BR4_PRELIM  ((CFG_DOC_BASE & BRx_BA_MSK)    |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR4_PRELIM  (P2SZ_TO_AM(CFG_DOC_SIZE)       |\
-			 ORxG_ACS_DIV2                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CFG_BR5_PRELIM  ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
-			 BRx_PS_8                         |\
-			 BRx_MS_GPCM_P                    |\
-			 BRx_V)
-
-#define CFG_OR5_PRELIM  (P2SZ_TO_AM(CFG_FDC37C78_SIZE)    |\
-			 ORxG_ACS_DIV2                    |\
-			 ORxG_SCY_8_CLK                   |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CFG_BR6_PRELIM  ((CFG_BCRS_BASE & BRx_BA_MSK)   |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR6_PRELIM  (P2SZ_TO_AM(CFG_BCRS_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_SCY_5_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CFG_BR7_PRELIM  ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_VMEEAR_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CFG_BR8_PRELIM  ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR8_PRELIM  (P2SZ_TO_AM(CFG_VMESAR_SIZE)    |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_5_CLK                 |\
-			 ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CFG_BR9_PRELIM  ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16                        |\
-			 BRx_MS_GPCM_P                    |\
-			 BRx_V)
-
-#define CFG_OR9_PRELIM  (P2SZ_TO_AM(CFG_VMESIOAR_SIZE)    |\
-			 ORxG_CSNT                        |\
-			 ORxG_ACS_DIV1                    |\
-			 ORxG_SCY_5_CLK                   |\
-			 ORxG_SETA)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
deleted file mode 100644
index ce969ecdd1..0000000000
--- a/include/configs/CPU87.h
+++ /dev/null
@@ -1,702 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
-#define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
-#define CONFIG_PCI
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-
-#define	CONFIG_HAS_ETH1		1
-#define	CONFIG_HAS_ETH2		1
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK12
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	100000000	/* in Hz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT								\
-	"echo; "								\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS; "	\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM/RTC configuration
- */
-#define CONFIG_SOFT_I2C			/* Software I2C support enabled */
-
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else	iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else	iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_PCI)
-#else	/* ! PCI */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_I2C	)
-#endif	/* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
-
-#define CONFIG_LOOPW
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Other areas to be mapped
- */
-
-/* CS3: Dual ported SRAM */
-#define CFG_DPSRAM_BASE		0x40000000
-#define CFG_DPSRAM_SIZE		0x00100000
-
-/* CS4: DiskOnChip */
-#define CFG_DOC_BASE		0xF4000000
-#define CFG_DOC_SIZE		0x00100000
-
-/* CS5: FDC37C78 controller */
-#define CFG_FDC37C78_BASE	0xF1000000
-#define CFG_FDC37C78_SIZE	0x00100000
-
-/* CS6: Board configuration registers */
-#define CFG_BCRS_BASE		0xF2000000
-#define CFG_BCRS_SIZE		0x00010000
-
-/* CS7: VME Extended Access Range */
-#define CFG_VMEEAR_BASE		0x60000000
-#define CFG_VMEEAR_SIZE		0x01000000
-
-/* CS8: VME Standard Access Range */
-#define CFG_VMESAR_BASE		0xFE000000
-#define CFG_VMESAR_SIZE		0x01000000
-
-/* CS9: VME Short I/O Access Range */
-#define CFG_VMESIOAR_BASE	0xFD000000
-#define CFG_VMESIOAR_SIZE	0x01000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-				 HRCW_BPS01 | HRCW_CS10PC01)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
-#endif
-
-#ifdef	CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-#endif
-
-#if 0
-/* environment is in Flash */
-#define CFG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_BOOT_ROM
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
-# define CFG_ENV_SIZE		0x10000
-# define CFG_ENV_SECT_SIZE	0x10000
-#endif
-#else
-/* environment is in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		512
-#define CFG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot		   */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
-			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
-			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR	SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-#define CFG_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
- * refresh rate = 7.68 uS (100 MHz Bus Clock)
- */
-
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register		10-18
- *-----------------------------------------------------------------------
- */
-#define CFG_MPTPR	0x2000
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register				10-16
- *-----------------------------------------------------------------------
- */
-#define CFG_PSRT	0x16
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register					10-10
- *-----------------------------------------------------------------------
- */
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
-			 PSDMR_BSMA_A14_A16		|\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI0_A9		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 10-column chips
-	 */
-#define CFG_OR2_10COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI1_A4		|\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_10COL	(PSDMR_PBI			|\
-			 PSDMR_SDAM_A17_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI1_A6		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	8  bit	Boot ROM
- *  1	60x	GPCM	64 bit	FLASH
- *  2	60x	SDRAM	64 bit	SDRAM
- *
- */
-
-#define CFG_MRS_OFFS	0x00000000
-
-#ifdef CONFIG_BOOT_ROM
-/* Bank 0 - Boot ROM
- */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - FLASH
- */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-#else /* CONFIG_BOOT_ROM */
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 1 - Boot ROM
- */
-#define CFG_BR1_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-#endif /* CONFIG_BOOT_ROM */
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	 CFG_OR2_8COL
-
-#define CFG_PSDMR	 CFG_PSDMR_8COL
-#endif /* CFG_RAMBOOT */
-
-/* Bank 3 - Dual Ported SRAM
- */
-#define CFG_BR3_PRELIM	((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR3_PRELIM	(P2SZ_TO_AM(CFG_DPSRAM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 4 - DiskOnChip
- */
-#define CFG_BR4_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR4_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV2			|\
-			 ORxG_SCY_9_CLK			|\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 5 - FDC37C78 controller
- */
-#define CFG_BR5_PRELIM	((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
-			 BRx_PS_8			  |\
-			 BRx_MS_GPCM_P			  |\
-			 BRx_V)
-
-#define CFG_OR5_PRELIM	(P2SZ_TO_AM(CFG_FDC37C78_SIZE)	  |\
-			 ORxG_ACS_DIV2			  |\
-			 ORxG_SCY_10_CLK		  |\
-			 ORxU_EHTR_8IDLE)
-
-/* Bank 6 - Board control registers
- */
-#define CFG_BR6_PRELIM	((CFG_BCRS_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR6_PRELIM	(P2SZ_TO_AM(CFG_BCRS_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_SCY_7_CLK)
-
-/* Bank 7 - VME Extended Access Range
- */
-#define CFG_BR7_PRELIM	((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR7_PRELIM	(P2SZ_TO_AM(CFG_VMEEAR_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 8 - VME Standard Access Range
- */
-#define CFG_BR8_PRELIM	((CFG_VMESAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR8_PRELIM	(P2SZ_TO_AM(CFG_VMESAR_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_7_CLK			|\
-			 ORxG_SETA)
-
-/* Bank 9 - VME Short I/O Access Range
- */
-#define CFG_BR9_PRELIM	((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			  |\
-			 BRx_MS_GPCM_P			  |\
-			 BRx_V)
-
-#define CFG_OR9_PRELIM	(P2SZ_TO_AM(CFG_VMESIOAR_SIZE)	  |\
-			 ORxG_CSNT			  |\
-			 ORxG_ACS_DIV1			  |\
-			 ORxG_SCY_7_CLK			  |\
-			 ORxG_SETA)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
deleted file mode 100644
index acc8484717..0000000000
--- a/include/configs/CU824.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8240		1
-#define CONFIG_CU824		1
-
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command	*/
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG  | \
-				0 /* CFG_CMD_DATE */	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#if 1
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFF000000
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFCE00000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x10000000
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-	/* Size in bytes reserved for initial data
-	 */
-#define CFG_GBL_DATA_SIZE    128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	4
-
-#define CFG_NS16550_CLK		(14745600 / 2)
-
-#define CFG_NS16550_COM1	0xFE800080
-#define CFG_NS16550_COM2	0xFE8000C0
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     1000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_REFINT	    430	    /* Refresh interval			*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    192
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
-#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CFG_ACTORW	    2
-#define CFG_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	    1
-#if 0
-#define CFG_ENV_ADDR		0xFF008000
-#define CFG_ENV_SIZE		0x8000	/* Size of the Environment Sector	*/
-#else
-#define CFG_ENV_ADDR		0xFFFC0000
-#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
-#define CFG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_USE_IO
-
-#define CFG_ETH_DEV_FN	     0x7800
-#define CFG_ETH_IOBASE	     0x00104000
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define PCI_ENET0_IOADDR	0x00104000
-#define PCI_ENET0_MEMADDR	0x80000000
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
deleted file mode 100644
index 997e1baa9a..0000000000
--- a/include/configs/DASA_SIM.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
-#define CONFIG_DASA_SIM		1	/* ...on a DASA_SIM board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK		66
-#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#define CONFIG_BOOTCOMMAND	"bootm ffe00000" /* autoboot command	*/
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_IPADDR		10.0.18.222
-#define CONFIG_SERVERIP		10.0.18.190
-
-#if 0
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_ELF	)
-#else
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BSP	)
-#endif
-
-#if 0 /* Does not appear to be used?!  If it is used, needs to be fixed */
-#define CONFIG_SOFT_I2C			/* Software I2C support enabled */
-#endif
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-#if 0
-#define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
-#else
-#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI			/* include pci support			*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
-
-#define CONFIG_TULIP
-
-#define CFG_ETH_DEV_FN	     0x0000
-#define CFG_ETH_IOBASE	     0x0fff0000
-#define CFG_PCI9054_DEV_FN   0x0800
-#define CFG_PCI9054_IOBASE   0x0eff0000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		2048	/* For PLX IOP480			*/
-#define CFG_CACHELINE_SIZE	16	/* For AMCC 401/403 CPUs		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
deleted file mode 100644
index b58846d831..0000000000
--- a/include/configs/DK1C20.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * Stephan Linz <linz@li-pro.net>
- *
- * CompactFlash/IDE:
- * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************************
- * Include the whole NIOS CPU configuration.
- *
- * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
- *
- ***********************************************************************/
-
-#if	defined(CONFIG_NIOS_SAFE_32)
-#include <configs/DK1C20_safe_32.h>
-#elif	defined(CONFIG_NIOS_STANDARD_32)
-#include <configs/DK1C20_standard_32.h>
-#else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
-#endif
-
-/*------------------------------------------------------------------------
- * BOARD/CPU -- TOP-LEVEL
- *----------------------------------------------------------------------*/
-#define CONFIG_NIOS		1		/* NIOS-32 core		*/
-#define	CONFIG_DK1C20		1		/* Cyclone DK-1C20 board*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
-#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
-
-/*------------------------------------------------------------------------
- * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
-
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
-
-#else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
-#endif
-
-#define CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION - For the most part, you can put things pretty
- * much anywhere. This is pretty flexible for Nios. So here we make some
- * arbitrary choices & assume that the monitor is placed at the end of
- * a memory resource (so you must make sure TEXT_BASE is chosen
- * appropriately).
- *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
-
-#else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
-#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
-
-#else
-#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
-#endif
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
-
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
-
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
-#else
-#undef	CFG_NIOS_FIXEDBAUD
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
- * so an avalon bus timer is required.
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0)
-
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
-#endif
-
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
-#endif
-
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
-
-#else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
-
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
-
-#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#define	CONFIG_SMC_USE_32_BIT	1
-#else	/* no */
-#undef	CONFIG_SMC_USE_32_BIT
-#endif
-
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
-
-	/********************************************/
-	/* !!! CS8900 is __not__ tested on NIOS !!! */
-	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
-#else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
-#endif
-
-#else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
-#endif
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.2.21
-#define CONFIG_SERVERIP		192.168.2.16
-
-#else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
-#endif
-
-/*------------------------------------------------------------------------
- * STATUS LEDs
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
-
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
-
-#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
-
-#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
-
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
-#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
-#define	STATUS_LED_WRONLY		1
-#else
-#undef	STATUS_LED_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
-
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
-
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
-
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
-
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
-
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
-
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
-
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
-
-#else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
-#endif
-
-#define	CONFIG_STATUS_LED		1 /* enable status led driver */
-
-#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
-#define	STATUS_LED_STATE		STATUS_LED_BLINKING
-#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_BOOT			0		/* boot LED */
-
-#if	(STATUS_LED_BITS > 1)
-#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
-#define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
-#define	STATUS_LED_RED			1		/* fail LED */
-#endif
-
-#if	(STATUS_LED_BITS > 2)
-#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
-#define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_YELLOW		2		/* info LED */
-#endif
-
-#if	(STATUS_LED_BITS > 3)
-#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
-#define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_GREEN		3		/* info LED */
-#endif
-
-#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
-
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
-
-/*------------------------------------------------------------------------
- * SEVEN SEGMENT LED DISPLAY
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
-
-#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
-
-#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
-
-#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
-
-#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
-
-#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
-#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
-#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
-#define	SEVENSEG_WRONLY			1
-#else
-#undef	SEVENSEG_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
-
-#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
-
-#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
-
-#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
-
-#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
-
-#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
-
-#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
-
-#else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
-#endif
-
-#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
-
-/*
- * Dual 7-Segment Display pin assignment -- read more in your
- * "Nios Development Board Reference Manual"
- *
- *
- *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
- *         ______               ______
- *        |  D14 |             |  D6  |
- *        |      |             |      |
- *      D9|      |D13        D1|      |D5
- *        |______|             |______|                  ___
- *        |  D8  |             |  D0  |                 | A |
- *        |      |             |      |                F|___|B
- *     D10|      |D12        D2|      |D4               | G |
- *        |______|             |______|                E|___|C
- *           D11  *               D3   *                  D  *
- *                D15                  D7                    DP
- *
- */
-#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
-#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
-#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
-#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
-#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
-#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
-#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
-#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
-#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
-
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
-
-/*------------------------------------------------------------------------
- * ASMI - Active Serial Memory Interface.
- *
- * ASMI is for Cyclone devices only and only works when the configuration
- * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
- *----------------------------------------------------------------------*/
-#define CONFIG_NIOS_ASMI			   /* Enable ASMI	*/
-#define CFG_NIOS_ASMIBASE	CFG_NIOS_CPU_ASMI0 /* ASMI base address	*/
-
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_CMD_ASKENV | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_BMP	| \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_CACHE	| \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_DTT	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_ELF    | \
-				 CFG_CMD_FDC	| \
-				 CFG_CMD_FDOS	| \
-				 CFG_CMD_HWFLOW	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_JFFS2	| \
-				 CFG_CMD_KGDB	| \
-				 CFG_CMD_NAND	| \
-				 CFG_CMD_NFS	| \
-				 CFG_CMD_MMC	| \
-				 CFG_CMD_MII	| \
-				 CFG_CMD_PCI	| \
-				 CFG_CMD_PCMCIA | \
-				 CFG_CMD_REISER	| \
-				 CFG_CMD_SCSI	| \
-				 CFG_CMD_SPI	| \
-				 CFG_CMD_VFD	| \
-				 CFG_CMD_USB	| \
-				 CFG_CMD_XIMG	) )
-
-
-#include <cmd_confdefs.h>
-
-/*------------------------------------------------------------------------
- * COMPACT FLASH
- *----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
-#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
-#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
-
-#define CFG_ATA_BASE_ADDR	0x00920a00	/* IDE/ATA base addr	*/
-#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
-#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
-#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
-#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
-#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
-#define CONFIG_DOS_PARTITION
-
-/* Board-specific cf regs */
-#define CFG_CF_PRESENT		0x009209b0	/* CF Present PIO base	*/
-#define CFG_CF_POWER		0x009209c0	/* CF Power FET PIO base*/
-#define CFG_CF_ATASEL		0x009209d0	/* CF ATASEL PIO base	*/
-
-#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
-
-/*------------------------------------------------------------------------
- * KGDB
- *----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	9600
-#endif
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_PROMPT		"DK1C20 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
-
-#if	(CFG_SRAM_SIZE != 0)
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE	/* Default load address	*/
-#else
-#undef	CFG_LOAD_ADDR
-#endif
-
-#if	(CFG_SDRAM_SIZE != 0)
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE	/* SDRAM til stack area */
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
-#else
-#undef	CFG_MEMTEST_START
-#undef	CFG_MEMTEST_END
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h
deleted file mode 100644
index a483e87664..0000000000
--- a/include/configs/DK1C20_safe_32.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_DK1C20_SAFE_32_H
-#define __CONFIG_DK1C20_SAFE_32_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/DK1C20.h)
- *
- * !!! TODO !!! TODO !!!
- */
-#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template)
-
-#endif	/* __CONFIG_DK1C20_SAFE_32_H */
diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h
deleted file mode 100644
index ed08121cc2..0000000000
--- a/include/configs/DK1C20_standard_32.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_DK1C20_STANDARD_32_H
-#define __CONFIG_DK1C20_STANDARD_32_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/DK1C20.h)
- *
- * Here we must define CPU dependencies. Any unsupported option have to
- * be defined with zero, example CPU without data cache / OCI:
- *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
- */
-
-/* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
-						/*		yes(1)	*/
-
-/* on-chip extensions */
-#define	CFG_NIOS_CPU_RAM_BASE	0		/* on chip RAM	addr	*/
-#define	CFG_NIOS_CPU_RAM_SIZE	0		/*		size	*/
-
-#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
-
-#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
-#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
-
-/* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
-
-#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
-#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-/* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-/* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
-
-#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
-#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
-#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
-#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
-#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-/* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
-
-/* active serial memory i/f */
-#define	CFG_NIOS_CPU_ASMI_NUMS	1		/* number of ASMI	*/
-#define	CFG_NIOS_CPU_ASMI0	0x00920b00	/* ASMI0	addr	*/
-#define	CFG_NIOS_CPU_ASMI0_IRQ	45		/*		IRQ	*/
-
-/* memory accessibility */
-#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
-#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
-
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
-
-/* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
-
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
-						/*	cs8900(1)	*/
-						/* ex:	alteramac(2)	*/
-
-/* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
-#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
-
-#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
-#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
-#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
-#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
-#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
-#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
-#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
-#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
-
-#endif	/* __CONFIG_DK1C20_STANDARD_32_H */
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
deleted file mode 100644
index 3e3803cd23..0000000000
--- a/include/configs/DK1S10.h
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/***********************************************************************
- * Include the whole NIOS CPU configuration.
- *
- * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
- *
- ***********************************************************************/
-
-#if	defined(CONFIG_NIOS_SAFE_32)
-#include <configs/DK1S10_safe_32.h>
-#elif	defined(CONFIG_NIOS_STANDARD_32)
-#include <configs/DK1S10_standard_32.h>
-#elif	defined(CONFIG_NIOS_MTX_LDK_20)
-#include <configs/DK1S10_mtx_ldk_20.h>
-#else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
-#endif
-
-/*------------------------------------------------------------------------
- * BOARD/CPU -- TOP-LEVEL
- *----------------------------------------------------------------------*/
-#define CONFIG_NIOS		1		/* NIOS-32 core		*/
-#define	CONFIG_DK1S10		1		/* Stratix DK-1S10 board*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
-#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
-
-/*------------------------------------------------------------------------
- * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
-
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
-
-#else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
-#endif
-
-#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
-
-#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
-
-#else
-
-#undef	CFG_SRAM_BASE
-#undef	CFG_SRAM_SIZE
-
-#endif
-
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION - For the most part, you can put things pretty
- * much anywhere. This is pretty flexible for Nios. So here we make some
- * arbitrary choices & assume that the monitor is placed at the end of
- * a memory resource (so you must make sure TEXT_BASE is chosen
- * appropriately).
- *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
-
-#else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
-
-#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-
-#if	defined(CONFIG_NIOS_STANDARD_32)
-#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
-#elif	defined(CONFIG_NIOS_MTX_LDK_20)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-#else
-#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
-#endif
-
-#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
-
-#else
-#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
-#endif
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
-
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
-#define CONFIG_LOADS_ECHO	1	 /* echo on for serial download */
-
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
-#else
-#undef	CFG_NIOS_FIXEDBAUD
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
- * so an avalon bus timer is required.
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
-
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
-#endif
-
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
-
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
-
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
-
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
-#else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
-#endif
-
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
-
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
-
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
-#else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
-#endif
-
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
-
-#else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
-#endif
-
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
-
-#else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
-#endif
-
-/*------------------------------------------------------------------------
- * Ethernet -- needs work!
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
-
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
-
-#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#define	CONFIG_SMC_USE_32_BIT	1
-#else	/* no */
-#undef	CONFIG_SMC_USE_32_BIT
-#endif
-
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
-
-	/********************************************/
-	/* !!! CS8900 is __not__ tested on NIOS !!! */
-	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
-
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
-#else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
-#endif
-
-#else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
-#endif
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.2.21
-#define CONFIG_SERVERIP		192.168.2.16
-
-#else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
-#endif
-
-/*------------------------------------------------------------------------
- * STATUS LEDs
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
-
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
-
-#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
-
-#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
-
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
-#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
-#define	STATUS_LED_WRONLY		1
-#else
-#undef	STATUS_LED_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
-
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
-
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
-
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
-
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
-
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
-
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
-
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
-
-#else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
-#endif
-
-#define	CONFIG_STATUS_LED		1 /* enable status led driver */
-
-#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
-#define	STATUS_LED_STATE		STATUS_LED_BLINKING
-#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_BOOT			0		/* boot LED */
-
-#if	(STATUS_LED_BITS > 1)
-#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
-#define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
-#define	STATUS_LED_RED			1		/* fail LED */
-#endif
-
-#if	(STATUS_LED_BITS > 2)
-#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
-#define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_YELLOW		2		/* info LED */
-#endif
-
-#if	(STATUS_LED_BITS > 3)
-#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
-#define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
-#define	STATUS_LED_GREEN		3		/* info LED */
-#endif
-
-#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
-
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
-
-/*------------------------------------------------------------------------
- * SEVEN SEGMENT LED DISPLAY
- *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
-
-#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
-
-#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
-
-#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
-
-#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
-
-#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
-#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
-#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
-
-#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
-#define	SEVENSEG_WRONLY			1
-#else
-#undef	SEVENSEG_WRONLY
-#endif
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
-
-#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
-
-#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
-
-#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
-
-#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
-
-#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
-
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
-
-#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
-
-#else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
-#endif
-
-#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
-
-/*
- * Dual 7-Segment Display pin assignment -- read more in your
- * "Nios Development Board Reference Manual"
- *
- *
- *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
- *         ______               ______
- *        |  D14 |             |  D6  |
- *        |      |             |      |
- *      D9|      |D13        D1|      |D5
- *        |______|             |______|                  ___
- *        |  D8  |             |  D0  |                 | A |
- *        |      |             |      |                F|___|B
- *     D10|      |D12        D2|      |D4               | G |
- *        |______|             |______|                E|___|C
- *           D11  *               D3   *                  D  *
- *                D15                  D7                    DP
- *
- */
-#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
-#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
-#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
-#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
-#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
-#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
-#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
-#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
-#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
-
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
-
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_CMD_ASKENV | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_BMP	| \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_CACHE	| \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_DTT	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_ELF    | \
-				 CFG_CMD_FAT	| \
-				 CFG_CMD_FDC	| \
-				 CFG_CMD_FDOS	| \
-				 CFG_CMD_HWFLOW	| \
-				 CFG_CMD_IDE	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_JFFS2	| \
-				 CFG_CMD_KGDB	| \
-				 CFG_CMD_NAND	| \
-				 CFG_CMD_NFS	| \
-				 CFG_CMD_MMC	| \
-				 CFG_CMD_MII	| \
-				 CFG_CMD_PCI	| \
-				 CFG_CMD_PCMCIA | \
-				 CFG_CMD_SCSI	| \
-				 CFG_CMD_SPI	| \
-				 CFG_CMD_VFD	| \
-				 CFG_CMD_USB	| \
-				 CFG_CMD_XIMG	) )
-
-
-#include <cmd_confdefs.h>
-
-/*------------------------------------------------------------------------
- * KGDB
- *----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	9600
-#endif
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_PROMPT		"DK1S10 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
-
-/* Default load address	*/
-#if	(CFG_SRAM_SIZE != 0)
-
-/* default in SRAM */
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
-
-#elif	(CFG_SDRAM_SIZE != 0)
-
-/* default in SDRAM */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
-#else
-#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
-#endif
-
-#else
-#undef	CFG_LOAD_ADDR		/* force error break */
-#endif
-
-
-/* MEM test area */
-#if	(CFG_SDRAM_SIZE != 0)
-
-/* SDRAM begin to stack area (1MB stack) */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
-#else
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
-#endif
-
-#else
-#undef	CFG_MEMTEST_START	/* force error break */
-#undef	CFG_MEMTEST_END
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h
deleted file mode 100644
index 4eb96290bb..0000000000
--- a/include/configs/DK1S10_mtx_ldk_20.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_DK1S10_MTX_LDK_20_H
-#define __CONFIG_DK1S10_MTX_LDK_20_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/DK1S10.h)
- *
- * Here we must define CPU dependencies. Any unsupported option have to
- * be defined with zero, example CPU without data cache / OCI:
- *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
- */
-
-/* CPU core */
-#define	CFG_NIOS_CPU_CLK	75000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x02000000	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x01000000	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
-						/*		yes(1)	*/
-
-/* The offset address in flash to check for the Nios signature "Ni".
- * (see GM_FlashExec in germs_monitor.s) */
-#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
-
-/* on-chip extensions */
-#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
-#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
-
-#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
-
-#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
-#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
-
-/* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
-
-#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-/* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	2		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-#define	CFG_NIOS_CPU_UART1	0x000008a0	/* UART1	addr	*/
-#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-/* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	2		/* number of parports	*/
-
-#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
-#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-/* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	25		/* 		IRQ	*/
-
-/* memory accessibility */
-#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
-#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
-
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00800000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
-
-/* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
-
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
-						/*	cs8900(1)	*/
-						/* ex:	openmac(2)	*/
-						/* ex:	alteramac(3)	*/
-
-/* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
-#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
-
-#define	CFG_NIOS_CPU_CFPOWER_PIO	0	/* PIO0: CF power/sw.	*/
-#define	CFG_NIOS_CPU_BUTTON_PIO		1	/* PIO1: buttons	*/
-#undef	CFG_NIOS_CPU_LCD_PIO			/* PIOx: ASCII LCD	*/
-#undef	CFG_NIOS_CPU_LED_PIO			/* PIOx: LED bar	*/
-#undef	CFG_NIOS_CPU_SEVENSEG_PIO		/* PIOx: 7-seg. display	*/
-#undef	CFG_NIOS_CPU_RECONF_PIO			/* PIOx: reconf pin	*/
-#undef	CFG_NIOS_CPU_CFPRESENT_PIO		/* PIOx: CF present IRQ	*/
-#undef	CFG_NIOS_CPU_CFATASEL_PIO		/* PIOx: CF ATA select	*/
-
-#endif	/* __CONFIG_DK1S10_MTX_LDK_20_H */
diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h
deleted file mode 100644
index 8541a119f7..0000000000
--- a/include/configs/DK1S10_safe_32.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_DK1S10_SAFE_32_H
-#define __CONFIG_DK1S10_SAFE_32_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/DK1S10.h)
- *
- * !!! TODO !!! TODO !!!
- */
-#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template)
-
-#endif	/* __CONFIG_DK1S10_SAFE_32_H */
diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h
deleted file mode 100644
index b83c31592a..0000000000
--- a/include/configs/DK1S10_standard_32.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_DK1S10_STANDARD_32_H
-#define __CONFIG_DK1S10_STANDARD_32_H
-
-/*
- * NIOS CPU configuration. (PART OF configs/DK1S10.h)
- *
- * Here we must define CPU dependencies. Any unsupported option have to
- * be defined with zero, example CPU without data cache / OCI:
- *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
- */
-
-/* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
-						/*		yes(1)	*/
-
-/* on-chip extensions */
-#define	CFG_NIOS_CPU_RAM_BASE	0x00900000	/* on chip RAM	addr	*/
-#define	CFG_NIOS_CPU_RAM_SIZE	(64 * 1024)	/* 64 KB	size	*/
-
-#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
-
-#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
-#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
-
-/* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
-
-#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
-#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
-						/*		yes(1)	*/
-
-/* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
-						/*		odd(1)	*/
-						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
-						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
-						/*		yes(1)	*/
-
-/* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
-
-#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
-#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
-#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
-#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
-#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
-						/*		out(1)	*/
-						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
-						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
-						/*		fall(1)	*/
-						/*		rise(2)	*/
-						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
-						/*		level(1)*/
-						/*		edge(2)	*/
-
-/* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
-
-/* memory accessibility */
-#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
-#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
-
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
-
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
-
-/* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
-
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
-						/*	cs8900(1)	*/
-						/* ex:	alteramac(2)	*/
-
-/* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
-#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
-
-#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
-#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
-#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
-#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
-#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
-#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
-#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
-#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
-
-#endif	/* __CONFIG_DK1S10_STANDARD_32_H */
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
deleted file mode 100644
index 2ae794dc26..0000000000
--- a/include/configs/DP405.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_DP405		1	/* ...on a DP405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-#define CONFIG_PRAM		2	/* reserve 2 kB "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-#if 0 /* test-only */
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-#endif
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
deleted file mode 100644
index 5489a53936..0000000000
--- a/include/configs/DU405.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IDENT_STRING     " $Name:  $"
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_DU405		1	/* ...on a DU405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
-
-#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	"bootm fff00000"
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
-#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
-#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
-#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
-#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
-#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
-
-#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP	0x92015480
-#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP	0x92015480
-#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0) initialization						*/
-#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (DUART) initialization						*/
-#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 4 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 5 (SRAM) initialization						*/
-#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
-#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
-
-/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
-#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
deleted file mode 100644
index 720b335b09..0000000000
--- a/include/configs/EB+MCF-EV123.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Configuation settings for the BuS EB+MCF-EV123 boards.
- *
- * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CONFIG_EB_MCF_EV123_H_
-#define _CONFIG_EB_MCF_EV123_H_
-
-#define  CONFIG_EB_MCF_EV123
-
-#undef DEBUG
-#undef CFG_HALT_BEFOR_RAM_JUMP
-#undef ET_DEBUG
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define	CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5282			/* define processor type */
-
-#define CONFIG_MISC_INIT_R
-
-#define FEC_ENET
-#define CONFIG_ETHADDR 00:CF:52:82:EB:01
-
-#define CONFIG_BAUDRATE 9600
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
-
-#define CONFIG_BOOTCOMMAND "printenv"
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_ADDR		0xF003C000	/* End of 256K */
-#define CFG_ENV_SECT_SIZE	0x4000
-#define CFG_ENV_IS_IN_FLASH	1
-/*
-#define CFG_ENV_IS_EMBEDDED	1
-#define CFG_ENV_ADDR_REDUND		0xF0018000
-#define CFG_ENV_SECT_SIZE_REDUND	0x4000
-*/
-#else
-#define CFG_ENV_ADDR		0xFFE04000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-#endif
-
-/*#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
-#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	5
-#define CFG_PROMPT		"\nEV123 U-Boot> "
-#define	CFG_LONGHELP				/* undef to save memory		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_LOAD_ADDR		0x20000
-
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x400000
-/*#define CFG_DRAM_TEST		1 */
-#undef CFG_DRAM_TEST
-
-/* Clock and PLL Configuration */
-#define CFG_HZ			10000000
-#define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
-
-/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-
-#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */
-#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define	CFG_MBAR		0x40000000
-
-#define	CFG_DISCOVER_PHY
-/* #define	CFG_ENET_BD_BASE	0x380000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR       0x20000000
-#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE1		0x00000000
-#define	CFG_SDRAM_SIZE1		16		/* SDRAM size in MB */
-
-/*
-#define CFG_SDRAM_BASE0		CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
-#define	CFG_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
-
-#define CFG_SDRAM_BASE		CFG_SDRAM_BASE1
-#define	CFG_SDRAM_SIZE		CFG_SDRAM_SIZE1
-
-#define CFG_FLASH_BASE		0xFFE00000
-#define	CFG_INT_FLASH_BASE	0xF0000000
-
-/* If M5282 port is fully implemented the monitor base will be behind
- * the vector table. */
-#if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
-#else
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
-#endif
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define	CFG_MAX_FLASH_SECT	35
-#define	CFG_MAX_FLASH_BANKS	2
-#define	CFG_FLASH_ERASE_TOUT	10000000
-#define	CFG_FLASH_PROTECTION
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-
-#define CFG_CS0_BASE		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		2*1024*1024
-#define CFG_CS0_WIDTH		16
-#define CFG_CS0_RO 		0
-#define CFG_CS0_WS		6
-
-#define CFG_CS3_BASE		0xE0000000
-#define CFG_CS3_SIZE		1*1024*1024
-#define CFG_CS3_WIDTH		16
-#define CFG_CS3_RO 		0
-#define CFG_CS3_WS		6
-
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
-#define CFG_PADDR		0x0000000
-#define CFG_PADAT		0x0000000
-
-#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
-#define CFG_PBDDR		0x0000000
-#define CFG_PBDAT		0x0000000
-
-#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
-
-#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
-
-#define CFG_PEHLPAR		0xC0
-#define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
-#define CFG_DDRUA		0x05
-#define CFG_PJPAR 		0xFF;
-
-/*-----------------------------------------------------------------------
- * CCM configuration
- */
-
-#define	CFG_CCM_SIZ		0
-
-/*---------------------------------------------------------------------*/
-#endif	/* _CONFIG_M5282EVB_H */
-/*---------------------------------------------------------------------*/
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
deleted file mode 100644
index 2c99b4b162..0000000000
--- a/include/configs/ELPPC.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef  DEBUG
-#define GTREGREAD(x) 0xffffffff         /* needed for debug */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* these hardware addresses are pretty bogus, please change them to
-   suit your needs */
-
-/* first ethernet */
-#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
-
-#define CONFIG_IPADDR           192.168.0.105
-#define CONFIG_SERVERIP         192.168.0.100
-
-#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */
-
-#define CONFIG_BAUDRATE         9600    /* console baudrate */
-
-#undef  CONFIG_WATCHDOG
-
-#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef  CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                  \
-    "bootp 1000000; "                                       \
-    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
-    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
-    "${netmask}:${hostname}:eth0:none; "                    \
-    "bootm"
-
-#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP                    /* undef to save memory */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
-
-/*
- * choose between COM1 and COM2 as serial console
- */
-#define CONFIG_CONS_INDEX       1
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16          /* max number of command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
-#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
-
-#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
-
-#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define CFG_BOARD_ASM_INIT
-#define CONFIG_MISC_INIT_R
-
-/*
- * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
- */
-#undef  CFG_ADDRESS_MAP_A
-
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
-
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7d000000
-
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xfd000000
-#define CFG_ISA_MEM_SIZE        0x01000000
-
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xfe800000
-#define CFG_PCI_IO_SIZE         0x00400000
-
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xfe000000
-#define CFG_ISA_IO_SIZE         0x00800000
-
-/* driver defines FDC,IDE,... */
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE          0x00000000
-
-#define CFG_USR_LED_BASE        0x78000000
-#define CFG_NVRAM_BASE          0xff000000
-#define CFG_UART_BASE           0xff400000
-#define CFG_FLASH_BASE          0xfff00000
-
-#define MPC107_EUMB_ADDR        0xfce00000
-#define MPC107_EUMB_PI          0xfce41090
-#define MPC107_EUMB_GCR         0xfce41020
-#define MPC107_EUMB_IACKR       0xfce600a0
-#define MPC107_I2C_ADDR         0xfce03000
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CFG_INIT_RAM_END        0x4000
-#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*
- * Flash mapping/organization on the MPC10x.
- */
-#define FLASH_BASE0_PRELIM      0xff800000
-#define FLASH_BASE1_PRELIM      0xffc00000
-
-#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
-#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
-#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
-*/
-
-#define CFG_MONITOR_BASE        CFG_FLASH_BASE
-#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
-#undef  CFG_MEMTEST
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
-#define CFG_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
-#define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
-#define CFG_ENV_ADDR            0x0
-#define CFG_ENV_MAP_ADRS        0xff000000
-#define CFG_NV_SROM_COPY_ADDR   (CFG_ENV_ADDR + CFG_ENV_SIZE)
-#define CFG_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
-#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
-
-/*
- * Serial devices
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK         24000000
-#define CFG_NS16550_COM1        (CFG_UART_BASE + 0)
-#define CFG_NS16550_COM2        (CFG_UART_BASE + 8)
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI                                /* include pci support */
-#define CONFIG_PCI_PNP                            /* pci plug-and-play */
-#define CONFIG_PCI_HOST         PCI_HOST_AUTO
-#undef  CONFIG_PCI_SCAN_SHOW
-
-/*
- * Optional Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
-#define VIDEO_TSTC_FCT        serial_tstc
-#define VIDEO_GETC_FCT        serial_getc
-
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-
-/*
- * Initial BATs
- */
-#if 1
-
-#define CFG_IBAT0L 0
-#define CFG_IBAT0U 0
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
-
-#define CFG_IBAT1L 0
-#define CFG_IBAT1U 0
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
-
-#define CFG_IBAT2L 0
-#define CFG_IBAT2U 0
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
-
-#define CFG_IBAT3L 0
-#define CFG_IBAT3U 0
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
-
-#else
-
-/* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
-
-/* address range for flashes */
-#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
-
-/* ISA IO space */
-#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
-
-/* ISA memory space */
-#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
-
-#endif
-
-/*
- * Speed settings are board specific
- */
-#define CFG_BUS_HZ              100000000
-#define CFG_CPU_CLK             400000000
-#define CFG_BUS_CLK             CFG_BUS_HZ
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
-#endif
-
-/*
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CFG_L2
-
-#if 1
-#define L2_INIT     0       /* cpu 750 CXe*/
-#else
-#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
-#endif
-#define L2_ENABLE   (L2_INIT | L2CR_L2E)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM           0x02    /* Software reboot */
-
-#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#endif    /* __CONFIG_H */
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
deleted file mode 100644
index e73bcec448..0000000000
--- a/include/configs/ELPT860.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
-**=====================================================================
-**
-** Copyright (C) 2000, 2001, 2002, 2003
-** The LEOX team <team@leox.org>, http://www.leox.org
-**
-** LEOX.org is about the development of free hardware and software resources
-**   for system on chip.
-**
-** Description: U-Boot port on the LEOX's ELPT860 CPU board
-** ~~~~~~~~~~~
-**
-**=====================================================================
-**
-** This program is free software; you can redistribute it and/or
-** modify it under the terms of the GNU General Public License as
-** published by the Free Software Foundation; either version 2 of
-** the License, or (at your option) any later version.
-**
-** This program is distributed in the hope that it will be useful,
-** but WITHOUT ANY WARRANTY; without even the implied warranty of
-** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-** GNU General Public License for more details.
-**
-** You should have received a copy of the GNU General Public License
-** along with this program; if not, write to the Free Software
-** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-** MA 02111-1307 USA
-**
-**=====================================================================
-*/
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* It's a MPC860, in fact a 860T CPU */
-#define CONFIG_MPC860T		1
-#define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */
-
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
-#undef	  CONFIG_8xx_CONS_SMC2
-#undef	  CONFIG_8xx_CONS_NONE
-
-#define CONFIG_CLOCKS_IN_MHZ	1  /* Clock passed to Linux (<2.4.5) in MHz */
-#define CONFIG_8xx_GCLK_FREQ	50000000       /* MPC860T runs at 50MHz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-/* BOOT arguments */
-#define CONFIG_PREBOOT							   \
-     "echo;"								   \
-     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"	   \
-     "echo"
-
-#undef	  CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-    "ramargs=setenv bootargs root=/dev/ram rw\0"			\
-    "rootargs=setenv rootpath /tftp/${ipaddr}\0"			\
-    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=${serverip}:${rootpath}\0"				\
-    "addip=setenv bootargs ${bootargs} "				\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
-	":${hostname}:eth0:off panic=1\0"				\
-    "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
-	"run ramargs;bootm\0"						\
-    "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
-	"run rootargs;run nfsargs;run addip;bootm\0"			\
-    ""
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
-#undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-#undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
-#define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-				  CFG_CMD_ASKENV | \
-				  CFG_CMD_DATE	 )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
-#endif
-
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	  16		/* max number of command args	*/
-#define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*
- * Environment Variables and Storages
- */
-#define CONFIG_ENV_OVERWRITE	1  /* Allow Overwrite of serial# & ethaddr */
-
-#undef	  CFG_ENV_IS_IN_NVRAM	       /* Environment is in NVRAM	*/
-#undef	  CFG_ENV_IS_IN_EEPROM	       /* Environment is in I2C EEPROM	*/
-#define CFG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/
-
-#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_ETHADDR		00:01:77:00:60:40
-#define CONFIG_IPADDR		192.168.0.30
-#define CONFIG_NETMASK		255.255.255.0
-
-#define CONFIG_SERVERIP		192.168.0.1
-#define CONFIG_GATEWAYIP	192.168.0.1
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02000000
-#define CFG_NVRAM_BASE		0x03000000
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-#  if defined(DEBUG)
-#    define CFG_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
-#  else
-#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
-#  endif
-#else
-#  if defined(DEBUG)
-#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
-#  else
-#    define CFG_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
-#  endif
-#endif
-
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-#  define CFG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
-#  define CFG_ENV_SIZE		0x10000 /* Total Size of Environment Sector  */
-#endif
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_BASE /* Base address of NVRAM area */
-#define CFG_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
-					       /*   8 top NVRAM locations    */
-
-#if defined(CFG_ENV_IS_IN_NVRAM)
-#  define CFG_ENV_ADDR		CFG_NVRAM_BASE /* Base address of NVRAM area */
-#  define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
-#else
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
-						   SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC11)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
- *  enabled
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	 SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
- *-----------------------------------------------------------------------
- *
- */
-#ifdef DEBUG
-#  define CFG_DER		0xFFE7400F	/* Debug Enable Register */
-#else
-#  define CFG_DER		0
-#endif
-
-/*
- * Init Memory Controller:
- * ~~~~~~~~~~~~~~~~~~~~~~
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	  */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/
-
-/* SDRAM timing:							*/
-#define CFG_OR_TIMING_SDRAM	0x00000000
-
-#define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2 and OR2 (NVRAM)
- *
- */
-#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0	*/
-#define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/
-
-#define CFG_OR2_PRELIM		0xFFF80160
-#define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		97     /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *-----------------------------------------------------------------------
- *
- */
-
-/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		 /* Software reboot		     */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
deleted file mode 100644
index c203aea924..0000000000
--- a/include/configs/ERIC.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_ERIC		1	/* ...on a ERIC board	*/
-
-#define	CONFIG_BOARD_EARLY_INIT_F 1	/* run board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-
-#if 1
-#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
-#endif
-#if 0
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-#if 0
-#define CFG_ENV_IS_IN_EEPROM	1	/* use I2C RTC X1240 for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars */
-#endif					/* total size of a X1240 is 2048 bytes */
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
-#define CONFIG_I2C_RTC		1	/* we have a Xicor X1240 RTC */
-#define CFG_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_EEPROM
-#else
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_EEPROM
-#else
-#ifdef CFG_ENV_IS_IN_EEPROM
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#endif
-#endif
-#endif
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-#endif
-
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/nfs "	\
-				"nfsroot=192.168.1.2:/eric_root_devel "	\
-				"ip=192.168.1.22:192.168.1.2"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ENV	| \
-				CFG_CMD_FLASH)
-
-/*
- * #define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
- *				 CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
- *				 CFG_CMD_ENV | CFG_CMD_FLASH)
- */
-
-/* CFG_CMD_ENV est definie */
-/*	((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
- */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	 CFG_EXT_SERIAL_CLOCK	 14318180
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-					/* resource configuration       */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
-#define CFG_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-/*	Bank 0 - Flash/SRAM	       0xFF000000 16MB	16 Bit */
-/*	Bank 1 - NVRAM/RTC	       0xF0000000  1MB	 8 Bit */
-/*	Bank 2 - A/D converter	       0xF0100000  1MB	 8 Bit */
-/*	Bank 3 - Ethernet PHY Reset    0xF0200000  1MB	 8 Bit */
-/*	Bank 4 - PC-MIP PRSNT1#	       0xF0300000  1MB	 8 Bit */
-/*	Bank 5 - PC-MIP PRSNT2#	       0xF0400000  1MB	 8 Bit */
-/*	Bank 6 - CPU LED0	       0xF0500000  1MB	 8 Bit */
-/*	Bank 7 - CPU LED1	       0xF0600000  1MB	 8 Bit */
-
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 0 (Flash) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS0_AP	0x9B015480
-#define CS0_CR	0xFF87A000 /*  BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 1 (NVRAM/RTC) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS1_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS1_CR	0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
- /* ----------------------------------------------------------------------- */
- /*  Memory Bank 2 (A/D converter) initialization */
- /* ----------------------------------------------------------------------- */
-#define CS2_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS2_CR	0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 3 (Ethernet PHY Reset) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS3_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS3_CR	0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 4 (PC-MIP PRSNT1#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS4_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS4_CR	0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 5 (PC-MIP PRSNT2#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS5_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS5_CR	0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 6 (CPU LED0) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS6_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS6_CR	0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 7 (CPU LED1) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS7_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS7_CR	0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-
-#define CFG_NVRAM_REG_BASE_ADDR	 0xF0000000
-#define CFG_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
-#define CFG_ADC_REG_BASE_ADDR	 0xF0100000
-#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000
-#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000
-#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000
-#define CFG_LED0_REG_BASE_ADDR	 0xF0500000
-#define CFG_LED1_REG_BASE_ADDR	 0xF0600000
-
-
-/*  SDRAM CONFIG */
-#define CFG_SDRAM_MANUALLY    1
-#define CFG_SDRAM_SINGLE_BANK 1
-
-#ifdef CFG_SDRAM_MANUALLY
-/*-----------------------------------------------------------------------
- * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#define MB0CF	0x00062001 /*  32MB @ 0 */
-/*-----------------------------------------------------------------------
- * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#ifdef CFG_SDRAM_SINGLE_BANK
-#define MB1CF	0x0 /*  0MB @ 32MB */
-#else
-#define MB1CF	0x02062001 /*  32MB @ 32MB */
-#endif
-/*-----------------------------------------------------------------------
- * Set MB2CF for bank 2. off
- *----------------------------------------------------------------------*/
-#define MB2CF	0x0 /*  0MB */
-/*-----------------------------------------------------------------------
- * Set MB3CF for bank 3. off
- *----------------------------------------------------------------------*/
-#define MB3CF	0x0 /*  0MB */
-
-#define SDTR_100    0x0086400D
-#define RTR_100     0x05F0
-#define SDTR_66     0x00854006	/* orig U-Boot-wallnut says 0x00854006 */
-#define RTR_66      0x03f8
-
-#endif   /* CFG_SDRAM_MANUALLY */
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		32
-#define CFG_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
-#define CFG_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
-/*#define CFG_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_FLASH_16BIT		1	/* Rom 16 bit data bus			*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE       (128*1024)
-
-#if 0  /* force ENV to be NOT embedded */
-#define CFG_ENV_ADDR            0xfffa0000
-#else  /* force ENV to be embedded */
-#define	CFG_ENV_SIZE		(2 * 1024) /* Total Size of Environment Sector 2k */
-#define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */
-/* #define CFG_ENV_ADDR            (CFG_MONITOR_BASE)*/
-#define CFG_ENV_OFFSET          (CFG_ENV_ADDR - CFG_FLASH_BASE)
-#endif
-
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x7F8		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB 	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-
-/* Configuration Port location */
-/*  #define CONFIG_PORT_ADDR	0xF0000500 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
deleted file mode 100644
index b176c6f37e..0000000000
--- a/include/configs/ESTEEM192E.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_ESTEEM192E	1	/* ...on a EST ESTEEM192E	*/
-
-#define CONFIG_FLASH_16BIT	1	/* Rom 16 bit data bus		*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef  CONFIG_8xx_CONS_NONE
-
-#define MPC8XX_FACT	10		/* Multiply by 10		*/
-#define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
-#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_BAUDRATE		9600
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 40030000" /* autoboot command	*/
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=8192 "			\
-				"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE	256			/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	8			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-  /*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
-
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-/*#define CFG_DER	0x02002000 */
-
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	0x00000160
-				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR) */
-
-#define CFG_OR0_REMAP	0x80000160     /*(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)*/
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )
-
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x04000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	0xFC000E00
-#define CFG_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)
-
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	0x18803112
-#define CFG_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
deleted file mode 100644
index d55eb7d192..0000000000
--- a/include/configs/ETX094.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_ETX094		1	/* ...on a ETX_094 board	*/
-
-#define	CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		57600
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define	CONFIG_FLASH_16BIT		/* for board with 16bit wide flash	*/
-#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM 	*/
-#define	CONFIG_BOOTP_RANDOM_DELAY	/* graceful BOOTP recovery mode		*/
-
-#define CONFIG_ETHADDR 08:00:06:00:00:00
-
-#ifdef	CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1	/* default MAC can be overwritten once	*/
-#endif
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/ram rw ramdisk_size=4690 "			\
-	"U-Boot_version=U-Boot-1.0.x-Date "					\
-	"panic=1 "								\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_FLASH_16BIT
-#define CFG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
-#else
-#define CFG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
-			       OR_SCY_2_CLK | OR_TRLX )
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-
-#ifdef CONFIG_FLASH_16BIT	/* 16 bit data port */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#else				/* 32 bit data port */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#endif	/* CONFIG_FLASH_16BIT */
-
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	23		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
deleted file mode 100644
index 78e5716885..0000000000
--- a/include/configs/EVB64260.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-#include "../board/evb64260/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
-
-#define CONFIG_BAUDRATE		38400 	/* console baudrate = 38400	*/
-
-#undef	CONFIG_ECC			/* enable ECC support */
-/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R	1
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#ifndef CONFIG_EVB64260_750CX
-#define CFG_BOARD_NAME		"EVB64260"
-#else
-#define CFG_BOARD_NAME         "EVB64260-750CX"
-#endif
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define	CONFIG_MPSC
-#define CONFIG_MPSC_PORT	0
-
-#define CONFIG_NET_MULTI        /* attempt all available adapters */
-
-/* define this if you want to enable GT MAC filtering */
-#define CONFIG_GT_USE_MAC_HASH_TABLE
-
-#undef CONFIG_ETHER_PORT_MII	/* use RMII */
-
-#if 1
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND						     \
-	"bootp && " 						     \
-	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
-	"ip=$ipaddr:$serverip:$gatewayip:" \
-	"$netmask:$hostname:eth0:none; && " \
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC                  /* undef to disable             */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE)
-
-
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ASKENV)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
-
-#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
-#define CFG_BUS_HZ		100000000	/* 100 MHz		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_EVB64260_750CX
-#define CONFIG_750CX
-#define CFG_BROKEN_CL2
-#endif
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define	CFG_INIT_RAM_END	0x1000
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_RAM_LOCK
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfff00000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
-#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
-
-/* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-#define CFG_GT_REGS		0xf8000000
-#define CFG_DEV_BASE		0xfc000000
-
-#define CFG_DEV0_SPACE		CFG_DEV_BASE
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
-
-#define CFG_DEV0_SIZE		 _8M /* evb64260 sram  @ 0xfc00.0000 */
-#define CFG_DEV1_SIZE		 _8M /* evb64260 rtc   @ 0xfc80.0000 */
-#define CFG_DEV2_SIZE		_16M /* evb64260 duart @ 0xfd00.0000 */
-#define CFG_DEV3_SIZE		_16M /* evb64260 flash @ 0xfe00.0000 */
-
-#define CFG_DEV0_PAR		0x20205093
-#define CFG_DEV1_PAR		0xcfcfffff
-#define CFG_DEV2_PAR		0xc0059bd4
-#define CFG_8BIT_BOOT_PAR	0xc00b5e7c
-#define CFG_32BIT_BOOT_PAR	0xc4a8241c
-	/*   c    4    a      8     2     4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-#if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
-						/* DMAAck[1:0] GNT0[1:0] */
-#else
-#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
-						/* REQ0[1:0] GNT0[1:0] */
-#endif
-#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
-						/* DMAReq[4] DMAAck[4] WDNMI WDE */
-#if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
-						/* DMAAck[1:0] GNT1[1:0] */
-#else
-#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
-						/* GPP[22] (RS232IntB or PCI1Int) */
-						/* GPP[21] (RS323IntA) */
-						/* BClkIn */
-						/* REQ1[1:0] GNT1[1:0] */
-#endif
-
-#if 0 /* Wrong?? NTL */
-# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
-						/* GPP[27:26] Int[1:0] */
-#else
-# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
-						/* GPP[29]    (PCI1Int) */
-						/* BClkOut0 */
-						/* GPP[27]    (PCI0Int) */
-						/* GPP[26]    (RtcInt or PCI1Int) */
-						/* CPUInt[25:24] */
-#endif
-
-# define CFG_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
-
-#if 0 /* Wrong?? - NTL */
-# define CFG_GPP_LEVEL_CONTROL	0x000002c6
-#else
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
-						/* gpp[29] */
-						/* gpp[27:26] */
-						/* gpp[22:21] */
-
-# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
-				/* idmas use buffer 1,1
-				   comm use buffer 0
-				   pci use buffer 1,1
-				   cpu use buffer 0
-				   normal load (see also ifdef HVL)
-				   standard SDRAM (see also ifdef REG)
-				   non staggered refresh */
-				/* 31:26  25 23  20 19 18 16 */
-				/* 110110 00 111 0  0  00 1 */
-				/* refresh_count=0x200
-				   phisical interleaving disable
-				   virtual interleaving enable */
-				/* 15 14 13:0 */
-				/* 1  0  0x200 */
-#endif
-
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
-#define CFG_INIT_CHAN1
-#define CFG_INIT_CHAN2
-
-#define SRAM_BASE		CFG_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI                      /* include pci support          */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
-
-/* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
-
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
-
-
-/* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
-
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-
-#define CFG_NS16550_REG_SIZE	-4
-
-#define CFG_NS16550_CLK		3686400
-
-#define CFG_NS16550_COM1	(CFG_DUART_IO + 0)
-#define CFG_NS16550_COM2	(CFG_DUART_IO + 0x20)
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
-
-/* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
-
-/* I2C speed and slave address (for compatability) defaults */
-#define CFG_I2C_SPEED	400000
-#define CFG_I2C_SLAVE	0x7F
-
-/* I2C addresses for the two DIMM SPD chips */
-#ifndef CONFIG_EVB64260_750CX
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
-#define DIMM0_I2C_ADDR  0x54
-#define DIMM1_I2C_ADDR	0x54
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
-#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_CFI		1
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE	0x10000
-#define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CFG_L2
-
-#ifdef CONFIG_750CX
-#define L2_INIT 0
-#else
-#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
-
-#define CFG_BOARD_ASM_INIT      1
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
deleted file mode 100644
index d85be424a2..0000000000
--- a/include/configs/EXBITGEN.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
-
-/* I2C configuration */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		40000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
-
-/* environment is in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM    1
-#undef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-
-#ifdef CFG_ENV_IS_IN_EEPROM
-#define CFG_I2C_EEPROM_ADDR		0x56    /* 1010110 */
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
-#define CFG_ENV_OFFSET		4	/* Offset of Environment Sector	*/
-#define	CFG_ENV_SIZE		350	/* that is 350 bytes only!	*/
-#endif
-
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds	*/
-/* Explanation:
-   autbooting is altogether disabled and cannot be
-   enabled if CONFIG_BOOTDELAY is negative.
-   If you want shorter bootdelay, then
-   - "setenv bootdelay <delay>" to the proper value
-*/
-
-#define CONFIG_BOOTCOMMAND	"bootm 20400000 20800000"
-
-#define CONFIG_BOOTARGS		"root=/dev/ram "  \
-				"ramdisk_size=32768 " \
-				"console=ttyS0,115200 " \
-				"ram=128M debug"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/* UART configuration */
-#define CFG_BASE_BAUD		691200
-
-/* Default baud rate */
-#define CONFIG_BAUDRATE		115200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_PCI			/* no pci support	        */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
-
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH0_BASE		0xFFF80000
-#define CFG_FLASH0_SIZE		0x00080000
-#define CFG_FLASH1_BASE		0x20000000
-#define CFG_FLASH1_SIZE		0x02000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE		CFG_FLASH0_SIZE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-#if CFG_MONITOR_BASE < CFG_FLASH0_BASE
-#define CFG_RAMSTART
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
-#define	CFG_ENV_SIZE		0x00010000 /* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x00010000 /* see README - env sector total size */
-#endif
-
-/* On Chip Memory location/size */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-/* Global info and initial stack */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/* Cache configuration */
-#define CFG_DCACHE_SIZE		8192
-#define CFG_CACHELINE_SIZE	32
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
deleted file mode 100644
index 1b562d6063..0000000000
--- a/include/configs/FADS823.h
+++ /dev/null
@@ -1,464 +0,0 @@
- /*
-  * A collection of structures, addresses, and values associated with
-  * the Motorola 860T FADS board.  Copied from the MBX stuff.
-  * Magnus Damm added defines for 8xxrom and extended bd_info.
-  * Helmut Buchsbaum added bitvalues for BCSRx
-  *
-  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
-  */
-
-/*
- * 1999-nov-26: The FADS is using the following physical memorymap:
- *
- * ff020000 -> ff02ffff : pcmcia     io remapping
- * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by U-Boot
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
- * fe000000 -> fe1fffff : flash      connected to CS0, setup by U-Boot
- * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
-*/
-
-#define CFG_PCMCIA_IO_ADDR	0xff020000
-#define CFG_PCMCIA_IO_SIZE	0x10000
-#define CFG_PCMCIA_MEM_ADDR	0xe0000000
-#define CFG_PCMCIA_MEM_SIZE	0x10000
-#define CFG_IMMR		0xFF000000
-#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02800000
-#define BCSR_ADDR		((uint) 0xff010000)
-#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
-#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
-
-#define CONFIG_VIDEO		1	/* To enable video controller support */
-#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-/*Now included by CFG_CMD_PCMCIA */
-/*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */
-
-/* Video related */
-
-#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
-#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
-#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	/* Default on fads */
-#define CONFIG_VIDEO_SIZE			(2*1024*1024)
-/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
-
-/* Wireless 56Khz 4PPM keyboard on SMCx */
-
-/*#define CONFIG_KEYBOARD		1 */
-#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823		1
-#define CONFIG_MPC823FADS	1
-#define CONFIG_FADS		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200
-
-/* Set the CPU speed to 50Mhz on the FADS */
-
-#if 0
-#define MPC8XX_FACT	10			/* Multiply by 10		*/
-#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
-#else
-#define MPC8XX_FACT	10			/* Multiply by 10 */
-#define MPC8XX_XIN	5000000			/* 5 MHz in */
-#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
-#endif
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#if 1
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
-#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
-#define CONFIG_BOOTARGS		""
-#define CONFIG_BOOTCOMMAND							\
-"bootp ;" 									\
-"setenv bootargs console=tty0 console=ttyS0 " 					\
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
-"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" 	\
-"bootm"
-#else
-#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
-#endif
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
- */
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
-#if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
-#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration						11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer  *
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
-				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-				SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define BCSR_SIZE		((uint)(64 * 1024))
-
-#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
-#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CFG_MAMR		0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
-
-/* values according to the manual */
-
-#define	BCSR0			((uint) (BCSR_ADDR + 00))
-#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
-#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
-#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
-#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
-
-/* FADS bitvalues by Helmut Buchsbaum
- * see MPC8xxADS User's Manual for a proper description
- * of the following structures
- */
-
-#define BCSR0_ERB       ((uint)0x80000000)
-#define BCSR0_IP        ((uint)0x40000000)
-#define BCSR0_BDIS      ((uint)0x10000000)
-#define BCSR0_BPS_MASK  ((uint)0x0C000000)
-#define BCSR0_ISB_MASK  ((uint)0x01800000)
-#define BCSR0_DBGC_MASK ((uint)0x00600000)
-#define BCSR0_DBPC_MASK ((uint)0x00180000)
-#define BCSR0_EBDF_MASK ((uint)0x00060000)
-
-#define BCSR1_FLASH_EN           ((uint)0x80000000)
-#define BCSR1_DRAM_EN            ((uint)0x40000000)
-#define BCSR1_ETHEN              ((uint)0x20000000)
-#define BCSR1_IRDEN              ((uint)0x10000000)
-#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
-#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
-#define BCSR1_BCSR_EN            ((uint)0x02000000)
-#define BCSR1_RS232EN_1          ((uint)0x01000000)
-#define BCSR1_PCCEN              ((uint)0x00800000)
-#define BCSR1_PCCVCC0            ((uint)0x00400000)
-#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
-#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
-#define BCSR1_RS232EN_2          ((uint)0x00040000)
-#define BCSR1_SDRAM_EN           ((uint)0x00020000)
-#define BCSR1_PCCVCC1            ((uint)0x00010000)
-
-#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
-#define BCSR2_FLASH_PD_SHIFT	 28
-#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
-#define BCSR2_DRAM_PD_SHIFT      23
-#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
-#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
-
-#define BCSR3_DBID_MASK          ((ushort)0x3800)
-#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
-#define BCSR3_BREVNR0            ((ushort)0x0080)
-#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
-#define BCSR3_BREVN1             ((ushort)0x0008)
-#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
-
-#define BCSR4_ETHLOOP            ((uint)0x80000000)
-#define BCSR4_TFPLDL             ((uint)0x40000000)
-#define BCSR4_TPSQEL             ((uint)0x20000000)
-#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
-#ifdef CONFIG_MPC823
-#define BCSR4_USB_EN             ((uint)0x08000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860SAR
-#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
-#endif /* CONFIG_MPC860SAR */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_USB_SPEED          ((uint)0x04000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VCCO               ((uint)0x02000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VIDEO_ON           ((uint)0x00800000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
-#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VIDEO_RST          ((uint)0x00200000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHRST            ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_MODEM_EN           ((uint)0x00100000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
-#define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC850
-#define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC850 */
-
-#define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
-/*
- * MPC8xx CPM Options
- */
-#define CONFIG_SCC_ENET 1
-#define CONFIG_SCC2_ENET 1
-#undef  CONFIG_FEC_ENET
-#undef  CONFIG_CPM_IIC
-#undef  CONFIG_UCODE_PATCH
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-/* PCMCIA configuration */
-
-#define PCMCIA_MAX_SLOTS    1
-
-#ifdef CONFIG_MPC860
-#define PCMCIA_SLOT_A 1
-#endif
-
-#define CFG_DAUGHTERBOARD
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
deleted file mode 100644
index 2a986f0768..0000000000
--- a/include/configs/FADS850SAR.h
+++ /dev/null
@@ -1,416 +0,0 @@
- /*
-  * A collection of structures, addresses, and values associated with
-  * the Motorola 860T FADS board.  Copied from the MBX stuff.
-  * Magnus Damm added defines for 8xxrom and extended bd_info.
-  * Helmut Buchsbaum added bitvalues for BCSRx
-  *
-  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
-  */
-
-/*
- * 1999-nov-26: The FADS is using the following physical memorymap:
- *
- * ff020000 -> ff02ffff : pcmcia
- * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
- * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC850		1
-#define CONFIG_MPC850SAR	1
-#define CONFIG_FADS			1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-
-#if 0
-#define MPC8XX_FACT	10				/* Multiply by 10		*/
-#define MPC8XX_XIN	50000000		/* 50 MHz in	*/
-#else
-#define MPC8XX_FACT	12				/* Multiply by 12 */
-#define MPC8XX_XIN	4000000			/* 4 MHz in */
-#endif
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#if 1
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BOOTCOMMAND	"bootm 02880000"	/* autoboot command */
-#define CONFIG_BOOTARGS		" "
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR			0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
-#define CFG_FLASH_BASE		0x02800000
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
-#if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
-#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration						11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer  *
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << 20) | \
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
-				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-				SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-
-#define BCSR_ADDR		((uint) 0x02100000)
-#define BCSR_SIZE		((uint)(64 * 1024))
-
-#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
-#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CFG_MAMR		0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
-
-
-/* values according to the manual */
-
-
-#define PCMCIA_MEM_ADDR		((uint)0xff020000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-
-#define	BCSR0			((uint) (BCSR_ADDR + 00))
-#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
-#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
-#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
-#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
-
-/* FADS bitvalues by Helmut Buchsbaum
- * see MPC8xxADS User's Manual for a proper description
- * of the following structures
- */
-
-#define BCSR0_ERB       ((uint)0x80000000)
-#define BCSR0_IP        ((uint)0x40000000)
-#define BCSR0_BDIS      ((uint)0x10000000)
-#define BCSR0_BPS_MASK  ((uint)0x0C000000)
-#define BCSR0_ISB_MASK  ((uint)0x01800000)
-#define BCSR0_DBGC_MASK ((uint)0x00600000)
-#define BCSR0_DBPC_MASK ((uint)0x00180000)
-#define BCSR0_EBDF_MASK ((uint)0x00060000)
-
-#define BCSR1_FLASH_EN           ((uint)0x80000000)
-#define BCSR1_DRAM_EN            ((uint)0x40000000)
-#define BCSR1_ETHEN              ((uint)0x20000000)
-#define BCSR1_IRDEN              ((uint)0x10000000)
-#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
-#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
-#define BCSR1_BCSR_EN            ((uint)0x02000000)
-#define BCSR1_RS232EN_1          ((uint)0x01000000)
-#define BCSR1_PCCEN              ((uint)0x00800000)
-#define BCSR1_PCCVCC0            ((uint)0x00400000)
-#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
-#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
-#define BCSR1_RS232EN_2          ((uint)0x00040000)
-#define BCSR1_SDRAM_EN           ((uint)0x00020000)
-#define BCSR1_PCCVCC1            ((uint)0x00010000)
-
-#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
-#define BCSR2_FLASH_PD_SHIFT	 28
-#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
-#define BCSR2_DRAM_PD_SHIFT      23
-#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
-#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
-
-#define BCSR3_DBID_MASK          ((ushort)0x3800)
-#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
-#define BCSR3_BREVNR0            ((ushort)0x0080)
-#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
-#define BCSR3_BREVN1             ((ushort)0x0008)
-#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
-
-#define BCSR4_ETHLOOP            ((uint)0x80000000)
-#define BCSR4_TFPLDL             ((uint)0x40000000)
-#define BCSR4_TPSQEL             ((uint)0x20000000)
-#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
-#ifdef CONFIG_MPC823
-#define BCSR4_USB_EN             ((uint)0x08000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860SAR
-#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
-#endif /* CONFIG_MPC860SAR */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_USB_SPEED          ((uint)0x04000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VCCO               ((uint)0x02000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VIDEO_ON           ((uint)0x00800000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
-#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
-#define BCSR4_VIDEO_RST          ((uint)0x00200000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHRST            ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-#define BCSR4_MODEM_EN           ((uint)0x00100000)
-#define BCSR4_DATA_VOICE         ((uint)0x00080000)
-
-#define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-/* PCMCIA configuration */
-
-#define PCMCIA_MAX_SLOTS    2
-
-#ifdef CONFIG_MPC860
-#define PCMCIA_SLOT_A 1
-#endif
-
-#define CFG_DAUGHTERBOARD
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h
deleted file mode 100644
index 18de6b00e7..0000000000
--- a/include/configs/FADS860T.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-  * A collection of structures, addresses, and values associated with
-  * the Motorola 860T FADS board.  Copied from the MBX stuff.
-  * Magnus Damm added defines for 8xxrom and extended bd_info.
-  * Helmut Buchsbaum added bitvalues for BCSRx
-  *
-  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
-  *
-  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
-  *
-  * Values common to all FADS family boards are in board/fads/fads.h
-  */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* board type */
-#define CONFIG_FADS		1       /* old/new FADS + new ADS */
-
-/* processor type */
-#define CONFIG_MPC860T		1       /* 860T */
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		38400
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#if 0 /* old FADS */
-# define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
-#else /* new FADS */
-# define CFG_8XX_FACT		10	/* 5 MHz oscillator on EXTCLK */
-#endif
-
-#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-#define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ              1
-
-#include "fads.h"
-
-#ifdef USE_REAL_FLASH_VALUES
-/*
- * These values fit our FADS860T ...
- * The "default" behaviour with 1Mbyte initial doesn't work for us!
- */
-#undef CFG_OR0_PRELIM
-#undef CFG_BR0_PRELIM
-#define CFG_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
-#define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
-#endif
-
-#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
deleted file mode 100644
index 8babee140f..0000000000
--- a/include/configs/FLAGADM.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_FLAGADM		1	/* ...on a FLAGA DM	*/
-#define CONFIG_8xx_GCLK_FREQ 48000000	/*48MHz*/
-
-#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1		*/
-#define CONFIG_8xx_CONS_SMC2	1
-#undef	CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-
-#undef	CONFIG_CLOCKS_IN_MHZ
-
-#if 0
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp"
-#define CONFIG_BOOTCOMMAND							\
-   "setenv bootargs root=/dev/ram ip=off panic=1;"     \
-   "bootm 40040000 400e0000"
-#else
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp panic=1"
-#define CONFIG_BOOTCOMMAND	"bootp 0x400000; bootm 0x400000"
-#endif /* 0|1*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-/*#define	CONFIG_WATCHDOG*/	/* watchdog enabled		*/
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
-		CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
-		CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"EEG> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x40040000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_ENV_IS_IN_FLASH	1
-/* This is a litlebit wasteful, but one sector is 128kb and we have to
- * assigne a whole sector for the environment, so that we can safely
- * erase and write it without disturbing the boot sector
- */
-#define CFG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector	*/
-#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
-							SIUMCR_MLRC01 | SIUMCR_GB5E)
-#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit miltiplier of 0x00b i.e. operation clock is
- * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
- */
-#define CFG_PLPRCR	(0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-#define CFG_DER 0
-
-/*
- * In the Flaga DM we have:
- * Flash on BR0/OR0/CS0a at 0x40000000
- * Display on BR1/OR1/CS1 at 0x20000000
- * SDRAM on BR2/OR2/CS2 at 0x00000000
- * Free BR3/OR3/CS3
- * DSP1 on BR4/OR4/CS4 at 0x80000000
- * DSP2 on BR5/OR5/CS5 at 0xa0000000
- *
- * For now we just configure the Flash and the SDRAM and leave the others
- * untouched.
-*/
-
-#define CFG_FLASH_PROTECTION 0
-
-#define FLASH_BASE0		0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_OR_AM		0xff000000	/* OR addr mask */
-#define CFG_OR_ATM		0x00006000
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
-				 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
-
-#define CFG_OR0_PRELIM	(CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2			0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	( 0x00000800 )
-
-#define CFG_OR2_PRELIM	(CFG_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR2_PRELIM	((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define CFG_BR2			CFG_BR2_PRELIM
-#define CFG_OR2			CFG_OR2_PRELIM
-
-/*
- * MAMR settings for SDRAM
- */
-#define CFG_MAMR_48_SDR (CFG_MAMR_PTA |	 MAMR_WLFA_1X | MAMR_RLFA_1X  \
-					| MAMR_G0CLA_A11)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	0x0F000000
-
-/*
-   * BR4 and OR4 (DSP1)
-   *
-   * We do not wan't preliminary setup of the DSP, anyway we need the
-   * UPMB setup correctly before we can access the DSP.
-   *
-*/
-#define DSP_BASE 0x80000000
-
-#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
-#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
deleted file mode 100644
index db42fd06fe..0000000000
--- a/include/configs/G2000.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_G2000		1	/* ...on a PLU405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
-
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE		115200
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_PREBOOT
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off\0"				\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"panic=1\0"						\
-	"flash_nfs=run nfsargs addip addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addmisc;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addmisc;bootm\0"			\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/g2000/pImage\0"				\
-	"kernel_addr=ff800000\0"				        \
-	"ramdisk_addr=ff900000\0"				        \
-	"pciconfighost=yes\0"				                \
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_NET_MULTI	1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
-
-#if 0 /* test-only */
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#endif
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#if 0 /* test-only */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*----------------------------------------------------------------------------*/
-/* adding Ethernet setting:  FTS OUI 00:11:0B */
-/*----------------------------------------------------------------------------*/
-#define CONFIG_ETHADDR          00:11:0B:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
-#define CONFIG_IPADDR		10.48.8.178
-#define CONFIG_IP1ADDR		10.48.8.188
-#define CONFIG_NETMASK		255.255.255.128
-#define CONFIG_SERVERIP		10.48.8.138
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR	0x68
-
-#if 0 /* test-only */
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if 0 /* APC405 */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
-#else /* G2000 */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
-#endif
-
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
-
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFFC0000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#if 1 /* test-only */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#else	/* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CFG_ENV_ADDR		0xFFFA0000 /* environment starts before u-boot */
-#define CFG_ENV_SECT_SIZE	0x20000	/* 128k bytes may be used for env vars*/
-
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-/* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Intel Strata Flash) initialization                            */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 ( Power TAU) initialization               */
-/* #define CFG_EBC_PB1AP           0x04041000 */
-/* #define CFG_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-#define CFG_EBC_PB1AP           0x00000000
-#define CFG_EBC_PB1CR           0x00000000
-
-/* Memory Bank 2 (Intel Flash) initialization                 */
-#define CFG_EBC_PB2AP           0x00000000
-#define CFG_EBC_PB2CR           0x00000000
-
-/* Memory Bank 3 (NAND) initialization                        */
-#define CFG_EBC_PB3AP           0x92015480
-#define CFG_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
-
-/* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CFG_EBC_PB4AP           0x00000000
-#define CFG_EBC_PB4CR           0x00000000  /* leave it blank  */
-
-#define CFG_NAND_BASE   0xF4000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- *
- * following GPIO setting changed for G20000, 080304
- */
-#define CFG_GPIO0_OSRH          0x40005555
-#define CFG_GPIO0_OSRL          0x40000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FF8014
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_266_66_33_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_66_33_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
deleted file mode 100644
index 6613f90a77..0000000000
--- a/include/configs/GEN860T.h
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Keith Outwater, keith_outwater@mvis.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config_GEN860T.h - board specific configuration options
- */
-
-#ifndef __CONFIG_GEN860T_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC860
-#define CONFIG_GEN860T
-
-/*
- * Identify the board
- */
-#if !defined(CONFIG_SC)
-#define CONFIG_IDENT_STRING				" B2"
-#else
-#define CONFIG_IDENT_STRING				" SC"
-#endif
-
-/*
- * Don't depend on the RTC clock to determine clock frequency -
- * the 860's internal rtc uses a 32.768 KHz clock which is
- * generated by the DS1337 - and the DS1337 clock can be turned off.
- */
-#if !defined(CONFIG_SC)
-#define	CONFIG_8xx_GCLK_FREQ			66600000
-#else
-#define	CONFIG_8xx_GCLK_FREQ			48000000
-#endif
-
-/*
- * The RS-232 console port is on SMC1
- */
-#define	CONFIG_8xx_CONS_SMC1
-#define CONFIG_BAUDRATE					38400
-
-/*
- * Set allowable console baud rates
- */
-#define CFG_BAUDRATE_TABLE				{ 9600,		\
-							 		 	  19200,	\
-							 		 	  38400,	\
-									 	  57600,	\
-									 	  115200,	\
-										}
-
-/*
- * Print console information
- */
-#undef	 CFG_CONSOLE_INFO_QUIET
-
-/*
- * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
- */
-#define CONFIG_BOOTDELAY				5
-
-/*
- * Pass the clock frequency to the Linux kernel in units of MHz
- */
-#define	CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_PREBOOT		\
-	"echo;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-
-/*
- * Turn off echo for serial download by default.  Allow baud rate to be changed
- * for downloads
- */
-#undef	CONFIG_LOADS_ECHO
-#define	CFG_LOADS_BAUD_CHANGE
-
-/*
- * Set default load address for tftp network downloads
- */
-#define	CFG_TFTP_LOADADDR				0x01000000
-
-/*
- * Turn off the watchdog timer
- */
-#undef	CONFIG_WATCHDOG
-
-/*
- * Do not reboot if a panic occurs
- */
-#define CONFIG_PANIC_HANG
-
-/*
- * Enable the status LED
- */
-#define	CONFIG_STATUS_LED
-
-/*
- * Reset address. We pick an address such that when an instruction
- * is executed at that address, a machine check exception occurs
- */
-#define CFG_RESET_ADDRESS				((ulong) -1)
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \
-									  	  CONFIG_BOOTP_BOOTFILESIZE   \
-										)
-
-/*
- * The GEN860T network interface uses the on-chip 10/100 FEC with
- * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
- * MII address is hardwired on the board to zero.
- */
-#define CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY
-#define CONFIG_MII
-#define CONFIG_PHY_ADDR         		0
-
-/*
- * Set default IP stuff just to get bootstrap entries into the
- * environment so that we can autoscript the full default environment.
- */
-#define CONFIG_ETHADDR					9a:52:63:15:85:25
-#define CONFIG_SERVERIP					10.0.4.201
-#define CONFIG_IPADDR					10.0.4.111
-
-/*
- * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
- * the MPC860T I2C interface.
- */
-#define CFG_I2C_EEPROM_ADDR				0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
-#define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
-#define CFG_ENV_EEPROM_SIZE				(32 * 1024)
-
-/*
- * Enable I2C and select the hardware/software driver
- */
-#define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
-#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/
-
-#ifdef CONFIG_HARD_I2C
-#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
-#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
-#endif
-
-#ifdef CONFIG_SOFT_I2C
-#define PB_SCL				0x00000020		/* PB 26					*/
-#define PB_SDA				0x00000010		/* PB 27 					*/
-#define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ			((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-								else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-								else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY			udelay(5)		/* 1/4 I2C clock duration	*/
-#endif
-
-/*
- * Allow environment overwrites by anyone
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if !defined(CONFIG_SC)
-/*
- * The MPC860's internal RTC is horribly broken in rev D masks. Three
- * internal MPC860T circuit nodes were inadvertently left floating; this
- * causes KAPWR current in power down mode to be three orders of magnitude
- * higher than specified in the datasheet (from 10 uA to 10 mA).  No
- * reasonable battery can keep that kind RTC running during powerdown for any
- * length of time, so we use an external RTC on the I2C bus instead.
- */
-#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR				0x68
-
-#else
-/*
- * No external RTC on SC variant, so we're stuck with the internal one.
- */
-#define	CONFIG_RTC_MPC8xx
-#endif
-
-/*
- * Power On Self Test support
- */
-#define CONFIG_POST			  ( CFG_POST_CACHE		| \
-								CFG_POST_MEMORY		| \
-								CFG_POST_CPU		| \
-								CFG_POST_UART		| \
-								CFG_POST_SPR )
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG		0
-#endif
-
-/*
- * List of available monitor commands.  Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define BASE_CONFIG_COMMANDS	( CONFIG_CMD_DFL	| \
-								CFG_CMD_ASKENV	| \
-								CFG_CMD_DHCP	| \
-								CFG_CMD_I2C		| \
-								CFG_CMD_EEPROM	| \
-								CFG_CMD_REGINFO	| \
-								CFG_CMD_IMMAP	| \
-								CFG_CMD_ELF		| \
-								CFG_CMD_DATE	| \
-								CFG_CMD_FPGA	| \
-								CFG_CMD_MII 	| \
-								CFG_CMD_BEDBUG	| \
-								CFG_CMD_POST_DIAG )
-
-#if !defined(CONFIG_SC)
-#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
-#else
-#define CONFIG_COMMANDS	BASE_CONFIG_COMMANDS
-#endif
-
-/*
- * There is no IDE/PCMCIA hardware support on the board.
- */
-#undef  CONFIG_IDE_PCMCIA
-#undef  CONFIG_IDE_LED
-#undef  CONFIG_IDE_RESET
-
-/*
- * Enable the call to misc_init_r() for miscellaneous platform
- * dependent initialization.
- */
-#define CONFIG_MISC_INIT_R
-
-/*
- * Enable call to last_stage_init() so we can twiddle some LEDS :)
- */
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * Virtex2 FPGA configuration support
- */
-#define CONFIG_FPGA_COUNT		1
-#define CONFIG_FPGA				CFG_XILINX_VIRTEX2
-#define CFG_FPGA_PROG_FEEDBACK
-
-
-/************************************************************************
- * This must be included AFTER the definition of any CONFIG_COMMANDS
- */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-/*
- * Verbose help from command monitor.
- */
-#define	CFG_LONGHELP
-#if !defined(CONFIG_SC)
-#define	CFG_PROMPT			"B2> "
-#else
-#define	CFG_PROMPT			"SC> "
-#endif
-
-
-/*
- * Use the "hush" command parser
- */
-#define	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-
-/*
- * Set buffer size for console I/O
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE			1024
-#else
-#define	CFG_CBSIZE			256
-#endif
-
-/*
- * Print buffer size
- */
-#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-/*
- * Maximum number of arguments that a command can accept
- */
-#define	CFG_MAXARGS			16
-
-/*
- * Boot argument buffer size
- */
-#define CFG_BARGSIZE		CFG_CBSIZE
-
-/*
- * Default memory test range
- */
-#define CFG_MEMTEST_START	0x0100000
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START  + (128 * 1024))
-
-/*
- * Select the more full-featured memory test
- */
-#define	CFG_ALT_MEMTEST
-
-/*
- * Default load address
- */
-#define	CFG_LOAD_ADDR		0x01000000
-
-/*
- * Set decrementer frequency (1 ms ticks)
- */
-#define	CFG_HZ				1000
-
-/*
- * Device memory map (after SDRAM remap to 0x0):
- *
- * CS		Device				Base Addr	Size
- * ----------------------------------------------------
- * CS0*		Flash				0x40000000	64 M
- * CS1*		SDRAM				0x00000000	16 M
- * CS2*		Disk-On-Chip		0x50000000	32 K
- * CS3*		FPGA				0x60000000	64 M
- * CS4*		SelectMap			0x70000000	32 K
- * CS5*		Mil-Std 1553 I/F	0x80000000	32 K
- * CS6*		Unused
- * CS7*		Unused
- * IMMR		860T Registers		0xfff00000
- */
-
-/*
- * Base addresses and block sizes
- */
-#define CFG_IMMR			0xFF000000
-
-#define SDRAM_BASE			0x00000000
-#define SDRAM_SIZE			(64 * 1024 * 1024)
-
-#define FLASH_BASE			0x40000000
-#define FLASH_SIZE			(16 * 1024 * 1024)
-
-#define DOC_BASE			0x50000000
-#define DOC_SIZE			(32 * 1024)
-
-#define FPGA_BASE			0x60000000
-#define FPGA_SIZE			(64 * 1024 * 1024)
-
-#define SELECTMAP_BASE		0x70000000
-#define SELECTMAP_SIZE		(32 * 1024)
-
-#define M1553_BASE			0x80000000
-#define M1553_SIZE			(64 * 1024)
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR		CFG_IMMR
-#define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
-#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE			SDRAM_BASE
-
-/*
- * FLASH organization
- */
-#define CFG_FLASH_BASE			FLASH_BASE
-#define CFG_FLASH_SIZE			FLASH_SIZE
-#define CFG_FLASH_SECT_SIZE		(128 * 1024)
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		128
-
-/*
- * The timeout values are for an entire chip and are in milliseconds.
- * Yes I know that the write timeout is huge.  Accroding to the
- * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
- * case VCC and temp after 100K programming cycles.  It works out
- * to 280 minutes (might as well be forever).
- */
-#define CFG_FLASH_ERASE_TOUT	(CFG_MAX_FLASH_SECT * 5000)
-#define CFG_FLASH_WRITE_TOUT	(CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
-
-/*
- * Allow direct writes to FLASH from tftp transfers (** dangerous **)
- */
-#define	CFG_DIRECT_FLASH_TFTP
-
-/*
- * Reserve memory for U-Boot.
- */
-#define CFG_MAX_UBOOT_SECTS		4
-#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-
-/*
- * Select environment placement.  NOTE that u-boot.lds must
- * be edited if this is changed!
- */
-#undef	CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_IS_IN_EEPROM
-
-#if defined(CFG_ENV_IS_IN_EEPROM)
-#define CFG_ENV_SIZE			(2 * 1024)
-#define CFG_ENV_OFFSET			(CFG_ENV_EEPROM_SIZE - (8 * 1024))
-#else
-#define CFG_ENV_SIZE			0x1000
-#define CFG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE
-
-/*
- * This ultimately gets passed right into the linker script, so we have to
- * use a number :(
- */
-#define CFG_ENV_OFFSET			0x060000
-#endif
-
-/*
- * Reserve memory for malloc()
- */
-#define	CFG_MALLOC_LEN		(128 * 1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 * 1024 * 1024)
-
-/*
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
-#endif
-
-/*------------------------------------------------------------------------
- * SYPCR - System Protection Control							UM 11-9
- * -----------------------------------------------------------------------
- * SYPCR can only be written once after reset!
- *
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
-					  SYPCR_SWE 	| \
-					  SYPCR_SWRI	| \
-					  SYPCR_SWP		  \
-					)
-#else
-#define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
-					  SYPCR_SWP		  \
-					)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration							UM 11-6
- *-----------------------------------------------------------------------
- * Set debug pin mux, enable SPKROUT and GPLB5*.
- */
-#define CFG_SIUMCR	( SIUMCR_DBGC11 | \
-					  SIUMCR_DBPC11 | \
-					  SIUMCR_MLRC11	| \
-					  SIUMCR_GB5E	  \
-					)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control							UM 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freeze enabled
- */
-#define CFG_TBSCR	( TBSCR_REFA | \
-					  TBSCR_REFB | \
-					  TBSCR_TBF	   \
-					)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register			UM 11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	( RTCSC_SEC	| \
-					  RTCSC_ALR | \
-					  RTCSC_RTF | \
-					  RTCSC_RTE	  \
-					)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control				UM 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	( PISCR_PS		| \
-					  PISCR_PITF	  \
-					)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register			UM 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit. Set MF for 1:2:1 mode.
- */
-#define CFG_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
-					  PLPRCR_SPLSS	| \
-					  PLPRCR_TEXPS	| \
-					  PLPRCR_TMIST	  \
-					)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register				UM 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK   SCCR_EBDF11
-
-#if !defined(CONFIG_SC)
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
-					  SCCR_DFNL000		| \
-					  SCCR_DFNH000		  \
-					)
-#else
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
-					  SCCR_DFNL000		| \
-					  SCCR_DFNH000		| \
-					  SCCR_RTDIV		| \
-					  SCCR_RTSEL		  \
-					)
-#endif
-
-/*-----------------------------------------------------------------------
- * DER - Debug Enable Register									UM 37-46
- *-----------------------------------------------------------------------
- * Mask all events that can cause entry into debug mode
- */
-#define CFG_DER				0
-
-/*
- * Initialize Memory Controller:
- *
- * BR0 and OR0 (FLASH memory)
- */
-#define FLASH_BASE0_PRELIM	FLASH_BASE
-
-/*
- * Flash address mask
- */
-#define CFG_PRELIM_OR_AM	0xfe000000
-
-/*
- * FLASH timing:
- * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
- */
-#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
-							  OR_ACS_DIV2	| \
-							  OR_BI			| \
-							  OR_SCY_2_CLK	| \
-							  OR_TRLX		| \
-							  OR_EHTR		  \
-							)
-
-#define CFG_OR0_PRELIM	( CFG_PRELIM_OR_AM		| \
-						  CFG_OR_TIMING_FLASH	  \
-						)
-
-#define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
-						  BR_MS_GPCM						| \
-						  BR_PS_8							| \
-						  BR_V 								  \
-						)
-
-/*
- * SDRAM configuration
- */
-#define CFG_OR1_AM	0xfc000000
-#define CFG_OR1		( (CFG_OR1_AM & OR_AM_MSK)	| \
-					  OR_CSNT_SAM				  \
-					)
-
-#define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
-					  BR_MS_UPMA 				| \
-					  BR_PS_32	 				| \
-					  BR_V 						  \
-					)
-
-/*
- * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
- * of 256 MBit SDRAM
- */
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16
-
-/*
- * Periodic timer for refresh @ 33 MHz system clock
- */
-#define CFG_MAMR_PTA	64
-
-/*
- * MAMR settings for SDRAM
- */
-#define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
-						  MAMR_PTAE	    			| \
-						  MAMR_AMA_TYPE_1			| \
-						  MAMR_DSA_1_CYCL 			| \
-						  MAMR_G0CLA_A10			| \
-						  MAMR_RLFA_1X				| \
-						  MAMR_WLFA_1X				| \
-						  MAMR_TLFA_4X				  \
-						)
-
-/*
- * CS2* configuration for Disk On Chip:
- * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
- * no burst.
- */
-#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \
-						  OR_CSNT_SAM				| \
-						  OR_ACS_DIV2				| \
-						  OR_BI						| \
-						  OR_SCY_2_CLK				| \
-						  OR_TRLX					| \
-						  OR_EHTR					  \
-						)
-
-#define CFG_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
-						  BR_PS_8					| \
-						  BR_MS_GPCM				| \
-						  BR_V						  \
-						)
-
-/*
- * CS3* configuration for FPGA:
- * 33 MHz bus with SCY=15, no burst.
- * The FPGA uses TA and TEA to terminate bus cycles, but we
- * clear SETA and set the cycle length to a large number so that
- * the cycle will still complete even if there is a configuration
- * error that prevents TA from asserting on FPGA accesss.
- */
-#define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
-						  OR_SCY_15_CLK				| \
-						  OR_BI 					  \
-						)
-
-#define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
-						  BR_PS_32					| \
-						  BR_MS_GPCM				| \
-						  BR_V		  				  \
-						)
-/*
- * CS4* configuration for FPGA SelectMap configuration interface.
- * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
- * of GCLK1_50
- */
-#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \
-						  OR_G5LS						| \
-						  OR_BI							  \
-						)
-
-#define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
-						  BR_PS_8						| \
-						  BR_MS_UPMB					| \
-						  BR_V			  				  \
-						)
-
-/*
- * CS5* configuration for Mil-Std 1553 databus interface.
- * 33 MHz bus, GPCM, no burst.
- * The 1553 interface  uses TA and TEA to terminate bus cycles,
- * but we clear SETA and set the cycle length to a large number so that
- * the cycle will still complete even if there is a configuration
- * error that prevents TA from asserting on FPGA accesss.
- */
-#define CFG_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
-						  OR_SCY_15_CLK				| \
-						  OR_EHTR					| \
-						  OR_TRLX					| \
-						  OR_CSNT_SAM				| \
-						  OR_BI						  \
-						)
-
-#define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
-						  BR_PS_16					| \
-						  BR_MS_GPCM				| \
-						  BR_V			  			  \
-						)
-
-/*
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02	/* Software reboot					*/
-
-/*
- * Disk On Chip (millenium) configuration
- */
-#if !defined(CONFIG_SC)
-#define CFG_MAX_DOC_DEVICE	1
-#undef	CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#undef	CFG_DOC_PASSIVE_PROBE
-#endif
-
-/*
- * FEC interrupt assignment
- */
-#define FEC_INTERRUPT   SIU_LEVEL1
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif	/* __CONFIG_GEN860T_H */
-
-/* vim: set ts=4 tw=78 ai shiftwidth=4: */
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
deleted file mode 100644
index 8c01d97fa3..0000000000
--- a/include/configs/GENIETV.h
+++ /dev/null
@@ -1,354 +0,0 @@
- /*
-  * A collection of structures, addresses, and values associated with
-  * the Motorola 860T FADS board.  Copied from the MBX stuff.
-  * Magnus Damm added defines for 8xxrom and extended bd_info.
-  * Helmut Buchsbaum added bitvalues for BCSRx
-  *
-  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
-  */
-
-/*
- * The GENIETV is using the following physical memorymap (copied from
- * the FADS configuration):
- *
- * ff020000 -> ff02ffff : pcmcia
- * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * 30000000 -> 300fffff : flash      connected to CS0
- * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
- *
- * CS pins are connected as follows:
- *
- * CS0 -512Kb boot flash
- * CS1 - SDRAM #1
- * CS2 - SDRAM #2
- * CS3 - Flash #1
- * CS4 - Flash #2
- * CS5 - Lon (if present)
- * CS6 - PCMCIA #1
- * CS7 - PCMCIA #2
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
-#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
-
-#define CFG_ALLOC_DPRAM			/* Use dynamic DPRAM allocation */
-
-#define CFG_AUTOLOAD		"n"	/* No autoload */
-
-/*#define CONFIG_VIDEO		1	/  To enable the video initialization */
-/*#define CONFIG_VIDEO_ADDR	0x00200000 */
-/*#define CONFIG_HARD_I2C	1	/  I2C with hardware support */
-/*#define CONFIG_PCMCIA		1	/  To enable the PCMCIA initialization */
-
-/*#define CFG_PCMCIA_IO_ADDR	0xff020000 */
-/*#define CFG_PCMCIA_IO_SIZE	0x10000 */
-/*#define CFG_PCMCIA_MEM_ADDR	0xe0000000 */
-/*#define CFG_PCMCIA_MEM_SIZE	0x10000 */
-
-/* Video related */
-
-/*#define CONFIG_VIDEO_LOGO			1	/  Show the logo */
-/*#define CONFIG_VIDEO_ENCODER_AD7177		1	/  Enable this encoder */
-/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR	0xF4	/  ALSB to ground */
-
-/* Wireless 56Khz 4PPM keyboard on SMCx */
-
-/*#define CONFIG_KEYBOARD		0 */
-/*#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/  SMC to use (0 indexed) */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#include <mpc8xx_irq.h>
-
-#define CONFIG_GENIETV		1
-#define CONFIG_MPC823		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-
-#define MPC8XX_FACT	12 			/* Multiply by 12	*/
-#define MPC8XX_XIN	5000000			/* 4 MHz clock 		*/
-
-#define MPC8XX_HZ 	((MPC8XX_XIN) * (MPC8XX_FACT))
-#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#if 1
-#define CONFIG_BOOTDELAY	1	/* autoboot after 2 seconds	*/
-#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
-#define CONFIG_BOOTARGS		""
-#define CONFIG_BOOTCOMMAND							\
-"bootp; tftp; "									\
-"setenv bootargs console=tty0 console=ttyS0 " 					\
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
-"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" 	\
-"bootm "
-#else
-#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
-#endif
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		8		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02800000
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
-#if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x10000	/* Offset of Environment Sector 	*/
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector (64k)*/
-
-/* values according to the manual */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration						11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- *
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer  *
- * interrupt status bit - leave PLL multiplication factor unchanged !
- *
- * #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
-				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-				SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0(FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0		*/
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask 	*/
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask (512Kb) */
-
-/* FLASH timing */
-#define CFG_OR_TIMING_FLASH 	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				OR_SCY_15_CLK | OR_TRLX )
-
-/*#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH) */
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 		/* 0xfff80ff4 */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)	/* 0x02800401 */
-
-/*
- * BR1/2 and OR1/2 (SDRAM)
-*/
-
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define SDRAM_MAX_SIZE		0x04000000	/* 64Mb bank */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* First bank */
-#define SDRAM_BASE2_PRELIM	0x10000000	/* Second bank */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MBMR_PTB		0x5d		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32
-/*
- * MBMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
-			MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
-			| MAMR_TLFA_4X)	/* 0x5d802114 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
-/*
- * MPC8xx CPM Options
- */
-#define CONFIG_SCC_ENET 1
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-/* PCMCIA configuration */
-
-#define PCMCIA_MAX_SLOTS    1
-#define PCMCIA_SLOT_B 1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
deleted file mode 100644
index 03b9659497..0000000000
--- a/include/configs/GTH.h
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
-  * Parameters for GTH board
-  * Based on FADS860T
-  * by thomas.lange@corelatus.com
-
-  * A collection of structures, addresses, and values associated with
-  * the Motorola 860T FADS board.  Copied from the MBX stuff.
-  * Magnus Damm added defines for 8xxrom and extended bd_info.
-  * Helmut Buchsbaum added bitvalues for BCSRx
-  *
-  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
-  */
-
-/*
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * e0000000 -> ennnnnnn : pcmcia
- * 98000000 -> 983nnnnn : FPGA 4MB
- * 90000000 -> 903nnnnn : FPGA 4MB
- * 80000000 -> 80nnnnnn : flash      connected to CS0, final ( real ) location
- * 00000000 -> nnnnnnnn : sdram
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#include <mpc8xx_irq.h>
-
-#define CONFIG_MPC860		1
-#define CONFIG_MPC860T		1
-#define CONFIG_GTH		1
-
-#define CONFIG_MISC_INIT_R      1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#define MPC8XX_FACT		3		/* Multiply by 3 */
-#define MPC8XX_XIN		16384000	/* 16.384 MHz */
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after 0 seconds	*/
-
-#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-
-#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
-
-#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#if 0
-/* Net boot */
-/* Loads a tftp image and starts it */
-#define CONFIG_BOOTCOMMAND	"bootp;bootm 100000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"panic=1"
-#else
-/* Compact flash boot */
-#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
-#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
-#endif
-
-/* Enable watchdog */
-#define CONFIG_WATCHDOG 1
-
-/* choose SCC1 ethernet (10BASET on motherboard)
- * or FEC ethernet (10/100 on daughterboard)
- */
-#if 1
-#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
-#undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
-#define CFG_DISCOVER_PHY
-#else
-#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define CFG_DISCOVER_PHY
-#endif
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#define CONFIG_COMMANDS               (CONFIG_CMD_DFL | CFG_CMD_IDE)
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-/* Default location to load data from net */
-#define CFG_LOAD_ADDR	 	0x100000
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR			0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-
-#define CFG_FLASH_BASE		0x80000000
-
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
-
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-
-#define CFG_MONITOR_BASE TEXT_BASE
-
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH 1
-#undef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_OFFSET		0x000E0000
-#define	CFG_ENV_SIZE		 0x4000 	/* Total Size of Environment Sector	*/
-
-#define CFG_ENV_SECT_SIZE	0x50000	/* see README - env sector total size	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-
-/*FIXME dont use for now */
-/*#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-/*#define CFG_RTCSC	(RTCSC_RTF) */
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-/* PITE */
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-/* FIXME check values */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-
-#define CFG_REMAP_OR_AM		0xFF800000	/* 4 MB OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-#define FPGA_2_BASE 0x90000000
-#define FPGA_3_BASE 0x98000000
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_ETHADDR          DE:AD:BE:EF:00:01    /* Ethernet address */
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_gth)
-
-#ifdef CONFIG_MPC860
-#define PCMCIA_SLOT_A 1
-#define CONFIG_PCMCIA_SLOT_A 1
-#endif
-
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-#define CONFIG_IDE_8xx_PCCARD       1       /* Use IDE with PC Card Adapter */
-#undef  CONFIG_IDE_8xx_DIRECT               /* Direct IDE    not supported  */
-#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
-#undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
-
-#define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
-#define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
-
-#define CFG_ATA_IDE0_OFFSET     0x0000
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
-/* Offset for data I/O                  */
-#define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
-
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ       /* Force it - dont measure it */
-
-#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
-#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
-#define PA_FL_CE     ((u16)0x1000) /* PA 3 */
-
-#define PB_ID_GND    ((u32)1) /* PB 31 */
-#define PB_REV_1     ((u32)2) /* PB 30 */
-#define PB_REV_0     ((u32)4) /* PB 29 */
-#define PB_BLUE_LED  ((u32)0x400) /* PB 21 */
-#define PB_EEPROM    ((u32)0x800) /* PB 20 */
-#define PB_ID_3      ((u32)0x2000) /* PB 18 */
-#define PB_ID_2      ((u32)0x4000) /* PB 17 */
-#define PB_ID_1      ((u32)0x8000) /* PB 16 */
-#define PB_ID_0      ((u32)0x10000) /* PB 15 */
-
-/* NOTE. This is reset for 100Mbit port only */
-#define PC_ENET100_RESET	((ushort)0x0080) /* PC 8 */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
deleted file mode 100644
index dc40ebc861..0000000000
--- a/include/configs/HH405.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_HH405		1	/* ...on a HH405 board 	        */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT	        "autoupd"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"pciconfighost=1\0"						\
-	""
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_NET_MULTI	1
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * Video console
- */
-#define CONFIG_VIDEO			/* for sm501 video support	*/
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#if 0
-#define CONFIG_VIDEO_SM501_32BPP
-#else
-#define CONFIG_VIDEO_SM501_16BPP
-#endif
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
-#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
-
-#define ADD_BMP_CMD		CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD		0
-#endif /* CONFIG_VIDEO */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				ADD_BMP_CMD	| \
-				CFG_CMD_EEPROM  )
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-#undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
-
-#undef  CFG_CONSOLE_INFO_QUIET          /* print console @ startup	*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1338
-#define CFG_I2C_RTC_ADDR	0x68
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
-
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#if 0 /* test-only */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#else
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#endif
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#define CFG_EEPROM_WREN         1
-
-#if 1 /* test-only */
-/* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last	5 bits of the address	*/
-#endif
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
-#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
-#define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (Epson LCD) initialization                                     */
-#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
-#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
-#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
-#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
-
-/*-----------------------------------------------------------------------
- * Universal Interrupt Controller (UIC) Setup
- */
-
-/*
- * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
- */
-#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_EXT6)
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
-
-/* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x000
-
-/* FPGA Control Reg */
-#define CFG_FPGA_CTRL_REV0      0x0001
-#define CFG_FPGA_CTRL_REV1      0x0002
-#define CFG_FPGA_CTRL_VGA0_BL   0x0004
-#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define CFG_FPGA_CTRL_CF_RESET  0x0040
-#define CFG_FPGA_CTRL_PS2_PWR   0x0080
-#define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
-#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
-#define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
-#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
-
-#define CFG_FPGA_STATUS_CF_DETECT 0x8000
-
-#define LCD_CLK_OFF             0x0000      /* Off                           */
-#define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
-#define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
-#define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
-#define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
-#define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
-#define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
-#define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
-
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555440
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0017
-
-#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
-#define CFG_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
-#define CFG_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
-#define CFG_LCD0_RST		(0x80000000 >> 30)
-#define CFG_LCD1_RST		(0x80000000 >> 31)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
deleted file mode 100644
index 6864740773..0000000000
--- a/include/configs/HIDDEN_DRAGON.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_HIDDEN_DRAGON	1
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX	3		/* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-				  CFG_CMD_EEPROM | \
-				  CFG_CMD_ELF	| \
-				  CFG_CMD_I2C	| \
-				  CFG_CMD_NET	| \
-				  CFG_CMD_PCI	| \
-				  CFG_CMD_PING	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
-
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define PCI_ENET1_IOADDR	0x81000000
-#define PCI_ENET1_MEMADDR	0x81000000
-
-#define CONFIG_RTL8139
-#define _IO_BASE	    0x00000000
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x)	    (x)
-/* Make sure the ethaddr can be overwritten
-   TODO: Remove this on final product
-*/
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-#endif
-
-#define CFG_FLASH_BASE		0xFFE00000
-#define CFG_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CFG_EUMB_ADDR		0xFC000000
-
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
-
-#define CFG_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x00200000
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* processor board flash	*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly.  Please review!"
-#define I2C_PORT		3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else	iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else	iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
-
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/* TODO: Change this to VIA686A */
-
-/*
- * NS87308 Configuration
- */
-#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
-
-#define CFG_NS87308_BADDR_10	1
-
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
-
-#undef	CFG_NS87308_PS2MOD
-
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CFG_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
-#else
-#define CFG_NS16550_CLK		1843200
-#endif
-
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
-
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
-#endif
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/* values according to the manual */
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
deleted file mode 100644
index f84e356216..0000000000
--- a/include/configs/HUB405.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_HUB405		1	/* ...on a HUB405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#undef	CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: UART) initialization			*/
-#if 0
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#else
-#define CFG_EBC_PB2AP		0x92015480
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#endif
-
-#define DUART0_BA	0xF0000000	    /* DUART Base Address		*/
-#define DUART1_BA	0xF0000008	    /* DUART Base Address		*/
-#define DUART2_BA	0xF0000010	    /* DUART Base Address		*/
-#define DUART3_BA	0xF0000018	    /* DUART Base Address		*/
-#define CFG_NAND_BASE	0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST           (0x80000000 >> 14)
-#define CFG_UART2_RS232         (0x80000000 >> 5)
-#define CFG_UART3_RS232         (0x80000000 >> 6)
-#define CFG_UART4_RS232         (0x80000000 >> 7)
-#define CFG_UART5_RS232         (0x80000000 >> 8)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
deleted file mode 100644
index 35d84aedf8..0000000000
--- a/include/configs/IAD210.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-
-# ifdef DEBUG
-#  warning DEBUG Defined
-# endif /* DEBUG */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860		1
-#define CONFIG_IAD210		1	/* ...on a IAD210  module	*/
-#define CONFIG_MPC860T		1
-#define CONFIG_MPC862		1
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#undef  CONFIG_8xx_CONS_SMC1
-#undef  CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_SCC2   /* V24 on SCC2 */
-#undef  CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-
-
-# define MPC8XX_FACT            16
-# define CONFIG_8xx_GCLK_FREQ   (64000000L)  /* define if can't use get_gclk_freq */
-# define CONFIG_CLOCKS_IN_MHZ	1            /* clocks passsed to Linux in MHz */
-
-#if 0
-# define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-# define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-/* using this define saves us updating another source file */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#undef	CONFIG_BOOTARGS
-/* #define CONFIG_BOOTCOMMAND							\
- 	"bootp;" 								\
- 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
- 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
- 	"bootm"
-*/
-
-#define CONFIG_BOOTCOMMAND	\
-	"setenv bootargs root=/dev/nfs" 	\
-	"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " 	\
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/* #define	CONFIG_STATUS_LED	1*/	/* Status LED enabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-# undef  CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-# define CONFIG_FEC_ENET    1	/* use FEC ethernet  */
-# define CONFIG_MII         1
-# define CFG_DISCOVER_PHY   1
-# define CONFIG_FEC_UTOPIA  1
-# define CONFIG_ETHADDR     08:00:06:26:A2:6D
-# define CONFIG_IPADDR      192.168.28.128
-# define CONFIG_SERVERIP    139.10.137.138
-# define CFG_DISCOVER_PHY   1
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support    */
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged               */
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xDD
-# define CFG_I2C_EEPROM_ADDR	0x50
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DATE	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	 	0x00100000
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x08000000
-#define CFG_FLASH_SIZE		((uint)(4 * 1024 * 1024))	/* max 16Mbyte */
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined(DEBUG)
-# define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-# define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-
-# define CFG_MONITOR_BASE	CFG_FLASH_BASE
-# define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x8000
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CFG_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define PCMCIA_MEM_ADDR		((uint)0xff020000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0xF8000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xF8000000	/* OR addr mask */
-
-/* FLASH timing:
- TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | \
-				 OR_SCY_3_CLK | OR_EHTR)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
-#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	124		/* start with divider for 64 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR	        MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
deleted file mode 100644
index cd17935893..0000000000
--- a/include/configs/ICU862.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860		1
-#define CONFIG_MPC860T		1
-#define CONFIG_ICU862		1
-#define CONFIG_MPC862		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#ifdef CONFIG_100MHz
-#define MPC8XX_FACT		24		/* Multiply by 24	*/
-#define MPC8XX_XIN		4165000		/* 4.165 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
-				    /* define if cant' use get_gclk_freq */
-#else
-#if 1				/* for 50MHz version of processor	*/
-#define MPC8XX_FACT		12		/* Multiply by 12	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	48000000 /* define if cant use get_gclk_freq */
-#else				/* for 80MHz version of processor	*/
-#define MPC8XX_FACT		20		/* Multiply by 20	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
-#endif
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;" 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
-	"bootm"
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define	CONFIG_MII		1
-#if 1
-#define CFG_DISCOVER_PHY	1
-#else
-#undef	CFG_DISCOVER_PHY
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-# define CFG_I2C_EEPROM_ADDR	0x50
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	 	0x00100000
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if 0
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#else
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00F40000
-
-#define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
-#define SCCR_MASK	0
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	)
-#endif	/* CONFIG_100MHz */
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CFG_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected to Port B
- *-----------------------------------------------------------------------
- */
-			/* Output pins */
-#define TPS2205_VCC5	0x00008000	/* PB.16:  5V Voltage Control	*/
-#define TPS2205_VCC3	0x00004000	/* PB.17:  3V Voltage Control	*/
-#define TPS2205_VPP_PGM	0x00002000	/* PB.18: PGM Voltage Control	*/
-#define TPS2205_VPP_VCC	0x00001000	/* PB.19: VPP Voltage Control	*/
-#define TPS2205_SHDN	0x00000200	/* PB.22: Shutdown		*/
-#define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
-			  TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
-			  TPS2205_SHDN)
-
-			/* Input pins */
-#define TPS2205_OC	0x00000100	/* PB.23: Over-Current		*/
-#define TPS2205_INPUTS	( TPS2205_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-
-#define CFG_OR0_PRELIM	0xFF000954		/* Real values for the board */
-#define CFG_BR0_PRELIM	0x40000001		/* Real values for the board */
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-#define CFG_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
-
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		97	/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CFG_MAMR		0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
deleted file mode 100644
index 29eb874dbf..0000000000
--- a/include/configs/IDS8247.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
-#define CONFIG_MPC8272_FAMILY	1
-#define CONFIG_IDS8247		1
-#define CPU_ID_STR		"MPC8247"
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw "			\
-	"console=ttyS0,115200\0"					\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/IDS8247/uImage\0"				\
-	"kernel_addr=ff800000\0"					\
-	"ramdisk_addr=ffa00000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_MISC_INIT_R	1
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
-#define I2C_READ	((iop->pdat & 0x00000080) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
-			else    iop->pdat &= ~0x00000080
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
-			else    iop->pdat &= ~0x00000100
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#if 0
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-#endif
-
-/*
- * select serial console configuration
- * use the extern UART for the console
- */
-#define	CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE    1
-
-#define CFG_NS16550_CLK         14745600
-
-#define	CFG_UART_BASE	0xE0000000
-#define CFG_UART_SIZE	0x10000
-
-#define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CFG_FLASH0_BASE 0xFFF00000
-#define CFG_FLASH0_SIZE 8
-
-/* Flash bank size (for preliminary settings)
- */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/* Environment in flash */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x60000)
-#define CFG_ENV_SIZE		0x20000
-#define CFG_ENV_SECT_SIZE	0x20000
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
-#define CFG_NAND_LEGACY
-#define CFG_NAND0_BASE 0xE1000000
-
-#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN     0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define NAND_DISABLE_CE(nand) do \
-{ \
-	*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
-} while(0)
-
-#define NAND_ENABLE_CE(nand) do \
-{ \
-	*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) do \
-{ \
-	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_SETALE(nandptr) do \
-{ \
-	*(((volatile __u8 *)nandptr) + 0x9) = 0; \
-} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) do \
-{ \
-	*(((volatile __u8 *)nandptr) + 0xa) = 0; \
-} while(0)
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
-	udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
-
-#endif /* CFG_CMD_NAND */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#define CFG_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CFG_HID0_FINAL  0
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		0
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    16 bit  FLASH
- *  1   60x     GPCM     8 bit  NAND
- *  2   60x     SDRAM   32 bit  SDRAM
- *  3   60x     GPCM     8 bit  UART
- *
- */
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CFG_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
-
-#define CFG_MPTPR       0x6600
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CFG_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-			 ORxG_SCY_6_CLK                 )
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-/* Bank 1 - NAND Flash
-*/
-#define	CFG_NAND_BASE		CFG_NAND0_BASE
-#define	CFG_NAND_SIZE		0x8000
-
-#define CFG_OR_TIMING_NAND	0x000036
-
-#define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
-#endif
-
-/* Bank 2 - 60x bus SDRAM
- */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
-
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	CFG_OR2
-
-
-/* SDRAM initialization values
-*/
-#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A10             |\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
-			 PSDMR_BSMA_A15_A17           |\
-			 PSDMR_SDA10_PBI0_A11         |\
-			 PSDMR_RFRC_5_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_2C              |\
-			 PSDMR_WRC_3C                   |\
-			 PSDMR_CL_3)
-
-/* Bank 3 - UART
-*/
-
-#define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
deleted file mode 100644
index 0e20e56763..0000000000
--- a/include/configs/IP860.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
-#define CONFIG_IP860		1	/* ...on a IP860 board		*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
-"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-/*----------------------------------------------------------------------*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF1000000	/* Non-standard value!!	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x10000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#else
-#if 0 /* need more space for I2C tests */
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(256 << 10)
-#endif
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#undef	CFG_ENV_IS_IN_FLASH
-#undef	CFG_ENV_IS_IN_NVRAM
-#undef  CFG_ENV_IS_IN_NVRAM
-#undef	DEBUG_I2C
-#define	CFG_ENV_IS_IN_EEPROM
-
-#ifdef	CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_ADDR		0x20000000	/* use SRAM	*/
-#define CFG_ENV_SIZE		(16<<10)	/* use 16 kB	*/
-#endif	/* CFG_ENV_IS_IN_NVRAM */
-
-#ifdef	CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_OFFSET		 512	/* Leave 512 bytes free for other data	*/
-#define CFG_ENV_SIZE		1536	/* Use remaining space			*/
-#endif	/* CFG_ENV_IS_IN_EEPROM */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x80600800
- */
-#define CFG_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
-			 SIUMCR_DBGC11 | SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - get clock frequency from Board Revision Register
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-extern  unsigned long           ip860_get_clk_freq (void);
-#endif
-#define	CONFIG_8xx_GCLK_FREQ	ip860_get_clk_freq()
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => was: 0x0000D000 */
-#define CFG_PLPRCR							\
-		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
-		)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
-			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CFG_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- * DER - Debug Event Register
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- */
-
-/*
- * MAMR settings for SDRAM	- 16-14
- * => 0xC3804114
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	0xC3
-
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/*
- * BR1 and OR1 (FLASH)
- */
-#define FLASH_BASE		0x10000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 8 MB of Flash */
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	CFG_BR0_PRELIM
-
-/*
- * BR2/OR2 - SDRAM
- */
-#define SDRAM_BASE		0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
-
-#define CFG_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3/OR3 - SRAM (16 bit)
- */
-#define	SRAM_BASE	0x20000000
-#define CFG_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
-#define CFG_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define SRAM_SIZE	(1 + (~(CFG_OR3 & BR_BA_MSK)))
-#define CFG_OR3_PRELIM	CFG_OR3			/* Make sure to map early */
-#define CFG_BR3_PRELIM	CFG_BR3			/* in case it's used for ENV */
-
-/*
- * BR4/OR4 - Board Control & Status (8 bit)
- */
-#define	BCSR_BASE	0xFC000000
-#define CFG_OR4		0xFFFF0120		/* BI (internal) */
-#define CFG_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR5/OR5 - IP Slot A/B (16 bit)
- */
-#define	IP_SLOT_BASE	0x40000000
-#define CFG_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
-#define CFG_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR6/OR6 - VME STD  (16 bit)
- */
-#define	VME_STD_BASE	0xFE000000
-#define CFG_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
-#define CFG_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
- */
-#define VME_SHORT_BASE	0xFF000000
-#define CFG_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
-#define CFG_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*-----------------------------------------------------------------------
- * Board Control and Status Region:
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-typedef	struct ip860_bcsr_s {
-	unsigned char	shmem_addr;	/* +00 shared memory address register	*/
-	unsigned char	reserved0;
-	unsigned char	mbox_addr;	/* +02 mailbox address register		*/
-	unsigned char	reserved1;
-	unsigned char	vme_int_mask;	/* +04 VME Bus interrupt mask register	*/
-	unsigned char	reserved2;
-	unsigned char	vme_int_pend;	/* +06 VME interrupt pending register	*/
-	unsigned char	reserved3;
-	unsigned char	bd_int_mask;	/* +08 board interrupt mask register	*/
-	unsigned char	reserved4;
-	unsigned char	bd_int_pend;	/* +0A board interrupt pending register	*/
-	unsigned char	reserved5;
-	unsigned char	bd_ctrl;	/* +0C board control register		*/
-	unsigned char	reserved6;
-	unsigned char	bd_status;	/* +0E board status  register		*/
-	unsigned char	reserved7;
-	unsigned char	vme_irq;	/* +10 VME interrupt request register	*/
-	unsigned char	reserved8;
-	unsigned char	vme_ivec;	/* +12 VME interrupt vector register	*/
-	unsigned char	reserved9;
-	unsigned char	cli_mbox;	/* +14 clear mailbox irq		*/
-	unsigned char	reservedA;
-	unsigned char	rtc;		/* +16 RTC control register		*/
-	unsigned char	reservedB;
-	unsigned char	mbox_data;	/* +18 mailbox read/write register	*/
-	unsigned char	reservedC;
-	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
-	unsigned char	reservedD;
-	unsigned char	rmw_req;	/* +1C RMW request register		*/
-	unsigned char	reservedE;
-	unsigned char	bd_rev;		/* +1E Board Revision register		*/
-} ip860_bcsr_t;
-#endif	/* __ASSEMBLY__ */
-
-/*-----------------------------------------------------------------------
- * Board Control Register: bd_ctrl (Offset 0x0C)
- *-----------------------------------------------------------------------
- */
-#define BD_CTRL_IPLSE	0x80	/* IP Slot Long Select Enable		*/
-#define BD_CTRL_WDOGE	0x40	/* Watchdog Enable			*/
-#define BD_CTRL_FLWE	0x20	/* Flash Write Enable			*/
-#define BD_CTRL_RWDN	0x10	/* VMEBus Requester Release When Done Enable */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
deleted file mode 100644
index c1565fc037..0000000000
--- a/include/configs/IPHASE4539.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * This file is based on similar values for other boards found in
- * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef DEBUG				/* General debug */
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*-----------------------------------------------------------------------
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else */
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-/*-----------------------------------------------------------------------
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	3	/* which channel for ether  */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*-----------------------------------------------------------------------
- * - Rx-CLK is CLK14
- * - Tx-CLK is CLK16
- * - Select bus for bd/buffers (see 28-13)
- * - Half duplex
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif	/* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* other options */
-
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#define CONFIG_BAUDRATE		19200
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SOFT_I2C
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CONFIG_COMMANDS		CONFIG_CMD_DFL
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passed to Linux in MHz */
-					/* for versions < 2.4.5-pre5	 */
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_RESET_ADDRESS	0x04400000
-
-#define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration (Setup by the
- * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_SIZE	(CFG_MAX_FLASH_SECT * 0x10000)	/* 4 MB */
-
-#define CFG_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/* Environment in FLASH, there is little space left in Serial EEPROM */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x10000 /* We use one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x10000) /* 2. sector */
-
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
-			  ( HRCW_L2CPC10 | HRCW_ISB110 )	|\
-			  ( HRCW_MMR11 | HRCW_APPC10 )		|\
-			  ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	 \
-			) /* 0x14863245 */
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000 /* We keep original value */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	  /* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02	  /* Software reboot			*/
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5      /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers		2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- 			 HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		0xA01C0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	0X4205C000
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined (CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- *-----------------------------------------------------------------------
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR	0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*-----------------------------------------------------------------------
- * Init Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	64 bit	FLASH
- *  1	60x	SDRAM	64 bit	SDRAM
- */
-
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
-#define CFG_OR0_PRELIM	0xFF800882
-#define CFG_BR1_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
-#define CFG_OR1_PRELIM	0xF8002CD0
-
-#define CFG_PSDMR	0x404A241A
-#define CFG_MPTPR	0x00007400
-#define CFG_PSRT	0x00000007
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
deleted file mode 100644
index a0cb1dd484..0000000000
--- a/include/configs/IVML24.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
-#define CONFIG_IVML24		1	/* ...on a IVML24 board		*/
-
-#if defined (CONFIG_IVML24_16M)
-# define CONFIG_IDENT_STRING     " IVML24"
-#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_IDENT_STRING     " IVML24_128"
-#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_IDENT_STRING     " IVML24_256"
-#endif
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ    50331648
-
-#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
-				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
-				"nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_IDE)
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_BOOTP_MASK \
-    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define CFG_PB_12V_ENABLE	0x00002000		/* PB 18	*/
-#define CFG_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
-#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
-#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
-#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
-
-#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
-#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-
-#if defined (CONFIG_IVML24_16M)
-# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#elif defined (CONFIG_IVML24_32M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#elif defined (CONFIG_IVML24_64M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#endif
-
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-
-# if defined (CONFIG_IVML24_16M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-# elif defined (CONFIG_IVML24_32M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWP)
-# elif defined (CONFIG_IVML24_64M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWP)
-# endif
-
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CFG_PLPRCR							\
-		(	(11 << PLPRCR_MF_SHIFT) |			\
-			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
-		)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
-			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CFG_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
-#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
-
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)
-
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE		0xFE000000
-#define ELIC_SACCO_OR_AM	0xFFFF8000
-#define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CFG_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
-			ELIC_SACCO_TIMING)
-#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE		0xFE008000
-#define ELIC_EPIC_OR_AM		0xFFFF8000
-#define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
-
-#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
-			ELIC_EPIC_TIMING)
-#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
-
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4 - HDLC Address
- *
- *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
- */
-#define HDLC_ADDR_BASE		0xFE108000	/* HDLC Address area */
-#define HDLC_ADDR_OR_AM		0xFFFF8000
-#define HDLC_ADDR_TIMING	OR_SCY_1_CLK
-
-#define CFG_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
-#define CFG_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE		0xFE400000
-#define SHARC_OR_AM		0xFFC00000
-#define SHARC_TIMING		OR_SCY_0_CLK
-
-#define CFG_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
-#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-
-#if defined (CONFIG_IVML24_16M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-#elif defined (CONFIG_IVML24_32M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-#elif defined (CONFIG_IVML24_64M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVML24_16M)
- /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_32M)
-/* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVML24_64M)
-/* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
deleted file mode 100644
index 46b4d53546..0000000000
--- a/include/configs/IVMS8.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
-#define CONFIG_IVMS8		1	/* ...on a IVMS8 board		*/
-
-#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_IDENT_STRING     " IVMS8"
-#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_IDENT_STRING     " IVMS8_128"
-#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_IDENT_STRING     " IVMS8_256"
-#endif
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ    50331648
-
-#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-
-#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
-				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
-				"nfsaddrs=10.0.0.99:10.0.0.2"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_IDE)
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_BOOTP_MASK \
-    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
-#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
-#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
-
-#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
-#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#if defined (CONFIG_IVMS8_16M)
-# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#elif defined (CONFIG_IVMS8_32M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#elif defined (CONFIG_IVMS8_64M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#endif
-
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-# if defined (CONFIG_IVMS8_16M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#  elif defined (CONFIG_IVMS8_32M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWP)
-#  elif defined (CONFIG_IVMS8_64M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWP)
-#  endif
-#else
-# define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00B0C0C0 */
-#define CFG_PLPRCR							\
-		(	(11 << PLPRCR_MF_SHIFT) |			\
-			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
-		)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
-			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* TIMEP=2 */
-#define CFG_RCCR 0x0200
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
-#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
-
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_SACCO_BASE		0xFE000000
-#define ELIC_SACCO_OR_AM	0xFFFF8000
-#define ELIC_SACCO_TIMING	0x00000F26
-
-#define CFG_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
-#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
- *
- * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
- */
-#define ELIC_EPIC_BASE		0xFE008000
-#define ELIC_EPIC_OR_AM		0xFFFF8000
-#define ELIC_EPIC_TIMING	0x00000F26
-
-#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
-#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
-
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: not used
- */
-
-/*
- * BR5/OR5: SHARC ADSP-2165L
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define SHARC_BASE		0xFE400000
-#define SHARC_OR_AM		0xFFC00000
-#define SHARC_TIMING		0x00000700
-
-#define CFG_OR5	(SHARC_OR_AM | SHARC_TIMING )
-#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#if defined (CONFIG_IVMS8_16M)
- #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-#elif defined (CONFIG_IVMS8_32M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-#elif defined (CONFIG_IVMS8_64M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
-#endif
-
-
-/*
- * MBMR settings for SDRAM
- */
-
-#if defined (CONFIG_IVMS8_16M)
- /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_32M)
-/* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-#elif defined (CONFIG_IVMS8_64M)
-/* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
-
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
deleted file mode 100644
index 0d3825413e..0000000000
--- a/include/configs/IceCube.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_ICECUBE		1	/* ... on IceCube board */
-
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP		1
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#define ADD_PCI_CMD 		CFG_CMD_PCI
-#endif
-
-#define CFG_XLB_PIPELINING	1
-
-#define CONFIG_NET_MULTI	1
-#define CONFIG_MII		1
-#define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-
-#else	/* MPC5100 */
-
-#define CONFIG_MII		1
-#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
-
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD             0
-#endif
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	| \
-				ADD_PCI_CMD	| \
-				ADD_USB_CMD	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT	        1
-#   define CFG_LOWBOOT16	1
-#endif
-#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
-#if defined(CONFIG_LITE5200B)
-#   error CFG_LOWBOOT08 is incompatible with the Lite5200B
-#else
-#   define CFG_LOWBOOT	        1
-#   define CFG_LOWBOOT08	1
-#endif
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/MPC5200/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if defined(CONFIG_MPC5200)
-/*
- * IPB Bus clocking configuration.
- */
-#if defined(CONFIG_LITE5200B)
-#define CFG_IPBSPEED_133 	/* define for 133MHz speed */
-#else
-#undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
-#endif
-#endif /* CONFIG_MPC5200 */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
-
-/*
- * Flash configuration
- */
-#if defined(CONFIG_LITE5200B)
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x01000000
-#if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x01760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#if defined(CFG_LOWBOOT08)
-# error CFG_LOWBOOT08 is incompatible with the Lite5200B
-#endif
-#if defined(CFG_LOWBOOT16)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x01060000)
-#endif
-#endif /* CFG_LOWBOOT */
-#else /* !CONFIG_LITE5200B (IceCube)*/
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x01000000
-#if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#if defined(CFG_LOWBOOT08)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000 + 0x00800000)
-#endif
-#if defined(CFG_LOWBOOT16)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
-#endif
-#endif	/* CFG_LOWBOOT */
-#endif /* CONFIG_LITE5200B */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
-
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
-
-#if defined(CONFIG_LITE5200B)
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST	{CFG_CS1_START,CFG_CS0_START}
-#endif
-
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000
-#if defined(CONFIG_LITE5200B)
-#define CFG_ENV_SECT_SIZE	0x20000
-#else
-#define CFG_ENV_SECT_SIZE	0x10000
-#endif
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_FEC_MII100	1
-#endif
-
-/*
- * GPIO configuration
- */
-#ifdef CONFIG_MPC5200_DDR
-#define CFG_GPS_PORT_CONFIG	0x90000004
-#else
-#define CFG_GPS_PORT_CONFIG	0x10000004
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#if defined(CONFIG_LITE5200B)
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_CFG		0x00047800
-#define CFG_CS0_START		(CFG_FLASH_BASE + CFG_FLASH_SIZE)
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_START	CFG_CS0_START
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
-#else /* IceCube aka Lite5200 */
-#ifdef CONFIG_MPC5200_DDR
-
-#define CFG_BOOTCS_START	(CFG_CS1_START + CFG_CS1_SIZE)
-#define CFG_BOOTCS_SIZE		0x00800000
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		0x00800000
-#define CFG_CS1_CFG		0x00047800
-
-#else /* !CONFIG_MPC5200_DDR */
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-#endif /* CONFIG_MPC5200_DDR */
-#endif /*CONFIG_LITE5200B */
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
-
-#define CONFIG_ATAPI            1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
deleted file mode 100644
index ccd1f19903..0000000000
--- a/include/configs/JSE.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2003 Picture Elements, Inc.
- * Stephen Williams <steve@icarus.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options for the JSE board
- * (Theoretically easy to change, but the board is fixed.)
- */
-
-#define CONFIG_JSE 1
-  /* JSE has a PPC405GPr */
-#define CONFIG_405GP 1
-  /* ... which is a 4xxx series */
-#define CONFIG_4xx   1
-  /* ... with a 33MHz OSC. connected to the SysCLK input */
-#define CONFIG_SYS_CLK_FREQ	33333333
-  /* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR 0xF4000000
-#define CFG_OCM_DATA_SIZE 0x00001000
-  /* Do not set up locked dcache as init ram. */
-#undef CFG_INIT_DCACHE_CS
-
-  /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
-#define CONFIG_SYSTEMACE 1
-#define CFG_SYSTEMACE_BASE 0xf0000000
-#define CONFIG_DOS_PARTITION 1
-
-  /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM 1
-  /* ... place INIT RAM in the OCM address */
-# define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
-  /* ... give it the whole init ram */
-# define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
-  /* ... Shave a bit off the end for global data */
-# define CFG_GBL_DATA_SIZE	128
-# define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-  /* ... and place the stack pointer at the top of what's left. */
-# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-  /* Enable board_pre_init function */
-#define CONFIG_BOARD_PRE_INIT	1
-#define CONFIG_BOARD_EARLY_INIT_F 1
-  /* Disable post-clk setup init function */
-#undef CONFIG_BOARD_POSTCLK_INIT
-  /* Disable call to post_init_f: late init function. */
-#undef CONFIG_POST
-  /* Enable DRAM test. */
-#define CFG_DRAM_TEST 1
-  /* Enable misc_init_r function. */
-#define CONFIG_MISC_INIT_R 1
-
-  /* JSE has EEPROM chips that are good for environment. */
-#undef	CFG_ENV_IS_IN_NVRAM
-#undef	CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_IS_IN_EEPROM 1
-#undef	CFG_ENV_IS_NOWHERE
-
-  /* This is the 7bit address of the device, not including P. */
-#define CFG_I2C_EEPROM_ADDR 0x50
-  /* After the device address, need one more address byte. */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-  /* The EEPROM is 512 bytes. */
-#define CFG_EEPROM_SIZE 512
-  /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-  /* Put the environment in the second half. */
-#define CFG_ENV_OFFSET	0x00
-#define CFG_ENV_SIZE	512
-
-
-  /* The JSE connects UART1 to the console tap connector. */
-#define CONFIG_UART1_CONSOLE	1
-  /* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE		9600
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-
-/*
- * Configuration related to auto-boot.
- *
- * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
- * before resorting to autoboot. This value can be overridden by the
- * bootdelay environment variable.
- *
- * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
- * user that an autoboot will happen.
- *
- * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
- * execute to boot the JSE. This loads the uimage and initrd.img files
- * from CompactFlash into memory, then boots them from memory.
- *
- * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
- * it going on the JSE.
- */
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTARGS		"root=/dev/ram0 init=/linuxrc rw"
-#define CONFIG_BOOTCOMMAND	"fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
-
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_FLASH	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-  /* watchdog disabled */
-#undef CONFIG_WATCHDOG
-  /* SPD EEPROM (sdram speed config) disabled */
-#undef CONFIG_SPD_EEPROM
-#undef SPD_EEPROM_ADDRESS
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
-
-#define CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define CFG_IR_REG_BASE_ADDR	0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405GPr CPUs	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR	0xF0000500
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
deleted file mode 100644
index e44f1cc627..0000000000
--- a/include/configs/LANTEC.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- * [derived from config_TQM850L.h]
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_LANTEC		2	/* ...on a Lantec rev.2 board	*/
-
-/*
- *  Port assignments (CONFIG_LANTEC == 1):
- *  - SMC1: J11 (MDB) ?
- *  - SMC2: J6  (Feature connector)
- *  - SCC2: J9  (RJ45)
- *  - SCC3: J8  (Sub-D9)
- *
- *  Port assignments (CONFIG_LANTEC == 2): TBD
- */
-
-
-#undef CONFIG_8xx_CONS_SMC2           /* Console is on SMC2           */
-#define	CONFIG_8xx_CONS_SCC3
-#undef  CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps  */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_CMD_MINIMAL	0
-#define CONFIG_CMD_TINY		(CFG_CMD_FLASH  | \
-				 CFG_CMD_MEMORY | \
-				 CFG_CMD_LOADS  | \
-				 CFG_CMD_LOADB)
-#define CONFIG_CMD_NORMAL	(CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER)
-#define CONFIG_CMD_GDB		(CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
-#define CONFIG_CMD_FULL		(CFG_CMD_ALL & ~CFG_CMD_BEDBUG	\
-					     & ~CFG_CMD_BMP	\
-					     & ~CFG_CMD_BSP	\
-					     & ~CFG_CMD_DISPLAY	\
-					     & ~CFG_CMD_DOC	\
-					     & ~CFG_CMD_DTT	\
-					     & ~CFG_CMD_EEPROM	\
-					     & ~CFG_CMD_ELF	\
-					     & ~CFG_CMD_EXT2	\
-					     & ~CFG_CMD_FDC	\
-					     & ~CFG_CMD_FDOS	\
-					     & ~CFG_CMD_HWFLOW	\
-					     & ~CFG_CMD_I2C	\
-					     & ~CFG_CMD_IDE	\
-					     & ~CFG_CMD_IRQ	\
-					     & ~CFG_CMD_JFFS2	\
-					     & ~CFG_CMD_KGDB	\
-					     & ~CFG_CMD_MII	\
-					     & ~CFG_CMD_MMC	\
-					     & ~CFG_CMD_NAND	\
-					     & ~CFG_CMD_PCI	\
-					     & ~CFG_CMD_PCMCIA	\
-					     & ~CFG_CMD_REISER	\
-					     & ~CFG_CMD_SCSI	\
-					     & ~CFG_CMD_SPI	\
-					     & ~CFG_CMD_UNIVERSE\
-					     & ~CFG_CMD_USB	\
-					     & ~CFG_CMD_VFD	\
-					     & ~CFG_CMD_XIMG	)
-
-#if CONFIG_LANTEC >= 2
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-#endif
-
-#if CONFIG_LANTEC >= 2
-# define CONFIG_COMMANDS	CONFIG_CMD_FULL
-#else
-# define CONFIG_COMMANDS	(CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET)
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
- *-----------------------------------------------------------------------
- */
-#define	CONFIG_8xx_GCLK_FREQ	33000000
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/5 and OR0/5 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE5_PRELIM	0x60000000	/* FLASH bank #1	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing */
-#define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
-				 OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CFG_OR5_REMAP   CFG_OR0_REMAP
-#define CFG_OR5_PRELIM  CFG_OR0_PRELIM
-#define CFG_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
-#define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses					*/
-#define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM)
-
-#define CFG_OR3_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL \
-			((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
deleted file mode 100644
index 5fd6a95c4d..0000000000
--- a/include/configs/M5272C3.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Configuation settings for the Motorola MC5272C3 board.
- *
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5272C3_H
-#define _M5272C3_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5272			/* define processor type */
-
-#define FEC_ENET
-
-#define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define CONFIG_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
-
-#define CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_OFFSET		0x4000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_IS_EMBEDDED	1
-#else
-#define CFG_ENV_ADDR		0xffe04000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-#endif
-
-#define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
-			   CFG_CMD_MII)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CONFIG_BOOTDELAY	5
-
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP				/* undef to save memory		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_LOAD_ADDR		0x20000
-
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-
-#define CFG_HZ			1000
-#define CFG_CLK			66000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
-
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE	0x380000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		4		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
-
-#ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
-#else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#endif
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	1000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-#define CFG_BR0_PRELIM		0xFFE00201
-#define CFG_OR0_PRELIM		0xFFE00014
-
-#define CFG_BR1_PRELIM		0
-#define CFG_OR1_PRELIM		0
-
-#define CFG_BR2_PRELIM		0x30000001
-#define CFG_OR2_PRELIM		0xFFF80000
-
-#define CFG_BR3_PRELIM		0
-#define CFG_OR3_PRELIM		0
-
-#define CFG_BR4_PRELIM		0
-#define CFG_OR4_PRELIM		0
-
-#define CFG_BR5_PRELIM		0
-#define CFG_OR5_PRELIM		0
-
-#define CFG_BR6_PRELIM		0
-#define CFG_OR6_PRELIM		0
-
-#define CFG_BR7_PRELIM		0x00000701
-#define CFG_OR7_PRELIM		0xFFC0007C
-
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-#define CFG_PACNT		0x00000000
-#define CFG_PADDR		0x0000
-#define CFG_PADAT		0x0000
-#define CFG_PBCNT		0x55554155		/* Ethernet/UART configuration */
-#define CFG_PBDDR		0x0000
-#define CFG_PBDAT		0x0000
-#define CFG_PDCNT		0x00000000
-
-#endif	/* _M5272C3_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
deleted file mode 100644
index cbb3e3bb9f..0000000000
--- a/include/configs/M5282EVB.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Configuation settings for the Motorola MC5282EVB board.
- *
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _CONFIG_M5282EVB_H
-#define _CONFIG_M5282EVB_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define	CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5282			/* define processor type */
-
-#define FEC_ENET
-
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#define CFG_ENV_ADDR		0xffe04000
-#define CFG_ENV_SIZE		0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-
-
-#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CONFIG_BOOTDELAY	5
-
-#define CFG_PROMPT		"-> "
-#define	CFG_LONGHELP				/* undef to save memory		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_LOAD_ADDR		0x20000
-
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-
-#define CFG_HZ			1000000
-#define	CFG_CLK			64000000
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define	CFG_MBAR		0x40000000
-
-#undef	CFG_DISCOVER_PHY
-#define	CFG_ENET_BD_BASE	0x380000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR       0x20000000
-#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define	CFG_SDRAM_SIZE		4		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
-#define	CFG_INT_FLASH_BASE	0xf0000000
-
-/* If M5282 port is fully implemented the monitor base will be behind
- * the vector table. */
-/* #define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400) */
-#define CFG_MONITOR_BASE	0x20000
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
-
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define	CFG_MAX_FLASH_SECT	35
-#define	CFG_MAX_FLASH_BANKS	1
-#define	CFG_FLASH_ERASE_TOUT	10000000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16
-
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-
-
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-
-
-#endif	/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
deleted file mode 100644
index 53684ca6b5..0000000000
--- a/include/configs/MHPC.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * (C) Copyright 2001
- * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Configuation settings for the miniHiPerCam.
- *
- * -----------------------------------------------------------------
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
-#undef	CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#undef	CONFIG_UCODE_PATCH
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
-#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
-#define LCD_VIDEO_COLS		640
-#define LCD_VIDEO_ROWS		480
-#define LCD_VIDEO_FG		255
-#define LCD_VIDEO_BG		0
-
-#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
-#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
-#define CONFIG_VIDEO_LOGO
-
-#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT		serial_tstc
-#define VIDEO_GETC_FCT		serial_getc
-
-#define CONFIG_BR0_WORKAROUND	1
-
-#define CONFIG_COMMANDS	     ( CONFIG_CMD_DFL  | \
-			       CFG_CMD_DATE    | \
-			       CFG_CMD_EEPROM  | \
-			       CFG_CMD_ELF     | \
-			       CFG_CMD_I2C     | \
-			       CFG_CMD_JFFS2   | \
-			       CFG_CMD_REGINFO )
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x300000	/* default load address */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical memory map
- */
-#define CFG_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfe000000
-
-#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
-#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=mhpc-0"
-#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
-*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
-#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_SEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		12-18
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define MPC8XX_SPEED	50000000L
-#define MPC8XX_XIN	5000000L      /* ref clk */
-#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
-#define CFG_SCCR	(SCCR_TBS | SCCR_DFLCD001)
-
-
-/*-----------------------------------------------------------------------
- * MAMR settings for SDRAM	- 16-14
- * => 0xC080200F
- *-----------------------------------------------------------------------
- * periodic timer for refresh
- */
-#define CFG_MAMR_PTA	0xC0
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
-
-/*
- * BR0 and OR0 (FLASH) used to re-map FLASH
- */
-
-/* allow for max 8 MB of Flash */
-#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
-#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
-#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
-
-/* SDRAM timing: drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS)
-
-#define CFG_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - DIMM
- */
-#define CFG_OR2		(OR_ACS_DIV4)
-#define CFG_BR2		(BR_MS_UPMA)
-
-/*
- * BR3/OR3 - DIMM
- */
-#define CFG_OR3		(OR_ACS_DIV4)
-#define CFG_BR3		(BR_MS_UPMA)
-
-/*
- * BR4/OR4
- */
-#define CFG_OR4		0
-#define CFG_BR4		0
-
-/*
- * BR5/OR5
- */
-#define CFG_OR5		0
-#define CFG_BR5		0
-
-/*
- * BR6/OR6
- */
-#define CFG_OR6		0
-#define CFG_BR6		0
-
-/*
- * BR7/OR7
- */
-#define CFG_OR7		0
-#define CFG_BR7		0
-
-
-/*-----------------------------------------------------------------------
- * Debug Entry Mode
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER 0
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
deleted file mode 100644
index d8805ea5a7..0000000000
--- a/include/configs/ML2.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * ML2.h: ML2 specific config options
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_ML2	1	/* ...on a ML2 board	*/
-
-
-#define CFG_ENV_IS_IN_FLASH     1
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootm" /* autoboot command	*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-#endif
-
-#define CONFIG_PREBOOT		"fsload 0x00100000 /boot/image"
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#if 0
-#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
-#else
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#endif
-
-#if 0
-#define CONFIG_BOOTARGS		"root=/dev/nfs "                        \
-    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
-    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 "			\
-   "console=ttyS0 console=tty"
-
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & \
-				     ~( CFG_CMD_NET | \
-					CFG_CMD_RTC | \
-					CFG_CMD_PCI | \
-					CFG_CMD_I2C   \
-				      ) ) | \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_KGDB	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_JFFS2	  )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SYS_CLK_FREQ 50000000
-
-#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-
-#define CFG_BASE_BAUD       (3125000*16)
-#define CFG_NS16550_CLK CFG_BASE_BAUD
-#define CFG_DUART_CHAN		0
-#define CFG_NS16550_COM1	0xa0001003
-#define CFG_NS16550_COM2	0xa0011003
-#define CFG_NS16550_REG_SIZE -4
-#define CFG_NS16550 1
-#define CFG_INIT_CHAN1	 1
-#define CFG_INIT_CHAN2	 1
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x18000000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x00050000 /* Offset of Environment Sector  */
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR	0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CFG_INIT_RAM_ADDR       0x800000  /* inside of SDRAM                     */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00080000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=ml2-0"
-#define MTDPARTS_DEFAULT	"mtdparts=ml2-0:-@512k(jffs2)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
deleted file mode 100644
index 6ad2feb28e..0000000000
--- a/include/configs/MOUSSE.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * James F. Dougherty (jfd@cs.stanford.edu)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the MOUSSE board.
- * See also: http://www.vooha.com/
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X      1
-#define CONFIG_MPC8240      1
-#define CONFIG_MOUSSE       1
-#define CFG_ADDR_MAP_B      1
-#define CONFIG_CONS_INDEX   1
-#define CONFIG_BAUDRATE     9600
-#if 1
-#define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND  "bootm ffe10000"
-#endif
-#define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
-#define CONFIG_BOOTDELAY     3
-#define CONFIG_COMMANDS      (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE)
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ETH_ADDR      "00:10:18:10:00:06"
-
-#define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-#include "../board/mousse/mousse.h"
-
-/*
- * Miscellaneous configurable options
- */
-#undef CFG_LONGHELP                /* undef to save memory     */
-#define CFG_PROMPT      "=>"  /* Monitor Command Prompt   */
-#define CFG_CBSIZE      256        /* Console I/O Buffer Size  */
-#define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS     8           /* Max number of command args   */
-
-#define CFG_BARGSIZE    CFG_CBSIZE  /* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR   0x00100000  /* Default load address         */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE      0x00000000
-
-#ifdef DEBUG
-#define CFG_MONITOR_BASE    CFG_SDRAM_BASE
-#else
-#define CFG_MONITOR_BASE    CFG_FLASH_BASE
-#endif
-
-#ifdef DEBUG
-#define CFG_MONITOR_LEN     (4 << 20)	/* lots of mem ... */
-#else
-#define CFG_MONITOR_LEN     (512 << 10)	/* 512K PLCC bootrom */
-#endif
-#define CFG_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on      */
-#define CFG_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */
-
-
-#define CFG_EUMB_ADDR       0xFC000000
-
-#define CFG_ISA_MEM         0xFD000000
-#define CFG_ISA_IO          0xFE000000
-
-#define CFG_FLASH_BASE      0xFFF00000
-#define CFG_FLASH_SIZE      ((uint)(512 * 1024))
-#define CFG_RESET_ADDRESS   0xFFF00100
-#define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
-#define FLASH_BASE0_SIZE    0x80000     /* 512K */
-#define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
-					   1MB - 64K FLASH0 SEG =960K
-					   (size=0xf0000)*/
-
-#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		18432000
-
-#define CFG_NS16550_COM1	0xFFE08080
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
-#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CFG_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
-#define CFG_HZ               1000
-
-#define CFG_ETH_DEV_FN       0x00
-#define CFG_ETH_IOBASE       0x00104000
-
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL          8
-#define CFG_ROMFAL          8
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_REFINT          0xf5     /* Refresh interval               */
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE         0x79
-
-#ifdef INCLUDE_ECC
-#define USE_ECC				1
-#else /* INCLUDE_ECC */
-#define USE_ECC				0
-#endif /* INCLUDE_ECC */
-
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC          8       /* Refresh to activate interval   */
-#define CFG_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT        3       /* Precharge to activate interval */
-#define CFG_ACTTOPRE        5       /* Activate to Precharge interval */
-#define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
-#define CFG_SDMODE_WRAP     0       /* SDMODE wrap type               */
-#define CFG_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
-#define CFG_ACTORW          2
-#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-#define CFG_RAM_SIZE        0x04000000  /* 64MB */
-
-
-#define CFG_BANK0_START     0x00000000
-#define CFG_BANK0_END       (CFG_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START     0x3ff00000
-#define CFG_BANK1_END       0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START     0x3ff00000
-#define CFG_BANK2_END       0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START     0x3ff00000
-#define CFG_BANK3_END       0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START     0x3ff00000
-#define CFG_BANK4_END       0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START     0x3ff00000
-#define CFG_BANK5_END       0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START     0x3ff00000
-#define CFG_BANK6_END       0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START     0x3ff00000
-#define CFG_BANK7_END       0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR            0x7f
-
-
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
-				    see 8240 book for details*/
-#define PCI_MEM_SPACE1_START	0x80000000
-#define PCI_MEM_SPACE2_START	0xfd000000
-
-/* IBAT/DBAT Configuration */
-/* Ram: 64MB, starts at address-0, r/w instruction/data */
-#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U      CFG_IBAT0U
-#define CFG_DBAT0L      CFG_IBAT0L
-
-/* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
-#define CFG_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
-#if 0
-#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
-			 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
-#else
-#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
-#endif
-#define CFG_DBAT1U  	CFG_IBAT1U
-#define CFG_DBAT1L  	CFG_IBAT1L
-
-/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
-#define CFG_IBAT2U  	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L 	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
-#define CFG_DBAT2U      CFG_IBAT2U
-#define CFG_DBAT2L      CFG_IBAT2L
-
-/* PCI Memory region 2: PCI Devices in 0xFD space */
-#define CFG_IBAT3U  	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L 	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CFG_DBAT3U      CFG_IBAT3U
-#define CFG_DBAT3L      CFG_IBAT3L
-
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
-#define CFG_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
-
-#define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
-
-#if 0
-#define	CFG_ENV_IS_IN_FLASH	    1
-#define CFG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector	 */
-#define CFG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
-#else
-#define CFG_ENV_IS_IN_NVRAM          1
-#define CFG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
-#define CFG_ENV_OFFSET          CFG_ENV_ADDR
-#define CFG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE  16
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM           0x02    /* Software reboot                  */
-
-/* Localizations */
-#if 0
-#define CONFIG_ETHADDR          0:0:0:0:1:d
-#define CONFIG_IPADDR           172.16.40.113
-#define CONFIG_SERVERIP         172.16.40.111
-#else
-#define CONFIG_ETHADDR          0:0:0:0:1:d
-#define CONFIG_IPADDR           209.128.93.138
-#define CONFIG_SERVERIP         209.128.93.133
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
-
-#define CONFIG_TULIP
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
deleted file mode 100644
index 6195bca85b..0000000000
--- a/include/configs/MPC8260ADS.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
- * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
- * Ported to MPC8272ADS board.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI bridge on MPC8272ADS
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260ADS	1	/* Motorola PQ2 ADS family board */
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*
- * Figure out if we are booting low via flash HRCW or high via the BCSR.
- */
-#if (TEXT_BASE != 0xFFF00000)		/* Boot low (flash HRCW) */
-#   define CFG_LOWBOOT		1
-#endif
-
-/* ADS flavours */
-#define CFG_8260ADS		1	/* MPC8260ADS */
-#define CFG_8266ADS		2	/* MPC8266ADS */
-#define CFG_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
-#define CFG_8272ADS		4	/* MPC8272ADS */
-
-#ifndef CONFIG_ADSTYPE
-#define CONFIG_ADSTYPE		CFG_8260ADS
-#endif /* CONFIG_ADSTYPE */
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CONFIG_MPC8272		1
-#else
-#define CONFIG_MPC8260		1
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else */
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-
-#if   CONFIG_ETHER_INDEX == 1
-
-# define CFG_PHY_ADDR		0
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-
-#elif CONFIG_ETHER_INDEX == 2
-
-#if CONFIG_ADSTYPE == CFG_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
-# define CFG_PHY_ADDR		3
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
-#else					/* RxCLK is CLK13, TxCLK is CLK14 */
-# define CFG_PHY_ADDR		0
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
-
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-
-#endif	/* CONFIG_ETHER_INDEX */
-
-#define CFG_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
-
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT	2		/* Port C */
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_MDIO_PIN	0x00002000	/* PC18 */
-#define CFG_MDC_PIN	0x00001000	/* PC19 */
-#else
-#define CFG_MDIO_PIN	0x00400000	/* PC9	*/
-#define CFG_MDC_PIN	0x00200000	/* PC10 */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
-
-#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-			else	iop->pdat &= ~CFG_MDIO_PIN
-
-#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
-			else	iop->pdat &= ~CFG_MDC_PIN
-
-#define MIIDELAY	udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
-#undef CONFIG_SPD_EEPROM	/* On new boards, SDRAM is soldered */
-#else
-#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR		0x50
-#endif
-#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
-
-/*PCI*/
-#ifdef CONFIG_MPC8272
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI	0 /* By default, use bank-based interleaving */
-#endif
-
-#ifndef CONFIG_8260_CLKIN
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
-#define CONFIG_8260_CLKIN	100000000	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	66000000	/* in Hz */
-#endif
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_EXCLUDE		CFG_CMD_BEDBUG	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DISPLAY | \
-				CFG_CMD_DOC	| \
-				CFG_CMD_DTT	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_FDC	| \
-				CFG_CMD_FDOS	| \
-				CFG_CMD_HWFLOW	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_KGDB	| \
-				CFG_CMD_MMC	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_PCMCIA	| \
-				CFG_CMD_REISER	| \
-				CFG_CMD_SCSI	| \
-				CFG_CMD_SPI	| \
-				CFG_CMD_SNTP	| \
-				CFG_CMD_UNIVERSE | \
-				CFG_CMD_USB	| \
-				CFG_CMD_VFD	| \
-				CFG_CMD_XIMG
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-			         CFG_CMD_SDRAM	| \
-				 CFG_CMD_I2C	| \
-				 CFG_EXCLUDE	) )
-#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_CMD_SDRAM	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_PCI	| \
-				 CFG_EXCLUDE	) )
-#else
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CMD_CFG_PCI 	| \
-				 CFG_EXCLUDE 	) )
-#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"bootm fff80000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
-#undef	CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CFG_FLASH_BASE		0xff800000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-/*
- * JFFS2 partitions
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-#define MTDIDS_DEFAULT		"nor0=mpc8260ads-0"
-#define MTDPARTS_DEFAULT	"mtdparts=mpc8260ads-0:-@1m(jffs2)"
-#define CFG_JFFS2_SORT_FRAGMENTS
-
-/* this is stuff came out of the Motorola docs */
-#ifndef CFG_LOWBOOT
-#define CFG_DEFAULT_IMMR	0x0F010000
-#endif
-
-#define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0xF4500000
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_PCI_INT		0xF8200000
-#endif
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_LSDRAM_BASE		0xFD000000
-
-#define RS232EN_1		0x02000002
-#define RS232EN_2		0x01000001
-#define FETHIEN1		0x08000008
-#define FETH1_RST		0x04000004
-#define FETHIEN2		0x10000000
-#define FETH2_RST		0x08000000
-#define BCSR_PCI_MODE		0x01000000
-
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#ifdef CFG_LOWBOOT
-/* PQ2FADS flash HRCW = 0x0EB4B645 */
-#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
-			    ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
-			    ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
-			    ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	     \
-			)
-#else
-/* PQ2FADS BCSR HRCW = 0x0CB23645 */
-#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
-			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
-			    ( HRCW_BMS | HRCW_APPC10 )			    |\
-			    ( HRCW_MODCK_H0101 )			     \
-			)
-#endif
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM	0x02	/* Software reboot	     */
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
-#endif /* CONFIG_BZIP2 */
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH	1
-#  define CFG_ENV_SECT_SIZE	0x40000
-#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
-#else
-#  define CFG_ENV_IS_IN_NVRAM	1
-#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CFG_HID2		0
-
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x100C0000
-#define CFG_SIUMCR		0x0A200000
-#define CFG_SCCR		SCCR_DFBRG01
-#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
-#define CFG_OR0_PRELIM		0xFF800876
-#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
-#define CFG_OR1_PRELIM		0xFFFF8010
-
-/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_BR3_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
-#define CFG_OR3_PRELIM	0xFFFF8010
-#endif
-
-#define CFG_RMR			RMR_CSRE
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-
-#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
-#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on these boards */
-#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
-
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
-#define CFG_OR2			0xFE002EC0
-#define CFG_PSDMR		0x824B36A3
-#define CFG_PSRT		0x13
-#define CFG_LSDMR		0x828737A3
-#define CFG_LSRT		0x13
-#define CFG_MPTPR		0x2800
-#elif CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_OR2			0xFC002CC0
-#define CFG_PSDMR		0x834E24A3
-#define CFG_PSRT		0x13
-#define CFG_MPTPR		0x2800
-#else
-#define CFG_OR2			0xFF000CA0
-#define CFG_PSDMR		0x016EB452
-#define CFG_PSRT		0x21
-#define CFG_LSDMR		0x0086A522
-#define CFG_LSRT		0x21
-#define CFG_MPTPR		0x1900
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
-
-#define CFG_RESET_ADDRESS	0x04400000
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-
-/* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
-				 PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
-#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-
-/* PCIBR0 - for PCI IO*/
-#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
-#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
-/* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
-#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
-
-#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
-
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CONFIG_HAS_ETH1
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
deleted file mode 100644
index 4953b7053b..0000000000
--- a/include/configs/MPC8266ADS.h
+++ /dev/null
@@ -1,594 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
- */
-
-/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-   !!								      !!
-   !!  This configuration requires JP3 to be in position 1-2 to work  !!
-   !!  To make it work for the default, the TEXT_BASE define in	      !!
-   !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
-   !!  0xfff00000						      !!
-   !!  The CFG_HRCW_MASTER define below must also be changed to match !!
-   !!								      !!
-   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
-#define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else */
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT	2	/* Port C */
-#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
-#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
-			else	iop->pdat &= ~0x00400000
-
-#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
-			else	iop->pdat &= ~0x00200000
-
-#define MIIDELAY	udelay(1)
-
-#if (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Half duplex
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif	/* CONFIG_ETHER_INDEX */
-
-/* other options */
-#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-
-/* PCI */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#undef CONFIG_PCI_SCAN_SHOW
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS	0x50
-
-
-#define CONFIG_8260_CLKIN	66000000	/* in Hz */
-#define CONFIG_BAUDRATE		115200
-
-
-#define CONFIG_COMMANDS	      ( CFG_CMD_ALL & ~( \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DISPLAY | \
-				CFG_CMD_DOC	| \
-				CFG_CMD_DTT	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_FDC	| \
-				CFG_CMD_FDOS	| \
-				CFG_CMD_HWFLOW	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_KGDB	| \
-				CFG_CMD_MMC	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_PCMCIA	| \
-				CFG_CMD_REISER	| \
-				CFG_CMD_SCSI	| \
-				CFG_CMD_SPI	| \
-				CFG_CMD_SNTP	| \
-				CFG_CMD_VFD	| \
-				CFG_CMD_UNIVERSE | \
-				CFG_CMD_USB	| \
-				CFG_CMD_XIMG	) )
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/ram0 rw " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-/* Add support for a few extra bootp options like:
- *	- File size
- *	- DNS
- */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
-					/* for versions < 2.4.5-pre5	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CFG_FLASH_BASE		0xFE000000
-#define FLASH_BASE		0xFE000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
-
-#undef	CFG_FLASH_CHECKSUM
-
-/* this is stuff came out of the Motorola docs */
-/* Only change this if you also change the Hardware configuration Word */
-#define CFG_DEFAULT_IMMR	0x0F010000
-
-/* Set IMMR to 0xF0000000 or above to boot Linux  */
-#define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0xF8000000
-#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
-
-/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
- */
-/*#define CONFIG_VERY_BIG_RAM	1*/
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?  This will normally auto-configure via the SPD.
-*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16
-
-#define SDRAM_SPD_ADDR 0x50
-
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- */
-
-/* The BR2 is configured as follows:
- *
- *     - Base address of 0x00000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CFG_BR3_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- *     - 64 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A8		|\
-			 ORxS_NUMR_12)
-#elif (CFG_SDRAM_SIZE == 16)
-#define CFG_OR2_PRELIM	(0xFF000C80)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-#if (CFG_SDRAM_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Bank Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A14-A16 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A14_A16   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-#elif (CFG_SDRAM_SIZE == 16)
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
- *
- *   configuration parameters found in Motorola documentation
- */
-#define CFG_PSDMR	(0x016EB452)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-
-#define RS232EN_1		0x02000002
-#define RS232EN_2		0x01000001
-#define FETHIEN			0x08000008
-#define FETH_RST		0x04000004
-
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
-/* 0x0EB2B645 */
-#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
-			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
-			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
-			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
-			)
-
-/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
-/* #define CFG_HRCW_MASTER 0x0cb23645 */
-
-/* This value should actually be situated in the first 256 bytes of the FLASH
-	which on the standard MPC8266ADS board is at address 0xFF800000
-	The linker script places it at 0xFFF00000 instead.
-
-	It still works, however, as long as the ADS board jumper JP3 is set to
-	position 2-3 so the board is using the BCSR as Hardware Configuration Word
-
-	If you want to use the one defined here instead, ust copy the first 256 bytes from
-	0xfff00000 to 0xff800000  (for 8MB flash)
-
-	- Rune
-
-*/
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM	0x02	/* Software reboot	     */
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH	1
-#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE	0x40000
-#else
-#  define CFG_ENV_IS_IN_NVRAM	1
-#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
-
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-/*#define CFG_HID0_INIT		0 */
-#define CFG_HID0_INIT	(HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CFG_HID2		0
-
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x004C0000
-#define CFG_SIUMCR		0x4E64C000
-#define CFG_SCCR		0x00000000
-
-/*	local bus memory map
- *
- *	0x00000000-0x03FFFFFF	 64MB	SDRAM
- *	0x80000000-0x9FFFFFFF	512MB	outbound prefetchable PCI memory window
- *	0xA0000000-0xBFFFFFFF	512MB	outbound non-prefetchable PCI memory window
- *	0xF0000000-0xF001FFFF	128KB	MPC8266 internal memory
- *	0xF4000000-0xF7FFFFFF	 64MB	outbound PCI I/O window
- *	0xF8000000-0xF8007FFF	 32KB	BCSR
- *	0xF8100000-0xF8107FFF	 32KB	ATM UNI
- *	0xF8200000-0xF8207FFF	 32KB	PCI interrupt controller
- *	0xF8300000-0xF8307FFF	 32KB	EEPROM
- *	0xFE000000-0xFFFFFFFF	 32MB	flash
- */
-#define CFG_BR0_PRELIM	0xFE001801		/* flash */
-#define CFG_OR0_PRELIM	0xFE000836
-#define CFG_BR1_PRELIM	(CFG_BCSR | 0x1801)	/* BCSR */
-#define CFG_OR1_PRELIM	0xFFFF8010
-#define CFG_BR4_PRELIM	0xF8300801		/* EEPROM */
-#define CFG_OR4_PRELIM	0xFFFF8846
-#define CFG_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
-#define CFG_OR5_PRELIM	0xFFFF8E36
-#define CFG_BR8_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
-#define CFG_OR8_PRELIM	0xFFFF8010
-
-#define CFG_RMR			0x0001
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-#define CFG_MPTPR		0x00001900
-#define CFG_PSRT		0x00000021
-
-/* This address must not exist */
-#define CFG_RESET_ADDRESS	0xFCFFFF00
-
-/* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
-				 PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/* PCIBR0 */
-#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
-#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
-/* PCIBR1 */
-#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
-#define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
-#define CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the third set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CFG_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
-#define CFG_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
-#define CFG_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
deleted file mode 100644
index 418a3a38e6..0000000000
--- a/include/configs/MPC8540EVAL.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Modified by Lunsheng Wang, lunsheng@sohu.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8540eval board configuration file */
-/* please refer to doc/README.mpc85xxads for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE		1	    /* BOOKE 			*/
-#define CONFIG_E500		1	    /* BOOKE e500 family	*/
-#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
-#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
-#define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */
-
-#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
-#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
- * Not availabe for EVAL board
- */
-#undef CONFIG_RAM_AS_FLASH
-
-/* sysclk for MPC8540EVAL */
-#if defined(CONFIG_SYSCLK_66M)
-	/*
-	 * the oscillator on board is 66Mhz
-	 * can also get 66M clock from external PCI
-	 */
-	#define CONFIG_SYS_CLK_FREQ   66000000
-#else
-	#define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
-#undef  CONFIG_BTB			    /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
-
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
-
-#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00400000
-
-#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
-#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
-
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-#else
-#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
-#endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
-#define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
-#else /* Boot from real Flash */
-#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
-#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit	*/
-#endif
-
-#define	CFG_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
-#define CFG_FLASH_CFI		1
-
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
-#else
-#undef  CFG_RAMBOOT
-#endif
-
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-
-/* Here some DDR setting should be added */
-
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/* local bus definitions */
-#define CFG_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
-#define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#else
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#endif
-#define CFG_OR4_PRELIM          0xffffe1f1
-#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX     1
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
-#define CONFIG_BAUDRATE	 	115200
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-
-/* General PCI */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	0x80000000
-#define CFG_PCI_MEM_SIZE	0x20000000
-#define CFG_PCI_IO_BASE         0xe2000000
-
-#if defined(CONFIG_PCI)
-#define CONFIG_NET_MULTI
-#undef CONFIG_EEPRO100
-#define CONFIG_TULIP
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR      0xe0000000
-#define PCI_ENET0_MEMADDR     0xe0000000
-#define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0008
-#elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 	1
-#define CONFIG_MII		1	/* MII PHY management	*/
-#define CONFIG_MPC85XX_TSEC1    1
-#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
-#define CONFIG_MPC85XX_FEC      1
-#define CONFIG_MPC85XX_FEC_NAME                "FEC"
-#define TSEC1_PHY_ADDR          7
-#define	TSEC2_PHY_ADDR		4
-#define FEC_PHY_ADDR            2
-#define TSEC1_PHYIDX            0
-#define TSEC2_PHYIDX            0
-#define FEC_PHYIDX              0
-/* Options are: TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME                "TSEC0"
-
-#define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
-#define INTEL_LXT971_PHY	1
-#endif
-
-#undef DEBUG
-
-/* Environment */
-#ifndef CFG_RAMBOOT
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_ENV_IS_NOWHERE
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
-#define CFG_ENV_SIZE		0x2000
-#else
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-#endif
-#define CFG_ENV_SIZE		0x2000
-#else
-/* #define CFG_NO_FLASH		1 */	/* Flash is not usable now	*/
-#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#define CFG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
-#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-#if defined(CONFIG_PCI)
-#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
-				| CFG_CMD_PCI | CFG_CMD_I2C ) & \
-				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#else
-#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
-				| CFG_CMD_I2C ) & \
-				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#endif
-#else
-#if defined(CONFIG_PCI)
-#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI \
-				| CFG_CMD_PING | CFG_CMD_I2C )
-#else
-#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
-#endif
-#endif
-
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_LOAD_ADDR   0x2000000       /* default load address */
-#define CFG_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE	32768
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*****************************/
-/* Environment Configuration */
-/*****************************/
-/* The mac addresses for all ethernet interface */
-/* NOTE: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR  00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
-#endif
-
-#define CONFIG_ROOTPATH  /nfsroot
-#define CONFIG_BOOTFILE  your.uImage
-
-#define CONFIG_SERVERIP         192.168.101.1
-#define CONFIG_IPADDR           192.168.101.11
-#define CONFIG_GATEWAYIP        192.168.101.0
-#define CONFIG_NETMASK          255.255.255.0
-
-#define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
-
-#define CONFIG_HOSTNAME         MPC8540EVAL
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
deleted file mode 100644
index da52e0ec0b..0000000000
--- a/include/configs/MUSENKI.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the MUSENKI board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_MUSENKI		1
-
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
-
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI      		/* include pci support          */
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
-
-#define CONFIG_TULIP
-
-#define PCI_ENET0_IOADDR		0x80000000
-#define PCI_ENET0_MEMADDR		0x80000000
-#define PCI_ENET1_IOADDR		0x81000000
-#define PCI_ENET1_MEMADDR		0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-
-#define CFG_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  CFG_FLASH_BASE0_PRELIM
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		get_bus_freq(0)
-
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CFG_MONITOR_BASE        TEXT_BASE */
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CFG_HZ		     1000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    7
-#define CFG_ROMFAL	    11
-#define CFG_DBUS_SIZE       0x3
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    121
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    8	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_ACTORW	    3		/* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
-
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	    1
-#define CFG_ENV_ADDR		0xFFFF0000
-#define CFG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
-#define CFG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
deleted file mode 100644
index 88eefa1907..0000000000
--- a/include/configs/MVBLUE.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define MV_VERSION	"v0.2.0"
-
-/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
-#define ERR_NONE			0
-#define ERR_ENV 			1
-#define ERR_BOOTM_BADMAGIC 	2
-#define ERR_BOOTM_BADCRC   	3
-#define ERR_BOOTM_GUNZIP   	4
-#define ERR_BOOTP_TIMEOUT	5
-#define ERR_DHCP			6
-#define ERR_TFTP			7
-#define ERR_NOLAN 			8
-#define ERR_LANDRV 			9
-
-#define CONFIG_BOARD_TYPES	1
-#define MVBLUE_BOARD_BOX	1
-#define MVBLUE_BOARD_LYNX	2
-
-#if 0
-#define ERR_LED(code)	do { if (code) \
-								*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
-							 else \
-								*(volatile char *)(0xff000003) = ( 1 ); \
-						} while(0)
-#else
-#define ERR_LED(code)
-#endif
-
-#undef DEBUG
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_MVBLUE		1
-
-#define CONFIG_CLOCKS_IN_MHZ	1
-
-#define CONFIG_BOARD_TYPES    1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_BOOT_RETRY_TIME	-1
-
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds (stop with 's')...\n"
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		60
-
-#define CONFIG_COMMANDS		( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP	| \
-				  CFG_CMD_ECHO	 | CFG_CMD_ENV   | CFG_CMD_FLASH | CFG_CMD_IMI	| \
-				  CFG_CMD_IRQ	 | CFG_CMD_NET	 | CFG_CMD_PCI	 | CFG_CMD_RUN   )
-
-
-#define CONFIG_BOOTP_MASK   ( 0xffffffff )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		/* undef to save memory		*/
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16			/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address			*/
-
-#define CONFIG_BOOTCOMMAND  	"run nfsboot"
-#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
-
-#define CONFIG_NFSBOOTCOMMAND  	"bootp; run nfsargs addcons;bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS			\
-	"console_nr=0\0"				\
-    "dhcp_client_id=mvBOX-XP\0"				\
-    "dhcp_vendor-class-identifier=mvBOX\0"		\
-    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
-    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
-    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
-    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
-	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
-    "mv_version=" MV_VERSION "\0"	\
-	"bootretry=30\0"
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-#define CONFIG_NET_MULTI
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_FIX_DAVICOM	1
-#define CONFIG_ETHADDR      		b6:b4:45:eb:fb:c0
-
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-
-#define CFG_FLASH_BASE      0xFFF00000
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_LEN     0x00100000
-#define CFG_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
-
-#define CFG_MEMTEST_START   0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
-
-/* Maximum amount of RAM.  */
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-#define CFG_ISA_IO      0xFE000000
-
-/*
- * serial configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE    1
-
-#define CFG_NS16550_CLK     get_bus_freq(0)
-
-#define CFG_NS16550_COM1    (CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2    (CFG_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_SIZE     128
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     	 10000
-
-/* Bit-field values for MCCR1.  */
-#define CFG_ROMNAL      7
-#define CFG_ROMFAL      11
-
-/* Bit-field values for MCCR2.  */
-#define CFG_TSWAIT      0x5
-#define CFG_REFINT      430
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
-#define CFG_BSTOPRE     121
-
-/* Bit-field values for MCCR3.  */
-#define CFG_REFREC      8
-
-/* Bit-field values for MCCR4.  */
-#define CFG_PRETOACT    3
-#define CFG_ACTTOPRE    5
-#define CFG_ACTORW      3
-#define CFG_SDMODE_CAS_LAT  3
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM      1
-#define CFG_REGDIMM     0
-#define CFG_DBUS_SIZE2  1
-#define CFG_SDMODE_WRAP 0
-
-#define CFG_PGMAX       0x32
-#define CFG_SDRAM_DSCD  0x20
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START     0x3ff00000
-#define CFG_BANK1_END       0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START     0x3ff00000
-#define CFG_BANK2_END       0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START     0x3ff00000
-#define CFG_BANK3_END       0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START     0x3ff00000
-#define CFG_BANK4_END       0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START     0x3ff00000
-#define CFG_BANK5_END       0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START     0x3ff00000
-#define CFG_BANK6_END       0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START     0x3ff00000
-#define CFG_BANK7_END       0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#undef  CFG_FLASH_PROTECTION
-#define CFG_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
-
-#define CFG_FLASH_ERASE_TOUT	12000
-#define CFG_FLASH_WRITE_TOUT	1000
-
-
-#define CFG_ENV_IS_IN_FLASH
-
-#define CFG_ENV_OFFSET		0x00010000
-#define CFG_ENV_SIZE		0x00010000
-#define CFG_ENV_SECT_SIZE	0x00010000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
deleted file mode 100644
index 5995918266..0000000000
--- a/include/configs/MVS1.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MVS		1	/* ...on a MVsensor module	*/
-#define CONFIG_MVS_16BIT_FLASH		/* ...with 16-bit flash access	*/
-#define CONFIG_8xx_GCLK_FREQ	50000000/* ... and a 50 MHz CPU		*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#undef	CONFIG_8xx_CONS_SMC1		/* Console is *NOT* on SMC1	*/
-#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate 		*/
-#define CONFIG_BOOTDELAY	5	/* autoboot after this many seconds	*/
-
-#define CONFIG_PREBOOT		"echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use  \"run bootflash\";echo"
-#define	CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND						\
-    "bootp; "                               				\
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
-    "bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG			/* watchdog disabled/enabled	*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled/enabled	*/
-
-#undef  CONFIG_CAN_DRIVER       /* CAN Driver support disabled  */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-/* MVsensor uses a really minimal U-Boot ! */
-#define CONFIG_COMMANDS	       (CFG_CMD_LOADS	| \
-				CFG_CMD_LOADB	| \
-				CFG_CMD_IMI	| \
-				CFG_CMD_FLASH	| \
-				CFG_CMD_MEMORY	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ENV	| \
-				CFG_CMD_BOOTD	| \
-				CFG_CMD_RUN	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#undef  CFG_HUSH_PARSER			/* Hush parse for U-Boot ?? */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/
-
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
-#define	CFG_ENV_OFFSET		0x8000	/* Offset of Environment Sector	(bottom boot sector) */
-#define	CFG_ENV_SIZE		0x2000	/* Used Size of Environment Sector 8k	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-	     SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_PCCARD	0	/* **DON'T** Use IDE with PC Card Adapter	*/
-
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
-#define CFG_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/
-
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#undef FLASH_BASE1_PRELIM
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-
-/*
- * FLASH timing:
- */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-/*
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-*/
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#ifdef CONFIG_MVS_16BIT_FLASH
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-#endif
-
-#undef CFG_OR1_REMAP
-#undef CFG_OR1_PRELIM
-#undef CFG_BR1_PRELIM
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#undef SDRAM_BASE3_PRELIM
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#undef CFG_OR3_PRELIM
-#undef CFG_BR3_PRELIM
-
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#define CFG_MAMR_PTA		 98
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
deleted file mode 100644
index 8da29c4afc..0000000000
--- a/include/configs/NC650.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC852T		1
-#define CONFIG_NC650		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-/*
- * 10 MHz - PLL input clock
- */
-#define CONFIG_8xx_OSCLK		10000000
-
-/*
- * 50 MHz - default CPU clock
- */
-#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
-
-/*
- * 15 MHz - CPU minimum clock
- */
-#define CFG_8xx_CPUCLK_MIN		15000000
-
-/*
- * 133 MHz - CPU maximum clock
- */
-#define CFG_8xx_CPUCLK_MAX		133000000
-
-#define CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN			CONFIG_8xx_OSCLK
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d seconds...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR	"ids"
-#define CONFIG_BOOT_RETRY_TIME		900
-#define CONFIG_BOOT_RETRY_MIN		30
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;" 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
-	"bootm"
-
-#define CONFIG_WATCHDOG			/* watchdog enabled 		*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define FEC_ENET
-#define CONFIG_MII
-#define CFG_DISCOVER_PHY	1
-
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* 100 kHz			*/
-#define CFG_I2C_SLAVE		0x7f
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#if defined(CONFIG_IDS852_REV1)
-
-#define SCL		0x1000		/* PA 3 */
-#define SDA		0x2000		/* PA 2 */
-
-#define __I2C_DIR	immr->im_ioport.iop_padir
-#define __I2C_DAT	immr->im_ioport.iop_padat
-#define __I2C_PAR	immr->im_ioport.iop_papar
-
-#elif defined(CONFIG_IDS852_REV2)
-
-#define SCL		0x0002		/* PB 30 */
-#define SDA		0x0001		/* PB 31 */
-
-#define __I2C_PAR	immr->im_cpm.cp_pbpar
-#define __I2C_DIR	immr->im_cpm.cp_pbdir
-#define __I2C_DAT	immr->im_cpm.cp_pbdat
-
-#endif
-
-#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
-			  __I2C_DIR |= (SDA|SCL);	}
-#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
-#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define	I2C_DELAY	{ udelay(5); }
-#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
-#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
-
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	 	0x00100000
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00740000
-
-#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*
- * NAND flash support
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_ChipID_UNKNOWN	0x00
-#define SECTORSIZE		512
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-#define ADDR_COLUMN		1
-#define NAND_NO_RB
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	| SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: Default value of OR0 after reset */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
-				 OR_SCY_15_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
- * rev2 only uses the chipselect
- */
-#define CFG_NAND_BASE		0x50000000
-#define CFG_NAND_SIZE		0x04000000
-
-#define CFG_OR_TIMING_NAND	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
-#define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
-
-/*
- * BR3 and OR3 (SDRAM)
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank		*/
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
- /*
-  * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
-  */
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * BR4 and OR4 (CPLD)
- */
-#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
-#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */
-
-#define CFG_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-				 OR_SCY_1_CLK)
-
-#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
-
-/*
- * BR5 and OR5 (SRAM)
- */
-#define CFG_SRAM_BASE		0x60000000
-#define CFG_SRAM_SIZE		0x00080000
-
-#define CFG_OR_TIMING_SRAM	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
-
-#if defined(CONFIG_CP850)
-/*
- *  BR6 and OR6 (DPRAM) - only on CP850
- */
-#define CFG_OR6_PRELIM          0xffff8170
-#define CFG_BR6_PRELIM          0xa0000401
-#define DPRAM_BASE_ADDR         0xa0000000
-
-#define CONFIG_MISC_INIT_R      1
-#endif
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4    Number of refresh cycles per period
- * 64   Refresh cycle in ms per number of rows
- */
-#define CFG_PTA_PER_CLK		((4096 * 64 * 1000) / (4 * 64))
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		39
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
-			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
-			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/*
- * MBMR settings for NAND flash
- */
-
-#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x00400000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=nc650-0,nand0=nc650-nand"
-
-#define MTDPARTS_DEFAULT	"mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
-					"4m(cramfs1),1m(cramfs2)," \
-					"256k(u-boot),128k(env);" \
-				"nc650-nand:4m(jffs1),28m(jffs2)"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
deleted file mode 100644
index 444f721cc8..0000000000
--- a/include/configs/NETPHONE.h
+++ /dev/null
@@ -1,812 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
-#error Unsupported CONFIG_NETPHONE version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
-#define CONFIG_NETPHONE		1	/* ...on a NetPhone board	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-
-/* #define CONFIG_XIN		 10000000 */
-#define CONFIG_XIN		 50000000
-/* #define MPC8XX_HZ		120000000 */
-#define MPC8XX_HZ		 66666666
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_AUTOSCRIPT
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
-
-#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
-#define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef CFG_DISCOVER_PHY
-#define CONFIG_MII		1
-#define CONFIG_RMII		1	/* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2	1
-#define CONFIG_FEC2_PHY		4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
-
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PING  	| \
-				CFG_CMD_MII 	| \
-				CFG_CMD_CDP	  \
-				)
-
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_MISC_INIT_R
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#if CONFIG_NETPHONE_VERSION == 2
-#define CFG_FLASH_BASE4		0x40080000
-#endif
-
-#define CFG_RESET_ADDRESS   0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETPHONE_VERSION == 1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#elif CONFIG_NETPHONE_VERSION == 2
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#endif
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x10000
-
-#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_OFFSET		0
-#define	CFG_ENV_SIZE		0x4000
-
-#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_OFFSET_REDUND	0
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  66666666
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK	SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETPHONE_VERSION == 2
-
-#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
-
-#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
-
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CFG_MAMR_PTA		 234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
- */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_ARTOS			/* include ARTOS support */
-
-#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE	0x00010000	/* 64K */
-#define NAND_SIZE	0x00010000	/* 64K */
-
-#define DSP_BASE	0xF1000000
-#define NAND_BASE	0xF1010000
-
-/****************************************************************/
-
-/* NAND */
-#define CFG_NAND_LEGACY
-#define CFG_NAND_BASE		NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CFG_MAX_NAND_DEVICE	1
-
-#define SECTORSIZE		512
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
-	} while(0)
-
-#define NAND_ENABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
-	} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
-	} while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
-	} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
-	} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
-	} while(0)
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define NAND_WAIT_READY(nand) \
-	do { \
-		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
-			if (++_tries > 100000) \
-				break; \
-	} while (0)
-#elif CONFIG_NETPHONE_VERSION == 2
-#define NAND_WAIT_READY(nand) \
-	do { \
-		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
-			if (++_tries > 100000) \
-				break; \
-	} while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define READ_NAND(adr) \
-	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-/*****************************************************************************/
-
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define STATUS_LED_BIT		0x00000008		/* bit 28 */
-#elif CONFIG_NETPHONE_VERSION == 2
-#define STATUS_LED_BIT		0x00000080		/* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
-#define STATUS_LED_STATE	STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
-		else \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
-	} while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
-   (V1) version 1 of the board
-   (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
- | PA7  | DSP_INT        | Output | DSP interrupt
- | PA10 | DSP_RESET      | Output | DSP reset
- | PA14 | USBOE          | Output | USB (1)
- | PA15 | USBRXD         | Output | USB (1)
- | PB19 | BT_RTS         | Output | Bluetooth (0)
- | PB23 | BT_CTS         | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP     | Output | Display chip select
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PC10 | DISPA0         | Output | Display A0
- | PC11 | BACKLIGHT      | Output | Display backlit
- | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
- |      | IO_RESET       | Output | (V2) General I/O reset
- | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
- |      | HOOK           | Input  | (V2) Hook input interrupt
- | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
- |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
- | PE17 | F_ALE          | Output | NAND F_ALE
- | PE18 | F_CLE          | Output | NAND F_CLE
- | PE20 | F_CE           | Output | NAND F_CE
- | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
- |      | LED            | Output | (V2) LED
- | PE27 | SPICS_ER       | Output | External serial register CS
- | PE28 | LEDIO1         | Output | (V1) LED
- |      | BKBR1          | Input  | (V2) Keyboard input scan
- | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
- |      | BKBR2          | Input  | (V2) Keyboard input scan
- | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
- |      | BKBR3          | Input  | (V2) Keyboard input scan
- | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
- |      | BKBR4          | Input  | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register input:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    0 | BKBR1          | (V1) Keyboard input scan
- |    1 | BKBR3          | (V1) Keyboard input scan
- |    2 | BKBR4          | (V1) Keyboard input scan
- |    3 | BKBR2          | (V1) Keyboard input scan
- |    4 | HOOK           | (V1) Hook switch
- |    5 | BT_LINK        | (V1) Bluetooth link status
- |    6 | HOST_WAKE      | (V1) Bluetooth host wake up
- |    7 | OK_ETH         | (V1) Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register output:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    0 | KEY1           | Keyboard output scan
- |    1 | KEY2           | Keyboard output scan
- |    2 | KEY3           | Keyboard output scan
- |    3 | KEY4           | Keyboard output scan
- |    4 | KEY5           | Keyboard output scan
- |    5 | KEY6           | Keyboard output scan
- |    6 | KEY7           | Keyboard output scan
- |    7 | BT_WAKE        | Bluetooth wake up
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_FLASH2      | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP        | DSP interrupt
- | IRQ3 | S_INTER        | DUSLIC ???
- | IRQ4 | F_RY_BY        | NAND
- | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT    | PHY interrupt for #1
- | IP_A3| RMII2_MDINT    | PHY interrupt for #2
- | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
- | IP_A6| OK_ETH         | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define CONFIG_SED156X			1	/* use SED156X */
-#define CONFIG_SED156X_PG12864Q		1	/* type of display used */
-
-/* serial interfacing macros */
-
-#define SED156X_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_RXD_MASK	0x00000008
-
-#define SED156X_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_TXD_MASK	0x00000004
-
-#define SED156X_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_CLK_MASK	0x00000002
-
-#define SED156X_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_CS_MASK		0x00000010
-
-#define SED156X_A0_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
-#define SED156X_A0_MASK		0x0020
-
-/*************************************************************************************************/
-
-#define CFG_CONSOLE_IS_IN_ENV		1
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CFG_CONSOLE_ENV_OVERWRITE	1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
-
-/*************************************************************************************************/
-
-/* phone console configuration */
-
-#define PHONE_CONSOLE_POLL_HZ		(CFG_HZ/200)	/* poll every 5ms */
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID		20
-#define CONFIG_CDP_DEVICE_ID_PREFIX	"NP"	/* netphone */
-#define CONFIG_CDP_PORT_ID		"eth%d"
-#define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
-#define CONFIG_CDP_PLATFORM		"Intracom NetPhone"
-#define CONFIG_CDP_TRIGGER		0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE	1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY	1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
-
-/*************************************************************************************************/
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
deleted file mode 100644
index 25b63457c7..0000000000
--- a/include/configs/NETTA.h
+++ /dev/null
@@ -1,788 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
-#define CONFIG_NETTA		1	/* ...on a NetTA board		*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-
-/* #define CONFIG_XIN		 10000000 */
-#define CONFIG_XIN		 50000000
-#define MPC8XX_HZ		120000000
-/* #define MPC8XX_HZ		100000000 */
-/* #define MPC8XX_HZ		 50000000 */
-/* #define MPC8XX_HZ		 80000000 */
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_HW_WATCHDOG
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
-#define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef  CFG_DISCOVER_PHY		/* do not discover phys */
-#define CONFIG_MII		1
-#define CONFIG_RMII		1	/* use RMII interface */
-
-#if defined(CONFIG_NETTA_ISDN)
-#define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		1   	/* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#undef  CONFIG_ETHER_ON_FEC2
-#else
-#define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8  	/* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#define CONFIG_ETHER_ON_FEC2	1
-#define CONFIG_FEC2_PHY		1   	/* phy address of FEC2 */
-#define CONFIG_FEC2_PHY_NORXERR 1
-#endif
-
-#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
-
-/* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CODEC	   | \
-				 CFG_POST_DSP	   )
-
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
-				CFG_CMD_CDP	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG    | \
-				CFG_CMD_FAT	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_MII 	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCMCIA	| \
-				CFG_CMD_PING  	| \
-				0)
-
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_MISC_INIT_R
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x10000
-
-#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_OFFSET		0
-#define	CFG_ENV_SIZE		0x4000
-
-#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_OFFSET_REDUND	0
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  80000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK	SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
-
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#if   MPC8XX_HZ == 120000000
-#define CFG_MAMR_PTA		 234
-#elif MPC8XX_HZ == 100000000
-#define CFG_MAMR_PTA		 195
-#elif MPC8XX_HZ ==  80000000
-#define CFG_MAMR_PTA		 156
-#elif MPC8XX_HZ ==  50000000
-#define CFG_MAMR_PTA		  98
-#else
-#error Unknown frequency
-#endif
-
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
- */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_ARTOS			/* include ARTOS support */
-
-#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
-
-/***********************************************************************************************************
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | OK_ETH_3V      | Input  | CISCO Ethernet power OK
- |      |                |        | (NetRoute: FEC1, TA: FEC2) (0=power OK)
- | PA6  | P_VCCD1        | Output | TPS2211A PCMCIA
- | PA7  | DCL1_3V        | Periph | IDL1 PCM clock
- | PA8  | DSP_DR1        | Periph | IDL1 PCM Data Rx
- | PA9  | L1TXDA         | Periph | IDL1 PCM Data Tx
- | PA10 | P_VCCD0        | Output | TPS2211A PCMCIA
- | PA12 | P_SHDN         | Output | TPS2211A PCMCIA
- | PA13 | ETH_LOOP       | Output | CISCO Loopback remote power
- |      |                |        | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
- | PA14 | P_VPPD0        | Output | TPS2211A PCMCIA
- | PA15 | P_VPPD1        | Output | TPS2211A PCMCIA
- | PB14 | SPIEN_FXO      | Output | SPI CS for FXO daughter-board
- | PB15 | SPIEN_S1       | Output | SPI CS for S-interface 1 (NetRoute only)
- | PB16 | DREQ1          | Output | D channel request for S-interface chip 1.
- | PB17 | L1ST3          | Periph | IDL1 timeslot enable signal for PPC
- | PB18 | L1ST2          | Periph | IDL1 timeslot enable signal for PPC
- | PB19 | SPIEN_S2       | Output | SPI CS for S-interface 2 (NetRoute only)
- | PB20 | SPIEN_SEEPROM  | Output | SPI CS for serial eeprom
- | PB21 | LEDIO          | Output | Led mode indication for PHY
- | PB22 | UART_CTS       | Input  | UART CTS
- | PB23 | UART_RTS       | Output | UART RTS
- | PB24 | UART_RX        | Periph | UART Data Rx
- | PB25 | UART_TX        | Periph | UART Data Tx
- | PB26 | RMII-MDC       | Periph | Free for future use (MII mgt clock)
- | PB27 | RMII-MDIO      | Periph | Free for future use (MII mgt data)
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PB31 | RMII1-REFCLK   | Periph | RMII reference clock for FEC1
- | PC4  | PHY1_LINK      | Input  | PHY link state FEC1 (interrupt)
- | PC5  | PHY2_LINK      | Input  | PHY link state FEC2 (interrupt)
- | PC6  | RMII1-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
- | PC7  | RMII2-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
- | PC8  | P_OC           | Input  | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
- | PC9  | COM_HOOK1      | Input  | Codec interrupt chip #1 (interrupt)
- | PC10 | COM_HOOK2      | Input  | Codec interrupt chip #2 (interrupt)
- | PC11 | COM_HOOK4      | Input  | Codec interrupt chip #4 (interrupt)
- | PC12 | COM_HOOK3      | Input  | Codec interrupt chip #3 (interrupt)
- | PC13 | F_RY_BY        | Input  | NAND ready signal (interrupt)
- | PC14 | FAN_OK         | Input  | Fan status signal (interrupt) (1=OK)
- | PC15 | PC15_DIRECT0   | Periph | PCMCIA DMA request.
- | PD3  | F_ALE          | Output | NAND
- | PD4  | F_CLE          | Output | NAND
- | PD5  | F_CE           | Output | NAND
- | PD6  | DSP_INT        | Output | DSP debug interrupt
- | PD7  | DSP_RESET      | Output | DSP reset
- | PD8  | RMII_MDC       | Periph | MII mgt clock
- | PD9  | SPIEN_C1       | Output | SPI CS for codec #1
- | PD10 | SPIEN_C2       | Output | SPI CS for codec #2
- | PD11 | SPIEN_C3       | Output | SPI CS for codec #3
- | PD12 | FSC2           | Periph | IDL2 frame sync
- | PD13 | DGRANT2        | Input  | D channel grant from S #2
- | PD14 | SPIEN_C4       | Output | SPI CS for codec #4
- | PD15 | TP700          | Output | Testpoint for software debugging
- | PE14 | RMII2-TXD0     | Periph | FEC2 transmit data
- | PE15 | RMII2-TXD1     | Periph | FEC2 transmit data
- | PE16 | RMII2-REFCLK   | Periph | TA: RMII ref clock for
- |      | DCL2           | Periph | NetRoute: PCM clock #2
- | PE17 | TP703          | Output | Testpoint for software debugging
- | PE18 | DGRANT1        | Input  |  D channel grant from S #1
- | PE19 | RMII2-TXEN     | Periph | TA: FEC2 tx enable
- |      | PCM2OUT        | Periph | NetRoute: Tx data for IDL2
- | PE20 | FSC1           | Periph | IDL1 frame sync
- | PE21 | RMII2-RXD0     | Periph | FEC2 receive data
- | PE22 | RMII2-RXD1     | Periph | FEC2 receive data
- | PE23 | L1ST1          | Periph | IDL1 timeslot enable signal for PPC
- | PE24 | U-N1           | Output | Select user/network for S #1 (0=user)
- | PE25 | U-N2           | Output | Select user/network for S #2 (0=user)
- | PE26 | RMII2-RXDV     | Periph | FEC2 valid
- | PE27 | DREQ2          | Output | D channel request for S #2.
- | PE28 | FPGA_DONE      | Input  | FPGA done signal
- | PE29 | FPGA_INIT      | Output | FPGA init signal
- | PE30 | UDOUT2_3V      | Input  | IDL2 PCM input
- | PE31 |                |        | Free
- +------+----------------+--------+---------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_ER1         | External output register
- +------+----------------+------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V      | S interupt chips interrupt (common)
- | IRQ3 | IRQ_DSP        | DSP interrupt
- | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define DSP_SIZE	0x00010000	/* 64K */
-#define NAND_SIZE	0x00010000	/* 64K */
-#define ER_SIZE		0x00010000	/* 64K */
-#define DUMMY_SIZE	0x00010000	/* 64K */
-
-#define DSP_BASE	0xF1000000
-#define NAND_BASE	0xF1010000
-#define ER_BASE		0xF1020000
-#define DUMMY_BASE	0xF1FF0000
-
-/****************************************************************/
-
-/* NAND */
-#define CFG_NAND_LEGACY
-#define CFG_NAND_BASE			NAND_BASE
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CFG_MAX_NAND_DEVICE		1
-/* #define NAND_NO_RB */
-
-#define SECTORSIZE		512
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-
-/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
-#define NAND_DISABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 5)); \
-	} while(0)
-
-#define NAND_ENABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
-	} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
-	} while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 3)); \
-	} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
-	} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 4)); \
-	} while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
-	do { \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
-			WATCHDOG_RESET(); \
-		} \
-	} while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define READ_NAND(adr) \
-	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#define CONFIG_JFFS2_NAND	1			/* jffs2 on nand support */
-#define NAND_CACHE_PAGES	16			/* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x00100000
-#define CONFIG_JFFS2_PART_OFFSET	0x00200000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nand0=netta-nand"
-#define MTDPARTS_DEFAULT	"mtdparts=netta-nand:1m@2m(jffs2)"
-*/
-
-/*****************************************************************************/
-
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
-
-/*****************************************************************************/
-
-#if 1
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID		20
-#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta */
-#define CONFIG_CDP_PORT_ID		"eth%d"
-#define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot 1.0" " " __DATE__ " " __TIME__
-#define CONFIG_CDP_PLATFORM		"Intracom NetTA"
-#define CONFIG_CDP_TRIGGER		0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE	1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY	1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
-
-/*************************************************************************************************/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
deleted file mode 100644
index e20e72495c..0000000000
--- a/include/configs/NETTA2.h
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
-#error Unsupported CONFIG_NETTA2 version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
-#define CONFIG_NETTA2		1	/* ...on a NetTA2 board		*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-
-/* #define CONFIG_XIN		 10000000 */
-#define CONFIG_XIN		 50000000
-/* #define MPC8XX_HZ		120000000 */
-#define MPC8XX_HZ		 66666666
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_AUTOSCRIPT
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
-
-#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
-#define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef CFG_DISCOVER_PHY
-#define CONFIG_MII		1
-#define CONFIG_RMII		1	/* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2	1
-#define CONFIG_FEC2_PHY		4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
-
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PING  	| \
-				CFG_CMD_MII 	| \
-				CFG_CMD_CDP	  \
-				)
-
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_MISC_INIT_R
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#if CONFIG_NETTA2_VERSION == 2
-#define CFG_FLASH_BASE4		0x40080000
-#endif
-
-#define CFG_RESET_ADDRESS   0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETTA2_VERSION == 1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#elif CONFIG_NETTA2_VERSION == 2
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#endif
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x10000
-
-#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_OFFSET		0
-#define	CFG_ENV_SIZE		0x4000
-
-#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_OFFSET_REDUND	0
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  66666666
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK	SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETTA2_VERSION == 2
-
-#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
-
-#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
-
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CFG_MAMR_PTA		 234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
- */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#define CONFIG_ARTOS			/* include ARTOS support */
-
-#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE	0x00010000	/* 64K */
-#define NAND_SIZE	0x00010000	/* 64K */
-
-#define DSP_BASE	0xF1000000
-#define NAND_BASE	0xF1010000
-
-/****************************************************************/
-
-/* NAND */
-#define CFG_NAND_LEGACY
-#define CFG_NAND_BASE		NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CFG_MAX_NAND_DEVICE	1
-
-#define SECTORSIZE		512
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
-	} while(0)
-
-#define NAND_ENABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
-	} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
-	} while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
-	} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
-	} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
-	} while(0)
-
-#if CONFIG_NETTA2_VERSION == 1
-#define NAND_WAIT_READY(nand) \
-	do { \
-		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
-			if (++_tries > 100000) \
-				break; \
-	} while (0)
-#elif CONFIG_NETTA2_VERSION == 2
-#define NAND_WAIT_READY(nand) \
-	do { \
-		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
-			if (++_tries > 100000) \
-				break; \
-	} while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define READ_NAND(adr) \
-	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-/*****************************************************************************/
-
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETTA2_VERSION == 1
-#define STATUS_LED_BIT		0x00000008		/* bit 28 */
-#elif CONFIG_NETTA2_VERSION == 2
-#define STATUS_LED_BIT		0x00000080		/* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
-#define STATUS_LED_STATE	STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
-		else \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
-	} while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
-   (V1) version 1 of the board
-   (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
- | PA7  | DSP_INT        | Output | DSP interrupt
- | PA10 | DSP_RESET      | Output | DSP reset
- | PA14 | USBOE          | Output | USB (1)
- | PA15 | USBRXD         | Output | USB (1)
- | PB19 | BT_RTS         | Output | Bluetooth (0)
- | PB23 | BT_CTS         | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP     | Output | Display chip select
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PC10 | DISPA0         | Output | Display A0
- | PC11 | BACKLIGHT      | Output | Display backlit
- | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
- |      | IO_RESET       | Output | (V2) General I/O reset
- | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
- |      | HOOK           | Input  | (V2) Hook input interrupt
- | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
- |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
- | PE17 | F_ALE          | Output | NAND F_ALE
- | PE18 | F_CLE          | Output | NAND F_CLE
- | PE20 | F_CE           | Output | NAND F_CE
- | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
- |      | LED            | Output | (V2) LED
- | PE27 | SPICS_ER       | Output | External serial register CS
- | PE28 | LEDIO1         | Output | (V1) LED
- |      | BKBR1          | Input  | (V2) Keyboard input scan
- | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
- |      | BKBR2          | Input  | (V2) Keyboard input scan
- | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
- |      | BKBR3          | Input  | (V2) Keyboard input scan
- | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
- |      | BKBR4          | Input  | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register input:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    4 | HOOK           | Hook switch
- |    5 | BT_LINK        | Bluetooth link status
- |    6 | HOST_WAKE      | Bluetooth host wake up
- |    7 | OK_ETH         | Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_FLASH2      | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP        | DSP interrupt
- | IRQ3 | S_INTER        | DUSLIC ???
- | IRQ4 | F_RY_BY        | NAND
- | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT    | PHY interrupt for #1
- | IP_A3| RMII2_MDINT    | PHY interrupt for #2
- | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
- | IP_A6| OK_ETH         | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-**************************************************************************************************/
-
-#define CFG_CONSOLE_IS_IN_ENV		1
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CFG_CONSOLE_ENV_OVERWRITE	1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID		20
-#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
-#define CONFIG_CDP_PORT_ID		"eth%d"
-#define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
-#define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
-#define CONFIG_CDP_TRIGGER		0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone ? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE	1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY	1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
-
-/*************************************************************************************************/
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
deleted file mode 100644
index e30be0987a..0000000000
--- a/include/configs/NETVIA.h
+++ /dev/null
@@ -1,532 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetVia board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#else
-#define CONFIG_8xx_CONS_NONE
-#define CONFIG_MAX3100_SERIAL
-#endif
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-
-#define CONFIG_XIN		10000000
-#define CONFIG_8xx_GCLK_FREQ	80000000
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
-#endif
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS_BASE  ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PING )
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_COMMANDS		(CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
-#else
-#define CONFIG_COMMANDS		CONFIG_COMMANDS_BASE
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x10000
-
-#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_OFFSET		0
-#define	CFG_ENV_SIZE		0x4000
-
-#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_OFFSET_REDUND	0
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- *
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK	SCCR_EBDF11
-
-#if CONFIG_8xx_GCLK_FREQ == 50000000
-
-#define CFG_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-#elif CONFIG_8xx_GCLK_FREQ == 80000000
-
-#define CFG_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00 | SCCR_EBDF01)
-
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
-
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	208
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/* Ethernet at SCC2 */
-#define CONFIG_SCC2_ENET
-
-#define CONFIG_ARTOS			/* include ARTOS support */
-
-/****************************************************************/
-
-#define DSP_SIZE	0x00010000	/* 64K */
-#define FPGA_SIZE	0x00010000	/* 64K */
-
-#define DSP0_BASE	0xF1000000
-#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
-#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-#define ER_SIZE		0x00010000	/* 64K */
-#define ER_BASE		(FPGA_BASE + FPGA_SIZE)
-
-#define NAND_SIZE	0x00010000	/* 64K */
-#define NAND_BASE	(ER_BASE + ER_SIZE)
-
-#endif
-
-/****************************************************************/
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-#define STATUS_LED_BIT		0x00000001		/* bit 31 */
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
-#define STATUS_LED_STATE	STATUS_LED_BLINKING
-
-#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
-#define STATUS_LED_PERIOD1	(CFG_HZ / 2)
-#define STATUS_LED_STATE1	STATUS_LED_OFF
-
-#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
-
-#endif
-
-/*****************************************************************************/
-
-#define CFG_NAND_LEGACY
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-/* NAND */
-#define CFG_NAND_BASE			NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-#define CFG_MAX_NAND_DEVICE		1
-
-#define SECTORSIZE		512
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-
-#define NAND_DISABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0040; \
-	} while(0)
-
-#define NAND_ENABLE_CE(nand) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
-	} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
-	} while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0100; \
-	} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
-	} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
-	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0080; \
-	} while(0)
-
-#define NAND_WAIT_READY(nand) \
-	do { \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
-			; \
-	} while (0)
-
-#define WRITE_NAND_COMMAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define WRITE_NAND(d, adr) \
-	do { \
-		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
-	} while(0)
-
-#define READ_NAND(adr) \
-	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#endif
-
-/*****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-/* LEDs */
-
-/* last value written to the external register; we cannot read back */
-extern unsigned int last_er_val;
-
-/* led_id_t is unsigned long mask */
-typedef unsigned int led_id_t;
-
-static inline void __led_init(led_id_t mask, int state)
-{
-	unsigned int new_er_val;
-
-	if (state)
-		new_er_val = last_er_val & ~mask;
-	else
-		new_er_val = last_er_val |  mask;
-
-	*(volatile unsigned int *)ER_BASE = new_er_val;
-	last_er_val = new_er_val;
-}
-
-static inline void __led_toggle(led_id_t mask)
-{
-	unsigned int new_er_val;
-
-	new_er_val = last_er_val ^ mask;
-	*(volatile unsigned int *)ER_BASE = new_er_val;
-	last_er_val = new_er_val;
-}
-
-static inline void __led_set(led_id_t mask, int state)
-{
-	unsigned int new_er_val;
-
-	if (state)
-		new_er_val = last_er_val & ~mask;
-	else
-		new_er_val = last_er_val |  mask;
-
-	*(volatile unsigned int *)ER_BASE = new_er_val;
-	last_er_val = new_er_val;
-}
-
-/* MAX3100 console */
-#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_RXD_BIT	0x00000008
-
-#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_TXD_BIT	0x00000004
-
-#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define MAX3100_SPI_CLK_BIT	0x00000002
-
-#define MAX3100_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
-#define MAX3100_CS_BIT		0x0010
-
-#endif
-
-#endif
-
-/*************************************************************************************************/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
deleted file mode 100644
index 1cb8b8ff3b..0000000000
--- a/include/configs/NX823.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU	    */
-#define CONFIG_NX823		1	/* ...on a NEXUS 823  module	*/
-
-/*#define  CONFIG_VIDEO		1 */
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 57600	/* console baudrate = 115kbps	*/
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
-#define CONFIG_BOOTARGS		"ramdisk=8000 "\
-				"root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
-				"nfsaddrs=10.77.77.20:10.77.77.250"
-#define CONFIG_BOOTCOMMAND	"bootm 400e0000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-#undef	CONFIG_WATCHDOG			/* watchdog disabled, for now	    */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS	 	(CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
-#define CONFIG_AUTOSCRIPT
-
-/* call various generic functions */
-#define CONFIG_MISC_INIT_R
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN 	(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define xEMBED
-#ifdef	EMBED
-#define CFG_ENV_SIZE		0x200	/* FIXME How big when embedded?? */
-#define CFG_ENV_ADDR		CFG_MONITOR_BASE
-#else
-#define CFG_ENV_ADDR		0x40020000	/* absolute address for now   */
-#define CFG_ENV_SIZE		0x20000 /* 8K ouch, this may later be */
-#endif
-
-#define CFG_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
-#define CFG_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
-#define CFG_FLASH_SN_BYTES	8
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				12-30
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				12-16
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		12-18
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		12-23
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		5-7
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define MPC8XX_SPEED	66666666L
-#define MPC8XX_XIN	32768	/* 32.768 kHz crystal */
-#define MPC8XX_FACT		(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
-#define CFG_PLPRCR		(CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		5-3
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER		0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0    */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
-				 OR_SCY_8_CLK )
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/2 and OR1/2 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0    */
-#define SDRAM_BASE2_PRELIM	0x20000000	/* SDRAM bank #1    */
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
-
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_OR2_PRELIM	CFG_OR1_PRELIM
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* IO and memory mapped stuff */
-#define NX823_IO_OR_AM		0xFFFF0000	/* mask for IO addresses */
-#define NX823_IO_BASE		0xFF000000	/* start of IO	*/
-#define GPOUT_OFFSET		(3<<16)
-#define QUART_OFFSET		(4<<16)
-#define VIDAC_OFFSET		(5<<16)
-#define CPLD_OFFSET		(6<<16)
-#define SED1386_OFFSET		(7<<16)
-
-/*
- * BR3 and OR3 (general purpose output latches)
- */
-#define GPOUT_BASE	(NX823_IO_BASE + GPOUT_OFFSET)
-#define GPOUT_TIMING	(OR_CSNT_SAM | OR_TRLX | OR_BI)
-#define CFG_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
-#define CFG_BR3_PRELIM	(GPOUT_BASE | BR_V)
-
-/*
- * BR4 and OR4 (QUART)
- */
-#define QUART_BASE	(NX823_IO_BASE + QUART_OFFSET)
-#define QUART_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
-#define CFG_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
-#define CFG_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR5 and OR5 (Video DAC)
- */
-#define VIDAC_BASE	(NX823_IO_BASE + VIDAC_OFFSET)
-#define VIDAC_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
-#define CFG_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR6 and OR6 (CPLD)
- * FIXME timing not verified for CPLD
- */
-#define CPLD_BASE	(NX823_IO_BASE + CPLD_OFFSET)
-#define CPLD_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
-#define CFG_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
-
-/*
- * BR7 and OR7 (SED1386)
- * FIXME timing not verified for SED controller
- */
-#define SED1386_BASE	0xF7000000
-#define CFG_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
-#define CFG_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz   */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02	/* Software reboot	    */
-
-#define CONFIG_ENV_OVERWRITE	/* allow changes to ethaddr (for now)	*/
-#define CONFIG_ETHADDR		00:10:20:30:40:50
-#define CONFIG_IPADDR		10.77.77.20
-#define CONFIG_SERVERIP		10.77.77.250
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
deleted file mode 100644
index aa9d1ba735..0000000000
--- a/include/configs/OCRTC.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "go fff00100"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
-#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (PLD - OSL) initialization					*/
-#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 4 (Spartan2 1) initialization					*/
-#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 5 (Spartan2 2) initialization					*/
-#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 6 (Virtex 1) initialization					*/
-#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 7 (Virtex 2) initialization					*/
-#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
-
-
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
deleted file mode 100644
index 787407c5eb..0000000000
--- a/include/configs/OXC.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8240		1
-#define CONFIG_OXC		1
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define CONFIG_IDENT_STRING     " [oxc] "
-
-#define CONFIG_WATCHDOG		1
-#define CONFIG_SHOW_ACTIVITY	1
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
-
-/*-----------------------------------------------------------------------
- * Boot options
- */
-
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_LOADADDR		0x10000
-#define CONFIG_BOOTFILE		"/mnt/ide0/p2/usr/tftp/oxc.elf"
-#define CONFIG_BOOTCOMMAND	"tftp 0x10000 ; bootelf 0x10000"
-#define CONFIG_BOOTDELAY	10
-
-#define CFG_OXC_GENERATE_IP	1		/* Generate IP automatically	*/
-#define CFG_OXC_IPMASK		0x0A000000	/* 10.0.0.x			*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-
-#define CONFIG_PCI				/* include pci support		*/
-
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
-
-#define CONFIG_EEPRO100				/* Ethernet Express PRO 100	*/
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-/*-----------------------------------------------------------------------
- * FLASH
- */
-
-#define CFG_FLASH_PRELIMBASE	0xFF800000
-#define CFG_FLASH_BASE		(0-flash_info[0].size)
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * RAM
- */
-
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		0x00030000
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-/*-----------------------------------------------------------------------
- * Memory mapping
- */
-
-#define CFG_CPLD_BASE		0xff000000	/* CPLD registers */
-#define CFG_CPLD_WATCHDOG	(CFG_CPLD_BASE)			/* Watchdog */
-#define CFG_CPLD_RESET		(CFG_CPLD_BASE + 0x040000)	/* Minor resets */
-#define CFG_UART_BASE		(CFG_CPLD_BASE + 0x700000)	/* debug UART */
-
-/*-----------------------------------------------------------------------
- * NS16550 Configuration
- */
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	-4
-#define CFG_NS16550_CLK		1843200
-#define CFG_NS16550_COM1	CFG_UART_BASE
-
-/*-----------------------------------------------------------------------
- * I2C Bus
- */
-
-#define CONFIG_I2C		1		/* I2C support on ... */
-#define CONFIG_HARD_I2C		1		/* ... hardware one */
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F		/* I2C slave address */
-
-#define CFG_I2C_EXPANDER0_ADDR	0x20		/* PCF8574 expander 0 addrerr */
-#define CFG_I2C_EXPANDER1_ADDR	0x21		/* PCF8574 expander 1 addrerr */
-#define CFG_I2C_EXPANDER2_ADDR	0x26		/* PCF8574 expander 2 addrerr */
-
-/*-----------------------------------------------------------------------
- * Environment
- */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0xFFF30000	/* Offset of Environment Sector	*/
-#define CFG_ENV_SIZE		0x00010000	/* Total Size of Environment Sector */
-#define	CFG_ENV_IS_EMBEDDED	1		/* short-cut compile-time test	*/
-#define CONFIG_ENV_OVERWRITE    1		/* Allow modifying the environment */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
-
-#define CFG_EUMB_ADDR		0xFC000000
-
-/* MCCR1 */
-#define CFG_ROMNAL		0	/* rom/flash next access time		*/
-#define CFG_ROMFAL		19	/* rom/flash access time		*/
-
-/* MCCR2 */
-#define CFG_ASRISE		15	/* ASRISE=15 clocks			*/
-#define CFG_ASFALL		3	/* ASFALL=3 clocks			*/
-#define CFG_REFINT		1000	/* REFINT=1000 clocks			*/
-
-/* MCCR3 */
-#define CFG_BSTOPRE		0x35c	/* Burst To Precharge			*/
-#define CFG_REFREC		7	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-
-/* MCCR4 */
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	3	/* SDMODE Burst length 2=4, 3=8		*/
-#define CFG_REGISTERD_TYPE_BUFFER   1
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x00000000
-#define CFG_BANK1_END		0x00000000
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x00000000
-#define CFG_BANK2_END		0x00000000
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x00000000
-#define CFG_BANK3_END		0x00000000
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
deleted file mode 100644
index 9d5c4f4d04..0000000000
--- a/include/configs/PCI405.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IDENT_STRING     " $Name: esd_PCI405_05_07_28 $"
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/
-
-#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"mem_linux=14336k\0"					        \
-	"optargs=panic=0\0"					        \
-	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
-	"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
-	""
-#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcon;loadpci"
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-
-#if 0 /* test-only */
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-#else
-#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization					*/
-#define CFG_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
-#define CFG_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-/*#define CFG_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (FPGA internal) initialization					*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	0x0001
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	0x2000
-
-/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
-/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
-#define CFG_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
deleted file mode 100644
index 3a97fbcbde..0000000000
--- a/include/configs/PCIPPC2.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the PCIPPC-2 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_PREBOOT		""
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define	CFG_MAXARGS	64		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-#define CFG_FLASH_MAX_SIZE  0x00100000
-/* Maximum amount of RAM.
- */
-#define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb			*/
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
-    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
-#define CFG_RAMBOOT
-#else
-#undef CFG_RAMBOOT
-#endif
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* Size in bytes reserved for initial data
- */
-#define CFG_GBL_DATA_SIZE    128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x8000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
-
-#define CFG_INIT_RAM_LOCK
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
-#define CFG_SCONSOLE_SIZE     0x0002000
-
-/* SDRAM 0 - 256MB
- */
-#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
-			       BATU_BL_256M | BATU_VS | BATU_VP)
-/* SDRAM 1 - 256MB
- */
-#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
-			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
-			       BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Init RAM in the CPU DCache (no backing memory)
- */
-#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
-			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
-			       BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* I/O and PCI memory at 0xf0000000
- */
-#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT0L	      CFG_DBAT0L
-#define CFG_IBAT0U	      CFG_DBAT0U
-#define CFG_IBAT1L	      CFG_DBAT1L
-#define CFG_IBAT1U	      CFG_DBAT1U
-#define CFG_IBAT2L	      CFG_DBAT2L
-#define CFG_IBAT2U	      CFG_DBAT2U
-#define CFG_IBAT3L	      CFG_DBAT3L
-#define CFG_IBAT3U	      CFG_DBAT3U
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the PCIPPC2 user's manual.
- */
-#define CFG_HZ		      1000
-#define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
-#define CFG_CPU_CLK	      300000000
-#define CFG_BUS_CLK	      100000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	      (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-/*
- * Note: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
-#define CFG_ENV_SIZE		0x1000	/* Size of the Environment		*/
-#define CFG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * L2 cache
- */
-#undef CFG_L2
-#define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-
-#define CFG_DOC_SUPPORT_2000
-#undef CFG_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
-  RTC m48t59
-*/
-#define CONFIG_RTC_MK48T59
-
-#define CONFIG_WATCHDOG
-
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_TULIP
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
deleted file mode 100644
index dd5d831680..0000000000
--- a/include/configs/PLU405.h
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#define CONFIG_BAUDRATE		9600
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#if 0 /* test-only */
-#define CONFIG_NET_MULTI	1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
-#else
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#endif
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#if 1 /* test-only */
-/* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last 5 bits of the address	*/
-#endif
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
-#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
-#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
-
-/* FPGA internal regs */
-#define CFG_FPGA_CTRL		0x000
-
-/* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET	0x0001
-#define CFG_FPGA_CTRL_WDI	0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
deleted file mode 100644
index 9c241e67e7..0000000000
--- a/include/configs/PM520.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_PM520		1	/* ... on PM520 board */
-
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_NET_MULTI	1
-#define CONFIG_MII		1
-#define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#undef  CONFIG_NS8382X
-
-#define ADD_PCI_CMD 		CFG_CMD_PCI
-
-#else	/* MPC5100 */
-
-#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
-
-#endif
-
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD             0
-#endif
-
-#if defined(CONFIG_BOOT_ROM)
-#define ADD_DOC_CMD             0
-#else
-#define ADD_DOC_CMD             CFG_CMD_DOC
-/* DoC requires legacy NAND for now */
-#define CFG_NAND_LEGACY
-#endif
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				ADD_DOC_CMD	| \
-				ADD_PCI_CMD	| \
-				ADD_USB_CMD	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=pm520\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk30/ppc_82xx\0"					\
-	"bootfile=/tftpboot/PM520/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if defined(CONFIG_MPC5200)
-/*
- * IPB Bus clocking configuration.
- */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
-#endif
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
-
-/*
- * Disk-On-Chip configuration
- */
-
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#define CFG_DOC_BASE		0xE0000000
-#define CFG_DOC_SIZE		0x00100000
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFA000000 for 64 MB
- *               0xFC000000 for 32 MB
- *               0xFD000000 for 16 MB
- *               0xFD800000 for  8 MB
- */
-#define CFG_FLASH_BASE		0xFA000000
-#define CFG_FLASH_SIZE		0x04000000
-#define CFG_BOOTROM_BASE	0xFFF00000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_ENV_ADDR		(0xFDF00000 + 0x40000)
-#else
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
- */
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_SIZE		0x04000000
-#define CFG_ENV_ADDR		(0xFFF00000 + 0x40000)
-#endif
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#undef CONFIG_FLASH_16BIT	/* Flash is 32-bit */
-
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000
-#define CFG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xf0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- */
-#define CFG_GPS_PORT_CONFIG	0x10000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_BOOTCS_START	CFG_BOOTROM_BASE
-#define CFG_BOOTCS_SIZE		CFG_BOOTROM_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
-#define CFG_CS0_START		CFG_BOOTROM_BASE
-#define CFG_CS0_SIZE		CFG_BOOTROM_SIZE
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_CFG		0x0004FF00
-#else
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004FF00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_START		CFG_DOC_BASE
-#define CFG_CS1_SIZE		CFG_DOC_SIZE
-#define CFG_CS1_CFG		0x00047800
-#endif
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00005000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
deleted file mode 100644
index 88fdb51ade..0000000000
--- a/include/configs/PM826.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CFG_RAMBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
-#define CONFIG_PM826		1	/* ...on a PM8260 module	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if CONFIG_ETHER_ON_SCC is selected, then
- *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
- *   - CONFIG_NET_MULTI must not be defined
- *
- * if CONFIG_ETHER_ON_FCC is selected, then
- *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
- *   - CONFIG_NET_MULTI must be defined
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#define	CONFIG_NET_MULTI
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
-
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK10
- */
-#define	CONFIG_ETHER_ON_FCC1
-# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-#ifndef CONFIG_DB_CR826_J30x_ON
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
-#else
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-#endif
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK14
- */
-#define	CONFIG_ETHER_ON_FCC2
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-/*
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	64000000	/* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-#else	/* ! PCI */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-#endif	/* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
-/*
- * Disk-On-Chip configuration
- */
-
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash and Boot ROM mapping
- */
-#ifdef CONFIG_FLASH_32MB
-#define	CFG_FLASH0_BASE		0x40000000
-#define	CFG_FLASH0_SIZE		0x02000000
-#else
-#define	CFG_FLASH0_BASE		0xFF000000
-#define	CFG_FLASH0_SIZE		0x00800000
-#endif
-#define	CFG_BOOTROM_BASE	0xFF800000
-#define	CFG_BOOTROM_SIZE	0x00080000
-#define CFG_DOC_BASE		0xFF800000
-#define CFG_DOC_SIZE		0x00100000
-
-/* Flash bank size (for preliminary settings)
- */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#ifdef CONFIG_FLASH_32MB
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
-#else
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#endif
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
-#define CFG_ENV_SIZE		0x40000
-#define CFG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		512
-#define CFG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
-#endif
-
-#ifdef	CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-
-#define BCR_APD01       0x10000000
-#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
-#else
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR        (SCCR_DFBRG00)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CFG_INIT_LOCAL_SDRAM
-
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CFG_MIN_AM_MASK	0xC0000000
-
-/*
- * we use the same values for 32 MB and 128 MB SDRAM
- * refresh rate = 7.73 uS (64 MHz Bus Clock)
- */
-#define CFG_MPTPR       0x2000
-#define CFG_PSRT        0x0E
-
-#define CFG_MRS_OFFS	0x00000000
-
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Bank 0 - Boot ROM (8 bit wide)
- */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_3_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-/*
- * Bank 1 - Flash (64 bit wide)
- */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_3_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-#else	/* ! CONFIG_BOOT_ROM */
-
-/*
- * Bank 0 - Flash (64 bit wide)
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-/*
- * Bank 1 - Disk-On-Chip
- */
-#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_3_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-#endif /* CONFIG_BOOT_ROM */
-
-/* Bank 2 - SDRAM
- */
-
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A9             |\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
-			 PSDMR_BSMA_A14_A16             |\
-			 PSDMR_SDA10_PBI0_A10           |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_1W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_1C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A7             |\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI0_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_1W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_1C                   |\
-			 PSDMR_CL_2)
-
-#define CFG_OR2_PRELIM   CFG_OR2_9COL
-#define CFG_PSDMR        CFG_PSDMR_9COL
-
-#endif /* CFG_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
deleted file mode 100644
index 37ee9771b5..0000000000
--- a/include/configs/PM828.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CFG_RAMBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
-#define CONFIG_PM828		1	/* ...on a PM828 module */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else	iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else	iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if CONFIG_ETHER_ON_SCC is selected, then
- *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
- *   - CONFIG_NET_MULTI must not be defined
- *
- * if CONFIG_ETHER_ON_FCC is selected, then
- *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
- *   - CONFIG_NET_MULTI must be defined
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#define CONFIG_NET_MULTI
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
-
-#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-/*
- * - Rx-CLK is CLK11
- * - Tx-CLK is CLK10
- */
-#define CONFIG_ETHER_ON_FCC1
-# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-#ifndef CONFIG_DB_CR826_J30x_ON
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
-#else
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-#endif
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK14
- */
-#define CONFIG_ETHER_ON_FCC2
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-/*
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	100000000	/* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-#else	/* ! PCI */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-#endif	/* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Disk-On-Chip configuration
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	     (8 << 20)	     /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash and Boot ROM mapping
- */
-
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH0_BASE		0x40000000
-#define CFG_FLASH0_SIZE		0x02000000
-#define CFG_DOC_BASE		0xFF800000
-#define CFG_DOC_SIZE		0x00100000
-
-
-/* Flash bank size (for preliminary settings)
- */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
-#define CFG_ENV_SIZE		0x40000
-#define CFG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_ENV_OFFSET		512
-#define CFG_ENV_SIZE		(2048 - 512)
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
-#endif
-
-#ifdef	CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot		   */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
-#else
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR	(SCCR_DFBRG00)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	64 bit	FLASH
- *  1	60x	SDRAM	64 bit	SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CFG_INIT_LOCAL_SDRAM
-
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CFG_MIN_AM_MASK 0xC0000000
-
-/*
- * we use the same values for 32 MB and 128 MB SDRAM
- * refresh rate = 7.68 uS (100 MHz Bus Clock)
- */
-#define CFG_MPTPR	0x2000
-#define CFG_PSRT	0x16
-
-#define CFG_MRS_OFFS	0x00000000
-
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Bank 0 - Boot ROM (8 bit wide)
- */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-/*
- * Bank 1 - Flash (64 bit wide)
- */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-#else	/* ! CONFIG_BOOT_ROM */
-
-/*
- * Bank 0 - Flash (64 bit wide)
- */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-/*
- * Bank 1 - Disk-On-Chip
- */
-#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_EHTR			|\
-			 ORxG_TRLX)
-
-#endif /* CONFIG_BOOT_ROM */
-
-/* Bank 2 - SDRAM
- */
-
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
-			 PSDMR_BSMA_A14_A16		|\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
-			 PSDMR_BSMA_A13_A15		|\
-			 PSDMR_SDA10_PBI0_A9		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_2W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
-#define CFG_PSDMR	 CFG_PSDMR_9COL
-
-#endif /* CFG_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
deleted file mode 100644
index 16e2cc6d64..0000000000
--- a/include/configs/PPChameleonEVB.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef	CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef	__DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-# define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef CONFIG_EXT_PHY
-#define CONFIG_NET_MULTI	1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#ifndef	 CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
-#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
-#else
-#define CONFIG_PHY_ADDR		2	/* PHY address			*/
-#endif
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_M41T11	1	/* uses a M41T00 RTC		*/
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/* SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL            2
-#define CFG_SDRAM_tRP           20
-#define CFG_SDRAM_tRC           65
-#define CFG_SDRAM_tRCD          20
-#undef  CFG_SDRAM_tRFC
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD		691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-/*
- * nand device 1 on dave (PPChameleonEVB) needs more time,
- * so we just introduce additional wait in nand_wait(),
- * effectively for both devices.
- */
-#define PPCHAMELON_NAND_TIMER_HACK
-
-#define CFG_NAND0_BASE 0xFF400000
-#define CFG_NAND1_BASE 0xFF000000
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE, CFG_NAND1_BASE }
-#define NAND_BIG_DELAY_US	25
-#define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
-
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
-#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
-#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-
-#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
-#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
-#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
-	switch((unsigned long)nandptr) { \
-	case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
-		break; \
-	case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-#if 0
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
-	udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-#endif
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-
-/* Reserve 256 kB for Monitor	*/
-/*
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)
-*/
-
-/* Reserve 320 kB for Monitor	*/
-#define CFG_FLASH_BASE		0xFFFB0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(320 * 1024)
-
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#ifdef ENVIRONMENT_IN_EEPROM
-
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
-
-#else	/* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CFG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
-#define CFG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
-#define CFG_ENV_ADDR_REDUND	0xFFFFA000
-#define CFG_ENV_SIZE_REDUND	0x2000
-
-#endif	/* ENVIRONMENT_IN_EEPROM */
-
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization					*/
-/* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB2AP		0x92015480
-#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB3AP		0x92015480
-#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CFG_ISA_IO 0xE8000000
-/* see also drivers/videomodes.c */
-#define CFG_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	0x0001
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	0x2000
-
-/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
-#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
-#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
-#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
-#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30]	- EMAC0 input
- * GPIO0[31]	- EMAC1 reject packet as output
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-/*#define CFG_GPIO0_ISR1L	0x15555445*/
-#define CFG_GPIO0_ISR1L		0x15555444
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FF8014
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!	are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef		AUTO_MEMORY_CONFIG
-#define		DIMM_READ_ADDR 0xAB
-#define		DIMM_WRITE_ADDR 0xAA
-
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		0x80000000
-#define CPC0_PLLMR1_SSCS	0x80000000
-#define PLL_RESET		0x40000000
-#define CPC0_PLLMR1_PLLR	0x40000000
-    /* Feedback multiplier */
-#define PLL_FBKDIV		0x00F00000
-#define CPC0_PLLMR1_FBDV	0x00F00000
-#define PLL_FBKDIV_16		0x00000000
-#define PLL_FBKDIV_1		0x00100000
-#define PLL_FBKDIV_2		0x00200000
-#define PLL_FBKDIV_3		0x00300000
-#define PLL_FBKDIV_4		0x00400000
-#define PLL_FBKDIV_5		0x00500000
-#define PLL_FBKDIV_6		0x00600000
-#define PLL_FBKDIV_7		0x00700000
-#define PLL_FBKDIV_8		0x00800000
-#define PLL_FBKDIV_9		0x00900000
-#define PLL_FBKDIV_10		0x00A00000
-#define PLL_FBKDIV_11		0x00B00000
-#define PLL_FBKDIV_12		0x00C00000
-#define PLL_FBKDIV_13		0x00D00000
-#define PLL_FBKDIV_14		0x00E00000
-#define PLL_FBKDIV_15		0x00F00000
-    /* Forward A divisor */
-#define PLL_FWDDIVA		0x00070000
-#define CPC0_PLLMR1_FWDVA	0x00070000
-#define PLL_FWDDIVA_8		0x00000000
-#define PLL_FWDDIVA_7		0x00010000
-#define PLL_FWDDIVA_6		0x00020000
-#define PLL_FWDDIVA_5		0x00030000
-#define PLL_FWDDIVA_4		0x00040000
-#define PLL_FWDDIVA_3		0x00050000
-#define PLL_FWDDIVA_2		0x00060000
-#define PLL_FWDDIVA_1		0x00070000
-    /* Forward B divisor */
-#define PLL_FWDDIVB		0x00007000
-#define CPC0_PLLMR1_FWDVB	0x00007000
-#define PLL_FWDDIVB_8		0x00000000
-#define PLL_FWDDIVB_7		0x00001000
-#define PLL_FWDDIVB_6		0x00002000
-#define PLL_FWDDIVB_5		0x00003000
-#define PLL_FWDDIVB_4		0x00004000
-#define PLL_FWDDIVB_3		0x00005000
-#define PLL_FWDDIVB_2		0x00006000
-#define PLL_FWDDIVB_1		0x00007000
-    /* PLL tune bits */
-#define PLL_TUNE_MASK		0x000003FF
-#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
-#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
-#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
-#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
-#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
-#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
-#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
-
-/* Defines for CPC0_PLLMR0 Register fields */
-    /* CPU divisor */
-#define PLL_CPUDIV		0x00300000
-#define CPC0_PLLMR0_CCDV	0x00300000
-#define PLL_CPUDIV_1		0x00000000
-#define PLL_CPUDIV_2		0x00100000
-#define PLL_CPUDIV_3		0x00200000
-#define PLL_CPUDIV_4		0x00300000
-    /* PLB divisor */
-#define PLL_PLBDIV		0x00030000
-#define CPC0_PLLMR0_CBDV	0x00030000
-#define PLL_PLBDIV_1		0x00000000
-#define PLL_PLBDIV_2		0x00010000
-#define PLL_PLBDIV_3		0x00020000
-#define PLL_PLBDIV_4		0x00030000
-    /* OPB divisor */
-#define PLL_OPBDIV		0x00003000
-#define CPC0_PLLMR0_OPDV	0x00003000
-#define PLL_OPBDIV_1		0x00000000
-#define PLL_OPBDIV_2		0x00001000
-#define PLL_OPBDIV_3		0x00002000
-#define PLL_OPBDIV_4		0x00003000
-    /* EBC divisor */
-#define PLL_EXTBUSDIV		0x00000300
-#define CPC0_PLLMR0_EPDV	0x00000300
-#define PLL_EXTBUSDIV_2		0x00000000
-#define PLL_EXTBUSDIV_3		0x00000100
-#define PLL_EXTBUSDIV_4		0x00000200
-#define PLL_EXTBUSDIV_5		0x00000300
-    /* MAL divisor */
-#define PLL_MALDIV		0x00000030
-#define CPC0_PLLMR0_MPDV	0x00000030
-#define PLL_MALDIV_1		0x00000000
-#define PLL_MALDIV_2		0x00000010
-#define PLL_MALDIV_3		0x00000020
-#define PLL_MALDIV_4		0x00000030
-    /* PCI divisor */
-#define PLL_PCIDIV		0x00000003
-#define CPC0_PLLMR0_PPFD	0x00000003
-#define PLL_PCIDIV_1		0x00000000
-#define PLL_PCIDIV_2		0x00000001
-#define PLL_PCIDIV_3		0x00000002
-#define PLL_PCIDIV_4		0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
-				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CFG_OPB_FREQ	55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CFG_OPB_FREQ	66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CFG_OPB_FREQ	66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x00400000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
-*/
-
-/* 256 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
-					"1792k(user),256k(u-boot);" \
-				"ppchameleonevb-nand:-(nand)"
-*/
-
-/* 320 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
-					"1728k(user),320k(u-boot);" \
-				"ppchameleonevb-nand:-(nand)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
deleted file mode 100644
index 967582b45e..0000000000
--- a/include/configs/QS850.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* various debug settings */
-#undef CFG_DEVICE_NULLDEV		/* null device */
-#undef CONFIG_SILENT_CONSOLE		/* silent console */
-#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
-#undef DEBUG				/* debug output code */
-#undef DEBUG_FLASH			/* debug flash code */
-#undef FLASH_DEBUG			/* debug fash code */
-#undef DEBUG_ENV			/* debug environment code */
-
-#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
-#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU */
-#define CONFIG_QS850		1	/* ...on a QS850 module */
-#define CONFIG_SCC2_ENET	1	/* SCC2 10BaseT ethernet */
-
-/* Select the target clock speed */
-#undef CONFIG_CLOCK_16MHZ		/* cpu=16,777,216 Hz, mem=16Mhz */
-#undef CONFIG_CLOCK_33MHZ		/* cpu=33,554,432 Hz, mem=33Mhz */
-#undef CONFIG_CLOCK_50MHZ		/* cpu=49,971,200 Hz, mem=33Mhz */
-#define CONFIG_CLOCK_66MHZ	1	/* cpu=67,108,864 Hz, mem=66Mhz */
-#undef CONFIG_CLOCK_80MHZ		/* cpu=79,986,688 Hz, mem=33Mhz */
-
-#ifdef CONFIG_CLOCK_16MHZ
-#define CONFIG_CLOCK_MULT	512
-#endif
-
-#ifdef CONFIG_CLOCK_33MHZ
-#define CONFIG_CLOCK_MULT	1024
-#endif
-
-#ifdef CONFIG_CLOCK_50MHZ
-#define CONFIG_CLOCK_MULT	1525
-#endif
-
-#ifdef CONFIG_CLOCK_66MHZ
-#define CONFIG_CLOCK_MULT	2048
-#endif
-
-#ifdef CONFIG_CLOCK_80MHZ
-#define CONFIG_CLOCK_MULT	2441
-#endif
-
-/* choose flash size, 4Mb or 8Mb */
-#define CONFIG_FLASH_4MB	1	/* board has 4Mb flash */
-#undef CONFIG_FLASH_8MB			/* board has 8Mb flash */
-
-#define CONFIG_CLOCK_BASE	32768	/* Base clock input freq */
-
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
-
-#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
-
-/* Define default IP addresses */
-#define CONFIG_IPADDR		192.168.1.99	/* own ip address */
-#define CONFIG_SERVERIP		192.168.1.19	/* used for tftp (not nfs?) */
-
-/* message to say directly after booting */
-#define CONFIG_PREBOOT		"echo '';" \
-	"echo 'type:';" \
-	"echo 'run boot_nfs       to boot to NFS';" \
-	"echo 'run boot_flash     to boot to flash';" \
-	"echo '';" \
-	"echo 'run flash_rootfs   to install a new rootfs';" \
-	"echo 'run flash_env      to clear the env sector';" \
-	"echo 'run flash_rw       to clear the rw fs';" \
-	"echo 'run flash_uboot    to install a new u-boot';" \
-	"echo 'run flash_kernel   to install a new kernel';"
-
-/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTCOMMAND	"run boot_nfs"
-
-#undef CONFIG_BOOTARGS		/* made by set_nfs of set_flash */
-
-/* Our flash filesystem looks like this
- *
- * 4Mb board:
- * ffc0 0000 - ffeb ffff	root filesystem (jffs2) (~3Mb)
- * ffec 0000 - ffed ffff	read-write filesystem (ext2)
- * ffee 0000 - ffef ffff	environment
- * fff0 0000 - fff1 ffff	u-boot
- * fff2 0000 - ffff ffff	linux kernel
- *
- * 8Mb board:
- * ff80 0000 - ffeb ffff	root filesystem (jffs2) (~7Mb)
- * ffec 0000 - ffed ffff	read-write filesystem (ext2)
- * ffee 0000 - ffef ffff	environment
- * fff0 0000 - fff1 ffff	u-boot
- * fff2 0000 - ffff ffff	linux kernel
- *
- */
-
-/* environment for 4Mb board */
-#ifdef CONFIG_FLASH_4MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"serial#=QS850\0" \
-	"hostname=qs850\0" \
-	"netdev=eth0\0" \
-	"ethaddr=00:01:02:B4:36:56\0" \
-	"rootpath=/exports/rootfs\0" \
-	"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
-	/* fill in variables */ \
-	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
-	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
-	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
-	/* commands */ \
-	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
-	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
-	/* reinstall flash parts */ \
-	"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
-	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
-	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
-	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
-	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_4MB */
-
-/* environment for 8Mb board */
-#ifdef CONFIG_FLASH_8MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"serial#=QS850\0" \
-	"hostname=qs850\0" \
-	"netdev=eth0\0" \
-	"ethaddr=00:01:02:B4:36:56\0" \
-	"rootpath=/exports/rootfs\0" \
-	"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
-	/* fill in variables */ \
-	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
-	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
-	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
-	/* commands */ \
-	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
-	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
-	/* reinstall flash parts */ \
-	"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
-	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
-	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
-	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
-	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_8MB */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-#undef CONFIG_STATUS_LED		/* Status LED disabled */
-#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
-
-#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
-	CFG_CMD_BOOTD	| \
-	CFG_CMD_CONSOLE	| \
-	CFG_CMD_DATE	| \
-	CFG_CMD_ENV	| \
-	CFG_CMD_FLASH	| \
-	CFG_CMD_IMI	| \
-	CFG_CMD_IMMAP	| \
-	CFG_CMD_MEMORY	| \
-	CFG_CMD_NET	| \
-	CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*-----------------------------------------------------------------------
- * Environment variable storage is in FLASH, one sector before U-boot
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x20000		/* 128Kb, one whole sector */
-#define CFG_ENV_SIZE		0x2000		/* 8kb */
-#define CFG_ENV_ADDR		0xffee0000	/* address of env sector */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-
-#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
-
-#define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
-#define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MONITOR_BASE	0xFFF00000	/* U-boot location */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * TODO flash parameters
- * FLASH organization for Intel Strataflash
- */
-#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-
-#ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- */
-
-/* MF (Multiplication Factor of SPLL) */
-/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
-#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
-#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
-#define CFG_BRGCLK_PRESCALE	1
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
-#endif
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
-#endif
-
-#define SCCR_MASK		CFG_SCCR
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- * 0x73E67C0F - All interrupts handled by BDM
- * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
- *-----------------------------------------------------------------------
-#define CFG_DER			0x73E67C0F
-#define CFG_DER			0x0082400F
-
- #-------------------------------------------------------------------------
- # Program the Debug Enable Register (DER). This register provides the user
- # with the reason for entering into the debug mode. We want all conditions
- # to end up as an exception. We don't want to enter into debug mode for
- # any condition. See the back of of the Development Support section of the
- # MPC860 User Manual for a description of this register.
- #-------------------------------------------------------------------------
-*/
-#define CFG_DER			0
-
-/*-----------------------------------------------------------------------
- * Memory Controller Initialization Constants
- *-----------------------------------------------------------------------
- */
-
-/*
- * BR0 and OR0 (AMD dual FLASH devices)
- * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
- */
-#define CFG_PRELIM_OR_AM
-#define CFG_OR_TIMING_FLASH
-
-/*
- *-----------------------------------------------------------------------
- * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
- *                        flash that resides on the QS850.
- *-----------------------------------------------------------------------
- */
-
-/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
-/*                     represents a minumum 32K block size. */
-#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
-#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)
-
-/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
-/*                                 which defines a 8 Mbyte memory block. */
-#define vOR0_AM			((0xFF80 << 16) + (0 << 15))
-
-#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/*  0101 = Add a 5 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
-/*  0011 = Add a 3 clock cycle wait state */
-/*  29.8ns clock * (3 + 2) = 149ns cycle time */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-/*  0010 = Add a 2 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
-#endif
-
-/*
- * BR1 and OR1 (SDRAM)
- * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
- * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
- * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
- * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
- */
-
-#define SDRAM_BASE		0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-
-/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
- *                                 represents a 128 Mbyte block the DRAM in
- *                                 this address base.
- */
-#define vOR1_AM			((0xF800 << 16) + (0 << 15))
-#define vBR1_BA			((0x0000 << 16) + (0 << 15))
-#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
-#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
-
-/* Machine A Mode Register */
-
-/* PTA Periodic Timer A */
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define vMAMR_PTA		(19 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define vMAMR_PTA		(16 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_50MHZ)
-#define vMAMR_PTA		(195 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ)
-#define vMAMR_PTA		(131 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-#define vMAMR_PTA		(65 << 24)
-#endif
-
-/* For boards with 16M of SDRAM */
-#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* For boards with 32M of SDRAM */
-#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
-#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/* Memory Periodic Timer Prescaler Register */
-
-#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/* Divide by 32 */
-#define CFG_MPTPR		0x02
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-/* Divide by 16 */
-#define CFG_MPTPR		0x04
-#endif
-
-/*
- * BR2 and OR2 (Unused)
- * Base address = 0xF020_0000 - 0xF020_0FFF
- *
- */
-#define CFG_OR2_PRELIM		0xFFF00000
-#define CFG_BR2_PRELIM		0xF0200000
-
-/*
- * BR3 and OR3 (External Bus CS3)
- * Base address = 0xF030_0000 - 0xF030_0FFF
- *
- */
-#define CFG_OR3_PRELIM		0xFFF00000
-#define CFG_BR3_PRELIM		0xF0300000
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF040_0000 - 0xF040_0FFF
- *
- */
-#define CFG_OR4_PRELIM		0xFFF00000
-#define CFG_BR4_PRELIM		0xF0400000
-
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF050_0000 - 0xF050_0FFF
- *
- */
-#define CFG_OR5_PRELIM		0xFFF00000
-#define CFG_BR5_PRELIM		0xF0500000
-
-/*
- * BR6 and OR6 (Unused)
- * Base address = 0xF060_0000 - 0xF060_0FFF
- *
- */
-#define CFG_OR6_PRELIM		0xFFF00000
-#define CFG_BR6_PRELIM		0xF0600000
-
-/*
- * BR7 and OR7 (Unused)
- * Base address = 0xF070_0000 - 0xF070_0FFF
- *
- */
-#define CFG_OR7_PRELIM		0xFFF00000
-#define CFG_BR7_PRELIM		0xF0700000
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot */
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
deleted file mode 100644
index 32faa61607..0000000000
--- a/include/configs/QS860T.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* various debug settings */
-#undef CFG_DEVICE_NULLDEV		/* null device */
-#undef CONFIG_SILENT_CONSOLE		/* silent console */
-#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
-#undef DEBUG				/* debug output code */
-#undef DEBUG_FLASH			/* debug flash code */
-#undef FLASH_DEBUG			/* debug fash code */
-#undef DEBUG_ENV			/* debug environment code */
-
-#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
-#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860 CPU */
-#define CONFIG_QS860T		1	/* ...on a QS860T module */
-
-#define CONFIG_FEC_ENET		1	/* FEC 10/100BaseT ethernet */
-#define CONFIG_MII
-#define FEC_INTERRUPT		SIU_LEVEL1
-#undef CONFIG_SCC1_ENET			/* SCC1 10BaseT ethernet */
-#define CFG_DISCOVER_PHY
-
-#undef CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC */
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-/* Pass clocks to Linux 2.4.18 in Hz */
-#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT		"echo;" \
-	"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
-	"echo"
-
-#undef CONFIG_BOOTARGS
-/* TODO compare against CADM860 */
-#define CONFIG_BOOTCOMMAND	"bootp; " \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-#undef CONFIG_STATUS_LED		/* Status LED disabled */
-
-#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-	CFG_CMD_REGINFO	| \
-	CFG_CMD_IMMAP	| \
-	CFG_CMD_ASKENV	| \
-	CFG_CMD_NET	| \
-	CFG_CMD_DHCP	| \
-	CFG_CMD_DATE	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
-/* TODO */
-#if 0
-/* Look at these */
-CONFIG_IPADDR
-CONFIG_SERVERIP
-CONFIG_I2C
-CONFIG_SPI
-#endif
-
-/*
- * Environment variable storage is in NVRAM
- */
-#define CFG_ENV_IS_IN_NVRAM	1
-#define CFG_ENV_SIZE		0x00001000	/* We use only the last 4K for PPCBoot */
-#define CFG_ENV_ADDR		0xD100E000
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-
-#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-/* TODO - size? */
-#define CFG_MEMTEST_START	0x0400000	/* memtest works */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF00000
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/* TODO flash parameters */
-/*-----------------------------------------------------------------------
- * FLASH organization for Intel Strataflash
- */
-#define CFG_FLASH_16BIT		1		/* 16-bit wide flash memory */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	64		/* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
-
-#undef	CFG_ENV_IS_IN_FLASH
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
-#else
-#define CFG_SYPCR	0xFFFFFF88
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	0x00620000
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- */
-#define CFG_TBSCR	0x00C3
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- */
-#define CFG_PISCR	0x0082
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- */
-#define CFG_PLPRCR	0x0090D000
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	0x02000000
-
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- * 0x73E67C0F - All interrupts handled by BDM
- * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
- *-----------------------------------------------------------------------
-#define CFG_DER			0x73E67C0F
-*/
-#define CFG_DER			0x0082400F
-
-
-/*-----------------------------------------------------------------------
- * Memory Controller Initialization Constants
- *-----------------------------------------------------------------------
- */
-
-/*
- * BR0 and OR0 (AMD 512K Socketed FLASH)
- * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
- */
-#define CFG_PRELIM_OR_AM
-#define CFG_OR_TIMING_FLASH
-
-#define FLASH_BASE0_PRELIM	0xFFF00001
-#define CFG_OR0_PRELIM		0xFFF80D42
-#define CFG_BR0_PRELIM		0xFFF00401
-
-
-/*
- * BR1 and OR1 (Intel 8M StrataFLASH)
- * Base address = 0xD000_0000 - 0xD07F_FFFF
- */
-
-#define FLASH_BASE1_PRELIM	0xD0000000
-#define CFG_OR1_PRELIM		0xFF800D42
-#define CFG_BR1_PRELIM		0xD0000801
-/* #define CFG_OR1		0xFF800D42 */
-/* #define CFG_BR1		0xD0000801 */
-
-
-/*
- * BR2 and OR2 (SDRAM)
- * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
- * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
- * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
- *
- */
-#define SDRAM_BASE		0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-
-/* SDRAM timing */
-#define SDRAM_TIMING		0x00000A00
-
-/* For boards with 16M of SDRAM */
-#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */
-
-/* For boards with 64M of SDRAM */
-#define SDRAM_64M_MAX_SIZE	0x04000000	/* max 64MB SDRAM */
-/* TODO - determine real value */
-#define CFG_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */
-
-#define CFG_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
-#define CFG_BR2			(SDRAM_BASE | 0x000000C1)
-
-
-/*
- * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
- * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
- * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
- * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
- * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
- *
- */
-
-#define CFG_OR3_PRELIM		0xFFC00DF6
-#define CFG_BR3_PRELIM		0xD1000401
-/* #define CFG_OR3		0xFFC00DF6 */
-/* #define CFG_BR3		0xD1000401 */
-
-
-/*
- * BR4 and OR4 (Unused)
- * Base address = 0xE000_0000 - 0xE3FF_FFFF
- *
- */
-
-#define CFG_OR4_PRELIM		0xFF000000
-#define CFG_BR4_PRELIM		0xE0000000
-/* #define CFG_OR4		0xFF000000 */
-/* #define CFG_BR4		0xE0000000 */
-
-
-/*
- * BR5 and OR5 (Expansion bus)
- * Base address = 0xE400_0000 - 0xE7FF_FFFF
- *
- */
-
-#define CFG_OR5_PRELIM		0xFF000000
-#define CFG_BR5_PRELIM		0xE4000000
-/* #define CFG_OR5		0xFF000000 */
-/* #define CFG_BR5		0xE4000000 */
-
-
-/*
- * BR6 and OR6 (Expansion bus)
- * Base address = 0xE800_0000 - 0xEBFF_FFFF
- *
- */
-
-#define CFG_OR6_PRELIM		0xFF000000
-#define CFG_BR6_PRELIM		0xE8000000
-/* #define CFG_OR6		0xFF000000 */
-/* #define CFG_BR6		0xE8000000 */
-
-
-/*
- * BR7 and OR7 (Expansion bus)
- * Base address = 0xEC00_0000 - 0xEFFF_FFFF
- *
- */
-
-#define CFG_OR7_PRELIM		0xFF000000
-#define CFG_BR7_PRELIM		0xE8000000
-/* #define CFG_OR7		0xFF000000 */
-/* #define CFG_BR7		0xE8000000 */
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot */
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
deleted file mode 100644
index 82228c0126..0000000000
--- a/include/configs/R360MPI.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_R360MPI		1
-
-#define CONFIG_LCD
-#undef  CONFIG_EDT32F10
-#define CONFIG_SHARP_LQ057Q3DC02
-
-#define	CONFIG_SPLASH_SCREEN
-
-#define MPC8XX_FACT             1		/* Multiply by 1	*/
-#define MPC8XX_XIN              50000000	/* 50 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
-#if 0
-#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#undef	CONFIG_SCC1_ENET
-#define	CONFIG_SCC2_ENET
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
-#undef CONFIG_SORT_I2C			/* To I2C with software support */
-#define CFG_I2C_SPEED		4700	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL			0x00000020	/* PB 26 */
-#define PB_SDA			0x00000010	/* PB 27 */
-
-#define I2C_INIT		(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE		(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ		((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-				else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY		udelay(50)
-
-#define CFG_I2C_LCD_ADDR	0x8	/* LCD Control */
-#define CFG_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
-#define CFG_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCMCIA	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_DEVICE_NULLDEV	1	/* we need the null device	*/
-#define CFG_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
-
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition
- * use all the space starting at offset 3MB*/
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00300000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=r360-0"
-#define MTDPARTS_DEFAULT	"mtdparts=r360-0:-@3m(user)"
-*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
-#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#if 1
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-#define CFG_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
-				 OR_SCY_0_CLK | OR_G5LS)
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3 and OR3 (CAN Controller)
- */
-#ifdef CONFIG_CAN_DRIVER
-#define CFG_CAN_BASE		0xC0000000	/* CAN base address   */
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA |OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
-				 BR_PS_8 | BR_MS_UPMB | BR_V)
-#endif	/* CONFIG_CAN_DRIVER */
-
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
- */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
deleted file mode 100644
index 242c837a3b..0000000000
--- a/include/configs/RBC823.h
+++ /dev/null
@@ -1,439 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Udi Finkelstein udif@udif.com
- * For the RBC823 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/
-
-
-#if 0
-#define DEBUG			1
-#define CONFIG_LAST_STAGE_INIT
-#endif
-#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
-#define CONFIG_LCD		1	/* use LCD controller ...	*/
-#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */
-
-#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_SMC1
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-#if 1
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ    48000000L
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#undef CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
-
-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 40000
-#define CFG_I2C_SLAVE 0xfe
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_WRITE_BITS		4
-#define CFG_EEPROM_WRITE_DELAY_MS	10
-
-#define CONFIG_COMMANDS	      ( CFG_CMD_ALL	& \
-				~CFG_CMD_BSP	& \
-				~CFG_CMD_DATE	& \
-				~CFG_CMD_DISPLAY& \
-				~CFG_CMD_DTT	& \
-				~CFG_CMD_EXT2	& \
-				~CFG_CMD_FDC	& \
-				~CFG_CMD_FDOS	& \
-				~CFG_CMD_HWFLOW	& \
-				~CFG_CMD_IDE	& \
-				~CFG_CMD_IRQ	& \
-				~CFG_CMD_JFFS2	& \
-				~CFG_CMD_MII	& \
-				~CFG_CMD_MMC	& \
-				~CFG_CMD_NAND	& \
-				~CFG_CMD_PCI	& \
-				~CFG_CMD_PCMCIA	& \
-				~CFG_CMD_REISER	& \
-				~CFG_CMD_SCSI	& \
-				~CFG_CMD_SETGETDCR & \
-				~CFG_CMD_SNTP	& \
-				~CFG_CMD_SPI	& \
-				~CFG_CMD_UNIVERSE & \
-				~CFG_CMD_USB	& \
-				~CFG_CMD_VFD	& \
-				~CFG_CMD_XIMG	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x0100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF00000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-/*
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-*/
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-/*
- * for 48 MHz, we use a 4 MHz clock * 12
- */
-#define CFG_PLPRCR							\
-		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
-		         SCCR_PRQEN   | SCCR_EBDF00   | \
-		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
-			 SCCR_DFALCD00)
-
-#ifdef NOT_USED
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-#endif
-
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
-
-#define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
-		          BR_PS_8 | BR_V)
-
-/*
- * BR4 and OR4 (SDRAM)
- *
- */
-#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/*
- * SDRAM timing:
- */
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM)
-
-#define CFG_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
-#define CFG_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	187		/* start with divider for 48 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
deleted file mode 100644
index 591382cd24..0000000000
--- a/include/configs/RPXClassic.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define	RPXClassic_50MHz
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860           1
-#define CONFIG_RPXCLASSIC		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
-
-/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1   */
-#define CONFIG_FEC_ENET
-#ifdef CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY        1
-#define CONFIG_MII              1
-#endif /* CONFIG_FEC_ENET */
-
-/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard         */
-#if 1
-#define CONFIG_VIDEO_SED13806
-#define CONFIG_NEC_NL6448BC20
-#define CONFIG_VIDEO_SED13806_16BPP
-
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK 1
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-
-#define CONFIG_COMMANDS	((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_RESET_ADDRESS	0x80000000
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFA200000
-
-/*-----------------------------------------------------------------------------
- * I2C Configuration
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_I2C              1
-#define CFG_I2C_SPEED           50000
-#define CFG_I2C_SLAVE           0x34
-
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	1		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00000010)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00000010)
-#define I2C_READ	((iop->pdat & 0x00000010) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000010; \
-			else    iop->pdat &= ~0x00000010
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000020; \
-			else    iop->pdat &= ~0x00000020
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0x34
-# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE	0xFF000000
-
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	0xFF000000
-/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#if 0
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x20000	/*   Offset   of Environment Sector  */
-#define CFG_ENV_SECT_SIZE       0x8000
-#define	CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector  */
-#else
-#define CFG_ENV_IS_IN_NVRAM     1
-#define CFG_ENV_ADDR            0xfa000100
-#define CFG_ENV_SIZE            0x1000
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/* #define	CFG_DER	0x2002000F */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
-
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xff7f8970
-#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFF80970
-
-/* ECCX CS settings                                                          */
-#define SED13806_OR             0xFFC00108     /* - 4 Mo
-						   - Burst inhibit
-						   - external TA             */
-#define SED13806_REG_ADDR       0xa0000000
-#define SED13806_ACCES          0x801           /* 16 bit access             */
-
-
-/* Global definitions for the ECCX board                                     */
-#define ECCX_CSR_ADDR           (0xfac00000)
-#define ECCX_CSR8_OFFSET        (0x8)
-#define ECCX_CSR11_OFFSET       (0xB)
-#define ECCX_CSR12_OFFSET       (0xC)
-
-#define ECCX_CSR8  (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
-#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
-#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
-
-
-#define REG_GPIO_CTRL 0x008
-
-/* Definitions for CSR8                                                      */
-#define ECCX_ENEPSON            0x80    /* Bit 0:
-					   0= disable and reset SED1386
-					   1= enable SED1386                 */
-/* Bit 1:   0= SED1386 in Big Endian mode                                    */
-/*          1= SED1386 in little endian mode                                 */
-#define ECCX_LE                 0x40
-#define ECCX_BE                 0x00
-
-/* Bit 2,3: Selection                                                        */
-/*      00 = Disabled                                                        */
-/*      01 = CS2 is used for the SED1386                                     */
-/*      10 = CS5 is used for the SED1386                                     */
-/*      11 = reserved                                                        */
-#define ECCX_CS2                0x10
-#define ECCX_CS5                0x20
-
-/* Definitions for CSR12                                                     */
-#define ECCX_ID                 0x02
-#define ECCX_860                0x01
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	58
-
-/*
- * Refresh clock Prescalar
- */
-#define CFG_MPTPR	MPTPR_PTP_DIV8
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
-			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
-#define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
-#define BCSR0_COLTEST	0x20
-#define BCSR0_ETHLPBK	0x40
-#define BCSR0_ETHEN	0x80
-
-#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
-#define BCSR1_PCVCTL6	0x02
-#define BCSR1_PCVCTL5	0x04
-#define BCSR1_PCVCTL4	0x08
-#define BCSR1_IPB5SEL	0x10
-
-#define BCSR2_MIIRST    0x80
-#define BCSR2_MIIPWRDWN 0x40
-#define BCSR2_MIICTL    0x08
-
-#define BCSR3_BWRTC		0x01	/* Real Time Clock Battery */
-#define BCSR3_BWNVR		0x02	/* NVRAM Battery */
-#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
-#define BCSR3_RPXL		0x08	/* Reserved (reads back '1') */
-#define BCSR3_D27		0x10	/* Dip Switch settings */
-#define BCSR3_D26		0x20
-#define BCSR3_D25		0x40
-#define BCSR3_D24		0x80
-
-
-/*
- * Environment setting
- */
-
-/* #define CONFIG_ETHADDR	00:10:EC:00:2C:A2 */
-/* #define CONFIG_IPADDR	10.10.106.1 */
-/* #define CONFIG_SERVERIP	10.10.104.11 */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
deleted file mode 100644
index 48ada0ed9b..0000000000
--- a/include/configs/RPXlite.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define	RPXLite_50MHz
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#undef CONFIG_MPC860
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_RPXLITE		1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_RESET_ADDRESS	0x09900000
-
-#define	CFG_LOAD_ADDR		0x400000	/* default load address	*/
-
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
-#else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
-#endif /* CONFIG_BZIP2 */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_DIRECT_FLASH_TFTP
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x40000 	/* We use one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
-
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0970
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	58
-
-/*
- * Refresh clock Prescalar
- */
-#define CFG_MPTPR	MPTPR_PTP_DIV8
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
-			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
-#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
-#define BCSR0_COLTEST	0x20
-#define BCSR0_ETHLPBK	0x40
-#define BCSR0_ETHEN	0x80
-
-#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
-#define BCSR1_PCVCTL6	0x02
-#define BCSR1_PCVCTL5	0x04
-#define BCSR1_PCVCTL4	0x08
-#define BCSR1_IPB5SEL	0x10
-
-#define BCSR2_ENPA5HDR	0x08	/* USB Control */
-#define BCSR2_ENUSBCLK	0x10
-#define BCSR2_USBPWREN	0x20
-#define BCSR2_USBSPD	0x40
-#define BCSR2_USBSUSP	0x80
-
-#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
-#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
-#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
-#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
-#define BCSR3_D27	0x10	/* Dip Switch settings */
-#define BCSR3_D26	0x20
-#define BCSR3_D25	0x40
-#define BCSR3_D24	0x80
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
deleted file mode 100644
index 31025473f4..0000000000
--- a/include/configs/RPXlite_DW.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-BOOT port on RPXlite board
- */
-
-/*
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- * U-BOOT port on RPXlite DW version board--RPXlite_DW
- * June 8 ,2004
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* #define DEBUG	1 */
-/* #define DEPLOYMENT	1 */
-
-#undef	CONFIG_MPC860
-#define CONFIG_MPC823		1	/* This is a MPC823e CPU. */
-#define CONFIG_RPXLITE		1	/* RPXlite DW version board */
-
-#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
-#define CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
-#endif
-
-#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console default baudrate = 9600bps	*/
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	6	/* autoboot after 6 seconds	*/
-
-#ifdef DEPLOYMENT
-#define CONFIG_BOOT_RETRY_TIME		-1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds (stop with 'st')...\n"
-#define CONFIG_AUTOBOOT_STOP_STR	"st"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1
-#define CONFIG_BOOT_RETRY_MIN		1
-#endif	/* DEPLOYMENT */
-#endif	/* DEBUG */
-
-/* pre-boot commands */
-#define CONFIG_PREBOOT		"setenv stdout serial;setenv stdin serial"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 "	\
-		"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
-	"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0"	\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"gatewayip=172.16.115.254\0"					\
-	"netmask=255.255.255.0\0"					\
-	"kernel_addr=ff040000\0"					\
-	"ramdisk_addr=ff200000\0"					\
-	"ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} "	\
-		"${filesize};md ${kernel_addr};"			\
-		"echo kernel updating finished\0"			\
-	"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 "		\
-		"${filesize};md ff000000;"				\
-		"echo u-boot updating finished\0"			\
-	"eu=protect off 1:6;era 1:6;reset\0"				\
-	"lcd=setenv stdout lcd;setenv stdin lcd\0"			\
-	"ser=setenv stdout serial;setenv stdin serial\0"		\
-	"verify=no"
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_STATUS_LED		/* disturbs display. Status LED disabled. */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#if 1	       /* Enable this stuff could make image enlarge about 25KB. Mask it if you
-		  don't want the advanced function */
-
-#ifdef	CONFIG_SPLASH_SCREEN
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_DHCP	)
-#else
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_DHCP	)
-#endif	/* CONFIG_SPLASH_SCREEN */
-
-/* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-
-#define CONFIG_NETCONSOLE
-
-#endif	/* 1 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"u-boot>"	/* Monitor Command Prompt   */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
-
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor */
-#endif
-
-#define CFG_MONITOR_BASE	0xFF000000
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#ifdef	CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_ADDR		0xFA000100
-#define CFG_ENV_SIZE		0x1000
-#else
-#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x30000 /* Offset of Environment Sector		*/
-#define CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
-#endif	/* CFG_ENV_IS_IN_NVRAM */
-
-#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control	32-bit			12-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif	/* We can get SYPCR: 0xFFFF0689. */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration	32-bit			 12-30
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)	       /* SIUMCR:0x00000800 */
-
-/*---------------------------------------------------------------------
- * TBSCR - Time Base Status and Control	 16-bit			 12-16
- *---------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-/* TBSCR: 0x00C3 [SAM] */
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 16-bit	 12-18
- *-----------------------------------------------------------------------
- * [RTC enabled but not stopped on FRZ]
- */
-#define CFG_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1	*/
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 16-bit		 12-23
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * [Periodic timer enabled,Periodic timer interrupt disable. ]
- */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083		*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	32-bit	 5-7
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-/* up to 64 MHz we use a 1:2 clock */
-#if defined(RPXlite_64MHz)
-#define CFG_PLPRCR	( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
-#else
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-#endif
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		5-3
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
-#if defined(RPXlite_64MHz)
-#define CFG_SCCR	( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
-#else
-#define CFG_SCCR	( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-#define		CFG_DER		0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base	*/
-#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB in system */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
-#define CFG_OR_AM_SDRAM		(-(SDRAM_MAX_SIZE & OR_AM_MSK))
-#define CFG_OR1_PRELIM	( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXlite mem setting */
-#define CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xFF7F8900
-#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0040
-
-/*
- * Memory Periodic Timer Prescaler
- */
-/* periodic timer for refresh */
-#if defined(RPXlite_64MHz)
-#define CFG_MAMR_PTA	32
-#else
-#define CFG_MAMR_PTA	20
-#endif
-
-/*
- * Refresh clock Prescalar
- */
-#define CFG_MPTPR	MPTPR_PTP_DIV2
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
-			MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
-/* CFG_MAMR_9COL:0x20904000 @ 64MHz */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
-#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
-#define BCSR0_COLTEST	0x20
-#define BCSR0_ETHLPBK	0x40
-#define BCSR0_ETHEN	0x80
-
-#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
-#define BCSR1_PCVCTL6	0x02
-#define BCSR1_PCVCTL5	0x04
-#define BCSR1_PCVCTL4	0x08
-#define BCSR1_IPB5SEL	0x10
-
-#define BCSR1_SMC1CTS	0x40	/* Added by SAM. */
-#define BCSR1_SMC1TRS	0x80	/* Added by SAM. */
-
-#define BCSR2_ENRTCIRQ	0x01	/* Added by SAM. */
-#define BCSR2_ENBRG1	0x04	/* Added by SAM. */
-
-#define BCSR2_ENPA5HDR	0x08	/* USB Control */
-#define BCSR2_ENUSBCLK	0x10
-#define BCSR2_USBPWREN	0x20
-#define BCSR2_USBSPD	0x40
-#define BCSR2_USBSUSP	0x80
-
-#define BCSR3_BWKAPWR	0x01   /* Changed by SAM. Backup battery situation */
-#define BCSR3_IRQRTC	0x02   /* Changed by SAM. NVRAM Battery */
-#define BCSR3_RDY_BSY	0x04   /* Changed by SAM. Flash Operation */
-#define BCSR3_MPLX_LIN	0x08   /* Changed by SAM. Linear or Multiplexed address Mode */
-
-#define BCSR3_D27	0x10	  /* Dip Switch settings */
-#define BCSR3_D26	0x20
-#define BCSR3_D25	0x40
-#define BCSR3_D24	0x80
-
-/*
- * Environment setting
- */
-#define CONFIG_ETHADDR	00:10:EC:00:37:5B
-#define CONFIG_IPADDR	172.16.115.7
-#define CONFIG_SERVERIP 172.16.115.6
-#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
-#define CONFIG_BOOTFILE uImage.rpxusb
-#define CONFIG_HOSTNAME LITE_H1_DW
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
deleted file mode 100644
index 45907aa0e7..0000000000
--- a/include/configs/RPXsuper.h
+++ /dev/null
@@ -1,503 +0,0 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-/* for the AY-Revision which does not use the HRCW */
-#define CFG_DEFAULT_IMMR	0x00010000
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
-
-/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
- * only the 3 least significant bits are important.
-*/
-#define CFG_SBC_S2  0x04
-
-/* What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]  Osc    CPM    Core
- * 0x2       0x2         33     133    133
- * 0x2       0x4         33     133    200
- * 0x5       0x5         66     133    133
- * 0x5       0x7         66     133    200
- */
-#define CFG_SBC_MODCK_H 0x06
-
-#define CFG_SBC_BOOT_LOW 1	/* only for HRCW */
-#undef CFG_SBC_BOOT_LOW
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CFG_FLASH0_BASE 0x80000000
-#define CFG_FLASH0_SIZE 16
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
- * want it enabled, don't define these constants.
- */
-#define CFG_FLASH1_BASE 0
-#define CFG_FLASH1_SIZE 0
-#undef CFG_FLASH1_BASE
-#undef CFG_FLASH1_SIZE
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM1_BASE 0x04000000
-#define CFG_SDRAM1_SIZE 32
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CFG_LED_BASE 0x00000000
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
-#undef  CONFIG_CONS_NONE            /* define if console on neither */
-#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
-#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
-#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
-
-#if ( CONFIG_ETHER_INDEX == 3 )
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Half Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-/*#define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
-# define CFG_FCC_PSMR		0
-
-#else /* CONFIG_ETHER_INDEX */
-# error "on RPX Super ethernet must be FCC3"
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_HARD_I2C         1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE         115200
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR          08:00:22:50:70:63
-
-#define CONFIG_IPADDR		192.168.1.99
-#define CONFIG_SERVERIP         192.168.1.3
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY        -1
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt       */
-#define CFG_PROMPT              "=> "
-
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS         ( CONFIG_CMD_DFL | \
-				  CFG_CMD_IMMAP  | \
-				  CFG_CMD_ASKENV | \
-				  CFG_CMD_I2C    | \
-				  CFG_CMD_REGINFO & \
-				 ~CFG_CMD_KGDB )
-
-/* Where do the internal registers live? */
-#define CFG_IMMR               0xF0000000
-
-/* Where do the on board registers (CS4) live? */
-#define CFG_REGS_BASE          0xFA000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
-#define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
-#else
-#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS       8            /* max number of command args   */
-
-#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
-#define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CFG_LOAD_ADDR     0x100000     /* default load address */
-#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE    CFG_FLASH0_BASE
-#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_IMMR & 0x00100000) >> 4) )
-
-#define CFG_HRCW_MASTER (HRCW_BPS11                           |\
-			 HRCW_DPPC11                          |\
-			 CFG_SBC_HRCW_IMMR                    |\
-			 HRCW_MMR00                           |\
-			 HRCW_LBPC11                          |\
-			 HRCW_APPC10                          |\
-			 HRCW_CS10PC00                        |\
-			 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
-			 CFG_SBC_HRCW_BOOT_FLAGS)
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR       CFG_IMMR
-#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE        (CFG_FLASH0_BASE + 0x00F00000)
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
-#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
-
-#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH  1
-
-#  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE  0x40000
-#  else
-#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
-#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
-#  endif /* CFG_ENV_IN_OWN_SECT */
-#else
-#  define CFG_ENV_IS_IN_NVRAM  1
-#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE         0x200
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (/*HID0_ICE  |*/\
-			 /*HID0_DCE  |*/\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR         0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR         (BCR_EBM   |\
-			 BCR_PLDP  |\
-			 BCR_EAV   |\
-			 BCR_NPQM0)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
-			 SIUMCR_APPC10  |\
-			 SIUMCR_CS10PC01)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                            11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CFG_SYPCR       (SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR        (SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90)
- *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
- *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
- *  3   unused
- *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches
- *  5   unused
- *  6   unused
- *  7   unused
- *  8   PCMCIA
- *  9   unused
- * 10   unused
- * 11   unused
-*/
-
-/* Bank 0 - FLASH
- *
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64                      |\
-			 BRx_DECC_NONE                  |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_6_CLK                 |\
-			 ORxG_EHTR)
-
-/* Bank 1 - SDRAM
- *
- */
-#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A8             |\
-			 ORxS_NUMR_12                   |\
-			 ORxS_IBID)
-
-#define CFG_PSDMR       0x014DA412
-#define CFG_PSRT	0x79
-
-
-/* Bank 2 - SDRAM
- *
- */
-#define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A9             |\
-			 ORxS_NUMR_12)
-
-#define CFG_LSDMR       0x0169A512
-#define CFG_LSRT	0x79
-
-#define CFG_MPTPR	(0x0800 & MPTPR_PTP_MSK)
-
-/* Bank 4 - On board registers
- *
- */
-#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-			   BRx_PS_8                     |\
-			   BRx_MS_GPCM_P                |\
-			   BRx_V)
-
-#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
-			   ORxG_CSNT                   |\
-			   ORxG_ACS_DIV1               |\
-			   ORxG_SCY_5_CLK              |\
-			   ORxG_TRLX)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM   0x02    /* Software reboot                   */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
deleted file mode 100644
index 3885bcdb1e..0000000000
--- a/include/configs/RRvision.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_RRVISION		1	/* ...on a RRvision board	*/
-
-#define CONFIG_8xx_GCLK_FREQ 64000000
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"setenv stdout serial"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_ETHADDR                00:50:C2:00:E0:70
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#define CONFIG_IPADDR                 10.0.0.5
-#define CONFIG_SERVERIP               10.0.0.2
-#define CONFIG_NETMASK                255.0.0.0
-#define CONFIG_ROOTPATH               /opt/eldk/ppc_8xx
-#define CONFIG_BOOTCOMMAND            "run flash_self"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}"	\
-		":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0"	\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
-	"update=protect off 1:0-8;era 1:0-8;"				\
-		"cp.b 100000 40000000 ${filesize};"			\
-		"setenv filesize;saveenv\0"				\
-	"kernel_addr=40040000\0"					\
-	"ramdisk_addr=40100000\0"					\
-	"kernel_img=/tftpboot/uImage\0"					\
-	"kernel_load=tftp 200000 ${kernel_img}\0"			\
-	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
-	"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0"	\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"
-
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef	CONFIG_STATUS_LED		/* disturbs display		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-
-#ifndef CONFIG_LCD
-#define CONFIG_VIDEO		1	/* To enable the video initialization */
-
-/* Video related */
-#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
-#define CONFIG_VIDEO_ENCODER_AD7179		1	/* Enable this encoder */
-#define CONFIG_VIDEO_ENCODER_AD7179_ADDR	0x2A	/* ALSB to ground */
-#endif
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C         	/* I2C bit-banged		*/
-
-# define CFG_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
-# define CFG_I2C_SLAVE		0xFE
-
-#ifdef CONFIG_SOFT_I2C
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
-#endif	/* CONFIG_SOFT_I2C */
-
-
-#define CONFIG_COMMANDS	    ( ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_DATE	) & \
-			     ~( CFG_CMD_PCMCIA  | \
-			        CFG_CMD_IDE	) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks = ms */
-#define CFG_FLASH_ERASE_TOUT	(120*CFG_HZ)	/* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(1 * CFG_HZ)	/* Timeout for Flash Write	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-
-/* for 64 MHz, we use a 16 MHz clock * 4 */
-#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/*
- * FLASH timing:
- */
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
-					BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#define CFG_MAMR_PTA		129
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
- */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
deleted file mode 100644
index e263db65a2..0000000000
--- a/include/configs/SCM.h
+++ /dev/null
@@ -1,711 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
-#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
-#define CONFIG_SCM              1	/* ...on a System Controller Module	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#if (CONFIG_TQM8260 <= 100)
-#  error "TQM8260 module revison not supported"
-#endif
-
-/* We use a TQM8260 module with a 300MHz CPU */
-#define CONFIG_300MHz
-
-/* Define 60x busmode only if your TQM8260 has L2 cache! */
-#ifdef CONFIG_L2_CACHE
-#  define CONFIG_BUSMODE_60x	1	/* bus mode: 60x			*/
-#else
-#  undef  CONFIG_BUSMODE_60x		/* bus mode: 8260			*/
-#endif
-
-/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
-#ifdef CONFIG_300MHz
-#  define CONFIG_BUSMODE_60x
-#endif
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK12
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE 	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifndef CONFIG_300MHz
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	83333000	/* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_DHCP	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_EEPROM	| \
-				 CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START 0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address		*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
-
-#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH0_SIZE 32
-#define CFG_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
-#define CFG_ENV_SIZE		0x40000
-#define CFG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#if defined(CONFIG_266MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-							      HRCW_MODCK_H0111)
-#elif defined(CONFIG_300MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-							      HRCW_MODCK_H0110)
-#else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#ifdef	CONFIG_BUSMODE_60x
-#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
-			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
-#else
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR        0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CFG_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
-
-#define CFG_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CFG_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-	/* SDRAM on TQM8260 can have either 8 or 9 columns.
-	 * The number affects configuration values.
-	 */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
-
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CFG_INIT_LOCAL_SDRAM
-#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	CFG_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM	0x80000000
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A8             |\
-			 ORxS_NUMR_12)
-
-#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_13)
-
-#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-#endif /* CFG_INIT_LOCAL_SDRAM */
-
-#endif /* CFG_RAMBOOT */
-
-#define CFG_CAN0_BASE		0xc0000000
-#define CFG_CAN1_BASE		0xc0008000
-#define CFG_FIOX_BASE		0xc0010000
-#define CFG_FDOHM_BASE		0xc0018000
-#define CFG_EXTPROM_BASE	0xc2000000
-
-#define CFG_CAN_SIZE		0x00000100
-#define CFG_FIOX_SIZE		0x00000020
-#define CFG_FDOHM_SIZE		0x00002000
-#define CFG_EXTPROM_BANK_SIZE	0x01000000
-
-#define EXT_EEPROM_MAX_FLASH_BANKS	0x02
-
-/* CS3 - CAN 0
- */
-#define CFG_CAN0_BR3   ((CFG_CAN0_BASE & BRx_BA_MSK)	|\
-			BRx_PS_8			|\
-			BRx_MS_UPMA			|\
-			BRx_V)
-
-#define CFG_CAN0_OR3   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
-			ORxU_BI				|\
-			ORxU_EHTR_4IDLE)
-
-/* CS4 - CAN 1
- */
-#define CFG_CAN1_BR4   ((CFG_CAN1_BASE & BRx_BA_MSK)	|\
-			BRx_PS_8			|\
-			BRx_MS_UPMA			|\
-			BRx_V)
-
-#define CFG_CAN1_OR4   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
-			ORxU_BI				|\
-			ORxU_EHTR_4IDLE)
-
-/* CS5 - Extended PROM (16MB optional)
- */
-#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
-			ORxG_CSNT			|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS6 - Extended PROM (16MB optional)
- */
-#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
-			CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
-			ORxG_CSNT			|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS7 - FPGA FIOX: Glue Logic
- */
-#define CFG_FIOX_BR7   ((CFG_FIOX_BASE & BRx_BA_MSK)	|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CFG_FIOX_OR7   (P2SZ_TO_AM(CFG_FIOX_SIZE)	|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS8 - FPGA DOH Master
- */
-#define CFG_FDOHM_BR8  ((CFG_FDOHM_BASE & BRx_BA_MSK)	|\
-			BRx_PS_16			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CFG_FDOHM_OR8  (P2SZ_TO_AM(CFG_FDOHM_SIZE)	|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-
-/* FPGA configuration */
-#define CFG_PD_FIOX_PROG	(1 << (31- 5))	/* PD  5 */
-#define CFG_PD_FIOX_DONE	(1 << (31-28))	/* PD 28 */
-#define CFG_PD_FIOX_INIT	(1 << (31-29))	/* PD 29 */
-
-#define CFG_PD_FDOHM_PROG	(1 << (31- 4))	/* PD  4 */
-#define CFG_PD_FDOHM_DONE	(1 << (31-26))	/* PD 26 */
-#define CFG_PD_FDOHM_INIT	(1 << (31-27))	/* PD 27 */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
deleted file mode 100644
index 61896d0d7d..0000000000
--- a/include/configs/SL8245.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * (C) Copyright 2001 - 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-/*
- * Configuration settings for the SL8245 board.
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_SL8245		1
-
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_BOOTDELAY	5
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_PCI)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
-
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	32		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    	0x00000000
-
-#define CFG_FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE 		CFG_FLASH_BASE0_PRELIM
-#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM }
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256 MB of (S)DRAM */
-
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		get_bus_freq(0)
-
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  66666666	/* external frequency to pll */
-#define CFG_HZ		     1000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
-#define CFG_BANK0_ROW       2
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    192
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval */
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval */
-#define CFG_ACTORW	    3       /* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8245 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8245 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8245 book for details		*/
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors per flash	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	    1
-#define CFG_ENV_ADDR		0xFFFF0000
-#define CFG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
-#define CFG_ENV_SECT_SIZE	0x00010000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#undef  CONFIG_PCI_SCAN_SHOW
-
-
-#define CONFIG_SK98
-#define CONFIG_NET_MULTI
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
deleted file mode 100644
index f4339ecd9c..0000000000
--- a/include/configs/Sandpoint8240.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8240		1
-#define CONFIG_SANDPOINT	1
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"net_self=tftp ${kernel_addr} ${bootfile};"			\
-		"tftp ${ramdisk_addr} ${ramdisk};"			\
-		"run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
-		"run nfsargs addip;bootm\0"				\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/SP8240/uImage\0"				\
-	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
-	"kernel_addr=200000\0"						\
-	"ramdisk_addr=400000\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-#endif
-
-#define CFG_FLASH_BASE		0xFFF00000
-#if 0
-#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
-#else
-#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
-#endif
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CFG_EUMB_ADDR		0xFC000000
-
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
-
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
-#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly.  Please review!"
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
-
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
-
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
-
-#define CFG_NS87308_BADDR_10	1
-
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
-
-#undef  CFG_NS87308_PS2MOD
-
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		1843200
-
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
-
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
-
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
deleted file mode 100644
index d42bd69231..0000000000
--- a/include/configs/Sandpoint8245.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_SANDPOINT	1
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#undef CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_NATSEMI
-#define CONFIG_NS8382X
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-#endif
-
-#define CFG_FLASH_BASE		0xFFF00000
-#if 0
-#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
-#else
-#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
-#endif
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CFG_EUMB_ADDR		0xFC000000
-
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
-
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
-#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly.  Please review!"
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
-
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
-
-#define CFG_NS87308_BADDR_10	1
-
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
-
-#undef  CFG_NS87308_PS2MOD
-
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CFG_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
-#else
-#define CFG_NS16550_CLK         1843200
-#endif
-
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
-
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
-#endif
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
deleted file mode 100644
index 119bc2442b..0000000000
--- a/include/configs/TASREG.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Configuation settings for the esd TASREG board.
- *
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _TASREG_H
-#define _TASREG_H
-
-#ifndef __ASSEMBLY__
-#include <asm/m5249.h>
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5249			/* define processor type */
-
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
-
-#define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#undef  CONFIG_WATCHDOG
-
-#undef CONFIG_MONITOR_IS_IN_RAM	              /* no pre-loader required!!! ;-) */
-
-#define CONFIG_COMMANDS	      ((CONFIG_CMD_DFL        |    \
-				CFG_CMD_BSP           |    \
-				CFG_CMD_EEPROM        |    \
-				CFG_CMD_I2C            ) & \
-			       ~(CFG_CMD_NET))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CONFIG_BOOTDELAY	3
-
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-
-#define CFG_LOAD_ADDR	        0x200000	/* default load address */
-
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-
-#define CFG_HZ			1000
-
-/*
- * Clock configuration: enable only one of the following options
- */
-
-#if 0 /* this setting will run the cpu at 11MHz */
-#define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
-#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
-#define CFG_CLK		        11289600         /* PLL bypass                  */
-#endif
-
-#if 0 /* this setting will run the cpu at 70MHz */
-#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
-#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
-#define CFG_CLK		        72185018         /* The next lower speed        */
-#endif
-
-#if 1 /* this setting will run the cpu at 140MHz */
-#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
-#define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
-#define	CFG_CLK		        132025600        /* MCF5249 can run at 140MHz   */
-#endif
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define	CFG_MBAR2	        0x80000000
-
-/*-----------------------------------------------------------------------
- * I2C
- */
-#define	CONFIG_SOFT_I2C
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last 5 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#if defined (CONFIG_SOFT_I2C)
-#if 0 /* push-pull */
-#define	SDA	        0x00800000
-#define	SCL	        0x00000008
-#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
-#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
-#define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
-#define	I2C_READ	((IN1&SDA)?1:0)
-#define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
-#define	I2C_SCL(x)	{if(x)OUT0|=SCL;else OUT0&=~SCL;}
-#define	I2C_DELAY	{udelay(5);}
-#define	I2C_ACTIVE	{DIR1|=SDA;}
-#define	I2C_TRISTATE    {DIR1&=~SDA;}
-#else /* open-collector */
-#define	SDA	        0x00800000
-#define	SCL	        0x00000008
-#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
-#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
-#define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
-#define	I2C_READ	((IN1&SDA)?1:0)
-#define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
-#define	I2C_SCL(x)	{if(x)DIR0&=~SCL;else DIR0|=SCL;}
-#define	I2C_DELAY	{udelay(5);}
-#define	I2C_ACTIVE	{DIR1|=SDA;}
-#define	I2C_TRISTATE    {DIR1&=~SDA;}
-#endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
-#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffc00000
-
-#if 0 /* test-only */
-#define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
-#endif
-
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
-#define CFG_BOOTPARAMS_LEN	64*1024
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-
-/* CS0 - AMD Flash, address 0xffc00000 */
-#define	CFG_CSAR0               0xffc0
-#define	CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
-/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
-
-/* CS1 - FPGA, address 0xe0000000 */
-#define	CFG_CSAR1               0xe000
-#define	CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
-#define	CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
-
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-#define	CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
-#define	CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
-#define	CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
-#define	CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
-#define	CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
-#define	CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
-
-#define CFG_GPIO1_LED           0x00400000      /* user led                     */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
-
-#endif	/* _TASREG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
deleted file mode 100644
index 08674ca49f..0000000000
--- a/include/configs/TQM5200.h
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
-#define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
-#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
-
-/* On a Cameron or on a FO300 board or ...				*/
-#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
-#define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
-#endif
-
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_FO300
-#define CFG_DEVICE_NULLDEV		1	/* enable null device */
-#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
-#define CONFIG_BOARD_EARLY_INIT_F	1	/* used to detect S1 switch position */
-#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
-#if 0
-#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
-							/* switch is closed */
-#endif
-
-#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED		/* silent console on PSC1 when S1 */
-							/* switch is open */
-#endif	/* CONFIG_FO300 */
-
-#ifdef CONFIG_STK52XX
-#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
-#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
-#define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_STK52XX */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#ifdef CONFIG_STK52XX
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_NET_MULTI	1
-#define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-#endif	/* CONFIG_STK52XX */
-
-#ifdef CONFIG_PCI
-#define ADD_PCI_CMD		CFG_CMD_PCI
-#else
-#define ADD_PCI_CMD		0
-#endif
-
-/*
- * Video console
- */
-#ifndef CONFIG_TQM5200S		/* No graphics controller on TQM5200S */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-
-#ifndef CONFIG_FO300
-#define CONFIG_CONSOLE_EXTRA_INFO
-#else
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
-#endif /* #ifndef CONFIG_TQM5200S */
-
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD		CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD		0
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD		0
-#endif
-
-#ifndef CONFIG_CAM5200
-/* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
-#endif
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
-
-/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
-#else
-#define ADD_IDE_CMD		0
-#endif
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				ADD_BMP_CMD	| \
-				ADD_IDE_CMD	| \
-				ADD_PCI_CMD	| \
-				ADD_USB_CMD	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_POST_DIAG | \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_SNTP	| \
-				CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define	CONFIG_TIMESTAMP		/* display image timestamps */
-
-#if (TEXT_BASE != 0xFFF00000)
-#   define CFG_LOWBOOT		1	/* Boot low */
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
-# define ENV_UPDT							\
-	"update=protect off FFF00000 +${filesize};"			\
-		"erase FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 +${filesize}\0"
-#else	/* default lowboot configuration */
-#   define ENV_UPDT							\
-	"update=protect off FC000000 +${filesize};"			\
-		"erase FC000000 +${filesize};"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 +${filesize}\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate}\0"				\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
-		"bootm\0"						\
-	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
-	"load=tftp 200000 ${u-boot}\0"					\
-	ENV_UPDT							\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
-
-#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#ifdef CONFIG_TQM5200_REV100
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
-#else
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
-#endif
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-
-/*
- * HW-Monitor configuration on Mini-FAP
- */
-#if defined (CONFIG_MINIFAP)
-#define CFG_I2C_HWMON_ADDR		0x2C
-#endif
-
-/* List of I2C addresses to be verified by POST */
-#if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
-				CFG_I2C_HWMON_ADDR,	\
-				CFG_I2C_SLAVE }
-#endif
-
-/*
- * Flash configuration
- */
-#define CFG_FLASH_BASE		0xFC000000
-
-#ifndef CONFIG_CAM5200
-/* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#else /* CONFIG_CAM5200 */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
-					   (= chip selects) */
-#define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CFG_FLASH_ADDR0		0x555
-#define CFG_FLASH_ADDR1		0x2AA
-#define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
-#define CFG_MAX_FLASH_SECT	128
-#endif /* ifndef CONFIG_CAM5200 */
-
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-
-#if defined (CONFIG_CAM5200)
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
-#elif defined(CONFIG_TQM5200_B)
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00080000)
-#else
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif
-
-/* Dynamic MTD partition support */
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
-
-#ifdef CONFIG_STK52XX
-# if defined(CONFIG_TQM5200_B)
-#  if defined(CFG_LOWBOOT)
-#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:1m(firmware),"	\
-						"1536k(kernel),"	\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#  else	/* highboot */
-#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:2560k(kernel),"	\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"15m(big-fs),"		\
-						"1m(firmware)"
-#  endif /* CFG_LOWBOOT */
-# else	/* !CONFIG_TQM5200_B */
-#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
-#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
-						"1792k(kernel),"	\
-						"5632k(rootfs),"	\
-						"24m(home)"
-#elif defined (CONFIG_FO300)
-#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#else
-# error "Unknown Carrier Board"
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
-#define CFG_ENV_SECT_SIZE	0x40000
-#else
-#define CFG_ENV_SECT_SIZE	0x20000
-#endif /* CONFIG_TQM5200_B */
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#if defined (CONFIG_CAM5200)
-# define CFG_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#elif defined(CONFIG_TQM5200_B)
-# define CFG_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#else
-# define CFG_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#endif
-
-#define CFG_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- *
- * use CS1: Bit 0 (mask: 0x80000000):
- *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
- *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *		Use for REV200 STK52XX boards and FO300 boards. Do not use
- *		with REV100 modules (because, there I2C1 is used as I2C bus).
- * use ATA: Bits 6-7 (mask 0x03000000):
- *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
- *		Use for CAM5200 board.
- *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
- * use PSC6: Bits 9-11 (mask 0x00700000):
- *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
- *		UART, CODEC or IrDA.
- *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
- *		enable extended POST tests.
- *		Use for MINI-FAP and TQM5200_IB boards.
- *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
- *		Extended POST test is not available.
- *		Use for STK52xx, FO300 and CAM5200 boards.
- * use PCI_DIS: Bit 16 (mask 0x00008000):
- *	   1 -> disable PCI controller (on CAM5200 board).
- * use USB: Bits 18-19 (mask 0x00003000):
- *	  10 -> two UARTs (on FO300 and CAM5200).
- * use PSC3: Bits 20-23 (mask: 0x00000f00):
- *	0000 -> All PSC3 pins are GPIOs.
- *	1100 -> UART/SPI (on FO300 board).
- *	0100 -> UART (on CAM5200 board).
- * use PSC2: Bits 25:27 (mask: 0x00000030):
- *	 000 -> All PSC2 pins are GPIOs.
- *	 100 -> UART (on CAM5200 board).
- *	 001 -> CAN1/2 on PSC2 pins.
- *	        Use for REV100 STK52xx boards
- *	 01x -> Use AC97 (on FO300 board).
- * use PSC1: Bits 29-31 (mask: 0x00000007):
- *	 100 -> UART (on all boards).
- */
-#if defined (CONFIG_MINIFAP)
-# define CFG_GPS_PORT_CONFIG	0x91000004
-#elif defined (CONFIG_STK52XX)
-# if defined (CONFIG_STK52XX_REV100)
-#  define CFG_GPS_PORT_CONFIG	0x81500014
-# else /* STK52xx REV200 and above */
-#  if defined (CONFIG_TQM5200_REV100)
-#   error TQM5200 REV100 not supported on STK52XX REV200 or above
-#  else/* TQM5200 REV200 and above */
-#   define CFG_GPS_PORT_CONFIG	0x91500004
-#  endif
-# endif
-#elif defined (CONFIG_FO300)
-# define CFG_GPS_PORT_CONFIG	0x91502c24
-#elif defined (CONFIG_CAM5200)
-# define CFG_GPS_PORT_CONFIG	0x8050A444
-#else  /* TMQ5200 Inbetriebnahme-Board */
-# define CFG_GPS_PORT_CONFIG	0x81000004
-#endif
-
-/*
- * RTC configuration
- */
-#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
-# define CONFIG_RTC_M41T11 1
-# define CFG_I2C_RTC_ADDR 0x68
-# define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
-					   year */
-#else
-# define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#define	CFG_PROMPT_HUSH_PS2	"> "
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
-#else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CFG_CS2_START		0xE5000000
-#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
-#define CFG_CS2_CFG		0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE		0xE0000000
-#define CFG_CS1_START		(SM501_FB_BASE)
-#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CFG_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
-
-#if defined(CONFIG_CAM5200)
-#define CFG_CS4_START		0xB0000000
-#define CFG_CS4_SIZE		0x00010000
-#define CFG_CS4_CFG		0x01019C10
-
-#define CFG_CS5_START		0xD0000000
-#define CFG_CS5_SIZE		0x01208000
-#define CFG_CS5_CFG		0x1414BF10
-#endif
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
deleted file mode 100644
index ffd5c0b95c..0000000000
--- a/include/configs/TQM8260.h
+++ /dev/null
@@ -1,646 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Imported from global configuration:
- *	CONFIG_MPC8255
- *	CONFIG_MPC8265
- *	CONFIG_200MHz
- *	CONFIG_266MHz
- *	CONFIG_300MHz
- *	CONFIG_L2_CACHE
- *	CONFIG_BUSMODE_60x
- */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
-
-#if 0
-#define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
-#else
-#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
-#endif
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/TQM8260/uImage\0"				\
-	"kernel_addr=40040000\0"					\
-	"ramdisk_addr=40100000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
-#if (CONFIG_TQM8260 <= 100)
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
-#define I2C_READ	((iop->pdat & 0x00020000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#else
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif
-
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else	/* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
-# ifndef CONFIG_300MHz
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-# else
-#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH0_SIZE 32
-#define CFG_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
-#define CFG_ENV_SIZE		0x40000
-#define CFG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else	/* ! MPC8255 && !MPC8265 */
-# if defined(CONFIG_266MHz)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-# elif defined(CONFIG_300MHz)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
-# else
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__)
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#ifdef	CONFIG_BUSMODE_60x
-#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
-			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
-#else
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR        0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CFG_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
-
-#define CFG_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CFG_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-	/* SDRAM on TQM8260 can have either 8 or 9 columns.
-	 * The number affects configuration values.
-	 */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
-
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CFG_INIT_LOCAL_SDRAM
-#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	CFG_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM	0x80000000
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A8             |\
-			 ORxS_NUMR_12)
-
-#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_13)
-
-#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-#endif /* CFG_INIT_LOCAL_SDRAM */
-
-#endif /* CFG_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
deleted file mode 100644
index 5f48a70938..0000000000
--- a/include/configs/VCMA9.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2002, 2003
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the MPL VCMA9 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
-#define CONFIG_VCMA9		1	/* on a MPL VCMA9 Board  */
-#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000/* VCMA9 has 12MHz input clock	*/
-
-#define USE_920T_MMU		1
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs    	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
-			(CONFIG_CMD_DFL	 | \
-			CFG_CMD_CACHE	 | \
-			/*CFG_CMD_JFFS2	 |*/ \
-			/*CFG_CMD_NAND	 |*/ \
-			CFG_CMD_EEPROM	 | \
-			CFG_CMD_I2C	 | \
-			CFG_CMD_USB	 | \
-			CFG_CMD_REGINFO  | \
-			CFG_CMD_FAT	 | \
-			CFG_CMD_DATE	 | \
-			CFG_CMD_ELF	 | \
-			CFG_CMD_DHCP	 | \
-			CFG_CMD_PING	 | \
-			CFG_CMD_BSP)
-
-/* this must be included after the definiton of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-/***********************************************************
- * I2C stuff:
- * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
- * address 0x50 with 16bit addressing
- ***********************************************************/
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED 		100000	/* I2C speed */
-#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
-
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN	2
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at offset 0 */
-#define CFG_ENV_SIZE		0x800	/* 2KB should be more than enough */
-
-#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
-#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* 64 bytes page write mode on 24C256 */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * Size of malloc() pool
- */
-/*#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)*/
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
-
-#define CFG_MONITOR_LEN		(256 * 1024)
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000300
-#define CS8900_BUS16		1 		/* the Linux driver does accesses as shorts */
-
-#define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on VCMA9 */
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_USB_OHCI		1
-#define CONFIG_USB_KEYBOARD	1
-#define CONFIG_USB_STORAGE	1
-#define CONFIG_DOS_PARTITION	1
-
-/* Enable needed helper functions */
-#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
-
-/************************************************************
- * RTC
- ************************************************************/
-#define	CONFIG_RTC_S3C24X0	1
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTDELAY	5
-/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
-
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		10.0.0.110
-#define CONFIG_SERVERIP		10.0.0.1
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"VCMA9 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
-
-#define CFG_ALT_MEMTEST
-#define	CFG_LOAD_ADDR		0x30800000	/* default load address	*/
-
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-/* we configure PWM Timer 4 to 1us ~ 1MHz */
-/*#define	CFG_HZ			1000000 */
-#define	CFG_HZ			1562500
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/* support BZIP2 compression */
-#define CONFIG_BZIP2		1
-
-/************************************************************
- * Ident
- ************************************************************/
-/*#define VERSION_TAG "released"*/
-#define VERSION_TAG "unstable"
-#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-#endif
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
-
-#if 0
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-#endif
-
-
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-
-#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
-#define CFG_NAND_LEGACY
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define NAND_WAIT_READY(nand)	NF_WaitRB()
-
-#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
-
-
-#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
-#define WRITE_NAND(d, adr)		NF_Write(d)
-#define READ_NAND(adr)			NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_MTD_NAND_ECC_JFFS2	1
-
-#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
deleted file mode 100644
index 96f3d26cc5..0000000000
--- a/include/configs/VOH405.h
+++ /dev/null
@@ -1,459 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_VOH405		1	/* ...on a VOH405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
-
-#define CFG_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_ATAPI		1	/* ATAPI for Travelstar		*/
-
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_IDE1_OFFSET	0x0010
-
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#if 0 /* test-only */
-/* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
-					/* 32 byte page write mode using*/
-					/* last 5 bits of the address	*/
-#endif
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
-#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
-#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (Epson VGA) initialization					*/
-#define CFG_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
-#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
-#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
-#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
-
-#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
-
-/* FPGA internal regs */
-#define CFG_FPGA_CTRL		0x000
-
-/* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET	0x0001
-#define CFG_FPGA_CTRL_WDI	0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555440
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0017
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
-#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
-#define CFG_LCD0_RST		(0x80000000 >> 30)
-#define CFG_LCD1_RST		(0x80000000 >> 31)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
deleted file mode 100644
index f2f3ea7cc4..0000000000
--- a/include/configs/VOM405.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_NET_MULTI	1
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-#undef  CONFIG_PRAM			/* no "protected RAM"           */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
deleted file mode 100644
index 92bade5187..0000000000
--- a/include/configs/VoVPN-GW.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * (C) Copyright 2004
- * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
- *
- * Support for the Elmeg VoVPN Gateway Module
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* define cpu used */
-#define	CONFIG_MPC8272			1
-
-/* define busmode: 8260 */
-#undef	CONFIG_BUSMODE_60x
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef	CONFIG_CLKIN_66MHz
-#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
-#else
-#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
-#endif
-
-/* call board_early_init_f */
-#define	CONFIG_BOARD_EARLY_INIT_F	1
-
-/* have misc_init_r() function */
-#define CONFIG_MISC_INIT_R		1
-
-/* have reset_phy_r() function */
-#define CONFIG_RESET_PHY_R		1
-
-/* have special reset function */
-#define	CONFIG_HAVE_OWN_RESET		1
-
-/* allow serial and ethaddr to be overwritten */
-#define	CONFIG_ENV_OVERWRITE
-
-/* watchdog disabled */
-#undef	CONFIG_WATCHDOG
-
-/* include support for bzip2 compressed images */
-#undef	CONFIG_BZIP2
-
-/* status led */
-#undef	CONFIG_STATUS_LED		/* XXX jse */
-
-/* vendor parameter protection */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define	CONFIG_CONS_ON_SMC
-#undef	CONFIG_CONS_ON_SCC
-#undef	CONFIG_CONS_NONE
-#define	CONFIG_CONS_INDEX		1
-
-/* serial port default baudrate */
-#define CONFIG_BAUDRATE			115200
-
-/* echo on for serial download	*/
-#define CONFIG_LOADS_ECHO		1
-
-/* don't allow baudrate change	*/
-#undef	CFG_LOADS_BAUD_CHANGE
-
-/* supported baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC
-#define	CONFIG_ETHER_ON_FCC
-#undef	CONFIG_ETHER_NONE
-
-#ifdef	CONFIG_ETHER_ON_FCC
-
-/* which SCC/FCC channel for ethernet */
-#define	CONFIG_ETHER_INDEX		1
-
-/* Marvell Switch SMI base addr */
-#define CFG_PHY_ADDR			0x10
-
-/* FCC1 RMII REFCLK is CLK10 */
-#define CFG_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
-#define CFG_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
-
-/* BDs and buffers on 60x bus */
-#define CFG_CPMFCR_RAMTYPE		0
-
-/* Local Protect, Full duplex, Flowcontrol, RMII */
-#define CFG_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
-					 FCC_PSMR_FCE|FCC_PSMR_RMII)
-
-/* bit-bang MII PHY management	*/
-#define CONFIG_BITBANGMII
-
-#define MDIO_PORT			1		/* Port B */
-#define CFG_MDIO_PIN			0x00002000	/* PB18 */
-#define CFG_MDC_PIN			0x00001000	/* PB19 */
-#define MDIO_ACTIVE			(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE			(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ			((iop->pdat &  CFG_MDIO_PIN) != 0)
-#define MDIO(bit)			if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-					else	iop->pdat &= ~CFG_MDIO_PIN
-#define MDC(bit)			if(bit) iop->pdat |=  CFG_MDC_PIN; \
-					else	iop->pdat &= ~CFG_MDC_PIN
-#define MIIDELAY			udelay(1)
-
-#endif
-
-/* configure commands */
-#define CONFIG_COMMANDS		(	CFG_CMD_AUTOSCRIPT	| \
-					CFG_CMD_BDI		| \
-					CFG_CMD_CONSOLE		| \
-					CFG_CMD_ECHO		| \
-					CFG_CMD_ENV		| \
-					CFG_CMD_FLASH		| \
-					CFG_CMD_IMI		| \
-					CFG_CMD_IMLS		| \
-					CFG_CMD_LOADB		| \
-					CFG_CMD_MEMORY		| \
-					CFG_CMD_MISC		| \
-					CFG_CMD_NET		| \
-					CFG_CMD_PING		| \
-					CFG_CMD_RUN	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * boot options & environment
- */
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_BOOTCOMMAND		"run flash_self"
-#undef  CONFIG_BOOTARGS
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-"clean_nv=erase fff20000 ffffffff\0" \
-"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
-"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
-"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
-"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
-"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
-"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
-"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
-"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
-"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
-"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
-"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
-"fstype=cramfs\0" \
-"rootpath=/root_fs\0" \
-"uboot=PPC/u-boot.bin\0" \
-"kernel=PPC/uImage\0" \
-"kernel_addr=ffe00000\0" \
-"fs=PPC/root_fs\0" \
-"console=ttyS0\0" \
-"netdev=eth0\0" \
-"rootdev=31:3\0" \
-"ethaddr=00:09:4f:01:02:03\0" \
-"ipaddr=10.0.0.201\0" \
-"netmask=255.255.255.0\0" \
-"serverip=10.0.0.136\0" \
-"gatewayip=10.0.0.10\0" \
-"hostname=bastard\0" \
-""
-
-
-/*
- * miscellaneous configurable options
- */
-
-/* undef to save memory */
-#define	CFG_LONGHELP
-
-/* monitor command prompt */
-#define	CFG_PROMPT			"=> "
-
-/* console i/o buffer size */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE			1024
-#else
-#define	CFG_CBSIZE			256
-#endif
-
-/* print buffer size */
-#define	CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-/* max number of command args */
-#define	CFG_MAXARGS			16
-
-/* boot argument buffer size */
-#define CFG_BARGSIZE			CFG_CBSIZE
-
-/* memtest works on */
-#define CFG_MEMTEST_START		0x00100000
-/* 1 ... 15 MB in DRAM */
-#define CFG_MEMTEST_END			0x00f00000
-/* full featured memtest */
-#define CFG_ALT_MEMTEST
-
-/* default load address */
-#define	CFG_LOAD_ADDR			0x00100000
-
-/* decrementer freq: 1 ms ticks	*/
-#define	CFG_HZ				1000
-
-/* configure flash */
-#define CFG_FLASH_BASE			0xff800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		64
-#define CFG_FLASH_SIZE			8
-#undef	CFG_FLASH_16BIT
-#define CFG_FLASH_ERASE_TOUT		240000
-#define CFG_FLASH_WRITE_TOUT		500
-#define CFG_FLASH_LOCK_TOUT		500
-#define CFG_FLASH_UNLOCK_TOUT		10000
-#define CFG_FLASH_PROTECTION
-
-/* monitor in flash */
-#define CFG_MONITOR_OFFSET		0x00700000
-
-/* environment in flash */
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_ADDR			(CFG_FLASH_BASE + 0x00020000)
-#define CFG_ENV_SIZE			0x00020000
-#define CFG_ENV_SECT_SIZE		0x00020000
-
-/*
- * Initial memory map for linux
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ			(8 << 20)
-
-/* hard reset configuration words */
-#ifdef	CONFIG_CLKIN_66MHz
-#define CFG_HRCW_MASTER			0x04643050
-#else
-#error NO HRCW FOR 100MHZ SPECIFIED !!!
-#endif
-#define CFG_HRCW_SLAVE1			0x00000000
-#define CFG_HRCW_SLAVE2			0x00000000
-#define CFG_HRCW_SLAVE3			0x00000000
-#define CFG_HRCW_SLAVE4			0x00000000
-#define CFG_HRCW_SLAVE5			0x00000000
-#define CFG_HRCW_SLAVE6			0x00000000
-#define CFG_HRCW_SLAVE7			0x00000000
-
-/* internal memory mapped register */
-#define CFG_IMMR			0xF0000000
-
-/* definitions for initial stack pointer and data area (in DPRAM) */
-#define CFG_INIT_RAM_ADDR		CFG_IMMR
-#define CFG_INIT_RAM_END		0x2000
-#define CFG_GBL_DATA_SIZE		128
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE			0x00000000
-#define CFG_SDRAM_SIZE			(32*1024*1024)
-#define CFG_MONITOR_BASE		TEXT_BASE
-#define CFG_MONITOR_FLASH		(CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
-#define CFG_MONITOR_LEN			0x00020000
-#define CFG_MALLOC_LEN			0x00020000
-
-/* boot flags */
-#define BOOTFLAG_COLD			0x01	/* normal power-on */
-#define BOOTFLAG_WARM			0x02	/* software reboot */
-
-/* cache configuration */
-#define CFG_CACHELINE_SIZE		32      /* for MPC8260 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT		5	/* log base 2 of above */
-#endif
-
-/*
- * HIDx - Hardware Implementation-dependent Registers
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT			(HID0_ICE|HID0_DCE|\
-					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL			(HID0_IFEM|HID0_ABE)
-#define CFG_HID2			0
-
-/* RMR - reset mode register - turn on checkstop reset enable */
-#define CFG_RMR				RMR_CSRE
-
-/* BCR - bus configuration */
-#define CFG_BCR				0x00000000
-
-/* SIUMCR - siu module configuration */
-#define CFG_SIUMCR			0x4905c000
-
-/* SYPCR - system protection control */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR			0xffffff87
-#else
-#define CFG_SYPCR			0xffffff83
-#endif
-
-/* TMCNTSC - time counter status and control */
-/* clear interrupts XXX jse */
-/*#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
-#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
-					 TMCNTSC_TCF|TMCNTSC_TCE)
-
-/* PISCR - periodic interrupt status and control */
-/* clear interrupts XXX jse */
-/*#define CFG_PISCR			(PISCR_PS) */
-#define CFG_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/* SCCR - system clock control */
-#define CFG_SCCR			0x000001a9
-
-/* RCCR - risc controller configuration */
-#define CFG_RCCR			0
-
-/*
- * MEMORY MAP
- * ----------
- * CS0 - FLASH    8MB/8Bit 	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
- * CS1 - SDRAM   32MB/64Bit	base=0x00000000
- * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
- * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
- * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
- * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
- * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
- *  x  - IMMR     384KB		base=0xf0000000
- */
-/* XXX jse 100MHz TODO */
-#define CFG_BR0_PRELIM			0xff800801
-#define CFG_OR0_PRELIM			0xff801e44
-#define CFG_BR1_PRELIM			0x00000041
-#define CFG_OR1_PRELIM			0xfe002ec0
-#if 1
-#define CFG_BR2_PRELIM			0xf0101001
-#define CFG_OR2_PRELIM			0xfff00ef4
-#define CFG_BR3_PRELIM			0xf0201001
-#define CFG_OR3_PRELIM			0xfff00ef4
-#define CFG_BR4_PRELIM			0xf0301001
-#define CFG_OR4_PRELIM			0xfff00ef4
-#define CFG_BR5_PRELIM			0xf0401001
-#define CFG_OR5_PRELIM			0xfff00ef4
-#else
-#define CFG_BR2_PRELIM			0xf0101081
-#define CFG_OR2_PRELIM			0xfff00104
-#define CFG_BR3_PRELIM			0xf0201081
-#define CFG_OR3_PRELIM			0xfff00104
-#define CFG_BR4_PRELIM			0xf0301081
-#define CFG_OR4_PRELIM			0xfff00104
-#define CFG_BR5_PRELIM			0xf0401081
-#define CFG_OR5_PRELIM			0xfff00104
-#endif
-#define CFG_BR7_PRELIM			0xf0500881
-#define CFG_OR7_PRELIM			0xffff8104
-#define CFG_MPTPR			0x2700
-#define CFG_PSDMR			0x822a2452	/* optimal */
-/*#define CFG_PSDMR			0x822a48a3 */	/* relaxed */
-#define CFG_PSRT			0x1a
-
-/* "bad" address */
-#define	CFG_RESET_ADDRESS		0x40000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
deleted file mode 100644
index 8dc623ea06..0000000000
--- a/include/configs/W7OLMC.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
-#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
-#define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
-#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR		F0080000
-
-#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR		192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.168.1.2
-
-#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
-#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
-
-#define CONFIG_MII		1		/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0		/* PHY address			*/
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-#define CONFIG_COMMANDS		\
-	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
-	 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
-	 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
-#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
-
-#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
-#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
-#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
-#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		384000
-
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	{9600}
-
-#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE		1		/* configure as pci host	*/
-#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
-
-
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
-/* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
-#undef CONFIG_USE_PERWE
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB0AP   0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_W7O_EBC_PB0CR   0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB1AP   0x05850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CFG_EBC_PB1CR   0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB2AP   0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB2CR   0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CFG_EBC_PB3AP   0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB3CR   0xFD01A000
-
-/* bank 4 is FPGA 1 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB4AP   0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB4CR   0xFD11A000
-
-/* bank 5 is FPGA 2 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB5AP   0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB5CR   0xFD21A000
-
-/* bank 6 is unused */
-/* pb6ap = 0 */
-#define CFG_EBC_PB6AP   0x00000000
-/* pb6cr = 0 */
-#define CFG_EBC_PB6CR   0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB7AP   0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CFG_W7O_EBC_PB7CR   0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
-#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
-#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-/*define CFG_ENV_ADDR		 \
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env  */
-#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
-
-#define CFG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
-#define CFG_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192		/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32		/* ...		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above val. */
-#endif
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
-#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
-#define CONFIG_NUM_FPGAS	3		/* Number of FPGAs on board	*/
-#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
-#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
-#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
deleted file mode 100644
index 2bd98b3af3..0000000000
--- a/include/configs/W7OLMG.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
-#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
-#define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
-#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR		F0080000
-
-#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR		192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.168.1.2
-
-#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
-#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
-
-#define CONFIG_MII		1		/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0		/* PHY address			*/
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-#define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
-
-#define CONFIG_COMMANDS		\
-	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
-	 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
-	 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
-	 CFG_CMD_DTT)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
-#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
-
-#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
-#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
-#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
-#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		384000
-
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	{9600}
-
-#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE		1		/* configure as pci host	*/
-#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
-/* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* use PerWE instead of PCI_INT ( these functions share a pin ) */
-#define CONFIG_USE_PERWE 1
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB0AP   0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_W7O_EBC_PB0CR   0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB1AP   0x04850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CFG_EBC_PB1CR   0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB2AP   0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB2CR   0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CFG_EBC_PB3AP   0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB3CR   0xFD01A000
-
-/* bank 4 is SAM 8 bit range */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB4AP   0x02840380
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB4CR   0xFE878000
-
-/* bank 5 is SAM 16 bit range */
-/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
-#define CFG_EBC_PB5AP   0x05040d80
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB5CR   0xFD87A000
-
-/* bank 6 is unused */
-/* pb6ap = 0 */
-#define CFG_EBC_PB6AP   0x00000000
-/* pb6cr = 0 */
-#define CFG_EBC_PB6CR   0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB7AP   0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CFG_W7O_EBC_PB7CR   0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
-#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
-#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-/*define CFG_ENV_ADDR		 \
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env  */
-#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
-
-#define CFG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (ATMEL 24C04N)
- */
-#define CONFIG_HARD_I2C		1		/* Hardware assisted I2C	*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM ATMEL 24C04N		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192		/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32		/* ...		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above val. */
-#endif
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
-#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
-#define CONFIG_NUM_FPGAS	1		/* Number of FPGAs on board	*/
-#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
-#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
-#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
deleted file mode 100644
index faf855d249..0000000000
--- a/include/configs/WUH405.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IDENT_STRING     " $Name:  $"
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_WUH405		1	/* ...on a WUH405 board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#undef  CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
-#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
-#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
-#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define CFG_NAND_BASE	0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
deleted file mode 100644
index 9b32514867..0000000000
--- a/include/configs/XPEDITE1K.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * config for XPedite1000 from XES Inc.
- * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
- * (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_XPEDITE1K	1		/* Board is XPedite 1000 */
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
-#define CONFIG_440		1
-#define CONFIG_440GX		1		/* 440 GX */
-#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST				/* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
-
-
-/* POST support */
-#define CONFIG_POST		(CFG_POST_RTC	   | \
-				 CFG_POST_I2C)
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xfff80000		/* start of FLASH	*/
-
-#define CFG_MONITOR_BASE    CFG_FLASH_BASE	/* start of monitor	*/
-#define CFG_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
-#define CFG_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
-#define CFG_PCI_BASE	    0xd0000000		/* internal PCI regs	*/
-
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_GPIO_BASE	    (CFG_PERIPHERAL_BASE + 0x00000700)
-
-#define USR_LED0	    0x00000080
-#define USR_LED1	    0x00000100
-#define USR_LED2	    0x00000200
-#define USR_LED3	    0x00000400
-
-#ifndef __ASSEMBLY__
-extern unsigned long in32(unsigned int);
-extern void out32(unsigned int, unsigned long);
-
-#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3))
-
-#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3))
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM  1
-#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
-
-
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR  (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET  CFG_POST_WORD_ADDR
-
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_BAUDRATE		9600
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-/* TBS:	 Xpedite 1000 has STMicro M41T00 via IIC */
-#define CONFIG_RTC_M41T11 1
-#define CFG_I2C_RTC_ADDR 0x68
-#define CFG_M41T11_BASE_YEAR 2000
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	8		    /* sectors per device   */
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS {0x54}	/* SPD i2c spd addresses	*/
-#define CONFIG_VERY_BIG_RAM 1
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7f
-#define CFG_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_EEPROM 1
-#define CFG_ENV_SIZE		0x100	    /* Size of Environment vars */
-#define CFG_ENV_OFFSET		0x100
-#define CFG_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTARGS		"root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
-#define CONFIG_BOOTDELAY	5		    /* disable autoboot */
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII			1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address phy0 not populated */
-#define CONFIG_PHY1_ADDR	1	/* PHY address phy1 not populated */
-#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
-#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
-#define CONFIG_NET_MULTI	1
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
-#define CFG_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr"	*/
-#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr"	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_BEDBUG	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_PING | \
-				CFG_CMD_ELF | \
-				CFG_CMD_MII | \
-				CFG_CMD_DIAG | \
-				CFG_CMD_FAT )
-
-/*				CFG_CMD_DHCP	| \ */
-/*				CFG_CMD_KGDB	| \ */
-
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI				    /* include pci support		*/
-#define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
-#define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_FORCE_PCI_CONV          /* Force PCI Conventional Mode */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192 /* For AMCC 440GX CPUs */
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
deleted file mode 100644
index 9a1c5596b7..0000000000
--- a/include/configs/armadillo.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the EP7312 board.
- *
- * Modified to work on Armadillo HT1070 ARM720T board
- * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-/*#define	CONFIG_INIT_CRITICAL*/		/* undef for developing */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
-#define CONFIG_ARMADILLO 	1	/* on an Armadillo Board      */
-#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
-
-#undef CONFIG_USE_IRQ			/* don't need them anymore */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000300 /* armadillo board */
-#define CS8900_BUS16		1
-#undef  CS8900_BUS32
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
-
-#define CONFIG_BOOTCOMMAND	"bootm 40000 180000"
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"ARMADILLO # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
-
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB armadillo SDRAM */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector	*/
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
deleted file mode 100644
index 8fad55d81c..0000000000
--- a/include/configs/at91rm9200dk.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Rick Bronson <rick@efn.org>
- *
- * Configuation settings for the AT91RM9200DK board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
-#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
-/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
-
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
-#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define USE_920T_MMU		1
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
-/* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-
-/* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Hardware drivers
- */
-
-/* define one of these to choose the DBGU, USART0  or USART1 as console */
-#define CONFIG_DBGU
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-
-#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
-
-#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
-
-#define CONFIG_BOOTDELAY      3
-/* #define CONFIG_ENV_OVERWRITE	1 */
-
-#define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL | CFG_CMD_MII |\
-			CFG_CMD_DHCP ) & \
-		      ~(CFG_CMD_BDI | \
-			CFG_CMD_IMI | \
-			CFG_CMD_AUTOSCRIPT | \
-			CFG_CMD_FPGA | \
-			CFG_CMD_MISC | \
-			CFG_CMD_LOADS ))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
-
-#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
-
-#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-/* the following are NOP's in our implementation */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
-
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
-
-#define CONFIG_DRIVER_ETHER
-#define CONFIG_NET_RETRY_COUNT		20
-#define CONFIG_AT91C_USE_RMII
-
-#define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS 	2
-#define CFG_MAX_DATAFLASH_PAGES 	16384
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
-
-#define PHYS_FLASH_1			0x10000000
-#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(2*CFG_HZ) /* Timeout for Flash Write */
-
-#undef	CFG_ENV_IS_IN_DATAFLASH
-
-#ifdef CFG_ENV_IS_IN_DATAFLASH
-#define CFG_ENV_OFFSET			0x20000
-#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
-#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
-#else
-#define CFG_ENV_IS_IN_FLASH		1
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
-#define CFG_ENV_SIZE			0x10000 /* sectors are 64K here */
-#else
-#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
-#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
-#endif	/* CFG_ENV_IS_IN_DATAFLASH */
-
-
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_BOOT_SIZE		0x00 /* 0 KBytes */
-#define CFG_U_BOOT_BASE		PHYS_FLASH_1
-#define CFG_U_BOOT_SIZE		0x60000 /* 384 KBytes */
-#else
-#define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
-#define CFG_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
-#define CFG_U_BOOT_SIZE		0x10000 /* 64 KBytes */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
-
-#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-
-#ifndef __ASSEMBLY__
-/*-----------------------------------------------------------------------
- * Board specific extension for bd_info
- *
- * This structure is embedded in the global bd_info (bd_t) structure
- * and can be used by the board specific code (eg board/...)
- */
-
-struct bd_info_ext {
-	/* helper variable for board environment handling
-	 *
-	 * env_crc_valid == 0    =>   uninitialised
-	 * env_crc_valid  > 0    =>   environment crc in flash is valid
-	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
-	 */
-	int env_crc_valid;
-};
-#endif
-
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
-					/* AT91C_TC_TIMER_DIV1_CLOCK */
-
-#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
-#endif
diff --git a/include/configs/atc.h b/include/configs/atc.h
deleted file mode 100644
index bf6c1709d9..0000000000
--- a/include/configs/atc.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
-#define CONFIG_ATC		1	/* ...on a ATC board	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-
-#define CONFIG_BAUDRATE		115200
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_ON_FCC
-
-#define	CONFIG_NET_MULTI
-#define CONFIG_ETHER_ON_FCC2
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#define CONFIG_ETHER_ON_FCC3
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- * - Enable Half Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	64000000	/* in Hz */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
-
-#define CONFIG_PREBOOT							\
-	"echo;"								\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND						\
-	"bootp;"							\
-	"setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=${serverip}:${rootpath} " 				\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
-	"bootm"
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configuration options
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_PCI | \
-				 CFG_CMD_PCMCIA | \
-				 CFG_CMD_DATE | \
-				 CFG_CMD_IDE)
-
-
-#define CONFIG_DOS_PARTITION
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
-
-#define CFG_ALLOC_DPRAM
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SPI
-
-#define CONFIG_RTC_DS12887
-
-#define RTC_BASE_ADDR 		0xF5000000
-#define RTC_PORT_ADDR 		RTC_BASE_ADDR + 0x800
-#define RTC_PORT_DATA 		RTC_BASE_ADDR + 0x808
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Flash configuration
- */
-
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_FLASH_16BIT
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-				 HRCW_BPS10 |\
-				 HRCW_APPC10)
-
-/* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
-#endif
-
-#define	CONFIG_PCI
-#define	CONFIG_PCI_PNP
-#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
-
-#if 1
-/* environment is in Flash */
-#define CFG_ENV_IS_IN_FLASH	1
-# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)
-# define CFG_ENV_SIZE		0x10000
-# define CFG_ENV_SECT_SIZE	0x10000
-#else
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_ENV_OFFSET		0
-#define CFG_ENV_SIZE		2048
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
-#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
-			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR        SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-#define CFG_MIN_AM_MASK	0xC0000000
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescaler Register              10-18
- *-----------------------------------------------------------------------
- */
-#define CFG_MPTPR       0x1F00
-
-/*-----------------------------------------------------------------------
- * PSRT - Refresh Timer Register                                10-16
- *-----------------------------------------------------------------------
- */
-#define CFG_PSRT        0x0f
-
-/*-----------------------------------------------------------------------
- * PSRT - SDRAM Mode Register                                   10-10
- *-----------------------------------------------------------------------
- */
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI1_A7		|\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_8COL	(PSDMR_PBI			|\
-			 PSDMR_SDAM_A15_IS_A5		|\
-			 PSDMR_BSMA_A15_A17		|\
-			 PSDMR_SDA10_PBI1_A7		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_3W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI1_A6		|\
-			 ORxS_NUMR_12)
-
-#define CFG_PSDMR_9COL	(PSDMR_PBI			|\
-			 PSDMR_SDAM_A16_IS_A5		|\
-			 PSDMR_BSMA_A15_A17		|\
-			 PSDMR_SDA10_PBI1_A6		|\
-			 PSDMR_RFRC_7_CLK		|\
-			 PSDMR_PRETOACT_3W		|\
-			 PSDMR_ACTTORW_2W		|\
-			 PSDMR_LDOTOPRE_1C		|\
-			 PSDMR_WRC_1C			|\
-			 PSDMR_CL_2)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    8  bit  Boot ROM
- *  1   60x     GPCM    64 bit  FLASH
- *  2   60x     SDRAM   64 bit  SDRAM
- *
- */
-
-#define CFG_MRS_OFFS	0x00000000
-
-/* Bank 0 - FLASH
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_16                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxU_EHTR_8IDLE)
-
-
-/* Bank 2 - 60x bus SDRAM
- */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR2_PRELIM	 CFG_OR2_8COL
-
-#define CFG_PSDMR	 CFG_PSDMR_8COL
-#endif /* CFG_RAMBOOT */
-
-#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
-			 BRx_PS_8                       |\
-			 BRx_MS_UPMA                    |\
-			 BRx_V)
-
-#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_I82365
-
-#define CFG_PCMCIA_MEM_ADDR	0x81000000
-#define CFG_PCMCIA_MEM_SIZE	0x1000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	0xa0000000
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0x100
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0x100
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x108
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
deleted file mode 100644
index 4961011b5c..0000000000
--- a/include/configs/bamboo.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- * (C) Copyright 2005-2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * bamboo.h - configuration for BAMBOO board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
-#define CONFIG_440EP		1	/* Specific PPC440EP support    */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
-
-/*
- * Please note that, if NAND support is enabled, the 2nd ethernet port
- * can't be used because of pin multiplexing. So, if you want to use the
- * 2nd ethernet port you have to "undef" the following define.
- */
-#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
-#define CFG_NAND_LEGACY
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
-#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BOOT_BASE_ADDR      0xf0000000
-#define CFG_NAND_ADDR           0x90000000
-#define CFG_NAND2_ADDR          0x94000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
-/* define this if you want console on UART1 */
-#undef CONFIG_UART1_CONSOLE
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
- * The DS1558 code assumes this condition
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
-#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	256		    /* sectors per device   */
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_ADDR0         0x555
-#define CFG_FLASH_ADDR1         0x2aa
-#define CFG_FLASH_WORD_SIZE     unsigned char
-
-#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device      */
-#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH related
- *----------------------------------------------------------------------*/
-#define NAND_CMD_REG   (0x00) /* NandFlash Command Register */
-#define NAND_ADDR_REG  (0x04) /* NandFlash Address Register */
-#define NAND_DATA_REG  (0x08) /* NandFlash Data Register */
-#define NAND_ECC0_REG  (0x10) /* NandFlash ECC Register0 */
-#define NAND_ECC1_REG  (0x14) /* NandFlash ECC Register1 */
-#define NAND_ECC2_REG  (0x18) /* NandFlash ECC Register2 */
-#define NAND_ECC3_REG  (0x1C) /* NandFlash ECC Register3 */
-#define NAND_ECC4_REG  (0x20) /* NandFlash ECC Register4 */
-#define NAND_ECC5_REG  (0x24) /* NandFlash ECC Register5 */
-#define NAND_ECC6_REG  (0x28) /* NandFlash ECC Register6 */
-#define NAND_ECC7_REG  (0x2C) /* NandFlash ECC Register7 */
-#define NAND_CR0_REG   (0x30) /* NandFlash Device Bank0 Config Register */
-#define NAND_CR1_REG   (0x34) /* NandFlash Device Bank1 Config Register */
-#define NAND_CR2_REG   (0x38) /* NandFlash Device Bank2 Config Register */
-#define NAND_CR3_REG   (0x3C) /* NandFlash Device Bank3 Config Register */
-#define NAND_CCR_REG   (0x40) /* NandFlash Core Configuration Register */
-#define NAND_STAT_REG  (0x44) /* NandFlash Device Status Register */
-#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
-#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
-
-/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
-#define NAND0_CMD_READ1_HALF1     0x00     /* Starting addr for 1rst half of registers */
-#define NAND0_CMD_READ1_HALF2     0x01     /* Starting addr for 2nd half of registers */
-#define NAND0_CMD_READ2           0x50
-#define NAND0_CMD_READ_ID         0x90
-#define NAND0_CMD_READ_STATUS     0x70
-#define NAND0_CMD_RESET           0xFF
-#define NAND0_CMD_PAGE_PROG       0x80
-#define NAND0_CMD_PAGE_PROG_TRUE  0x10
-#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
-#define NAND0_CMD_BLOCK_ERASE     0x60
-#define NAND0_CMD_BLOCK_ERASE_END 0xD0
-
-#define CFG_MAX_NAND_DEVICE     1	/* Max number of NAND devices */
-#define SECTORSIZE              512
-
-#define ADDR_COLUMN             1
-#define ADDR_PAGE               2
-#define ADDR_COLUMN_PAGE        3
-
-#define NAND_ChipID_UNKNOWN     0x00
-#define NAND_MAX_FLOORS         1
-#define NAND_MAX_CHIPS          1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
-#define WRITE_NAND(d, adr)      do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
-#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
-#define NAND_WAIT_READY(nand)   while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
-
-/* not needed with 440EP NAND controller */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------------- */
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
-#undef CONFIG_DDR_ECC			/* don't use ECC			*/
-#define CFG_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
-#define SPD_EEPROM_ADDRESS      {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#ifdef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
-#define CFG_ENV_OFFSET		0x0
-#endif /* CFG_ENV_IS_IN_EEPROM */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=bamboo\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/bamboo/uImage\0"				\
-	"kernel_addr=fff00000\0"					\
-	"ramdisk_addr=fff10000\0"					\
-	"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"		\
-	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
-		"cp.b 100000 fffa0000 60000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR        1
-
-#ifndef CONFIG_BAMBOO_NAND
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#endif /* CONFIG_BAMBOO_NAND */
-
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI        1       /* required for netconsole      */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-#ifdef CONFIG_BAMBOO_NAND
-#define _CFG_CMD_NAND CFG_CMD_NAND
-#else
-#define _CFG_CMD_NAND 0
-#endif /* CONFIG_BAMBOO_NAND */
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_USB	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_EXT2	| \
-				_CFG_CMD_NAND	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1       /* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/barco.h b/include/configs/barco.h
deleted file mode 100644
index 624fa1d6e2..0000000000
--- a/include/configs/barco.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
- * $Revision: 1.2 $
- * $Author: mleeman $
- * $Date: 2005/02/21 12:48:58 $
- *
- * Last ChangeLog Entry
- * $Log: barco.h,v $
- * Revision 1.2  2005/02/21 12:48:58  mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.1  2005/02/14 09:29:25  mleeman
- * moved barcohydra.h to barco.h
- *
- * Revision 1.4  2005/02/09 12:56:23  mleeman
- * add generic header to track changes in sources
- *
- *
- *******************************************************************/
-
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_BARCOBCD_STREAMING	1
-
-#undef USE_DINK32
-
-#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-#define CONFIG_BOOTARGS "mem=32M"
-
-/* Add support for a few extra bootp options like:
- *	- File size
- *	- DNS
- */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
-				  CFG_CMD_ELF    | \
-				  CFG_CMD_I2C 	 | \
-				  CFG_CMD_EEPROM | \
-				  CFG_CMD_PCI    )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-#define CONFIG_HUSH_PARSER	1 /* use "hush" command parser */
-#define CONFIG_BOOTDELAY 	1
-#define CONFIG_BOOTCOMMAND 	"boot_default"
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#undef CONFIG_PCI_PNP
-#undef CFG_CMD_NET
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
-
-#define CONFIG_LOGBUFFER
-#ifdef	CONFIG_LOGBUFFER
-#define CFG_STDOUT_ADDR 	0x1FFC000
-#else
-#define CFG_STDOUT_ADDR 	0x2B9000
-#endif
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-#endif
-
-#define CFG_FLASH_BASE		0xFFF00000
-#define CFG_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x000047A4	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-/* #define ENV_CRC		0x8BF6F24B	XXX - FIXME: gets defined automatically */
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CFG_EUMB_ADDR		0xFDF00000
-
-#define CFG_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x00400000
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
-#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly.  Please review!"
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-#define CFG_DBUS_SIZE2		1
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
- /*
- * NS16550 Configuration (internal DUART)
- */
- /*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-#define CFG_ROMNAL		0x0F	/*rom/flash next access time		*/
-#define CFG_ROMFAL		0x1E	/*rom/flash access time			*/
-
-#define CFG_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CFG_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 0
-#define CFG_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		0x01FFFFFF
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x02000000
-#define CFG_BANK1_END		0x02ffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x03f00000
-#define CFG_BANK2_END		0x03ffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x04000000
-#define CFG_BANK3_END		0x04ffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x05000000
-#define CFG_BANK4_END		0x05FFFFFF
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x06000000
-#define CFG_BANK5_END		0x06FFFFFF
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x07000000
-#define CFG_BANK6_END		0x07FFFFFF
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x08000000
-#define CFG_BANK7_END		0x08FFFFFF
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_CHECKSUM
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
deleted file mode 100644
index a66cdc3956..0000000000
--- a/include/configs/bubinga.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-------------------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!       are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
-*/
-#define        AUTO_MEMORY_CONFIG
-#define        DIMM_READ_ADDR 0xAB
-#define        DIMM_WRITE_ADDR 0xAA
-
-/*
-!-------------------------------------------------------------------------------
-! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
-! assuming a 33MHz input clock to the 405EP from the C9531.
-!-------------------------------------------------------------------------------
-*/
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66
-
-#endif
-/*----------------------------------------------------------------------------*/
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *       supported for backward compatibility.
- */
-#if 1
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=bubinga\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/bubinga/uImage\0"				\
-	"kernel_addr=fff80000\0"					\
-	"ramdisk_addr=fff90000\0"					\
-	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_CACHE	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD       691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
-
-#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
-#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SRAM_BASE		0xFFF00000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405EP CPU			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash/SRAM) initialization                                    */
-#define CFG_EBC_PB0AP           0x04006000
-#define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
-#define CFG_EBC_PB1AP           0x04041000
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 2 (not used) initialization                                      */
-#define CFG_EBC_PB2AP           0x00000000
-#define CFG_EBC_PB2CR           0x00000000
-
-/* Memory Bank 2 (not used) initialization                                      */
-#define CFG_EBC_PB3AP           0x00000000
-#define CFG_EBC_PB3CR           0x00000000
-
-/* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CFG_EBC_PB4AP           0x01815000
-#define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x55
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH          0x55555555
-#define CFG_GPIO0_OSRL          0x40000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xFFFF8014
-
-/*-----------------------------------------------------------------------
- * Some BUBINGA stuff...
- */
-#define NVRAM_BASE      0xF0000000
-#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
-#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
-#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
-#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
-
-#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
-#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
-#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
-#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
-#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
-#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
-
-#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
-#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
-#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
-#define FPGA_REG1_CLOCK_BIT_SHIFT  4
-#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
-#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
-#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
-#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
deleted file mode 100644
index ae75539c37..0000000000
--- a/include/configs/c2mon.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
-#define CONFIG_C2MON		1	/* ...on a C2MON module		*/
-
-#define CONFIG_80MHz		1	/* Running at 5 * 16 = 80 MHz	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_FEC_ENET		1	/* Use Fast Ethernet Controller	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected
- * to Port C (all outputs) and Port B (Over-Current Input)
- *-----------------------------------------------------------------------
- */
-			/* Output pins */
-#define TPS2211_VCCD0	0x0002		/* PC.14 */
-#define TPS2211_VCCD1	0x0004		/* PC.13 */
-#define TPS2211_VPPD0	0x0008		/* PC.12 */
-#define TPS2211_VPPD1	0x0010		/* PC.11 */
-#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
-			  TPS2211_VPPD0 | TPS2211_VPPD1 )
-
-			/* Input pins */
-#define TPS2211_OC	0x00000200	/* PB.22: Over-Current		*/
-#define TPS2211_INPUTS	( TPS2211_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
-					BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
deleted file mode 100644
index 6997c7a6f4..0000000000
--- a/include/configs/cerf250.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the CERF250 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
-#define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
-#define BOARD_LATE_INIT		1
-#define CONFIG_BAUDRATE		38400
-
-#undef 	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE 0x04000300
-#define CONFIG_SMC_USE_32_BIT
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ETHADDR		00:D0:CA:F1:3C:D2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.0.5
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_BOOTCOMMAND	"bootm 0xC0000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
-#define CONFIG_CMDLINE_TAG
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#define CFG_LONGHELP					/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT			"uboot$ "	/* Monitor Command Prompt */
-#else
-#define CFG_PROMPT			"=> "		/* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE			256			/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE 			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-										/* Print Buffer Size */
-#define CFG_MAXARGS			16			/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
-
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ
-
-#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
-
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   		/* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1			0xa0000000 	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x04000000 	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000 	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000 	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000 	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000 	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000 	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000 	/* 0 MB */
-
-#define PHYS_FLASH_1			0x00000000 	/* Flash Bank #1 */
-#define PHYS_FLASH_2			0x04000000 	/* Flash Bank #2 */
-#define PHYS_FLASH_SIZE			0x02000000 	/* 32 MB */
-#define PHYS_FLASH_BANK_SIZE		0x02000000 	/* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE		0x00040000 	/* 256 KB sectors (x2) */
-
-#define CFG_DRAM_BASE			0xa0000000
-#define CFG_DRAM_SIZE			0x04000000
-
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-
-/*
- * GPIO settings
- */
-
-
-#define CFG_GPSR0_VAL		0x00408030
-#define CFG_GPSR1_VAL		0x00BFA882
-#define CFG_GPSR2_VAL		0x0001C000
-#define CFG_GPCR0_VAL		0xC0031100
-#define CFG_GPCR1_VAL		0xFC400300
-#define CFG_GPCR2_VAL		0x00003FFF
-#define CFG_GPDR0_VAL		0xC0439330
-#define CFG_GPDR1_VAL		0xFCFFAB82
-#define CFG_GPDR2_VAL		0x0001FFFF
-#define CFG_GAFR0_L_VAL		0x80000000
-#define CFG_GAFR0_U_VAL		0xA5000010
-#define CFG_GAFR1_L_VAL		0x60008018
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAA0000A
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL		0x12447FF0
-#define CFG_MSC1_VAL		0x12BC5554
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x03CDC017
-#define CFG_MDMRS_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-#define _LED			0x08000010	/*check this */
-#define LED_BLANK		0x08000040
-#define LED_GPIO		0x10
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  	/* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_MONITOR_LEN		0x40000		/* 256 KiB */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
-#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
deleted file mode 100644
index 5947c2a319..0000000000
--- a/include/configs/cm4008.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2004
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
-#define CONFIG_CM4008	1		/* it is an OpenGear CM4008 boad */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CFG_ENV_IS_NOWHERE
-#define	CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
-
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTARGS		"mem=16M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x00008000	/* default load address */
-
-#define CFG_HZ			(1000)		/* 1ms resolution ticks */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
deleted file mode 100644
index e62fc06337..0000000000
--- a/include/configs/cm41xx.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
-#define CONFIG_CM41xx	1		/* it is an OpenGear CM41xx boad */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CFG_ENV_IS_NOWHERE
-#define	CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
-
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTARGS		"mem=32M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x00008000	/* default load address */
-
-#define CFG_HZ			(1000)		/* 1ms resolution ticks */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
deleted file mode 100644
index 572a70f120..0000000000
--- a/include/configs/cmc_pu2.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * 2004-2005 Gary Jennejohn <garyj@denx.de>
- *
- * Configuration settings for the CMC PU2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
-#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
-
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
-#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board		*/
-#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define USE_920T_MMU		1
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
-/* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
-
-/* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_BAUDRATE		9600
-
-/*
- * Hardware drivers
- */
-
-/* define one of these to choose the DBGU, USART0  or USART1 as console */
-#undef CONFIG_DBGU
-#define CONFIG_USART0
-#undef CONFIG_USART1
-
-#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
-
-#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
-
-#define CONFIG_HARD_I2C
-
-#ifdef CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		0	/* not used */
-#define CFG_I2C_SLAVE		0	/* not used */
-#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
-#define CFG_I2C_RTC_ADDR	0x32
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW
-#endif
-/* still about 20 kB free with this defined */
-#define CFG_LONGHELP
-
-#define CONFIG_BOOTDELAY      1
-
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DATE	| \
-			CFG_CMD_DHCP 	| \
-			CFG_CMD_EEPROM	| \
-			CFG_CMD_I2C	| \
-			CFG_CMD_NFS	| \
-			CFG_CMD_SNTP  ) & \
-		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#else
-#define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DHCP 	| \
-			CFG_CMD_NFS	| \
-			CFG_CMD_SNTP  ) & \
-		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#define CONFIG_TIMESTAMP
-#endif
-#define CFG_LONGHELP
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define AT91_SMART_MEDIA_ALE	(1 << 22)	/* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE	(1 << 21)	/* our CLE is AD21 */
-
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM		0x20000000
-#define PHYS_SDRAM_SIZE		0x1000000 	/* 16 megs */
-
-#define CFG_MEMTEST_START	PHYS_SDRAM
-#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
-
-#define CONFIG_DRIVER_ETHER
-#define CONFIG_NET_RETRY_COUNT		20
-#define CONFIG_AT91C_USE_RMII
-
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		2
-#define CFG_MAX_DATAFLASH_PAGES		16384
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
-
-#define PHYS_FLASH_1			0x10000000
-#define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(11 * CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		( 2 * CFG_HZ)	/* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_OFFSET			0x20000		/* after u-boot.bin */
-#define CFG_ENV_SECT_SIZE		(64 << 10)	/* sectors are 64 kB */
-#define CFG_ENV_SIZE			(16 << 10)	/* Use only 16 kB */
-
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
-
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
-
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		32		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-
-#ifndef __ASSEMBLY__
-/*-----------------------------------------------------------------------
- * Board specific extension for bd_info
- *
- * This structure is embedded in the global bd_info (bd_t) structure
- * and can be used by the board specific code (eg board/...)
- */
-
-struct bd_info_ext {
-	/* helper variable for board environment handling
-	 *
-	 * env_crc_valid == 0	 =>   uninitialised
-	 * env_crc_valid  > 0	 =>   environment crc in flash is valid
-	 * env_crc_valid  < 0	 =>   environment crc in flash is invalid
-	 */
-	int env_crc_valid;
-};
-#endif	/* __ASSEMBLY__ */
-
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
-						/* AT91C_TC_TIMER_DIV1_CLOCK */
-
-#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
-		"addmtd;bootm\0" \
-	"nfsargs=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath}\0" \
-	"net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
-		"addcons addmtd; bootm\0" \
-	"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
-	"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
-	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
-		"${hostname}::off\0" \
-	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
-		"64k(environment),768k(linux),4096k(root),-\0" \
-	"load=tftp ${loadaddr} ${loadfile}\0" \
-	"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
-		"cp.b ${loadaddr} 10000000 ${filesize};" \
-		"protect on 10000000 1001ffff\0" \
-	"updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
-		"cp.b ${loadaddr} 10030000 ${filesize}\0" \
-	"updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
-		"cp.b ${loadaddr} 100f0000 ${filesize}\0" \
-	"updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
-		"cp.b ${loadaddr} 104f0000 ${filesize}\0" \
-	"cramfsimage=cramfs_cmc-pu2.img\0" \
-	"jffsimage=jffs2_cmc-pu2.img\0" \
-	"loadfile=u-boot_cmc-pu2.bin\0" \
-	"bootfile=uImage_cmc-pu2\0" \
-	"loadaddr=0x20800000\0" \
-	"hostname=CMC-TC-PU2\0" \
-	"bootcmd=run dhcp_start;run flash_cramfs\0" \
-	"autoload=n\0" \
-	"dhcp_start=echo no DHCP\0" \
-	"ipaddr=192.168.0.190\0"
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
deleted file mode 100644
index e459919294..0000000000
--- a/include/configs/cmi_mpc5xx.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation,
- */
-
-/*
- * File:		cmi_mpc5xx.h
- *
- * Discription:		Config header file for cmi
- * 			board  using an MPC5xx CPU
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
-#define CONFIG_CMI		1		/* Using the customized cmi board 	*/
-
-/* Serial Console Configuration */
-#define	CONFIG_5xx_CONS_SCI1
-#undef	CONFIG_5xx_CONS_SCI2
-
-#define CONFIG_BAUDRATE		57600
-
-#define CONFIG_COMMANDS		(CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | 		\
-				 CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV |   		\
-				 CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN |	\
-				 CFG_CMD_IMI)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if 0
-#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
-#else
-#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
-#endif
-#define CONFIG_BOOTCOMMAND	"go 02034004" 	/* autoboot command			*/
-
-#define CONFIG_BOOTARGS		""		/* Assuming OS Image in 4 flash sector at offset 4004 */
-
-#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
-
-#define CONFIG_STATUS_LED	1		/* Enable status led */
-
-#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
-
-/*
- * Miscellaneous configurable options
- */
-
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	       /* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
-
-#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
-
-
-/*
- * Low Level Configuration Settings
- */
-
-/*
- * Internal Memory Mapped (This is not the IMMR content)
- */
-#define CFG_IMMR		0x01000000				/* Physical start adress of internal memory map */
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	64					/* Size in bytes reserved for initial global data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	0x013fa000				/* Physical start adress of inital stack */
-
-/*
- * Start addresses for the final memory configuration
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
-#define CFG_FLASH_BASE		0x02000000	/* External flash */
-#define PLD_BASE		0x03000000	/* PLD  */
-#define ANYBUS_BASE		0x03010000	/* Anybus Module */
-
-#define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file. 	*/
-						/* This adress is given to the linker with -Ttext to 	*/
-						/* locate the text section at this adress. 		*/
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
-#define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
-
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *-----------------------------------------------------------------------
- *
- */
-
-#define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip 	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
-#define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-#ifdef	CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x00020000		/* Environment starts at this adress 	*/
-#define	CFG_ENV_SIZE		0x00010000		/* Set whole sector as env 		*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
-			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration
- *-----------------------------------------------------------------------
- * Data show cycle
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle 	*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register
- *-----------------------------------------------------------------------
- * Set all bits to 40 Mhz
- *
- */
-#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
-#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
-
-
-/*-----------------------------------------------------------------------
- * UMCR - UIMB Module Configuration Register
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
-
-/*-----------------------------------------------------------------------
- * ICTRL - I-Bus Support Control Register
- */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
-
-/*-----------------------------------------------------------------------
- * USIU - Memory Controller Register
- *-----------------------------------------------------------------------
- */
-
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
-#define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
-#define CFG_BR1_PRELIM		(ANYBUS_BASE)
-#define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
-#define CFG_BR2_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_PS_32)
-#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
-#define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
-#define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
-			 	 OR_ACS_10 | OR_ETHR | OR_CSNT)
-
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
-
-/*-----------------------------------------------------------------------
- * DER - Timer Decrementer
- *-----------------------------------------------------------------------
- * Initialise to zero
- */
-#define CFG_DER			0x00000000
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01			/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02			/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
deleted file mode 100644
index 9033fa88ed..0000000000
--- a/include/configs/cobra5272.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Configuation settings for the Sentec Cobra Board.
- *
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ---
- * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
- * Date: 2004-03-29
- * Author: Florian Schlote
- *
- * For a description of configuration options please refer also to the
- * general u-boot-1.x.x/README file
- * ---
- */
-
-/* ---
- * board/config.h - configuration options, board specific
- * ---
- */
-
-#ifndef _CONFIG_COBRA5272_H
-#define _CONFIG_COBRA5272_H
-
-/* ---
- * Define processor
- * possible values for Sentec board: only Coldfire M5272 processor supported
- * (please do not change)
- * ---
- */
-
-#define CONFIG_MCF52x2			/* define processor family */
-#define CONFIG_M5272			/* define processor type */
-
-/* ---
- * Defines processor clock - important for correct timings concerning serial
- * interface etc.
- * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
- * ---
- */
-
-#define CFG_HZ			1000
-#define CFG_CLK			66000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-
-/* ---
- * Enable use of Ethernet
- * ---
- */
-
-#define FEC_ENET
-
-/* ---
- * Define baudrate for UART1 (console output, tftp, ...)
- * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command
- * interface
- * ---
- */
-
-#define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-/* ---
- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
- * timeout acc. to your needs
- * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
- * for 10 sec
- * ---
- */
-
-#if 0
-#define CONFIG_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
-#endif
-
-/* ---
- * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
- * bootloader residing in flash ('chainloading'); if you want to use
- * chainloading or want to compile a u-boot binary that can be loaded into
- * RAM via BDM set
- * 	"#if 0" to "#if 1"
- * You will need a first stage bootloader then, e. g. colilo or a working BDM
- * cable (Background Debug Mode)
- *
- * Setting #if 0: u-boot will start from flash and relocate itself to RAM
- *
- * Please do not forget to modify the setting of TEXT_BASE
- * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
- *
- * ---
- */
-
-#if 0
-#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
-#endif
-
-/* ---
- * Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- * ---
- */
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_OFFSET		0x4000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_IS_EMBEDDED	1
-#else
-#define CFG_ENV_ADDR		0xffe04000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH	1
-#endif
-
-/* ---
- * Define which commmands should be available at u-boot command prompt
- * ---
- */
-
-#define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \
-CFG_CMD_LOADB) | CFG_CMD_MII)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- *-----------------------------------------------------------------------------
- * Define user parameters that have to be customized most likely
- *-----------------------------------------------------------------------------
- */
-
-/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
-
-#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
-seconds u-boot will wait before starting defined (auto-)boot command, setting
-to -1 disables delay, setting to 0 will too prevent access to u-boot command
-interface: u-boot then has to reflashed */
-
-
-/* The following settings will be contained in the environment block ; if you
-want to use a neutral environment all those settings can be manually set in
-u-boot: 'set' command */
-
-#if 0
-
-#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
-enter a valid image address in flash */
-
-#define CONFIG_BOOTARGS		" "			/* default bootargs that are
-considered during boot */
-
-/* User network settings */
-
-#define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
-#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
-#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
-
-#endif
-
-#define CFG_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
-
-#define CFG_LOAD_ADDR		0x20000		/*Defines default RAM address
-from which user programs will be started */
-
-/*---*/
-
-#define CFG_LONGHELP				/* undef to save memory		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*
- *-----------------------------------------------------------------------------
- * End of user parameters to be customized
- *-----------------------------------------------------------------------------
- */
-
-/* ---
- * Defines memory range for test
- * ---
- */
-
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-
-/* ---
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * ---
- */
-
-/* ---
- * Base register address
- * ---
- */
-
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-
-/* ---
- * System Conf. Reg. & System Protection Reg.
- * ---
- */
-
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
-
-/* ---
- * Ethernet settings
- * ---
- */
-
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE	0x780000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in internal SRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-
-/*
- *-------------------------------------------------------------------------
- * RAM SIZE (is defined above)
- *-----------------------------------------------------------------------
- */
-
-/* #define CFG_SDRAM_SIZE		16 */
-
-/*
- *-----------------------------------------------------------------------
- */
-
-#define CFG_FLASH_BASE		0xffe00000
-
-#ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
-#else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#endif
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	1000	/* flash timeout */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- *
- * Please refer also to Motorola Coldfire user manual - Chapter XXX
- * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
- */
-#define CFG_BR0_PRELIM		0xFFE00201
-#define CFG_OR0_PRELIM		0xFFE00014
-
-#define CFG_BR1_PRELIM		0
-#define CFG_OR1_PRELIM		0
-
-#define CFG_BR2_PRELIM		0
-#define CFG_OR2_PRELIM		0
-
-#define CFG_BR3_PRELIM		0
-#define CFG_OR3_PRELIM		0
-
-#define CFG_BR4_PRELIM		0
-#define CFG_OR4_PRELIM		0
-
-#define CFG_BR5_PRELIM		0
-#define CFG_OR5_PRELIM		0
-
-#define CFG_BR6_PRELIM		0
-#define CFG_OR6_PRELIM		0
-
-#define CFG_BR7_PRELIM		0x00000701
-#define CFG_OR7_PRELIM		0xFF00007C
-
-/*-----------------------------------------------------------------------
- * LED config
- */
-#define	LED_STAT_0	0xffff /*all LEDs off*/
-#define	LED_STAT_1	0xfffe
-#define	LED_STAT_2	0xfffd
-#define	LED_STAT_3	0xfffb
-#define	LED_STAT_4	0xfff7
-#define	LED_STAT_5	0xffef
-#define	LED_STAT_6	0xffdf
-#define	LED_STAT_7	0xff00 /*all LEDs on*/
-
-/*-----------------------------------------------------------------------
- * Port configuration (GPIO)
- */
-#define CFG_PACNT		0x00000000		/* PortA control reg.: All pins are external
-GPIO*/
-#define CFG_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
-(1^=output, 0^=input) */
-#define CFG_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
-#define CFG_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
-configuration */
-#define CFG_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
-#define CFG_PBDAT		0x0000			/* PortB value reg. */
-#define CFG_PDCNT		0x00000000		/* PortD control reg. */
-
-#endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h
deleted file mode 100644
index cdf5802a83..0000000000
--- a/include/configs/cogent_common.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen, CSIRO-MST
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _CONFIG_COGENT_COMMON_H
-#define _CONFIG_COGENT_COMMON_H
-
-/*
- * Cogent Motherboard Capabilities
- */
-#define CMA_MB_CAP_SERPAR	0x0001	/* has dual serial+parallel (16C552) */
-#define CMA_MB_CAP_LCD		0x0002	/* has LCD display (HD44780) */
-#define CMA_MB_CAP_FLASH	0x0004	/* has flash (E28F800B or AM29F800BB) */
-#define CMA_MB_CAP_RTC		0x0008	/* has RTC+NVRAM (MK48T02) */
-#define CMA_MB_CAP_ETHER	0x0010	/* has Ethernet (MB86964) */
-#define CMA_MB_CAP_SLOT1	0x0020	/* has CMABus slot 1 */
-#define CMA_MB_CAP_SLOT2	0x0040	/* has CMABus slot 2 */
-#define CMA_MB_CAP_SLOT3	0x0080	/* has CMABus slot 3 */
-#define CMA_MB_CAP_KBM		0x0100	/* has PS/2 keyboard+mouse (HT6542B) */
-#define CMA_MB_CAP_SER2		0x0200	/* has 2nd dual serial (16C2552) */
-#define CMA_MB_CAP_PCI		0x0400	/* has pci bridge (V360EPC) */
-#define CMA_MB_CAP_PCI_EXT	0x0800	/* can access extended pci space  */
-#define CMA_MB_CAP_PCI_ETHER	0x1000	/* has 10/100 ether on PCI (GD82559) */
-#define CMA_MB_CAP_PCI_VIDEO	0x2000	/* has video int'face on PCI (B69000) */
-#define CMA_MB_CAP_PCI_CARDBUS	0x4000	/* has Cardbus Ctlr on PCI (PD6832) */
-
-/*
- * Cogent option sanity checking
- */
-
-#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
-      defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
-
-/*
- * check a PowerPC 8xx cpu module has been selected
- */
-
-# if defined(CONFIG_CMA286_21)
-
-#  define COGENT_CPU_MODULE	"CMA286-21"
-
-# elif defined(CONFIG_CMA286_60_OLD)
-
-#  define COGENT_CPU_MODULE	"CMA286-60 (old)"
-
-# elif defined(CONFIG_CMA286_60)
-
-#  define COGENT_CPU_MODULE	"CMA286-60"
-
-# elif defined(CONFIG_CMA286_60P)
-
-#  define COGENT_CPU_MODULE	"CMA286-60P"
-
-# elif defined(CONFIG_CMA287_21)
-
-#  define COGENT_CPU_MODULE	"CMA287-21"
-
-# elif defined(CONFIG_CMA287_50)
-
-#  define COGENT_CPU_MODULE	"CMA287-50"
-
-# else
-
-#  error Cogent CPU Module must be a PowerPC MPC8xx module
-
-# endif
-
-#elif defined(CONFIG_MPC8260)
-
-/*
- * check a PowerPC 8260 cpu module has been selected
- */
-
-# if defined(CONFIG_CMA282)
-
-#  define COGENT_CPU_MODULE	"CMA282"
-
-# else
-
-#  error Cogent CPU Module must be a PowerPC MPC8260 module
-
-# endif
-
-#else
-
-# error CPU type must be PowerPC 8xx or 8260
-
-#endif
-
-/*
- * check a motherboard has been selected
- * define the motherboard capabilities while we're at it
- */
-
-#if defined(CONFIG_CMA101)
-
-# define COGENT_MOTHERBOARD	"CMA101"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
-				 CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS		3
-
-#elif defined(CONFIG_CMA102)
-
-# define COGENT_MOTHERBOARD	"CMA102"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
-				 CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS		3
-
-#elif defined(CONFIG_CMA110)
-
-# define COGENT_MOTHERBOARD	"CMA110"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
-# define CMA_MB_NSLOTS		0
-
-#elif defined(CONFIG_CMA111)
-
-# define COGENT_MOTHERBOARD	"CMA111"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
-				 CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
-				 CMA_MB_CAP_PCI_ETHER)
-# define CMA_MB_NSLOTS		1
-
-#elif defined(CONFIG_CMA120)
-
-# define COGENT_MOTHERBOARD	"CMA120"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
-				 CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
-				 CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
-				 CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
-# define CMA_MB_NSLOTS		1
-
-#elif defined(CONFIG_CMA150)
-
-# define COGENT_MOTHERBOARD	"CMA150"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_KBM)
-# define CMA_MB_NSLOTS		0
-
-#else
-
-# error Cogent Motherboard either unsupported or undefined
-
-#endif
-
-/*
- * check a flash i/o module has been selected if no flash on m/b
- */
-
-#if defined(CONFIG_CMA302)
-
-# define COGENT_FLASH_MODULE	"CMA302"
-
-#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
-
-# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
-
-#endif
-
-/*
- * some further sanity checks
- */
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#error Cogent Sanity Check: Both Slot2 and PCI are defined
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Extended PCI capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Motherboard ethernet capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#error 2nd dual serial capability defined without serial/parallel capability
-#endif
-#include "../board/cogent/mb.h"
-#endif	/* _CONFIG_COGENT_COMMON_H */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
deleted file mode 100644
index aea2e64365..0000000000
--- a/include/configs/cogent_mpc8260.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
-#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
-#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#define	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
-#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#ifdef CONFIG_CONS_NONE
-#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
-#endif
-#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#define CFG_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
-			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
-/* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
-#else
-#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
-#endif
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
-#else
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CFG_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		BCR_EBM
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR	(SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-#if defined(CONFIG_CMA282)
-
-/*
- * Init Memory Controller:
- *
- * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
- * and CS2 for (optional) local bus RAM on the CPU module.
- *
- * Note the motherboard address space (256 Mbyte in size) is connected
- * to the 60x Bus and is located starting at address 0. The Hard Reset
- * Configuration Word should put the 60x Bus into External Bus Mode, since
- * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
-#define CFG_CMA_CS0_SIZE	(1 << 20)
-#if 0
-#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
-#define CFG_CMA_CS2_SIZE	(16 << 20)
-#endif
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom at any other addresses will disappear.
- */
-
-/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
-/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
-				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * CS2 enables the Local Bus SDRAM on the CPU Module
- *
- * Will leave this unset for the moment, because a) my CPU module has no
- * SDRAM installed (it is optional); and b) it will require programming
- * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
- * if you can't test it.
- */
-
-#if 0
-/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
-/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
-#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
-#endif
-
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
deleted file mode 100644
index 80962d35fd..0000000000
--- a/include/configs/cogent_mpc8xx.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
-#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
-#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
-#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */
-
-/* serial console configuration */
-#undef	CONFIG_8xx_CONS_SMC1
-#undef	CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */
-
-#if defined(CONFIG_CMA286_60_OLD)
-#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
-#endif
-
-#define CONFIG_BAUDRATE		230400
-
-#define CONFIG_HARD_I2C		/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000  /* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CFG_ALLOC_DPRAM
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
-#define CONFIG_CONS_INDEX	1
-#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
-#else
-#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
-#endif
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
-#else
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-#if defined(CONFIG_CMA286_60_OLD)
-
-/*
- * Init Memory Controller:
- *
- * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
- * they are actually the final settings for this cpu/board, because the
- * flash and RAM are on the motherboard, accessed via the CMAbus, and the
- * mappings are pretty much fixed.
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CFG_CMA_CS0_BASE	TEXT_BASE		/* EPROM */
-#define CFG_CMA_CS0_SIZE	(1 << 20)
-#define CFG_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
-#define CFG_CMA_CS1_SIZE	(64 << 20)
-#define CFG_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
-#define CFG_CMA_CS2_SIZE	(64 << 20)
-#define CFG_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
-#define CFG_CMA_CS3_SIZE	(32 << 20)
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom at any other addresses will disappear.
- */
-
-/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
-/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
-#define CFG_OR0_PRELIM	((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
-
-/*
- * CS1 maps motherboard DRAM and motherboard I/O slot 1
- * (each 32Mbyte in size)
- */
-
-/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR1_PRELIM	((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CFG_OR1_PRELIM	((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS2 maps motherboard I/O slots 2 and 3
- * (each 32Mbyte in size)
- */
-
-/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR2_PRELIM	((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS3 maps motherboard I/O
- * (32Mbyte in size)
- */
-
-/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR3_PRELIM	((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
-#define CFG_OR3_PRELIM	((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
-
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
deleted file mode 100644
index f9586fbcb9..0000000000
--- a/include/configs/cpci5200.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
-#define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
-#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
-
-#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#if 1
-#define CONFIG_PCI		1
-#if 1
-#define CONFIG_PCI_PNP		1
-#endif
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#endif
-
-#define CONFIG_MII
-#if 0				/* test-only !!! */
-#define CONFIG_NET_MULTI	1
-#define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
-#define CONFIG_NS8382X		1
-#endif
-
-#define ADD_PCI_CMD		CFG_CMD_PCI
-
-#else				/* MPC5100 */
-
-#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
-
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD		0
-#endif
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
-				 CFG_CMD_EEPROM	| \
-				 CFG_CMD_FAT	| \
-				 CFG_CMD_IDE	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_ELF	| \
-				 CFG_CMD_EXT2	| \
-				 CFG_CMD_DATE	| \
-				 ADD_PCI_CMD	  )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
-#endif
-#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT08	1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Welcome to esd CPU CPCI/5200;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=eth0\0" \
-	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
-	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
-	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
-	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
-	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
-	"loadaddr=01000000\0" \
-	"serverip=192.168.2.99\0" \
-	"gatewayip=10.0.0.79\0" \
-	"user=mu\0" \
-	"target=cpci5200.esd\0" \
-	"script=cpci5200.bat\0" \
-	"image=/tftpboot/vxWorks_cpci5200\0" \
-	"ipaddr=10.0.13.196\0" \
-	"netmask=255.255.0.0\0" \
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
-
-#if defined(CONFIG_MPC5200)
-
-#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
-#define CFG_NVRAM_BASE_ADDR	0xfd010000
-#define CFG_NVRAM_SIZE		32*1024
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
-#endif
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
-
-#define CFG_I2C_SPEED		86000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1
-/*
- * Flash configuration
- */
-
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	     */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CFG_FLASH_INCREMENT	0x01000000
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128
-
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection	     */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/*
- * Environment settings
- */
-#if 1				/* test-only */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x20000
-#define CFG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-#else
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
-				   /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE	1
-#endif
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_UDP_CHECKSUM	1
-
-/*
- * GPIO configuration
- */
-#define CFG_GPS_PORT_CONFIG	0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004DD00
-
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-#define CFG_CS1_START		0xfd000000
-#define CFG_CS1_SIZE		0x00010000
-#define CFG_CS1_CFG		0x10101410
-
-#define CFG_CS3_START		0xfd010000
-#define CFG_CS3_SIZE		0x00010000
-#define CFG_CS3_CFG		0x10109410
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
-
-#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
-#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
-
-/* CPLD program pin configuration */
-#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
-#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
-#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
-
-#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
-#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
-#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
-
-#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET	0x00000000
-#define JTAG_GPIO_CFG_RESET	0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
-#define JTAG_GPIO_TDI_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
-#define JTAG_GPIO_TDO_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET	0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
deleted file mode 100644
index 776e1d2b7f..0000000000
--- a/include/configs/cradle.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
-#define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */
-
-#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE 0x10000300
-#define CONFIG_SMC91111_EXT_PHY
-#define CONFIG_SMC_USE_32_BIT
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE         115200
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY        3
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
-#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
-#define CONFIG_NETMASK          255.255.0.0
-#define CONFIG_IPADDR           192.168.0.21
-#define CONFIG_SERVERIP         192.168.0.250
-#define CONFIG_BOOTCOMMAND      "bootm 40000"
-#define CONFIG_CMDLINE_TAG
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR           0xa2000000      /* default load address */
-
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
-#define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
-
-#define CFG_DRAM_BASE           0xa0000000
-#define CFG_DRAM_SIZE           0x04000000
-
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS     1     /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR				0x00020000	/* absolute address for now   */
-#define CFG_ENV_SIZE				0x20000	   /* 8K ouch, this may later be */
-
-/******************************************************************************
- *
- * CPU specific defines
- *
- ******************************************************************************/
-
-/*
- * GPIO settings
- *
- * GPIO pin assignments
- * GPIO     Name        Dir Out AF
- * 0        NC
- * 1        NC
- * 2        SIRQ1       I
- * 3        SIRQ2       I
- * 4        SIRQ3       I
- * 5        DMAACK1     O   0
- * 6        DMAACK2     O   0
- * 7        DMAACK3     O   0
- * 8        TC1         O   0
- * 9        TC2         O   0
- * 10       TC3         O   0
- * 11       nDMAEN      O   1
- * 12       AENCTRL     O   0
- * 13       PLDTC       O   0
- * 14       ETHIRQ      I
- * 15       NC
- * 16       NC
- * 17       NC
- * 18       RDY         I
- * 19       DMASIO      I
- * 20       ETHIRQ      NC
- * 21       NC
- * 22       PGMEN       O   1    FIXME for debug only enable flash
- * 23       NC
- * 24       NC
- * 25       NC
- * 26       NC
- * 27       NC
- * 28       NC
- * 29       NC
- * 30       NC
- * 31       NC
- * 32       NC
- * 33       NC
- * 34       FFRXD       I       01
- * 35       FFCTS       I       01
- * 36       FFDCD       I       01
- * 37       FFDSR       I       01
- * 38       FFRI        I       01
- * 39       FFTXD       O   1   10
- * 40       FFDTR       O   0   10
- * 41       FFRTS       O   0   10
- * 42       RS232FOFF   O   0   00
- * 43       NC
- * 44       NC
- * 45       IRSL0       O   0
- * 46       IRRX0       I       01
- * 47       IRTX0       O   0   10
- * 48       NC
- * 49       nIOWE       O   0
- * 50       NC
- * 51       NC
- * 52       NC
- * 53       NC
- * 54       NC
- * 55       NC
- * 56       NC
- * 57       NC
- * 58       DKDIRQ      I
- * 59       NC
- * 60       NC
- * 61       NC
- * 62       NC
- * 63       NC
- * 64       COMLED      O   0
- * 65       COMLED      O   0
- * 66       COMLED      O   0
- * 67       COMLED      O   0
- * 68       COMLED      O   0
- * 69       COMLED      O   0
- * 70       COMLED      O   0
- * 71       COMLED      O   0
- * 72       NC
- * 73       NC
- * 74       NC
- * 75       NC
- * 76       NC
- * 77       NC
- * 78       CSIO        O   1
- * 79       NC
- * 80       CSETH       O   1
- *
- * NOTE: All NC's are defined to be outputs
- *
- */
-/* Pin direction control */
-/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
-#define CFG_GPDR0_VAL       0xfff3bf02
-#define CFG_GPDR1_VAL       0xfbffbf83
-#define CFG_GPDR2_VAL       0x0001ffff
-/* Set and Clear registers */
-#define CFG_GPSR0_VAL       0x00400800
-#define CFG_GPSR1_VAL       0x00000480
-#define CFG_GPSR2_VAL       0x00014000
-#define CFG_GPCR0_VAL       0x00000000
-#define CFG_GPCR1_VAL       0x00000000
-#define CFG_GPCR2_VAL       0x00000000
-/* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL       0x00000000
-#define CFG_GRER1_VAL       0x00000000
-#define CFG_GRER2_VAL       0x00000000
-#define CFG_GFER0_VAL       0x00000000
-#define CFG_GFER1_VAL       0x00000000
-#define CFG_GFER2_VAL       0x00000000
-/* Alternate function registers */
-#define CFG_GAFR0_L_VAL     0x00000000
-#define CFG_GAFR0_U_VAL     0x00000010
-#define CFG_GAFR1_L_VAL     0x900a9550
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0x20000000
-#define CFG_GAFR2_U_VAL     0x00000002
-
-/*
- * Clocks, power control and interrupts
- */
-#define CFG_PSSR_VAL        0x00000020
-#define CFG_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
-#define CFG_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
-#define CFG_ICMR_VAL        0x00000000  /* No interrupts enabled        */
-
-/* FIXME
- *
- * RTC settings
- * Watchdog
- *
- */
-
-/*
- * Memory settings
- *
- * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
- *       Verify timings on all
- */
-#define CFG_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
-/*#define CFG_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
-#define CFG_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
-#define CFG_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
-#ifdef REDBOOT_WAY
-#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CFG_MDMRS_VAL       0x00000000
-#define CFG_MDREFR_VAL      0x00018018
-#else
-#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CFG_MDMRS_VAL       0x00000000
-#define CFG_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
-#endif
-
-/*
- * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
- */
-#define CFG_MECR_VAL          0x00000000
-#define CFG_MCMEM0_VAL        0x00010504
-#define CFG_MCMEM1_VAL        0x00010504
-#define CFG_MCATT0_VAL        0x00010504
-#define CFG_MCATT1_VAL        0x00010504
-#define CFG_MCIO0_VAL         0x00004715
-#define CFG_MCIO1_VAL         0x00004715
-
-/* Board specific defines */
-
-/* LED defines */
-#define YELLOW    0x03
-#define RED       0x02
-#define GREEN     0x01
-#define OFF       0x00
-#define LED_IRDA0 0
-#define LED_IRDA1 2
-#define LED_IRDA2 4
-#define LED_IRDA3 6
-#define CRADLE_LED_SET_REG GPSR2
-#define CRADLE_LED_CLR_REG GPCR2
-
-/* SuperIO defines */
-#define CRADLE_SIO_INDEX      0x2e
-#define CRADLE_SIO_DATA       0x2f
-
-/* IO defines */
-#define CRADLE_CPLD_PHYS      0x08000000
-#define CRADLE_SIO1_PHYS      0x08100000
-#define CRADLE_SIO2_PHYS      0x08200000
-#define CRADLE_SIO3_PHYS      0x08300000
-#define CRADLE_ETH_PHYS       0x10000000
-
-#ifndef __ASSEMBLY__
-
-/* global prototypes */
-void led_code(int code, int color);
-
-#endif
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
deleted file mode 100644
index f04102e95c..0000000000
--- a/include/configs/csb226.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Cogent CSB226 board. For details see
- * http://www.cogcomp.com/csb_csb226.htm
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/csb226.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DEBUG 1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
-#define CONFIG_CSB226		1	/* on a CSB226 board                */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
-					/* for timer/console/ethernet       */
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART		1	/* we use FFUART on CSB226          */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-#undef  CONFIG_MISC_INIT_R		/* not used yet                     */
-
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
-#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.1.56
-#define CONFIG_SERVERIP		192.168.1.5
-#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG	1
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CFG_MALLOC_LEN		(128*1024)
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
-
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		128		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR           0xa3000000	/* default load address */
-						/* RS: where is this documented? */
-						/* RS: is this where U-Boot is  */
-						/* RS: relocated to in RAM?      */
-
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
-						/* RS: the oscillator is actually 3680130?? */
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-						/* 0101000001 */
-						/*      ^^^^^ Memory Speed 99.53 MHz         */
-						/*    ^^      Run Mode Speed = 2x Mem Speed  */
-						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Network chip
- */
-#define CONFIG_DRIVER_CS8900	1
-#define CS8900_BUS32		1
-#define CS8900_BASE		0x08000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
-#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB                    */
-
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
-#define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */
-
-#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CFG_DRAM_SIZE		0x02000000
-
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-
-# if 0
-/* FIXME: switch to _documented_ registers */
-/*
- * GPIO settings
- *
- * GP15 == nCS1      is 1
- * GP24 == SFRM      is 1
- * GP25 == TXD       is 1
- * GP33 == nCS5      is 1
- * GP39 == FFTXD     is 1
- * GP41 == RTS       is 1
- * GP47 == TXD       is 1
- * GP49 == nPWE      is 1
- * GP62 == LED_B     is 1
- * GP63 == TDM_OE    is 1
- * GP78 == nCS2      is 1
- * GP79 == nCS3      is 1
- * GP80 == nCS4      is 1
- */
-#define CFG_GPSR0_VAL       0x03008000
-#define CFG_GPSR1_VAL       0xC0028282
-#define CFG_GPSR2_VAL       0x0001C000
-
-/* GP02 == DON_RST   is 0
- * GP23 == SCLK      is 0
- * GP45 == USB_ACT   is 0
- * GP60 == PLLEN     is 0
- * GP61 == LED_A     is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CFG_GPCR0_VAL       0x00800004
-#define CFG_GPCR1_VAL       0x30002000
-#define CFG_GPCR2_VAL       0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK    is input
- * GP02 == DON_RST   is output
- * GP03 == RESET_IND is input
- * GP07 == RES11     is input
- * GP09 == RES12     is input
- * GP11 == SWUPDATE  is input
- * GP14 == nPOWEROK  is input
- * GP15 == nCS1      is output
- * GP17 == RES22     is input
- * GP18 == RDY       is input
- * GP23 == SCLK      is output
- * GP24 == SFRM      is output
- * GP25 == TXD       is output
- * GP26 == RXD       is input
- * GP32 == RES21     is input
- * GP33 == nCS5      is output
- * GP34 == FFRXD     is input
- * GP35 == CTS       is input
- * GP39 == FFTXD     is output
- * GP41 == RTS       is output
- * GP42 == USB_OK    is input
- * GP45 == USB_ACT   is output
- * GP46 == RXD       is input
- * GP47 == TXD       is output
- * GP49 == nPWE      is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT    is input
- * GP60 == PLLEN     is output
- * GP61 == LED_A     is output
- * GP62 == LED_B     is output
- * GP63 == TDM_OE    is output
- * GP64 == nDSPINT   is input
- * GP65 == STRAP0    is input
- * GP67 == STRAP1    is input
- * GP69 == STRAP2    is input
- * GP70 == STRAP3    is input
- * GP71 == STRAP4    is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2      is output
- * GP79 == nCS3      is output
- * GP80 == nCS4      is output
- */
-#define CFG_GPDR0_VAL       0x03808004
-#define CFG_GPDR1_VAL       0xF002A282
-#define CFG_GPDR2_VAL       0x0001C200
-
-/* GP15 == nCS1  is AF10
- * GP18 == RDY   is AF01
- * GP23 == SCLK  is AF10
- * GP24 == SFRM  is AF10
- * GP25 == TXD   is AF10
- * GP26 == RXD   is AF01
- * GP33 == nCS5  is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS   is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS   is AF10
- * GP46 == RXD   is AF10
- * GP47 == TXD   is AF01
- * GP49 == nPWE  is AF10
- * GP78 == nCS2  is AF10
- * GP79 == nCS3  is AF10
- * GP80 == nCS4  is AF10
- */
-#define CFG_GAFR0_L_VAL     0x80000000
-#define CFG_GAFR0_U_VAL     0x001A8010
-#define CFG_GAFR1_L_VAL     0x60088058
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0xA0000000
-#define CFG_GAFR2_U_VAL     0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH  = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CFG_PSSR_VAL		0x37
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31]    0    - Slower Device
- * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 000  - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15]    0    - Slower Device
- * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 000  - nonburst RAM or FLASH
- */
-#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15]    0    - Slower Device
- * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15]    0    - Slower Device
- * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29]   000 - reserved
- * [28]      0	 - no SA1111 compatiblity mode
- * [27]      0   - latch return data with return clock
- * [26]      0   - alternate addressing for pair 2/3
- * [25:24]   00  - timings
- * [23]      0   - internal banks in lower partition 2/3 (not used)
- * [22:21]   00  - row address bits for partition 2/3 (not used)
- * [20:19]   00  - column address bits for partition 2/3 (not used)
- * [18]      0   - SDRAM partition 2/3 width is 32 bit
- * [17]      0   - SDRAM partition 3 disabled
- * [16]      0   - SDRAM partition 2 disabled
- * [15:13]   000 - reserved
- * [12]      1	 - SA1111 compatiblity mode
- * [11]      1   - latch return data with return clock
- * [10]      0   - no alternate addressing for pair 0/1
- * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7]       1   - 4 internal banks in lower partition pair
- * [06:05]   10  - 13 row address bits for partition 0/1
- * [04:03]   01  - 9 column address bits for partition 0/1
- * [02]      0   - SDRAM partition 0/1 width is 32 bit
- * [01]      0   - disable SDRAM partition 1
- * [00]      1   - enable  SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0     - reserved
- * [25]    0     - K2FREE: not free running
- * [24]    0     - K1FREE: not free running
- * [23]    1     - K0FREE: not free running
- * [22]    0     - SLFRSH: self refresh disabled
- * [21]    0     - reserved
- * [20]    0     - APD: no auto power down
- * [19]    0     - K2DB2: SDCLK2 is MemClk
- * [18]    0     - K2RUN: disable SDCLK2
- * [17]    0     - K1DB2: SDCLK1 is MemClk
- * [16]    1     - K1RUN: enable SDCLK1
- * [15]    1     - E1PIN: SDRAM clock enable
- * [14]    1     - K0DB2: SDCLK0 is MemClk
- * [13]    0     - K0RUN: disable SDCLK0
- * [12]    1     - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CFG_MDREFR_VAL		0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31]      0       - reserved
- * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
- * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
- * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
- * [15]      0       - reserved
- * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
- * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CFG_MDMRS_VAL		0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00000000
-#define CFG_MCMEM1_VAL		0x00000000
-#define CFG_MCATT0_VAL		0x00000000
-#define CFG_MCATT1_VAL		0x00000000
-#define CFG_MCIO0_VAL		0x00000000
-#define CFG_MCIO1_VAL		0x00000000
-#endif
-
-/*
- * GPIO settings
- */
-#define CFG_GPSR0_VAL		0xFFFFFFFF
-#define CFG_GPSR1_VAL		0xFFFFFFFF
-#define CFG_GPSR2_VAL		0xFFFFFFFF
-#define CFG_GPCR0_VAL		0x08022080
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0xCD82A878
-#define CFG_GPDR1_VAL		0xFCFFAB80
-#define CFG_GPDR2_VAL		0x0001FFFF
-#define CFG_GAFR0_L_VAL		0x80000000
-#define CFG_GAFR0_U_VAL		0xA5254010
-#define CFG_GAFR1_L_VAL		0x599A9550
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAAAAAAA
-#define CFG_GAFR2_U_VAL		0x00000002
-
-/* FIXME: set GPIO_RER/FER */
-
-#define CFG_PSSR_VAL        0x20
-
-/*
- * Memory settings
- */
-
-#define CFG_MSC0_VAL            0x2ef15af0
-#define CFG_MSC1_VAL            0x00003ff4
-#define CFG_MSC2_VAL            0x7ff07ff0
-#define CFG_MDCNFG_VAL          0x09a909a9
-#define CFG_MDREFR_VAL          0x038ff030
-#define CFG_MDMRS_VAL           0x00220022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL        0x00000000
-#define CFG_MCMEM0_VAL      0x00000000
-#define CFG_MCMEM1_VAL      0x00000000
-#define CFG_MCATT0_VAL      0x00000000
-#define CFG_MCATT1_VAL      0x00000000
-#define CFG_MCIO0_VAL       0x00000000
-#define CFG_MCIO1_VAL       0x00000000
-
-#define CSB226_USER_LED0	0x00000008
-#define CSB226_USER_LED1	0x00000010
-#define CSB226_USER_LED2	0x00000020
-
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
-					/* Addr of Environment Sector       */
-#define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
deleted file mode 100644
index 4cc5085293..0000000000
--- a/include/configs/dbau1x00.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the dbau1x00 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
-#define CONFIG_DBAU1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
-
-#ifdef CONFIG_DBAU1000
-/* Also known as Merlot */
-#define CONFIG_AU1000		1
-#else
-#ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100		1
-#else
-#ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500		1
-#else
-#ifdef CONFIG_DBAU1550
-/* Cabernet */
-#define CONFIG_AU1550           1
-#else
-#error "No valid board set"
-#endif
-#endif
-#endif
-#endif
-
-#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
-
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
-
-#define CONFIG_BAUDRATE		115200
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"panic=1\0"						\
-	"bootfile=/tftpboot/vmlinux.srec\0"				\
-	"load=tftp 80500000 ${u-boot}\0"				\
-	""
-
-#ifdef CONFIG_DBAU1550
-/* Boot from flash by default, revert to bootp */
-#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
-
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
-				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
-				   CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
-				   CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
-#else /* CONFIG_DBAU1550 */
-#define CONFIG_BOOTCOMMAND	"bootp;bootm"
-
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
-				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
-				   CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
-				   CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
-#endif /* CONFIG_DBAU1550 */
-
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory      */
-
-#define	CFG_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */
-
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-#define CFG_MHZ			396
-
-#if (CFG_MHZ % 12) != 0
-#error "Invalid CPU frequency - must be multiple of 12!"
-#endif
-
-#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
-
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
-
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
-
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef CONFIG_DBAU1550
-
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */
-
-#else /* CONFIG_DBAU1550 */
-
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
-
-#endif /* CONFIG_DBAU1550 */
-
-#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
-
-#define CFG_FLASH_CFI           1
-#define CFG_FLASH_CFI_DRIVER    1
-
-/* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_INIT_SP_OFFSET	0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH_2
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_NOWHERE	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xB0030000
-#define CFG_ENV_SIZE		0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS	2
-
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_DBAU1550
-#define MEM_SIZE 192
-#else
-#define MEM_SIZE 64
-#endif
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-#ifndef CONFIG_DBAU1550
-/*---ATA PCMCIA ------------------------------------*/
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CFG_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     8
-
-/* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
-
-/* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
-#endif /* CONFIG_DBAU1550 */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/debris.h b/include/configs/debris.h
deleted file mode 100644
index 8ff963f55a..0000000000
--- a/include/configs/debris.h
+++ /dev/null
@@ -1,459 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Environments */
-
-/* bootargs */
-#define CONFIG_BOOTARGS \
-	"console=ttyS0,9600 init=/linuxrc " \
-	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
-	"/tftpboot/target " \
-	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
-	"255.255.255.0:debris:eth0:none " \
-	"mtdparts=phys:12m(root),-(kernel)"
-
-/* bootcmd */
-#define CONFIG_BOOTCOMMAND \
-	"tftp 800000 pImage; " \
-	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
-	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
-	"${netmask}:${hostname}:eth0:none " \
-	"mtdparts=phys:12m(root),-(kernel); " \
-	"bootm 800000"
-
-/* bootdelay */
-#define CONFIG_BOOTDELAY	5	/* autoboot 5s */
-
-/* baudrate */
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
-
-/* loads_echo */
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-
-/* ethaddr */
-#undef CONFIG_ETHADDR
-
-/* eth2addr */
-#undef CONFIG_ETH2ADDR
-
-/* eth3addr */
-#undef CONFIG_ETH3ADDR
-
-/* ipaddr */
-#define CONFIG_IPADDR	192.168.0.2
-
-/* serverip */
-#define CONFIG_SERVERIP	192.168.0.1
-
-/* autoload */
-#undef CFG_AUTOLOAD
-
-/* rootpath */
-#define CONFIG_ROOTPATH /tftpboot/target
-
-/* gatewayip */
-#define CONFIG_GATEWAYIP 192.168.0.1
-
-/* netmask */
-#define CONFIG_NETMASK 255.255.255.0
-
-/* hostname */
-#define CONFIG_HOSTNAME debris
-
-/* bootfile */
-#define CONFIG_BOOTFILE pImage
-
-/* loadaddr */
-#define CONFIG_LOADADDR 800000
-
-/* preboot */
-#undef CONFIG_PREBOOT
-
-/* clocks_in_mhz */
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_DEBRIS		1
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX       1
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_DRAM_SPEED	100		/* MHz */
-
-#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
-				  CFG_CMD_ASKENV	| \
-				  CFG_CMD_CACHE		| \
-				  CFG_CMD_DATE		| \
-				  CFG_CMD_DHCP		| \
-				  CFG_CMD_DIAG		| \
-				  CFG_CMD_EEPROM	| \
-				  CFG_CMD_ELF		| \
-				  CFG_CMD_I2C		| \
-				  CFG_CMD_JFFS2		| \
-				  CFG_CMD_KGBD		| \
-				  CFG_CMD_PCI		| \
-				  CFG_CMD_PING		| \
-				  CFG_CMD_SAVES		| \
-				  CFG_CMD_SDRAM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_PNP
-
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x20000000
-#define CONFIG_VERY_BIG_RAM
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	TEXT_BASE
-
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-#endif
-
-#define CFG_FLASH_BASE		0x7C000000
-#define CFG_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
-
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CFG_EUMB_ADDR		0xFC000000
-
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
-#define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=debris-0"
-#define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
-*/
-
-#define CFG_ENV_IS_IN_NVRAM      1
-#define CONFIG_ENV_OVERWRITE     1
-#define CFG_NVRAM_ACCESS_ROUTINE 1
-#define CFG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
-#define CFG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning */
-
-#define CFG_NVRAM_BASE_ADDR	0xff000000
-
-/*
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
- * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
- */
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly.  Please review!"
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		7372800
-
-#define CFG_NS16550_COM1	0xFF080000
-#define CFG_NS16550_COM2	(CFG_NS16550_COM1 + 8)
-#define CFG_NS16550_COM3	(CFG_NS16550_COM1 + 16)
-#define CFG_NS16550_COM4	(CFG_NS16550_COM1 + 24)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-#define CFG_DLL_EXTEND		0x00
-#define CFG_PCI_HOLD_DEL	0x20
-
-#define CFG_ROMNAL	15	/* rom/flash next access time */
-#define CFG_ROMFAL	31	/* rom/flash access time */
-
-#define CFG_REFINT	430	/* # of clocks between CBR refresh cycles */
-
-#define CFG_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
-
-/* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC	8	/* Refresh to activate interval		*/
-#define CFG_RDLAT	4	/* data latency from read command	*/
-#define CFG_PRETOACT	3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
-#endif
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(0x4000000 - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x04000000
-#define CFG_BANK1_END		(0x8000000 - 1)
-#define CFG_BANK1_ENABLE	1
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CFG_BANK_ENABLE		0x01
-
-#define CFG_ODCR		0x75	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
deleted file mode 100644
index 9ac2856f65..0000000000
--- a/include/configs/dnp1110.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Rolf Offermanns <rof@sysgo.de>
- *
- * Configuation settings for the SSV DNP1110 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_SKIP_LOWLEVEL_INIT	1
-#undef  CONFIG_SKIP_RELOCATE_UBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1110		1	/* This is an SA1110 CPU	*/
-#define CONFIG_DNP1110		1	/* on an DNP/1110 Board      */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE 0x20000300
-
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
-#define CONFIG_ETHADDR		02:80:ad:20:31:b8
-#define CONFIG_NETMASK          255.255.0.0
-#define CONFIG_IPADDR		172.22.2.23
-#define CONFIG_SERVERIP		172.22.2.22
-#define CONFIG_BOOTFILE		"dnp1110"
-#define CONFIG_BOOTCOMMAND	"tftp; bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"DNP1110 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xc0200000	/* default load address	*/
-
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
-#define PHYS_FLASH_BANK_SIZE    0x01000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 256 KB sectors (x2) */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128		/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xF80000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE			0x20000						/* Total Size of Environment Sector	*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
deleted file mode 100644
index d8882ea31c..0000000000
--- a/include/configs/ebony.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_EBONY		1	    /* Board is ebony		*/
-#define CONFIG_440GP		1	    /* Specifc GP support	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *       supported for backward compatibility.
- */
-#if 1
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
-
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
-
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_NVRAM */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=ebony\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/ebony/uImage\0"				\
-	"kernel_addr=ff800000\0"					\
-	"ramdisk_addr=ff810000\0"					\
-	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		8	/* PHY address			*/
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	9	/* EMAC1 PHY address		*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI			            /* include pci support	        */
-#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
deleted file mode 100644
index bdda6292ed..0000000000
--- a/include/configs/ep7312.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the EP7312 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
-#define CONFIG_EP7312		1	/* on an EP7312 Board      */
-#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
-
-#undef CONFIG_USE_IRQ			/* don't need them anymore */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000000
-#define CS8900_BUS16		1
-#undef  CS8900_BUS32
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
-#define CONFIG_ETHADDR	08:00:3e:21:c7:f7
-/*#define CONFIG_NETMASK        255.255.0.0	*/
-/*#define CONFIG_IPADDR		172.22.2.128	*/
-/*#define CONFIG_SERVERIP	172.22.2.126	*/
-/*#define CONFIG_BOOTFILE	"impa7"	*/
-#define CONFIG_BOOTCOMMAND	"bootp;bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"EP7312 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xc0500000	/* default load address	*/
-
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector	*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=ep7312-0"
-#define MTDPARTS_DEFAULT	"mtdparts=ep7312-0:-(jffs2)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
deleted file mode 100644
index 6862519309..0000000000
--- a/include/configs/ep8260.h
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
- * (C) Copyright 2002
- * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
- *
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the EP8260 manual.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- *
- * "EP8260 H, V.1.1"
- * 	- 64M 60x Bus SDRAM
- * 	- 32M Local Bus SDRAM
- * 	- 16M Flash (4 x AM29DL323DB90WDI)
- * 	- 128k NVRAM with RTC
- *
- * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
- * 	- 300MHz/133MHz/66MHz
- * 	- 64M 60x Bus SDRAM
- * 	- 32M Local Bus SDRAM
- * 	- 32M Flash
- * 	- 128k NVRAM with RTC
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Define this to enable support the EP8260 H2 version */
-#define CFG_EP8260_H2	1
-/* #undef CFG_EP8260_H2  */
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]	 Osc	CPM    Core
- * -------   ----------	 ---	---    ----
- * 0x2	     0x2	 33	133    133
- * 0x2	     0x3	 33	133    166
- * 0x2	     0x4	 33	133    200
- * 0x2	     0x5	 33	133    233
- * 0x2	     0x6	 33	133    266
- *
- * 0x5	     0x5	 66	133    133
- * 0x5	     0x6	 66	133    166
- * 0x5	     0x7	 66	133    200 *
- * 0x6	     0x0	 66	133    233
- * 0x6	     0x1	 66	133    266
- * 0x6	     0x2	 66	133    300
- */
-#ifdef CFG_EP8260_H2
-#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
-#else
-#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
-#endif
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-/* #define CFG_SBC_BOOT_LOW 1 */	/* only for HRCW */
-/* #undef CFG_SBC_BOOT_LOW */
-
-/* The reset command will not work as expected if the reset address does
- * not point to the correct address.
- */
-
-#define CFG_RESET_ADDRESS	0xFFF00100
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#ifdef CFG_EP8260_H2
-#define CFG_FLASH0_BASE 0xFE000000
-#define CFG_FLASH0_SIZE 32
-#else
-#define CFG_FLASH0_BASE 0xFF000000
-#define CFG_FLASH0_SIZE 16
-#endif
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
- * want it enabled, don't define these constants.
- */
-#define CFG_FLASH1_BASE 0
-#define CFG_FLASH1_SIZE 0
-#undef CFG_FLASH1_BASE
-#undef CFG_FLASH1_SIZE
-
-/* What should be the base address of SDRAM DIMM (60x bus) and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
-
-/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
- * local bus (8260 local bus is NOT cacheable!)
-*/
-/* #define CFG_LSDRAM */
-#undef CFG_LSDRAM
-
-#ifdef CFG_LSDRAM
-/* What should be the base address of SDRAM DIMM (local bus) and how big is
- * it (in Mbytes)?
-*/
-  #define CFG_SDRAM1_BASE 0x04000000
-  #define CFG_SDRAM1_SIZE 32
-#else
-  #define CFG_SDRAM1_BASE 0
-  #define CFG_SDRAM1_SIZE 0
-  #undef CFG_SDRAM1_BASE
-  #undef CFG_SDRAM1_SIZE
-#endif /* CFG_LSDRAM */
-
-/* What should be the base address of NVRAM and how big is
- * it (in Bytes)
- */
-#define CFG_NVRAM_BASE_ADDR  0xFA080000
-#define CFG_NVRAM_SIZE       (128*1024)-16
-
-/* The RTC is a Dallas DS1556
- */
-#define CONFIG_RTC_DS1556
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CFG_LED_BASE 0x00000000
-#undef CFG_LED_BASE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
-#undef  CONFIG_CONS_NONE            /* define if console on neither */
-#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
-#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
-#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
-
-#if ( CONFIG_ETHER_INDEX == 3 )
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- * - Enable Half Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-
-/*
- * - RAM for BD/Buffers is on the local Bus (see 28-13)
- */
-#ifdef CFG_LSDRAM
-  #define CFG_CPMFCR_RAMTYPE	3
-#else /* CFG_LSDRAM */
-  #define CFG_CPMFCR_RAMTYPE	0
-#endif /* CFG_LSDRAM */
-
-/* - Enable Half Duplex in FSMR */
-/* # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
-# define CFG_FCC_PSMR		0
-
-#else /* CONFIG_ETHER_INDEX */
-# error "on EP8260 ethernet must be FCC3"
-#endif /* CONFIG_ETHER_INDEX */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SOFT_I2C
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-/* #define CONFIG_RTC_DS174x */
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#ifdef CFG_EP8260_H2
-#define CONFIG_BAUDRATE         9600
-#else
-#define CONFIG_BAUDRATE         115200
-#endif
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR          00:10:EC:00:30:8C
-
-#define CONFIG_IPADDR		192.168.254.130
-#define CONFIG_SERVERIP         192.168.254.49
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY        -1
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt       */
-#define CFG_PROMPT              "=> "
-
-/* Define this variable to enable the "hush" shell (from
-   Busybox) as command line interpreter, thus enabling
-   powerful command line syntax like
-   if...then...else...fi conditionals or `&&' and '||'
-   constructs ("shell scripts").
-   If undefined, you get the old, much simpler behaviour
-   with a somewhat smapper memory footprint.
-*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-/* What U-Boot subsytems do you want enabled? */
-/*
-*/
-#define CONFIG_COMMANDS		( CFG_CMD_ALL     & \
-				  ~(	CFG_CMD_BMP	| \
-					CFG_CMD_BSP	| \
-					CFG_CMD_DCR	| \
-					CFG_CMD_DHCP	| \
-					CFG_CMD_DISPLAY	| \
-					CFG_CMD_DOC	| \
-					CFG_CMD_DTT	| \
-					CFG_CMD_EEPROM	| \
-					CFG_CMD_EXT2	| \
-					CFG_CMD_FDC	| \
-					CFG_CMD_FDOS	| \
-					CFG_CMD_HWFLOW	| \
-					CFG_CMD_IDE	| \
-					CFG_CMD_JFFS2	| \
-					CFG_CMD_KGDB	| \
-					CFG_CMD_MII	| \
-					CFG_CMD_MMC	| \
-					CFG_CMD_NAND	| \
-					CFG_CMD_PCI	| \
-					CFG_CMD_PCMCIA	| \
-					CFG_CMD_REISER	| \
-					CFG_CMD_SCSI	| \
-					CFG_CMD_SPI	| \
-					CFG_CMD_UNIVERSE| \
-					CFG_CMD_USB	| \
-					CFG_CMD_VFD	| \
-					CFG_CMD_XIMG	) )
-
-
-/* Where do the internal registers live? */
-#define CFG_IMMR               0xF0000000
-#define CFG_DEFAULT_IMMR       0x00010000
-
-/* Where do the on board registers (CS4) live? */
-#define CFG_REGS_BASE          0xFA000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
-#define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
-#else
-#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS       8            /* max number of command args   */
-
-#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
-
-#ifdef CFG_LSDRAM
-  #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
-  #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
-#else
-  #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
-  #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
-#endif /* CFG_LSDRAM */
-
-#define	CONFIG_CLOCKS_IN_MHZ	1      /* clocks passsed to Linux in MHz */
-
-#define CFG_LOAD_ADDR     0x00100000   /* default load address */
-#define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
-
-#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE    CFG_FLASH0_BASE
-#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-#ifdef CFG_EP8260_H2
-/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
-#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
-
-#define CFG_HRCW_MASTER (HRCW_EBM                |\
-			 HRCW_L2CPC01            |\
-			 CFG_SBC_HRCW_IMMR       |\
-			 HRCW_APPC10             |\
-			 HRCW_CS10PC01           |\
-			 CFG_SBC_MODCK_H 	 |\
-			 CFG_SBC_HRCW_BOOT_FLAGS)
-#else
-#define CFG_HRCW_MASTER 0x10400245
-#endif
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR       CFG_IMMR
-#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE          TEXT_BASE
-
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
-#ifdef CFG_EP8260_H2
-#define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
-#else
-#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
-#endif
-
-#ifdef CFG_EP8260_H2
-#define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
-#else
-#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
-#endif
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH  1
-
-#  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE  0x40000
-#  else
-#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
-#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
-#  endif /* CFG_ENV_IN_OWN_SECT */
-#else
-#  define CFG_ENV_IS_IN_NVRAM  1
-#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE         0x200
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-#ifdef CFG_LSDRAM
-/* 8260 local bus is NOT cacheable */
-#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#else /* !CFG_LSDRAM */
-#define CFG_HID0_FINAL  (HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#endif /* CFG_LSDRAM */
-
-#define CFG_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR         0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR         (BCR_EBM   |\
-			 BCR_PLDP  |\
-			 BCR_EAV   |\
-			 BCR_NPQM0)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
-			 SIUMCR_APPC10  |\
-			 SIUMCR_CS10PC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                            11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#ifdef CFG_EP8260_H2
-/* TBD: Find out why setting the BMT to 0xff causes the FCC to
- * generate TX buffer underrun errors for large packets under
- * Linux
- */
-#define CFG_SYPCR_BMT	0x00000600
-#else
-#define CFG_SYPCR_BMT	SYPCR_BMT
-#endif
-
-#ifdef CFG_LSDRAM
-#define CFG_SYPCR       (SYPCR_SWTC |\
-			 CFG_SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWP)
-#else
-#define CFG_SYPCR       (SYPCR_SWTC |\
-			 CFG_SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC     (TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#ifdef CFG_EP8260_H2
-#define CFG_PISCR       (PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-#else
-#define CFG_PISCR	0
-#endif
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- */
-#ifdef CFG_EP8260_H2
-#define CFG_SCCR        (SCCR_DFBRG00)
-#else
-#define CFG_SCCR        (SCCR_DFBRG01)
-#endif
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR        0
-
-/*-----------------------------------------------------------------------
- * MPTPR - Memory Refresh Timer Prescale Register               10-32
- *-----------------------------------------------------------------------
- */
-#define CFG_MPTPR	(0x0A00 & MPTPR_PTP_MSK)
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
- *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
- *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
- *  3   unused
- *  4   60x     GPCM     8 bit  Board Regs, NVRTC
- *  5   unused
- *  6   unused
- *  7   unused
- *  8   PCMCIA
- *  9   unused
- * 10   unused
- * 11   unused
-*/
-
-/*-----------------------------------------------------------------------
- * BRx - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * ORx - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0 - FLASH
- *
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64                      |\
-			 BRx_DECC_NONE                  |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_8_CLK                 |\
-			 ORxG_EHTR)
-
-/* Bank 1 - SDRAM
- * PSDRAM
- */
-#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_12)
-
-#ifdef CFG_EP8260_H2
-#define CFG_PSDMR       0xC34E246E
-#else
-#define CFG_PSDMR       0xC34E2462
-#endif
-
-#define CFG_PSRT	0x64
-
-#ifdef CFG_LSDRAM
-/* Bank 2 - SDRAM
- * LSDRAM
- */
-
-  #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
-			   BRx_PS_32                      |\
-			   BRx_MS_SDRAM_L                 |\
-			   BRx_V)
-
-  #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
-			   ORxS_BPD_4                     |\
-			   ORxS_ROWST_PBI0_A9             |\
-			   ORxS_NUMR_12)
-
-  #define CFG_LSDMR      0x416A2562
-  #define CFG_LSRT	0x64
-#else
-  #define CFG_LSRT	0x0
-#endif /* CFG_LSDRAM */
-
-/* Bank 4 - On board registers
- * NVRTC and BCSR
- */
-#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-			   BRx_PS_8                     |\
-			   BRx_MS_GPCM_P                |\
-			   BRx_V)
-/*
-#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
-			   ORxG_CSNT                   |\
-			   ORxG_ACS_DIV1               |\
-			   ORxG_SCY_10_CLK              |\
-			   ORxG_TRLX)
-*/
-#define CFG_OR4_PRELIM 0xfff00854
-
-#ifdef _NOT_USED_SINCE_NOT_WORKING_
-/* Bank 8 - On board registers
- * PCMCIA (currently not working!)
- */
-#define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-			   BRx_PS_16                     |\
-			   BRx_MS_GPCM_P                |\
-			   BRx_V)
-
-#define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
-			   ORxG_CSNT                   |\
-			   ORxG_ACS_DIV1               |\
-			   ORxG_SETA                   |\
-			   ORxG_SCY_10_CLK)
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM   0x02    /* Software reboot                   */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
deleted file mode 100644
index 88c2c7437d..0000000000
--- a/include/configs/evb4510.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * Configuation settings for evb4510 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * If we are developing, we might want to start u-boot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- *
- * Also swap the flash1 and flash2 addresses during debug.
- *
- * #define CONFIG_SKIP_LOWLEVEL_INIT
- */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7		1	/* This is a ARM7 CPU	 */
-#define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI	 */
-#define CONFIG_S3C4510B		1	/* it's a S3C4510B chip	 */
-#define CONFIG_EVB4510		1	/* on an EVB4510 Board	 */
-
-#define CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)
-#define CONFIG_STACKSIZE_FIQ    (4*1024)
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_S3C4510_ETH   1
-#define CONFIG_DRIVER_S3C4510_I2C   1
-#define CONFIG_DRIVER_S3C4510_UART  1
-#define CONFIG_DRIVER_S3C4510_FLASH 1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1, could also use 2 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_PING)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_ETHADDR		00:40:95:36:35:33
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		10.0.0.11
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_CMDLINE_TAG	/* submit bootargs to kernel */
-
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTCOMMAND	"tftp 100000 uImage"
-/* #define CONFIG_BOOTARGS    	"console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"evb4510 # "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_CMDLINE_TAG                      /* allow passing of command line args to linux */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00780000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0x00000000	/* default load address */
-
-#define CFG_SYS_CLK_FREQ	50000000	/* CPU freq: 50 MHz */
-#define CFG_HZ			1000		/* decrementer freq: 1 KHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
-*/
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map after relocation
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1		0x01000000 /* Flash Bank #1 */
-#define PHYS_FLASH_1_SIZE	0x00200000 /* 2 MB (one chip, 8bit access) */
-
-#define PHYS_FLASH_2		0x02000000 /* Flash Bank #2 */
-#define PHYS_FLASH_2_SIZE	0x00080000 /* 512KB (one chip, 8bit access) */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
-#define CFG_MAIN_SECT_SIZE	0x00010000  /* main size of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(4*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-/* environment settings */
-#define CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_NOWHERE
-
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x20000) /* environment start address */
-#define CFG_ENV_SECT_SIZE	0x10000	   /* Total Size of Environment Sector */
-#define CFG_ENV_SIZE		0x1000	   /* max size for environment */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h
deleted file mode 100644
index 5eda6732ca..0000000000
--- a/include/configs/ezkit533.h
+++ /dev/null
@@ -1,188 +0,0 @@
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
-
-#define CFG_LONGHELP		1
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_STAMP		1
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_DRIVER_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20310300
-#if 0
-#define CONFIG_MII
-#define CFG_DISCOVER_PHY
-#endif
-
-#define CONFIG_RTC_BF533	1
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz				 */
-#define CONFIG_CLKIN_HZ		 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
-/*						    1=CLKIN/2	 */
-#define CONFIG_CLKIN_HALF		0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
-/*						 1=bypass PLL	 */
-#define CONFIG_PLL_BYPASS		0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
-/* Values can range from 1-64					 */
-#define CONFIG_VCO_MULT			22
-/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
-/* Values can be 1, 2, 4, or 8 ONLY				 */
-#define CONFIG_CCLK_DIV			1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15					 */
-#define CONFIG_SCLK_DIV			5
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
-#endif
-
-#define CONFIG_MEM_SIZE			32	       /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH		 9	       /* 8, 9, 10, 11	  */
-#define CONFIG_MEM_MT48LC16M16A2TG_75	 1
-
-#define CONFIG_LOADS_ECHO	1
-
-
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
-					 CFG_CMD_PING	| \
-					 CFG_CMD_ELF	| \
-					 CFG_CMD_I2C	| \
-					 CFG_CMD_JFFS2	| \
-					 CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01F00000	/* 1 ... 31 MB in DRAM */
-#define CFG_LOAD_ADDR		0x01000000	/* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
-#define CFG_FLASH_BASE		0x20000000
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-#define CFG_FLASH0_BASE		0x20000000
-#define CFG_FLASH1_BASE		0x20200000
-#define CFG_FLASH2_BASE		0x20280000
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x20020000
-#define CFG_ENV_SECT_SIZE	0x10000 /* Total Size of Environment Sector */
-
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR		       11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#define POLL_MODE		1
-#define FLASH_TOT_SECT		40
-#define FLASH_SIZE		0x220000
-#define CFG_FLASH_SIZE		0x220000
-
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
-
-/*
- * I2C settings
- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
- */
-#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL				PF0
-#define PF_SDA				PF1
-
-#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SDA; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SDA; \
-							asm("ssync;"); \
-						}
-#define I2C_SCL(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SCL; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SCL; \
-							asm("ssync;"); \
-						}
-#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-
-
-#define __ADSPLPBLACKFIN__	1
-#define __ADSPBF533__		1
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |	\
-				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |	\
-				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0x7BB07BB0
-#define AMBCTL1VAL		0xFFC27BB0
-
-#define CONFIG_VDSP		1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
-
-#endif
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
deleted file mode 100644
index b68a2dca09..0000000000
--- a/include/configs/gcplus.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * 2003-2004 (c) MontaVista Software, Inc.
- *
- * Configuation settings for the ADS GraphicsClient+ board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef	 DEBUG
-
-/*
- * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
- * We don't actually init RAM in this case since we're using U-Boot as
- * an secondary boot loader during Linux kernel development and testing,
- * e.g. bootp/tftp download of the kernel is a far more convenient
- * when testing new kernels on this target. However the ADS GCPlus Linux
- * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
- * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
- */
-#undef  CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT	1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1110		1	/* This is an SA1100 CPU	*/
-#define CONFIG_GCPLUS		1	/* on an ADS GCPlus Board      */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
-
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_LAN91C96	/* we have an SMC9194 on-board */
-#define CONFIG_LAN91C96_BASE	0x100e0000
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on ADS GCPlus */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		38400
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
-#define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
-#define CFG_AUTOLOAD            "n"             /* No autoload */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	38400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"ADS GCPlus # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xc0000000	/* default load address	*/
-
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0a		/* set core clock to 206MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-#define PHYS_SDRAM_2		0xc8000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x01000000 /* 16 MB */
-
-
-#define PHYS_FLASH_1		0x08000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x00800000 /* 8 MB */
-#define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
-#define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#if	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-#else
-/* REVISIT: This doesn't work on ADS GCPlus just yet: */
-#define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
-#define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
-#define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
-#define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
-/*#define CFG_FLASH_PROTECTION    1       /--* hardware flash protection    */
-#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
-#endif
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		PHYS_FLASH_SECT_SIZE
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
deleted file mode 100644
index a49ed3bae3..0000000000
--- a/include/configs/gth2.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * (C) Copyright 2005
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the gth2 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
-#define CONFIG_GTH2		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
-
-#define CONFIG_AU1000		1
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_ETHADDR		DE:AD:BE:EF:01:02    /* Ethernet address */
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
-
-#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-
-#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
-
-#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
-
-#define CONFIG_BAUDRATE		115200
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 115200 }
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#define CONFIG_BOOTARGS "panic=1"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"addmisc=setenv bootargs $(bootargs) "				\
-		"ethaddr=$(ethaddr) \0"					\
-	"netboot=bootp;run addmisc;bootm\0"				\
-		""
-
-/* Boot from Compact flash partition 2 as default */
-#define CONFIG_BOOTCOMMAND	"ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
-   CFG_CMD_MII | CFG_CMD_LOADS	| CFG_CMD_LOADB | CFG_CMD_ELF | \
-   CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
-
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory	     */
-#define CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args*/
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-#define CFG_MHZ			500
-
-#define CFG_HZ			(CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
-
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
-
-#define CFG_LOAD_ADDR		0x81000000     /* default load address	*/
-
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x83000000
-
-#define CONFIG_HW_WATCHDOG	1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH		0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_INIT_SP_OFFSET	0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_ENV_IS_NOWHERE	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xB0030000
-#define CFG_ENV_SIZE		0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS	2
-
-#define CONFIG_NET_MULTI
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-/*---ATA PCMCIA ------------------------------------*/
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-
-#define CFG_PCMCIA_MEM_ADDR  0x20000000
-#define CFG_PCMCIA_IO_BASE   0x28000000
-#define CFG_PCMCIA_ATTR_BASE 0x30000000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_ATA_IDE0_OFFSET	0
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_IO_BASE
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0200
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
-
-#define GPIO_CACONFIG  (1<<0)
-#define GPIO_DPACONFIG (1<<6)
-#define GPIO_ERESET    (1<<11)
-#define GPIO_EEDQ      (1<<17)
-#define GPIO_WDI       (1<<18)
-#define GPIO_RJ1LY     (1<<22)
-#define GPIO_RJ1LG     (1<<23)
-#define GPIO_LEDCLK    (1<<29)
-#define GPIO_LEDD      (1<<30)
-#define GPIO_CPU_LED   (1<<31)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
deleted file mode 100644
index 4f83b1945d..0000000000
--- a/include/configs/gw8260.h
+++ /dev/null
@@ -1,820 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jmonkman@adventnetworks.com>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Oliver Brown <obrown@adventnetworks.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*********************************************************************/
-/* DESCRIPTION:
- *   This file contains the board configuartion for the GW8260 board.
- *
- * MODULE DEPENDENCY:
- *   None
- *
- * RESTRICTIONS/LIMITATIONS:
- *   None
- *
- * Copyright (c) 2001, Advent Networks, Inc.
- */
-/*********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Enable debug prints */
-#undef DEBUG                  /* General debug */
-#undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
- * -------   ----------  ---    ---    ----  -----  -----  -----
- * 0x5       0x5     66 133     133    Open  Close  Open
- * 0x5       0x6     66 133     166    Open  Open   Close
- * 0x5       0x7     66 133     200    Open  Open   Open
- * 0x6       0x0     66 133     233    Close Close  Close
- * 0x6       0x1     66 133     266    Close Close  Open
- * 0x6       0x2     66 133     300    Close Open   Close
- */
-#define CFG_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 8
-
-/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
- * Note: the 'flashchecksum' environment variable must also be set to 'y'.
- */
-#define CFG_FLASH_CHECKSUM
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
- */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
-
-/*
- * DRAM tests
- *   CFG_DRAM_TEST - enables the following tests.
- *
- *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *                        Environment variable 'test_dram_data' must be
- *                        set to 'y'.
- *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *                        addressable. Environment variable
- *                        'test_dram_address' must be set to 'y'.
- *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *                        This test takes about 6 minutes to test 64 MB.
- *                        Environment variable 'test_dram_walk' must be
- *                        set to 'y'.
- */
-#define CFG_DRAM_TEST
-#if defined(CFG_DRAM_TEST)
-#define CFG_DRAM_TEST_DATA
-#define CFG_DRAM_TEST_ADDRESS
-#define CFG_DRAM_TEST_WALK
-#endif /* CFG_DRAM_TEST */
-
-/*
- * GW8260 with 16 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *           :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *           :
- *           :
- *
- *           :
- *           :
- *     0x00F5 FF30     Monitor Stack (Growing downward)
- *                     Monitor Stack Buffer (0x80)
- *     0x00F5 FFB0     Board Info Data
- *     0x00F6 0000     Malloc Arena
- *           :          CFG_ENV_SECT_SIZE, 256k
- *           :          CFG_MALLOC_LEN,    128k
- *     0x00FC 0000     RAM Copy of Monitor Code
- *           :              CFG_MONITOR_LEN,   256k
- *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-/*
- * GW8260 with 64 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *           :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *           :
- *           :
- *
- *           :
- *           :
- *     0x03F5 FF30     Monitor Stack (Growing downward)
- *                     Monitor Stack Buffer (0x80)
- *     0x03F5 FFB0     Board Info Data
- *     0x03F6 0000     Malloc Arena
- *           :          CFG_ENV_SECT_SIZE, 256k
- *           :          CFG_MALLOC_LEN,    128k
- *     0x03FC 0000     RAM Copy of Monitor Code
- *           :              CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
-#undef  CONFIG_CONS_NONE        /* define if console on neither */
-#define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-
-#undef  CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
-
-#ifdef  CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
-#endif  /* CONFIG_ETHER_ON_SCC */
-
-#ifdef  CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
-#define CONFIG_MII              /* MII PHY management           */
-#define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT   2       /* Port C */
-#define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
-#define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
-	    else            iop->pdat &= ~0x00400000
-
-#define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
-	    else    iop->pdat &= ~0x00200000
-
-#define MIIDELAY    udelay(1)
-#endif  /* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE     115200
-
-/* Ethernet MAC address - This is set to all zeros to force an
- *                        an error if we use BOOTP without setting
- *                        the MAC address
- */
-#define CONFIG_ETHADDR      00:00:00:00:00:00
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
-
-/* Be selective on what keys can delay or stop the autoboot process
- *     To stop  use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT  "Autobooting in %d seconds, press \" \" to stop\n"
-#define CONFIG_AUTOBOOT_STOP_STR    " "
-#undef  CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS      0
-
-/* Add support for a few extra bootp options like:
- *  - File size
- *  - DNS
- */
-#define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | \
-			     CONFIG_BOOTP_BOOTFILESIZE | \
-			     CONFIG_BOOTP_DNS)
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt */
-#define CFG_PROMPT      "=> "
-
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS     (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-			       CFG_CMD_BEDBUG  | \
-			       CFG_CMD_ELF | \
-			       CFG_CMD_ASKENV  | \
-			       CFG_CMD_REGINFO | \
-			       CFG_CMD_IMMAP   | \
-			       CFG_CMD_MII)
-
-/* Where do the internal registers live? */
-#define CFG_IMMR        0xf0000000
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* What is the address of IO controller */
-#define CFG_IO_BASE 0xe0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
-#define CONFIG_GW8260       1   /* on an GW8260 Board  */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE        1024    /* Console I/O Buffer Size       */
-#else
-#  define CFG_CBSIZE        256     /* Console I/O Buffer Size       */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE    (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS     8          /* max number of command args   */
-
-#define CFG_BARGSIZE    CFG_CBSIZE /* Boot Argument Buffer Size    */
-
-/* Convert clocks to MHZ when passing board info to kernel.
- * This must be defined for eariler 2.4 kernels (~2.4.4).
- */
-#define CONFIG_CLOCKS_IN_MHZ
-
-#define CFG_LOAD_ADDR   0x100000 /* default load address */
-#define CFG_HZ          1000     /* decrementer freq: 1 ms ticks */
-
-
-/* memtest works from the end of the exception vector table
- * to the end of the DRAM less monitor and malloc area
- */
-#define CFG_MEMTEST_START   0x2000
-
-#define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
-
-#define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
-			    + CFG_MALLOC_LEN \
-			    + CFG_ENV_SECT_SIZE \
-			    + CFG_STACK_USAGE )
-
-#define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
-			    - CFG_MEM_END_USAGE )
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE  CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
-		  ((CFG_IMMR & 0x01000000) >>  7) | \
-		  ((CFG_IMMR & 0x00100000) >>  4) )
-
-#define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
-		  HRCW_DPPC11               | \
-		  CFG_SBC_HRCW_IMMR         | \
-		  HRCW_MMR00                | \
-		  HRCW_LBPC11               | \
-		  HRCW_APPC10               | \
-		  HRCW_CS10PC00             | \
-		  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
-		  CFG_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1     0
-#define CFG_HRCW_SLAVE2     0
-#define CFG_HRCW_SLAVE3     0
-#define CFG_HRCW_SLAVE4     0
-#define CFG_HRCW_SLAVE5     0
-#define CFG_HRCW_SLAVE6     0
-#define CFG_HRCW_SLAVE7     0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR    CFG_IMMR
-#define CFG_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET   CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE    CFG_FLASH0_BASE
-
-#define CFG_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS   1    /* max number of memory banks        */
-#define CFG_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
-
-#define CFG_ENV_IS_IN_FLASH   1
-
-#ifdef CFG_ENV_IN_OWN_SECT
-#  define CFG_ENV_ADDR        (CFG_MONITOR_BASE +  (256 * 1024))
-#  define CFG_ENV_SECT_SIZE   (256 * 1024)
-#else
-#  define CFG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
-#  define CFG_ENV_ADD  ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE)
-#  define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
-#endif /* CFG_ENV_IN_OWN_SECT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE  32      /* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT    5   /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers            2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT   (HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL  (HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CFG_HID2    0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR     0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                           4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR     (BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                 4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR  (SIUMCR_DPPC11  |\
-		     SIUMCR_L2CPC00 |\
-		     SIUMCR_APPC10  |\
-		     SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CFG_SYPCR   (SYPCR_SWTC |\
-		     SYPCR_BMT  |\
-		     SYPCR_PBME |\
-		     SYPCR_LBME |\
-		     SYPCR_SWRI |\
-		     SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control             4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC (TMCNTSC_SEC |\
-		     TMCNTSC_ALR |\
-		     TMCNTSC_TCF |\
-		     TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control         4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR   (PISCR_PS  |\
-		     PISCR_PTF |\
-		     PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                           9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR    0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                 13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR    0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus   Machine PortSz  Device
- * ---- ---   ------- ------  ------
- *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
- *  1   60x   GPCM    32 bit  unused
- *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
- *  3   60x   SDRAM   64 bit  unused
- *  4   Local GPCM     8 bit  IO    (on board - 64k)
- *  5   60x   GPCM     8 bit  unused
- *  6   60x   GPCM     8 bit  unused
- *  7   60x   GPCM     8 bit  unused
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR0 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F016D parts.
- *
- * Note: For the 8 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- *     - Base address of 0x40000000
- *     - 32 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			  BRx_PS_32                     |\
-			  BRx_MS_GPCM_P                 |\
-			  BRx_V)
-
-/* OR0 is configured as follows:
- *
- *     - 8 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *       unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *       initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *       current bank and the next access.
- */
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE) |\
-			 ORxG_CSNT          |\
-			 ORxG_ACS_DIV1      |\
-			 ORxG_SCY_5_CLK     |\
-			 ORxG_TRLX          |\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2 - SDRAM DIMM
- *
- *     16MB DIMM: P/N
- *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
- *                     MT4LSDT864AG-10EB1 (Micron)
- *
- * Note: *CS3 is unused for this DIMM
- */
-
-/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
- *
- *     - Base address of 0x00000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			  BRx_PS_64          |\
-			  BRx_MS_SDRAM_P     |\
-			  BRx_V)
-
-/* With a 16 MB DIMM, the OR2 is configured as follows:
- *
- *     - 16 MB
- *     - 2 internal banks per device
- *     - Row start address bit is A9 with PSDMR[PBI] = 0
- *     - 11 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 16)
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
-			 ORxS_BPD_2         |\
-			 ORxS_ROWST_PBI0_A9 |\
-			 ORxS_NUMR_11)
-
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Page Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *       (A6 on A15, and so on),
- *     - use address pins A16-A18 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *       is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *       2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-#define CFG_PSDMR   (PSDMR_RFEN       |\
-		     PSDMR_SDAM_A14_IS_A5 |\
-		     PSDMR_BSMA_A16_A18   |\
-		     PSDMR_SDA10_PBI0_A9  |\
-		     PSDMR_RFRC_7_CLK     |\
-		     PSDMR_PRETOACT_3W    |\
-		     PSDMR_ACTTORW_2W     |\
-		     PSDMR_LDOTOPRE_1C    |\
-		     PSDMR_WRC_1C         |\
-		     PSDMR_CL_2)
-#endif /* (CFG_SDRAM0_SIZE == 16) */
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- *     - 64 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
-	     ORxS_BPD_4         |\
-	     ORxS_ROWST_PBI0_A8     |\
-	     ORxS_NUMR_12)
-
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Page Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *       (A6 on A15, and so on),
- *     - use address pins A14-A16 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *       is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *       2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-#define CFG_PSDMR   (PSDMR_RFEN       |\
-		     PSDMR_SDAM_A14_IS_A5 |\
-		     PSDMR_BSMA_A14_A16   |\
-		     PSDMR_SDA10_PBI0_A9  |\
-		     PSDMR_RFRC_7_CLK     |\
-		     PSDMR_PRETOACT_3W    |\
-		     PSDMR_ACTTORW_2W     |\
-		     PSDMR_LDOTOPRE_1C    |\
-		     PSDMR_WRC_1C         |\
-		     PSDMR_CL_2)
-#endif  /* (CFG_SDRAM0_SIZE == 64) */
-
-#define CFG_PSRT    0x0e
-#define CFG_MPTPR   MPTPR_PTP_DIV32
-
-
-/*-----------------------------------------------------------------------
- * BR4 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR4 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-/* Bank 4 - Onboard Memory Mapped IO controller
- *
- * This expects the onboard IO controller to connected to *CS4 and
- * the local bus.
- *     - Base address of 0xe0000000
- *     - 8 bit port size (local bus only)
- *     - Read and write access
- *     - GPCM local bus
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- *     - extended hold time
- *     - 11 wait states
- */
-
-#ifdef CFG_IO_BASE
-#  define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK)  |\
-			    BRx_PS_8                   |\
-			    BRx_MS_GPCM_L              |\
-			    BRx_V)
-
-#  define CFG_OR4_PRELIM   (ORxG_AM_MSK                |\
-			    ORxG_SCY_11_CLK            |\
-			    ORxG_EHTR)
-#endif /* CFG_IO_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM   0x02    /* Software reboot           */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
deleted file mode 100644
index 91117bab72..0000000000
--- a/include/configs/hermes.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
-#define CONFIG_HERMES		1	/* ...on a HERMES-PRO board	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_COMMANDS		CONFIG_CMD_DFL
-
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-/*----------------------------------------------------------------------*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_ALLOC_DPRAM		1	/* use allocation routines 	*/
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000	/* Non-Standard value!	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFE000000
-#ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x000000C0
- */
-#define CFG_SIUMCR	0
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => 0x00B0D0C0 */
-#define CFG_PLPRCR							\
-		(	(11 << PLPRCR_MF_SHIFT) |			\
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
-		)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* +0x0282 => 0x03800000 */
-#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
-			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CFG_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 4 MB of Flash */
-#define CFG_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
-				 OR_SCY_5_CLK | OR_TRLX)
-
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-/* 8 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR1/OR1 - SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
-#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
-
-#define CFG_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
- */
-#define HPRO2_BASE		0xE0000000
-#define HPRO2_OR_AM		0xFFFF8000
-#define HPRO2_TIMING		0x00000934
-
-#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
-#define CFG_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3/OR3: not used
- * BR4/OR4: not used
- * BR5/OR5: not used
- * BR6/OR6: not used
- * BR7/OR7: not used
- */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
deleted file mode 100644
index 8cad98dbd2..0000000000
--- a/include/configs/hymod.h
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for Hymod board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
-#define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#define	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
-#define CONFIG_ETHER_LOOPBACK_TEST	/* add ether external loopback test */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
-# define MDIO_CLCK_PINMASK	0x00080000	/* Pin 12 */
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
-# define MDIO_CLCK_PINMASK	0x00000080	/* Pin 24 */
-
-#elif (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
-# define MDIO_CLCK_PINMASK	0x00000200	/* Pin 22 */
-
-#endif	/* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management	*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-
-#define MDIO_ACTIVE	(iop->pdir |=  MDIO_DATA_PINMASK)
-#define MDIO_TRISTATE	(iop->pdir &= ~MDIO_DATA_PINMASK)
-#define MDIO_READ	((iop->pdat &  MDIO_DATA_PINMASK) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
-			else	iop->pdat &= ~MDIO_DATA_PINMASK
-
-#define MDC(bit)	if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
-			else	iop->pdat &= ~MDIO_CLCK_PINMASK
-
-#define MIIDELAY	udelay(1)
-
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-
-/* other options */
-#define CONFIG_HARD_I2C		1	/* To enable I2C hardware support	*/
-#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef DEBUG
-#define CONFIG_8260_CLKIN	33333333	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		115200
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/* default ip addresses - these will be overridden */
-#define CONFIG_IPADDR		192.168.1.1	/* hymod "boot" address */
-#define CONFIG_SERVERIP		192.168.1.254	/* hymod "server" address */
-
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-					CFG_CMD_BEDBUG	| \
-					CFG_CMD_BMP	| \
-					CFG_CMD_DISPLAY	| \
-					CFG_CMD_DOC	| \
-					CFG_CMD_EXT2	| \
-					CFG_CMD_FDC	| \
-					CFG_CMD_FDOS	| \
-					CFG_CMD_FPGA    | \
-					CFG_CMD_HWFLOW	| \
-					CFG_CMD_IDE	| \
-					CFG_CMD_JFFS2	| \
-					CFG_CMD_NAND	| \
-					CFG_CMD_MMC	| \
-					CFG_CMD_PCMCIA	| \
-					CFG_CMD_PCI	| \
-					CFG_CMD_USB	| \
-					CFG_CMD_REISER	| \
-					CFG_CMD_SCSI	| \
-					CFG_CMD_SPI	| \
-					CFG_CMD_UNIVERSE| \
-					CFG_CMD_VFD	| \
-					CFG_CMD_XIMG	) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#define CONFIG_BOOT_RETRY_TIME 30	/* retry autoboot after 30 secs	*/
-#define CONFIG_BOOT_RETRY_MIN	1	/* can go down to 1 second timeout */
-/* Be selective on what keys can delay or stop the autoboot process
- *	To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds, " \
-					"press <SPACE> to stop\n"
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS		0
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
-#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
-
-/*
- * Hymod specific configurable options
- */
-#undef	CFG_HYMOD_DBLEDS			/* walk mezz board LEDs */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
-
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define	CFG_I2C_SPEED		50000
-#define	CFG_I2C_SLAVE		0x7e
-
-/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* write eeprom in pages */
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CFG_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
-
-#define CFG_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
-
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the ADM1021, the rest determines index into
- * CFG_DTT_ADM1021 array below.
- *
- * On HYMOD board, the remote sensor should be connected to the MPC8260
- * temperature diode thingy, but an errata said this didn't work and
- * should be disabled - so it isn't connected.
- */
-#if 0
-#define CONFIG_DTT_SENSORS		{ 0, 1 }
-#else
-#define CONFIG_DTT_SENSORS		{ 0 }
-#endif
-
-/*
- * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For HYMOD board:
- * - only one ADM1021
- * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
- */
-#define CFG_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CFG_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
- */
-#ifdef DEBUG
-#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0010)
-#else
-#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0101)
-#endif
-/* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		TEXT_BASE
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_FPGA_BASE		0x80000000
-/*
- * unfortunately, CFG_MONITOR_LEN must include the
- * (very large i.e. 256kB) environment flash sector
- */
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
-#define	CFG_ENV_ADDR	(CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#ifdef DEBUG
-#define CFG_HID0_FINAL	0
-#else
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#endif
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#ifdef DEBUG
-#define CFG_RMR		0
-#else
-#define CFG_RMR		RMR_CSRE
-#endif
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
-			 SIUMCR_APPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CFG_SCCR	(SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Init Memory Controller:
- *
- * Bank	Bus	Machine	PortSz	Device
- * ----	---	-------	------	------
- *  0	60x	GPCM	32 bit	FLASH
- *  1	60x	GPCM	32 bit	FLASH (same as 0 - unused for now)
- *  2	60x	SDRAM	64 bit	SDRAM
- *  3	Local	UPMC	 8 bit	Main Xilinx configuration
- *  4	Local	GPCM	32 bit	Main Xilinx register mode
- *  5	Local	UPMB	32 bit	Main Xilinx port mode
- *  6	Local	UPMC	 8 bit	Mezz Xilinx configuration
- */
-
-/*
- * Bank 0 - FLASH
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The flash memory is two Intel StrataFlash chips, each configured for
- *  16 bit operation and connected to give a 32 bit wide port."
- *
- * "The chip select logic is configured to respond to both *CS0 and *CS1.
- *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
- *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
- *  FLASH will then appear as ROM during boot."
- *
- * Initially, we are only going to use bank 0 in read/write mode.
- */
-
-/* 32 bit, read-write, GPCM on 60x bus */
-#define	CFG_BR0_PRELIM	((CFG_FLASH_BASE&BRx_BA_MSK)|\
-				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
-/* up to 32 Mb */
-#define	CFG_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * Bank 2 - SDRAM
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
- *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
- *  dynamic random access memory organised as 4 banks by 4096 rows by 512
- *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
- *
- * "The locations in SDRAM are accessed using multiplexed address pins to
- *  specify row and column. The pins also act to specify commands. The state
- *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
- *  pin may function as a row address or as the AUTO PRECHARGE control line,
- *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
- *  address lines to be configured to the required multiplexing scheme."
- */
-
-#define CFG_SDRAM_SIZE	64
-
-/* 64 bit, read-write, SDRAM on 60x bus */
-#define	CFG_BR2_PRELIM	((CFG_SDRAM_BASE&BRx_BA_MSK)|\
-				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
-/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define	CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)|\
-				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
-
-/*
- * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
- *
- * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
- * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
- * as bank select, A7 is output on SDA10 during an ACTIVATE command,
- * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
- * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
- * command is 2 clocks, earliest timing for PRECHARGE after last data
- * was read is 1 clock, earliest timing for PRECHARGE after last data
- * was written is 1 clock, CAS Latency is 2.
- */
-
-#define CFG_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
-				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
-				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
-				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
-				PSDMR_WRC_1C|PSDMR_CL_2)
-
-/*
- * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
- * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
- * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
- * Prescaler, hence the P instead of the R). The refresh timer period is given
- * by (note that there was a change in the 8260 UM Errata):
- *
- *	TimerPeriod = (PSRT + 1) / Fmptc
- *
- * where Fmptc is the BusClock divided by PTP. i.e.
- *
- *	TimerPeriod = (PSRT + 1) / (BusClock / PTP)
- *
- * or
- *
- *	TImerPeriod = (PTP * (PSRT + 1)) / BusClock
- *
- * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
- * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
- * = 15.625 usecs.
- *
- * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
- * appear to be reasonable.
- */
-
-#ifdef DEBUG
-#define CFG_PSRT	39
-#define CFG_MPTPR	MPTPR_PTP_DIV8
-#else
-#define CFG_PSRT	31
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-#endif
-
-/*
- * Banks 3,4,5 and 6 - FPGA access
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
- *  for configuring an optional FPGA on the mezzanine interface.
- *
- *  Access to the FPGAs may be divided into several catagories:
- *
- *  1. Configuration
- *  2. Register mode access
- *  3. Port mode access
- *
- *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
- *  configured only (mode 1). Consequently there are four access types.
- *
- *  To improve interface performance and simplify software design, the four
- *  possible access types are separately mapped to different memory banks.
- *
- *  All are accessed using the local bus."
- *
- *	 Device		    Mode      Memory Bank Machine Port Size    Access
- *
- *	  Main		Configuration	   3	   UPMC	     8bit	R/W
- *	  Main		  Register	   4	   GPCM	    32bit	R/W
- *	  Main		    Port	   5	   UPMB	    32bit	R/W
- *	Mezzanine	Configuration	   6	   UPMC	     8bit	W/O
- *
- * "Note that mezzanine mode 1 access is write-only."
- */
-
-/* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE	(CFG_FPGA_BASE)
-#define FPGA_MAIN_CFG_SIZE	32768
-#define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
-#define FPGA_MAIN_REG_SIZE	32768
-#define FPGA_MAIN_PORT_BASE	(FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
-#define FPGA_MAIN_PORT_SIZE	32768
-#define FPGA_MEZZ_CFG_BASE	(FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
-#define FPGA_MEZZ_CFG_SIZE	32768
-
-/* 8 bit, read-write, UPMC */
-#define	CFG_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CFG_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
-
-/* 32 bit, read-write, GPCM */
-#define	CFG_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
-/* up to 32Kbyte */
-#define	CFG_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
-
-/* 32 bit, read-write, UPMB */
-#define	CFG_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
-/* up to 32Kbyte */
-#define	CFG_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
-
-/* 8 bit, write-only, UPMC */
-#define	CFG_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CFG_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * MBMR - Machine B Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CFG_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
-
-/*-----------------------------------------------------------------------
- * MCMR - Machine C Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CFG_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
-
-/*
- * FPGA I/O Port/Bit information
- */
-
-#define FPGA_MAIN_PROG_PORT	IOPIN_PORTA
-#define FPGA_MAIN_PROG_PIN	4	/* PA4 */
-#define FPGA_MAIN_INIT_PORT	IOPIN_PORTA
-#define FPGA_MAIN_INIT_PIN	5	/* PA5 */
-#define FPGA_MAIN_DONE_PORT	IOPIN_PORTA
-#define FPGA_MAIN_DONE_PIN	6	/* PA6 */
-
-#define FPGA_MEZZ_PROG_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_PROG_PIN	0	/* PA0 */
-#define FPGA_MEZZ_INIT_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_INIT_PIN	1	/* PA1 */
-#define FPGA_MEZZ_DONE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_DONE_PIN	2	/* PA2 */
-#define FPGA_MEZZ_ENABLE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_ENABLE_PIN	3	/* PA3 */
-
-/*
- * FPGA Interrupt configuration
- */
-#define FPGA_MAIN_IRQ		SIU_INT_IRQ2
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
deleted file mode 100644
index 48915b32e3..0000000000
--- a/include/configs/idmr.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Configuration settings for the iDMR board
- *
- * Based on MC5272C3, r5200  and M5271EVB board configs
- * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IDMR_H
-#define _IDMR_H
-
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5271		/* define processor type */
-#define CONFIG_IDMR		/* define board type */
-
-#undef CONFIG_WATCHDOG		/* disable watchdog */
-
-/*
- * Default environment settings
- */
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_ETHADDR		00:06:3b:01:41:55
-#define CONFIG_ETHPRIME
-#define CONFIG_IPADDR		192.168.30.1
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_ROOTPATH
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_HOSTNAME		idmr
-#define CONFIG_BOOTFILE		/tftpboot/idmr/uImage
-#define CONFIG_PREBOOT		"echo;echo Type \"run flash_nfs\" to mount root " \
-				"filesystem over NFS; echo"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ethact=FEC ETHERNET\0"						\
-	"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; "	\
-		"cp.b 200000 ff800000 $(filesize);"			\
-		"prot on ff800000 ff81ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"u-boot=/tftpboot/idmr/u-boot.bin\0"				\
-	""
-
-/*
- * Commands' definition
- */
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL		| \
-					CFG_CMD_PING		| \
-					CFG_CMD_NET		| \
-					CFG_CMD_MII)		& \
-					~(CFG_CMD_LOADS		| \
-						CFG_CMD_LOADB))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Configuration for environment, which occupies third sector in flash.
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_ADDR		0xff820000
-#define CFG_ENV_SECT_SIZE	0x10000
-#define CFG_ENV_SIZE		0x2000
-#define CFG_ENV_IS_IN_FLASH
-#else /* CONFIG_MONITOR_IS_IN_RAM */
-#define CFG_ENV_OFFSET		0x4000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CFG_ENV_IS_IN_FLASH
-#endif /* !CONFIG_MONITOR_IS_IN_RAM */
-
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
-#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
-
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CFG_LOAD_ADDR		0x00100000
-
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-
-#define CFG_HZ			(50000000 / 64)
-#define CFG_CLK			100000000
-
-#define CFG_MBAR		0x40000000	/* Register Base Addrs */
-
-/*
- * Ethernet
- */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT	5
-#define CFG_ENET_BD_BASE	0x480000
-#define CFG_DISCOVER_PHY	1
-#define CONFIG_MII		1
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xff800000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
-#else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
-
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	(64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/* FLASH organization */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
-
-#define CFG_FLASH_SIZE		0x800000
-/*
- * #define CFG_FLASH_USE_BUFFER_WRITE	1
- */
-
-/* Cache Configuration */
-#define CFG_CACHELINE_SIZE	16
-
-/* Port configuration */
-#define CFG_FECI2C		0xF0
-#endif /* _IDMR_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
deleted file mode 100644
index 8b841ff546..0000000000
--- a/include/configs/impa7.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the implementa impA7 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
-#define CONFIG_IMPA7		1	/* on an impA7 Board      */
-#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#define CONFIG_ARM7_REVD	1 	/* enable ARM720 REV.D Workarounds */
-
-#undef CONFIG_USE_IRQ			/* don't need them anymore */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000000
-#define CS8900_BUS32		1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
-/*#define CONFIG_ETHADDR	08:00:3e:26:0a:5a	*/
-/*#define CONFIG_NETMASK        255.255.0.0	*/
-/*#define CONFIG_IPADDR		172.22.2.128	*/
-/*#define CONFIG_SERVERIP	172.22.2.126	*/
-/*#define CONFIG_BOOTFILE	"impa7"	*/
-#define CONFIG_BOOTCOMMAND	"bootp;bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"impA7 # "		/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xc1000000	/* default load address	*/
-
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x10000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x00800000 /* 16 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00020000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=impA7 NOR Flash Bank #0,nor1=impA7 NOR Flash Bank #1"
-#define MTDPARTS_DEFAULT	"mtdparts=impA7 NOR Flash Bank #0:-(FileSystem1);impA7 NOR Flash Bank #1:-(FileSystem2)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
deleted file mode 100644
index 1c6216be84..0000000000
--- a/include/configs/incaip.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the INCA-IP board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
-#define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
-
-#ifndef	CPU_CLOCK_RATE
-/* allowed values: 100000000, 133000000, and 150000000 */
-#define CPU_CLOCK_RATE	150000000	/* default: 150 MHz clock for the MIPS core */
-#endif
-
-#define INFINEON_EBU_BOOTCFG	0x40C4	/* CMULT = 8 */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BAUDRATE		115200
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off\0"				\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"ethaddr=${ethaddr} "					\
-		"panic=1\0"						\
-	"flash_nfs=run nfsargs addip addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addmisc;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 80500000 ${bootfile};"				\
-		"run nfsargs addip addmisc;bootm\0"			\
-	"rootpath=/opt/eldk/mips_4KC\0"					\
-	"bootfile=/tftpboot/INCA/uImage\0"				\
-	"kernel_addr=B0040000\0"					\
-	"ramdisk_addr=B0100000\0"					\
-	"u-boot=/tftpboot/INCA/u-boot.bin\0"				\
-	"load=tftp 80500000 ${u-boot}\0"				\
-	"update=protect off 1:0-2;era 1:0-2;"				\
-		"cp.b 80500000 B0000000 ${filesize}\0"			\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_SNTP	)
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"INCA-IP # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-#define CFG_HZ			(incaip_get_cpuclk() / 2)
-
-#define CFG_SDRAM_BASE		0x80000000
-
-#define	CFG_LOAD_ADDR		0x80100000	/* default load address	*/
-
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0xb0800000 /* Flash Bank #2 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_INIT_SP_OFFSET	0x400000
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xB0030000
-#define CFG_ENV_SIZE		0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define CONFIG_INCA_IP_SWITCH
-#define CONFIG_NET_MULTI
-#define CONFIG_INCA_IP_SWITCH_AMDIX
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, use all space on the device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=INCA-IP Bank 0"
-#define MTDPARTS_DEFAULT	"mtdparts=INCA-IP Bank 0:192k(uboot)," \
-							"64k(env)," \
-							"768k(linux)," \
-							"1m@3m(rootfs)," \
-							"768k(linux2)," \
-							"3m@5m(rootfs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		4096
-#define CFG_ICACHE_SIZE		4096
-#define CFG_CACHELINE_SIZE	16
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
deleted file mode 100644
index 773d5d2c1d..0000000000
--- a/include/configs/inka4x0.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
-#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/
-
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CFG_XLB_PIPELINING	1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_SNTP	| \
-				CFG_CMD_USB	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (TEXT_BASE == 0xFFE00000)		/* Boot low */
-#   define CFG_LOWBOOT		1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_ETHADDR		00:a0:a4:03:00:00
-#define	CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define	CONFIG_IPADDR		192.168.100.2
-#define	CONFIG_SERVERIP		192.168.100.1
-#define	CONFIG_NETMASK		255.255.255.0
-#define HOSTNAME		inka4x0
-#define CONFIG_BOOTFILE		/tftpboot/inka4x0/uImage
-#define	CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addcons;bootm\0"			\
-	"enable_disp=mw.l 100000 04000000 1;"				\
-		"cp.l 100000 f0000b20 1;"				\
-		"cp.l 100000 f0000b28 1\0"				\
-	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
-	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
-		"run ideargs addip addcons enable_disp;bootm"		\
-	"brightness=255\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run ide_boot"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CFG_FLASH_BASE		0xFFE00000
-
-#define CFG_FLASH_SIZE		0x00200000 /* 2 MByte */
-#define CFG_MAX_FLASH_SECT	35	/* max num of sects on one chip */
-
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000) /* second sector */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x2000
-#define CFG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_MPC5200_DDR
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII
-
-/*
- * GPIO configuration
- *
- * use CS1 as gpio_wkup_6 output
- *	Bit 0 (mask: 0x80000000): 0
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
- *	      EEPROM
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
- *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
- */
-#define CFG_GPS_PORT_CONFIG	0x01001004
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-/* 32Mbit SRAM @0x30000000 */
-#define CFG_CS1_START		0x30000000
-#define CFG_CS1_SIZE		0x00400000
-#define CFG_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CFG_CS2_START		0x80000000
-#define CFG_CS2_SIZE		0x0001000
-#define CFG_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
-
-/* GPIO in @0x30400000 */
-#define CFG_CS3_START		0x30400000
-#define CFG_CS3_SIZE		0x00100000
-#define CFG_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK	0x00015555
-#define CONFIG_USB_CONFIG	0x00001000
-#define CONFIG_USB_STORAGE
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CFG_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
-#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE          4	/* Interval between registers	*/
-
-#define CONFIG_ATAPI            1
-
-#define CFG_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
deleted file mode 100644
index 3cb9ebc454..0000000000
--- a/include/configs/innokom.h
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Auerswald Innokom CPU board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/innokom.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
-#define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
-					/* for timer/console/ethernet       */
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART		1	/* we use FFUART on CSB226 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-#define CONFIG_MISC_INIT_R	1	/* we have a misc_init_r() function */
-
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)   */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
-#define CONFIG_BOOTARGS		"console=ttyS0,19200"
-#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.1.56
-#define CONFIG_SERVERIP		192.168.1.2
-#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG	1
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(256*1024)
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
-
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
-
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
-						/* RS: the oscillator is actually 3680130?? */
-
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-						/* 0101000001 */
-						/*      ^^^^^ Memory Speed 99.53 MHz         */
-						/*    ^^      Run Mode Speed = 2x Mem Speed  */
-						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * I2C bus
- */
-#define CONFIG_HARD_I2C 		1
-#define CFG_I2C_SPEED 			50000
-#define CFG_I2C_SLAVE 			0xfe
-
-#define CFG_ENV_IS_IN_EEPROM 		1
-
-#define CFG_ENV_OFFSET			0x00	/* environment starts here  */
-#define CFG_ENV_SIZE			1024	/* 1 KiB                    */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
-#define CFG_EEPROM_SIZE			4096	/* size in bytes            */
-#define CFG_I2C_INIT_BOARD		1	/* board has it's own init  */
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_DRIVER_SMC91111		1
-#define CONFIG_SMC91111_BASE		0x14000000 /* chip select 5         */
-#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
-#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
-#define CONFIG_SMC_AUTONEG_TIMEOUT	10	   /* timeout 10 seconds    */
-#undef  CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
-#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
-#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB                    */
-
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
-#define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */
-
-#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CFG_DRAM_SIZE		0x04000000
-
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-
-/*
- * JFFS2 partitions
- *
- */
-/* development flash */
-#define CONFIG_MTD_INNOKOM_16MB	1
-#undef CONFIG_MTD_INNOKOM_64MB
-
-/* production flash */
-/*
-#define CONFIG_MTD_INNOKOM_64MB	1
-#undef CONFIG_MTD_INNOKOM_16MB
-*/
-
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=innokom-0"
-*/
-
-/* development flash */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
-*/
-
-/* production flash */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
-*/
-
-/*
- * GPIO settings
- *
- * GP15 == nCS1      is 1
- * GP24 == SFRM      is 1
- * GP25 == TXD       is 1
- * GP33 == nCS5      is 1
- * GP39 == FFTXD     is 1
- * GP41 == RTS       is 1
- * GP47 == TXD       is 1
- * GP49 == nPWE      is 1
- * GP62 == LED_B     is 1
- * GP63 == TDM_OE    is 1
- * GP78 == nCS2      is 1
- * GP79 == nCS3      is 1
- * GP80 == nCS4      is 1
- */
-#define CFG_GPSR0_VAL       0x03008000
-#define CFG_GPSR1_VAL       0xC0028282
-#define CFG_GPSR2_VAL       0x0001C000
-
-/* GP02 == DON_RST   is 0
- * GP23 == SCLK      is 0
- * GP45 == USB_ACT   is 0
- * GP60 == PLLEN     is 0
- * GP61 == LED_A     is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CFG_GPCR0_VAL       0x00800004
-#define CFG_GPCR1_VAL       0x30002000
-#define CFG_GPCR2_VAL       0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK    is input
- * GP02 == DON_RST   is output
- * GP03 == RESET_IND is input
- * GP07 == RES11     is input
- * GP09 == RES12     is input
- * GP11 == SWUPDATE  is input
- * GP14 == nPOWEROK  is input
- * GP15 == nCS1      is output
- * GP17 == RES22     is input
- * GP18 == RDY       is input
- * GP23 == SCLK      is output
- * GP24 == SFRM      is output
- * GP25 == TXD       is output
- * GP26 == RXD       is input
- * GP32 == RES21     is input
- * GP33 == nCS5      is output
- * GP34 == FFRXD     is input
- * GP35 == CTS       is input
- * GP39 == FFTXD     is output
- * GP41 == RTS       is output
- * GP42 == USB_OK    is input
- * GP45 == USB_ACT   is output
- * GP46 == RXD       is input
- * GP47 == TXD       is output
- * GP49 == nPWE      is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT    is input
- * GP60 == PLLEN     is output
- * GP61 == LED_A     is output
- * GP62 == LED_B     is output
- * GP63 == TDM_OE    is output
- * GP64 == nDSPINT   is input
- * GP65 == STRAP0    is input
- * GP67 == STRAP1    is input
- * GP69 == STRAP2    is input
- * GP70 == STRAP3    is input
- * GP71 == STRAP4    is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2      is output
- * GP79 == nCS3      is output
- * GP80 == nCS4      is output
- */
-#define CFG_GPDR0_VAL       0x03808004
-#define CFG_GPDR1_VAL       0xF002A282
-#define CFG_GPDR2_VAL       0x0001C200
-
-/* GP15 == nCS1  is AF10
- * GP18 == RDY   is AF01
- * GP23 == SCLK  is AF10
- * GP24 == SFRM  is AF10
- * GP25 == TXD   is AF10
- * GP26 == RXD   is AF01
- * GP33 == nCS5  is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS   is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS   is AF10
- * GP46 == RXD   is AF10
- * GP47 == TXD   is AF01
- * GP49 == nPWE  is AF10
- * GP78 == nCS2  is AF10
- * GP79 == nCS3  is AF10
- * GP80 == nCS4  is AF10
- */
-#define CFG_GAFR0_L_VAL     0x80000000
-#define CFG_GAFR0_U_VAL     0x001A8010
-#define CFG_GAFR1_L_VAL     0x60088058
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0xA0000000
-#define CFG_GAFR2_U_VAL     0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH  = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CFG_PSSR_VAL		0x37
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31]    0    - Slower Device
- * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 000  - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15]    0    - Slower Device
- * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 000  - nonburst RAM or FLASH
- */
-#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15]    0    - Slower Device
- * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15]    0    - Slower Device
- * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29]   000 - reserved
- * [28]      0	 - no SA1111 compatiblity mode
- * [27]      0   - latch return data with return clock
- * [26]      0   - alternate addressing for pair 2/3
- * [25:24]   00  - timings
- * [23]      0   - internal banks in lower partition 2/3 (not used)
- * [22:21]   00  - row address bits for partition 2/3 (not used)
- * [20:19]   00  - column address bits for partition 2/3 (not used)
- * [18]      0   - SDRAM partition 2/3 width is 32 bit
- * [17]      0   - SDRAM partition 3 disabled
- * [16]      0   - SDRAM partition 2 disabled
- * [15:13]   000 - reserved
- * [12]      1	 - SA1111 compatiblity mode
- * [11]      1   - latch return data with return clock
- * [10]      0   - no alternate addressing for pair 0/1
- * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7]       1   - 4 internal banks in lower partition pair
- * [06:05]   10  - 13 row address bits for partition 0/1
- * [04:03]   01  - 9 column address bits for partition 0/1
- * [02]      0   - SDRAM partition 0/1 width is 32 bit
- * [01]      0   - disable SDRAM partition 1
- * [00]      1   - enable  SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0     - reserved
- * [25]    0     - K2FREE: not free running
- * [24]    0     - K1FREE: not free running
- * [23]    1     - K0FREE: not free running
- * [22]    0     - SLFRSH: self refresh disabled
- * [21]    0     - reserved
- * [20]    0     - APD: no auto power down
- * [19]    0     - K2DB2: SDCLK2 is MemClk
- * [18]    0     - K2RUN: disable SDCLK2
- * [17]    0     - K1DB2: SDCLK1 is MemClk
- * [16]    1     - K1RUN: enable SDCLK1
- * [15]    1     - E1PIN: SDRAM clock enable
- * [14]    1     - K0DB2: SDCLK0 is MemClk
- * [13]    0     - K0RUN: disable SDCLK0
- * [12]    1     - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CFG_MDREFR_VAL		0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31]      0       - reserved
- * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
- * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
- * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
- * [15]      0       - reserved
- * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
- * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CFG_MDMRS_VAL		0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00000000
-#define CFG_MCMEM1_VAL		0x00000000
-#define CFG_MCATT0_VAL		0x00000000
-#define CFG_MCATT1_VAL		0x00000000
-#define CFG_MCIO0_VAL		0x00000000
-#define CFG_MCIO1_VAL		0x00000000
-
-/*
-#define CSB226_USER_LED0	0x00000008
-#define CSB226_USER_LED1	0x00000010
-#define CSB226_USER_LED2	0x00000020
-*/
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
deleted file mode 100644
index 2f6e3993be..0000000000
--- a/include/configs/integratorap.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Integrator AP board.
- *.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x10000000
-#define CFG_HZ			1000
-#define CFG_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
-#define CFG_TIMERBASE		0x13000100	/* Timer1		       */
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
-
-#undef CONFIG_INIT_CRITICAL
-#define CONFIG_CM_INIT		1
-#define CONFIG_CM_REMAP		1
-#undef CONFIG_CM_SPD_DETECT
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * PL010 Configuration
- */
-#define CFG_PL010_SERIAL
-#define CONFIG_CONS_INDEX	0
-#define CONFIG_BAUDRATE		38400
-#define CONFIG_PL01x_PORTS	{ (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x16000000
-#define CFG_SERIAL1		0x17000000
-
-/*#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
-/*#define CONFIG_NET_MULTI */
-/*#define CONFIG_BOOTP_MASK	  CONFIG_BOOTP_DEFAULT */
-
-#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
-
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
-#define CONFIG_BOOTCOMMAND	""
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP	/* undef to save memory	    */
-#define CFG_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-
-#define CFG_FLASH_BASE		0x24000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_ENV_IS_NOWHERE
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT	128
-#define CFG_ENV_SIZE		32768
-
-#define PHYS_FLASH_1		(CFG_FLASH_BASE)
-
-/*-----------------------------------------------------------------------
- * PCI definitions
- */
-
-/*#define CONFIG_PCI			/--* include pci support	*/
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#define DEBUG
-
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
-
-
-#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
-#define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000
-
-/* PCI Base area */
-#define INTEGRATOR_PCI_BASE		0x40000000
-#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF
-
-/* memory map as seen by the CPU on the local bus */
-#define CPU_PCI_IO_ADRS		0x60000000	/* PCI I/O space base */
-#define CPU_PCI_IO_SIZE		0x10000
-
-#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
-#define CPU_PCI_CNFG_SIZE	0x1000000
-
-#define PCI_MEM_BASE		0x40000000   /* 512M to xxx */
-/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
-#define INTEGRATOR_PCI_IO_BASE	0x60000000   /* 16M to xxx */
-/*  unused (128-16)M from B1000000-B7FFFFFF */
-#define PCI_CONFIG_BASE		0x61000000   /* 16M to xxx */
-/*  unused ((128-16)M - 64K) from XXX */
-
-#define PCI_V3_BASE		0x62000000
-
-/* V3 PCI bridge controller */
-#define V3_BASE			0x62000000    /* V360EPC registers */
-
-#define PCI_ENET0_IOADDR	(CPU_PCI_IO_ADRS)
-#define PCI_ENET0_MEMADDR	(PCI_MEM_BASE)
-
-
-#define V3_PCI_VENDOR		0x00000000
-#define V3_PCI_DEVICE		0x00000002
-#define V3_PCI_CMD		0x00000004
-#define V3_PCI_STAT		0x00000006
-#define V3_PCI_CC_REV		0x00000008
-#define V3_PCI_HDR_CF		0x0000000C
-#define V3_PCI_IO_BASE		0x00000010
-#define V3_PCI_BASE0		0x00000014
-#define V3_PCI_BASE1		0x00000018
-#define V3_PCI_SUB_VENDOR	0x0000002C
-#define V3_PCI_SUB_ID		0x0000002E
-#define V3_PCI_ROM		0x00000030
-#define V3_PCI_BPARAM		0x0000003C
-#define V3_PCI_MAP0		0x00000040
-#define V3_PCI_MAP1		0x00000044
-#define V3_PCI_INT_STAT		0x00000048
-#define V3_PCI_INT_CFG		0x0000004C
-#define V3_LB_BASE0		0x00000054
-#define V3_LB_BASE1		0x00000058
-#define V3_LB_MAP0		0x0000005E
-#define V3_LB_MAP1		0x00000062
-#define V3_LB_BASE2		0x00000064
-#define V3_LB_MAP2		0x00000066
-#define V3_LB_SIZE		0x00000068
-#define V3_LB_IO_BASE		0x0000006E
-#define V3_FIFO_CFG		0x00000070
-#define V3_FIFO_PRIORITY	0x00000072
-#define V3_FIFO_STAT		0x00000074
-#define V3_LB_ISTAT		0x00000076
-#define V3_LB_IMASK		0x00000077
-#define V3_SYSTEM		0x00000078
-#define V3_LB_CFG		0x0000007A
-#define V3_PCI_CFG		0x0000007C
-#define V3_DMA_PCI_ADR0		0x00000080
-#define V3_DMA_PCI_ADR1		0x00000090
-#define V3_DMA_LOCAL_ADR0	0x00000084
-#define V3_DMA_LOCAL_ADR1	0x00000094
-#define V3_DMA_LENGTH0		0x00000088
-#define V3_DMA_LENGTH1		0x00000098
-#define V3_DMA_CSR0		0x0000008B
-#define V3_DMA_CSR1		0x0000009B
-#define V3_DMA_CTLB_ADR0	0x0000008C
-#define V3_DMA_CTLB_ADR1	0x0000009C
-#define V3_DMA_DELAY		0x000000E0
-#define V3_MAIL_DATA		0x000000C0
-#define V3_PCI_MAIL_IEWR	0x000000D0
-#define V3_PCI_MAIL_IERD	0x000000D2
-#define V3_LB_MAIL_IEWR		0x000000D4
-#define V3_LB_MAIL_IERD		0x000000D6
-#define V3_MAIL_WR_STAT		0x000000D8
-#define V3_MAIL_RD_STAT		0x000000DA
-#define V3_QBA_MAP		0x000000DC
-
-/* SYSTEM register bits */
-#define V3_SYSTEM_M_RST_OUT		(1 << 15)
-#define V3_SYSTEM_M_LOCK		(1 << 14)
-
-/*  PCI_CFG bits */
-#define V3_PCI_CFG_M_RETRY_EN		(1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1		(1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0		(1 << 8)
-
-/* PCI MAP register bits (PCI -> Local bus) */
-#define V3_PCI_MAP_M_MAP_ADR		0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH	(1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE		(1 << 11 | 1 << 10)
-#define V3_PCI_MAP_M_SWAP		(1 << 9 | 1 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE		0x000000F0
-#define V3_PCI_MAP_M_REG_EN		(1 << 1)
-#define V3_PCI_MAP_M_ENABLE		(1 << 0)
-
-/* 9 => 512M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_512M	0x00000090
-
-/* A => 1024M window size */
-#define V3_PCI_MAP_M_ADR_SIZE_1024M	0x000000A0
-
-/* LB_BASE register bits (Local bus -> PCI) */
-#define V3_LB_BASE_M_MAP_ADR		0xFFF00000
-#define V3_LB_BASE_M_SWAP		(1 << 8 | 1 << 9)
-#define V3_LB_BASE_M_ADR_SIZE		0x000000F0
-#define V3_LB_BASE_M_PREFETCH		(1 << 3)
-#define V3_LB_BASE_M_ENABLE		(1 << 0)
-
-/* PCI COMMAND REGISTER bits */
-#define V3_COMMAND_M_FBB_EN		(1 << 9)
-#define V3_COMMAND_M_SERR_EN		(1 << 8)
-#define V3_COMMAND_M_PAR_EN		(1 << 6)
-#define V3_COMMAND_M_MASTER_EN		(1 << 2)
-#define V3_COMMAND_M_MEM_EN		(1 << 1)
-#define V3_COMMAND_M_IO_EN		(1 << 0)
-
-#define INTEGRATOR_SC_BASE		0x11000000
-#define INTEGRATOR_SC_PCIENABLE_OFFSET	0x18
-#define INTEGRATOR_SC_PCIENABLE \
-			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
-
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- *   to define the necessary CONFIG_ s for the CM involved
- * see e.g. integratorcp_CM926EJ-S_config
- */
-#include "armcoremodule.h"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
deleted file mode 100644
index 4189f9c995..0000000000
--- a/include/configs/integratorcp.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Compact Integrator board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x10000000
-#define CFG_HZ			1000
-#define CFG_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
-#define CFG_TIMERBASE		0x13000100
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE    0xC8000000
-#undef CONFIG_SMC91111_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CFG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK	14745600
-#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
-#define CONFIG_CONS_INDEX	0
-#define CONFIG_BAUDRATE		38400
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x16000000
-#define CFG_SERIAL1		0x17000000
-
-/*
-#define CONFIG_COMMANDS		(CFG_CMD_DFL | CFG_CMD_PCI)
-*/
-#define CONFIG_COMMANDS		(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
-				 CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
-				)
-
-/* #define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if 0
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/nfs nfsroot=<IP address>:/<exported rootfs>  mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
-#define CONFIG_BOOTCOMMAND "bootp ; bootm"
-#endif
-/* The kernel command line & boot command below are for a platform flashed with afu.axf
-
-Image 666 Block  0 End Block  0 address 0x24000000 exec 0x24000000- name u-boot
-Image 667 Block  1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
-Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
-SIB at Block62 End Block62 address 0x24f80000
-
-*/
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
-#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size*/
-/* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16			/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE		/* Boot Argument Buffer Size*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 	0x08000000	/* 128 MB */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
-
- * Top varies according to amount fitted
- * Reserve top 4 blocks of flash
- * - ARM Boot Monitor
- * - Unused
- * - SIB block
- * - U-Boot environment
- *
- * Base is always 0x24000000
-
- */
-#define CFG_FLASH_BASE		0x24000000
-#define CFG_MAX_FLASH_SECT 	64
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define PHYS_FLASH_SIZE 	0x01000000	/* 16MB */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
-
-#define CFG_MONITOR_LEN		0x00100000
-#define CFG_ENV_IS_IN_FLASH	(1)
-
-/*
- * Move up the U-Boot & monitor area if more flash is fitted.
- * If this U-Boot is to be run on Integrators with varying flash sizes,
- * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
- * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
- * - CFG_MONITOR_BASE is set to indicate that the environment is not
- * embedded in the boot monitor(s) area
- */
-#if ( PHYS_FLASH_SIZE == 0x04000000 )
-
-#define CFG_ENV_ADDR		0x27F00000
-#define CFG_MONITOR_BASE	0x27F40000
-
-#elif (PHYS_FLASH_SIZE == 0x02000000 )
-
-#define CFG_ENV_ADDR		0x25F00000
-#define CFG_MONITOR_BASE	0x25F40000
-
-#else
-
-#define CFG_ENV_ADDR		0x24F00000
-#define CFG_MONITOR_BASE	0x27F40000
-
-#endif
-
-#define CFG_ENV_SECT_SIZE	0x40000		/* 256KB */
-#define CFG_ENV_SIZE		8192		/* 8KB */
-/*-----------------------------------------------------------------------
- * CP control registers
- */
-#define CPCR_BASE		0xCB000000	/* CP Registers*/
-#define OS_FLASHPROG		0x00000004	/* Flash register*/
-#define CPMASK_EXTRABANK	0x8
-#define CPMASK_FLASHSIZE	0x4
-#define CPMASK_FLWREN		0x2
-#define CPMASK_FLVPPEN		0x1
-
-/*
- * The ARM boot monitor initializes the board.
- * However, the default U-Boot code also performs the initialization.
- * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
- * - see documentation supplied with board for details of how to choose the
- * image to run at reset/power up
- * e.g. whether the ARM Boot Monitor runs before U-Boot
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
- */
-
-/*
- * The ARM boot monitor does not relocate U-Boot.
- * However, the default U-Boot code performs the relocation check,
- * and may relocate the code if the memory map is changed.
- * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
-
-#define SKIP_CONFIG_RELOCATE_UBOOT
-
- */
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. cp_926ejs_config
- */
-
-#include "armcoremodule.h"
-
-/*
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
-#undef	CONFIG_CM_INIT
- */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
deleted file mode 100644
index 9f9fdb25e2..0000000000
--- a/include/configs/ixdp425.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2003
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * Configuation settings for the IXDP425 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IXP425           1       /* This is an IXP425 CPU    */
-#define CONFIG_IXDP425          1       /* on an IXDP425 Board      */
-
-#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
-#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-
-#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE         115200
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
-
-#define CONFIG_PCI
-#define CONFIG_NET_MULTI
-#define CONFIG_EEPRO100
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY        3
-/*#define CONFIG_ETHADDR          08:00:3e:26:0a:5b*/
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR           192.168.0.21
-#define CONFIG_SERVERIP         192.168.0.148
-#define CONFIG_BOOTCOMMAND      "bootm 50040000"
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR           0x00010000      /* default load address */
-
-#define CFG_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/***************************************************************
- * Platform/Board specific defines start here.
- ***************************************************************/
-
-/*
- * Hardware drivers
- */
-
-
-/*
- * select serial console configuration
- */
-#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
-#define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
-#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
-
-#define CFG_DRAM_BASE           0x00000000
-#define CFG_DRAM_SIZE           0x01000000
-
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-
-/*
- * Expansion bus settings
- */
-#define CFG_EXP_CS0				0xbcd23c42
-
-/*
- * SDRAM settings
- */
-#define CFG_SDR_CONFIG		0xd
-#define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT 	0x81a
-
-/*
- * GPIO settings
- */
-
-/*
- * FLASH and environment organization
- */
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128 	/* max number of sectors on one chip    */
-
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define	CFG_ENV_IS_IN_FLASH	1
-
-#define CFG_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
-
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/lart.h b/include/configs/lart.h
deleted file mode 100644
index a00640bf8e..0000000000
--- a/include/configs/lart.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the LART board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1100		1	/* This is an SA1100 CPU	*/
-#define CONFIG_LART		1	/* on an LART Board      */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20008300
-#define CS8900_BUS16		1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on LART */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK          255.255.0.0
-#define CONFIG_IPADDR		172.22.2.131
-#define CONFIG_SERVERIP		172.22.2.126
-#define CONFIG_BOOTFILE		"elinos-lart"
-#define CONFIG_BOOTCOMMAND	"tftp; bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"LART # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xc8000000	/* default load address	*/
-
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_3            0xc8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE       0x00800000 /* 8 MB */
-#define PHYS_SDRAM_4            0xc9000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE       0x00800000 /* 8 MB */
-
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(31+8)	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
deleted file mode 100644
index 715ed74ead..0000000000
--- a/include/configs/logodl.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * (C) Copyright 2003
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Logotronic DL board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/logodl.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
-#define CONFIG_GEALOG		1	/* on a Logotronic GEALOG SG board  */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
-					/* for timer/console/ethernet       */
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART		1	/* we use FFUART                    */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-#undef CONFIG_MISC_INIT_R		/* FIXME: misc_init_r() missing     */
-
-#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)   */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
-#define CONFIG_BOOTARGS		"console=ttyS0,19200"
-#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.1.56
-#define CONFIG_SERVERIP		192.168.1.2
-#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG	1
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CFG_MALLOC_LEN		(256*1024)
-
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	0x08000000      /* memtest works on             */
-#define CFG_MEMTEST_END         0x0800ffff	/* 64 KiB                       */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR           0x08000000      /* load kernel to this address   */
-
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
-						/* RS: the oscillator is actually 3680130?? */
-
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-						/* 0101000001 */
-						/*      ^^^^^ Memory Speed 99.53 MHz         */
-						/*    ^^      Run Mode Speed = 2x Mem Speed  */
-						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * SMSC91C111 Network Card
- */
-#if 0
-#define CONFIG_DRIVER_SMC91111		1
-#define CONFIG_SMC91111_BASE		0x10000000 /* chip select 4         */
-#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
-#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
-#undef  CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of RAM    */
-#define PHYS_SDRAM_1		0x08000000	/* SRAM Bank #1             */
-#define PHYS_SDRAM_1_SIZE	(4*1024*1024)	/* 4 MB                     */
-
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
-#define PHYS_FLASH_2		0x01000000	/* Flash Bank #2            */
-#define PHYS_FLASH_SIZE		(32*1024*1024)	/* 32 MB                    */
-
-#define CFG_DRAM_BASE		PHYS_SDRAM_1	/* RAM starts here          */
-#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
-
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-
-
-/*
- * GPIO settings
- *
- * GP?? == FOOBAR    is 0/1
- */
-
-#define _BIT0       0x00000001
-#define _BIT1       0x00000002
-#define _BIT2       0x00000004
-#define _BIT3       0x00000008
-
-#define _BIT4       0x00000010
-#define _BIT5       0x00000020
-#define _BIT6       0x00000040
-#define _BIT7       0x00000080
-
-#define _BIT8       0x00000100
-#define _BIT9       0x00000200
-#define _BIT10      0x00000400
-#define _BIT11      0x00000800
-
-#define _BIT12      0x00001000
-#define _BIT13      0x00002000
-#define _BIT14      0x00004000
-#define _BIT15      0x00008000
-
-#define _BIT16      0x00010000
-#define _BIT17      0x00020000
-#define _BIT18      0x00040000
-#define _BIT19      0x00080000
-
-#define _BIT20      0x00100000
-#define _BIT21      0x00200000
-#define _BIT22      0x00400000
-#define _BIT23      0x00800000
-
-#define _BIT24      0x01000000
-#define _BIT25      0x02000000
-#define _BIT26      0x04000000
-#define _BIT27      0x08000000
-
-#define _BIT28      0x10000000
-#define _BIT29      0x20000000
-#define _BIT30      0x40000000
-#define _BIT31      0x80000000
-
-
-#define CFG_LED_A_BIT           (_BIT18)
-#define CFG_LED_A_SR            GPSR0
-#define CFG_LED_A_CR            GPCR0
-
-#define CFG_LED_B_BIT           (_BIT16)
-#define CFG_LED_B_SR            GPSR1
-#define CFG_LED_B_CR            GPCR1
-
-
-/* LED A: off, LED B: off */
-#define CFG_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
-#define CFG_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CFG_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
-
-#define CFG_GPCR0_VAL       0x00000000
-#define CFG_GPCR1_VAL       0x00000000
-#define CFG_GPCR2_VAL       0x00000000
-
-#define CFG_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
-#define CFG_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CFG_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
-
-#define CFG_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
-#define CFG_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
-			     _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
-#define CFG_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
-			     _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
-#define CFG_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CFG_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
-			     _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CFG_GAFR2_U_VAL     (_BIT1)
-
-#define CFG_PSSR_VAL        (0x20)
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL	0x123c2980
-#define CFG_MSC1_VAL	0x123c2661
-#define CFG_MSC2_VAL	0x7ff87ff8
-
-
-/* no sdram/pcmcia here */
-#define CFG_MDCNFG_VAL		0x00000000
-#define CFG_MDREFR_VAL		0x00000000
-#define CFG_MDREFR_VAL_100	0x00000000
-#define CFG_MDMRS_VAL		0x00000000
-
-/* only SRAM */
-#define SXCNFG_SETTINGS	0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-
-#define CFG_MECR_VAL        0x00000000
-#define CFG_MCMEM0_VAL      0x00010504
-#define CFG_MCMEM1_VAL      0x00010504
-#define CFG_MCATT0_VAL      0x00010504
-#define CFG_MCATT1_VAL      0x00010504
-#define CFG_MCIO0_VAL       0x00004715
-#define CFG_MCIO1_VAL       0x00004715
-
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
-
-/* FIXME */
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
-#define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
deleted file mode 100644
index 0350e91f0f..0000000000
--- a/include/configs/luan.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- * John Otken, jotken@softadvances.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * luan.h - configuration for LUAN board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_LUAN		1	/* Board is Luan		*/
-#define CONFIG_440SP		1	/* Specific PPC440SP support    */
-#define CONFIG_4xx		1	/* PPC4xx family	        */
-#define CONFIG_440		1
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc  */
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	/* MUST be zero */
-
-#define CFG_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
-#define CFG_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
-#define CFG_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
-#define CFG_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
-
-#define CFG_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
-
-#define CFG_PERIPHERAL_BASE     0xf0000000	/* internal peripherals */
-
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory */
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-#if CFG_LARGE_FLASH == 0xffc00000
-#define CFG_FLASH_BASE		CFG_LARGE_FLASH
-#else
-#define CFG_FLASH_BASE		CFG_SMALL_FLASH
-#endif
-
-#undef CFG_DRAM_TEST
-#if CFG_SRAM_BASE
-#define CFG_KBYTES_SDRAM	1024*2
-#else
-#define CFG_KBYTES_SDRAM	1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_END	(8 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
-#define CONFIG_BAUDRATE		115200
-#undef  CONFIG_SERIAL_MULTI
-#undef  CONFIG_UART1_CONSOLE		/* define if you want console on UART1 */
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_FLASH_ADDR0         0x555
-#define CFG_FLASH_ADDR1         0x2aa
-#define CFG_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef  CONFIG_SPD_EEPROM		/* SPD EEPROM init doesn't support DDR2 */
-#define SPD_EEPROM_ADDRESS {0x52,0x53}	/* I2C SPD addresses */
-#define IIC0_DIMM0_ADDR         0x52
-#define IIC0_DIMM1_ADDR         0x53
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=luan\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=1\0"			\
-	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm $(kernel_addr)\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/luan/uImage\0"				\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc100000\0"					\
-	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0"			\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG			/* watchdog */
-#endif
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL		|	\
-				CFG_CMD_ASKENV		|	\
-			        CFG_CMD_CACHE		|	\
-				CFG_CMD_DHCP		|	\
-				CFG_CMD_DIAG		|	\
-				CFG_CMD_ELF		|	\
-				CFG_CMD_EEPROM		|	\
-				CFG_CMD_I2C		|	\
-				CFG_CMD_IRQ		|	\
-				CFG_CMD_MII		|	\
-				CFG_CMD_NET		|	\
-				CFG_CMD_NFS		|	\
-				CFG_CMD_PCI		|	\
-				CFG_CMD_PING		|	\
-				CFG_CMD_REGINFO		|	\
-				CFG_CMD_SETGETDCR	|	\
-				CFG_CMD_SDRAM		|	\
-				0)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000 /* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#undef  CONFIG_LYNXKDI			/* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
-
-/* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT
-#undef  CFG_PCI_MASTER_INIT
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
-
-#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
deleted file mode 100644
index ad1035b6d6..0000000000
--- a/include/configs/lubbock.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the LUBBOCK board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
-#define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
-#define CONFIG_LCD		1
-#ifdef CONFIG_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-#define CONFIG_MMC		1
-#define BOARD_LATE_INIT		1
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x0C000000
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.0.21
-#define CONFIG_SERVERIP		192.168.0.250
-#define CONFIG_BOOTCOMMAND	"bootm 80000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_TIMESTAMP
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
-
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
-
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_MMC_BASE		0xF0000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-#define FPGA_REGS_BASE_PHYSICAL 0x08000000
-
-/*
- * GPIO settings
- */
-#define CFG_GPSR0_VAL		0x00008000
-#define CFG_GPSR1_VAL		0x00FC0382
-#define CFG_GPSR2_VAL		0x0001FFFF
-#define CFG_GPCR0_VAL		0x00000000
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0x0060A800
-#define CFG_GPDR1_VAL		0x00FF0382
-#define CFG_GPDR2_VAL		0x0001C000
-#define CFG_GAFR0_L_VAL		0x98400000
-#define CFG_GAFR0_U_VAL		0x00002950
-#define CFG_GAFR1_L_VAL		0x000A9558
-#define CFG_GAFR1_U_VAL		0x0005AAAA
-#define CFG_GAFR2_L_VAL		0xA0000000
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL		0x23F223F2
-#define CFG_MSC1_VAL		0x3FF1A441
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x00018018
-#define CFG_MDMRS_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-#define _LED			0x08000010
-#define LED_BLANK		0x08000040
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-/* NOTE: many default partitioning schemes assume the kernel starts at the
- * second sector, not an environment.  You have been warned!
- */
-#define	CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
-#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
-#define CFG_ENV_SIZE		(PHYS_FLASH_SECT_SIZE / 16)
-
-
-/*
- * FPGA Offsets
- */
-#define WHOAMI_OFFSET		0x00
-#define HEXLED_OFFSET		0x10
-#define BLANKLED_OFFSET		0x40
-#define DISCRETELED_OFFSET	0x40
-#define CNFG_SWITCHES_OFFSET	0x50
-#define USER_SWITCHES_OFFSET	0x60
-#define MISC_WR_OFFSET		0x80
-#define MISC_RD_OFFSET		0x90
-#define INT_MASK_OFFSET		0xC0
-#define INT_CLEAR_OFFSET	0xD0
-#define GP_OFFSET		0x100
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
deleted file mode 100644
index 9b4c0046ef..0000000000
--- a/include/configs/lwmon.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* External logbuffer support */
-#define CONFIG_LOGBUFFER
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823E CPU	*/
-#define CONFIG_LWMON		1	/* ...on a LWMON board		*/
-
-/* Default Ethernet MAC address */
-#define CONFIG_ETHADDR          00:11:B0:00:00:00
-
-/* The default Ethernet MAC address can be overwritten just once */
-#ifdef CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE   1
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-#define CONFIG_BOARD_POSTCLK_INIT 1	/* Call board_postclk_init	*/
-
-#define CONFIG_LCD		1	/* use LCD controller ...	*/
-#define CONFIG_HLD1045		1	/* ... with a HLD1045 display	*/
-
-#define CONFIG_LCD_LOGO		1	/* print our logo on the LCD	*/
-#define CONFIG_LCD_INFO		1	/* ... and some board info	*/
-#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
-
-#define CONFIG_SERIAL_MULTI	1
-#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#define CONFIG_8xx_CONS_SCC2	1	/* Console is on SCC2		*/
-
-#define CONFIG_BAUDRATE		115200	/* with watchdog >= 38400 needed */
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-/* pre-boot commands */
-#define	CONFIG_PREBOOT		"setenv bootdelay 15"
-
-#undef	CONFIG_BOOTARGS
-
-/* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE	   | \
-				 CFG_POST_WATCHDOG | \
-				 CFG_POST_RTC	   | \
-				 CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_ETHER    | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_SPI	   | \
-				 CFG_POST_USB	   | \
-				 CFG_POST_SPR	   | \
-				 CFG_POST_SYSMON)
-
-/*
- * Keyboard commands:
- * # = 0x28 = ENTER :		enable bootmessages on LCD
- * 2 = 0x3A+0x3C = F1 + F3 :	enable update mode
- * 3 = 0x3C+0x3F = F3 + F6 :	enable test mode
- */
-
-#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
-
-/*	"gatewayip=10.8.211.250\0"			                \ */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"kernel_addr=40080000\0"					\
-	"ramdisk_addr=40280000\0"					\
-	"netmask=255.255.192.0\0"				        \
-	"serverip=10.8.2.101\0"				                \
-	"ipaddr=10.8.57.0\0"				                \
-	"magic_keys=#23\0"						\
-	"key_magic#=28\0"						\
-	"key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
-	"key_magic2=3A+3C\0"						\
-	"key_cmd2=echo *** Entering Update Mode ***;"			\
-		"if fatload ide 0:3 10000 update.scr;"			\
-			"then autoscr 10000;"				\
-			"else echo *** UPDATE FAILED ***;"		\
-		"fi\0"							\
-	"key_magic3=3C+3F\0"						\
-	"key_cmd3=echo *** Entering Test Mode ***;"			\
-		"setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"	\
-	"addip=setenv bootargs $bootargs "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
-		"panic=1\0"						\
-	"add_wdt=setenv bootargs $bootargs $wdt_args\0"			\
-	"add_misc=setenv bootargs $bootargs runmode\0"			\
-	"flash_nfs=run nfsargs addip add_wdt addfb add_misc;"		\
-		"bootm $kernel_addr\0"					\
-	"flash_self=run ramargs addip add_wdt addfb add_misc;"		\
-		"bootm $kernel_addr $ramdisk_addr\0"			\
-	"net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"			\
-		"run nfsargs addip add_wdt addfb;bootm\0"		\
-	"rootpath=/opt/eldk/ppc_8xx\0"					\
-	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
-	"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
-	"wdt_args=wdt_8xx=off\0"					\
-	"verify=no"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
-#define	CFG_WATCHDOG_FREQ       (CFG_HZ / 20)
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
-
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
-
-#ifdef CONFIG_SOFT_I2C
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
-#endif	/* CONFIG_SOFT_I2C */
-
-
-#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_POST_DIAG | \
-				CFG_CMD_SNTP	)
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-
-#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * When the watchdog is enabled, output must be fast enough in Linux.
- */
-#ifdef CONFIG_WATCHDOG
-#define CFG_BAUDRATE_TABLE	{		38400, 57600, 115200 }
-#else
-#define CFG_BAUDRATE_TABLE	{  9600, 19200, 38400, 57600, 115200 }
-#endif
-
-/*----------------------------------------------------------------------*/
-#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
-#undef CONFIG_MODEM_SUPPORT_DEBUG
-
-#define	CONFIG_MODEM_KEY_MAGIC	"3C+3D"	/* press F3 + F4 keys to enable modem */
-#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
-#if 0
-#define	CONFIG_AUTOBOOT_KEYED		/* Enable "password" protection	*/
-#define CONFIG_AUTOBOOT_PROMPT	"\nEnter password - autoboot in %d sec...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR	"  "	/* "password"	*/
-#endif
-/*----------------------------------------------------------------------*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_USE_BUFFER_WRITE
-#define CFG_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
-/* Buffer size.
-   We have two flash devices connected in parallel.
-   Each device incorporates a Write Buffer of 32 bytes.
- */
-#define CFG_FLASH_BUFFER_SIZE	(2*32)
-
-/* Put environment in flash which is much faster to boot than using the EEPROM	*/
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR	    0x40040000	/* Address    of Environment Sector	*/
-#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
-#define CFG_ENV_SECT_SIZE	0x40000 /* we have BIG sectors only :-(		*/
-
-/*-----------------------------------------------------------------------
- * I2C/EEPROM Configuration
- */
-
-#define CFG_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
-#define CFG_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
-#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
-#define CFG_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
-#define CFG_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
-#define CFG_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
-#define CFG_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/
-
-#undef	CONFIG_USE_FRAM			/* Use FRAM instead of EEPROM	*/
-
-#ifdef CONFIG_USE_FRAM	/* use FRAM */
-#define CFG_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2
-#else			/* use EEPROM */
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
-#endif	/* CONFIG_USE_FRAM */
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-
-/* List of I2C addresses to be verified by POST */
-#ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
-				CFG_I2C_SYSMON_ADDR,	\
-				CFG_I2C_RTC_ADDR,	\
-				CFG_I2C_POWER_A_ADDR,	\
-				CFG_I2C_POWER_B_ADDR,	\
-				CFG_I2C_KEYBD_ADDR,	\
-				CFG_I2C_PICIO_ADDR,	\
-				CFG_I2C_EEPROM_ADDR,	\
-			}
-#else	/* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
-				CFG_I2C_SYSMON_ADDR,	\
-				CFG_I2C_RTC_ADDR,	\
-				CFG_I2C_POWER_A_ADDR,	\
-				CFG_I2C_POWER_B_ADDR,	\
-				CFG_I2C_KEYBD_ADDR,	\
-				CFG_I2C_PICIO_ADDR,	\
-				CFG_I2C_EEPROM_ADDR+0,	\
-				CFG_I2C_EEPROM_ADDR+1,	\
-				CFG_I2C_EEPROM_ADDR+2,	\
-				CFG_I2C_EEPROM_ADDR+3,	\
-				CFG_I2C_EEPROM_ADDR+4,	\
-				CFG_I2C_EEPROM_ADDR+5,	\
-				CFG_I2C_EEPROM_ADDR+6,	\
-				CFG_I2C_EEPROM_ADDR+7,	\
-			}
-#endif	/* CONFIG_USE_FRAM */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if 0 && defined(CONFIG_WATCHDOG)	/* LWMON uses external MAX706TESA WD */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-/* EARB, DBGC and DBPC are initialised by the HCW */
-/* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_GB5E)
-/*#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00405000 */
-#define CFG_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
-#define CFG_PLPRCR							\
-		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
-		)
-
-#define CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*13200000)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* 0x01800000 */
-#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
-			 SCCR_EBDF00 |	 SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
-			 SCCR_DFALCD01)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/* 0x00C3 => 0x0003 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR 0x0000
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0x50000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0x54000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0x5C000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-#define CONFIG_SUPPORT_VFAT		/* enable VFAT support */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x41000000	/* FLASH bank #1	*/
-
-/* used to re-map FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0xFF000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK)
-
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-/*
- * BR3/OR3: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM	0xF0000000	/* map 256 MB (>SDRAM_MAX_SIZE!) */
-#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB SDRAM */
-
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR5/OR5: Touch Panel
- *
- * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
- */
-#define TOUCHPNL_BASE		0x20000000
-#define TOUCHPNL_OR_AM		0xFFFF8000
-#define TOUCHPNL_TIMING		OR_SCY_0_CLK
-
-#define CFG_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-			 TOUCHPNL_TIMING )
-#define CFG_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define	CFG_MEMORY_75
-#undef	CFG_MEMORY_7E
-#undef	CFG_MEMORY_8E
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MPTPR	0x200
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CFG_MAMR_8COL	0x80802114
-#define CFG_MAMR_9COL	0x80904114
-
-/*
- * MAR setting for SDRAM
- */
-#define CFG_MAR		0x00000088
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
deleted file mode 100644
index 20287674fa..0000000000
--- a/include/configs/modnet50.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2004
- * IMMS, gGmbH <www.imms.de>
- * Thomas Elste <info@elste.org>
- *
- * Configuation settings for ModNET50 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
-#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#define CONFIG_NETARM                   /* it's a Netsiclicon NET+ARM */
-#undef  CONFIG_NETARM_NET40_REV2        /* it's a Net+40 Rev. 2 */
-#undef  CONFIG_NETARM_NET40_REV4	/* it's a Net+40 Rev. 4 */
-#define CONFIG_NETARM_NET50             /* it's a Net+50 */
-
-#define CONFIG_MODNET50		1	/* on an ModNET50 Board      */
-
-#undef CONFIG_USE_IRQ			/* don't need them anymore */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_NETARMETH 1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		38400
-
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_JFFS2))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.30.2
-#define CONFIG_SERVERIP         192.168.30.122
-#define CFG_ETH_PHY_ADDR        0x100
-#define CONFIG_CMDLINE_TAG      /* submit bootargs to kernel */
-
-/*#define CONFIG_BOOTDELAY	10*/
-/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
-#define CONFIG_BOOTCOMMAND	"bootm 0x10020000 0x100a0000"
-#define CONFIG_BOOTARGS    	"console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory	*/
-#define	CFG_PROMPT		"modnet50 # "	/* Monitor Command Prompt */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define	CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x00500000	/* default load address	*/
-
-#define	CFG_HZ			900		/* decrementer freq: 2 kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
-*/
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-#define PHYS_SDRAM_2		0x01000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2_SIZE	0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1		0x10000000 /* Flash Bank #1 */
-#define PHYS_FLASH_1_SIZE	0x00200000 /* 2 MB (one chip only, 16bit access) */
-
-#define PHYS_FLASH_2            0x10200001
-#define PHYS_FLASH_2_SIZE       0x00200000
-
-#define CONFIG_NETARM_EEPROM
-/* #ifdef CONFIG_NETARM_EEPROM */
-#define PHYS_NVRAM_1		0x20000000 /* EEPROM Bank #1 */
-#define PHYS_NVRAM_SIZE		0x00002000 /* 8 KB */
-/* #endif */
-
-#define PHYS_EXT_1		0x30000000 /* Extensions Bank #1 */
-#define PHYS_EXT_SIZE		0x01000000 /* 32 MB memory mapped I/O */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
-#define CFG_MAIN_SECT_SIZE      0x00010000  /* main size of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-/* environment settings */
-#define	CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_NOWHERE
-
-#define CFG_ENV_ADDR		0x1001C000 /* environment start address */
-#define CFG_ENV_SECT_SIZE       0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SIZE		0x4000	/* max size for environment */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00080000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=modnet50-0"
-#define MTDPARTS_DEFAULT	"mtdparts=modnet50-0:-@512k(jffs2)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
deleted file mode 100644
index 04f1f24080..0000000000
--- a/include/configs/mp2usb.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * 2004-2005 Gary Jennejohn <garyj@denx.de>
- *
- * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
- * ebenard@eukrea.com
- *
- * Configuration settings for the MP2USB board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
-#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
-
-#define AT91_SLOW_CLOCK		32768	/* slow clock */
-
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
-#define CONFIG_MP2USB		1	/* on an MP2USB Board		*/
-#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define USE_920T_MMU		1
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
-#define CFG_ATMEL_PLL_INIT_BUG	1
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
-/* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
-#define PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
-
-/* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3211295A /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000020 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_AT91C_BRGR_DIVISOR	33	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
-
-/*
- * Hardware drivers
- */
-
-/* define one of these to choose the DBGU, USART0  or USART1 as console */
-#define CONFIG_DBGU
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-
-#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
-
-#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
-
-#define CONFIG_USB_OHCI		1
-#define CONFIG_USB_KEYBOARD	1
-#define CONFIG_USB_STORAGE	1
-#define CONFIG_DOS_PARTITION	1
-#define CONFIG_AT91C_PQFP_UHPBUG 1
-
-#undef CONFIG_HARD_I2C
-
-#ifdef CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		0	/* not used */
-#define CFG_I2C_SLAVE		0	/* not used */
-#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
-#define CFG_I2C_RTC_ADDR	0x32
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW
-#endif
-/* still about 20 kB free with this defined */
-#define CFG_LONGHELP
-
-#define CONFIG_BOOTDELAY      3
-
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DATE	| \
-			CFG_CMD_DHCP 	| \
-			CFG_CMD_EEPROM	| \
-			CFG_CMD_I2C	| \
-			CFG_CMD_NFS	| \
-			CFG_CMD_SNTP	| \
-			CFG_CMD_MISC))
-#else
-#define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL	| \
-			CFG_CMD_DHCP 	| \
-			CFG_CMD_NFS	| \
-			CFG_CMD_SNTP	| \
-			CFG_CMD_USB      | \
-			CFG_CMD_CACHE)	& \
-		      ~(CFG_CMD_BDI | \
-			CFG_CMD_IMI | \
-			CFG_CMD_AUTOSCRIPT | \
-			CFG_CMD_FPGA | \
-			CFG_CMD_MISC | \
-			CFG_CMD_LOADS ))
-#define CONFIG_TIMESTAMP
-#endif
-#define CFG_LONGHELP
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM		0x20000000
-#define PHYS_SDRAM_SIZE		0x08000000 	/* 128 megs */
-
-#define CFG_MEMTEST_START	PHYS_SDRAM
-#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
-
-#define CONFIG_DRIVER_ETHER
-#define CONFIG_NET_RETRY_COUNT		20
-#undef CONFIG_AT91C_USE_RMII
-
-#define PHYS_FLASH_1			0x10000000
-#define PHYS_FLASH_SIZE			0x1000000  /* 16 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_FLASH_LOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CFG_FLASH_UNLOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CFG_FLASH_PROTECTION				/* "Real" (hardware) sectors protection */
-
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_OFFSET			0x20000		/* after u-boot.bin */
-#define CFG_ENV_ADDR			(CFG_FLASH_BASE+CFG_ENV_OFFSET)
-#define CFG_ENV_SIZE			0x20000
-
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
-
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
-
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		32		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-
-#define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
-#define LITTLEENDIAN            1       /* used by usb_ohci.c  */
-
-#ifndef __ASSEMBLY__
-/*-----------------------------------------------------------------------
- * Board specific extension for bd_info
- *
- * This structure is embedded in the global bd_info (bd_t) structure
- * and can be used by the board specific code (eg board/...)
- */
-
-struct bd_info_ext {
-	/* helper variable for board environment handling
-	 *
-	 * env_crc_valid == 0	 =>   uninitialised
-	 * env_crc_valid  > 0	 =>   environment crc in flash is valid
-	 * env_crc_valid  < 0	 =>   environment crc in flash is invalid
-	 */
-	int env_crc_valid;
-};
-#endif	/* __ASSEMBLY__ */
-
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
-						/* AT91C_TC_TIMER_DIV1_CLOCK */
-
-#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
-#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
-#undef CONFIG_SILENT_CONSOLE		/* enable silent startup	*/
-
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
deleted file mode 100644
index 9816be8dc4..0000000000
--- a/include/configs/mx1fs2.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright (C) 2004 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARM920T	   1	 /* this is an ARM920T CPU     */
-#define CONFIG_IMX	   1	 /* in a Motorola MC9328MXL Chip */
-#define CONFIG_MX1FS2	   1	 /* on a mx1fs2 board */
-#undef	CONFIG_USE_IRQ		 /* don't need use IRQ/FIQ    */
-
-/*
- * Select serial console configuration
- */
-#undef	_CONFIG_UART1 /* internal uart 1 */
-#define _CONFIG_UART2 /* internal uart 2 */
-#undef	_CONFIG_UART3 /* internal uart 3 */
-#undef	_CONFIG_UART4 /* internal uart 4 */
-#undef	CONFIG_SILENT_CONSOLE  /* use this to disable output */
-
-/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
- */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		 \
-				& ~CFG_CMD_LOADS	 \
-				& ~CFG_CMD_CONSOLE	 \
-				& ~CFG_CMD_AUTOSCRIPT	 \
-				& ~CFG_CMD_NET		 \
-				& ~CFG_CMD_PING		 \
-				& ~CFG_CMD_DHCP		 \
-				| CFG_CMD_JFFS2		 \
-				)
-
-#include <cmd_confdefs.h>
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- */
-#define CONFIG_BOOTDELAY   10
-#define CONFIG_BOOTARGS	   "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
-#define CONFIG_BOOTCOMMAND "bootm 10080000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CFG_LONGHELP				      /* undef saves memory  */
-#define CFG_PROMPT		"mx1fs2> "	      /* prompt string	     */
-#define CFG_CBSIZE		256		      /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS		16		      /* max command args    */
-#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
-
-#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
-#define CFG_MEMTEST_END		0x08F00000
-
-#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
-
-#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_BAUDRATE 115200
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
-#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
-#define	 CONFIG_INITRD_TAG	     1	   /* send initrd params	*/
-#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CFG_MALLOC_LEN	  (CFG_ENV_SIZE + (128<<10) )
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE	(120<<10)      /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack  */
-#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack  */
-#endif
-
-/* SDRAM Setup Values
- * 0x910a8300 Precharge Command CAS 3
- * 0x910a8200 Precharge Command CAS 2
- *
- * 0xa10a8300 AutoRefresh Command CAS 3
- * 0xa10a8200 Set AutoRefresh Command CAS 2
- */
-#define PRECHARGE_CMD 0x910a8300
-#define AUTOREFRESH_CMD 0xa10a8300
-
-#define BUS32BIT_VERSION
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS  1			     /* we have 1 bank of SDRAM */
-#define MX1FS2_SDRAM_1	      0x08000000	     /* SDRAM bank #1		*/
-#ifdef BUS32BIT_VERSION
-#define MX1FS2_SDRAM_1_SIZE  (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
-#else
-#define MX1FS2_SDRAM_1_SIZE  (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
-#endif
-/*
- * Flash Controller settings
- */
-
-#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT	256	/* number of sector in FLASH bank    */
-
-#ifdef BUS32BIT_VERSION
-#define MX1FS2_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
-#define MX1FS2_FLASH_INTERLEAVE 2	/* ... made of 2 chips */
-#define MX1FS2_FLASH_BANK_SIZE	0x02000000  /* size of one flash bank*/
-#define MX1FS2_FLASH_SECT_SIZE	0x00020000  /* size of erase sector */
-#else
-#define MX1FS2_FLASH_BUS_WIDTH	2	/* we use 16 bit FLASH memory...     */
-#define MX1FS2_FLASH_INTERLEAVE 1	/* ... made of 1 chip */
-#define MX1FS2_FLASH_BANK_SIZE	0x01000000  /* size of one flash bank*/
-#define MX1FS2_FLASH_SECT_SIZE	0x00010000  /* size of erase sector */
-#endif
-#define MX1FS2_FLASH_BASE	0x10000000  /* location of flash memory */
-#define MX1FS2_FLASH_UNLOCK	   1	   /* perform hw unlock first */
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef	CFG_FLASH_CFI
-
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
-
-#define CFG_FLASH_BASE		MX1FS2_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
- */
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-/*
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00050000
-*/
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=mx1fs2-0"
-
-#ifdef BUS32BIT_VERSION
-#define MTDPARTS_DEFAULT	"mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
-#else
-#define MTDPARTS_DEFAULT	"mtdparts=mx1fs2-0:-@320k(jffs2)"
-#endif
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CFG_MONITOR_BASE	0x10000000
-#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )   */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
-#define CFG_ENV_SIZE		0x20000
-
-#define	 CONFIG_ENV_OVERWRITE	1		/* env is not writable now   */
-
-/* Setup CS4 and CS5 */
-#define CFG_GIUS_A_VAL		0x0003fffe
-
-/*
- * CSxU_VAL:
- * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
- *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
- *
- * CSxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
- *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
- */
-
-#define CFG_CS0U_VAL 0x00008C00
-#define CFG_CS0L_VAL 0x22222601
-#define CFG_CS1U_VAL 0x00008C00
-#define CFG_CS1L_VAL 0x22222301
-#define CFG_CS4U_VAL 0x00008C00
-#define CFG_CS4L_VAL 0x22222301
-#define CFG_CS5U_VAL 0x00008C00
-#define CFG_CS5L_VAL 0x22222301
-
-/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
-   f_ref=16,777MHz
-
-   0x002a141f: 191,9944MHz
-   0x040b2007: 144MHz
-   0x042a141f: 96MHz
-   0x0811140d: 64MHz
-   0x040e200e: 150MHz
-   0x00321431: 200MHz
-
-   0x08001800: 64MHz mit 16er Quarz
-   0x04001800: 96MHz mit 16er Quarz
-   0x04002400: 144MHz mit 16er Quarz
-
-   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
-      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
-
-#define CFG_MPCTL0_VAL		0x07E723AD
-#define CFG_MPCTL1_VAL		0x00000040
-#define CFG_PCDR_VAL		0x00010005
-#define CFG_GPCR_VAL		0x00000FFB
-
-#define USE_16M_OSZI /* If you have one, you want to use it
-			The internal 32kHz oszillator jitters */
-#ifdef USE_16M_OSZI
-
-#define CFG_SPCTL0_VAL		0x04001401
-#define CFG_SPCTL1_VAL		0x0C000040
-#define CFG_CSCR_VAL		0x07030003
-#define CONFIG_SYS_CLK_FREQ	16780000
-#define CONFIG_SYSPLL_CLK_FREQ	16000000
-
-#else
-
-#define CFG_SPCTL0_VAL		0x07E716D1
-#define CFG_CSCR_VAL		0x06000003
-#define CONFIG_SYS_CLK_FREQ	16780000
-#define CONFIG_SYSPLL_CLK_FREQ	16780000
-
-#endif
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CFG_LOAD_ADDR		0x08400000
-
-#define CFG_FMCR_VAL		0x00000003 /* Reset Default */
-
-/* Bit[0:3] contain PERCLK1DIV for UART 1
-   0x000b00b ->b<- -> 192MHz/12=16MHz
-   0x000b00b ->8<- -> 144MHz/09=16MHz
-   0x000b00b ->3<- -> 64MHz/4=16MHz */
-
-#ifdef _CONFIG_UART1
-#define CONFIG_IMX_SERIAL1
-#elif defined _CONFIG_UART2
-#define CONFIG_IMX_SERIAL2
-#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
-#define CONFIG_IMX_SERIAL_NONE
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK		3686400
-#define CFG_NS16550_REG_SIZE	1
-#define CONFIG_CONS_INDEX	1
-#ifdef _CONFIG_UART3
-#define CFG_NS16550_COM1	0x15000000
-#elif defined _CONFIG_UART4
-#define CFG_NS16550_COM1	0x16000000
-#endif
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
deleted file mode 100644
index 697796a114..0000000000
--- a/include/configs/netstar.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
- *
- * Configuation settings for the TI OMAP NetStar board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/omap1510.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM925T	1		/* This is an arm925t CPU */
-#define CONFIG_OMAP	1		/* in a TI OMAP core */
-#define CONFIG_OMAP1510 1		/* which is in a 5910 */
-
-/* Input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
-#define CONFIG_XTAL_FREQ	12000000
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_MISC_INIT_R		/* There is nothing to really init */
-#define BOARD_LATE_INIT			/* but we flash the LEDs here */
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-#define CFG_DEVICE_NULLDEV		1	/* enable null device */
-#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
-
-/*
- * FLASH organization
- */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS	1
-#if (PHYS_SDRAM_1_SIZE == SZ_32M)
-/*#if 1*/
-#define CFG_FLASH_CFI			/* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER		/* Use the common driver */
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT	128
-#else
-#define PHYS_FLASH_1_SIZE	SZ_1M
-#define CFG_MAX_FLASH_SECT	19
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* in ticks */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ)
-#endif
-
-#define CFG_MONITOR_BASE	PHYS_FLASH_1
-#define CFG_MONITOR_LEN		SZ_256K
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH
-#define ENV_IS_SOLITARY
-#define CFG_ENV_ADDR		0x4000
-#define CFG_ENV_SIZE		SZ_8K
-#define CFG_ENV_SECT_SIZE	SZ_8K
-#define CFG_ENV_ADDR_REDUND	0x6000
-#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Size of malloc() pool
- */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-/* XXX #define CFG_MALLOC_LEN		(SZ_64K - CFG_GBL_DATA_SIZE)*/
-#define CFG_MALLOC_LEN		SZ_4M
-
-/*
- * The stack size is set up in start.S using the settings below
- */
-/* XXX #define CONFIG_STACKSIZE	SZ_8K	/XXX* regular stack */
-#define CONFIG_STACKSIZE	SZ_1M	/* regular stack */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE	0x04000300
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CFG_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT */
-
-/*
- * NAND flash
- */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE	0x04000000 + (2 << 23)
-
-/*
- * JFFS2 partitions (mtdparts command line support)
- */
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
-#define MTDPARTS_DEFAULT	"mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
-
-#if 0
-#define CONFIG_COMMANDS		(CFG_CMD_BDI    | \
-				 CFG_CMD_BOOTD  | \
-				 CFG_CMD_DHCP   | \
-				 CFG_CMD_ENV	| \
-				 CFG_CMD_FLASH  | \
-				 CFG_CMD_IMI    | \
-				 CFG_CMD_LOADB  | \
-				 CFG_CMD_NET    | \
-				 CFG_CMD_MEMORY | \
-				 CFG_CMD_PING   | \
-				 CFG_CMD_RUN)
-
-#else
-#define CONFIG_COMMANDS		(CFG_CMD_BDI    | \
-				 CFG_CMD_BOOTD  | \
-				 CFG_CMD_DHCP   | \
-				 CFG_CMD_ENV	| \
-				 CFG_CMD_FLASH  | \
-				 CFG_CMD_NAND	| \
-				 CFG_CMD_IMI    | \
-				 CFG_CMD_JFFS2	| \
-				 CFG_CMD_LOADB  | \
-				 CFG_CMD_NET    | \
-				 CFG_CMD_MEMORY | \
-				 CFG_CMD_PING   | \
-				 CFG_CMD_RUN)
-
-#define CONFIG_JFFS2_NAND	1	/* jffs2 on nand support */
-#endif
-
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-#define CONFIG_LOOPW
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
-#define CFG_AUTOLOAD		"n"		/* No autoload */
-#define CONFIG_BOOTCOMMAND	"run nboot"
-#define CONFIG_PREBOOT		"run setup"
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"setup=setenv bootargs console=ttyS0,$baudrate "	\
-		"$mtdparts\0"					\
-	"ospart=0\0"						\
-	"setpart="						\
-	"if test -n $swapos; then "				\
-		"if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
-		"setenv swapos; saveenv; "			\
-	"else "							\
-		"chpart nand0,$ospart; "			\
-	"fi\0"							\
-	"nfsargs=setenv bootargs $bootargs "			\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
-		"nfsroot=$rootpath root=/dev/nfs\0"		\
-	"flashargs=run setpart;setenv bootargs $bootargs "	\
-		"root=/dev/mtdblock$partition ro "		\
-		"rootfstype=jffs2\0"				\
-	"initrdargs=setenv bootargs $bootargs "			\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"iboot=bootp;run initrdargs;tftp;bootm\0"		\
-	"fboot=run flashargs;fsload /boot/uImage;bootm\0"	\
-	"nboot=bootp;run nfsargs;tftp;bootm\0"
-
-#if 0	/* feel free to disable for development */
-#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
-#define CONFIG_AUTOBOOT_PROMPT	"\nNetStar PBX - boot in %d sec...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR	"R"	/* 1st "password"	*/
-#define CONFIG_BOOT_RETRY_TIME	30
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CONFIG_AUTO_COMPLETE
-
-#define CFG_MEMTEST_START	PHYS_SDRAM_1
-#define CFG_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
-
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
- * This time is further subdivided by a local divisor.
- */
-#define CFG_TIMERBASE		OMAP1510_TIMER1_BASE
-#define CFG_PVT			7		/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
-#define OMAP5910_DPLL_DIV	1
-#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
-				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
-
-#define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
-#define OMAP5910_LCD_DIV	2	/* CKL/4 */
-#define OMAP5910_ARM_DIV	0	/* CKL/1 */
-#define OMAP5910_DSP_DIV	0	/* CKL/1 */
-#define OMAP5910_TC_DIV		1	/* CKL/2 */
-#define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
-#define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */
-
-#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
-#define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
-				 (OMAP5910_LCD_DIV << 2) |	\
-				 (OMAP5910_ARM_DIV << 4) |	\
-				 (OMAP5910_DSP_DIV << 6) |	\
-				 (OMAP5910_TC_DIV << 8) |	\
-				 (OMAP5910_DSP_MMU_DIV << 10) |	\
-				 (OMAP5910_ARM_TIM_SEL << 12))
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
deleted file mode 100644
index 0b1541d5c3..0000000000
--- a/include/configs/ns9750dev.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- *
- * Configuation settings for the NetSilicon NS9750 DevBoard
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
-#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */
-
-#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
-#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
-#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-/*@TODO #define CONFIG_STATUS_LED*/
-#define CONFIG_USE_IRQ
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
-					 * data */
-
-/*
- * Hardware drivers
- */
-#define CFG_NS9750_UART			1	/* use on-chip UART */
-#define CONFIG_DRIVER_NS9750_ETHERNET	1	/* use on-chip ethernet */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX          1 		/* Port B */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		38400
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#if 0 /* @TODO */
-#define CONFIG_COMMANDS \
-			(CONFIG_CMD_DFL	 | \
-			CFG_CMD_CACHE	 | \
-			/*CFG_CMD_NAND	 |*/ \
-			/*CFG_CMD_EEPROM |*/ \
-			/*CFG_CMD_I2C	 |*/ \
-			/*CFG_CMD_USB	 |*/ \
-			CFG_CMD_REGINFO  | \
-			CFG_CMD_DATE	 | \
-			CFG_CMD_ELF)
-#else
-#define CONFIG_COMMANDS \
-			(CONFIG_CMD_BDI | \
-			CFG_CMD_NET | \
-			CFG_CMD_PING	 | \
-			CFG_CMD_CONSOLE	 | \
-			CFG_CMD_LOADB	 | \
-			CFG_CMD_LOADS	 | \
-			CFG_CMD_MEMORY)
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
-
-#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.42.30
-#define CONFIG_SERVERIP		192.168.42.1
-
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
-
-#define	CFG_HZ			(CPU_CLK_FREQ/64)
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define NS9750_ETH_PHY_ADDRESS	(0x0000)
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-/* TODO */
-#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* @TODO*/
-#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-#endif
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
-
-/* @TODO */
-/*#define	CFG_ENV_IS_IN_FLASH	1*/
-#define CFG_ENV_IS_NOWHERE
-#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-#ifdef CONFIG_STATUS_LED
-
-extern void __led_init(led_id_t mask, int state);
-extern void __led_toggle(led_id_t mask);
-extern void __led_set(led_id_t mask, int state);
-
-#endif /* CONFIG_STATUS_LED */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
deleted file mode 100644
index 5c05a745db..0000000000
--- a/include/configs/o2dnt.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200
-#define CONFIG_O2DNT		1	/* ... on O2DNT board */
-
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CFG_XLB_PIPELINING	1
-
-#define CONFIG_NET_MULTI	1
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-
-#define ADD_PCI_CMD 		CFG_CMD_PCI
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				ADD_PCI_CMD	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#else
-#   error "TEXT_BASE must be 0xFF000000"
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/MPC5200/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if defined(CONFIG_MPC5200)
-/*
- * IPB Bus clocking configuration.
- */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
-
-#if defined(CFG_IPBSPEED_133)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
-#endif
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
-
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration:
- *
- * O2DNT board is equiped with Ramtron FRAM device FM24CL16
- * 16 Kib Ferroelectric Nonvolatile serial RAM memory
- * organized as 2048 x 8 bits and addressable as eight I2C devices
- * 0x50 ... 0x57 each 256 bytes in size
- *
- */
-#define CFG_I2C_FRAM
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-/*
- * There is no write delay with FRAM, write operations are performed at bus
- * speed. Thus, no status polling or write delay is needed.
- */
-/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70*/
-
-
-/*
- * Flash configuration
- */
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x01000000
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
-
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-/*
- * Environment settings
- */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x20000
-#define CFG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- */
-/*#define CFG_GPS_PORT_CONFIG	0x10002004 */
-#define CFG_GPS_PORT_CONFIG	0x00002006	/* no CAN */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-
-#ifdef CFG_PCISPEED_66
-/*
- * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
- */
-#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
-#else
-#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
-#endif
-
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
deleted file mode 100644
index 89e9164e03..0000000000
--- a/include/configs/ocotea.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
- * Adapted to current Das U-Boot source
- ***********************************************************************/
-
-
-/************************************************************************
- * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
-#define CONFIG_440GX		1	    /* Specifc GX support	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
-
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM  1
-#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
-
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
-
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *       supported for backward compatibility.
- */
-#if 1
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_NVRAM */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	64		    /* sectors per device   */
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	 /* Use SPD EEPROM for setup	 */
-#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=ocotea\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/ocotea/uImage\0"				\
-	"kernel_addr=fff00000\0"					\
-	"ramdisk_addr=fff10000\0"					\
-	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI	1
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR	2
-#define CONFIG_PHY2_ADDR	0x10
-#define CONFIG_PHY3_ADDR	0x18
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
deleted file mode 100644
index f28ede0967..0000000000
--- a/include/configs/omap1610inn.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP	1			/* in a TI OMAP core    */
-#define CONFIG_OMAP1610	1		/* which is in a 1610  */
-#define CONFIG_INNOVATOROMAP1610	1	/*  a Innovator Board  */
-#define CONFIG_MACH_OMAP_INNOVATOR	/* Select board mach-type */
-
-/* input clock of PLL */
-/* the OMAP1610 Innovator has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ	12000000
-
-#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-/*
-*/
-#define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart on helen */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1		/* we use SERIAL 1 on OMAP1610 Innovator */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE	115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#include <configs/omap1510.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
-				root=/dev/nfs rw nfsroot=157.87.82.48:\
-				/home/a0875451/mwd/myfs/target ip=dhcp"
-#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
-#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
-#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
-#define CONFIG_BOOTFILE	"uImage"	/* file to load */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP	/* undef to save memory     */
-#define CFG_PROMPT	"OMAP1610 Innovator # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args   */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
-#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR	0x10000000	/* default load address */
-
-/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
- * DPLL1. This time is further subdivided by a local divisor.
- */
-#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
-#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-
-#define PHYS_FLASH_1_BM1	0x00000000	/* Flash Bank #1 if booting from flash */
-#define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
-
-#ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
-
-#ifndef __ASSEMBLY__
-extern unsigned long omap_flash_base;		/* set in flash__init */
-#endif
-#define CFG_FLASH_BASE		omap_flash_base
-
-#elif defined(CONFIG_CS0_BOOT)
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0
-
-#else
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
-#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
-/* addr of environment */
-#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
-#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */
-
-#endif							/* __CONFIG_H */
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
deleted file mode 100644
index 58374616a1..0000000000
--- a/include/configs/omap2420h4.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the 242x TI H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
-#define CONFIG_OMAP              1    /* in a TI OMAP core */
-#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
-#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
-/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
-/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
-
-/* Clock config to target*/
-#define PRCM_CONFIG_II	1
-/* #define PRCM_CONFIG_III		1 */
-
-#include <asm/arch/omap2420.h>        /* get chip and board defs */
-
-/* On H4, NOR and NAND flash are mutual exclusive.
-   Define this if you want to use NAND
- */
-/*#define CFG_NAND_BOOT */
-
-#ifdef CONFIG_APTIX
-#define V_SCLK                   1500000
-#else
-#define V_SCLK                   12000000
-#endif
-
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ      V_SCLK
-
-#undef CONFIG_USE_IRQ                 /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG        1
-#define CONFIG_REVISION_TAG      1
-
-/*
- * Size of malloc() pool
- */
-#define CFG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
-#define CFG_MALLOC_LEN           (CFG_ENV_SIZE + SZ_128K)
-#define CFG_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-/*
- * SMC91c96 Etherent
- */
-#define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#ifdef CONFIG_APTIX
-#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
-#else
-#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
-#endif
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
-#define CFG_NS16550_COM1         OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1           1    /* UART1 on H4 */
-
-  /*
-   * I2C configuration
-   */
-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED          100000
-#define CFG_I2C_SLAVE          1
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX        1
-#define CONFIG_BAUDRATE          115200
-#define CFG_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
-
-#ifdef CFG_NAND_BOOT
-#define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
-#else
-#define CONFIG_COMMANDS          ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
-#endif
-#define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- *  Board NAND Info.
- */
-#define CFG_NAND_LEGACY
-#define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
-
-#define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
-#define SECTORSIZE          512
-
-#define ADDR_COLUMN         1
-#define ADDR_PAGE           2
-#define ADDR_COLUMN_PAGE    3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS     1
-#define NAND_MAX_CHIPS      1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
-#define NAND_NO_RB          1
-
-#define CFG_NAND_WP
-#define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-
-#define CONFIG_BOOTDELAY         3
-
-#ifdef NFS_BOOT_DEFAULTS
-#define CONFIG_BOOTARGS	         "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
-#else
-#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-#endif
-
-#define CONFIG_NETMASK           255.255.254.0
-#define CONFIG_IPADDR            128.247.77.90
-#define CONFIG_SERVERIP          128.247.77.158
-#define CONFIG_BOOTFILE          "uImage"
-
-/*
- * Miscellaneous configurable options
- */
-#ifdef CONFIG_APTIX
-#define V_PROMPT                 "OMAP2420 Aptix # "
-#else
-#define V_PROMPT                 "OMAP242x H4 # "
-#endif
-
-#define CFG_LONGHELP             /* undef to save memory */
-#define CFG_PROMPT               V_PROMPT
-#define CFG_CBSIZE               256  /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CFG_PBSIZE               (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS              16          /* max number of command args */
-#define CFG_BARGSIZE             CFG_CBSIZE  /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
-#define CFG_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
-
-#undef	CFG_CLKS_IN_HZ           /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
-
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#ifdef CONFIG_APTIX
-#define V_PVT                    3
-#else
-#define V_PVT                    7  /* use with 12MHz/128 */
-#endif
-
-#define CFG_TIMERBASE            OMAP2420_GPT2
-#define CFG_PVT                  V_PVT  /* 2^(pvt+1) */
-#define CFG_HZ	                 ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE         SZ_128K /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
-#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
-
-#define PHYS_FLASH_SECT_SIZE     SZ_128K
-#define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE_1        SZ_32M
-#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
-#define PHYS_FLASH_SIZE_2        SZ_32M
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_FLASH_BASE           PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
-#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
-
-#ifdef CFG_NAND_BOOT
-#define CFG_ENV_IS_IN_NAND	1
-#define CFG_ENV_OFFSET	0x80000	/* environment starts here  */
-#else
-#define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
-#define	CFG_ENV_IS_IN_FLASH      1
-#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
-#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
-#endif
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
-#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_JFFS2_MEM_NAND
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor1=omap2420-1"
-#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
-*/
-
-#endif							/* __CONFIG_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
deleted file mode 100644
index fda55cf06f..0000000000
--- a/include/configs/omap730p2.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * MPC Data Limited (http://www.mpc-data.co.uk)
- * Dave Peverley <dpeverley at mpc-data.co.uk>
- *
- * Configuation settings for the TI OMAP Perseus 2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
-#define CONFIG_OMAP730		   1	     /* which is in a 730  */
-#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
-
-/*
- * Input clock of PLL
- * The OMAP730 Perseus 2 has 13MHz input clock
- */
-
-#define CONFIG_SYS_CLK_FREQ	   13000000
-
-#undef CONFIG_USE_IRQ			     /* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
-#define CONFIG_SETUP_MEMORY_TAGS   1
-
-/*
- * Size of malloc() pool
- */
-
-#define CFG_MALLOC_LEN		   (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE	   0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	   (1)
-#define CFG_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
-						   * on perseus */
-
-/*
- * select serial console configuration
- */
-
-#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
-
-#define CONFIG_CONS_INDEX	   1
-#define CONFIG_BAUDRATE		   115200
-#define CFG_BAUDRATE_TABLE	   { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_COMMANDS		   (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK	   CONFIG_BOOTP_DEFAULT
-
-/*
- * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-
-#include <cmd_confdefs.h>
-#include <configs/omap730.h>
-#include <configs/h2_p2_dbg_board.h>
-
-#define CONFIG_BOOTDELAY	   3
-#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
-
-#define CONFIG_LOADADDR		   0x10000000
-
-#define CONFIG_ETHADDR
-#define CONFIG_NETMASK		   255.255.255.0
-#define CONFIG_IPADDR		   192.168.0.23
-#define CONFIG_SERVERIP		   192.150.0.100
-#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
-
-#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CFG_LONGHELP				       /* undef to save memory	   */
-#define CFG_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CFG_CBSIZE		   256		       /* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CFG_PBSIZE		   (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		   16		       /* max number of command args   */
-#define CFG_BARGSIZE		   CFG_CBSIZE	       /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START	   0x10000000	       /* memtest works on */
-#define CFG_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
-
-#undef CFG_CLKS_IN_HZ		     /* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		   0x10000000	       /* default load address */
-
-/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
- * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
- * local divisor.
- */
-
-#define CFG_TIMERBASE		   0xFFFEC500	       /* use timer 1 */
-#define CFG_PVT			   7		       /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			   ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-
-#define CONFIG_STACKSIZE	   (128*1024)	  /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	   (4*1024)	  /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	   (4*1024)	  /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
-
-#if defined(CONFIG_CS0_BOOT)
-#define PHYS_FLASH_1		   0x0C000000
-#elif defined(CONFIG_CS3_BOOT)
-#define PHYS_FLASH_1		   0x00000000
-#else
-#error Unknown Boot Chip-Select number
-#endif
-
-#define CFG_FLASH_BASE		   PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
-#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
-#define CFG_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
-/* addr of environment */
-#define CFG_ENV_ADDR		   (CFG_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH	   1
-#define CFG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
-#define CFG_ENV_OFFSET		   0x20000	  /* environment starts here  */
-
-#endif	  /* ! __CONFIG_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
deleted file mode 100644
index ed1893f574..0000000000
--- a/include/configs/pb1x00.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the dbau1x00 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
-#define CONFIG_PB1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
-
-#ifdef CONFIG_PB1000
-#define CONFIG_AU1000		1
-#else
-#ifdef CONFIG_PB1100
-#define CONFIG_AU1100		1
-#else
-#ifdef CONFIG_PB1500
-#define CONFIG_AU1500		1
-#else
-#error "No valid board set"
-#endif
-#endif
-#endif
-
-#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
-
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
-
-#define CONFIG_BAUDRATE		115200
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"panic=1\0"						\
-	"bootfile=/vmlinux.img\0"				\
-	"load=tftp 80500000 ${u-boot}\0"				\
-	""
-/* Boot from NFS root */
-#define CONFIG_BOOTCOMMAND	"bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"Pb1x00 # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-#define CFG_HZ			396000000      /* FIXME causes overflow in net.c */
-
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
-
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
-
-#define CFG_MEMTEST_START	0x80100000
-#undef CFG_MEMTEST_START
-#define CFG_MEMTEST_START       0x80200000
-#define CFG_MEMTEST_END		0x83800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_INIT_SP_OFFSET	0x4000000
-
-/* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH_2
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_NOWHERE	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xB0030000
-#define CFG_ENV_SIZE		0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS	2
-
-#define CONFIG_NET_MULTI
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-
-/*---USB -------------------------------------------*/
-#if 0
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#else
-#define ADD_USB_CMD             0
-#endif
-
-/*---ATA PCMCIA ------------------------------------*/
-#if 0
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CFG_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     8
-
-/* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
-
-/* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
-
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
-
-#define CONFIG_COMMANDS	\
-  (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
-   CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
-   CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD)
-#include <cmd_confdefs.h>
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
deleted file mode 100644
index 23bdfc8dfb..0000000000
--- a/include/configs/pcs440ep.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * pcs440ep.h - configuration for PCS440EP board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
-#define CONFIG_440EP		1	/* Specific PPC440EP support    */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
-#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_BOOT_BASE_ADDR      0xf0000000
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(8 << 10)
-#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK		/* no external clk used		*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
-/*define this if you want console on UART1*/
-#undef CONFIG_UART1_CONSOLE
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
-#undef CONFIG_DDR_ECC			/* don't use ECC			*/
-#define SPD_EEPROM_ADDRESS      {0x50}
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	(0xa4>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=pcs440ep\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/pcs440ep/uImage\0"				\
-	"kernel_addr=FFF00000\0"					\
-	"ramdisk_addr=FFF00000\0"					\
-	"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"		\
-	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-		"cp.b 100000 FFFA0000 60000\0"			        \
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI        1	/* required for netconsole      */
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR        2
-
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG			/* watchdog */
-#endif
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_USB	)
-
-
-#define CONFIG_SUPPORT_VFAT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1       /* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
-
-#define CFG_FLASH		FLASH_BASE0_PRELIM
-#define CFG_SRAM		0xF1000000
-#define CFG_FPGA		0xF2000000
-#define CFG_CF1			0xF0000000
-#define CFG_CF2			0xF0100000
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 1 (SRAM) initialization						*/
-#define CFG_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
-#define CFG_EBC_PB1CR		(CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
-
-/* Memory Bank 2 (FPGA) initialization						*/
-#define CFG_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
-#define CFG_EBC_PB2CR		(CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
-
-/* Memory Bank 3 (CompactFlash) initialization					*/
-#define CFG_EBC_PB3AP		0x080BD400
-#define CFG_EBC_PB3CR		(CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
-
-/* Memory Bank 4 (CompactFlash) initialization					*/
-#define CFG_EBC_PB4AP		0x080BD400
-#define CFG_EBC_PB4CR		(CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
-
-/*-----------------------------------------------------------------------
- * PPC440 GPIO Configuration
- */
-#define CFG_440_GPIO_TABLE { /*		GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6	EBC_CS_N(1)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7	EBC_CS_N(2)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8	EBC_CS_N(3)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9	EBC_CS_N(4)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10	EBC_CS_N(5)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11	EBC_BUS_ERR			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12	ZII_p0Rxd(0)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13	ZII_p0Rxd(1)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14	ZII_p0Rxd(2)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15	ZII_p0Rxd(3)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16	ZII_p0Txd(0)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17	ZII_p0Txd(1)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18	ZII_p0Txd(2)			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19	ZII_p0Txd(3)			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20	ZII_p0Rx_er			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21	ZII_p0Rx_dv			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22	ZII_p0RxCrs			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23	ZII_p0Tx_er			*/	\
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24	ZII_p0Tx_en			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25	ZII_p0Col			*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26			USB2D_RXVALID	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28			USB2D_TXVALID	*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
-{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
-},											\
-{											\
-/* GPIO Core 1 */									\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32	USB2D_OPMODE0			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33	USB2D_OPMODE1			*/	\
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37	UART0_RTS_N			*/	\
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40	UIC_IRQ(0)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41	UIC_IRQ(1)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42	UIC_IRQ(2)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43	UIC_IRQ(3)			*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
-{ GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
deleted file mode 100644
index 73aa3a8825..0000000000
--- a/include/configs/pcu_e.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Workaround for layout bug on prototype board
- */
-#define	PCU_E_WITH_SWAPPED_CS	1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
-#define CONFIG_MPC860T		1
-#define CONFIG_PCU_E		1	/* ...on a PCU E board		*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-
-#define CONFIG_BAUDRATE		9600
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define	CONFIG_SPI			/* enable SPI driver		*/
-#define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CFG_SPI_INIT_OFFSET		0xB00
-
-#define CONFIG_COMMANDS		(	CONFIG_CMD_DFL	| \
-					CFG_CMD_BSP	| \
-					CFG_CMD_DATE	| \
-					CFG_CMD_DHCP	| \
-					CFG_CMD_EEPROM	| \
-					CFG_CMD_NFS	| \
-					CFG_CMD_SNTP	)
-
-#define CONFIG_BOOTP_MASK \
-    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
-
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
-
-/* Ethernet hardware configuration done using port pins */
-#define CFG_PB_ETH_RESET	0x00000020		/* PB 26	*/
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_PA_ETH_MDDIS	0x4000			/* PA  1	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/
-#define CFG_PB_ETH_CFG1		0x00000400		/* PB 21	*/
-#define CFG_PB_ETH_CFG2		0x00000200		/* PB 22	*/
-#define CFG_PB_ETH_CFG3		0x00000100		/* PB 23	*/
-#else /* XXX */
-#define CFG_PB_ETH_MDDIS	0x00000010		/* PB 27	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000100		/* PB 23	*/
-#define CFG_PB_ETH_CFG1		0x00000200		/* PB 22	*/
-#define CFG_PB_ETH_CFG2		0x00000400		/* PB 21	*/
-#define CFG_PB_ETH_CFG3		0x00000800		/* PB 20	*/
-#endif /* XXX */
-
-/* Ethernet settings:
- * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CFG_ETH_MDDIS_VALUE	0
-#define CFG_ETH_CFG1_VALUE	1
-#define CFG_ETH_CFG2_VALUE	1
-#define CFG_ETH_CFG3_VALUE	1
-
-/* PUMA configuration */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_PB_PUMA_PROG	0x00000010		/* PB 27	*/
-#else /* XXX */
-#define CFG_PA_PUMA_PROG	0x4000			/* PA  1	*/
-#endif /* XXX */
-#define CFG_PC_PUMA_DONE	0x0008			/* PC 12	*/
-#define CFG_PC_PUMA_INIT	0x0004			/* PC 13	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFE000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define	CFG_RESET_ADDRESS	0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-/* this is an ugly hack needed because of the silly non-constant address map */
-#define CFG_FLASH_BASE		(0-flash_info[0].size-flash_info[1].size)
-
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	160	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#if 0
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment 		*/
-#define CFG_ENV_ADDR	    0xFFFFE000	/* Address    of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x2000	/* use the top-most 8k boot sector	*/
-#define	CFG_ENV_IS_EMBEDDED	1	/* short-cut compile-time test		*/
-#else
-/* Final version: environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0
-#define CFG_I2C_EEPROM_ADDR_LEN	2
-#define CFG_ENV_OFFSET		1024
-#define CFG_ENV_SIZE		1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * External Arbitration max. priority (7),
- * Debug pins configuration '11',
- * Asynchronous external master enable.
- */
-/* => 0x70600200 */
-#define CFG_SIUMCR	(SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00004080 */
-#define	CFG_PLPRCR_MF	0	/* (0+1) * 50 = 50 MHz Clock */
-#define CFG_PLPRCR							\
-		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
-			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
-			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
-		)
-
-#define	CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*50000000)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* 0x01800000 */
-#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
-			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
-			 SCCR_EBDF00 |   SCCR_DFSYNC00 |	\
-			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
-			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
-			 SCCR_DFALCD01)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- *
- * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
- *
- * Don't expect the "date" command to work without a 32kHz clock input!
- */
-/* 0x00C3 => 0x0003 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR 0x0000
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define FLASH_BASE6_PRELIM	0xFF000000	/* FLASH bank #1	*/
-#else /* XXX */
-#define FLASH_BASE1_PRELIM	0xFF000000	/* FLASH bank #1	*/
-#endif /* XXX */
-
-/*
- * used to re-map FLASH: restrict access enough but not too much to
- * meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1			*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK | OR_EHTR)
-
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_OR6_REMAP	CFG_OR0_REMAP
-#define CFG_OR6_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR6_PRELIM	((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else /* XXX */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#endif /* XXX */
-
-/*
- * BR2/OR2: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define SDRAM_BASE5_PRELIM	0x00000000	/* SDRAM bank */
-#else /* XXX */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank */
-#endif /* XXX */
-#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map 128 MB (>SDRAM_MAX_SIZE!) */
-#define SDRAM_TIMING		OR_CSNT_SAM	/* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_OR5_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR5_PRELIM	((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* XXX */
-#define CFG_OR2_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#endif /* XXX */
-
-/*
- * BR3/OR3: CAN Controller
- *	BR3: 0x10000401		OR3: 0xffff818a
- */
-#define CAN_CTRLR_BASE		0x10000000	/* CAN Controller */
-#define CAN_CTRLR_OR_AM		0xFFFF8000	/* 32 kB */
-#define CAN_CTRLR_TIMING	(OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR4_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR4_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#else /* XXX */
-#define CFG_BR3_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR3_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#endif /* XXX */
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- *	BR4: 0x10100801		OR4: 0xffff8530
- * - "load" mode (chip select on UPM B):
- *	BR4: 0x101008c1		OR4: 0xffff8630
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE		0x10100000	/* PUMA Config */
-#define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */
-#define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_3_CLK)
-#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_3_CLK)
-
-#define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \
-					BR_PS_16 | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD	(PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR3_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR3_PRELIM		PUMA_CONF_OR_READ
-#else /* XXX */
-#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
-#endif /* XXX */
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- *	BR5: 0x10200401		OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE		0x10200000	/* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */
-#define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR2_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#else /* XXX */
-#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- *	BR6: 0x10600801		OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE		0x10600000	/* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */
-#define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR1_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR1_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#else /* XXX */
-#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR7/OR7: PUMA: external Flash
- *	BR7: 0x10a00801		OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE		0x10A00000	/* PUMA external Flash */
-#define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
-#define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MPTPR	0x0200
-
-/*
- * MAMR settings for SDRAM
- * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
- *		MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
- * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
- */
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	0x30	/* = 48 */
-
-#define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
-			  MAMR_AMA_TYPE_1	| \
-			  MAMR_G0CLA_A10	| \
-			  MAMR_RLFA_1X		| \
-			  MAMR_WLFA_1X		| \
-			  MAMR_TLFA_8X		)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
deleted file mode 100644
index ba6b113d8c..0000000000
--- a/include/configs/pdnb3.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Configuation settings for the PDNB3 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IXP425		1       /* This is an IXP425 CPU	*/
-#define CONFIG_PDNB3		1       /* on an PDNB3 board		*/
-
-#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
-#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
-
-/*
- * Ethernet
- */
-#define CONFIG_IXP4XX_NPE	1	/* include IXP4xx NPE support	*/
-#define CONFIG_NET_MULTI	1
-#define	CONFIG_PHY_ADDR		16	/* NPE0 PHY address		*/
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	18	/* NPE1 PHY address		*/
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
-
-/*
- * Misc configuration options
- */
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-
-#define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
-#define CFG_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(1 << 20)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE         115200
-#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_PING)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
-#define CFG_LOAD_ADDR           0x00010000      /* default load address */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/***************************************************************
- * Platform/Board specific defines start here.
- ***************************************************************/
-
-/*-----------------------------------------------------------------------
- * Default configuration (environment varibles...)
- *----------------------------------------------------------------------*/
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=pdnb3\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} "		\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} "	\
-	"mtdparts=${mtdparts}\0"					\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/buildroot\0"					\
-	"bootfile=/tftpboot/netbox/uImage\0"				\
-	"kernel_addr=50080000\0"					\
-	"ramdisk_addr=50200000\0"					\
-	"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0"		\
-	"update=protect off 50000000 5007dfff;era 50000000 5007dfff;"	\
-		"cp.b 100000 50000000 ${filesize};"			\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	"ipaddr=10.0.0.233\0"						\
-	"serverip=10.0.0.152\0"						\
-	"netmask=255.255.0.0\0"					\
-	"ethaddr=c6:6f:13:36:f3:81\0"					\
-	"eth1addr=c6:6f:13:36:f3:82\0"					\
-	"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env),"		\
-	"4k@508k(renv)\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
-
-#define CFG_FLASH_BASE          0x50000000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
-
-/*
- * Expansion bus settings
- */
-#define CFG_EXP_CS0		0x94913C43	/* 8bit, max size		*/
-#define CFG_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
-
-/*
- * SDRAM settings
- */
-#define CFG_SDR_CONFIG		0x18
-#define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT 	0x81a
-
-/*
- * FLASH and environment organization
- */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-#define CFG_ENV_SECT_SIZE	0x1000 	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-/*
- * NAND-FLASH stuff
- */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		0x51000000	/* NAND FLASH Base Address	*/
-
-/*
- * GPIO settings
- */
-
-/* FPGA program pin configuration */
-#define CFG_GPIO_PRG		12		/* FPGA program pin (cpu output)*/
-#define CFG_GPIO_CLK		10		/* FPGA clk pin (cpu output)    */
-#define CFG_GPIO_DATA		14		/* FPGA data pin (cpu output)   */
-#define CFG_GPIO_INIT		13		/* FPGA init pin (cpu input)    */
-#define CFG_GPIO_DONE		11		/* FPGA done pin (cpu input)    */
-
-/* other GPIO's */
-#define CFG_GPIO_RESTORE_INT	0
-#define CFG_GPIO_RESTART_INT	1
-#define CFG_GPIO_SYS_RUNNING	2
-#define CFG_GPIO_PCI_INTA	3
-#define CFG_GPIO_PCI_INTB	4
-#define CFG_GPIO_I2C_SCL	6
-#define CFG_GPIO_I2C_SDA	7
-#define CFG_GPIO_FPGA_RESET	9
-#define CFG_GPIO_CLK_33M	15
-
-/*
- * I2C stuff
- */
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-
-#define CFG_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		(1 << CFG_GPIO_I2C_SCL)
-#define PB_SDA		(1 << CFG_GPIO_I2C_SDA)
-
-#define I2C_INIT	GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL)
-#define I2C_ACTIVE	GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA)
-#define I2C_TRISTATE	GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA)
-#define I2C_READ	((*IXP425_GPIO_GPINR & PB_SDA) != 0)
-#define I2C_SDA(bit)	if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA);	\
-	                else     GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA)
-#define I2C_SCL(bit)	if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL);	\
-			else     GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL)
-#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
-
-/*
- * I2C RTC
- */
-#define CONFIG_RTC_M41T11	1
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
-
-/*
- * Spartan3 FPGA configuration support
- */
-#define CFG_FPGA_MAX_SIZE	700*1024	/* 700kByte for XC3S500E	*/
-
-#define CFG_FPGA_PRG	(1 << CFG_GPIO_PRG)	/* FPGA program pin (cpu output)*/
-#define CFG_FPGA_CLK	(1 << CFG_GPIO_CLK)	/* FPGA clk pin (cpu output)    */
-#define CFG_FPGA_DATA	(1 << CFG_GPIO_DATA)	/* FPGA data pin (cpu output)   */
-#define CFG_FPGA_INIT	(1 << CFG_GPIO_INIT)	/* FPGA init pin (cpu input)    */
-#define CFG_FPGA_DONE	(1 << CFG_GPIO_DONE)	/* FPGA done pin (cpu input)    */
-
-/*
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
deleted file mode 100644
index fefdb3cca0..0000000000
--- a/include/configs/pf5200.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_ICECUBE		1	/* ... on IceCube board */
-#define CONFIG_PF5200		1	/* ... on PF5200  board */
-#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
-
-#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
-
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#if 0				/* test-only */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#else
-#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
-#endif
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_MII		1
-#if 0				/* test-only !!! */
-#define CONFIG_NET_MULTI	1
-#define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
-#define CONFIG_NS8382X		1
-#endif
-
-#define ADD_PCI_CMD		CFG_CMD_PCI
-
-#else				/* MPC5100 */
-
-#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
-
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
-#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD		0
-#endif
-
-/*
- * Supported commands
- */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
-				 CFG_CMD_EEPROM	| \
-				 CFG_CMD_FAT	| \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_IDE	| \
-				 CFG_CMD_BSP	| \
-				 CFG_CMD_ELF	| \
-				 ADD_PCI_CMD	  )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
-#endif
-#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT08	1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Welcome to ParaFinder pf5200;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=eth0\0" \
-	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
-	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
-	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
-	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
-	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
-	"loadaddr=01000000\0" \
-	"serverip=192.168.2.99\0" \
-	"gatewayip=10.0.0.79\0" \
-	"user=mu\0" \
-	"target=pf5200.esd\0" \
-	"script=pf5200.bat\0" \
-	"image=/tftpboot/vxWorks_pf5200\0" \
-	"ipaddr=10.0.13.196\0" \
-	"netmask=255.255.0.0\0" \
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
-
-#if defined(CONFIG_MPC5200)
-/*
- * IPB Bus clocking configuration.
- */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
-#endif
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-
-#define CFG_I2C_SPEED		86000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1
-/*
- * Flash configuration
- */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	512
-
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-/*
- * Environment settings
- */
-#if 1				/* test-only */
-#define CFG_ENV_IS_IN_FLASH	0
-#define CFG_ENV_SIZE		0x10000
-#define CFG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_OVERWRITE	1
-#else
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
-				   /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE	1
-#endif
-
-/*
- * Memory map
- */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
-#endif
-
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_UDP_CHECKSUM	1
-
-/*
- * GPIO configuration
- */
-#define CFG_GPS_PORT_CONFIG	0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP		/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
-
-/*
- * Various low-level settings
- */
-#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
-#else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
-#endif
-
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004DD00
-
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-
-#define CFG_CS1_START		0xfd000000
-#define CFG_CS1_SIZE		0x00010000
-#define CFG_CS1_CFG		0x10101410
-
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-
-#define CFG_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
-
-#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
-#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
-
-/* CPLD program pin configuration */
-#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
-#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
-#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
-
-#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
-#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
-#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
-
-#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET	0x00000000
-#define JTAG_GPIO_CFG_RESET	0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
-#define JTAG_GPIO_TDI_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
-#define JTAG_GPIO_TDO_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET	0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
deleted file mode 100644
index a6c23712b5..0000000000
--- a/include/configs/pleb2.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuration settings for the PLEB 2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
-#define CONFIG_PLEB2		1	/* on an PLEB2 Board	    */
-#undef CONFIG_LCD
-#undef CONFIG_MMC
-#define BOARD_LATE_INIT		1
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-/* None - PLEB 2 doesn't have any of this.
-   #define CONFIG_DRIVER_LAN91C96
-   #define CONFIG_LAN91C96_BASE 0x0C000000 */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_NET)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.0.21
-#define CONFIG_SERVERIP		192.168.0.250
-#define CONFIG_BOOTCOMMAND	"bootm 40000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
-
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
-
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x00800000 /* 4 MB */
-
-/* Not entirely sure about this - DS/CHC */
-#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE	0x00010000 /* 64 KB sectors (x2) */
-
-#define CFG_DRAM_BASE		PHYS_SDRAM_1
-#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-
-/*
- * GPIO settings
- */
-#define CFG_GPSR0_VAL		0x00000000  /* Don't set anything */
-#define CFG_GPSR1_VAL		0x00000080
-#define CFG_GPSR2_VAL		0x00000000
-
-#define CFG_GPCR0_VAL		0x00000000  /* Don't clear anything */
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-
-#define CFG_GPDR0_VAL		0x00000000
-#define CFG_GPDR1_VAL		0x000007C3
-#define CFG_GPDR2_VAL		0x00000000
-
-/* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL	    0x00000000
-#define CFG_GRER1_VAL	    0x00000000
-#define CFG_GRER2_VAL	    0x00000000
-#define CFG_GFER0_VAL	    0x00000000
-#define CFG_GFER1_VAL	    0x00000000
-#define CFG_GFER2_VAL	    0x00000000
-
-#define CFG_GAFR0_L_VAL		0x00000000
-#define CFG_GAFR0_U_VAL		0x00000000
-#define CFG_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
-#define CFG_GAFR1_U_VAL		0x00000000
-#define CFG_GAFR2_L_VAL		0x00000000
-#define CFG_GAFR2_U_VAL		0x00000000
-
-#define CFG_PSSR_VAL		0x20
-#define CFG_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CFG_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
-#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
-#define CFG_MSC1_VAL		0x00000000
-#define CFG_MSC2_VAL		0x00000000
-
-#define CFG_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
-					      tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
-
-#define CFG_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
-					   /* bits set in lowlevel_init.S	*/
-#define CFG_MDMRS_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000  /* Hangover from Lubbock.
-					       Needs calculating. (DS/CHC) */
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-/* FIXME */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-/* Flash protection */
-#define CFG_FLASH_PROTECTION	1
-
-/* FIXME */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x3C000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment */
-#define CFG_ENV_SECT_SIZE	0x20000
-
-/* Option added to get around byte ordering issues in the flash driver */
-#define CFG_LITTLE_ENDIAN	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
deleted file mode 100644
index 072b9dd5b4..0000000000
--- a/include/configs/ppmc7xx.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * ppmc7xx.h
- * ---------
- *
- * Wind River PPMC 7xx/74xx board configuration file.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPMC7XX
-
-
-/*===================================================================
- *
- * User configurable settings - Modify to your preference
- *
- *===================================================================
- */
-
-/*
- * Debug
- *
- * DEBUG			- Define this is you want extra debug info
- * GTREGREAD			- Required to build with debug
- * do_bdinfo			- Required to build with debug
- */
-
-#undef	DEBUG
-#define	GTREGREAD(x)			0xFFFFFFFF
-#define	do_bdinfo(a,b,c,d)
-
-
-/*
- * CPU type
- *
- * CONFIG_7xx			- We have a 750 or 755 CPU
- * CONFIG_74xx			- We have a 7400 CPU
- * CONFIG_ALTIVEC		- We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK		- System bus clock in Hz
- */
-
-#define	CONFIG_7xx
-#undef	CONFIG_74xx
-#undef	CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK			66000000
-
-
-/*
- * Monitor configuration
- *
- * CONFIG_COMMANDS		- List of command sets to include in shell
- *
- * The following command sets have been tested and known to work:
- *
- * CFG_CMD_CACHE		- Cache control commands
- * CFG_CMD_MEMORY		- Memory display, change and test commands
- * CFG_CMD_FLASH		- Erase and program flash
- * CFG_CMD_ENV			- Environment commands
- * CFG_CMD_RUN			- Run commands stored in env vars
- * CFG_CMD_ELF			- Load ELF files
- * CFG_CMD_NET			- Networking/file download commands
- * CFG_CMD_PING			- ICMP Echo Request command
- * CFG_CMD_PCI			- PCI Bus scanning command
- */
-
-#define CONFIG_COMMANDS		( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) |	\
-						   CFG_CMD_FLASH |	\
-						   CFG_CMD_ENV |	\
-						   CFG_CMD_RUN |	\
-						   CFG_CMD_ELF |	\
-						   CFG_CMD_NET |	\
-						   CFG_CMD_PING |	\
-						   CFG_CMD_PCI)
-
-
-/*
- * Serial configuration
- *
- * CONFIG_CONS_INDEX		- Serial console port number (COM1)
- * CONFIG_BAUDRATE			- Serial speed
- */
-
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			9600
-
-
-/*
- * PCI config
- *
- * CONFIG_PCI				- Enable PCI bus
- * CONFIG_PCI_PNP			- Enable Plug & Play support
- * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
- */
-
-#define	CONFIG_PCI
-#define	CONFIG_PCI_PNP
-#undef	CONFIG_PCI_SCAN_SHOW
-
-
-/*
- * Network config
- *
- * CONFIG_NET_MULTI			- Support for multiple network interfaces
- * CONFIG_EEPRO100			- Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
- */
-
-#define	CONFIG_NET_MULTI
-#define	CONFIG_EEPRO100
-#define	CONFIG_EEPRO100_SROM_WRITE
-
-
-/*
- * Enable extra init functions
- *
- * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
- * CONFIG_MISC_INIT_R		- Call post relocation init functions
- */
-
-#undef	CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
-
-/*
- * Boot config
- *
- * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY			- How long to wait before auto-boot (in sec)
- */
-
-#define CONFIG_BOOTCOMMAND		\
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
-	"bootm"
-#define CONFIG_BOOTDELAY		5
-
-
-/*===================================================================
- *
- * Board configuration settings - You should not need to modify these
- *
- *===================================================================
- */
-
-
-#include <cmd_confdefs.h>
-
-
-/*
- * Memory map
- *
- * This board runs in a standard CHRP (Map-B) configuration.
- *
- *	Type		Start		End			Size	Width	Chip Sel
- *	----------- ----------- ----------- ------- ------- --------
- *	SDRAM		0x00000000	0x04000000	64MB	64b		SDRAMCS0
- *	User LED's	0x78000000						RCS3
- *	UART		0x7C000000						RCS2
- *	Mailbox		0xFF000000						RCS1
- *	Flash		0xFFC00000	0xFFFFFFFF	4MB	64b		RCS0
- *
- * Flash sectors are laid out as follows.
- *
- *	Sector	Start		End			Size	Comments
- *	------- ----------- ----------- ------- -----------
- *	 0		0xFFC00000	0xFFC3FFFF	256KB
- *   1		0xFFC40000	0xFFC7FFFF	256KB
- *	 2		0xFFC80000	0xFFCBFFFF	256KB
- *	 3		0xFFCC0000	0xFFCFFFFF	256KB
- *	 4		0xFFD00000	0xFFD3FFFF	256KB
- *	 5		0xFFD40000	0xFFD7FFFF	256KB
- *	 6		0xFFD80000	0xFFDBFFFF	256KB
- *	 7		0xFFDC0000	0xFFDFFFFF	256KB
- *   8		0xFFE00000	0xFFE3FFFF	256KB
- *	 9		0xFFE40000	0xFFE7FFFF	256KB
- *  10		0xFFE80000	0xFFEBFFFF	256KB
- *  11		0xFFEC0000	0xFFEFFFFF	256KB
- *  12		0xFFF00000	0xFFF3FFFF	256KB	U-Boot code here
- *  13		0xFFF40000	0xFFF7FFFF	256KB
- *  14		0xFFF80000	0xFFFBFFFF	256KB
- *  15		0xFFFC0000	0xFFFDFFFF	128KB
- *  16		0xFFFE0000	0xFFFE7FFF	 32KB	U-Boot env vars here
- *  17		0xFFFE8000	0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
- *  18		0xFFFF0000	0xFFFFFFFF	 64KB
- */
-
-
-/*
- * SDRAM config - see memory map details above.
- *
- * CFG_SDRAM_BASE			- Start address of SDRAM, this _must_ be zero!
- * CFG_SDRAM_SIZE			- Total size of contiguous SDRAM bank(s)
- */
-
-#define CFG_SDRAM_BASE			0x00000000
-#define CFG_SDRAM_SIZE			0x04000000
-
-
-/*
- * Flash config - see memory map details above.
- *
- * CFG_FLASH_BASE			- Start address of flash memory
- * CFG_FLASH_SIZE			- Total size of contiguous flash mem
- * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
- * CFG_FLASH_WRITE_TOUT		- Write timeout in ms
- * CFG_MAX_FLASH_BANKS		- Number of banks of flash on board
- * CFG_MAX_FLASH_SECT		- Number of sectors in a bank
- */
-
-#define CFG_FLASH_BASE			0xFFC00000
-#define CFG_FLASH_SIZE			0x00400000
-#define CFG_FLASH_ERASE_TOUT	250000
-#define CFG_FLASH_WRITE_TOUT	5000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		19
-
-
-/*
- * Monitor config - see memory map details above
- *
- * CFG_MONITOR_BASE			- Base address of monitor code
- * CFG_MALLOC_LEN			- Size of malloc pool (128KB)
- */
-
-#define CFG_MONITOR_BASE		TEXT_BASE
-#define CFG_MALLOC_LEN			0x20000
-
-
-/*
- * Command shell settings
- *
- * CFG_BARGSIZE			- Boot Argument buffer size
- * CFG_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
- * CFG_CBSIZE			- Console Buffer (input) size
- * CFG_LOAD_ADDR		- Default load address
- * CFG_LONGHELP			- Provide more detailed help
- * CFG_MAXARGS			- Number of args accepted by monitor commands
- * CFG_MEMTEST_START		- Start address of test to run on RAM
- * CFG_MEMTEST_END		- End address of RAM test
- * CFG_PBSIZE			- Print Buffer (output) size
- * CFG_PROMPT			- Prompt string
- */
-
-#define CFG_BARGSIZE			1024
-#define CFG_BOOTMAPSZ			0x800000
-#define CFG_CBSIZE			1024
-#define CFG_LOAD_ADDR			0x100000
-#define CFG_LONGHELP
-#define CFG_MAXARGS			16
-#define CFG_MEMTEST_START		0x00040000
-#define CFG_MEMTEST_END			0x00040100
-#define CFG_PBSIZE			1024
-#define CFG_PROMPT			"=> "
-
-
-/*
- * Environment config - see memory map details above
- *
- * CFG_ENV_IS_IN_FLASH		- The env variables are stored in flash
- * CFG_ENV_ADDR			- Address of the sector containing env vars
- * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
- * CFG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
- */
-
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_ADDR			0xFFFE0000
-#define CFG_ENV_SIZE			0x1000
-#define CFG_ENV_ADDR_REDUND		0xFFFE8000
-#define CFG_ENV_SIZE_REDUND		0x1000
-#define CFG_ENV_SECT_SIZE		0x8000
-
-
-/*
- * Initial RAM config
- *
- * Since the main system RAM is initialised very early, we place the INIT_RAM
- * in the main system RAM just above the exception vectors. The contents are
- * copied to top of RAM by the init code.
- *
- * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
- * CFG_INIT_RAM_END			- Size of Init RAM
- * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
- * CFG_GBL_DATA_OFFSET		- Start of global data, top of stack
- */
-
-#define CFG_INIT_RAM_ADDR		(CFG_SDRAM_BASE + 0x4000)
-#define CFG_INIT_RAM_END		0x4000
-#define CFG_GBL_DATA_SIZE		128
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-
-/*
- * Initial BAT config
- *
- * BAT0	- System SDRAM
- * BAT1 - LED's and Serial Port
- * BAT2 - PCI Memory
- * BAT3 - PCI I/O including Flash Memory
- */
-
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT0L
-#define CFG_DBAT0U CFG_IBAT0U
-
-#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-
-/*
- * Cache config
- *
- * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
- * CFG_L2					- L2 cache enabled if defined
- * L2_INIT					- L2 cache init flags
- * L2_ENABLE				- L2 cache enable flags
- */
-
-#define CFG_CACHELINE_SIZE		32
-#undef	CFG_L2
-#define L2_INIT					0
-#define L2_ENABLE				0
-
-
-/*
- * Clocks config
- *
- * CFG_BUS_HZ				- Bus clock frequency in Hz
- * CFG_BUS_CLK				- As above (?)
- * CFG_HZ					- Decrementer freq in Hz
- */
-
-#define CFG_BUS_HZ				CONFIG_BUS_CLK
-#define CFG_BUS_CLK				CONFIG_BUS_CLK
-#define CFG_HZ					1000
-
-
-/*
- * Serial port config
- *
- * CFG_BAUDRATE_TABLE		- List of valid baud rates
- * CFG_NS16550				- Include the NS16550 driver
- * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
- * CFG_NS16550_CLK			- Frequency of reference clock
- * CFG_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
- * CFG_NS16550_COM1			- Base address of 1st serial port
- */
-
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK			3686400
-#define CFG_NS16550_REG_SIZE	-8
-#define CFG_NS16550_COM1		0x7C000000
-
-
-/*
- * PCI Config - Address Map B (CHRP)
- */
-
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7D000000
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xFD000000
-#define CFG_ISA_MEM_SIZE        0x01000000
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xFE800000
-#define CFG_PCI_IO_SIZE         0x00400000
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xFE000000
-#define CFG_ISA_IO_SIZE         0x00800000
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
-
-
-/*
- * Extra init functions
- *
- * CFG_BOARD_ASM_INIT		- Call assembly init code
- */
-
-#define CFG_BOARD_ASM_INIT
-
-
-/*
- * Boot flags
- *
- * BOOTFLAG_COLD			- Indicates a power-on boot
- * BOOTFLAG_WARM			- Indicates a software reset
- */
-
-#define BOOTFLAG_COLD			0x01
-#define BOOTFLAG_WARM			0x02
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
deleted file mode 100644
index d671dccc19..0000000000
--- a/include/configs/ppmc8260.h
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuation settings for the WindRiver PPMC8260 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
- * -------   ----------	 ---	---    ----  -----  -----  -----
- * 0x2	     0x2	 33	133    133   Close  Open   Close
- * 0x2	     0x3	 33	133    166   Close  Open   Open
- * 0x2	     0x4	 33	133    200   Open   Close  Close
- * 0x2	     0x5	 33	133    233   Open   Close  Open
- * 0x2	     0x6	 33	133    266   Open   Open   Close
- *
- * 0x5	     0x5	 66	133    133   Open   Close  Open
- * 0x5	     0x6	 66	133    166   Open   Open   Close
- * 0x5	     0x7	 66	133    200   Open   Open   Open
- * 0x6	     0x0	 66	133    233   Close  Close  Close
- * 0x6	     0x1	 66	133    266   Close  Close  Open
- * 0x6	     0x2	 66	133    300   Close  Open   Close
- */
-#define CFG_PPMC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_PPMC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CFG_FLASH0_BASE 0xFE000000
-#define CFG_FLASH0_SIZE 16
-
-/* What should be the base address of the first SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 128
-
-/* What should be the base address of the second SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM1_BASE 0x08000000
-#define CFG_SDRAM1_SIZE 128
-
-/* What should be the base address of the on board SDRAM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM2_BASE 0x38000000
-#define CFG_SDRAM2_SIZE 16
-
-/* What should be the base address of the MAILBOX  and how big is it
- * (in Bytes)
- * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
- */
-#define CFG_MAILBOX_BASE 0x32000000
-#define CFG_MAILBOX_SIZE 8192
-
-/* What is the base address of the I/O select lines and how big is it
- * (In Mbytes)?
- */
-
-#define CFG_IOSELECT_BASE 0xE0000000
-#define CFG_IOSELECT_SIZE 32
-
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CFG_LED_BASE 0xF1000000
-
-/*
- * PPMC8260 with 256 16 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *	     :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *	     :
- *	     :
- *
- *	     :
- *	     :
- *     0x0FF5 FF30     Monitor Stack (Growing downward)
- *		       Monitor Stack Buffer (0x80)
- *     0x0FF5 FFB0     Board Info Data
- *     0x0FF6 0000     Malloc Arena
- *	     :		    CFG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
- *     0x0FFC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x0FFF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- * The console can be on SMC1 or SMC2
- */
-#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-
-#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
-#define CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-#define CONFIG_MII			/* MII PHY management	*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT	2	/* Port C */
-#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
-#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
-			else	iop->pdat &= ~0x00400000
-
-#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
-			else	iop->pdat &= ~0x00200000
-
-#define MIIDELAY	udelay(1)
-
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT	1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE		9600
-
-/* Ethernet MAC address */
-
-#define CONFIG_ETHADDR		00:a0:1e:90:2b:00
-
-/* Define this to set the last octet of the ethernet address
- * from the DS0-DS7 switch and light the leds with the result
- * The DS0-DS7 switch and the leds are backwards with respect
- * to each other. DS7 is on the board edge side of both the
- * led strip and the DS0-DS7 switch.
- */
-#define CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#if 0
-/* Be selective on what keys can delay or stop the autoboot process
- *     To stop	use: " "
- */
-# define CONFIG_AUTOBOOT_KEYED
-# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
-# define CONFIG_AUTOBOOT_STOP_STR	" "
-# undef CONFIG_AUTOBOOT_DELAY_STR
-# define DEBUG_BOOTKEYS		0
-#endif
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
-#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/ram0 rw " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-/* Add support for a few extra bootp options like:
- *	- File size
- *	- DNS
- */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS)
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
-
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS		(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ELF	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_MEMTEST | \
-				CFG_CMD_MII	| \
-				CFG_CMD_IMMAP)
-
-
-/* Where do the internal registers live? */
-#define CFG_IMMR		0xf0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
-#else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS		32	/* max number of command args	*/
-
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
-
-#define CFG_LOAD_ADDR		0x140000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
-					/* the exception vector table */
-					/* to the end of the DRAM  */
-					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
-				+ CFG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
-
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-/*
- *  Attention: This is board specific
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-#define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
-				CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-/*
- * Attention: this is board-specific
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-#define CFG_CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif	/* CONFIG_ETHER_INDEX */
-
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	(CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CFG_PPMC_BOOT_LOW)
-#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_PPMC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_PPMC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
-
-#define CFG_HRCW_MASTER		( HRCW_EBM				| \
-				  HRCW_BPS11				| \
-				  HRCW_L2CPC10				| \
-				  HRCW_DPPC00				| \
-				  CFG_PPMC_HRCW_IMMR			| \
-				  HRCW_MMR00				| \
-				  HRCW_LBPC00				| \
-				  HRCW_APPC10				| \
-				  HRCW_CS10PC00				| \
-				  (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
-				  CFG_PPMC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
-
-#ifndef CFG_MONITOR_BASE
-#define CFG_MONITOR_BASE	0x0ff80000
-#endif
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 374 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
-
-
-#ifndef CFG_RAMBOOT
-
-#  define CFG_ENV_IS_IN_FLASH	1
-#  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE	0x40000
-#  else
-#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
-#    define CFG_ENV_SECT_SIZE	0x40000 /* see README - env sect real size	*/
-#  endif /* CFG_ENV_IN_OWN_SECT */
-
-#else
-#  define CFG_ENV_IS_IN_FLASH	1
-#  define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
-#define CFG_ENV_SIZE		0x1000
-#  define CFG_ENV_SECT_SIZE	0x40000
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL	(HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		(BCR_EBM      |\
-			 0x30000000)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- * Ref Section 4.3.2.6	page 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR	(SIUMCR_ESE	 |\
-			 SIUMCR_DPPC00	 |\
-			 SIUMCR_L2CPC10	 |\
-			 SIUMCR_LBPC00	 |\
-			 SIUMCR_APPC10	 |\
-			 SIUMCR_CS10PC00 |\
-			 SIUMCR_BCTLC00	 |\
-			 SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CFG_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR	0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	32 bit	FLASH (SIMM - 32MB) *
- *  1	unused
- *  2	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
- *  3	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
- *  4	Local	SDRAM	32 bit	SDRAM (on board - 16MB)
- *  5	60x	GPCM	 8 bit	Mailbox/EEPROM (8KB)
- *  6	60x	GPCM	 8 bit	FLASH  (on board - 2MB) *
- *  7	60x	GPCM	 8 bit	LEDs, switches
- *
- *  (*) This configuration requires the PPMC8260 be configured
- *	so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
- *	the on board FLASH. In other words, JP24 should have
- *	pins 1 and 2 jumpered and pins 3 and 4 jumpered.
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F080B parts.
- *
- * Note: For the 4 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- *     - Base address of 0xFE000000
- *     - 32 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-/* OR0 is configured as follows:
- *
- *     - 32 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_TRLX			|\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 2,3 - 128 MB SDRAM DIMM
- */
-
-/* With a 128 MB DIMM, the BR2 is configured as follows:
- *
- *     - Base address of 0x00000000/0x08000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CFG_BR3_PRELIM	((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-/* With a 128 MB DIMM, the OR2 is configured as follows:
- *
- *     - 128 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 13 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-#define CFG_OR3_PRELIM	(MEG_TO_AM(CFG_SDRAM1_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A7		|\
-			 ORxS_NUMR_13)
-
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* With a 128 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Page Based Interleaving,
- *     - Refresh Enable,
- *     - Normal Operation
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A13-A15 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - External Address Multiplexing enabled
- *     - CAS Latency is 2.
- */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A13_A15   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_EAMUX	      |\
-			 PSDMR_CL_2)
-
-
-#define CFG_PSRT	0x0e
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-
-
-/*-----------------------------------------------------------------------
- * BR4 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR4 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 4 - On board SDRAM
- *
- */
-/* With 16 MB of onboard SDRAM	BR4 is configured as follows
- *
- *     - Base address 0x38000000
- *     - 32 bit port size
- *     - Data error checking disabled
- *     - Read/Write access
- *     - SDRAM local bus
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- *
- */
-
-#define CFG_BR4_PRELIM	((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32			|\
-			 BRx_DECC_NONE			|\
-			 BRx_MS_SDRAM_L			|\
-			 BRx_V)
-
-/*
- * With 16MB SDRAM, OR4 is configured as follows
- *     - 4 internal banks per device
- *     - Row start address bit is A10 with LSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-
-#define CFG_OR4_PRELIM	(MEG_TO_AM(CFG_SDRAM2_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A10		|\
-			 ORxS_NUMR_12)
-
-
-/*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register
- *     Ref: Section 10.3.4 on page 10-24
- *-----------------------------------------------------------------------
- */
-
-/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
- *
- *     - Page Based Interleaving,
- *     - Refresh Enable,
- *     - Normal Operation
- *     - Address Multiplexing where A5 is output on A13 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A15-A17 as bank select,
- *     - A11 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 2 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - SDRAM burst length is 8
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - External Address Multiplexing disabled
- *     - CAS Latency is 2.
- */
-#define CFG_LSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A13_IS_A5 |\
-			 PSDMR_BSMA_A15_A17   |\
-			 PSDMR_SDA10_PBI0_A11 |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_2W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_BL	      |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-
-#define CFG_LSRT	0x0e
-
-/*-----------------------------------------------------------------------
- * BR5 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR5 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/*
- * Bank 5 EEProm and Mailbox
- *
- * The EEPROM and mailbox live on the same chip select.
- * the eeprom is selected if the MSb of the address is set and the mailbox is
- * selected if the MSb of the address is clear.
- *
- */
-
-/* BR5 is configured as follows:
- *
- *     - Base address of 0x32000000/0xF2000000
- *     - 8 bit
- *     - Data error checking disabled
- *     - Read/Write access
- *     - GPCM 60x Bus
- *     - SDRAM local bus
- *     - No data pipelining is done
- *     - Valid
- */
-
-#define CFG_BR5_PRELIM	((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
-			 BRx_PS_8			 |\
-			 BRx_DECC_NONE			 |\
-			 BRx_MS_GPCM_P			 |\
-			 BRx_V)
-/* OR5 is configured as follows
- *     - buffer control enabled
- *     - chip select negated normally
- *     - CS output 1/2 clock after address
- *     - 15 wait states
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-
-#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
-			 ORxG_ACS_DIV2				     |\
-			 ORxG_SCY_15_CLK			     |\
-			 ORxG_TRLX				     |\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - I/O select
- *
- */
-
-/* BR6 is configured as follows:
- *
- *     - Base address of 0xE0000000
- *     - 16 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR6_PRELIM	((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
-			   BRx_PS_16			  |\
-			   BRx_MS_GPCM_P		  |\
-			   BRx_V)
-
-/* OR6 is configured as follows
- *     - buffer control enabled
- *     - chip select negated normally
- *     - CS output 1/2 clock after address
- *     - 15 wait states
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-
-#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
-			 ORxG_ACS_DIV2		     |\
-			 ORxG_SCY_15_CLK	     |\
-			 ORxG_TRLX		     |\
-			 ORxG_EHTR)
-
-
-/*-----------------------------------------------------------------------
- * BR7 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR7 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 7 - LEDs and switches
- *
- *  LEDs     are at 0x00001 (write only)
- *  switches are at 0x00001 (read only)
- */
-#ifdef CFG_LED_BASE
-
-/* BR7 is configured as follows:
- *
- *     - Base address of 0xA0000000
- *     - 8 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR7_PRELIM	((CFG_LED_BASE & BRx_BA_MSK)	 |\
-			   BRx_PS_8			 |\
-			   BRx_DECC_NONE		 |\
-			   BRx_MS_GPCM_P		 |\
-			   BRx_V)
-
-/* OR7 is configured as follows:
- *
- *     - 1 byte
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 15
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#define CFG_OR7_PRELIM	(ORxG_AM_MSK		       |\
-			 ORxG_CSNT		       |\
-			 ORxG_ACS_DIV1		       |\
-			 ORxG_SCY_15_CLK	       |\
-			 ORxG_TRLX		       |\
-			 ORxG_EHTR)
-#endif /* CFG_LED_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/purple.h b/include/configs/purple.h
deleted file mode 100644
index 2ecb7fb2bf..0000000000
--- a/include/configs/purple.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the PURPLE board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1	/* MIPS 5Kc CPU core	*/
-#define CONFIG_PURPLE		1	/* on a PURPLE Board	*/
-
-#define CPU_CLOCK_RATE	125000000   /* 125 MHz clock for the MIPS core */
-#define ASC_CLOCK_RATE	 62500000   /* 62.5 MHz ASC clock              */
-
-#define INFINEON_EBU_BOOTCFG	0xE0CC
-
-#define CONFIG_STACKSIZE	(128 * 1024)
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BAUDRATE		19200
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off\0"				\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"ethaddr=${ethaddr} "					\
-		"panic=1\0"						\
-	"flash_nfs=run nfsargs addip addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addmisc;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 80500000 ${bootfile};"				\
-		"run nfsargs addip addmisc;bootm\0"			\
-	"rootpath=/opt/eldk/mips_5KC\0"					\
-	"bootfile=/tftpboot/purple/uImage\0"				\
-	"kernel_addr=B0040000\0"					\
-	"ramdisk_addr=B0100000\0"					\
-	"u-boot=/tftpboot/purple/u-boot.bin\0"				\
-	"load=tftp 80500000 ${u-boot}\0"				\
-	"update=protect off 1:0-4;era 1:0-4;"				\
-		"cp.b 80500000 B0000000 ${filesize}\0"			\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ELF)
-#include <cmd_confdefs.h>
-
-#define CFG_SDRAM_BASE		0x80000000
-
-#define CFG_INIT_SP_OFFSET      0x400000
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_HZ			(CPU_CLOCK_RATE/2)
-#define	CFG_MAXARGS		16		/* max number of command args*/
-
-#define	CFG_LOAD_ADDR		0x80500000	/* default load address	*/
-
-#define CFG_MEMTEST_START	0x80200000
-#define CFG_MEMTEST_END		0x80800000
-
-#define	CONFIG_MISC_INIT_R
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(35)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xB0008000
-#define CFG_ENV_SIZE		0x4000
-
-#define CONFIG_FLASH_32BIT
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define CONFIG_PLB2800_ETHER
-#define CONFIG_NET_MULTI
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CFG_SCONSOLE_ADDR     (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \
-			       CFG_DCACHE_SIZE / 2)
-#define CFG_SCONSOLE_SIZE     (CFG_DCACHE_SIZE / 4)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
deleted file mode 100644
index b319cf497d..0000000000
--- a/include/configs/rmu.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#undef CONFIG_MPC860
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_RPXLITE		1	/* RMU is the RPXlite clone */
-#define CONFIG_RMU			1
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-/* enable I2C and select the hardware/software driver */
-#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-
-#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
-
-/* Software (bit-bang) I2C driver configuration */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-/* M41T11 Serial Access Timekeeper(R) SRAM */
-#define CONFIG_RTC_M41T11 1
-#define CFG_I2C_RTC_ADDR 0x68
-#define CFG_M41T11_BASE_YEAR 1900	/* play along with the linux driver */
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection */
-#define	CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d sec...\n"
-#define	CONFIG_AUTOBOOT_DELAY_STR	"system"
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		(0-flash_info[0].size)	/* Put flash at end	*/
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		((TEXT_BASE) + 0x40000)
-#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Reset address
- */
-#define	CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base - up to 64 MB of flash */
-#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask - map 64 MB */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
-
-#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define CFG_NVRAM_BASE	0xFA000000		/* NVRAM & SRAM base */
-/*      IMMR:		0xFA200000		   IMMR base address - see above */
-#define	CFG_BCSR_BASE	0xFA400000		/* BCSR base address */
-
-#define	CFG_BR3_PRELIM	(CFG_BCSR_BASE | BR_V)			/* BCSR */
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define CFG_BR4_PRELIM  (CFG_NVRAM_BASE | BR_PS_8 | BR_V)	/* NVRAM & SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0970
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	20
-
-/*
- * Refresh clock Prescalar
- */
-#define CFG_MPTPR	MPTPR_PTP_DIV2
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0	(CFG_BCSR_BASE + 0)
-#define BCSR1	(CFG_BCSR_BASE + 1)
-#define BCSR2	(CFG_BCSR_BASE + 2)
-#define BCSR3	(CFG_BCSR_BASE + 3)
-
-#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
-#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
-#define BCSR0_COLTEST	0x20
-#define BCSR0_ETHLPBK	0x40
-#define BCSR0_ETHEN	0x80
-
-#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
-#define BCSR1_PCVCTL6	0x02
-#define BCSR1_PCVCTL5	0x04
-#define BCSR1_PCVCTL4	0x08
-#define BCSR1_IPB5SEL	0x10
-
-#define BCSR2_ENPA5HDR	0x08	/* USB Control */
-#define BCSR2_ENUSBCLK	0x10
-#define BCSR2_USBPWREN	0x20
-#define BCSR2_USBSPD	0x40
-#define BCSR2_USBSUSP	0x80
-
-#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
-#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
-#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
-#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
-#define BCSR3_D27	0x10	/* Dip Switch settings */
-#define BCSR3_D26	0x20
-#define BCSR3_D25	0x40
-#define BCSR3_D24	0x80
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
deleted file mode 100644
index 6c9e392c36..0000000000
--- a/include/configs/rsdproto.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the R&S Protocol Board board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
-#define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef 	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
-#define	CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-
-#if (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	(0)
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* enable I2C */
-#define CONFIG_HARD_I2C        	1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	50000000	/* in Hz */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_RSD_BOOT_LOW 1
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs"
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5a
-#define CONFIG_NETMASK          255.255.0.0
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define PHYS_SDRAM_60X		0x00000000 /* SDRAM (60x Bus) */
-#define PHYS_SDRAM_60X_SIZE	0x08000000 /* 128 MB */
-
-#define PHYS_SDRAM_LOCAL	0x40000000 /* SDRAM (Local Bus) */
-#define PHYS_SDRAM_LOCAL_SIZE	0x04000000 /* 64 MB */
-
-#define PHYS_DPRAM_PCI       	0xE8000000 /* DPRAM PPC/PCI */
-#define PHYS_DPRAM_PCI_SIZE   	0x00020000 /* 128 KB */
-
-/*#define PHYS_DPRAM_PCI_SEM	0x04020000 / * DPRAM PPC/PCI Semaphore */
-/*#define PHYS_DPRAM_PCI_SEM_SIZE	0x00000001 / * 1 Byte */
-
-#define PHYS_DPRAM_SHARC       	0xE8100000 /* DPRAM PPC/Sharc */
-#define PHYS_DPRAM_SHARC_SIZE 	0x00040000 /* 256 KB */
-
-/*#define PHYS_DPRAM_SHARC_SEM	0x04140000 / * DPRAM PPC/Sharc Semaphore */
-/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
-
-#define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
-#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
-
-#define PHYS_USB		0x04200000 /* USB Controller (60x Bus) */
-#define PHYS_USB_SIZE		0x00000002 /* 2 Bytes */
-
-#define PHYS_IMMR		0xF0000000 /* Internal Memory Mapped Reg. */
-
-#define PHYS_FLASH		0xFF000000 /* Flash (60x Bus) */
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
-
-#define CFG_IMMR		PHYS_IMMR
-
-/*-----------------------------------------------------------------------
- * Reset Address
- *
- * In order to reset the CPU, U-Boot jumps to a special address which
- * causes a machine check exception. The default address for this is
- * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
- * testing the monitor in RAM using a JTAG debugger.
- *
- * Just set CFG_RESET_ADDRESS to an address that you know is sure to
- * cause a bus error on your hardware.
- */
-#define CFG_RESET_ADDRESS	0x20000000
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-
-#if defined(CFG_RSD_BOOT_LOW)
-#  define  CFG_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_RSD_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_RSD_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_IMMR & 0x00100000) >> 4) )
-
-#define CFG_HRCW_MASTER	(HRCW_L2CPC10 | \
-			 HRCW_DPPC11 | \
-			 CFG_RSD_HRCW_IMMR |\
-			 HRCW_MMR00 | \
-			 HRCW_APPC10 | \
-			 HRCW_CS10PC00 | \
-			 HRCW_MODCK_H0000 |\
-			 CFG_RSD_HRCW_BOOT_FLAGS)
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1	0
-#define CFG_HRCW_SLAVE2	0
-#define CFG_HRCW_SLAVE3	0
-#define CFG_HRCW_SLAVE4	0
-#define CFG_HRCW_SLAVE5	0
-#define CFG_HRCW_SLAVE6	0
-#define CFG_HRCW_SLAVE7	0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
- */
-#define	CFG_SDRAM_BASE		PHYS_SDRAM_60X
-#define CFG_FLASH_BASE		PHYS_FLASH
-/*#define	CFG_MONITOR_BASE	0x200000 */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMBOOT
-#endif
-#define	CFG_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/
-
-/* turn off NVRAM env feature */
-#undef CONFIG_NVRAM_ENV
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR	(PHYS_FLASH + 0x28000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x8000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		0x100c0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
-					 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
-			 SYPCR_SWRI | SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR	0x00000000
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Init Memory Controller:
- */
-
-#define CFG_PSDMR	0x494D2452
-#define CFG_LSDMR	0x49492552
-
-/* Flash */
-#define CFG_BR0_PRELIM	(PHYS_FLASH | BRx_V)
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
-			 ORxG_BCTLD | \
-			 ORxG_SCY_5_CLK)
-
-/* DPRAM to the PCI BUS on the protocol board */
-#define CFG_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
-			 ORxG_ACS_DIV4)
-
-/* 60x Bus SDRAM */
-#define CFG_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
-#define CFG_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
-			 ORxS_BPD_4 | \
-			 ORxS_ROWST_PBI1_A2 | \
-			 ORxS_NUMR_13 | \
-			 ORxS_IBID)
-
-/* Virtex-FPGA - Register */
-#define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
-#define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
-			 ORxG_SCY_1_CLK | \
-			 ORxG_ACS_DIV2 | \
-			 ORxG_CSNT )
-
-/* local bus SDRAM */
-#define CFG_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
-#define CFG_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
-			 ORxS_BPD_4 | \
-			 ORxS_ROWST_PBI1_A4 | \
-			 ORxS_NUMR_13)
-
-/* DPRAM to the Sharc-Bus on the protocol board */
-#define CFG_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
-#define CFG_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
-			 ORxG_ACS_DIV4)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
deleted file mode 100644
index 97b52fa1ae..0000000000
--- a/include/configs/sacsng.h
+++ /dev/null
@@ -1,1072 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuration settings for the WindRiver SBC8260 board.
- *	See http://www.windriver.com/products/html/sbc8260.html
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef DEBUG		      /* General debug */
-#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
-
-#undef CONFIG_LOGBUFFER       /* External logbuffer support */
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  66666600
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
- * -------   ----------	 ---	---    ----  -----  -----  -----
- * 0x1	     0x5	 33	100    133   Open   Close  Open
- * 0x1	     0x6	 33	100    166   Open   Open   Close
- * 0x1	     0x7	 33	100    200   Open   Open   Open
- *
- * 0x2	     0x2	 33	133    133   Close  Open   Close
- * 0x2	     0x3	 33	133    166   Close  Open   Open
- * 0x2	     0x4	 33	133    200   Open   Close  Close
- * 0x2	     0x5	 33	133    233   Open   Close  Open
- * 0x2	     0x6	 33	133    266   Open   Open   Close
- *
- * 0x5	     0x5	 66	133    133   Open   Close  Open
- * 0x5	     0x6	 66	133    166   Open   Open   Close
- * 0x5	     0x7	 66	133    200   Open   Open   Open
- * 0x6	     0x0	 66	133    233   Close  Close  Close
- * 0x6	     0x1	 66	133    266   Close  Close  Open
- * 0x6	     0x2	 66	133    300   Close  Open   Close
- */
-#define CFG_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)?  This must contain TEXT_BASE from board/sacsng/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 2
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)?  The secondary FLASH is whichever is connected
- * to *CS6.
- */
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH1_SIZE 2
-
-/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
- */
-#define CONFIG_VERY_BIG_RAM	1
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?  This will normally auto-configure via the SPD.
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
-
-/*
- * Memory map example with 64 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *	     :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *	     :
- *	     :
- *
- *	     :
- *	     :
- *     0x03F5 FF30     Monitor Stack (Growing downward)
- *		       Monitor Stack Buffer (0x80)
- *     0x03F5 FFB0     Board Info Data
- *     0x03F6 0000     Malloc Arena
- *	     :		    CFG_ENV_SECT_SIZE, 16k
- *	     :		    CFG_MALLOC_LEN,    128k
- *     0x03FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-#define CONFIG_POST		(CFG_POST_MEMORY | \
-				 CFG_POST_CPU)
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-
-#undef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-
-#ifdef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-#endif	/* CONFIG_ETHER_ON_SCC */
-
-#ifdef	CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-
-#define MDIO_PORT	2	        /* Port A=0, B=1, C=2, D=3 */
-#define MDIO_ACTIVE	(iop->pdir |=  0x40000000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x40000000)
-#define MDIO_READ	((iop->pdat &  0x40000000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x40000000; \
-			else	iop->pdat &= ~0x40000000
-
-#define MDC(bit)	if(bit) iop->pdat |=  0x80000000; \
-			else	iop->pdat &= ~0x80000000
-
-#define MIIDELAY	udelay(50)
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1	/* boot progress enabled	*/
-
-/*
- * Configure for RAM tests.
- */
-#undef  CFG_DRAM_TEST			/* calls other tests in board.c	*/
-
-
-/*
- * Status LED for power up status feedback.
- */
-#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define STATUS_LED_PAR		im_ioport.iop_ppara
-#define STATUS_LED_DIR		im_ioport.iop_pdira
-#define STATUS_LED_ODR		im_ioport.iop_podra
-#define STATUS_LED_DAT		im_ioport.iop_pdata
-
-#define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/
-#define STATUS_LED_PERIOD	(CFG_HZ)
-#define STATUS_LED_STATE	STATUS_LED_OFF
-#define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/
-#define STATUS_LED_PERIOD1	(CFG_HZ)
-#define STATUS_LED_STATE1	STATUS_LED_OFF
-#define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/
-#define STATUS_LED_PERIOD2	(CFG_HZ/2)
-#define STATUS_LED_STATE2	STATUS_LED_ON
-
-#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-
-#define STATUS_LED_YELLOW	0
-#define STATUS_LED_GREEN	1
-#define STATUS_LED_RED		2
-#define STATUS_LED_BOOT		1
-
-
-/*
- * Select SPI support configuration
- */
-#define CONFIG_SOFT_SPI		/* Enable SPI driver */
-#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
-#undef  DEBUG_SPI               /* Disable SPI debugging */
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#ifdef CONFIG_SOFT_SPI
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#define I2C_SCLK	0x00002000      /* PD 18: Shift clock */
-#define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */
-#define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */
-
-#undef  SPI_INIT			/* no port initialization needed */
-#define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
-#define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
-#define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
-#define SPI_DELAY                       /* No delay is needed */
-#endif /* CONFIG_SOFT_SPI */
-
-
-/*
- * select I2C support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SOFT_I2C
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(20)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-/* Define this to reserve an entire FLASH sector for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT	1
-
-/* Define this to contain any number of null terminated strings that
- * will be part of the default enviroment compiled into the boot image.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"quiet=0\0" \
-"serverip=192.168.123.205\0" \
-"ipaddr=192.168.123.203\0" \
-"checkhostname=VR8500\0" \
-"reprog="\
-    "bootp; " \
-    "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
-    "protect off 60000000 6003FFFF; " \
-    "erase 60000000 6003FFFF; " \
-    "cp.b 140000 60000000 ${filesize}; " \
-    "protect on 60000000 6003FFFF\0" \
-"copyenv="\
-    "protect off 60040000 6004FFFF; " \
-    "erase 60040000 6004FFFF; " \
-    "cp.b 40040000 60040000 10000; " \
-    "protect on 60040000 6004FFFF\0" \
-"copyprog="\
-    "protect off 60000000 6003FFFF; " \
-    "erase 60000000 6003FFFF; " \
-    "cp.b 40000000 60000000 40000; " \
-    "protect on 60000000 6003FFFF\0" \
-"zapenv="\
-    "protect off 40040000 4004FFFF; " \
-    "erase 40040000 4004FFFF; " \
-    "protect on 40040000 4004FFFF\0" \
-"zapotherenv="\
-    "protect off 60040000 6004FFFF; " \
-    "erase 60040000 6004FFFF; " \
-    "protect on 60040000 6004FFFF\0" \
-"root-on-initrd="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/ram0 rw quiet " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-initrd-debug="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/ram0 rw debug " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run debug-hook\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-nfs="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/nfs rw quiet " \
-    "nfsroot=\\${serverip}:\\${rootpath} " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-nfs-debug="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/nfs rw debug " \
-    "nfsroot=\\${serverip}:\\${rootpath} " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run debug-hook\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"debug-checkout="\
-    "setenv checkhostname;" \
-    "setenv ethaddr 00:09:70:00:00:01;" \
-    "bootp;" \
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-    "run debug-hook;" \
-    "run boot-hook;" \
-    "bootm\0" \
-"debug-hook="\
-    "echo ipaddr    ${ipaddr};" \
-    "echo serverip  ${serverip};" \
-    "echo gatewayip ${gatewayip};" \
-    "echo netmask   ${netmask};" \
-    "echo hostname  ${hostname}\0" \
-"ana=run adc ; run dac\0" \
-"adc=run adc-12 ; run adc-34\0" \
-"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
-"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
-"dac=echo ### DAC ; imd.b 11 81 5\0" \
-"boot-hook=echo\0"
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE		9600
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR		00:09:70:00:00:00
-
-/* The default Ethernet MAC address can be overwritten just once  */
-#ifdef  CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#endif
-
-/*
- * Define this to do some miscellaneous board-specific initialization.
- */
-#define CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
-
-/* Be selective on what keys can delay or stop the autoboot process
- *     To stop	use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-#undef  CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define DEBUG_BOOTKEYS		0
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
-#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/ram0 rw quiet " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"run boot-hook;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"run boot-hook;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-#define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
-
-/* Add support for a few extra bootp options like:
- *	- File size
- *	- DNS (up to 2 servers)
- *      - Send hostname to DHCP server
- */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME)
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
-
-#undef  CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
-#endif
-
-/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
- * of an image is printed by image commands like bootm or iminfo.
- */
-#define CONFIG_TIMESTAMP
-
-/* If this variable is defined, an environment variable named "ver"
- * is created by U-Boot showing the U-Boot version.
- */
-#define CONFIG_VERSION_VARIABLE
-
-/* What U-Boot subsytems do you want enabled? */
-#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ELF	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_SPI	| \
-				CFG_CMD_SDRAM   | \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_IMMAP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_MII	)
-#else
-# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ELF	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_SPI	| \
-				CFG_CMD_SDRAM   | \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_IMMAP	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_PING	)
-#endif /* CONFIG_ETHER_ON_FCC */
-
-/* Where do the internal registers live? */
-#define CFG_IMMR		0xF0000000
-
-#undef	CONFIG_WATCHDOG			/* disable the watchdog */
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
-#define CONFIG_SACSng		1	/* munged for the SACSng */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
-					/* in the bootm command.             */
-#define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
-					/* "## <message>" from the bootm cmd */
-#define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
-					/* defined, then the hostname param  */
-					/* validated against checkhostname.  */
-#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
-#define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
-					/* (limited to maximum of 1024 msec) */
-#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
-					/* Check for abort key presses       */
-					/* at least once in dependent of the */
-					/* CONFIG_BOOTDELAY value.           */
-#define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
-#define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
-					/* state to the fault LED.           */
-#define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
-					/* the Ethernet link state.          */
-#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
-					/* until the TFTP is successful.     */
-#define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
-					/* turn off the STATUS LEDs.         */
-#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
-					/* incoming data.                    */
-#define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
-					/* to signify that tftp is moving.   */
-#define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
-					/* flash the status LED.             */
-#define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
-					/* during the tftp file transfer.    */
-#define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
-					/* '#'s from the tftp command.       */
-#define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
-					/* issued during the tftp command.   */
-#define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
-					/* before it gives up.               */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
-#else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS		32	/* max number of command args	*/
-
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
-
-#define CFG_LOAD_ADDR		0x400000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_ALT_MEMTEST                 /* Select full-featured memory test */
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
-					/* the exception vector table */
-					/* to the end of the DRAM  */
-					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
-				+ CFG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
-
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
-
-#define CFG_HRCW_MASTER		( HRCW_BPS10				| \
-				  HRCW_DPPC11				| \
-				  CFG_SBC_HRCW_IMMR			| \
-				  HRCW_MMR00				| \
-				  HRCW_LBPC11				| \
-				  HRCW_APPC10				| \
-				  HRCW_CS10PC00				| \
-				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
-				  CFG_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#undef  CFG_FLASH_PROTECTION		/* use hardware protection		*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH	1
-
-#  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#    define CFG_ENV_SECT_SIZE	0x10000
-#  else
-#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
-#    define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
-#  endif /* CFG_ENV_IN_OWN_SECT */
-
-#else
-#  define CFG_ENV_IS_IN_NVRAM	1
-#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL	(HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
-			 SIUMCR_L2CPC00 |\
-			 SIUMCR_APPC10	|\
-			 SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP  |\
-			 SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR	0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	16 bit	FLASH (primary flash - 2MB)
- *  1	60x	GPCM	-- bit	(Unused)
- *  2	60x	SDRAM	64 bit	SDRAM (DIMM)
- *  3	60x	SDRAM	64 bit	SDRAM (DIMM)
- *  4	60x	GPCM	-- bit	(Unused)
- *  5	60x	GPCM	-- bit	(Unused)
- *  6	60x	GPCM	16 bit	FLASH  (secondary flash - 2MB)
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0 - Primary FLASH
- */
-
-/* BR0 is configured as follows:
- *
- *     - Base address of 0x40000000
- *     - 16 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-/* OR0 is configured as follows:
- *
- *     - 4 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_TRLX			|\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- */
-
-/* The BR2 is configured as follows:
- *
- *     - Base address of 0x00000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- *     - 64 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A8		|\
-			 ORxS_NUMR_12)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* Address that the DIMM SPD memory lives at.
- */
-#define SDRAM_SPD_ADDR 0x50
-
-#if (CFG_SDRAM0_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Bank Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A14-A16 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A14_A16   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*
- * Shoot for approximately 1MHz on the prescaler.
- */
-#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV64
-#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-#else
-#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-#endif
-#define CFG_PSRT	14
-
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - Secondary FLASH
- *
- * The secondary FLASH is connected to *CS6
- */
-#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
-
-/* BR6 is configured as follows:
- *
- *     - Base address of 0x60000000
- *     - 16 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
-			   BRx_PS_16			  |\
-			   BRx_MS_GPCM_P		  |\
-			   BRx_V)
-
-/* OR6 is configured as follows:
- *
- *     - 2 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
-			   ORxG_CSNT		       |\
-			   ORxG_ACS_DIV1	       |\
-			   ORxG_SCY_5_CLK	       |\
-			   ORxG_TRLX		       |\
-			   ORxG_EHTR)
-#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
deleted file mode 100644
index 866f7b0426..0000000000
--- a/include/configs/sbc2410x.h
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Modified for the friendly-arm SBC-2410X by
- * (C) Copyright 2005
- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
- *
- * Configuation settings for the friendly-arm SBC-2410X board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT	/* undef for developing */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
-#define CONFIG_SBC2410X		1	/* on a friendly-arm SBC-2410X Board  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000/* the SBC2410X has 12MHz input clock */
-
-
-#define USE_920T_MMU		1
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x19000300
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SBC2410X */
-
-/************************************************************
- * RTC
- ************************************************************/
-#define	CONFIG_RTC_S3C24X0	1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
-			(CONFIG_CMD_DFL	 | \
-			CFG_CMD_CACHE	 | \
-			/*CFG_CMD_NAND	 |*/ \
-			/*CFG_CMD_EEPROM |*/ \
-			/*CFG_CMD_I2C	 |*/ \
-			/*CFG_CMD_USB	 |*/ \
-			CFG_CMD_REGINFO  | \
-			CFG_CMD_DATE	 | \
-			CFG_CMD_PING     | \
-			CFG_CMD_DHCP     | \
-			CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
-#define CONFIG_ETHADDR	        08:00:3e:26:0a:5b
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.0.69
-#define CONFIG_SERVERIP		192.168.0.1
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-#define CONFIG_BOOTCOMMAND	"dhcp; bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
-
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/* #define CONFIG_AMD_LV400	1	/\* uncomment this if you have a LV400 flash *\/ */
-
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define NAND_WAIT_READY(nand)	NF_WaitRB()
-#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
-#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
-#define WRITE_NAND(d, adr)		NF_Write(d)
-#define READ_NAND(adr)			NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
-#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2   "> "
-
-#define CONFIG_CMDLINE_EDITING
-
-#ifdef CONFIG_CMDLINE_EDITING
-#undef CONFIG_AUTO_COMPLETE
-#else
-#define CONFIG_AUTO_COMPLETE
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
deleted file mode 100644
index d891e07b31..0000000000
--- a/include/configs/sbc8240.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Configuration settings for the sbc8240 board.
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8240		1
-#define CONFIG_WRSBC8240	1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_PREBOOT  "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND	"version;echo;tftpboot $loadaddr $loadfile;bootvx"	/* autoboot command	*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
-	       "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
-	       "tn=sbc8240 o=fei \0" \
-	"env_startaddr=FFF70000\0" \
-	"env_endaddr=FFF7FFFF\0" \
-	"loadfile=vxWorks.st\0" \
-	"loadaddr=0x01000000\0" \
-	"net_load=tftpboot $loadaddr $loadfile\0" \
-	"uboot_startaddr=FFF00000\0" \
-	"uboot_endaddr=FFF3FFFF\0" \
-	"update=tftp $loadaddr /u-boot.bin;" \
-		"protect off $uboot_startaddr $uboot_endaddr;" \
-		"era $uboot_startaddr $uboot_endaddr;" \
-		"cp.b $loadaddr $uboot_startaddr $filesize;" \
-		"protect on $uboot_startaddr $uboot_endaddr\0" \
-	"zapenv=protect off $env_startaddr $env_endaddr;" \
-		"era $env_startaddr $env_endaddr;" \
-		"protect on $env_startaddr $env_endaddr\0"
-
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_COMMANDS	( CONFIG_CMD_DFL | \
-				  CFG_CMD_BSP    | \
-				  CFG_CMD_DIAG   | \
-				  CFG_CMD_ELF    | \
-				  CFG_CMD_ENV    | \
-				  CFG_CMD_FLASH  | \
-				  CFG_CMD_PCI    | \
-				  CFG_CMD_PING   | \
-				  CFG_CMD_SDRAM  | \
-				  0 )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#if 1
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#define CONFIG_ETHADDR          DE:AD:BE:EF:01:01    /* Ethernet address */
-#define CONFIG_IPADDR           192.168.193.102
-#define CONFIG_NETMASK          255.255.255.248
-#define CONFIG_SERVERIP         192.168.193.99
-
-#define CONFIG_STATUS_LED               /* Status LED enabled           */
-#define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
-
-#define STATUS_LED_BIT          0x00000001
-#define STATUS_LED_PERIOD       (CFG_HZ / 2)
-#define STATUS_LED_STATE        STATUS_LED_BLINKING
-#define STATUS_LED_ACTIVE       0       /* LED on for bit == 0  */
-#define STATUS_LED_BOOT         0       /* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-/* LEDs */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		*((volatile char *) (CFG_LED_BASE)) ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			*((volatile char *) (CFG_LED_BASE)) |= (_msk); \
-		else \
-			*((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \
-	} while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-#define CONFIG_MISC_INIT_R
-#define CFG_LED_BASE	0xFFE80000
-
-/* Print Buffer Size
- */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFCE00000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x10000000
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-	/* Size in bytes reserved for initial data
-	 */
-#define CFG_GBL_DATA_SIZE    128
-
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#define CFG_NS16550_CLK		3686400
-
-#define CFG_NS16550_COM1	0xFFF80000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     1000
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_REFINT	    430	    /* Refresh interval			*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    192
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
-#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CFG_ACTORW	    2
-#define CFG_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* Max number of sectors in one bank	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
-#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0xFFF70000
-#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
-#define CFG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#define CONFIG_PCI_PNP                  /* we need Plug 'n Play */
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
-#define CONFIG_TULIP
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
-#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
deleted file mode 100644
index 9cf0654be1..0000000000
--- a/include/configs/sbc8260.h
+++ /dev/null
@@ -1,1086 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuration settings for the WindRiver SBC8260 board.
- *	See http://www.windriver.com/products/html/sbc8260.html
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Enable debug prints */
-#undef DEBUG		      /* General debug */
-#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
- * -------   ----------	 ---	---    ----  -----  -----  -----
- * 0x1	     0x5	 33	100    133   Open   Close  Open
- * 0x1	     0x6	 33	100    166   Open   Open   Close
- * 0x1	     0x7	 33	100    200   Open   Open   Open
- *
- * 0x2	     0x2	 33	133    133   Close  Open   Close
- * 0x2	     0x3	 33	133    166   Close  Open   Open
- * 0x2	     0x4	 33	133    200   Open   Close  Close
- * 0x2	     0x5	 33	133    233   Open   Close  Open
- * 0x2	     0x6	 33	133    266   Open   Open   Close
- *
- * 0x5	     0x5	 66	133    133   Open   Close  Open
- * 0x5	     0x6	 66	133    166   Open   Open   Close
- * 0x5	     0x7	 66	133    200   Open   Open   Open
- * 0x6	     0x0	 66	133    233   Close  Close  Close
- * 0x6	     0x1	 66	133    266   Close  Close  Open
- * 0x6	     0x2	 66	133    300   Close  Open   Close
- */
-#define CFG_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 4
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
- * want it enabled, don't define these constants.
- */
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH1_SIZE 2
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
-
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
- */
-#define CFG_LED_BASE 0xa0000000
-
-
-/*
- * SBC8260 with 16 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *	     :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *	     :
- *	     :
- *
- *	     :
- *	     :
- *     0x00F5 FF30     Monitor Stack (Growing downward)
- *		       Monitor Stack Buffer (0x80)
- *     0x00F5 FFB0     Board Info Data
- *     0x00F6 0000     Malloc Arena
- *	     :		    CFG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
- *     0x00FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-/*
- * SBC8260 with 64 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *	     :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *	     :
- *	     :
- *
- *	     :
- *	     :
- *     0x03F5 FF30     Monitor Stack (Growing downward)
- *		       Monitor Stack Buffer (0x80)
- *     0x03F5 FFB0     Board Info Data
- *     0x03F6 0000     Malloc Arena
- *	     :		    CFG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
- *     0x03FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
- */
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- */
-
-#undef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-
-#ifdef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-#endif	/* CONFIG_ETHER_ON_SCC */
-
-#ifdef	CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-#undef	CONFIG_ETHER_LOOPBACK_TEST	/* Ethernet external loopback test */
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT	2	/* Port C */
-#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
-#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
-			else	iop->pdat &= ~0x00400000
-
-#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
-			else	iop->pdat &= ~0x00200000
-
-#define MIIDELAY	udelay(1)
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-/*
- * Select SPI support configuration
- */
-#undef  CONFIG_SPI			/* Disable SPI driver */
-
-/*
- * Select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SOFT_I2C
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT	1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE		9600
-
-/* Ethernet MAC address
- *     Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
- *           http://standards.ieee.org/regauth/oui/index.shtml
- */
-#define CONFIG_ETHADDR		00:a0:1e:a8:7b:cb
-
-/*
- * Define this to set the last octet of the ethernet address from the
- * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
- * switch and the LEDs are backwards with respect to each other. DS7
- * is on the board edge side of both the LED strip and the DS0-DS7
- * switch.
- */
-#undef	CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-/* Be selective on what keys can delay or stop the autoboot process
- *     To stop	use: " "
- */
-#undef CONFIG_AUTOBOOT_KEYED
-#ifdef CONFIG_AUTOBOOT_KEYED
-#   define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, press \" \" to stop\n"
-#   define CONFIG_AUTOBOOT_STOP_STR	" "
-#   undef  CONFIG_AUTOBOOT_DELAY_STR
-#   define DEBUG_BOOTKEYS		0
-#endif
-
-/* Define this to contain any number of null terminated strings that
- * will be part of the default enviroment compiled into the boot image.
- *
- * Variable		Usage
- * --------------       -------------------------------------------------------
- * serverip		server IP address
- * ipaddr		my IP address
- * reprog		Reload flash with a new copy of U-Boot
- * zapenv		Erase the environment area in flash
- * root-on-initrd       Set the bootcmd variable to allow booting of an initial
- *                      ram disk.
- * root-on-nfs          Set the bootcmd variable to allow booting of a NFS
- *                      mounted root filesystem.
- * boot-hook            Convenient stub to do something useful before the
- *                      bootm command is executed.
- *
- * Example usage of root-on-initrd and root-on-nfs :
- *
- * Note: The lines have been wrapped to improved its readability.
- *
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=${serverip}:${rootpath}
- * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
- *
- * => run root-on-initrd
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
- * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
- *
- * => run root-on-nfs
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=${serverip}:${rootpath}
- * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
- *
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"serverip=192.168.123.205\0" \
-	"ipaddr=192.168.123.213\0" \
-	"reprog="\
-		"bootp;" \
-		"tftpboot 0x140000 /bdi2000/u-boot.bin;" \
-		"protect off 1:0;" \
-		"erase 1:0;" \
-		"cp.b 140000 40000000 ${filesize};" \
-		"protect on 1:0\0" \
-	"zapenv="\
-		"protect off 1:1;" \
-		"erase 1:1;" \
-		"protect on 1:1\0" \
-	"root-on-initrd="\
-		"setenv bootcmd "\
-		"version;" \
-		"echo;" \
-		"bootp;" \
-		"setenv bootargs root=/dev/ram0 rw " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-		"run boot-hook;" \
-		"bootm\0" \
-	"root-on-nfs="\
-		"setenv bootcmd "\
-		"version;" \
-		"echo;" \
-		"bootp;" \
-		"setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-		"run boot-hook;" \
-		"bootm\0" \
-	"boot-hook=echo\0"
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
-#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/ram0 rw " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-/* Add support for a few extra bootp options like:
- *	- File size
- *	- DNS (up to 2 servers)
- *	- Send hostname to DHCP server
- */
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_BOOTFILESIZE | \
-				 CONFIG_BOOTP_DNS  | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME)
-
-/* undef this to save memory */
-#define CFG_LONGHELP
-
-/* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
-
-#undef  CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
- * of an image is printed by image commands like bootm or iminfo.
- */
-#define CONFIG_TIMESTAMP
-
-/* If this variable is defined, an environment variable named "ver"
- * is created by U-Boot showing the U-Boot version.
- */
-#define CONFIG_VERSION_VARIABLE
-
-/* What U-Boot subsytems do you want enabled? */
-#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IMMAP	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM   )
-#else
-# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IMMAP	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM   )
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#undef CONFIG_WATCHDOG				/* disable the watchdog */
-
-/* Where do the internal registers live? */
-#define CFG_IMMR		0xF0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
-#else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
-#endif
-
-/* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS		32	/* max number of command args	*/
-
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
-
-#define CFG_LOAD_ADDR		0x400000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_ALT_MEMTEST			/* Select full-featured memory test */
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
-					/* the exception vector table */
-					/* to the end of the DRAM  */
-					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
-				+ CFG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
-
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
-
-#define CFG_HRCW_MASTER		( HRCW_BPS11				| \
-				  HRCW_DPPC11				| \
-				  CFG_SBC_HRCW_IMMR			| \
-				  HRCW_MMR00				| \
-				  HRCW_LBPC11				| \
-				  HRCW_APPC10				| \
-				  HRCW_CS10PC00				| \
-				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
-				  CFG_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
-#endif
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
-
-#ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH	1
-
-#  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE	0x40000
-#  else
-#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
-#    define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
-#  endif /* CFG_ENV_IN_OWN_SECT */
-
-#else
-#  define CFG_ENV_IS_IN_NVRAM	1
-#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT	(HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CFG_HID0_FINAL	(HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CFG_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
-			 SIUMCR_L2CPC00 |\
-			 SIUMCR_APPC10	|\
-			 SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP  |\
-			 SYPCR_SWE)
-#else
-#define CFG_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR	(PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR	0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR	0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	32 bit	FLASH (SIMM - 4MB) *
- *  1	60x	GPCM	32 bit	FLASH (SIMM - Unused)
- *  2	60x	SDRAM	64 bit	SDRAM (DIMM - 16MB or 64MB)
- *  3	60x	SDRAM	64 bit	SDRAM (DIMM - Unused)
- *  4	Local	SDRAM	32 bit	SDRAM (on board - 4MB)
- *  5	60x	GPCM	 8 bit	EEPROM (8KB)
- *  6	60x	GPCM	 8 bit	FLASH  (on board - 2MB) *
- *  7	60x	GPCM	 8 bit	LEDs, switches
- *
- *  (*) This configuration requires the SBC8260 be configured
- *	so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
- *	the on board FLASH. In other words, JP24 should have
- *	pins 1 and 2 jumpered and pins 3 and 4 jumpered.
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F080B parts.
- *
- * Note: For the 4 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- *     - Base address of 0x40000000
- *     - 32 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_32			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-/* OR0 is configured as follows:
- *
- *     - 4 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_TRLX			|\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- *
- *     16MB DIMM: P/N
- *     64MB DIMM: P/N  1W-8864X8-4-P1-EST
- *
- * Note: *CS3 is unused for this DIMM
- */
-
-/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
- *
- *     - Base address of 0x00000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-/* With a 16 MB DIMM, the OR2 is configured as follows:
- *
- *     - 16 MB
- *     - 2 internal banks per device
- *     - Row start address bit is A9 with PSDMR[PBI] = 0
- *     - 11 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 16)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
-			 ORxS_BPD_2			|\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_11)
-#endif
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- *     - 64 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A8		|\
-			 ORxS_NUMR_12)
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* Address that the DIMM SPD memory lives at.
- */
-#define SDRAM_SPD_ADDR 0x54
-
-#if (CFG_SDRAM0_SIZE == 16)
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Bank Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A16-A18 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A16_A18   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-#endif
-
-#if (CFG_SDRAM0_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Bank Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A14-A16 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A14_A16   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-#endif
-
-/*
- * Shoot for approximately 1MHz on the prescaler.
- */
-#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV64
-#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-#else
-#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
-#define CFG_MPTPR	MPTPR_PTP_DIV32
-#endif
-#define CFG_PSRT	14
-
-
-/* Bank 4 - On board SDRAM
- *
- * This is not implemented yet.
- */
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - On board FLASH
- *
- * This expects the on board FLASH SIMM to be connected to *CS6
- * It consists of 1 AM29F016A part.
- */
-#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
-
-/* BR6 is configured as follows:
- *
- *     - Base address of 0x60000000
- *     - 8 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
-			   BRx_PS_8			  |\
-			   BRx_MS_GPCM_P		  |\
-			   BRx_V)
-
-/* OR6 is configured as follows:
- *
- *     - 2 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
-			   ORxG_CSNT		       |\
-			   ORxG_ACS_DIV1	       |\
-			   ORxG_SCY_5_CLK	       |\
-			   ORxG_TRLX		       |\
-			   ORxG_EHTR)
-#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
-
-/*-----------------------------------------------------------------------
- * BR7 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR7 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 7 - LEDs and switches
- *
- *  LEDs     are at 0x00001 (write only)
- *  switches are at 0x00001 (read only)
- */
-#ifdef CFG_LED_BASE
-
-/* BR7 is configured as follows:
- *
- *     - Base address of 0xA0000000
- *     - 8 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#  define CFG_BR7_PRELIM  ((CFG_LED_BASE & BRx_BA_MSK)	 |\
-			   BRx_PS_8			 |\
-			   BRx_MS_GPCM_P		 |\
-			   BRx_V)
-
-/* OR7 is configured as follows:
- *
- *     - 1 byte
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 15
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#  define CFG_OR7_PRELIM  (ORxG_AM_MSK		       |\
-			   ORxG_CSNT		       |\
-			   ORxG_ACS_DIV1	       |\
-			   ORxG_SCY_15_CLK	       |\
-			   ORxG_TRLX		       |\
-			   ORxG_EHTR)
-#endif /* CFG_LED_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
deleted file mode 100644
index d7d07a62fc..0000000000
--- a/include/configs/sc520_cdp.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_X86		1	/* This is a X86 CPU		*/
-#define CONFIG_SC520		1	/* Include support for AMD SC520 */
-#define CONFIG_ALI152X		1	/* Include support for Ali 152x SIO */
-
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
-#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
-#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
-
-/* define at most one of these */
-#undef CFG_SDRAM_CAS_LATENCY_2T
-#define CFG_SDRAM_CAS_LATENCY_3T
-
-#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
-#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
-#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
-#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
-#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
-#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
-#define  CFG_USE_SIO_UART       0       /* prefer the uarts on the SIO to those
-					 * in the SC520 on the CDP */
-
-#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define CONFIG_LAST_STAGE_INIT    1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
-
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	15
-#define CONFIG_BOOTARGS    	"root=/dev/mtdblock0 console=ttyS0,9600"
-/* #define CONFIG_BOOTCOMMAND	"bootm 38000000" */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_SPI_EEPROM      /* Support for SPI EEPROMs (AT25128) */
-#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-
-/* Environment in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM   1
-#define CONFIG_SPI
-#define CFG_ENV_SIZE	       0x4000	/* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
-#define CFG_ENV_OFFSET         0
-#define CONFIG_SC520_CDP_USE_SPI  /* Store configuration in the SPI part */
-#undef CONFIG_SC520_CDP_USE_MW    /* Store configuration in the MicroWire part */
-#define CONFIG_SPI_X 1
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=SC520CDP Flash Bank #0"
-#define MTDPARTS_DEFAULT	"mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Device drivers
- */
-#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
-#define CONFIG_PCNET
-#define CONFIG_PCNET_79C973
-#define CONFIG_PCNET_79C975
-#define PCNET_HAS_PROM         1
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-/*#define CFG_ATA_IDE1_OFFSET	0x0170	/###* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
-#define CFG_ATA_BASE_ADDR       0
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
-#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
-
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI			/* enable ATAPI Support */
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-/************************************************************
- * Video/Keyboard support
- ************************************************************/
-#define CONFIG_VIDEO			/* To enable video controller support */
-#define CONFIG_I8042_KBD
-#define CFG_ISA_IO 0
-
-
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI                                /* include pci support */
-#define CONFIG_PCI_PNP                            /* pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW
-
-#define	CFG_FIRST_PCI_IRQ   10
-#define	CFG_SECOND_PCI_IRQ  9
-#define CFG_THIRD_PCI_IRQ   11
-#define	CFG_FORTH_PCI_IRQ   15
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
deleted file mode 100644
index a8e355508b..0000000000
--- a/include/configs/sc520_spunk.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_X86		1	/* This is a X86 CPU		*/
-#define CONFIG_SC520		1	/* Include support for AMD SC520 */
-
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
-#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
-#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
-
-/* define at most one of these */
-#undef CFG_SDRAM_CAS_LATENCY_2T
-#define CFG_SDRAM_CAS_LATENCY_3T
-
-#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
-#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
-#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
-#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
-#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
-#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
-
-#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define CONFIG_LAST_STAGE_INIT    1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
-
-
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	15
-#define CONFIG_BOOTARGS    	"root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
-#define CONFIG_BOOTCOMMAND	"setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-
-#define CONFIG_SPI_EEPROM       /* SPI EEPROMs such as AT25010 or AT25640 */
-#define CONFIG_MW_EEPROM        /* MicroWire EEPROMS such as AT93LC46 */
-#define CONFIG_DS1722           /* Dallas DS1722 SPI Temperature probe */
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-
-#if 0
-/* Environment in flash */
-#define CFG_ENV_IS_IN_FLASH     1
-# define CFG_ENV_ADDR		(0x387a0000)	/* Addr of Environment Sector	*/
-# define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector (or 0x10000) */
-# define CFG_ENV_OFFSET         0
-
-#else
-/* Environment in EEPROM */
-
-# define CFG_ENV_IS_IN_EEPROM   1
-# define CONFIG_SPI
-# define CONFIG_SPI_X 1
-# define CFG_ENV_SIZE		0x2000	/* Total Size of Environment EEPROM	*/
-# define CFG_ENV_OFFSET         0x1c00
-
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=sc520_spunk-0"
-#define MTDPARTS_DEFAULT	"mtdparts=sc520_spunk-0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Device drivers
- */
-#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-
-/************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR       0
-#define CFG_ATA_IDE0_OFFSET	0x01f0	/* ide0 offset */
-#define CFG_ATA_IDE1_OFFSET	0xe000	/* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
-
-#define CFG_FIRST_PCMCIA_BUS    1
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
-#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
-
-#define CONFIG_IDE_TI_CARDBUS
-#define CFG_PCMCIA_CIS_WIN          0x27f00000
-#define CFG_PCMCIA_CIS_WIN_SIZE     0x00100000
-#define CFG_PCMCIA_IO_WIN           0xe000
-#define CFG_PCMCIA_IO_WIN_SIZE      16
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-
-/************************************************************
- * RTC
- ***********************************************************/
-#define CONFIG_RTC_MC146818
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI                                /* include pci support */
-#define CONFIG_PCI_PNP                            /* pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW
-
-#define	CFG_FIRST_PCI_IRQ   9
-#define	CFG_SECOND_PCI_IRQ  10
-#define	CFG_THIRD_PCI_IRQ   11
-#define	CFG_FORTH_PCI_IRQ   12
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h
deleted file mode 100644
index 2e7a7e1fa2..0000000000
--- a/include/configs/sc520_spunk_rel.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _outer_config
-#define _outer_config
-
-#include "sc520_spunk.h"
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND	"fsload boot/vmlinuz ; bootm"
-
-#endif
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
deleted file mode 100644
index a4249c47c6..0000000000
--- a/include/configs/scb9328.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- * 2003/13/06 Initial MP10 Support copied from wepep250
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARM920T		1     /* this is an ARM920T CPU	    */
-#define CONFIG_IMX		1     /* in a Motorola MC9328MXL Chip */
-#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
-#undef	CONFIG_USE_IRQ		      /* don't need use IRQ/FIQ	   */
-
-#define CONFIG_IMX_SERIAL1
-/*
- * Select serial console configuration
- */
-
-
-/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
- */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
-				& ~CFG_CMD_LOADS	\
-				& ~CFG_CMD_CONSOLE	\
-				& ~CFG_CMD_AUTOSCRIPT	\
-				| CFG_CMD_NET		\
-				| CFG_CMD_PING		\
-				| CFG_CMD_DHCP		\
-				)
-
-#include <cmd_confdefs.h>
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY   -1
-#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
-#define CONFIG_BOOTCOMMAND "bootm 10040000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_ETHADDR		80:81:82:83:84:85
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		10.10.10.9
-#define CONFIG_SERVERIP		10.10.10.10
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CFG_LONGHELP				      /* undef saves memory  */
-#define CFG_PROMPT		"scb9328> "	      /* prompt string	     */
-#define CFG_CBSIZE		256		      /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS		16		      /* max command args    */
-#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
-
-#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
-#define CFG_MEMTEST_END		0x08F00000
-
-#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
-
-#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_BAUDRATE 115200
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
-#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
-#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + (128<<10) )
-
-
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack		     */
-#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack		     */
-#endif
-
-/* SDRAM Setup Values
-0x910a8300 Precharge Command CAS 3
-0x910a8200 Precharge Command CAS 2
-
-0xa10a8300 AutoRefresh Command CAS 3
-0xa10a8200 Set AutoRefresh Command CAS 2 */
-
-#define PRECHARGE_CMD 0x910a8200
-#define AUTOREFRESH_CMD 0xa10a8200
-
-/*
- * SDRAM Memory Map
- */
-/* SH FIXME */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
-#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
-#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
-
-/*
- * Flash Controller settings
- */
-
-/*
- * Hardware drivers
- */
-
-
-/*
- * Configuration for FLASH memory for the Synertronixx board
- */
-
-/* #define SCB9328_FLASH_32M */
-
-/* 32MB */
-#ifdef SCB9328_FLASH_32M
-#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
-#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
-#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
-#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
-#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
-#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
-#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
-#else
-
-/* 16MB */
-#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
-#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
-#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
-#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
-#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
-#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
-#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
-#endif /* SCB9328_FLASH_32M */
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef	CFG_FLASH_CFI
-
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
-
-#define CFG_FLASH_BASE		SCB9328_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
- */
-#define CFG_JFFS2_FIRST_BANK		0
-#define CFG_JFFS2_FIRST_SECTOR		5
-#define CFG_JFFS2_NUM_BANKS		1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-/* Setup for PA23 which is Reset Default PA23 but has to become
-   CS5 */
-
-#define CFG_GPR_A_VAL		0x00800000
-#define CFG_GIUS_A_VAL		0x0043fffe
-
-#define CFG_MONITOR_BASE	0x10000000
-#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
-#define CFG_ENV_SIZE		0x20000
-
-#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */
-
-/*
- * CSxU_VAL:
- * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
- *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
- *
- * CSxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
- *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
- */
-
-#define CFG_CS0U_VAL 0x000F2000
-#define CFG_CS0L_VAL 0x11110d01
-#define CFG_CS1U_VAL 0x000F0a00
-#define CFG_CS1L_VAL 0x11110601
-#define CFG_CS2U_VAL 0x0
-#define CFG_CS2L_VAL 0x0
-
-#define CFG_CS3U_VAL 0x000FFFFF
-#define CFG_CS3L_VAL 0x00000303
-
-#define CFG_CS4U_VAL 0x000F0a00
-#define CFG_CS4L_VAL 0x11110301
-
-/* CNC == 3 too long
-   #define CFG_CS5U_VAL 0x0000C210 */
-
-/* #define CFG_CS5U_VAL 0x00008400
-   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
-   kaum langsamer ist */
-/* #define CFG_CS5U_VAL 0x00009400
-   #define CFG_CS5L_VAL 0x11010D03 */
-
-#define CFG_CS5U_VAL 0x00008400
-#define CFG_CS5L_VAL 0x00000D03
-
-#define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DM9000_BASE		0x16000000
-#define DM9000_IO			CONFIG_DM9000_BASE
-#define DM9000_DATA			(CONFIG_DM9000_BASE+4)
-/* #define CONFIG_DM9000_USE_8BIT */
-#define CONFIG_DM9000_USE_16BIT
-/* #define CONFIG_DM9000_USE_32BIT */
-
-/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
-   f_ref=16,777MHz
-
-   0x002a141f: 191,9944MHz
-   0x040b2007: 144MHz
-   0x042a141f: 96MHz
-   0x0811140d: 64MHz
-   0x040e200e: 150MHz
-   0x00321431: 200MHz
-
-   0x08001800: 64MHz mit 16er Quarz
-   0x04001800: 96MHz mit 16er Quarz
-   0x04002400: 144MHz mit 16er Quarz
-
-   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
-      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
-
-#define CPU200
-
-#ifdef CPU200
-#define CFG_MPCTL0_VAL 0x00321431
-#else
-#define CFG_MPCTL0_VAL 0x040e200e
-#endif
-
-/* #define BUS64 */
-#define BUS72
-
-#ifdef BUS72
-#define CFG_SPCTL0_VAL 0x04002400
-#endif
-
-#ifdef BUS96
-#define CFG_SPCTL0_VAL 0x04001800
-#endif
-
-#ifdef BUS64
-#define CFG_SPCTL0_VAL 0x08001800
-#endif
-
-/* Das ist der BCLK Divider, der aus der System PLL
-   BCLK und HCLK erzeugt:
-   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
-   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
-   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
-   0x2f001003 : 192MHz/5=38,4MHz
-   0x2f000003 : 64MHz/1
-   Bit 22: SPLL Restart
-   Bit 21: MPLL Restart */
-
-#ifdef BUS64
-#define CFG_CSCR_VAL 0x2f030003
-#endif
-
-#ifdef BUS72
-#define CFG_CSCR_VAL 0x2f030403
-#endif
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CFG_LOAD_ADDR 0x08400000
-
-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-
-/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
-#define CFG_FMCR_VAL 0x00000001
-
-/* Bit[0:3] contain PERCLK1DIV for UART 1
-   0x000b00b ->b<- -> 192MHz/12=16MHz
-   0x000b00b ->8<- -> 144MHz/09=16MHz
-   0x000b00b ->3<- -> 64MHz/4=16MHz */
-
-#ifdef BUS96
-#define CFG_PCDR_VAL 0x000b00b5
-#endif
-
-#ifdef BUS64
-#define CFG_PCDR_VAL 0x000b00b3
-#endif
-
-#ifdef BUS72
-#define CFG_PCDR_VAL 0x000b00b8
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
deleted file mode 100644
index 572985b051..0000000000
--- a/include/configs/shannon.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Since we use the Inferno-Loader to bring us to live,
- * we skip the lowlevel init stuff.
- * But U-Boot still relocates itself into RAM
- */
-#define CONFIG_INFERNO			/* we are using the inferno bootldr */
-#define CONFIG_SKIP_LOWLEVEL_INIT	1
-#undef  CONFIG_SKIP_RELOCATE_UBOOT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1100		1	/* This is an SA1100 CPU	*/
-#define CONFIG_SHANNON		1	/* on an SHANNON/TuxScreen Board      */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_3C589	1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL3          1	/* we use SERIAL 3  */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
-				 CFG_CMD_PCMCIA	| \
-				 CFG_CMD_IDE)
-#endif /* 0 */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
-#define CONFIG_NETMASK          255.255.0.0
-#define CONFIG_BOOTCOMMAND	"help"
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"TuxScreen # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0xd0000000	/* default load address	*/
-
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x09		/* 190 MHz for Shannon */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_DOS_PARTITION	1		/* DOS partitiion support */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-/* BE CAREFUL */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of EDORAM */
-#define PHYS_SDRAM_1		0xc0000000 /* RAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00400000 /* 4 MB */
-#define PHYS_SDRAM_2		0xc8000000 /* RAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00400000 /* 4 MB */
-#define PHYS_SDRAM_3            0xd0000000 /* RAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE       0x00400000 /* 4 MB */
-#define PHYS_SDRAM_4            0xd8000000 /* RAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE       0x00400000 /* 4 MB */
-
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(31+4)	/* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_INFERNO
-/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x003E0000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#else
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-
-/* we pick the upper one */
-
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CFG_PCMCIA_IO_ADDR	(0x20000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0x24000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0x2C000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_MEM_ADDR	(0x28000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-
-/* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-/* it's simple, all regs are in I/O space */
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_ATTRB_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0
-
-/*-----------------------------------------------------------------------
- */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
deleted file mode 100644
index a137f9d7c9..0000000000
--- a/include/configs/smdk2400.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- *
- * Configuation settings for the SAMSUNG board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an ARM920T core	*/
-#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
-#define CONFIG_SMDK2400		1	/* on an SAMSUNG SMDK2400 Board */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000 /* SMDK2400 has 12 MHz input clock */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SAMSUNG */
-
-#undef	CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
-
-#undef	CONFIG_MODEM_SUPPORT		/* enable modem initialization stuff */
-
-/*
- * The following enables modem debugging stuff. The dbg() and
- * 'char screen[1024]' are used for debug printfs. Unfortunately,
- * it is usable only from BDI
- */
-#undef CONFIG_MODEM_SUPPORT_DEBUG
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
-
-/* Use s3c2400's RTC */
-#define CONFIG_RTC_S3C24X0	1
-
-#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS_tmp    ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
-				CFG_CMD_DATE	| \
-				CFG_CMD_SNTP	)
-#else
-#define CONFIG_COMMANDS_tmp    (CONFIG_CMD_DFL	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_SNTP	)
-#endif
-
-#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS		(CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW)
-#else
-#define CONFIG_COMMANDS		CONFIG_COMMANDS_tmp
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-#if 0
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#endif
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		134.98.93.36
-#define CONFIG_SERVERIP		134.98.93.22
-#if 0
-#define CONFIG_BOOTFILE		"elinos-lart"
-#define CONFIG_BOOTCOMMAND	"tftp; bootm"
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"SMDK2400 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0c000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0e000000	/* 32 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x0cf00000	/* default load address	*/
-
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x0c000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-
-#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
-#define CFG_ENV_SIZE		0x40000
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
deleted file mode 100644
index 7edec0db43..0000000000
--- a/include/configs/smdk2410.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the SAMSUNG SMDK2410 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
-#define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
-
-
-#define USE_920T_MMU		1
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x19000300
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */
-
-/************************************************************
- * RTC
- ************************************************************/
-#define	CONFIG_RTC_S3C24X0	1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
-			(CONFIG_CMD_DFL	 | \
-			CFG_CMD_CACHE	 | \
-			/*CFG_CMD_NAND	 |*/ \
-			/*CFG_CMD_EEPROM |*/ \
-			/*CFG_CMD_I2C	 |*/ \
-			/*CFG_CMD_USB	 |*/ \
-			CFG_CMD_REGINFO  | \
-			CFG_CMD_DATE	 | \
-			CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
-/*#define CONFIG_ETHADDR	08:00:3e:26:0a:5b */
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		10.0.0.110
-#define CONFIG_SERVERIP		10.0.0.1
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"SMDK2410 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
-
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
-
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-#endif
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
deleted file mode 100644
index 625cf20144..0000000000
--- a/include/configs/stxgp3.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * (C) Copyright 2003 Embedded Edge, LLC
- * Dan Malek <dan@embeddededge.com>
- * Copied from ADS85xx.
- * Updates for Silicon Tx GP3 8560 board.
- *
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE		1	/* BOOKE		*/
-#define CONFIG_E500		1	/* BOOKE e500 family	*/
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
-#define CONFIG_CPM2		1	/* has CPM2 */
-#define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
-
-#undef  CONFIG_PCI	         	/* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
-#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-
-/* sysclk for MPC85xx
- */
-
-#define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
-
-/* Blinkin' LEDs for Robert :-)
-*/
-#define CONFIG_SHOW_ACTIVITY 1
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
-#define  CONFIG_BTB                          /* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
-
-#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
-
-#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
-#define CFG_MEMTEST_START       0x00200000  /* memtest region */
-#define CFG_MEMTEST_END         0x00400000
-
-
-/* Localbus SDRAM is an option, not all boards have it.
- * This address, however, is used to configure a 256M local bus
- * window that includes the Config latch below.
- */
-#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
-
-#define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
-#define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
-
-#define CFG_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	136		/* sectors per device   */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/* The configuration latch is Chip Select 1.
- * It's an 8-bit latch in the lower 8 bits of the word.
- */
-#define CFG_BR1_PRELIM		0xfc001801	/* 32-bit port */
-#define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
-#define CFG_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
-
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
-#else
-#undef  CFG_RAMBOOT
-#endif
-
-#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 	0x40000000	/* CCSRBAR by BDI cfg	*/
-#else
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#endif
-#define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
-
-
-/*
- * DDR Setup
- */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-
-#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
-#define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_ON_SCC              	/* define if console on SCC */
-#undef  CONFIG_CONS_NONE                	/* define if console on something else */
-#define CONFIG_CONS_INDEX       2       	/* which serial channel for console */
-
-#define CONFIG_BAUDRATE	 	38400
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#if 0
-#define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
-#else
-/* I did the 'if 0' so we could keep the syntax above if ever needed. */
-#undef CFG_I2C_NOPROBES
-#endif
-#define CFG_I2C_OFFSET		0x3000
-
-/* RapdIO Map configuration, mapped 1:1.
-*/
-#define CFG_RIO_MEM_BASE	0xc0000000
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x200000000	/* 512 M */
-
-/* Standard 8560 PCI addressing, mapped 1:1.
-*/
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16 M */
-
-#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR    	0xe0000000
-  #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
-#endif
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
-#undef CONFIG_MPS85XX_FEC
-
-#define TSEC1_PHY_ADDR		2
-#define TSEC2_PHY_ADDR		4
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
-
-#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
-#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
-#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
-
-#if (CONFIG_ETHER_INDEX == 2)
-  /*
-   * - Rx-CLK is CLK13
-   * - Tx-CLK is CLK14
-   * - Select bus for bd/buffers
-   * - Full duplex
-   */
-  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE    0
-#if 0
-  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
-#else
-  #define CFG_FCC_PSMR          0
-#endif
-  #define FETH2_RST		0x01
-#elif (CONFIG_ETHER_INDEX == 3)
-  /* need more definitions here for FE3 */
-  #define FETH3_RST		0x80
-#endif  				/* CONFIG_ETHER_INDEX */
-
-/* MDIO is done through the TSEC0 control.
-*/
-#define CONFIG_MII			/* MII PHY management */
-#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-
-#endif
-
-/* Environment */
-/* We use the top boot sector flash, so we have some 16K sectors for env
- */
-#ifndef CFG_RAMBOOT
-  #define CFG_ENV_IS_IN_FLASH	1
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
-  #define CFG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
-  #define CFG_ENV_SIZE		0x2000
-#else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
-  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-  #define CFG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
-#define CONFIG_BOOTCOMMAND	"bootm 0xff000000 0xff100000"
-#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#if defined(CFG_RAMBOOT)
-  #if defined(CONFIG_PCI)
-  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
-				CFG_CMD_PING | CFG_CMD_I2C) & \
-				 ~(CFG_CMD_ENV | \
-				  CFG_CMD_LOADS ))
-  #elif defined(CONFIG_TSEC_ENET)
-  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | \
-				CFG_CMD_MII | CFG_CMD_I2C ) & \
-				~(CFG_CMD_ENV))
-  #elif defined(CONFIG_ETHER_ON_FCC)
-  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
-				CFG_CMD_PING | CFG_CMD_I2C) & \
-				~(CFG_CMD_ENV))
-  #endif
-#else
-  #if defined(CONFIG_PCI)
-  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
-				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
-  #elif defined(CONFIG_TSEC_ENET)
-  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | \
-				CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
-  #elif defined(CONFIG_ETHER_ON_FCC)
-  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
-				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
-  #endif
-#endif
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE		32768
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
-#endif
-
-#define CONFIG_SERVERIP 	192.168.85.1
-#define CONFIG_IPADDR  		192.168.85.60
-#define CONFIG_GATEWAYIP	192.168.85.1
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_HOSTNAME 	STX_GP3
-#define CONFIG_ROOTPATH 	/gppproot
-#define CONFIG_BOOTFILE 	uImage
-#define CONFIG_LOADADDR		0x1000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
deleted file mode 100644
index 1ee6be174f..0000000000
--- a/include/configs/suzaku.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MICROBLAZE	1	/* This is an MicroBlaze CPU	*/
-#define CONFIG_SUZAKU		1	/* on an SUZAKU Board		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x80000000
-#define CFG_SDRAM_SIZE		0x01000000
-#define CFG_FLASH_BASE		0xfff00000
-#define CFG_FLASH_SIZE		0x00400000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE        (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 115200 }
-
-#define CONFIG_COMMANDS		(CONFIG__CMD_DFL)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_UART1_BASE		(0xFFFF2000)
-#define CONFIG_SERIAL_BASE	CFG_UART1_BASE
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"SUZAKU> "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* default load address		*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	1	/* max number of sectors on one chip	*/
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_ENV_IS_NOWHERE	1
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CFG_INIT_RAM_ADDR	0x80000000	/* inside of SDRAM */
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
deleted file mode 100644
index 92ee8cb333..0000000000
--- a/include/configs/svm_sc8xx.h
+++ /dev/null
@@ -1,471 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific,
- *                  for SinoVee Microsystems SC8xx series SBC
- *                  http://www.fel.com.cn (Chinese)
- *                  http://www.sinovee.com (English)
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Custom configuration */
-/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
-/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
-/*#define CONFIG_FEL8xx_AT */
-/*#define CONFIG_LCD */
-/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
-/* #define CONFIG_50MHz */
-/* #define CONFIG_66MHz */
-/* #define CONFIG_75MHz */
-#define CONFIG_80MHz
-/*#define CONFIG_100MHz */
-/* #define CONFIG_BUS_DIV2	1 */
-/* for BOOT device port size */
-/* #define CONFIG_BOOT_8B */
-#define CONFIG_BOOT_16B
-/* #define CONFIG_BOOT_32B */
-/* #define CONFIG_CAN_DRIVER */
-/* #define DEBUG */
-#define CONFIG_FEC_ENET
-
-/* #define CONFIG_SDRAM_16M */
-#define CONFIG_SDRAM_32M
-/* #define CONFIG_SDRAM_64M */
-#define CFG_RESET_ADDRESS 0xffffffff
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* #define CONFIG_MPC823		1 */
-/* #define CONFIG_MPC850		1 */
-#define CONFIG_MPC855		1
-/* #define CONFIG_MPC860		1 */
-/* #define CONFIG_MPC860T		1 */
-
-#undef	CONFIG_WATCHDOG			/* watchdog */
-
-#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series 	*/
-
-#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
-/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
-#endif
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		19200	/* console baudrate = 115kbps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES      1       /* support board types          */
-
-#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS                                       \
-	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-	 "nfsroot=${serverip}:${rootpath}\0"                     \
-	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-	"addip=setenv bootargs ${bootargs} "                            \
-	       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
-		":${hostname}:${netdev}:off panic=1\0"                  \
-		"flash_nfs=run nfsargs addip;"                                  \
-	     "bootm ${kernel_addr}\0"                                \
-	"flash_self=run ramargs addip;"                                 \
-	       "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-	"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0"     \
-	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
-	"bootfile=pImage-sc855t\0"                           \
-	"kernel_addr=48000000\0"                                        \
-	"ramdisk_addr=48100000\0"                                       \
-	""
-#define CONFIG_BOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-
-#ifdef CONFIG_LCD
-# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
-#else
-# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-#endif	/* CONFIG_LCD */
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV  | \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DOC	| \
-/*				CFG_CMD_IDE     |*/ \
-				CFG_CMD_DATE	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CFG_NAND_LEGACY
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-#ifdef CONFIG_BOOT_8B
-#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-#elif defined (CONFIG_BOOT_16B)
-#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
-#elif defined (CONFIG_BOOT_32B)
-#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-
-/* Address and size of Redundant Environment Sector     */
-#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
-
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-/*#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-*/
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR 0xffffff88
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-/*#define CFG_SIUMCR 0x00610c00	*/
-#define CFG_SIUMCR 0x00000000
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	0x0001
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CFG_RTCSC	0x00c3
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR	0x0000
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#if defined (CONFIG_100MHz)
-#define CFG_PLPRCR 0x06301000
-#define CONFIG_8xx_GCLK_FREQ 100000000
-#elif defined (CONFIG_80MHz)
-#define CFG_PLPRCR 0x04f01000
-#define CONFIG_8xx_GCLK_FREQ 80000000
-#elif defined(CONFIG_75MHz)
-#define CFG_PLPRCR 0x04a00100
-#define CONFIG_8xx_GCLK_FREQ 75000000
-#elif defined(CONFIG_66MHz)
-#define CFG_PLPRCR 0x04101000
-#define CONFIG_8xx_GCLK_FREQ 66000000
-#elif defined(CONFIG_50MHz)
-#define CFG_PLPRCR 0x03101000
-#define CONFIG_8xx_GCLK_FREQ 50000000
-#endif
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_BUS_DIV2
-#define CFG_SCCR	0x02020000 | SCCR_RTSEL
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR    0x02000000 | SCCR_RTSEL
-#endif
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD   	/* Use IDE with PC Card	Adapter	*/
-
-#define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1 	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_BASE_ADDR       0xFE100010
-#define CFG_ATA_IDE0_OFFSET     0x0000
-/*#define CFG_ATA_IDE1_OFFSET     0x0C00 */
-#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
-					   */
-#define CFG_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
-					   */
-#define CFG_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
-					   */
-#define CONFIG_ATAPI
-#define CFG_PIO_MODE 0
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0x0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#if defined(CONFIG_100MHz)
-#define CFG_OR_TIMING_FLASH 0x000002f4
-#define CFG_OR_TIMING_DOC   0x000002f4
-#define CFG_MxMR_PTx 0x61000000
-#define CFG_MPTPR 0x400
-
-#elif  defined(CONFIG_80MHz)
-#define CFG_OR_TIMING_FLASH 0x00000ff4
-#define CFG_OR_TIMING_DOC   0x000001f4
-#define CFG_MxMR_PTx 0x4e000000
-#define CFG_MPTPR 0x400
-
-#elif defined(CONFIG_75MHz)
-#define CFG_OR_TIMING_FLASH 0x000008f4
-#define CFG_OR_TIMING_DOC   0x000002f4
-#define CFG_MxMR_PTx 0x49000000
-#define CFG_MPTPR 0x400
-
-#elif defined(CONFIG_66MHz)
-#define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-	OR_SCY_3_CLK | OR_EHTR | OR_BI)
-/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
-#define CFG_OR_TIMING_DOC   0x000003f4
-#define CFG_MxMR_PTx  0x40000000
-#define CFG_MPTPR 0x400
-
-#else		/*   50 MHz */
-#define CFG_OR_TIMING_FLASH 0x00000ff4
-#define CFG_OR_TIMING_DOC   0x000001f4
-#define CFG_MxMR_PTx  0x30000000
-#define CFG_MPTPR 0x400
-#endif	/*CONFIG_??MHz */
-
-
-#if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
-#define CFG_OR0_PRELIM	(0xffe00000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
-#elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
-#define CFG_OR0_PRELIM	(0xffc00000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
-#define CFG_OR0_PRELIM	(0xfc000000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-#else
-#error Boot device port size missing.
-#endif
-
-/*
- * Disk-On-Chip configuration
- */
-
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
-
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#define CFG_DOC_BASE 0x80000000
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
deleted file mode 100644
index dac1eb736d..0000000000
--- a/include/configs/tb0229.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003
- * Masami Komiya <mkomiya@sonare.it>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Config header file for TANBAC TB0229 board using an VR4131 CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
-#define CONFIG_TB0229		1	/* on a TB0229 Board	*/
-
-#ifndef CPU_CLOCK_RATE
-#define CPU_CLOCK_RATE	200000000	/* 200 MHz clock for the MIPS core */
-#endif
-#define CPU_TCLOCK_RATE 16588800	/* 16.5888 MHz for TClock */
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
-	"echo Type \"run netboot_initrd\" for the network boot with initrd;" \
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo Type \"run flash_local\" to mount local root filesystem;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netboot=dhcp;tftp;run netargs; bootm\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0"		\
-	"localargs=setenv bootargs root=1F02 ip=dhcp\0"			\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"read-only=readonly\0"					\
-	"netargs=run nfsargs addmisc\0"					\
-	"flash_nfs=run nfsargs addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_local=run localargs addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;"		\
-		"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
-		"run addmisc;"						\
-		"bootm 80400000 80600000\0"				\
-	"rootpath=/export/miniroot-mipsel\0"				\
-	"autoload=no\0"							\
-	"kernel_addr=BFC60000\0"					\
-	"ramdisk_addr=B0100000\0"					\
-	"u-boot=u-boot.bin\0"						\
-	"bootfile=uImage\0"						\
-	"load=dhcp;tftp 80400000 ${u-boot}\0"				\
-	"load_kernel=dhcp;tftp 80400000 ${bootfile}\0"			\
-	"update_uboot=run load;"					\
-		"protect off BFC00000 BFC3FFFF;"			\
-		"erase BFC00000 BFC3FFFF;"				\
-		"cp.b 80400000 BFC00000 ${filesize}\0"			\
-	"update_kernel=run load_kernel;"				\
-		"erase BFC60000 BFD5FFFF;"				\
-		"cp.b 80400000 BFC60000 ${filesize}\0"			\
-	"initenv=erase bfc40000 bfc5ffff\0"				\
-	""
-/*#define CONFIG_BOOTCOMMAND	"run flash_local" */
-#define CONFIG_BOOTCOMMAND	"run netboot"
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_ASKENV | \
-				 CFG_CMD_DHCP	| \
-				 CFG_CMD_PING	| \
-				 CFG_CMD_PCI	| \
-				 CFG_CMD_ELF	)
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory	     */
-#define CFG_PROMPT		"# "		/* Monitor Command Prompt    */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args*/
-
-#define CFG_MALLOC_LEN		128*1024
-
-#define CFG_BOOTPARAMS_LEN	128*1024
-
-#define CFG_HZ			(CPU_TCLOCK_RATE/4)
-
-#define CFG_SDRAM_BASE		0x80000000
-
-#define CFG_LOAD_ADDR		0x80400000	/* default load address */
-
-#define CFG_MEMTEST_START	0x80000000
-#define CFG_MEMTEST_END		0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)
-
-#define CFG_INIT_SP_OFFSET	0x400000
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CFG_ENV_ADDR		0xBFC40000
-#define CFG_ENV_SIZE		0x20000
-
-#define CFG_DIRECT_FLASH_TFTP
-
-#define CONFIG_NR_DRAM_BANKS	1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	 1
-#define CFG_NS16550_CLK		 18432000
-#define CFG_NS16550_COM1	 0xaf000800
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_NET_MULTI
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-
-#define CONFIG_RTL8139
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/trab.h b/include/configs/trab.h
deleted file mode 100644
index a2dc8e7bff..0000000000
--- a/include/configs/trab.h
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * (C) Copyright 2002-2005
- * Gary Jennejohn <gj@denx.de>
- *
- * Configuation settings for the TRAB board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Default configuration is with 8 MB Flash, 32 MB RAM
- */
-#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB))
-# define CONFIG_FLASH_8MB	/*  8 MB Flash	*/
-#endif
-#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB))
-# define CONFIG_RAM_32MB	/* 32 MB SDRAM	*/
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an arm920t CPU	*/
-#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
-#define CONFIG_TRAB		1	/* on a TRAB Board		*/
-#undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
-#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
-
-/* automatic software updates (see board/trab/auto_update.c) */
-#define CONFIG_AUTO_UPDATE	1
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
-#define CONFIG_SILENT_CONSOLE	 1	/* enable silent startup	*/
-
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
-
-/***********************************************************
- * I2C stuff:
- * the TRAB is equipped with an ATMEL 24C04 EEPROM at
- * address 0x54 with 8bit addressing
- ***********************************************************/
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED 		100000	/* I2C speed */
-#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
-
-#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
-
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* USB stuff */
-#define CONFIG_USB_OHCI		1
-#define CONFIG_USB_STORAGE	1
-#define CONFIG_DOS_PARTITION	1
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
-
-#define CONFIG_DRIVER_S3C24X0_I2C 1	/* we use the buildin I2C controller */
-
-#define CONFIG_VFD		1	/* VFD linear frame buffer driver */
-#define VFD_TEST_LOGO		1	/* output a test logo to the VFDs */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on TRAB */
-
-#define CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
-
-#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
-
-#define	CONFIG_MODEM_KEY_MAGIC	"23"	/* hold down these keys to enable modem */
-
-/*
- * The following enables modem debugging stuff. The dbg() and
- * 'char screen[1024]' are used for debug printfs. Unfortunately,
- * it is usable only from BDI
- */
-#undef CONFIG_MODEM_SUPPORT_DEBUG
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
-
-/* Use s3c2400's RTC */
-#define CONFIG_RTC_S3C24X0	1
-
-#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS_ADD_HWFLOW	CFG_CMD_HWFLOW
-#else
-#define	CONFIG_COMMANDS_ADD_HWFLOW	0
-#endif
-
-#ifdef	CONFIG_VFD
-#define CONFIG_COMMANDS_ADD_VFD		CFG_CMD_VFD
-#else
-#define CONFIG_COMMANDS_ADD_VFD		0
-#endif
-
-#ifdef CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_COMMANDS_ADD_EEPROM	CFG_CMD_EEPROM
-#define CONFIG_COMMANDS_I2C		CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS_ADD_EEPROM	0
-#define CONFIG_COMMANDS_I2C		0
-#endif
-
-#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
-				CONFIG_COMMANDS_ADD_HWFLOW	| \
-				CONFIG_COMMANDS_ADD_VFD		| \
-				CONFIG_COMMANDS_ADD_EEPROM	| \
-				CONFIG_COMMANDS_I2C		| \
-				CFG_CMD_BSP			| \
-				CFG_CMD_DATE			| \
-				CFG_CMD_DHCP			| \
-				CFG_CMD_FAT			| \
-				CFG_CMD_NFS			| \
-				CFG_CMD_SNTP			| \
-				CFG_CMD_USB	)
-#else
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL			| \
-				CONFIG_COMMANDS_ADD_HWFLOW	| \
-				CONFIG_COMMANDS_ADD_VFD		| \
-				CONFIG_COMMANDS_ADD_EEPROM	| \
-				CONFIG_COMMANDS_I2C		| \
-				CFG_CMD_BSP			| \
-				CFG_CMD_DATE			| \
-				CFG_CMD_DHCP			| \
-				CFG_CMD_FAT			| \
-				CFG_CMD_NFS			| \
-				CFG_CMD_SNTP			| \
-				CFG_CMD_USB	)
-#endif
-
-/* moved up */
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
-#define CONFIG_PREBOOT		"echo;echo *** booting ***;echo"
-#define CONFIG_BOOTARGS		"console=ttyS0"
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.3.68
-#define CONFIG_HOSTNAME		trab
-#define CONFIG_SERVERIP		192.168.3.1
-#define CONFIG_BOOTCOMMAND	"burn_in"
-
-#ifndef CONFIG_FLASH_8MB	/* current config: 16 MB flash */
-#ifdef CFG_HUSH_PARSER
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$serverip:$rootpath\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 5FFFF;era 0 5FFFF;" \
-		"cp.b C100000 0 $filesize\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
-	"net_load=tftpboot $loadaddr $loadfile\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00060000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#else /* !CFG_HUSH_PARSER */
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath}\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
-	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 5FFFF;era 0 5FFFF;" \
-		"cp.b C100000 0 ${filesize}\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
-	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#endif	/* CFG_HUSH_PARSER */
-#else	/* CONFIG_FLASH_8MB 	 => 8 MB flash */
-#ifdef CFG_HUSH_PARSER
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$serverip:$rootpath\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 3FFFF;era 0 3FFFF;" \
-		"cp.b C100000 0 $filesize;" \
-		"setenv filesize;saveenv\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=C400000\0" \
-	"net_load=tftpboot $loadaddr $loadfile\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#else /* !CFG_HUSH_PARSER */
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath}\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
-	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 3FFFF;era 0 3FFFF;" \
-		"cp.b C100000 0 ${filesize};" \
-		"setenv filesize;saveenv\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=C400000\0" \
-	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#endif /* CFG_HUSH_PARSER */
-#endif	/* CONFIG_FLASH_8MB */
-
-#if 1	/* feel free to disable for development */
-#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
-#define CONFIG_AUTOBOOT_PROMPT	"\nEnter password - autoboot in %d sec...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR	"R"	/* 1st "password"	*/
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0C000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
-
-#undef CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x0CF00000	/* default load address	*/
-
-#ifdef CONFIG_TRAB_50MHZ
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define	CFG_HZ			1562500
-#else
-/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
-/* it to wrap 100 times (total 1039000) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define	CFG_HZ			1039000
-#endif
-
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
-
-/*-----------------------------------------------------------------------
- * burn-in test stuff.
- *
- * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle
- * Because the burn-in test itself causes also an delay of about 4 seconds,
- * this time must be subtracted from the desired overall burn-in cycle time.
- */
-#define BURN_IN_CYCLE_DELAY	296	/* seconds between burn-in cycles */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x0C000000	/* SDRAM Bank #1 */
-#ifndef CONFIG_RAM_16MB
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-#else
-#define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
-#endif
-
-#define CFG_FLASH_BASE		0x00000000	/* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)
-
-/* Dynamic MTD partition support */
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=0"
-
-/* production flash layout */
-#define MTDPARTS_DEFAULT	"mtdparts=0:16k(Firmware1)ro,"		\
-						"16k(Env1),"		\
-						"16k(Env2),"		\
-						"336k(Firmware2)ro,"	\
-						"896k(Kernel),"		\
-						"5376k(Root-FS),"	\
-						"1408k(JFFS2),"		\
-						"-(VFD)"
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifndef CONFIG_FLASH_8MB
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#else
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
-#endif
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(15*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
-
-#define	CFG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#ifndef CONFIG_FLASH_8MB
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_SECT_SIZE	0x20000
-#else
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_SECT_SIZE	0x4000
-#endif
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-
-/* Initial value of the on-board touch screen brightness */
-#define CFG_BRIGHTNESS 0x20
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
deleted file mode 100644
index e5d4397d2c..0000000000
--- a/include/configs/utx8245.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen@arlut.utexas.edu
- * Matthew E. Karger, karger@arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas at Austin
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the utx8245 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8245		1
-#define CONFIG_UTX8245		1
-#define DEBUG				1
-
-#define CONFIG_IDENT_STRING     " [UTX5] "
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		57600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_AUTOBOOT_PROMPT 	"autoboot in %d seconds\n"
-#define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
-#define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
-#define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
-#define CONFIG_SERVERIP		10.8.17.105	/* Spree */
-#define CFG_TFTP_LOADADDR	10000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr=FFA00000\0" \
-	"ramdisk_addr=FF800000\0" \
-	"u-boot_startaddr=FFB00000\0" \
-	"u-boot_endaddr=FFB2FFFF\0" \
-	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
-nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
-	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
-	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
-	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
-	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
-	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
-${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
-${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
-protect on ${u-boot_startaddr} ${u-boot_endaddr}"
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_COMMANDS		(CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
-								| CFG_CMD_FLASH | CFG_CMD_MEMORY \
-								| CFG_CMD_ENV | CFG_CMD_CONSOLE \
-								| CFG_CMD_LOADS | CFG_CMD_LOADB \
-								| CFG_CMD_IMI | CFG_CMD_CACHE \
-								| CFG_CMD_REGINFO | CFG_CMD_NET\
-								| CFG_CMD_DHCP | CFG_CMD_I2C \
-								| CFG_CMD_DATE)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_NET_MULTI
-#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR	0xF0000000
-#define PCI_ENET0_MEMADDR	0xF0000000
-
-#define PCI_FIREWIRE_IOADDR		0xF1000000
-#define PCI_FIREWIRE_MEMADDR	0xF1000000
-/*
-#define PCI_ENET0_IOADDR	0xFE000000
-#define PCI_ENET0_MEMADDR	0x80000000
-
-#define PCI_FIREWIRE_IOADDR	0x81000000
-#define PCI_FIREWIRE_MEMADDR	0x81000000
-*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 256MB  */
-/*#define CFG_VERY_BIG_RAM	1 */
-
-/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
- * is actually located at FFF00100.  Therefore, U-Boot is
- * physically located at 0xFFB0_0000, but is also mirrored at
- * 0xFFF0_0000.
- */
-#define CFG_RESET_ADDRESS   0xFFF00100
-
-#define CFG_EUMB_ADDR	    0xFC000000
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-/*#define CFG_DRAM_TEST		1 */
-#define CFG_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
-#define CFG_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
-										/* vectors and U-Boot */
-
-
-/*--------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- *------------------------------------------------------------------*/
-#define CFG_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
-									/* initial data */
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_INIT_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-
-/*--------------------------------------------------------------------
- * NS16550 Configuration
- *------------------------------------------------------------------*/
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-
-#define CFG_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
-#	define CFG_NS16550_CLK		get_bus_freq(0)
-#else
-#	define CFG_NS16550_CLK 33000000
-#endif
-
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-#define CFG_NS16550_COM3	0xFF000000
-#define CFG_NS16550_COM4	0xFF000008
-
-/*--------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- *------------------------------------------------------------------*/
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ				1000
-
-/*#define CFG_ETH_DEV_FN	     0x7800 */
-/*#define CFG_ETH_IOBASE	     0x00104000 */
-
-/*--------------------------------------------------------------------
- * I2C Configuration
- *------------------------------------------------------------------*/
-#if 1
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#endif
-
-#define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
-									/* Philips PCF8563 RTC */
-#define CFG_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
-
-/*--------------------------------------------------------------------
- *	Memory Control Configuration Register values
- *	- see sec. 4.12 of MPC8245 UM
- *------------------------------------------------------------------*/
-
-/**** MCCR1 ****/
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
-									mem_freq = 100MHz */
-
-#define CFG_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
-#define CFG_BANK6_ROW	0		/* 	bit count */
-#define CFG_BANK5_ROW	0
-#define CFG_BANK4_ROW	0
-#define CFG_BANK3_ROW	0
-#define CFG_BANK2_ROW	0
-#define CFG_BANK1_ROW	2
-#define CFG_BANK0_ROW	2
-
-/**** MCCR2, refresh interval clock cycles ****/
-#define CFG_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CFG_BSTOPRE	    1023	/* burst to precharge[0..9], */
-								/* sets open page interval */
-
-/**** MCCR3 ****/
-#define CFG_REFREC	    7	    /* Refresh to activate interval, trc */
-
-/**** MCCR4 ****/
-#define CFG_PRETOACT	    2	    /* trp */
-#define CFG_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
-#define CFG_ACTORW	    	2		/* trcd min */
-#define CFG_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    0			/* we don't need extended ROM space */
-#define CFG_REGDIMM	    0
-
-/* calculate according to formula in sec. 6-22 of 8245 UM */
-#define CFG_PGMAX           50		/* how long the 8245 retains the */
-									/* currently accessed page in memory */
-									/* was 45 */
-
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
-								/* bits 7,6, and 3-0 MUST be 0 */
-
-#if 0
-#define CFG_DLL_MAX_DELAY	0x04
-#else
-#define CFG_DLL_MAX_DELAY	0
-#endif
-#if 0							/* need for 33MHz SDRAM */
-#define CFG_DLL_EXTEND	0x80
-#else
-#define CFG_DLL_EXTEND	0
-#endif
-#define CFG_PCI_HOLD_DEL 0x20
-
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these values to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8245 user manual.
- */
-
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE/2 - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    CFG_MAX_RAM_SIZE/2
-#define CFG_BANK1_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK1_ENABLE    1
-#define CFG_BANK2_START	    0x3ff00000		/* not available in this design */
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-/*--------------------------------------------------------------------*/
-/* 4.4 - Output Driver Control Register */
-/*--------------------------------------------------------------------*/
-#define CFG_ODCR	    0xe5
-
-/*--------------------------------------------------------------------*/
-/* 4.8 - Error Handling Registers */
-/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
-#define CFG_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
-
-/* SDRAM 0-256 MB */
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-/*#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in dcache */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-
-#define CFG_IBAT2L  (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U  (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* PCI memory */
-/*#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
-/*#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
-
-/*Flash, config addrs, etc. */
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE	    0xFF800000
-#define CFG_MAX_FLASH_BANKS	1			/* Max number of flash banks */
-
-/*	NOTE: environment is not EMBEDDED in the u-boot code.
-	It's stored in flash in its own separate sector.  */
-#define CFG_ENV_IS_IN_FLASH	    1
-
-#if 1	/* AMD AM29LV033C */
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
-#define CFG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
-#define CFG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
-#else	/* AMD AM29LV116D */
-#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
-#define CFG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
-#define CFG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
-#endif /* #if */
-
-#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE		/* Size of the Environment */
-#define CFG_ENV_OFFSET		0			/* starting right at the beginning */
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
-#else
-#define CFG_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/v37.h b/include/configs/v37.h
deleted file mode 100644
index a2e99b59e2..0000000000
--- a/include/configs/v37.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_V37		1	/* ...on a Marel V37 board 	*/
-
-#define CONFIG_LCD
-#define CONFIG_SHARP_LQ084V1DG21
-#undef CONFIG_LCD_LOGO
-
-/*-----------------------------------------------------------------------------
- * I2C Configuration
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_I2C              1
-#define CFG_I2C_SLAVE           0x2
-
-#define	CONFIG_8xx_CONS_SMC1	1
-#undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 115kbps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs console=tty0 "                                   \
-	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "		 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_DATE	)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor1=v37-1"
-#define MTDPARTS_DEFAULT	"mtdparts=v37-1:-(jffs2)"
-*/
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CFG_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE0		0x40000000
-#define CFG_FLASH_BASE1		0x60000000
-#define CFG_FLASH_BASE		CFG_FLASH_BASE1
-
-#if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE0
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CFG_ENV_IS_IN_NVRAM	1
-#define	CFG_ENV_ADDR		0x80000000/* Address of Environment */
-#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-#define CFG_ENV_OFFSET		0
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CFG_SYPCR	0xFFFFFF88
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
-/*
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
-*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CFG_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
-
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
-
-#define CFG_OR_TIMING_FLASH 	0xF56
-
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-#define CFG_OR5_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
-
-/*
- * BR1 and OR1 (Battery backed SRAM)
- */
-#define	CFG_BR1_PRELIM	0x80000401
-#define CFG_OR1_PRELIM	0xFFC00736
-
-/*
- * BR2 and OR2 (SDRAM)
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */
-
-#define CFG_OR_TIMING_SDRAM	0x00000A00
-
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* Marel V37 mem setting */
-
-#define	CFG_BR3_CAN	0xC0000401
-#define CFG_OR3_CAN	0xFFFF0724
-
-/*
-#define	CFG_BR3_PRELIM	0xFA400001
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define	CFG_BR4_PRELIM	0xFA000401
-#define CFG_OR4_PRELIM	0xFFFE0970
-*/
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/*
- * Refresh clock Prescalar
- */
-#define CFG_MPTPR	MPTPR_PTP_DIV16
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
-			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
deleted file mode 100644
index 16db43bb93..0000000000
--- a/include/configs/versatile.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Versatile PB.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
-#define CONFIG_VERSATILE	1	/* in Versatile Platform Board	*/
-#define CONFIG_ARCH_VERSATILE   1	/* Specifically, a Versatile	*/
-
-
-#define CFG_MEMTEST_START       0x100000
-#define CFG_MEMTEST_END         0x10000000
-#define CFG_HZ                  (1000000 / 256)
-#define CFG_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */
-
-#define CFG_TIMER_INTERVAL	10000
-#define CFG_TIMER_RELOAD	(CFG_TIMER_INTERVAL >> 4)	/* Divide by 16 */
-#define CFG_TIMER_CTRL          0x84				/* Enable, Clock / 16 */
-
-/*
- * control registers
- */
-#define VERSATILE_SCTL_BASE            0x101E0000	/* System controller */
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK	0
-#define VERSATILE_TIMCLK	1
-
-#define VERSATILE_TIMER1_EnSel	15
-#define VERSATILE_TIMER2_EnSel	17
-#define VERSATILE_TIMER3_EnSel	19
-#define VERSATILE_TIMER4_EnSel	21
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE    	0x10010000
-#undef CONFIG_SMC91111_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CFG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK	24000000
-#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
-#define CONFIG_CONS_INDEX	0
-
-#define CONFIG_BAUDRATE         38400
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x101F1000
-#define CFG_SERIAL1		0x101F2000
-
-#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV)
-
-/*#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
-
-#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
-/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
-
-/*
- * Static configuration when assigning fixed address
- */
-/*#define CONFIG_NETMASK	255.255.255.0	/--* talk on MY local net */
-/*#define CONFIG_IPADDR		xx.xx.xx.xx	/--* static IP I currently own */
-/*#define CONFIG_SERVERIP	xx.xx.xx.xx	/--* current IP of my dev pc */
-#define CONFIG_BOOTFILE	    "/tftpboot/uImage" /* file to load */
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP	/* undef to save memory     */
-#define CFG_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args   */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x08000000	/* 128 MB */
-
-#define CFG_FLASH_BASE          0x34000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define VERSATILE_SYS_BASE                    0x10000000
-#define VERSATILE_SYS_FLASH_OFFSET            0x4C
-#define VERSATILE_FLASHCTRL		      (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-#define VERSATILE_FLASHPROG_FLVPPEN	      (1 << 0)	/* Enable writing to flash */
-
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define PHYS_FLASH_SIZE         0x34000000	/* 64MB */
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT	(256)
-
-#define PHYS_FLASH_1		(CFG_FLASH_BASE)
-
-#define CFG_ENV_IS_IN_FLASH     1               /* env in flash instead of CFG_ENV_IS_NOWHERE */
-#define CFG_ENV_SECT_SIZE       0x00020000      /* 256 KB sectors (x2) */
-#define CFG_ENV_SIZE            0x10000         /* Total Size of Environment Sector */
-#define CFG_ENV_OFFSET          0x01f00000      /* environment starts here  */
-#define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_ENV_OFFSET)
-
-#endif							/* __CONFIG_H */
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
deleted file mode 100644
index 28abd6e153..0000000000
--- a/include/configs/walnut.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
-					/* ...and on a SYCAMORE board	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=walnut\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/walnut/uImage\0"				\
-	"kernel_addr=fff80000\0"					\
-	"ramdisk_addr=fff80000\0"					\
-	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"				\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
-#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW		1	/* enable loopw command		*/
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * I2C stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-
-/*
- * Define here the location of the environment variables (FLASH or NVRAM).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- *	 supported for backward compatibility.
- */
-#if 1
-#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0		*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
-
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CFG_FLASH_ADDR0		0x5555
-#define CFG_FLASH_ADDR1		0x2aaa
-#define CFG_FLASH_WORD_SIZE	unsigned char
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CFG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x9B015480
-#define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CFG_EBC_PB1AP		0x02815480
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CFG_EBC_PB2AP		0x04815A80
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CFG_EBC_PB3AP		0x01815280
-#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
-
-#define CFG_EBC_PB7AP		0x01815280
-#define CFG_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#define CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define CFG_IR_REG_BASE_ADDR	0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS	0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
deleted file mode 100644
index 47251bbb64..0000000000
--- a/include/configs/wepep250.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PXA250          1        /* this is an PXA250 CPU     */
-#define CONFIG_WEPEP250        1        /* config for wepep250 board */
-#undef  CONFIG_USE_IRQ                  /* don't need use IRQ/FIQ    */
-
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_BTUART          1       /* BTUART is default on WEP dev board */
-#define CONFIG_BAUDRATE   115200
-
-
-/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
- */
-#define CONFIG_COMMANDS         (CONFIG_CMD_DFL		\
-				& ~CFG_CMD_NET 		\
-				& ~CFG_CMD_LOADS	\
-				& ~CFG_CMD_CONSOLE	\
-				& ~CFG_CMD_AUTOSCRIPT	\
-/*				| CFG_CMD_JFFS2 */	\
-				)
-#include <cmd_confdefs.h>
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY   -1
-#define CONFIG_BOOTARGS    "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CFG_LONGHELP                                  /* undef saves memory  */
-#define CFG_PROMPT              "WEP> "               /* prompt string       */
-#define CFG_CBSIZE              256                   /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS             16                    /* max command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE            /* boot args buf size  */
-
-#define CFG_MEMTEST_START       0xa0400000            /* memtest test area   */
-#define CFG_MEMTEST_END         0xa0800000
-
-#undef  CFG_CLKS_IN_HZ                       /* use HZ for freq. display     */
-
-#define CFG_HZ                  3686400      /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED            0x141        /* core clock - register value  */
-
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
-#define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
-#undef  CONFIG_INITRD_TAG                /* do not send initrd params        */
-#undef  CONFIG_VFD                       /* do not send framebuffer setup    */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CFG_MALLOC_LEN	  (CFG_ENV_SIZE + (128<<10) )
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE        (120<<10)      /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4<<10)        /* IRQ stack  */
-#define CONFIG_STACKSIZE_FIQ    (4<<10)        /* FIQ stack  */
-#endif
-
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1                /* we have 1 bank of SDRAM */
-#define WEP_SDRAM_1            0xa0000000        /* SDRAM bank #1           */
-#define WEP_SDRAM_1_SIZE       0x02000000        /* 32 MB ( 2 chip )        */
-#define WEP_SDRAM_2            0xa2000000        /* SDRAM bank #2           */
-#define WEP_SDRAM_2_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_3            0xa8000000        /* SDRAM bank #3           */
-#define WEP_SDRAM_3_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_4            0xac000000        /* SDRAM bank #4           */
-#define WEP_SDRAM_4_SIZE       0x00000000        /* 0 MB                    */
-
-#define CFG_DRAM_BASE           0xa0000000
-#define CFG_DRAM_SIZE           0x02000000
-
-/* Uncomment used SDRAM chip */
-#define WEP_SDRAM_K4S281633
-/*#define WEP_SDRAM_K4S561633*/
-
-
-/*
- * Configuration for FLASH memory
- */
-#define CFG_MAX_FLASH_BANKS    	1  	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT     	128	/* number of sector in FLASH bank    */
-#define WEP_FLASH_BUS_WIDTH 	4	/* we use 32 bit FLASH memory...     */
-#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
-#define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
-#define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
-#define WEP_FLASH_BASE       0x0000000  /* location of flash memory */
-#define WEP_FLASH_UNLOCK        1       /* perform hw unlock first */
-
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef  CFG_FLASH_CFI
-
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ)    /* timeout for Write operation */
-
-#define CFG_FLASH_BASE          WEP_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
- */
-#define CFG_JFFS2_FIRST_BANK		0
-#define CFG_JFFS2_FIRST_SECTOR		5
-#define CFG_JFFS2_NUM_BANKS		1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CFG_MONITOR_BASE	PHYS_FLASH_1
-#define CFG_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x20000	        /* absolute address for now  */
-#define CFG_ENV_SIZE		0x2000
-
-#undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CFG_LOAD_ADDR        0x40000
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
deleted file mode 100644
index 1039762830..0000000000
--- a/include/configs/xaeniax.h
+++ /dev/null
@@ -1,557 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2004
- * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the xaeniax board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
-#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
-
-
-#define BOARD_LATE_INIT		1
-
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
-
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-
-#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SDRAM	| \
-				CFG_CMD_SNTP	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.68.201
-#define CONFIG_SERVERIP		192.168.68.62
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
-#define CONFIG_BOOTARGS		"console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 	1
-#define CONFIG_INITRD_TAG		1
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
-#endif
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- */
-#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory	*/
-#define CFG_HUSH_PARSER		1
-
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
-#else
-#define CFG_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
-
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
-
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-/* FIXME */
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_DRIVER_SMC91111		1
-#define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
-#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
-#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
-#undef  CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
-
-/*
- * GPIO settings
- */
-
-/*
- * GP05 == nUSBReset  is 1
- * GP10 == CFReset   is 1
- * GP13 == nCFDataEnable is 1
- * GP14 == nCFAddrEnable is 1
- * GP15 == nCS1      is 1
- * GP21 == ComBrdReset is 1
- * GP24 == SFRM      is 1
- * GP25 == TXD       is 1
- * GP31 == SYNC      is 1
- * GP33 == nCS5      is 1
- * GP39 == FFTXD     is 1
- * GP41 == RTS       is 1
- * GP43 == BTTXD     is 1
- * GP45 == BTRTS     is 1
- * GP47 == TXD       is 1
- * GP48 == nPOE      is 1
- * GP49 == nPWE      is 1
- * GP50 == nPIOR     is 1
- * GP51 == nPIOW     is 1
- * GP52 == nPCE[1]   is 1
- * GP53 == nPCE[2]   is 1
- * GP54 == nPSKTSEL  is 1
- * GP55 == nPREG     is 1
- * GP78 == nCS2      is 1
- * GP79 == nCS3      is 1
- * GP80 == nCS4      is 1
- * GP82 == NSSPSFRM  is 1
- * GP83 == NSSPTXD   is 1
- */
-#define CFG_GPSR0_VAL		0x8320E420
-#define CFG_GPSR1_VAL		0x00FFAA82
-#define CFG_GPSR2_VAL		0x000DC000
-
-/*
- * GP03 == LANReset  is 0
- * GP06 == USBWakeUp  is 0
- * GP11 == USBControl is 0
- * GP12 == Buzzer     is 0
- * GP16 == PWM0       is 0
- * GP17 == PWM1       is 0
- * GP23 == SCLK      is 0
- * GP30 == SDATA_OUT is 0
- * GP81 == NSSPCLK   is 0
- */
-#define CFG_GPCR0_VAL		0x40C31848
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00020000
-
-/*
- * GP00 == CPUWakeUpUSB is input
- * GP01 == GP reset is input
- * GP02 == LANInterrupt is input
- * GP03 == LANReset     is output
- * GP04 == USBInterrupt is input
- * GP05 == nUSBReset    is output
- * GP06 == USBWakeUp    is output
- * GP07 == CFReady/nBusy is input
- * GP08 == nCFCardDetect1 is input
- * GP09 == nCFCardDetect2 is input
- * GP10 == nCFReset   is output
- * GP11 == USBControl is output
- * GP12 == Buzzer     is output
- * GP13 == CFDataEnable is output
- * GP14 == CFAddressEnable is output
- * GP15 == nCS1      is output
- * GP16 == PWM0      is output
- * GP17 == PWM1      is output
- * GP18 == RDY       is input
- * GP19 == ReaderReady is input
- * GP20 == ReaderReset is input
- * GP21 == ComBrdReset is output
- * GP23 == SCLK      is output
- * GP24 == SFRM      is output
- * GP25 == TXD       is output
- * GP26 == RXD       is input
- * GP27 == EXTCLK    is input
- * GP28 == BITCLK    is output
- * GP29 == SDATA_IN0 is input
- * GP30 == SDATA_OUT is output
- * GP31 == SYNC      is output
- * GP32 == SYSSCLK   is output
- * GP33 == nCS5      is output
- * GP34 == FFRXD     is input
- * GP35 == CTS       is input
- * GP36 == DCD       is input
- * GP37 == DSR       is input
- * GP38 == RI        is input
- * GP39 == FFTXD     is output
- * GP40 == DTR       is output
- * GP41 == RTS       is output
- * GP42 == BTRXD     is input
- * GP43 == BTTXD     is output
- * GP44 == BTCTS     is input
- * GP45 == BTRTS     is output
- * GP46 == RXD       is input
- * GP47 == TXD       is output
- * GP48 == nPOE      is output
- * GP49 == nPWE      is output
- * GP50 == nPIOR     is output
- * GP51 == nPIOW     is output
- * GP52 == nPCE[1]   is output
- * GP53 == nPCE[2]   is output
- * GP54 == nPSKTSEL  is output
- * GP55 == nPREG     is output
- * GP56 == nPWAIT    is input
- * GP57 == nPIOS16   is input
- * GP58 == LDD[0]    is output
- * GP59 == LDD[1]    is output
- * GP60 == LDD[2]    is output
- * GP61 == LDD[3]    is output
- * GP62 == LDD[4]    is output
- * GP63 == LDD[5]    is output
- * GP64 == LDD[6]    is output
- * GP65 == LDD[7]    is output
- * GP66 == LDD[8]    is output
- * GP67 == LDD[9]    is output
- * GP68 == LDD[10]   is output
- * GP69 == LDD[11]   is output
- * GP70 == LDD[12]   is output
- * GP71 == LDD[13]   is output
- * GP72 == LDD[14]   is output
- * GP73 == LDD[15]   is output
- * GP74 == LCD_FCLK  is output
- * GP75 == LCD_LCLK  is output
- * GP76 == LCD_PCLK  is output
- * GP77 == LCD_ACBIAS is output
- * GP78 == nCS2      is output
- * GP79 == nCS3      is output
- * GP80 == nCS4      is output
- * GP81 == NSSPCLK   is output
- * GP82 == NSSPSFRM  is output
- * GP83 == NSSPTXD   is output
- * GP84 == NSSPRXD   is input
- */
-#define CFG_GPDR0_VAL		0xD3E3FC68
-#define CFG_GPDR1_VAL		0xFCFFAB83
-#define CFG_GPDR2_VAL		0x000FFFFF
-
-/*
- * GP01 == GP reset is AF01
- * GP15 == nCS1     is AF10
- * GP16 == PWM0     is AF10
- * GP17 == PWM1     is AF10
- * GP18 == RDY      is AF01
- * GP23 == SCLK     is AF10
- * GP24 == SFRM     is AF10
- * GP25 == TXD      is AF10
- * GP26 == RXD      is AF01
- * GP27 == EXTCLK   is AF01
- * GP28 == BITCLK   is AF01
- * GP29 == SDATA_IN0 is AF10
- * GP30 == SDATA_OUT is AF01
- * GP31 == SYNC     is AF01
- * GP32 == SYSCLK   is AF01
- * GP33 == nCS5  is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS   is AF01
- * GP36 == DCD   is AF01
- * GP37 == DSR   is AF01
- * GP38 == RI    is AF01
- * GP39 == FFTXD is AF10
- * GP40 == DTR   is AF10
- * GP41 == RTS   is AF10
- * GP42 == BTRXD is AF01
- * GP43 == BTTXD is AF10
- * GP44 == BTCTS is AF01
- * GP45 == BTRTS is AF10
- * GP46 == RXD   is AF10
- * GP47 == TXD   is AF01
- * GP48 == nPOE  is AF10
- * GP49 == nPWE  is AF10
- * GP50 == nPIOR is AF10
- * GP51 == nPIOW is AF10
- * GP52 == nPCE[1] is AF10
- * GP53 == nPCE[2] is AF10
- * GP54 == nPSKTSEL is AF10
- * GP55 == nPREG   is AF10
- * GP56 == nPWAIT  is AF01
- * GP57 == nPIOS16 is AF01
- * GP58 == LDD[0]  is AF10
- * GP59 == LDD[1]  is AF10
- * GP60 == LDD[2]  is AF10
- * GP61 == LDD[3]  is AF10
- * GP62 == LDD[4]  is AF10
- * GP63 == LDD[5]  is AF10
- * GP64 == LDD[6]  is AF10
- * GP65 == LDD[7]  is AF10
- * GP66 == LDD[8]  is AF10
- * GP67 == LDD[9]  is AF10
- * GP68 == LDD[10] is AF10
- * GP69 == LDD[11] is AF10
- * GP70 == LDD[12] is AF10
- * GP71 == LDD[13] is AF10
- * GP72 == LDD[14] is AF10
- * GP73 == LDD[15] is AF10
- * GP74 == LCD_FCLK is AF10
- * GP75 == LCD_LCLK is AF10
- * GP76 == LCD_PCLK is AF10
- * GP77 == LCD_ACBIAS is AF10
- * GP78 == nCS2     is AF10
- * GP79 == nCS3     is AF10
- * GP80 == nCS4     is AF10
- * GP81 == NSSPCLK  is AF01
- * GP82 == NSSPSFRM is AF01
- * GP83 == NSSPTXD  is AF01
- * GP84 == NSSPRXD  is AF10
- */
-#define CFG_GAFR0_L_VAL		0x80000004
-#define CFG_GAFR0_U_VAL		0x595A801A
-#define CFG_GAFR1_L_VAL		0x699A9559
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAAAAAAA
-#define CFG_GAFR2_U_VAL		0x00000256
-
-/*
- * clock settings
- */
-/* RDH = 1
- * PH  = 0
- * VFS = 0
- * BFS = 0
- * SSS = 0
- */
-#define CFG_PSSR_VAL		0x00000030
-
-#define CFG_CKEN_VAL            0x00000080  /*  */
-#define CFG_ICMR_VAL            0x00000000  /* No interrupts enabled        */
-
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1 :
- * [31]    0    -
- * [30:28] 000  -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19]    0    -
- * [18:16] 000  -
- * configuration for nCS0:
- * [15]    0    - Slower Device
- * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
- * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
- * [03]    0    - 32 Bit bus width
- * [02:00] 010  - burst OF 4 ROM or FLASH
-*/
-#define CFG_MSC0_VAL		0x000023D2
-
-/* This is the configuration for nCS2/3 -> USB controller, LAN
- * configuration for nCS3: LAN
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
- * [19]    0    - 32 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS2: USB
- * [15]    1    - Faster Device
- * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC1_VAL		0x1224A26C
-
-/* This is the configuration for nCS4/5 -> LAN
- * configuration for nCS5:
- * [31]    0    -
- * [30:28] 000  -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19]    0    -
- * [18:16] 000  -
- * configuration for nCS4: LAN
- * [15]    1    - Faster Device
- * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03]    0    - 32 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CFG_MSC2_VAL		0x00001224
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29]   000 - reserved
- * [28]      0	 - no SA1111 compatiblity mode
- * [27]      0   - latch return data with return clock
- * [26]      0   - alternate addressing for pair 2/3
- * [25:24]   00  - timings
- * [23]      0   - internal banks in lower partition 2/3 (not used)
- * [22:21]   00  - row address bits for partition 2/3 (not used)
- * [20:19]   00  - column address bits for partition 2/3 (not used)
- * [18]      0   - SDRAM partition 2/3 width is 32 bit
- * [17]      0   - SDRAM partition 3 disabled
- * [16]      0   - SDRAM partition 2 disabled
- * [15:13]   000 - reserved
- * [12]      0	 - no SA1111 compatiblity mode
- * [11]      1   - latch return data with return clock
- * [10]      0   - no alternate addressing for pair 0/1
- * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7]       1   - 4 internal banks in lower partition pair
- * [06:05]   10  - 13 row address bits for partition 0/1
- * [04:03]   01  - 9 column address bits for partition 0/1
- * [02]      0   - SDRAM partition 0/1 width is 32 bit
- * [01]      0   - disable SDRAM partition 1
- * [00]      1   - enable  SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x00000AC9
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0     - reserved
- * [25]    0     - K2FREE: not free running
- * [24]    0     - K1FREE: not free running
- * [23]    0     - K0FREE: not free running
- * [22]    0     - SLFRSH: self refresh disabled
- * [21]    0     - reserved
- * [20]    1     - APD: auto power down
- * [19]    0     - K2DB2: SDCLK2 is MemClk
- * [18]    0     - K2RUN: disable SDCLK2
- * [17]    0     - K1DB2: SDCLK1 is MemClk
- * [16]    1     - K1RUN: enable SDCLK1
- * [15]    1     - E1PIN: SDRAM clock enable
- * [14]    0     - K0DB2: SDCLK0 is MemClk
- * [13]    0     - K0RUN: disable SDCLK0
- * [12]    0     - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CFG_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31]      0       - reserved
- * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
- * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
- * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
- * [15]      0       - reserved
- * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
- * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CFG_MDMRS_VAL		0x00320032
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
deleted file mode 100644
index 825bfd14e9..0000000000
--- a/include/configs/xm250.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
-#define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CFG_MALLOC_LEN		(256*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE		0x04000300
-#undef	CONFIG_SMC91111_EXT_PHY
-#define CONFIG_SMC_USE_32_BIT
-#undef	CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries		*/
-
-/*
- * I2C bus
- */
-#define CONFIG_HARD_I2C			1
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xfe
-
-#define CONFIG_RTC_PCF8563		1
-#define CFG_I2C_RTC_ADDR		0x51
-
-#define CFG_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
-#define CFG_EEPROM_SIZE			2048	/* size in bytes		*/
-#undef	CFG_I2C_INIT_BOARD			/* board has no own init	*/
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART	       1       /* we use FFUART */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_ELF	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_I2C	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	3
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR		0xa3000000	/* default load address */
-
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
-
-						/* valid baudrates */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
-#define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
-#define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
-#undef	CONFIG_VFD			 /* do not send framebuffer setup	*/
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1	*/
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB		*/
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2	*/
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB		*/
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3	*/
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB		*/
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4	*/
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB		*/
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1	*/
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #1	*/
-#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB		*/
-#define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
-
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-
-/*
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write	*/
-#define CFG_FLASH_LOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CFG_FLASH_UNLOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CFG_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
-#define CFG_MONITOR_LEN		0x20000				/* 128 KiB */
-
-/******************************************************************************
- *
- * CPU specific defines
- *
- ******************************************************************************/
-
-/*
- * GPIO settings
- *
- * GPIO pin assignments
- * GPIO	    Name	Dir Out AF
- * 0	    NC
- * 1	    NC
- * 2	    SIRQ1	I
- * 3	    SIRQ2	I
- * 4	    SIRQ3	I
- * 5	    DMAACK1	O   0
- * 6	    DMAACK2	O   0
- * 7	    DMAACK3	O   0
- * 8	    TC1		O   0
- * 9	    TC2		O   0
- * 10	    TC3		O   0
- * 11	    nDMAEN	O   1
- * 12	    AENCTRL	O   0
- * 13	    PLDTC	O   0
- * 14	    ETHIRQ	I
- * 15	    NC
- * 16	    NC
- * 17	    NC
- * 18	    RDY		I
- * 19	    DMASIO	I
- * 20	    ETHIRQ	NC
- * 21	    NC
- * 22	    PGMEN	O   1	 FIXME for debug only enable flash
- * 23	    NC
- * 24	    NC
- * 25	    NC
- * 26	    NC
- * 27	    NC
- * 28	    NC
- * 29	    NC
- * 30	    NC
- * 31	    NC
- * 32	    NC
- * 33	    NC
- * 34	    FFRXD	I	01
- * 35	    FFCTS	I	01
- * 36	    FFDCD	I	01
- * 37	    FFDSR	I	01
- * 38	    FFRI	I	01
- * 39	    FFTXD	O   1	10
- * 40	    FFDTR	O   0	10
- * 41	    FFRTS	O   0	10
- * 42	    RS232FOFF	O   0	00
- * 43	    NC
- * 44	    NC
- * 45	    IRSL0	O   0
- * 46	    IRRX0	I	01
- * 47	    IRTX0	O   0	10
- * 48	    NC
- * 49	    nIOWE	O   0
- * 50	    NC
- * 51	    NC
- * 52	    NC
- * 53	    NC
- * 54	    NC
- * 55	    NC
- * 56	    NC
- * 57	    NC
- * 58	    DKDIRQ	I
- * 59	    NC
- * 60	    NC
- * 61	    NC
- * 62	    NC
- * 63	    NC
- * 64	    COMLED	O   0
- * 65	    COMLED	O   0
- * 66	    COMLED	O   0
- * 67	    COMLED	O   0
- * 68	    COMLED	O   0
- * 69	    COMLED	O   0
- * 70	    COMLED	O   0
- * 71	    COMLED	O   0
- * 72	    NC
- * 73	    NC
- * 74	    NC
- * 75	    NC
- * 76	    NC
- * 77	    NC
- * 78	    CSIO	O   1
- * 79	    NC
- * 80	    CSETH	O   1
- *
- * NOTE: All NC's are defined to be outputs
- *
- */
-/* Pin direction control */
-#define CFG_GPDR0_VAL	    0xd3808000
-#define CFG_GPDR1_VAL	    0xfcffab83
-#define CFG_GPDR2_VAL	    0x0001ffff
-/* Set and Clear registers */
-#define CFG_GPSR0_VAL	    0x00008000
-#define CFG_GPSR1_VAL	    0x00ff0002
-#define CFG_GPSR2_VAL	    0x0001c000
-#define CFG_GPCR0_VAL	    0x00000000
-#define CFG_GPCR1_VAL	    0x00000000
-#define CFG_GPCR2_VAL	    0x00000000
-/* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL	    0x00002180
-#define CFG_GRER1_VAL	    0x00000000
-#define CFG_GRER2_VAL	    0x00000000
-#define CFG_GFER0_VAL	    0x000043e0
-#define CFG_GFER1_VAL	    0x00000000
-#define CFG_GFER2_VAL	    0x00000000
-/* Alternate function registers */
-#define CFG_GAFR0_L_VAL	    0x80000004
-#define CFG_GAFR0_U_VAL	    0x595a8010
-#define CFG_GAFR1_L_VAL	    0x699a9559
-#define CFG_GAFR1_U_VAL	    0xaaa5aaaa
-#define CFG_GAFR2_L_VAL	    0xaaaaaaaa
-#define CFG_GAFR2_U_VAL	    0x00000002
-
-/*
- * Clocks, power control and interrupts
- */
-#define CFG_PSSR_VAL	    0x00000030
-#define CFG_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
-#define CFG_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
-#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
-
-/* FIXME
- *
- * RTC settings
- * Watchdog
- *
- */
-
-/*
- * Memory settings
- *
- */
-#define CFG_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
-#define CFG_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
-#define CFG_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
-#define CFG_MDCNFG_VAL	    0x000009c9
-#define CFG_MDMRS_VAL	    0x00220022
-#define CFG_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
-
-/*
- * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
- */
-#define CFG_MECR_VAL	      0x00000000
-#define CFG_MCMEM0_VAL	      0x00010504
-#define CFG_MCMEM1_VAL	      0x00010504
-#define CFG_MCATT0_VAL	      0x00010504
-#define CFG_MCATT1_VAL	      0x00010504
-#define CFG_MCIO0_VAL	      0x00004715
-#define CFG_MCIO1_VAL	      0x00004715
-
-/* Board specific defines */
-
-#ifndef __ASSEMBLY__
-
-/* global prototypes */
-void led_code(int code, int color);
-
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
deleted file mode 100644
index dc702cf445..0000000000
--- a/include/configs/xsengine.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
-#define CONFIG_XSENGINE			1
-#define CONFIG_MMC			1
-#define BOARD_POST_INIT			1
-#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-
-#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
-
-#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
-#define CFG_DRAM_BASE			0xa0000000
-#define CFG_DRAM_SIZE			0x04000000
-
-/* FLASH organization */
-#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
-#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
-#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
-#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=xsengine-0"
-#define MTDPARTS_DEFAULT	"mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
-*/
-
-/* Environment settings */
-#define CONFIG_ENV_OVERWRITE
-#define CFG_ENV_IS_IN_FLASH             1
-#define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
-#define CFG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
-#define CFG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ) 	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */
-
-/* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
-#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
-
-/* Hardware drivers */
-#define CONFIG_DRIVER_SMC91111
-#define CONFIG_SMC91111_BASE		0x04000300
-#define CONFIG_SMC_USE_32_BIT 		1
-
-/* select serial console configuration */
-#define CONFIG_FFUART			1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK			255.255.255.0
-#define CONFIG_IPADDR			192.168.1.50
-#define CONFIG_SERVERIP			192.168.1.2
-#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG
-
-/* Miscellaneous configurable options */
-#define CFG_HUSH_PARSER			1
-#define CFG_PROMPT_HUSH_PS2		"> "
-#define CFG_LONGHELP								/* undef to save memory	*/
-#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
-#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 	/* Print Buffer Size */
-#define CFG_MAXARGS			16					/* max number of command args */
-#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
-#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
-#undef  CFG_CLKS_IN_HZ          						/* everything, incl board info, in Hz */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
-#define CFG_MMC_BASE			0xF0000000
-#define CFG_LOAD_ADDR           	0xA0000000				/* load kernel to this address   */
-
-/* Stack sizes - The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
-
-/* GP set register */
-#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
-#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
-
-/* GP clear register */
-#define CFG_GPCR0_VAL			0x00000000
-#define CFG_GPCR1_VAL			0x00000000
-#define CFG_GPCR2_VAL			0x00000000
-
-/* GP direction register */
-#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
-#define CFG_GPDR2_VAL			0x0000C000  	/* CS2, CS3 */
-
-/* GP rising edge detect register */
-#define CFG_GRER0_VAL			0x00000000
-#define CFG_GRER1_VAL			0x00000000
-#define CFG_GRER2_VAL			0x00000000
-
-/* GP falling edge detect register */
-#define CFG_GFER0_VAL			0x00000000
-#define CFG_GFER1_VAL			0x00000000
-#define CFG_GFER2_VAL			0x00000000
-
-/* GP alternate function register */
-#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
-#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
-#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
-#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
-#define CFG_GAFR2_L_VAL			0xA0000000  	/* CS2, CS3 */
-#define CFG_GAFR2_U_VAL			0x00000000
-
-#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
-#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
-#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
-#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
-
-/* Memory settings */
-#define CFG_MSC0_VAL			0x25F425F0
-
-/* MDCNFG: SDRAM Configuration Register */
-#define CFG_MDCNFG_VAL			0x000009C9
-
-/* MDREFR: SDRAM Refresh Control Register */
-#define CFG_MDREFR_VAL			0x00018018
-
-/* MDMRS: Mode Register Set Configuration Register */
-#define CFG_MDMRS_VAL			0x00220022
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
deleted file mode 100644
index a6532b5e85..0000000000
--- a/include/configs/yucca.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * 1 january 2005	Alain Saurel <asaurel@amcc.com>
- * Adapted to current Das U-Boot source
- ***********************************************************************/
-/************************************************************************
- * yucca.h - configuration for AMCC 440SPe Ref (yucca)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_4xx			1	/* ... PPC4xx family	*/
-#define CONFIG_440			1	/* ... PPC440 family	*/
-#define CONFIG_440SPE			1	/* Specifc SPe support	*/
-#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST				/* Disable-takes long time */
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-#define EXTCLK_33_33		33333333
-#define EXTCLK_66_66		66666666
-#define EXTCLK_50		50000000
-#define EXTCLK_83		83333333
-
-#define	CONFIG_IBM_EMAC4_V4		1
-#define	CONFIG_MISC_INIT_F		1	/* Use misc_init_f()	*/
-#undef  CONFIG_SHOW_BOOT_PROGRESS
-#undef  CONFIG_STRESS
-#undef  ENABLE_ECC
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	0xfffb0000	/* start of monitor	*/
-#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
-#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
-
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
-
-#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x01000000
-#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
-
-#define CFG_PCIE0_CFGBASE	0xc0000000
-#define CFG_PCIE0_XCFGBASE	0xc0000400
-#define CFG_PCIE1_CFGBASE	0xc0001000
-#define CFG_PCIE1_XCFGBASE	0xc0001400
-#define CFG_PCIE2_CFGBASE	0xc0002000
-#define CFG_PCIE2_XCFGBASE	0xc0002400
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#define CFG_FPGA_BASE		0xe2000000	/* epld			*/
-#define CFG_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
-
-/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
-
-#define CFG_MONITOR_LEN		(320 * 1024)	/* Reserve 320 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_SERIAL_MULTI	1
-#undef CONFIG_UART1_CONSOLE
-
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK
-/* #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS {0x53, 0x52}	/* SPD i2c spd addresses	*/
-#define IIC0_DIMM0_ADDR		0x53
-#define IIC0_DIMM1_ADDR		0x52
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-#define IIC0_BOOTPROM_ADDR	0x50
-#define IIC0_ALT_BOOTPROM_ADDR	0x54
-
-/* Don't probe these addrs */
-#define CFG_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
-
-/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
-/* #define CFG_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* #endif */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-/* #define CFG_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
-
-#undef  CFG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
-#define	CFG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
-#undef	CFG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=yucca\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"				\
-	"bootfile=yucca/uImage\0"					\
-	"kernel_addr=E7F10000\0"					\
-	"ramdisk_addr=E7F20000\0"					\
-	"load=tftp 100000 yuca/u-boot.bin\0"				\
-	"update=protect off 2:4-7;era 2:4-7;"				\
-		"cp.b ${fileaddr} FFFB0000 ${filesize};"		\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load;run update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM	)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#undef CONFIG_NET_MULTI
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
-#define CONFIG_PHY_RESET_DELAY	1000
-#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3	/* number of banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* sectors per device		*/
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CFG_FLASH_ADDR0		0x5555
-#define CFG_FLASH_ADDR1		0x2aaa
-#define CFG_FLASH_WORD_SIZE	unsigned char
-
-#define CFG_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
-#define CFG_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CFG_ENV_ADDR		0xfffa0000
-/* #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
-#define CFG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
-#endif /* CFG_ENV_IS_IN_FLASH */
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CFG_PCI_MASTER_INIT
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */
-
-/*
- *  NETWORK Support (PCI):
- */
-/* Support for Intel 82557/82559/82559ER chips. */
-#define CONFIG_EEPRO100
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs		*/
-#define CFG_CACHELINE_SIZE	32	/* ...				*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* FB Divisor selection */
-#define FPGA_FB_DIV_6		6
-#define FPGA_FB_DIV_10		10
-#define FPGA_FB_DIV_12		12
-#define FPGA_FB_DIV_20		20
-
-/* VCO Divisor selection */
-#define	FPGA_VCO_DIV_4		4
-#define	FPGA_VCO_DIV_6		6
-#define	FPGA_VCO_DIV_8		8
-#define	FPGA_VCO_DIV_10		10
-
-/*----------------------------------------------------------------------------+
-| FPGA registers and bit definitions
-+----------------------------------------------------------------------------*/
-/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
-/* TLB initialization makes it correspond to logical address 0xE2000000. */
-/* => Done init_chip.s in bootlib */
-#define FPGA_REG_BASE_ADDR	0xE2000000
-#define FPGA_GPIO_BASE_ADDR	0xE2010000
-#define FPGA_INT_BASE_ADDR	0xE2020000
-
-/*----------------------------------------------------------------------------+
-| Display
-+----------------------------------------------------------------------------*/
-#define PPC440SPE_DISPLAY	FPGA_REG_BASE_ADDR
-
-#define PPC440SPE_DISPLAY_D8	(FPGA_REG_BASE_ADDR+0x06)
-#define PPC440SPE_DISPLAY_D4	(FPGA_REG_BASE_ADDR+0x04)
-#define PPC440SPE_DISPLAY_D2	(FPGA_REG_BASE_ADDR+0x02)
-#define PPC440SPE_DISPLAY_D1	(FPGA_REG_BASE_ADDR+0x00)
-/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
-/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
-
-/*----------------------------------------------------------------------------+
-| ethernet/reset/boot Register 1
-+----------------------------------------------------------------------------*/
-#define FPGA_REG10	(FPGA_REG_BASE_ADDR+0x10)
-
-#define FPGA_REG10_10MHZ_ENABLE		0x8000
-#define FPGA_REG10_100MHZ_ENABLE	0x4000
-#define FPGA_REG10_GIGABIT_ENABLE	0x2000
-#define FPGA_REG10_FULL_DUPLEX		0x1000	/* force Full Duplex*/
-#define FPGA_REG10_RESET_ETH		0x0800
-#define FPGA_REG10_AUTO_NEG_DIS		0x0400
-#define FPGA_REG10_INTP_ETH		0x0200
-
-#define FPGA_REG10_RESET_HISR		0x0080
-#define FPGA_REG10_ENABLE_DISPLAY	0x0040
-#define FPGA_REG10_RESET_SDRAM		0x0020
-#define FPGA_REG10_OPER_BOOT		0x0010
-#define FPGA_REG10_SRAM_BOOT		0x0008
-#define FPGA_REG10_SMALL_BOOT		0x0004
-#define FPGA_REG10_FORCE_COLA		0x0002
-#define FPGA_REG10_COLA_MANUAL		0x0001
-
-#define FPGA_REG10_SDRAM_ENABLE		0x0020
-
-#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
-#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
-
-/*----------------------------------------------------------------------------+
-| MUX control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG12	(FPGA_REG_BASE_ADDR+0x12)
-
-#define FPGA_REG12_EBC_CTL		0x8000
-#define FPGA_REG12_UART1_CTS_RTS	0x4000
-#define FPGA_REG12_UART0_RX_ENABLE	0x2000
-#define FPGA_REG12_UART1_RX_ENABLE	0x1000
-#define FPGA_REG12_UART2_RX_ENABLE	0x0800
-#define FPGA_REG12_EBC_OUT_ENABLE	0x0400
-#define FPGA_REG12_GPIO0_OUT_ENABLE	0x0200
-#define FPGA_REG12_GPIO1_OUT_ENABLE	0x0100
-#define FPGA_REG12_GPIO_SELECT		0x0010
-#define FPGA_REG12_GPIO_CHREG		0x0008
-#define FPGA_REG12_GPIO_CLK_CHREG	0x0004
-#define FPGA_REG12_GPIO_OETRI		0x0002
-#define FPGA_REG12_EBC_ERROR		0x0001
-
-/*----------------------------------------------------------------------------+
-| PCI Clock control
-+----------------------------------------------------------------------------*/
-#define FPGA_REG16	(FPGA_REG_BASE_ADDR+0x16)
-
-#define FPGA_REG16_PCI_CLK_CTL0		0x8000
-#define FPGA_REG16_PCI_CLK_CTL1		0x4000
-#define FPGA_REG16_PCI_CLK_CTL2		0x2000
-#define FPGA_REG16_PCI_CLK_CTL3		0x1000
-#define FPGA_REG16_PCI_CLK_CTL4		0x0800
-#define FPGA_REG16_PCI_CLK_CTL5		0x0400
-#define FPGA_REG16_PCI_CLK_CTL6		0x0200
-#define FPGA_REG16_PCI_CLK_CTL7		0x0100
-#define FPGA_REG16_PCI_CLK_CTL8		0x0080
-#define FPGA_REG16_PCI_CLK_CTL9		0x0040
-#define FPGA_REG16_PCI_EXT_ARB0		0x0020
-#define FPGA_REG16_PCI_MODE_1		0x0010
-#define FPGA_REG16_PCI_TARGET_MODE	0x0008
-#define FPGA_REG16_PCI_INTP_MODE	0x0004
-
-/* FB1 Divisor selection */
-#define FPGA_REG16_FB2_DIV_MASK		0x1000
-#define FPGA_REG16_FB2_DIV_LOW		0x0000
-#define FPGA_REG16_FB2_DIV_HIGH		0x1000
-/* FB2 Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_FB1_DIV_MASK		0x2000
-#define FPGA_REG16_FB1_DIV_LOW		0x0000
-#define FPGA_REG16_FB1_DIV_HIGH		0x2000
-/* PCI0 Clock Selection */
-/* S3 switch on Board */
-#define FPGA_REG16_PCI0_CLK_MASK	0x0c00
-#define FPGA_REG16_PCI0_CLK_33_33	0x0000
-#define FPGA_REG16_PCI0_CLK_66_66	0x0800
-#define FPGA_REG16_PCI0_CLK_100		0x0400
-#define FPGA_REG16_PCI0_CLK_133_33	0x0c00
-/* VCO Divisor selection */
-/* S3 switch on Board */
-#define FPGA_REG16_VCO_DIV_MASK		0xc000
-#define FPGA_REG16_VCO_DIV_4		0x0000
-#define FPGA_REG16_VCO_DIV_8		0x4000
-#define FPGA_REG16_VCO_DIV_6		0x8000
-#define FPGA_REG16_VCO_DIV_10		0xc000
-/* Master Clock Selection */
-/* S3, S4 switches on Board */
-#define FPGA_REG16_MASTER_CLK_MASK	0x01c0
-#define FPGA_REG16_MASTER_CLK_EXT	0x0000
-#define FPGA_REG16_MASTER_CLK_66_66	0x0040
-#define FPGA_REG16_MASTER_CLK_50	0x0080
-#define FPGA_REG16_MASTER_CLK_33_33	0x00c0
-#define FPGA_REG16_MASTER_CLK_25	0x0100
-
-/*----------------------------------------------------------------------------+
-| PCI Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG18	(FPGA_REG_BASE_ADDR+0x18)
-
-#define FPGA_REG18_PCI_PRSNT1		0x8000
-#define FPGA_REG18_PCI_PRSNT2		0x4000
-#define FPGA_REG18_PCI_INTA		0x2000
-#define FPGA_REG18_PCI_SLOT0_INTP	0x1000
-#define FPGA_REG18_PCI_SLOT1_INTP	0x0800
-#define FPGA_REG18_PCI_SLOT2_INTP	0x0400
-#define FPGA_REG18_PCI_SLOT3_INTP	0x0200
-#define FPGA_REG18_PCI_PCI0_VC		0x0100
-#define FPGA_REG18_PCI_PCI0_VTH1	0x0080
-#define FPGA_REG18_PCI_PCI0_VTH2	0x0040
-#define FPGA_REG18_PCI_PCI0_VTH3	0x0020
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1A	(FPGA_REG_BASE_ADDR+0x1A)
-
-#define FPGA_REG1A_PE0_GLED		0x8000
-#define FPGA_REG1A_PE1_GLED		0x4000
-#define FPGA_REG1A_PE2_GLED		0x2000
-#define FPGA_REG1A_PE0_YLED		0x1000
-#define FPGA_REG1A_PE1_YLED		0x0800
-#define FPGA_REG1A_PE2_YLED		0x0400
-#define FPGA_REG1A_PE0_PWRON		0x0200
-#define FPGA_REG1A_PE1_PWRON		0x0100
-#define FPGA_REG1A_PE2_PWRON		0x0080
-#define FPGA_REG1A_PE0_REFCLK_ENABLE	0x0040
-#define FPGA_REG1A_PE1_REFCLK_ENABLE	0x0020
-#define FPGA_REG1A_PE2_REFCLK_ENABLE	0x0010
-#define FPGA_REG1A_PE_SPREAD0		0x0008
-#define FPGA_REG1A_PE_SPREAD1		0x0004
-#define FPGA_REG1A_PE_SELSOURCE_0	0x0002
-#define FPGA_REG1A_PE_SELSOURCE_1	0x0001
-
-/*----------------------------------------------------------------------------+
-| PCIe Miscellaneous
-+----------------------------------------------------------------------------*/
-#define FPGA_REG1C	(FPGA_REG_BASE_ADDR+0x1C)
-
-#define FPGA_REG1C_PE0_ROOTPOINT	0x8000
-#define FPGA_REG1C_PE1_ENDPOINT		0x4000
-#define FPGA_REG1C_PE2_ENDPOINT		0x2000
-#define FPGA_REG1C_PE0_PRSNT		0x1000
-#define FPGA_REG1C_PE1_PRSNT		0x0800
-#define FPGA_REG1C_PE2_PRSNT		0x0400
-#define FPGA_REG1C_PE0_WAKE		0x0080
-#define FPGA_REG1C_PE1_WAKE		0x0040
-#define FPGA_REG1C_PE2_WAKE		0x0020
-#define FPGA_REG1C_PE0_PERST		0x0010
-#define FPGA_REG1C_PE1_PERST		0x0008
-#define FPGA_REG1C_PE2_PERST		0x0004
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-#define PERIOD_133_33MHZ	7500	/* 7,5ns */
-#define PERIOD_100_00MHZ	10000	/* 10ns */
-#define PERIOD_83_33MHZ		12000	/* 12ns */
-#define PERIOD_75_00MHZ		13333	/* 13,333ns */
-#define PERIOD_66_66MHZ		15000	/* 15ns */
-#define PERIOD_50_00MHZ		20000	/* 20ns */
-#define PERIOD_33_33MHZ		30000	/* 30ns */
-#define PERIOD_25_00MHZ		40000	/* 40ns */
-
-/*---------------------------------------------------------------------------*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
deleted file mode 100644
index c6aa8ece5b..0000000000
--- a/include/configs/zylonite.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the Zylonite board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_MONAHANS	1	/* Intel Monahan CPU    */
-#define CONFIG_ZYLONITE		1	/* Zylonite board       */
-
-/* #define CONFIG_LCD		1 */
-#ifdef CONFIG_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-/* #define CONFIG_MMC		1 */
-#define BOARD_LATE_INIT		1
-
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-
-#undef TURN_ON_ETHERNET
-#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
-# define CONFIG_SMC91111_BASE   0x14000300
-# define CONFIG_SMC91111_EXT_PHY
-# define CONFIG_SMC_USE_32_BIT
-# undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
-#endif
-
-/*
- * select serial console configuration
- */
-#define CONFIG_FFUART	       1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#ifdef TURN_ON_ETHERNET
-# define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
-#else
-# define CONFIG_COMMANDS	((CONFIG_CMD_DFL \
-				  | CFG_CMD_ENV \
-				  | CFG_CMD_NAND) \
-				 & ~(CFG_CMD_NET \
-				     | CFG_CMD_FLASH \
-				     | CFG_CMD_IMLS))
-#endif
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CONFIG_BOOTDELAY	-1
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.0.21
-#define CONFIG_SERVERIP		192.168.0.250
-#define CONFIG_BOOTCOMMAND	"bootm 80000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_TIMESTAMP
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
-
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
-
-#define CFG_MEMTEST_START	0x9c000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x9c400000	/* 4 ... 8 MB in DRAM	*/
-
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
-#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
-
-#define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
-
-/* Monahans Core Frequency */
-#define CFG_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
-#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
-
-						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/* #define CFG_MMC_BASE		0xF0000000 */
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
-
-#define CFG_DRAM_BASE		0x80000000 /* at CS0 */
-#define CFG_DRAM_SIZE		0x04000000 /* 64 MB Ram */
-
-#undef CFG_SKIP_DRAM_SCRUB
-
-
-/*
- * NAND Flash
- */
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
-#define CONFIG_NEW_NAND_CODE
-#define CFG_NAND0_BASE		0x0
-#undef CFG_NAND1_BASE
-
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-
-/* nand timeout values */
-#define CFG_NAND_PROG_ERASE_TO	3000
-#define CFG_NAND_OTHER_TO	100
-#define CFG_NAND_SENDCMD_RETRY	3
-#undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
-
-/* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH		10
-#define NAND_TIMING_tCS		0
-#define NAND_TIMING_tWH		20
-#define NAND_TIMING_tWP		40
-
-#define NAND_TIMING_tRH		20
-#define NAND_TIMING_tRP		40
-
-#define NAND_TIMING_tR		11123
-#define NAND_TIMING_tWHR	100
-#define NAND_TIMING_tAR		10
-
-/* NAND debugging */
-#define CFG_DFC_DEBUG1 /* usefull */
-#undef CFG_DFC_DEBUG2  /* noisy */
-#undef CFG_DFC_DEBUG3  /* extremly noisy  */
-
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 1
-
-#define ADDR_COLUMN		1
-#define ADDR_PAGE		2
-#define ADDR_COLUMN_PAGE	3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
-
-#define CFG_NO_FLASH		1
-
-#define CFG_ENV_IS_IN_NAND	1
-#define CFG_ENV_OFFSET		0x40000
-#define CFG_ENV_OFFSET_REDUND	0x44000
-#define CFG_ENV_SIZE		0x4000
-
-
-#endif	/* __CONFIG_H */