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| author | sascha <sascha@nomad.localdomain> | 2007-10-16 14:45:58 +0200 |
|---|---|---|
| committer | sascha <sascha@nomad.localdomain> | 2007-10-16 14:45:58 +0200 |
| commit | 52fb34f5adf5d1095c0b4c9462dd078d9382fa7a (patch) | |
| tree | 4b70f990b8f36d2bf2bf7f502bc6626e532222f5 /include/configs | |
| parent | fdf739c7a5f5d4c9f2a49c65c1be14cdafa1b1db (diff) | |
| download | barebox-52fb34f5adf5d1095c0b4c9462dd078d9382fa7a.tar.gz barebox-52fb34f5adf5d1095c0b4c9462dd078d9382fa7a.tar.xz | |
update scb9328 config
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/scb9328.h | 106 |
1 files changed, 1 insertions, 105 deletions
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index b01ce48233..ed7e10f0fd 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -29,8 +29,6 @@ #define CONFIG_ARCH_NUMBER MACH_TYPE_SCB9328 #define CONFIG_BOOT_PARAMS 0x08000100 -#define CFG_CPUSPEED 0x141 /* core clock - register value */ - /* * Definitions related to passing arguments to kernel. */ @@ -39,109 +37,7 @@ #define CONFIG_STACKSIZE (120<<10) /* stack size */ - -/* CNC == 3 too long - #define CFG_CS5U_VAL 0x0000C210 */ - -/* #define CFG_CS5U_VAL 0x00008400 - mal laenger mahcen, ob der bei 150MHz laenger haelt dann und - kaum langsamer ist */ -/* #define CFG_CS5U_VAL 0x00009400 - #define CFG_CS5L_VAL 0x11010D03 */ - -#define CONFIG_DM9000_BASE 0x16000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) -/* #define CONFIG_DM9000_USE_8BIT */ -#define CONFIG_DM9000_USE_16BIT -/* #define CONFIG_DM9000_USE_32BIT */ - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CPU200 - -#ifdef CPU200 -#define CFG_MPCTL0_VAL 0x00321431 -#else -#define CFG_MPCTL0_VAL 0x040e200e -#endif - -/* #define BUS64 */ -#define BUS72 - -#ifdef BUS72 -#define CFG_SPCTL0_VAL 0x04002400 -#endif - -#ifdef BUS96 -#define CFG_SPCTL0_VAL 0x04001800 -#endif - -#ifdef BUS64 -#define CFG_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CFG_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 -#define CFG_CSCR_VAL 0x2f030403 -#endif - -#define MHZ16QUARZINUSE - -#ifdef MHZ16QUARZINUSE #define CONFIG_SYSPLL_CLK_FREQ 16000000 -#else -#define CONFIG_SYSPLL_CLK_FREQ 16780000 -#endif - -#define CONFIG_SYS_CLK_FREQ 16780000 - -/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ -#define CFG_FMCR_VAL 0x00000001 - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef BUS96 -#define CFG_PCDR_VAL 0x000b00b5 -#endif - -#ifdef BUS64 -#define CFG_PCDR_VAL 0x000b00b3 -#endif - -#ifdef BUS72 -#define CFG_PCDR_VAL 0x000b00b8 -#endif #endif /* __CONFIG_H */ + |