diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2007-07-05 18:01:18 +0200 |
|---|---|---|
| committer | Sascha Hauer <sha@octopus.labnet.pengutronix.de> | 2007-07-05 18:01:18 +0200 |
| commit | 87c8aafa9cc23c7ba1e85021ebe7ca26643bce85 (patch) | |
| tree | c064b73f04f8417d311cb5fb2ed526700f60c222 /include/configs | |
| parent | b8ae2bfea4b40637e710541573cd8c47e3985964 (diff) | |
| download | barebox-87c8aafa9cc23c7ba1e85021ebe7ca26643bce85.tar.gz barebox-87c8aafa9cc23c7ba1e85021ebe7ca26643bce85.tar.xz | |
svn_rev_054
remove all boards except the ones I am working on
Diffstat (limited to 'include/configs')
126 files changed, 0 insertions, 46358 deletions
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h deleted file mode 100644 index f53ce57cdd..0000000000 --- a/include/configs/ADS860.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860 ADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ - -/* Processor type */ -#define CONFIG_MPC860 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* Console baudrate */ - -#define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ - ) - - -#include "fads.h" - -#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h deleted file mode 100644 index 0e6b50f8b0..0000000000 --- a/include/configs/Adder.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) -#define CONFIG_MPC875 -#endif - -#define CONFIG_ADDER /* Analogue&Micro Adder board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 - -#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) -#define CFG_DISCOVER_PHY -#define FEC_ENET -#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#ifdef CONFIG_MPC852T -#define CFG_8xx_CPUCLK_MAX 50000000 -#else -#define CFG_8xx_CPUCLK_MAX 133000000 -#endif /* CONFIG_MPC852T */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x400000 /* Default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * RAM configuration (note that CFG_SDRAM_BASE must be zero) - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ - -#define CFG_MAMR 0x00002114 - -/* - * 4096 Up to 4096 SDRAM rows - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ - -#define CFG_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -#define CFG_OR0_PRELIM 0xFF000774 -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CFG_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CFG_PLPRCR PLPRCR_TEXPS */ - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR SCCR_RTSEL - -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h deleted file mode 100644 index 5b54f30e08..0000000000 --- a/include/configs/BC3450.h +++ /dev/null @@ -1,568 +0,0 @@ -/* - * -- Version 1.1 -- - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2005 - * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de. - * - * History: - * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ - -#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ -#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */ -#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */ -#define CONFIG_BC3450_USB 1 /* + USB support */ -# define CONFIG_FAT 1 /* + FAT support */ -# define CONFIG_EXT2 1 /* + EXT2 support */ -#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */ -#undef CONFIG_BC3450_CAN /* + CAN transceiver */ -#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */ -#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */ -#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */ -#define CONFIG_BC3450_FP 1 /* + enable FP O/P */ -#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * AT-PS/2 Multiplexer - */ -#ifdef CONFIG_BC3450_PS2 -# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -# define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ -# define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_BC3450_PS2 */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -#ifdef CONFIG_PCI -# define ADD_PCI_CMD CFG_CMD_PCI -#else -# define ADD_PCI_CMD 0 -#endif - -/* - * Video console - */ -# define CONFIG_VIDEO -# define CONFIG_VIDEO_SM501 -# define CONFIG_VIDEO_SM501_32BPP -# define CONFIG_CFB_CONSOLE -# define CONFIG_VIDEO_LOGO -# define CONFIG_VGA_AS_SINGLE_DEVICE -# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */ -# define CONFIG_VIDEO_SW_CURSOR -# define CONFIG_SPLASH_SCREEN -# define CFG_CONSOLE_IS_IN_ENV - -#ifdef CONFIG_VIDEO -# define ADD_BMP_CMD CFG_CMD_BMP -#else -# define ADD_BMP_CMD 0 -#endif - -/* - * Partitions - */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * USB - */ -#ifdef CONFIG_BC3450_USB -# define CONFIG_USB_OHCI -# define ADD_USB_CMD CFG_CMD_USB -# define CONFIG_USB_STORAGE -#else /* !CONFIG_BC3450_USB */ -# define ADD_USB_CMD 0 -#endif /* CONFIG_BC3450_USB */ - -/* - * POST support - */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -# define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -# define CFG_CMD_POST_DIAG 0 -#endif /* CONFIG_POST */ - -/* - * IDE - */ -#ifdef CONFIG_BC3450_IDE -# define ADD_IDE_CMD CFG_CMD_IDE -#else -# define ADD_IDE_CMD 0 -#endif /* CONFIG_BC3450_IDE */ - -/* - * Filesystem support - */ -#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB) -#ifdef CONFIG_FAT -# define ADD_FAT_CMD CFG_CMD_FAT -#else -# define ADD_FAT_CMD 0 -#endif /* CONFIG_FAT */ - -#ifdef CONFIG_EXT2 -# define ADD_EXT2_CMD CFG_CMD_EXT2 -#else -# define ADD_EXT2_CMD 0 -#endif /* CONFIG_EXT2 */ -#endif /* CONFIG_BC3450_IDE / _USB */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_FAT_CMD | \ - ADD_EXT2_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo;" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ipaddr=192.168.1.10\0" \ - "serverip=192.168.1.3\0" \ - "netmask=255.255.255.0\0" \ - "hostname=bc3450\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "kernel_addr=fc0a0000\0" \ - "ramdisk_addr=fc1c0000\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ideargs=setenv bootargs root=/dev/hda2 ro\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addcons=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) console=tty0\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile); " \ - "run nfsargs addip addcons; bootm\0" \ - "ide_nfs=run nfsargs addip addcons; " \ - "disk 200000 0:1; bootm\0" \ - "ide_ide=run ideargs addip addcons; " \ - "disk 200000 0:1; bootm\0" \ - "usb_self=run usbload; run ramargs addip addcons; " \ - "bootm 200000 400000\0" \ - "usbload=usb reset; usb scan; usbboot 200000 0:1; " \ - "usbboot 400000 0:2\0" \ - "bootfile=uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 $(filesize);" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet - * hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#if defined(CFG_IPBSPEED_133) -# define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for I²C EEPROM M24C32 - * M24C64 should work also. For other EEPROMs config should be verified. - * - * The TQM5200 module may hold an EEPROM at address 0x50. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231) -# define CONFIG_RTC_M41T11 1 -# define CFG_I2C_RTC_ADDR 0x68 -#else -# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */ -# define CONFIG_BOARD_EARLY_INIT_R -#endif - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -# define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -# define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif /*CONFIG_POST*/ - -#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - * - * Define CONFIG_FEC10MBIT to force FEC at 10MBIT - */ -#define CONFIG_MPC5xxx_FEC 1 -#undef CONFIG_FEC_10MBIT -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration on BC3450 - * - * PSC1: UART1 (Service-UART) [0x xxxxxxx4] - * PSC2: UART2 [0x xxxxxx4x] - * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x] - * PSC3: USB2 [0x xxxxx1xx] - * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx] - * (this has to match - * CONFIG_USB_CONFIG which is - * used by usb_ohci.c to set - * the USB ports) - * Eth: 10/100Mbit Ethernet [0x xxx0xxxx] - * (this is reset to '5' - * in FEC driver: fec.c) - * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx] - * ATA/CS: ??? [0x x1xxxxxx] - * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx] - * CS1: Use Pin gpio_wkup_6 as second - * SDRAM chip select (mem_cs1) - * Timer: CAN2 / SPI - * I2C: CAN1 / I²C2 [0x bxxxxxxx] - */ -#ifdef CONFIG_BC3450_AC97 -# define CFG_GPS_PORT_CONFIG 0xb1502124 -#else /* PSC2=UART2 */ -# define CFG_GPS_PORT_CONFIG 0xb1502144 -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max no of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg. Buffer Size */ - -#define CFG_ALT_MEMTEST /* Enable an alternative, */ - /* more extensive mem test */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* dec freq: 1ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -# define CFG_HID0_INIT HID0_ICE | HID0_ICFI -# define CFG_HID0_FINAL HID0_ICE -#else -# define CFG_HID0_INIT 0 -# define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* automatic configuration of chip selects */ -#ifdef CONFIG_TQM5200 -# define CONFIG_LAST_STAGE_INIT -#endif /* CONFIG_TQM5200 */ - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#ifdef CONFIG_TQM5200 -# define CFG_CS2_START 0xE5000000 -# define CFG_CS2_SIZE 0x100000 /* 1 MByte */ -# define CFG_CS2_CFG 0x0004D930 -#endif /* CONFIG_TQM5200 */ - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#ifdef CONFIG_TQM5200 -# define SM501_FB_BASE 0xE0000000 -# define CFG_CS1_START (SM501_FB_BASE) -# define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -# define CFG_CS1_CFG 0x8F48FF70 -# define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif /* CONFIG_TQM5200 */ - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */ - /* flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -/* - * USB stuff - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */ - -/* - * IDE/ATA stuff Supports IDE harddisk - */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h deleted file mode 100644 index b6c5cbee0c..0000000000 --- a/include/configs/CATcenter.h +++ /dev/null @@ -1,765 +0,0 @@ -/* - * ueberarbeitet durch Christoph Seyfert - * - * (C) Copyright 2004-2005 DENX Software Engineering, - * Wolfgang Grandegger <wg@denx.de> - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_UART1_CONSOLE 1 /* Use second UART */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* add version variable */ -#define CONFIG_IDENT_STRING "1" - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#undef CONFIG_EXT_PHY -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_NAND0_BASE 0xFF400000 -#define CFG_NAND1_BASE 0xFF000000 -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } -#define NAND_BIG_DELAY_US 25 - -/* For CATcenter there is only NAND on the module */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - - -#define MACRO_NAND_DISABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_ENABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CFG_ENV_ADDR_REDUND 0xFFFFA000 -#define CFG_ENV_SIZE_REDUND 0x2000 - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB2AP 0x92015480 -#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x92015480 -#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ -#define CFG_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ -#define CFG_GPIO0_ISR1L 0x15555444 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FF8014 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CFG_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support - * - * Note: fake mtd_id used, no linux mtd map file - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nand0=catcenter" -#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h deleted file mode 100644 index 933fd5939b..0000000000 --- a/include/configs/CPCI750.h +++ /dev/null @@ -1,613 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2004 esd gmbh Hannover - * - * - * from db64360.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - ************************************************************************/ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif -/*-----------------------------------------------------*/ - -#include "../board/esd/cpci750/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_750FX /* we have a 750FX (override local.h) */ - -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ - -#undef CONFIG_ECC /* enable ECC support */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CFG_BOARD_NAME "CPCI750" -#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" - -/*#define CFG_HUSH_PARSER*/ -#define CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CONFIG_AUTO_COMPLETE 1 - -/* Define which ETH port will be used for connecting the network */ -#define CFG_ETH_PORT ETH_0 - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 1 -#define CONFIG_ETHER_PORT 0 - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS - -/* ----------------------------------------------------------------------------- - * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus - */ - -#define CONFIG_IPADDR "192.168.0.185" - -#define CONFIG_SERIAL "AA000001" -#define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* ----------------------------------------------------------------------------- */ - - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_CACHE \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_ELF \ - | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ - ) - -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_USE_CPCIDVI - -#ifdef CONFIG_USE_CPCIDVI -#define CONFIG_VIDEO -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_LOGO -#define CONFIG_I8042_KBD -#define CFG_ISA_IO 0 -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 80000 /* I2C speed default */ - -#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_TCLK 133000000 - -/*#define CFG_750FX_HID0 0x8000c084*/ -#define CFG_750FX_HID0 0x80008484 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CFG_INIT_RAM_LOCK -/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CFG_INTERNAL_RAM_ADDR 0xf1080000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE 0xfff00000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ - CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ - CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ - CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } -#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ - -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#endif - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* MPP Control MV64360 Appendix P P. 632*/ -#define CFG_MPP_CONTROL_0 0x00002222 /* */ -#define CFG_MPP_CONTROL_1 0x11110000 /* */ -#define CFG_MPP_CONTROL_2 0x11111111 /* */ -#define CFG_MPP_CONTROL_3 0x00001111 /* */ -/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ - - -#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ - -/* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ - /* GB has high prio. - idma has low prio - MPSC has low prio - pci has low prio 1 and 2 - cpu has high prio - Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices - ECC disable - non registered DRAM */ - /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ - /* refresh_count=0x400 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ - -#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* - * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) - * IBAT4 and DBAT4 - * FIXME: ingo disable BATs for Linux Kernel - */ -#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ -/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ - -#ifdef SETUP_HIGH_BATS_FX750 -#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT7U - -#else /* set em out of range for Linux !!!!!!!!!!! */ -#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT4U - -/* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT4U - -/* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT4U - -#endif -/* FIXME: ingo end: disable BATs for Linux Kernel */ - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ - - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_EEPROM_ADDR 0x050 -#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ - -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -/*#define CFG_L2*/ -#undef CFG_L2 - -/* #ifdef CONFIG_750CX*/ -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h deleted file mode 100644 index 020de59adc..0000000000 --- a/include/configs/CRAYL1.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CRAYL1 -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ -#define CONFIG_SYS_CLK_FREQ 25000000 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ - -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 - */ -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ -#undef CONFIG_BOOTARGS - -/* Bootcmd is overridden by the bootscript in board/cray/L1 - */ -#define CFG_AUTOLOAD "no" -#define CONFIG_BOOTCOMMAND "dhcp" - -/* - * ..during experiments.. - #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 - */ -#define CONFIG_HARD_I2C 1 /* hardware support for i2c */ -#define CONFIG_SDRAM_BANK0 1 -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_IDENT_STRING "Cray L1" -#define CONFIG_ENV_OVERWRITE 1 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTOSCRIPT 1 - - -#define CONFIG_COMMANDS (\ - CFG_CMD_BDI|\ - CFG_CMD_IMI|\ - CFG_CMD_FLASH|\ - CFG_CMD_MEMORY|\ - CFG_CMD_NET|\ - CFG_CMD_ENV|\ - CFG_CMD_CONSOLE|\ - CFG_CMD_ASKENV|\ - CFG_CMD_ECHO|\ - CFG_CMD_IMMAP|\ - CFG_CMD_REGINFO|\ - CFG_CMD_DHCP|\ - CFG_CMD_DATE|\ - CFG_CMD_RUN|\ - CFG_CMD_I2C|\ - CFG_CMD_EEPROM|\ - CFG_CMD_DIAG|\ - CFG_CMD_AUTOSCRIPT|\ - CFG_CMD_SETGETDCR) - -/* - * optional BOOTP / DHCP fields - */ -#define CONFIG_BOOTP_MASK (\ - CONFIG_BOOTP_VENDOREX|\ - CONFIG_BOOTP_SUBNETMASK|\ - CONFIG_BOOTP_GATEWAY|\ - CONFIG_BOOTP_DNS|\ - CONFIG_BOOTP_HOSTNAME|\ - CONFIG_BOOTP_BOOTFILESIZE|\ - CONFIG_BOOTP_BOOTPATH) - -/* - * how many time to fail & restart a net-TFTP before giving up & resetting - * the board hoping that a reset of net interface might help.. - */ -#define CONFIG_NET_RESET 5 - -/* - * bauds. Just to make it compile; in our case, I read the base_baud - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn - * drives the system clock. - */ -#define CFG_BASE_BAUD 403225 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ - - -#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ -#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_DRAM_TEST 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_MONITOR_BASE TEXT_BASE - - -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CFG_ENV_OFFSET 0x3c8000 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at - * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. - */ -#define CFG_SDRAM_SIZE 32 /* megs of ram */ -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) -/* END ENVIRONNEMENT FLASH */ - -/*----------------------------------------------------------------------- - * Cache Configuration. Only used to ..?? clear it, I guess.. - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in OnChipMem ) - */ -/* On Chip Memory location */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - */ -#define EEPROM_WRITE_ADDRESS 0xA0 -#define EEPROM_READ_ADDRESS 0xA1 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h deleted file mode 100644 index f67dd24806..0000000000 --- a/include/configs/DB64360.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2002 Datentechnik AG - Project: Dino - * - * - * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ - * - ************************************************************************/ - -/************************************************************************* - * - * History: - * - * $Log: DB64360.h,v $ - * Revision 1.3 2003/04/26 04:58:13 brad - * Cosmetic changes and compiler warning cleanups - * - * Revision 1.2 2003/04/23 15:48:15 ingo - * mem. map output added - * - * Revision 1.1 2003/04/17 09:31:42 ias - * keymile changes 17_04_2003 - * - * Revision 1.10 2003/03/06 12:25:04 ias - * 750 FX CPU HID settings updated - * - * Revision 1.9 2003/03/03 16:14:36 ias - * cleanup compiler warnings of printf fuctions - * - * Revision 1.8 2003/03/03 15:11:44 ias - * Marvell MPSC-UART is working - * - * Revision 1.7 2003/02/26 12:15:45 ssu - * adapted default parameters to new board flash address - * - * Revision 1.6 2003/02/25 14:55:42 ssu - * changed default environment parameters - * - * Revision 1.5 2003/02/21 17:14:23 ias - * added extended SPD handling - * - * Revision 1.4 2003/01/14 09:16:08 ias - * PPCBoot for Marvel Beta 0.9 - * - * Revision 1.3 2002/12/03 13:56:26 ias - * Environment in flash support added - * - * Revision 1.2 2002/11/29 16:53:29 ias - * Flash support for STM added - * - * Revision 1.1 2002/11/29 13:36:31 ias - * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board - * - working DDRRAM (only 32MByte of 128MB Modul) - * - working I2C Driver for SPD EEPROM read - * - working DUART 16650 for Serial Console - * - working "console" - * - * - * - ************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64360/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -/* first ethernet */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - /* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:36:00:00:00:02 -/* in the atlantis 64360 we have only 2 ETH port on the board, -if we use PCI it has its own MAC addr */ - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64360_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CFG_BOARD_NAME "DB64360" -#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" - -/*#define CFG_HUSH_PARSER */ -#undef CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 2 - -/* #undef CONFIG_ETHER_PORT_MII */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64360:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH /mnt/yellow_dog_mini - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=db64360-1" -#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" -*/ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64360 core) */ -#define CFG_TCLK 133000000 - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_750FX_HID0 0x8000c084 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CFG_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_FLASH_BASE 0xfff00000 - -#define CFG_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64360 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64360*/ -#define CFG_MPP_CONTROL_0 0x02222222 -#define CFG_MPP_CONTROL_1 0x11333011 -#define CFG_MPP_CONTROL_2 0x40431111 -#define CFG_MPP_CONTROL_3 0x00000044 - -/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64360 DDR-RAM !! */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 - -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CFG_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h deleted file mode 100644 index 1c5da54754..0000000000 --- a/include/configs/DB64460.h +++ /dev/null @@ -1,530 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64460/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -#define CONFIG_ETHADDR 64:46:00:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:46:00:00:00:02 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 64:46:00:00:00:03 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64460_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CFG_BOARD_NAME "DB64460" -#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" - -/*#define CFG_HUSH_PARSER */ -#undef CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 3 - -/* #undef CONFIG_ETHER_PORT_MII */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64460:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH /mnt/yellow_dog_mini - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=db64460-1" -#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" -*/ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64460 core) */ -#define CFG_TCLK 133000000 - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_750FX_HID0 0x8000c084 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CFG_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_FLASH_BASE 0xfff00000 - -#define CFG_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64460 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64460*/ -#define CFG_MPP_CONTROL_0 0x02222222 -#define CFG_MPP_CONTROL_1 0x11333011 -#define CFG_MPP_CONTROL_2 0x40431111 -#define CFG_MPP_CONTROL_3 0x00000044 - -/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64460 DDR-RAM !! */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 - -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CFG_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h deleted file mode 100644 index 5507f352b9..0000000000 --- a/include/configs/EP1C20.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1C20 1 /* EP1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include <cmd_confdefs.h> - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h deleted file mode 100644 index 6eca9f23dc..0000000000 --- a/include/configs/EP1S10.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S10 1 /* EP1S10 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CFG_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include <cmd_confdefs.h> - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h deleted file mode 100644 index 976e79acb6..0000000000 --- a/include/configs/EP1S40.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S40 1 /* EP1S40 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CFG_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include <cmd_confdefs.h> - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h deleted file mode 100644 index 738763b86f..0000000000 --- a/include/configs/EP88x.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2005 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Embedded Planet EP88x boards. - * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC885 - -#define CONFIG_EP88X /* Embedded Planet EP88x board */ - -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ -#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) -#define CFG_DISCOVER_PHY -#define FEC_ENET -#endif /* CONFIG_FEC_ENET */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#define CFG_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x400000 /* Default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * RAM configuration (note that CFG_SDRAM_BASE must be zero) - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ - -#define CFG_MAMR 0x00805000 - -/* - * 4096 Up to 4096 SDRAM rows - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ - -#define CFG_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CFG_FLASH_BASE 0xFC000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -#define CFG_OR0_PRELIM 0xFC000160 -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) - -#define CFG_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * BCSR - */ -#define CFG_OR3_PRELIM 0xFF0005B0 -#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CFG_BCSR 0xFA400000 - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR PISCR_PS - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR SCCR_RTSEL - -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h deleted file mode 100644 index b6d6905887..0000000000 --- a/include/configs/FPS850L.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \ - CFG_CMD_CONSOLE | \ - CFG_CMD_BDI | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_CACHE ) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h deleted file mode 100644 index 8aa6f9a3e4..0000000000 --- a/include/configs/FPS860L.h +++ /dev/null @@ -1,326 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h deleted file mode 100644 index 1510d67e5f..0000000000 --- a/include/configs/HMI10.h +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HMI10 -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_LCD -#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on COM3 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/HMI10/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0100000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4100000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC100000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 5 -#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ -#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#endif - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h deleted file mode 100644 index 706bdb94f5..0000000000 --- a/include/configs/ISPAN.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger <wg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ -#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/*----------------------------------------------------------------------- - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * If CONFIG_CONS_NONE is defined, then the serial console routines must be - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ -#undef CONFIG_CONS_NONE /* Define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ - -/*----------------------------------------------------------------------- - * Select Ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC). - * - * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must - * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ -#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if CONFIG_ETHER_INDEX == 3 - -#define CFG_PHY_ADDR 0 -#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) -#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) - -#endif /* CONFIG_ETHER_INDEX == 3 */ - -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 3 /* Port D */ - -#define CFG_MDIO_PIN 0x00040000 /* PD13 */ -#define CFG_MDC_PIN 0x00080000 /* PD12 */ - -#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ - else iop->pdat &= ~CFG_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ - else iop->pdat &= ~CFG_MDC_PIN - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#define CONFIG_8260_CLKIN 65536000 /* in Hz */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_REGINFO \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0x09900000 - -#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */ -#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ - -/* Environment is in flash, there is little space left in Serial EEPROM */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * If you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -/* 0x1686B245 */ -#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_ISB110 |\ - HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ - HRCW_CS10PC01 | HRCW_MODCK_H0101 \ - ) -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0F00000 -#ifdef CFG_REV_B -#define CFG_DEFAULT_IMMR 0xFF000000 -#endif /* CFG_REV_B */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR 0xA01C0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR 0x42250000/* 0x4205C000 */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined (CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - *----------------------------------------------------------------------- - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/*----------------------------------------------------------------------- - * Init Memory Controller: - * - * Bank Bus Machine PortSize Device - * ---- --- ------- ----------------------------- ------ - * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - */ -#define CFG_USE_FIRMWARE /* If defined - do not initialise memory - controller, rely on initialisation - performed by the Interphase boot firmware. - */ - -#define CFG_OR0_PRELIM 0xFE000882 -#ifdef CFG_REV_B -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V) -#else /* Rev. D */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V) -#endif /* CFG_REV_B */ - -#define CFG_MPTPR 0x7F00 - -/* Please note that 60x SDRAM MUST start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_60x_BR 0x00000041 -#define CFG_60x_OR 0xF0002CD0 -#define CFG_PSDMR 0x0049929A -#define CFG_PSRT 0x07 - -#define CFG_LSDRAM_BASE 0xF7000000 -#define CFG_LOC_BR 0x00001861 -#define CFG_LOC_OR 0xFF803280 -#define CFG_LSDMR 0x8285A552 -#define CFG_LSRT 0x07 - -#endif /* __CONFIG_H */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h deleted file mode 100644 index 2ad6f06985..0000000000 --- a/include/configs/KAREF.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference - * design. - ***********************************************************************/ - -/* - * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ -#undef CFG_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) -#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000) -#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) -#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) - -/* Here for completeness */ -#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C hardware support */ -#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ - - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CFG_ALT_MEMTEST 1 /* use real memory test */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ -#define CFG_PROMPT_HUSH_PS2 "> " - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of cmd args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0000000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ -#define CFG_PCI_TARGET_INIT /* let board init pci target*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CFG_LOAD_ADDR 0x8000000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info */ - -#define CFG_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h deleted file mode 100644 index a613850cf1..0000000000 --- a/include/configs/KUP4K.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_KUP4K 1 /* ...on a KUP4K module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - - -#undef CONFIG_BOOTARGS - - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ -"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ -"netdev=eth0\0" \ -"contrast=55\0" \ -"silent=1\0" \ -"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40050000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" - - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * enable I2C and select the hardware/software driver - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - - -/* List of I2C addresses to be verified by POST */ - -#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ - CFG_I2C_RTC_ADDR, \ - } - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CFG_DISCOVER_PHY -#define CONFIG_MII - -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -/* POST support */ - -#define CONFIG_POST (CFG_POST_CPU | \ - CFG_POST_RTC | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CFG_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 - -/* Address and size of Redundant Environment Sector */ -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ - -/* KUP4K use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define PCMCIA_SOCKETS_NO 2 -#define PCMCIA_MEM_WIN_NO 8 -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 2 -#define CFG_IDE_MAXDEVICE 4 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR 0x80802114 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h deleted file mode 100644 index cdf65dfd2a..0000000000 --- a/include/configs/KUP4X.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ -#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CFG_8XX_FACT 8 /* Multiply by 8 */ -#define CFG_8XX_XIN 16000000 /* 16 MHz in */ - - -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - - -#undef CONFIG_BOOTARGS - - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw;diskboot 200000 0:1;bootm 200000\0" \ -"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\ - run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\ - usb stop; bootm 200000\0" \ -"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ -"netdev=eth0\0" \ -"silent=1\0" \ -"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ -"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40040000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot" - - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * enable I2C and select the hardware/software driver - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - - -/* List of I2C addresses to be verified by POST */ - -#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ - CFG_I2C_RTC_ADDR, \ - } - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CFG_DISCOVER_PHY -#define CONFIG_MII - -#undef CONFIG_KUP4K_LOGO - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -/* POST support */ - -#define CONFIG_POST (CFG_POST_CPU | \ - CFG_POST_RTC | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CFG_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 - -/* Address and size of Redundant Environment Sector */ -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS) - - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ - -/* KUP4K use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define PCMCIA_SOCKETS_NO 1 -#define PCMCIA_MEM_WIN_NO 8 -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 2 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - - -#define CFG_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR 0x80802114 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 - -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_SL811HS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h deleted file mode 100644 index f0fc013434..0000000000 --- a/include/configs/M5271EVB.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Configuation settings for the Freescale M5271EVB - * - * Based on MC5272C3 and r5200 board configs - * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com> - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5271EVB_H -#define _M5271EVB_H - -#define DEBUG -#undef DEBUG - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_M5271EVB /* define board type */ - -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#undef CONFIG_WATCHDOG /* disable watchdog */ - -#define CONFIG_BOOTDELAY 5 - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#else -#define CFG_ENV_ADDR 0xffe04000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#endif - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -#define CFG_HZ 1000000 -#define CFG_CLK 100000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_MBAR 0x40000000 /* Register Base Addrs */ - -/* Enable FEC ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CFG_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CFG_MONITOR_BASE 0x20000 -#else -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) -#endif - -#define CFG_MONITOR_LEN 0x40000 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 1000 - -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_SIZE 0x200000 - -/* Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 - -/* Port configuration */ -#define CFG_FECI2C 0xF0 - -#endif /* _M5271EVB_H */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h deleted file mode 100644 index c958d39704..0000000000 --- a/include/configs/MBX.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Configuation settings for the MBX8xx board. - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Changed 2002-10-01 - * Added PCMCIA defines mostly taken from other U-Boot boards that - * have PCMCIA already working. If you find any bugs, incorrect assumptions - * feel free to fix them yourself and submit a patch. - * Rod Boyce <rod_boyce@stratexnet.com. - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MBX 1 /* ...on an MBX module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -/* Define this to use the PCI bus */ -#undef CONFIG_USE_PCI - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ (50000000UL) -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \ - CFG_CMD_PCMCIA | CFG_CMD_IDE ) - -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map as defined by the MBX PGM - */ -#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ -#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CFG_PCIMEM_OR 0xA0000108 -#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CFG_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfe000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) -#define CFG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CFG_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 - -#define CONFIG_PCMCIA_SLOT_A 1 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h deleted file mode 100644 index 3917c33198..0000000000 --- a/include/configs/MBX860T.h +++ /dev/null @@ -1,402 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T MBX board. - * Copied from the FADS stuff, which was originally copied from the MBX stuff! - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * Rob Taylor coverted it back to MBX - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MBX 1 - -#define CONFIG_8xx_CPUCLOCK 40 -#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) -#define TARGET_SYSTEM_FREQUENCY 40 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 40000000 /* 50 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_8xx_TFTP_MODE - -#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTARGS " " -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFA00000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) -#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CFG_PCIMEM_OR 0xA0000108 -#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CFG_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x00000000 -/*0xFE000000*/ -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN) -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) -#define CFG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CFG_SCCR SCCR_TBS - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CFG_BR0_PRELIM (0xFE000000 | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 -#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR 0x13821000 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_40MHZ 1 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC1_ENET 1 -#define CONFIG_FEC_ENET 1 -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h deleted file mode 100644 index 465a4ecb8b..0000000000 --- a/include/configs/METROBOX.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * METROBOX.h - configuration Sandburst MetroBox - ***********************************************************************/ - -/* - * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ - * - * - * $Log: METROBOX.h,v $ - * Revision 1.21 2005/06/03 15:05:25 tsawyer - * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB - * - * Revision 1.20 2005/04/11 20:51:11 tsawyer - * fix ethernet - * - * Revision 1.19 2005/04/06 15:13:36 tsawyer - * Update appropriate files to coincide with u-boot 1.1.3 - * - * Revision 1.18 2005/03/10 14:16:02 tsawyer - * add def'n for cis8201 short etch option. - * - * Revision 1.17 2005/03/09 19:49:51 tsawyer - * Remove KGDB to allow use of 2nd serial port - * - * Revision 1.16 2004/12/02 19:00:23 tsawyer - * Add misc_init_f to turn on i2c-1 and all four fans before sdram init - * - * Revision 1.15 2004/09/15 18:04:12 tsawyer - * add multiple serial port support - * - * Revision 1.14 2004/09/03 15:27:51 tsawyer - * All metrobox boards are at 66.66 sys clock - * - * Revision 1.13 2004/08/05 20:27:46 tsawyer - * Remove system ace definitions, add net console support - * - * Revision 1.12 2004/07/29 20:00:13 tsawyer - * Add i2c bus 1 - * - * Revision 1.11 2004/07/21 13:44:18 tsawyer - * SystemACE is out, CF direct to local bus is in - * - * Revision 1.10 2004/06/29 19:08:55 tsawyer - * Add CONFIG_MISC_INIT_R - * - * Revision 1.9 2004/06/28 21:30:53 tsawyer - * Fix default BOOTARGS - * - * Revision 1.8 2004/06/17 15:51:08 tsawyer - * auto complete - * - * Revision 1.7 2004/06/17 15:08:49 tsawyer - * Add autocomplete - * - * Revision 1.6 2004/06/15 12:33:57 tsawyer - * debugging checkpoint - * - * Revision 1.5 2004/06/12 19:48:28 tsawyer - * Debugging checkpoint - * - * Revision 1.4 2004/06/02 13:03:06 tsawyer - * Fix eth addrs - * - * Revision 1.3 2004/05/18 19:56:10 tsawyer - * Change default bootcommand to pImage.metrobox - * - * Revision 1.2 2004/05/18 14:13:44 tsawyer - * Add bringup values for bootargs and bootcommand. - * Remove definition of ipaddress and serverip addresses. - * - * Revision 1.1 2004/04/16 15:08:54 tsawyer - * Initial Revision - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_METROBOX 1 /* Board is Metrobox */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ -#undef CFG_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Metrobox" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) -#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) -#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C hardware support */ -#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ - - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " -#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) - -/* tbs 09-March-2005 Removed to be able to use 2nd serial */ -/* CFG_CMD_KGDB | \ */ - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CFG_ALT_MEMTEST 1 /* use real memory test */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ -#define CFG_PROMPT_HUSH_PS2 "> " - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of cmd args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0000000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ -#define CFG_PCI_TARGET_INIT /* let board init pci target*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CFG_LOAD_ADDR 0x8000000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info */ - -#define CFG_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h deleted file mode 100644 index 03bd4e9542..0000000000 --- a/include/configs/MIP405.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************** - * High Level Configuration Options - * (easy to change) - ***********************************************************/ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_MIP405 1 /* ...on a MIP405 board */ -/*********************************************************** - * Note that it may also be a MIP405T board which is a subset of the - * MIP405 - ***********************************************************/ -/*********************************************************** - * WARNING: - * CONFIG_BOOT_PCI is only used for first boot-up and should - * NOT be enabled for production bootloader - ***********************************************************/ -/*#define CONFIG_BOOT_PCI 1*/ -/*********************************************************** - * Clock - ***********************************************************/ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/*********************************************************** - * Command definitions - ***********************************************************/ -#define MIP405_COMMON_CMDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) - -#if defined(CONFIG_MIP405T) -#define CONFIG_COMMANDS \ - MIP405_COMMON_CMDS -#else -#define CONFIG_COMMANDS \ - (MIP405_COMMON_CMDS | \ - CFG_CMD_USB | \ - CFG_CMD_DOC ) - -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_NAND_LEGACY - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -/************************************************************** - * I2C Stuff: - * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address - * 0x53. - * The Atmel EEPROM uses 16Bit addressing. - ***************************************************************/ - -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ - /* 64 byte page write mode using*/ - /* last 6 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ - -/*************************************************************** - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - ***************************************************************/ -/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 -*/ -/************************************************************** - * Environment definitions - **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ - -#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ - -#define CONFIG_IPADDR 10.0.0.100 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_PREBOOT -/*************************************************************** - * defines if the console is stored in the environment - ***************************************************************/ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -/*************************************************************** - * defines if an overwrite_console function exists - *************************************************************/ -#define CFG_CONSOLE_OVERWRITE_ROUTINE -#define CFG_CONSOLE_INFO_QUIET -/*************************************************************** - * defines if the overwrite_console should be stored in the - * environment - **************************************************************/ -#undef CFG_CONSOLE_ENV_OVERWRITE - -/************************************************************** - * loads config - *************************************************************/ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MISC_INIT_R -/*********************************************************** - * Miscellaneous configurable options - **********************************************************/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_BASE_BAUD 916667 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ - /* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=mip405-0" -#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * Logbuffer Configuration - */ -#undef CONFIG_LOGBUFFER /* supported but not enabled */ -/*----------------------------------------------------------------------- - * Bootcountlimit Configuration - */ -#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ - -/*----------------------------------------------------------------------- - * POST Configuration - */ -/* - * Init Memory Controller: - */ -#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ -#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* Peripheral Bus Mapping */ -#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ -#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ -#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ - -#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in On Chip SRAM) - */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 32) - -#ifdef CONFIG_POST /* reserve one word for POST Info */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#endif - -#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ -#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*********************************************************************** - * External peripheral base address - ***********************************************************************/ -#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT -/************************************************************ - * Ethernet Stuff - ***********************************************************/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ -#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#if defined(CONFIG_MIP405T) -#define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ -#else -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#endif - -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* reset for ide supported... */ -#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ -#define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -/************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -/************************************************************ - * Keyboard support - ************************************************************/ -#undef CONFIG_ISA_KEYBOARD - -/************************************************************ - * Video support - ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#undef CONFIG_VIDEO_ONBOARD -/************************************************************ - * USB support EXPERIMENTAL - ************************************************************/ -#if !defined(CONFIG_MIP405T) -#define CONFIG_USB_UHCI -#define CONFIG_USB_KEYBOARD -#define CONFIG_USB_STORAGE - -/* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ -#endif -/************************************************************ - * Debug support - ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/************************************************************ - * support BZIP2 compression - ************************************************************/ -#define CONFIG_BZIP2 1 - -/************************************************************ - * Ident - ************************************************************/ - -#define VERSION_TAG "released" -#if !defined(CONFIG_MIP405T) -#define CONFIG_ISO_STRING "MEV-10072-001" -#else -#define CONFIG_ISO_STRING "MEV-10082-001" -#endif - -#if !defined(CONFIG_BOOT_PCI) -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG -#else -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" -#endif - - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h deleted file mode 100644 index 2fceae504a..0000000000 --- a/include/configs/MPC8349EMDS.h +++ /dev/null @@ -1,730 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ - -#undef CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ - -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif -#endif - -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - -#define CFG_IMMR 0xE0000000 - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CFG_DDR_SIZE 256 /* MB */ -#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) -#define CFG_DDR_TIMING_1 0x36332321 -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ -#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ -#else -/* the default burst length is 4 - for 64-bit data path */ -#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* flash size in MB */ -/* #define CFG_FLASH_USE_BUFFER_WRITE */ - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ - BR_V) /* valid */ - -#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ - -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CFG_BCSR 0xE2400000 -#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ -#define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) -#define CFG_LBC_LBCR 0x00000000 - -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CFG_OR2_PRELIM 0xFC006901 - -#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 - -/* TSEC */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) - -/* USB */ -#define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_MMIO_BASE 0x90000000 -#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE -#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xE2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CFG_PCI2_MEM_BASE 0xA0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_MMIO_BASE 0xB0000000 -#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE -#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xE2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ -#define CONFIG_TSEC_ENET /* TSEC ethernet support */ - -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE \ - ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - | CFG_CMD_DATE \ - ) -#endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -/* System IO Config */ -#define CFG_SICRH SICRH_TSOBI1 -#define CFG_SICRL SICRL_LDP_A - -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK - -/* #define CFG_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST ) */ - - -#define CFG_HID2 HID2_HBE - -/* DDR @ 0x00000000 */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ -#ifdef CONFIG_PCI -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT1L (0) -#define CFG_IBAT1U (0) -#define CFG_IBAT2L (0) -#define CFG_IBAT2U (0) -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT3L (0) -#define CFG_IBAT3U (0) -#define CFG_IBAT4L (0) -#define CFG_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT7L (0) -#define CFG_IBAT7U (0) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U -#define CFG_DBAT4L CFG_IBAT4L -#define CFG_DBAT4U CFG_IBAT4U -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:04:9f:ef:23:33 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME mpc8349emds -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ - "upd=run load;run update\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h deleted file mode 100644 index bacccd1a3a..0000000000 --- a/include/configs/MPC8349ITX.h +++ /dev/null @@ -1,790 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - MPC8349E-mITX board configuration file - - Memory map: - - 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash - 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) - - I2C address list: - Align. Board - Bus Addr Part No. Description Length Location - ---------------------------------------------------------------- - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - - I2C1 0x20 PCF8574 I2C Expander 0 U8 - I2C1 0x21 PCF8574 I2C Expander 0 U10 - I2C1 0x38 PCF8574A I2C Expander 0 U8 - I2C1 0x39 PCF8574A I2C Expander 0 U10 - I2C1 0x51 (DDR) DDR EEPROM 1 U1 - I2C1 0x68 DS1339 RTC 1 U68 - - Note that a given board has *either* a pair of 8574s or a pair of 8574As. -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ -#define CONFIG_MPC8349 /* MPC8349 specific */ - -#define CONFIG_PCI - -#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ -#define CONFIG_RTC_DS1337 - -/* I2C */ -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C - -#define CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R - -#define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 -#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ - -#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ -#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ -#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ -#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ -#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ - -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* Don't probe these addresses: */ -#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ - {1, CFG_I2C_8574_ADDR2}, \ - {1, CFG_I2C_8574A_ADDR1}, \ - {1, CFG_I2C_8574A_ADDR2}} -/* Bit definitions for the 8574[A] I2C expander */ -#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ -#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ -#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ -#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ -#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ - -#undef CONFIG_SOFT_I2C - -#endif - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif - -#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ - -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING -#define CFG_83XX_DDR_USES_CS0 - -#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ - #define CFG_DDR_SIZE 256 /* Mb */ - #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - - #define CFG_DDR_TIMING_1 0x26242321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ -#endif - -/* FLASH on the Local Bus */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ -#define CFG_FLASH_EMPTY_INFO - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) -#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ - -/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ - -#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ - -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ -#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -#ifdef CONFIG_COMPACT_FLASH - -#define CFG_CF_BASE 0xF0000000 - -#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) - -#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_CF_BASE -#define CFG_ATA_DATA_OFFSET 0x0000 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 -#define CFG_ATA_STRIDE 2 - -#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ - -#endif - -#define CONFIG_DOS_PARTITION - -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) -#define CFG_LBC_LBCR 0x00000000 - -#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - -#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" - -#ifdef CONFIG_PCI - -#define CONFIG_MPC83XX_PCI2 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) -#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE -#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xE2000000 -#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#ifdef CONFIG_MPC83XX_PCI2 -#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) -#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE -#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) -#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ -#endif - -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#endif - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR 0x00000000 - #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE - #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* TSEC */ - -#ifdef CONFIG_TSEC_ENET - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif - -#define CONFIG_MII -#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ - -#define CONFIG_MPC83XX_TSEC1 - -#ifdef CONFIG_MPC83XX_TSEC1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CFG_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define CFG_TSEC2_OFFSET 0x25000 -#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ -#define TSEC2_PHY_ADDR 4 -#define TSEC2_PHYIDX 0 -#endif - -#define CONFIG_ETHPRIME "Freescale TSEC" - -#endif - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* CONFIG_COMMANDS */ - -#ifdef CONFIG_COMPACT_FLASH -#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) -#else -#define CONFIG_COMMANDS_CF 0 -#endif - -#ifdef CONFIG_PCI -#define CONFIG_COMMANDS_PCI CFG_CMD_PCI -#else -#define CONFIG_COMMANDS_PCI 0 -#endif - -#ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS_I2C CFG_CMD_I2C -#else -#define CONFIG_COMMANDS_I2C 0 -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CONFIG_COMMANDS_CF | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CONFIG_COMMANDS_I2C | \ - CONFIG_COMMANDS_PCI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DATE | \ - CFG_CMD_CACHE | \ - CFG_CMD_IRQ) -#include <cmd_confdefs.h> - -/* Watchdog */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ -#endif - -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef PCI_64BIT -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -/* System performance */ -#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ -#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ - -/* System IO Config */ -#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ -#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) - -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT - -#define CFG_HID2 HID2_HBE - -/* DDR @ 0x00000000 */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ -#ifdef CONFIG_PCI -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT1L 0 -#define CFG_IBAT1U 0 -#define CFG_IBAT2L 0 -#define CFG_IBAT2U 0 -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT3L 0 -#define CFG_IBAT3U 0 -#define CFG_IBAT4L 0 -#define CFG_IBAT4U 0 -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT7L 0 -#define CFG_IBAT7U 0 - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U -#define CFG_DBAT4L CFG_IBAT4L -#define CFG_DBAT4U CFG_IBAT4U -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_MPC83XX_TSEC1 -#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 -#endif - -#ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 -#endif - -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin - -#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 -#else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ -#endif - -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -#define CONFIG_BOOTARGS \ - "root=/dev/nfs rw" \ - " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ - MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ - MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ - " console=ttyS0," MK_STR(CONFIG_BAUDRATE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - - -#undef MK_STR -#undef XMK_STR - -#endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h deleted file mode 100644 index 8ad6551de7..0000000000 --- a/include/configs/MPC8360EMDS.h +++ /dev/null @@ -1,635 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * Dave Liu <daveliu@freescale.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ - -/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - -/* - * Hardware Reset Configuration Word - */ -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CE_PLL_VCO_DIV_4 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X6 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_PCISLAVE -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCICKDRV_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCICKDRV_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#endif - -/* - * System IO Config - */ -#define CFG_SICRH 0x00000000 -#define CFG_SICRL 0x40000000 - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - -/* - * IMMR new address - */ -#define CFG_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE - -#define CFG_83XX_DDR_USES_CS0 - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CFG_DDR_SIZE 256 /* MB */ -#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) -#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ -#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ -#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ -#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ -#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ -#endif - -/* - * Memory test - */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) -#define CFG_LBC_LBCR 0x00000000 - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ - -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ - -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM - -/* - * BCSR on the Local Bus - */ -#define CFG_BCSR 0xF8000000 -#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ - -#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON 0x0063b723 - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - -#endif - -/* - * Windows to access PIB via local bus - */ -#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ -#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ - -/* - * CS4 on Local Bus, to PIB - */ -#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ -#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ - -/* - * CS5 on Local Bus, to PIB - */ -#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ -#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8360@0" -#define OF_SOC "soc8360@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI_MEM_BASE 0x80000000 -#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE -#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_MMIO_BASE 0x90000000 -#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE -#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0xE0300000 -#define CFG_PCI_IO_PHYS 0xE0300000 -#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE -#define CFG_PCI_SLV_MEM_BUS 0x00000000 -#define CFG_PCI_SLV_MEM_SIZE 0x80000000 - - -#ifdef CONFIG_PCI - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "Freescale GETH" -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ -#define CFG_UEC1_RX_CLK QE_CLK_NONE -#define CFG_UEC1_TX_CLK QE_CLK9 -#define CFG_UEC1_ETH_TYPE GIGA_ETH -#define CFG_UEC1_PHY_ADDR 0 -#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ -#define CFG_UEC2_RX_CLK QE_CLK_NONE -#define CFG_UEC2_TX_CLK QE_CLK4 -#define CFG_UEC2_ETH_TYPE GIGA_ETH -#define CFG_UEC2_PHY_ADDR 1 -#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII -#endif - -/* - * Environment - */ - -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C ) -#endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK -#define CFG_HID2 HID2_HBE - -/* - * Cache Config - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ -#endif - -/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* BCSR: cache-inhibit and guarded */ -#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* Local bus SDRAM: cacheable */ -#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CFG_DBAT4L CFG_IBAT4L -#define CFG_DBAT4U CFG_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) -#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U -#else -#define CFG_IBAT6L (0) -#define CFG_IBAT6U (0) -#define CFG_IBAT7L (0) -#define CFG_IBAT7U (0) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_ETHADDR 00:04:9f:ef:01:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h deleted file mode 100644 index 74a84f4e86..0000000000 --- a/include/configs/MPC8540ADS.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8540ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ - -#ifndef CONFIG_HAS_FEC -#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ -#endif - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - * - * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to - * 33MHz to accommodate, based on a PCI pin. - * Note that PCI-X won't work at 33MHz. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ - #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ - #define CFG_DDR_CS0_CONFIG 0x80000002 - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BR4_PRELIM 0xf8000801 -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8540@0" -#define OF_SOC "soc8540@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" - -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - - -#if CONFIG_HAS_FEC -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h deleted file mode 100644 index db389cfe67..0000000000 --- a/include/configs/MPC8541CDS.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8541cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8541 1 /* MPC8541 specific */ -#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8541@0" -#define OF_SOC "soc8541@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_MPC85XX_PCI2 -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h deleted file mode 100644 index 7c4849fadf..0000000000 --- a/include/configs/MPC8548CDS.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8548cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ - -#undef CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8548@0" -#define OF_SOC "soc8548@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_85XX_PCI2 - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 -#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 - -/* Options are: eTSEC[0-3] */ -#define CONFIG_ETHPRIME "eTSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h deleted file mode 100644 index 4c8b4e73f3..0000000000 --- a/include/configs/MPC8555CDS.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8555cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8555 1 /* MPC8555 specific */ -#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8555@0" -#define OF_SOC "soc8555@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_MPC85XX_PCI2 - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h deleted file mode 100644 index 835bf5cb64..0000000000 --- a/include/configs/MPC8560ADS.h +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8560ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ - #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ - #define CFG_DDR_CS0_CONFIG 0x80000002 - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BR4_PRELIM 0xf8000801 -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8560@0" -#define OF_SOC "soc8560@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h deleted file mode 100644 index 246ac7f316..0000000000 --- a/include/configs/MPC8641HPCN.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor. - * - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8641HPCN board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ -#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG - -#ifdef RUN_DIAG -#define CFG_DIAG_ADDR 0xff800000 -#endif - -#define CFG_RESET_ADDRESS 0xfff00100 - -/*#undef CONFIG_PCI*/ -#define CONFIG_PCI - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_NUM_DDR_CONTROLLERS 2 -/* #define CONFIG_DDR_INTERLEAVE 1 */ -#define CACHE_LINE_INTERLEAVING 0x20000000 -#define PAGE_INTERLEAVING 0x21000000 -#define BANK_INTERLEAVING 0x22000000 -#define SUPER_BANK_INTERLEAVING 0x23000000 - - -#define CONFIG_ALTIVEC 1 - -/* - * L2CR setup -- make sure this is right for your board! - */ -#define CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define MPC86xx_DDR_SDRAM_CLK_CNTL - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ - -#else - /* - * Manually set up DDR1 parameters - */ - - #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ - - #define CFG_DDR_CS0_BNDS 0x0000000F - #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ - #define CFG_DDR_EXT_REFRESH 0x00000000 - #define CFG_DDR_TIMING_0 0x00260802 - #define CFG_DDR_TIMING_1 0x39357322 - #define CFG_DDR_TIMING_2 0x14904cc8 - #define CFG_DDR_MODE_1 0x00480432 - #define CFG_DDR_MODE_2 0x00000000 - #define CFG_DDR_INTERVAL 0x06090100 - #define CFG_DDR_DATA_INIT 0xdeadbeef - #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 - #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ - #define CFG_DDR_CONTROL2 0x04400000 - - /* Not used in fixed_sdram function */ - - #define CFG_DDR_MODE 0x00000022 - #define CFG_DDR_CS1_BNDS 0x00000000 - #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ - #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ - #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ - #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ -#endif - -#define CFG_ID_EEPROM 1 -#define ID_EEPROM_ADDR 0x57 - -/* - * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. - * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff - * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. - * However, when u-boot comes up, the flash_init needs hard start addresses - * to build its info table. For user convenience, the flash addresses is - * fe800000 and ff800000. That way, u-boot knows where the flash is - * and the user can download u-boot code from promjet to fef00000, a - * more intuitive location than fe700000. - * - * Note that, on switching the boot location, fef00000 becomes fff00000. - */ -#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ -#define CFG_FLASH_BASE2 0xff800000 - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} - -#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ - -#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ - -#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ -#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ - -#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ -#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ - - -#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ - -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#if defined(CFG_RAMBOOT) -#undef CFG_FLASH_CFI_DRIVER -#undef CONFIG_SPD_EEPROM -#define CFG_SDRAM_SIZE 256 -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#ifndef CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ -#else -#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ -#endif -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * Pass open firmware flat tree to kernel - */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" - -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3100 - -/* - * RapidIO MMU - */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -/* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 - -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#undef CFG_SCSI_SCAN_BUS_REVERSE - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_RTL8139 - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_SCSI_AHCI - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CFG_SCSI_MAX_SCSI_ID 4 -#define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) -#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE -#endif - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_MPC86XX_TSEC1 1 -#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC86XX_TSEC2 1 -#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" -#define CONFIG_MPC86XX_TSEC3 1 -#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" -#define CONFIG_MPC86XX_TSEC4 1 -#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR - */ -#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CFG_IBAT0U CFG_DBAT0U - -/* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 512M PCI-Express 1 Memory - * 0xa000_0000 512M PCI-Express 2 Memory - * Changed it for operating from 0xd0000000 - */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U CFG_DBAT1U - -/* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M RapidIO Memory - */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT2U CFG_DBAT2U - -/* - * BAT3 4M Cache-inhibited, guarded - * 0xf800_0000 4M CCSR - */ -#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U CFG_DBAT3U - -/* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 - * Note that this is at 0xe0000000 - */ -#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U CFG_DBAT4U - -/* - * BAT5 128K Cacheable, non-guarded - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_IBAT5L CFG_DBAT5L -#define CFG_IBAT5U CFG_DBAT5U - -/* - * BAT6 32M Cache-inhibited, guarded - * 0xfe00_0000 32M FLASH - */ -#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT6U CFG_DBAT6U - -#define CFG_DBAT7L 0x00000000 -#define CFG_DBAT7U 0x00000000 -#define CFG_IBAT7L 0x00000000 -#define CFG_IBAT7U 0x00000000 - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CFG_CMD_EXT2) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CGF_CMD_EXT2) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_IMLS \ - | CFG_CMD_FLASH \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CFG_CMD_EXT2) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:01 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD -#endif - -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 - -#define CONFIG_IPADDR 192.168.1.100 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /opt/nfsroot -#define CONFIG_BOOTFILE uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=400000\0" \ - "dtbfile=mpc8641_hpcn.dtb\0" \ - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ - "maxcpus=2" - - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h deleted file mode 100644 index 831cc5ecd3..0000000000 --- a/include/configs/MPC86xADS.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MPC8xxADS board. Copied from the FADS config. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* board type */ -#define CONFIG_MPC86xADS 1 /* new ADS */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -/* CPU type - pick one of these */ -#define CONFIG_MPC866T 1 -#undef CONFIG_MPC866P -#undef CONFIG_MPC859T -#undef CONFIG_MPC859DSL -#undef CONFIG_MPC852T - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#define CFG_8xx_CPUCLK_MAX 80000000 - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "fads.h" - -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h deleted file mode 100644 index 1867c5bf0a..0000000000 --- a/include/configs/MPC885ADS.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MPC885ADS board. Values common to all FADS family boards - * are in board/fads/fads.h - * - * Copyright (C) 2003-2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#define CFG_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SDRAM_50MHZ 1 - -#include "fads.h" - -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#define CONFIG_HAS_ETH1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h deleted file mode 100644 index 35dfe25d62..0000000000 --- a/include/configs/NSCU.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ -#define CONFIG_NSCU 1 - -#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ - -#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/NSCU/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -/* NSCU use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ -#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */ -#define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */ - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB -#define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ -#define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \ - OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) -#define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_GPCM | BR_V ) -#endif /* CONFIG_ISP1362_USB */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#undef CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -/* #define CONFIG_ETHPRIME "FEC ETHERNET" */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h deleted file mode 100644 index 5630e34251..0000000000 --- a/include/configs/ORSG.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ORSG 1 /* ...on a ORSG board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h deleted file mode 100644 index 875449c564..0000000000 --- a/include/configs/P3G4.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_P3G4 1 /* this is a P3G4 board */ -#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CFG_BOARD_NAME "P3G4" - -#undef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -#define CONFIG_NET_MULTI /* attempt all available adapters */ - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3g4\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_74xx\0" \ - "bootfile=/tftpboot/p3g4/uImage\0" \ - "kernel_addr=ff000000\0" \ - "ramdisk_addr=ff010000\0" \ - "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_BSP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xff000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 1 -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CFG_GT_REGS 0xf8000000 -#define CFG_DEV_BASE 0xff000000 - -#define CFG_DEV0_SPACE CFG_DEV_BASE -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) - -#define CFG_DEV0_SIZE _8M /* Flash bank */ -#define CFG_DEV1_SIZE 0 /* unused */ -#define CFG_DEV2_SIZE 0 /* unused */ -#define CFG_DEV3_SIZE 0 /* unused */ - -#define CFG_16BIT_BOOT_PAR 0xc01b5e7c -#define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR - -#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ - -# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ - -#define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ - -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#undef CFG_INIT_CHAN1 -#undef CFG_INIT_CHAN2 - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) - -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 - -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CFG_I2C_SPEED 400000 -#define CFG_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE -#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ -#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR 0xFFFE0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h deleted file mode 100644 index 8f6abcfb43..0000000000 --- a/include/configs/PATI.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: PATI.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ - CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ - CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ - CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ -) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -#define CONFIG_PREBOOT - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00010000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ -/* - * Start addresses for the final memory configuration - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CFG_FLASH_BASE 0xffC00000 /* External flash */ -#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ -#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ -#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ - -#define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ - - -#define CFG_ENV_IS_IN_EEPROM -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 -#endif - -#undef CFG_ENV_IS_IN_FLASH -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ -#endif - - -#define CONFIG_SPI 1 -#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */ -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#undef CONFIG_WATCHDOG -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ - - -#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ -/* SDRAM */ -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ -/* PCI */ -#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) -/* config registers: */ -#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR3_PRELIM (0xffff0000) - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CFG_DER 0x00000000 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define VERSION_TAG "released" -#define CONFIG_ISO_STRING "MEV-10084-001" - -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h deleted file mode 100644 index 3a7f7f0647..0000000000 --- a/include/configs/PCI5441.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PCI5441 1 /* PCI-5441 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include <cmd_confdefs.h> - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h deleted file mode 100644 index 130beb78e6..0000000000 --- a/include/configs/PCIPPC6.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-6 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SCSI | \ - CFG_CMD_SNTP ) - - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include <cmd_confdefs.h> - -#define CFG_NAND_LEGACY - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 64 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ - CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x8000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR -#define CFG_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT0L CFG_DBAT0L -#define CFG_IBAT0U CFG_DBAT0U -#define CFG_IBAT1L CFG_DBAT1L -#define CFG_IBAT1U CFG_DBAT1U -#define CFG_IBAT2L CFG_DBAT2L -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_IBAT3L CFG_DBAT3L -#define CFG_IBAT3U CFG_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CFG_HZ 1000 -#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ -#define CFG_CPU_CLK 300000000 -#define CFG_BUS_CLK 100000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#undef CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - - -#define CONFIG_SCSI_SYM53C8XX -#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ -#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ -#define CFG_SCSI_SPIN_UP_TIME 2 -#define CFG_SCSI_SCAN_BUS_REVERSE 0 -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h deleted file mode 100644 index 806e95f480..0000000000 --- a/include/configs/PIP405.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************** - * High Level Configuration Options - * (easy to change) - ***********************************************************/ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PIP405 1 /* ...on a PIP405 board */ -/*********************************************************** - * Clock - ***********************************************************/ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/*********************************************************** - * Command definitions - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_IDE | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_CACHE | \ - CFG_CMD_IRQ | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO | \ - CFG_CMD_FDC | \ - CFG_CMD_SCSI | \ - CFG_CMD_FAT | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_USB | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DOC | \ - CFG_CMD_PING | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_NAND_LEGACY - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -/************************************************************** - * I2C Stuff: - * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address - * 0x53. - * Caution: on the same bus is the SPD (Serial Presens Detect - * EEPROM of the SDRAM - * The Atmel EEPROM uses 16Bit addressing. - ***************************************************************/ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x53 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */ - -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ - /* 64 byte page write mode using*/ - /* last 6 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - - -/*************************************************************** - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - ***************************************************************/ -#define SPD_EEPROM_ADDRESS 0x50 - -#define CONFIG_BOARD_EARLY_INIT_F -/************************************************************** - * Environment definitions - **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ - - -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ - - -#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ - -#define CONFIG_IPADDR 10.0.0.100 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_PREBOOT -/*************************************************************** - * defines if the console is stored in the environment - ***************************************************************/ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -/*************************************************************** - * defines if an overwrite_console function exists - *************************************************************/ -#define CFG_CONSOLE_OVERWRITE_ROUTINE -#define CFG_CONSOLE_INFO_QUIET -/*************************************************************** - * defines if the overwrite_console should be stored in the - * environment - **************************************************************/ -#undef CFG_CONSOLE_ENV_OVERWRITE - -/************************************************************** - * loads config - *************************************************************/ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MISC_INIT_R -/*********************************************************** - * Miscellaneous configurable options - **********************************************************/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ - /* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - */ -#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ -#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF4000000 -#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in On Chip SRAM) - */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*********************************************************************** - * External peripheral base address - ***********************************************************************/ -#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT -/************************************************************ - * Ethernet Stuff - ***********************************************************/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */ -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* reset for ide supported... */ -#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ -#define CONFIG_SUPPORT_VFAT - -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ - * SCSI support (experimental) only SYM53C8xx supported - ************************************************************/ -#define CONFIG_SCSI_SYM53C8XX -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ -#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ -#define CFG_SCSI_SPIN_UP_TIME 2 - -/************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -/************************************************************ - * Keyboard support - ************************************************************/ -#define CONFIG_ISA_KEYBOARD - -/************************************************************ - * Video support - ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ - -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_USB_UHCI -#define CONFIG_USB_KEYBOARD -#define CONFIG_USB_STORAGE - -/* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ - -/************************************************************ - * Debug support - ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/************************************************************ - * support BZIP2 compression - ************************************************************/ -#define CONFIG_BZIP2 1 - -/************************************************************ - * Ident - ************************************************************/ -#define VERSION_TAG "released" -#define CONFIG_ISO_STRING "MEV-10066-001" -#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG - - -#endif /* __CONFIG_H */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h deleted file mode 100644 index 83a7ec27b4..0000000000 --- a/include/configs/PK1C20.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PK1C20 1 /* PK1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include <cmd_confdefs.h> - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ -#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ -#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ -#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ - -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ - -/*------------------------------------------------------------------------ - * JFFS2 - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS_CUSTOM_PART /* board defined part */ -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h deleted file mode 100644 index 4fb54402b1..0000000000 --- a/include/configs/PM854.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * pm854 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_PM854 1 /* PM854 board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47444321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#define CONFIG_E1000 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm854/uImage - -#define CONFIG_HOSTNAME pm854 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm854/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h deleted file mode 100644 index 87ab934873..0000000000 --- a/include/configs/PM856.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MicroSys PM856 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8560 1 /* MPC8560 specific */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ -#define CONFIG_PM856 1 /* PM856 board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47444321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#endif /* CONFIG_TSEC_ENET */ - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ -#define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE) - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm856/uImage - -#define CONFIG_HOSTNAME pm856 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm856/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h deleted file mode 100644 index 3e7d1154cf..0000000000 --- a/include/configs/PMC405.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PMC405 1 /* ...on a PMC405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */ -#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */ -#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() - -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */ -#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFFC0000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_INCREMENT 0x01000000 - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT } -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - second bank contains u-boot - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x01b00000 -#define CONFIG_JFFS2_PART_OFFSET 0x00400000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=pmc405-0" -#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 2 (CAN0, 1, RTC) initialization */ -#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 -> unused */ - -/* Memory Bank 4 (NVRAM) initialization */ -#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * GPIOs - */ -#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */ -#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */ -#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ -#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */ -#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h deleted file mode 100644 index 6848f7d5c8..0000000000 --- a/include/configs/PN62.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_PN62 1 - -#define CONFIG_CONS_INDEX 1 - - -#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_LOADS | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMLS ) - -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ - CFG_CMD_PCI |\ - CFG_CMD_BSP) - -#define CONFIG_BAUDRATE 19200 /* console baudrate */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 -#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_BOOTARGS -/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/ram rw " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 200000; bootm" - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ - -/* - * Networking stuff - */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ -#define CONFIG_PCNET_79C973 - -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ - - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 - -#define CFG_RESET_ADDRESS 0xfff00100 - -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - - -#define CFG_NO_FLASH 1 /* There is no FLASH memory */ - -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ - -/* - * Serial port configuration - */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 1843200 - -#define CFG_NS16550_COM1 0xff800008 -#define CFG_NS16550_COM2 0xff800000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CFG_EUMB_ADDR 0xFCE00000 - -/* MCCR1 */ -#define CFG_ROMNAL 3 /* rom/flash next access time */ -#define CFG_ROMFAL 7 /* rom/flash access time */ - -/* MCCR2 */ -#define CFG_ASRISE 6 /* ASRISE in clocks */ -#define CFG_ASFALL 12 /* ASFALL in clocks */ -#define CFG_REFINT 5600 /* REFINT in clocks */ - -/* MCCR3 */ -#define CFG_BSTOPRE 0x3cf /* Burst To Precharge */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* data latency from read command */ - -/* MCCR4 */ -#define CFG_PRETOACT 1 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CFG_ACTORW 2 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE Wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings: - * - * only bits 20-29 are actually used from these vales to set the - * start/qend address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x00000000 -#define CFG_BANK1_END 0x00000000 -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x00000000 -#define CFG_BANK2_END 0x00000000 -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x00000000 -#define CFG_BANK3_END 0x00000000 -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 - -/* - * Memory bank enable bitmask, specifying which of the banks defined above - * are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory space */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h deleted file mode 100644 index 235bc480c7..0000000000 --- a/include/configs/QS823.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CFG_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG /* debug output code */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_QS823 1 /* ...on a QS823 module */ -#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ - -/* Select the target clock speed */ -#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ -#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ -#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ -#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ -#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ - -#ifdef CONFIG_CLOCK_16MHZ -#define CONFIG_CLOCK_MULT 512 -#endif - -#ifdef CONFIG_CLOCK_33MHZ -#define CONFIG_CLOCK_MULT 1024 -#endif - -#ifdef CONFIG_CLOCK_50MHZ -#define CONFIG_CLOCK_MULT 1525 -#endif - -#ifdef CONFIG_CLOCK_66MHZ -#define CONFIG_CLOCK_MULT 2048 -#endif - -#ifdef CONFIG_CLOCK_80MHZ -#define CONFIG_CLOCK_MULT 2441 -#endif - -/* choose flash size, 4Mb or 8Mb */ -#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ -#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ - -#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -/* Define default IP addresses */ -#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ -#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ - -/* message to say directly after booting */ -#define CONFIG_PREBOOT "echo '';" \ - "echo 'type:';" \ - "echo 'run boot_nfs to boot to NFS';" \ - "echo 'run boot_flash to boot to flash';" \ - "echo '';" \ - "echo 'run flash_rootfs to install a new rootfs';" \ - "echo 'run flash_env to clear the env sector';" \ - "echo 'run flash_rw to clear the rw fs';" \ - "echo 'run flash_uboot to install a new u-boot';" \ - "echo 'run flash_kernel to install a new kernel';" - -/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND "run boot_nfs" - -#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ - -/* Our flash filesystem looks like this - * - * 4Mb board: - * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - * 8Mb board: - * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - */ - -/* environment for 4Mb board */ -#ifdef CONFIG_FLASH_4MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_4MB */ - -/* environment for 8Mb board */ -#ifdef CONFIG_FLASH_8MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_8MB */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* Status LED disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_DATE | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_RUN) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/*----------------------------------------------------------------------- - * Environment variable storage is in FLASH, one sector before U-boot - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ -#define CFG_ENV_SIZE 0x2000 /* 8kb */ -#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ - -#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ -#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * TODO flash parameters - * FLASH organization for Intel Strataflash - */ -#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ - -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ - -/* MF (Multiplication Factor of SPLL) */ -/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ -#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) -#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) -#define CFG_BRGCLK_PRESCALE 1 -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#if defined(CONFIG_CLOCK_80MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#define SCCR_MASK CFG_SCCR - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CFG_DER 0x73E67C0F -#define CFG_DER 0x0082400F - - #------------------------------------------------------------------------- - # Program the Debug Enable Register (DER). This register provides the user - # with the reason for entering into the debug mode. We want all conditions - # to end up as an exception. We don't want to enter into debug mode for - # any condition. See the back of of the Development Support section of the - # MPC860 User Manual for a description of this register. - #------------------------------------------------------------------------- -*/ -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD dual FLASH devices) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CFG_PRELIM_OR_AM -#define CFG_OR_TIMING_FLASH - -/* - *----------------------------------------------------------------------- - * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) - * flash that resides on the QS823. - *----------------------------------------------------------------------- - */ - -/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ -/* represents a minumum 32K block size. */ -#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) -#define CFG_BR0_PRELIM (vBR0_BA | BR_V) - -/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ -/* which defines a 8 Mbyte memory block. */ -#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) - -#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* 0101 = Add a 5 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) -/* 0011 = Add a 3 clock cycle wait state */ -/* 29.8ns clock * (3 + 2) = 149ns cycle time */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -/* 0010 = Add a 2 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) -#endif - -/* - * BR1 and OR1 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - */ - -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which - * represents a 128 Mbyte block the DRAM in - * this address base. - */ -#define vOR1_AM ((0xF800 << 16) + (0 << 15)) -#define vBR1_BA ((0x0000 << 16) + (0 << 15)) -#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) -#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) - -/* Machine A Mode Register */ - -/* PTA Periodic Timer A */ - -#if defined(CONFIG_CLOCK_80MHZ) -#define vMAMR_PTA (19 << 24) -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define vMAMR_PTA (16 << 24) -#endif - -#if defined(CONFIG_CLOCK_50MHZ) -#define vMAMR_PTA (195 << 24) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) -#define vMAMR_PTA (131 << 24) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -#define vMAMR_PTA (65 << 24) -#endif - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* For boards with 32M of SDRAM */ -#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* Memory Periodic Timer Prescaler Register */ - -#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* Divide by 32 */ -#define CFG_MPTPR 0x02 -#endif - -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -/* Divide by 16 */ -#define CFG_MPTPR 0x04 -#endif - -/* - * BR2 and OR2 (Unused) - * Base address = 0xF020_0000 - 0xF020_0FFF - * - */ -#define CFG_OR2_PRELIM 0xFFF00000 -#define CFG_BR2_PRELIM 0xF0200000 - -/* - * BR3 and OR3 (External Bus CS3) - * Base address = 0xF030_0000 - 0xF030_0FFF - * - */ -#define CFG_OR3_PRELIM 0xFFF00000 -#define CFG_BR3_PRELIM 0xF0300000 - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF040_0000 - 0xF040_0FFF - * - */ -#define CFG_OR4_PRELIM 0xFFF00000 -#define CFG_BR4_PRELIM 0xF0400000 - - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF050_0000 - 0xF050_0FFF - * - */ -#define CFG_OR5_PRELIM 0xFFF00000 -#define CFG_BR5_PRELIM 0xF0500000 - -/* - * BR6 and OR6 (Unused) - * Base address = 0xF060_0000 - 0xF060_0FFF - * - */ -#define CFG_OR6_PRELIM 0xFFF00000 -#define CFG_BR6_PRELIM 0xF0600000 - -/* - * BR7 and OR7 (Unused) - * Base address = 0xF070_0000 - 0xF070_0FFF - * - */ -#define CFG_OR7_PRELIM 0xFFF00000 -#define CFG_BR7_PRELIM 0xF0700000 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h deleted file mode 100644 index dbc57e8b27..0000000000 --- a/include/configs/Rattler.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * U-Boot configuration for Analogue&Micro Rattler boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" -#else -#define CONFIG_MPC8260 -#define CPU_ID_STR "MPC8250" -#endif /* CONFIG_MPC8248 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_RATTLER /* Analogue&Micro Rattler board */ - -#undef DEBUG - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) - -/* - Rx clock is CLK11 - * - Tx clock is CLK10 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - Rx clock is CLK15 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ - else iop->pdat &= ~0x00800000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00100000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=rattler-0" -#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" -*/ -#endif /* CFG_CMD_JFFS2 */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CFG_ENV_IS_IN_FLASH - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#endif /* CFG_ENV_IS_IN_FLASH */ - -#define CFG_DEFAULT_IMMR 0xFF010000 - -#define CFG_IMMR 0xF0000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 32 -#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) -#define CFG_SDRAM_OR 0xFE002EC0 - -#define CFG_BCSR 0xFC000000 - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x0E04C000 -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x00000000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_PSDMR 0x8249A452 -#define CFG_PSRT 0x1F -#define CFG_MPTPR 0x2000 - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001) -#define CFG_OR0_PRELIM 0xFF001ED6 -#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) -#define CFG_OR7_PRELIM 0xFFFF87F6 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h deleted file mode 100644 index 3974a0dd21..0000000000 --- a/include/configs/SBC8540.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. - * Added support for Wind River SBC8540 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG -#endif -#define TSEC_DEBUG - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ - #define CFG_OR5_PRELIM 0xff000ff7 - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */ - -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* SBC8540 uses internal COMM controller */ -#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500) -#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define CONFIG_MII 1 /* MII PHY management */ -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH YourRootPath -#define CONFIG_BOOTFILE YourImageName - -#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h deleted file mode 100644 index cc66640b4d..0000000000 --- a/include/configs/SBC8560.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG -#endif -#define TSEC_DEBUG - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ - #define CFG_OR5_PRELIM 0xff000ff7 - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 /* MII PHY management */ -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH YourRootPath -#define CONFIG_BOOTFILE YourImageName - -#endif /* __CONFIG_H */ diff --git a/include/configs/SM850.h b/include/configs/SM850.h deleted file mode 100644 index 84b1bf1593..0000000000 --- a/include/configs/SM850.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ - -#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */ -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED not enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* TQM8xxL_80MHz */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif /* TQM8xxL_80MHz */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h deleted file mode 100644 index ad88cb0318..0000000000 --- a/include/configs/SPD823TS.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_COMMANDS \ -((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/*----------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:D0:93:00:01:CB -#define CONFIG_IPADDR 10.0.0.98 -#define CONFIG_SERVERIP 10.0.0.1 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* 0x00000040 */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00b0c0c0 */ -#define CFG_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CFG_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * SDSR - SDMA Status Register - *----------------------------------------------------------------------- - */ -#define CFG_SDSR ((u_char)0x83) - -/*----------------------------------------------------------------------- - * SDMR - SDMA Mask Register - *----------------------------------------------------------------------- - */ -#define CFG_SDMR ((u_char)0x00) - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xFE100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET 0x0C00 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -/* 16 bit, bank valid */ -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) - * - */ -#define SRAM_BASE 0xFE200000 /* SRAM bank */ -#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ - -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define PER8_BASE 0xFE000000 /* PER8 bank */ -#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ - -#define SHARC_BASE 0xFE400000 /* SHARC bank */ -#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ - -/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ -#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) -#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ -#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ -#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) -#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ -#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) -#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/SX1.h b/include/configs/SX1.h deleted file mode 100644 index 6ed98b8fb1..0000000000 --- a/include/configs/SX1.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ - -/* - * USB device configuration - */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -#define CONFIG_USBD_VENDORID 0x1234 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Siemens" -#define CONFIG_USBD_PRODUCT_NAME "SX1" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ - CFG_CMD_I2C ) & \ - ~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> -#include <configs/omap1510.h> - -#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" -#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SX1# " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE (16 << 10) /* 16 MB */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_SIZE_REDUND 0x20000 -#define CFG_ENV_OFFSET_REDUND 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h deleted file mode 100644 index d110014067..0000000000 --- a/include/configs/SXNI855T.h +++ /dev/null @@ -1,455 +0,0 @@ -/* - * U-Boot configuration for SIXNET SXNI855T CPU board. - * This board is based (loosely) on the Motorola FADS board, so this - * file is based (loosely) on config_FADS860T.h, see it for additional - * credits. - * - * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ - -/* The 855T is just a stripped 860T and needs code for 860, so for now - * at least define 860, 860T and 855T - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC855T 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_SCC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_HAS_ETH1 - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ -# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifdef DEV /* development (debug) settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF -#else /* production settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_ON -#endif - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram ip=off" - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ - -#define CONFIG_SOFT_I2C /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ -# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 - -#define CFG_DISCOVER_PHY - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE - -/* -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x00780000 -#define CONFIG_JFFS2_PART_OFFSET 0x00080000 -*/ - -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand" -#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)" -*/ - -/* NAND flash support */ -#define CFG_NAND_LEGACY -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* DFBUSY is available on Port C, bit 12; 0 if busy */ -#define NAND_WAIT_READY(nand) \ - while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008)); -#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND(d, adr) \ - do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0) -#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) -#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */ -#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */ -#define CE_LO 0x04 /* 1 selects chip (CE low) */ -#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0) -#define NAND_DISABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO) -#define NAND_ENABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_CLRALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | CLE_LO) -#define NAND_CTL_CLRCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO) - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save a little memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SRAM_BASE 0xF4000000 -#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ - -#define CFG_FLASH_BASE 0xF8000000 -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ -#define CFG_DFLASH_SIZE 0x00010000 - -#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ -#define CFG_FPGA_PROG 0xFF130000 /* Programming address */ -#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */ - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. - * AMD 29LV641 has 128 64K sectors in 8MB - */ -#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the - * entire address space, we have to set the memory controller - * differently. Normally, you write the option register - * first, and then enable the chip select by writing the - * base register. For CS0, you must write the base register - * first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - ********************************************************** - * BR0 and OR0 (FLASH) - */ - -#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH) - -#define CONFIG_FLASH_16BIT -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) -#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ - -/********************************************************** - * BR1 and OR1 (FPGA) - * These preliminary values are also the final values. - */ -#define CFG_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) -#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA) - -/********************************************************** - * BR4 and OR4 (data flash) - * These preliminary values are also the final values. - */ -#define CFG_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) -#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH) - -/********************************************************** - * BR5/6 and OR5/6 (Dual UART) - */ -#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ -#define CFG_DUARTA_BASE 0xff010000 -#define CFG_DUARTB_BASE 0xff018000 - -#define DUART_MBMR 0 -#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI) -#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) -#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) -#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) - -/********************************************************** - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ - -#define CFG_ENV_IS_IN_FLASH -#ifdef CFG_ENV_IS_IN_FLASH - /* environment is in FLASH */ - #define CFG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ - #define CFG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ - #define CFG_ENV_SECT_SIZE 0x00010000 - #define CFG_ENV_SIZE 0x00002000 -#else - /* environment is in EEPROM */ - #define CFG_ENV_IS_IN_EEPROM 1 - #define CFG_ENV_OFFSET 0 /* at beginning of EEPROM */ - #define CFG_ENV_SIZE 1024 /* Use only a part of it*/ -#endif - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" -#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h deleted file mode 100644 index b9edf078f6..0000000000 --- a/include/configs/TB5200.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#define CONFIG_TB5200 1 /* ... on a TB5200 base board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */ -#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */ -#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CFG_CONSOLE_IS_IN_ENV - -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* IDE */ -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined(CONFIG_TQM5200_B) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" \ - "" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" -#endif /* CONFIG_TQM5200_B */ - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* List of I2C addresses to be verified by POST */ -#undef I2C_ADDR_LIST -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_RTC_ADDR, \ - CFG_I2C_SLAVE } - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#if defined(CONFIG_TQM5200_B) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000) -#else -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CONFIG_TQM5200_B */ -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ - -/* Dynamic MTD partition support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#if defined(CONFIG_TQM5200_B) -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ - "1280k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" -#else -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" -#endif /* CONFIG_TQM5200_B */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#if defined(CONFIG_TQM5200_B) -#define CFG_ENV_SECT_SIZE 0x40000 -#else -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CONFIG_TQM5200_B */ - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#if defined(CONFIG_TQM5200_B) -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#endif /* CONFIG_TQM5200_B */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC3: Bits 20:23 (mask: 0x00000300): - * 0001 -> USB2 - * 0000 -> GPIO - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#define CFG_GPS_PORT_CONFIG 0x81500114 - -/* - * RTC configuration - */ -#define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base - year */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CFG_CS2_START 0xE5000000 -#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ -#define CFG_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h deleted file mode 100644 index e44dde5424..0000000000 --- a/include/configs/TOP5200.h +++ /dev/null @@ -1,405 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de - * - * TOP5200 differences from IceCube: - * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks - * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins - * 1 SDRAM/DDRAM Bank up to 256 MB - * local VPD I2C Bus is software driven and uses - * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL - * FLASH is re-located at 0xff000000 - * Internal regs are at 0xf0000000 - * Reset jumps to 0x00000100 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -# define CONFIG_PCI_SCAN_SHOW 1 - -# define CONFIG_PCI_MEM_BUS 0x40000000 -# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -# define CONFIG_PCI_MEM_SIZE 0x10000000 - -# define CONFIG_PCI_IO_BUS 0x50000000 -# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -# define CONFIG_PCI_IO_SIZE 0x01000000 - -# define ADD_PCI_CMD CFG_CMD_PCI - -#else /* no Evaluation board */ - -# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* USB */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define CONFIG_USB_OHCI -# define CONFIG_USB_CLOCK 0x0001bbbb -# if defined (CONFIG_EVAL5200) -# define CONFIG_USB_CONFIG 0x00005100 -# else -# define CONFIG_USB_CONFIG 0x00001000 -# endif -# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -# define CONFIG_DOS_PARTITION -# define CONFIG_USB_STORAGE - -#else - -# define ADD_USB_CMD 0 - -#endif - -/* IDE */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT -# define CONFIG_DOS_PARTITION - -#else - -# define ADD_IDE_CMD 0 - -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - ADD_IDE_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#else -# error "TEXT_BASE must be 0xff000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * I2C configuration - */ -/* - * EEPROM configuration - */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_SIZE 0x2000 - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */ - -#if defined (CONFIG_SOFT_I2C) -# define SDA0 0x40 -# define SCL0 0x80 -# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00)) -# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08)) -# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c)) -# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20)) -# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04)) -# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} -# define I2C_READ ((DVI0&SDA0)?1:0) -# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} -# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} -# define I2C_DELAY {udelay(5);} -# define I2C_ACTIVE {DDR0|=SDA0;} -# define I2C_TRISTATE {DDR0&=~SDA0;} -# define CFG_I2C_SPEED 100000 -# define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_FACT_ADDR 0x57 -#endif - -#if defined (CONFIG_HARD_I2C) -# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -# define CFG_I2C_SPEED 100000 /* 100 kHz */ -# define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x54 -#define CFG_I2C_FACT_ADDR 0x54 -#endif - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CFG_FLASH_BASE 0xff000000 -#define CFG_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0) - -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -/* - * DRAM configuration - will be read from VPD later... TODO! - */ -/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ -#define CFG_DRAM_DDR 0 -#define CFG_DRAM_EMODE 0 -#define CFG_DRAM_MODE 0x00CD -#define CFG_DRAM_CONTROL 0x514F0000 -#define CFG_DRAM_CONFIG1 0xD2333A00 -#define CFG_DRAM_CONFIG2 0x8AD70004 -#define CFG_DRAM_TAP_DEL 0x08 -#define CFG_DRAM_RAM_SIZE 0x19 - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x0700 - -/* - * VPD settings - */ -#define CFG_FACT_OFFSET 0x1800 -#define CFG_FACT_SIZE 0x0800 - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CFG_GPS_PORT_CONFIG 0x00058044 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ - #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ - #define RTC(reg) (0xf0010000+reg) - /* setup CS2 for M48T08. Must MAP 64kB */ - #define CFG_CS2_START RTC(0) - #define CFG_CS2_SIZE 0x10000 - /* setup CS2 configuration register: */ - /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ - /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ - #define CFG_CS2_CFG 0x00047800 -#else - #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0x7f000000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005c) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h deleted file mode 100644 index 2344b96811..0000000000 --- a/include/configs/TOP860.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH <www.emk-elektronik.de> - * Reinhard Meyer <r.meyer@emk-elektronik.de> - * - * Configuation settings for the TOP860 board. - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * TOP860 is a simple module: - * 16-bit wide FLASH on CS0 (2MB or more) - * 32-bit wide DRAM on CS2 (either 4MB or 16MB) - * FEC with Am79C874 100-Base-T and Fiber Optic - * Ports available, but we choose SMC1 for Console - * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set - * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock - * - * This config has been copied from MBX.h / MBX860T.h - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/*----------------------------------------------------------------------- - * CPU and BOARD type - */ -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MPC860T 1 /* even better... an FEC! */ -#define CONFIG_TOP860 1 /* ...on a TOP860 module */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_IDENT_STRING " EMK TOP860" - -/*----------------------------------------------------------------------- - * CLOCK settings - */ -#define CONFIG_SYSCLK 49152000 -#define CFG_XTAL 32768 -#define CONFIG_EBDF 1 -#define CONFIG_COM 3 -#define CONFIG_RTC_MPC8xx - -/*----------------------------------------------------------------------- - * Physical memory map as defined by EMK - */ -#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ -#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */ -#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */ -#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */ -#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */ - -/*----------------------------------------------------------------------- - * derived values - */ -#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL) -#define CFG_CPUCLOCK CONFIG_SYSCLK -#define CFG_BRGCLOCK CONFIG_SYSCLK -#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_CFI - -/*----------------------------------------------------------------------- - * Command interpreter - */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -/* - * Allow partial commands to be matched to uniqueness. - */ -#define CFG_MATCH_PARTIAL_CMD - -/* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) - -#define CONFIG_AUTOSCRIPT 1 -#define CFG_LOADS_BAUD_CHANGE 1 -#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ - -#ifdef CFG_HUSH_PARSER - #define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test Command - */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Environment handler - * only the first 6k in EEPROM are available for user. Of that we use 256b - */ -#define CONFIG_SOFT_I2C -#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x0700 -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_FACT_OFFSET 0x1800 -#define CFG_FACT_SIZE 0x0800 -#define CFG_I2C_FACT_ADDR 0x57 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_SIZE 0x2000 -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 0xFE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#if defined (CONFIG_SOFT_I2C) -#define SDA 0x00010 -#define SCL 0x00020 -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_ODR immr->im_cpm.cp_pbodr -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_ODR &= ~(SDA|SCL); \ - __I2C_DAT |= (SDA|SCL); \ - __I2C_DIR|=(SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } -#endif - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * defines we need to get FEC running - */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#define CFG_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#define CONFIG_PHY_ADDR 31 - -/*----------------------------------------------------------------------- - * adresses - */ -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x80000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Debug Enable Register - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 /* used in start.S */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set up PLPRCR (PLL, Low-Power, and Reset Control Register) - * 12 MF calculated Multiplication factor - * 4 0 0000 - * 1 SPLSS 0 System PLL lock status sticky - * 1 TEXPS 1 Timer expired status - * 1 0 0 - * 1 TMIST 0 Timers interrupt status - * 1 0 0 - * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) - * 2 LPM 00 Low-power modes - * 1 CSR 0 Checkstop reset enable - * 1 LOLRE 0 Loss-of-lock reset enable - * 1 FIOPD 0 Force I/O pull down - * 5 0 00000 - */ -#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20)) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * set up SYPCR: - * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing - * 1 BME 1 Bus monitor enable - * 3 0 000 - * 1 SWF 1 Software watchdog freeze - * 1 SWE 0/1 Software watchdog enable - * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) - * 1 SWP 0/1 Software watchdog prescale (1=/2048) - */ -#if defined (CONFIG_WATCHDOG) - #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else - #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * set up SIUMCR - * 1 EARB 0 External arbitration - * 3 EARP 000 External arbitration request priority - * 4 0 0000 - * 1 DSHW 0 Data show cycles - * 2 DBGC 00 Debug pin configuration - * 2 DBPC 00 Debug port pins configuration - * 1 0 0 - * 1 FRC 0 FRZ pin configuration - * 1 DLK 0 Debug register lock - * 1 OPAR 0 Odd parity - * 1 PNCS 0 Parity enable for non memory controller regions - * 1 DPC 0 Data parity pins configuration - * 1 MPRE 0 Multiprocessor reservation enable - * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) - * 1 AEME 0 Async external master enable - * 1 SEME 0 Sync external master enable - * 1 BSC 0 Byte strobe configuration - * 1 GB5E 0 GPL_B5 enable - * 1 B2DD 0 Bank 2 double drive - * 1 B3DD 0 Bank 3 double drive - * 4 0 0000 - */ -#define CFG_SIUMCR (SIUMCR_MLRC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * set up SCCR (System Clock and Reset Control Register) - * 1 0 0 - * 2 COM 11 Clock output module (00=full, 01=half, 11=off) - * 3 0 000 - * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) - * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) - * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) - * 1 CRQEN 0 CPM request enable - * 1 PRQEN 0 Power management request enable - * 2 0 00 - * 2 EBDF xx External bus division factor - * 2 0 00 - * 2 DFSYNC 00 Division factor for SYNCLK - * 2 DFBRG 00 Division factor for BRGCLK - * 3 DFNL 000 Division factor low frequency - * 3 DFNH 000 Division factor high frequency - * 5 0 00000 - */ -#define SCCR_MASK 0 -#ifdef CONFIG_EBDF - #define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) -#else - #define CFG_SCCR (SCCR_COM11 | SCCR_TBS) -#endif - -/*----------------------------------------------------------------------- - * Chip Select 0 - FLASH - *----------------------------------------------------------------------- - * Preliminary Values - */ -/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) -#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V ) - -/*----------------------------------------------------------------------- - * misc - *----------------------------------------------------------------------- - * - */ -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * BOOTP options - */ -#undef CONFIG_BOOTP_MASK -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) - - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can autoscript the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 -#define CONFIG_IPADDR 10.0.4.111 - -/*----------------------------------------------------------------------- - * Defaults for Autoscript - */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_TFTP_LOADADDR 0x00100000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h deleted file mode 100644 index 247f705fb6..0000000000 --- a/include/configs/TQM823L.h +++ /dev/null @@ -1,452 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_LCD) -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 1461b5f203..0000000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index a66a7da0a5..0000000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,729 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load;run cphwib;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define ADD_CMD_I2C CFG_CMD_I2C | \ - CFG_CMD_DATE |\ - CFG_CMD_DTT |\ - CFG_CMD_EEPROM -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_HARD_I2C -#undef CONFIG_SOFT_I2C -#define ADD_CMD_I2C 0 -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CFG_FCC_ETHERNET - -#if defined(CFG_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ - -#if STK82xx_150 -#define CFG_MDIO_PIN 0x00008000 /* PC16 */ -#define CFG_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CFG_MDIO_PIN 0x00000002 /* PC30 */ -#define CFG_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ - else iop->pdat &= ~CFG_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ - else iop->pdat &= ~CFG_MDC_PIN - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - ADD_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x300000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CFG_CAN_BASE 0x51000000 -#define CFG_CAN_SIZE 1 -#define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_UPDATE_FLASH_SIZE - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) -#define CFG_ENV_SIZE 0x20000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#define CFG_NAND_CS_DIST 0x80 -#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CFG_NAND_SIZE 1 -#define CFG_NAND0_BASE 0x50000000 -#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) -#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) -#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) - -#define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ - CFG_NAND1_BASE, \ - CFG_NAND2_BASE, \ - CFG_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CFG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CFG_SIUMCR_LOW (SIUMCR_DPPC00) -#define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CFG_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CFG_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CFG_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CFG_PSRT 0x20 /* Low Value */ -/* #define CFG_PSRT 0x10 Fast Value */ -#define CFG_LSRT 0x20 /* Local Bus */ -#ifndef CFG_RAMBOOT -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM CFG_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CFG_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h deleted file mode 100644 index 728083b304..0000000000 --- a/include/configs/TQM834x.h +++ /dev/null @@ -1,587 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM8349 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define DEBUG -#undef DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_TQM834X 1 /* TQM834X board specific */ - -/* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMR 0xff400000 - -/* System clock. Primary input clock when in PCI host mode */ -#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ - -/* - * Local Bus LCRR - * LCRR: DLL bypass, Clock divider is 8 - * - * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz - * - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) - -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - -/* board pre init: do not call, nothing to do */ -#undef CONFIG_BOARD_EARLY_INIT_F - -/* detect the number of flash banks */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * DDR Setup - */ -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ - -/* buffered writes in the AMD chip set is not supported yet */ -#undef CFG_FLASH_USE_BUFFER_WRITE - -/* - * FLASH bank number detection - */ - -/* - * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash - * banks has to be determined at runtime and stored in a gloabl variable - * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only - * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and - * should be made sufficiently large to accomodate the number of banks that - * might actually be detected. Since most (all?) Flash related functions use - * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is - * defined as tqm834x_num_flash_banks. - */ -#define CFG_MAX_FLASH_BANKS_DETECT 2 -#ifndef __ASSEMBLY__ -extern int tqm834x_num_flash_banks; -#endif -#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) - -#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ - -/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ - BR_MS_GPCM | BR_PS_32 | BR_V) - -/* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ - OR_GPCM_SCY_5 | OR_GPCM_TRLX) - -#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) - -#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ - -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ - -/* disable remaining mappings */ -#define CFG_BR1_PRELIM 0x00000000 -#define CFG_OR1_PRELIM 0x00000000 -#define CFG_LBLAWBAR1_PRELIM 0x00000000 -#define CFG_LBLAWAR1_PRELIM 0x00000000 - -#define CFG_BR2_PRELIM 0x00000000 -#define CFG_OR2_PRELIM 0x00000000 -#define CFG_LBLAWBAR2_PRELIM 0x00000000 -#define CFG_LBLAWAR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0x00000000 -#define CFG_OR3_PRELIM 0x00000000 -#define CFG_LBLAWBAR3_PRELIM 0x00000000 -#define CFG_LBLAWAR3_PRELIM 0x00000000 - -#define CFG_BR4_PRELIM 0x00000000 -#define CFG_OR4_PRELIM 0x00000000 -#define CFG_LBLAWBAR4_PRELIM 0x00000000 -#define CFG_LBLAWAR4_PRELIM 0x00000000 - -#define CFG_BR5_PRELIM 0x00000000 -#define CFG_OR5_PRELIM 0x00000000 -#define CFG_LBLAWBAR5_PRELIM 0x00000000 -#define CFG_LBLAWAR5_PRELIM 0x00000000 - -#define CFG_BR6_PRELIM 0x00000000 -#define CFG_OR6_PRELIM 0x00000000 -#define CFG_LBLAWBAR6_PRELIM 0x00000000 -#define CFG_LBLAWAR6_PRELIM 0x00000000 - -#define CFG_BR7_PRELIM 0x00000000 -#define CFG_OR7_PRELIM 0x00000000 -#define CFG_LBLAWBAR7_PRELIM 0x00000000 -#define CFG_LBLAWAR7_PRELIM 0x00000000 - -/* - * Monitor config - */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) - -/* - * I2C - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ -#define CFG_I2C_SLAVE 0x7F /* slave address */ -#define CFG_I2C_OFFSET 0x3000 - -/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -/* - * TSEC - */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_MII - -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif - -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_PCI - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* PCI1 host bridge */ -#define CFG_PCI1_MEM_BASE 0xc0000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - -#undef CONFIG_EEPRO100 -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE - #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ -#endif - -#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* Common commands */ -#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ - | CFG_CMD_PING | CFG_CMD_EEPROM \ - | CFG_CMD_MII | CFG_CMD_JFFS2 - -#if defined(CFG_RAMBOOT) - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#endif - -#else /* CFG_RAMBOOT */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) -#endif - -#endif /* CFG_RAMBOOT */ - -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -/* System IO Config */ -#define CFG_SICRH SICRH_TSOBI1 -#define CFG_SICRL SICRL_LDP_A - -/* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 HID2_HBE - -/* DDR 0 - 512M */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 512M (no backing mem) */ -#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI */ -#ifdef CONFIG_PCI -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT3L (0) -#define CFG_IBAT3U (0) -#define CFG_IBAT4L (0) -#define CFG_IBAT4U (0) -#define CFG_IBAT5L (0) -#define CFG_IBAT5U (0) -#endif - -/* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) - -/* FLASH */ -#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U -#define CFG_DBAT4L CFG_IBAT4L -#define CFG_DBAT4U CFG_IBAT4U -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR D2:DA:5E:44:BC:29 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 -#endif - -#define CONFIG_IPADDR 192.168.205.1 - -#define CONFIG_HOSTNAME tqm8349 -#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx -#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=tqm83xx\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/tqm83xx/uImage\0" \ - "kernel_addr=80060000\0" \ - "ramdisk_addr=80160000\0" \ - "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ - "update=protect off 80000000 8003ffff; " \ - "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ - "upd=run load;run update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * JFFS2 partitions - */ -/* mtdparts command line support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM834x-0" - -/* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ - "1m(kernel),2m(initrd),"\ - "-(user);"\ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h deleted file mode 100644 index 90ecbadb2e..0000000000 --- a/include/configs/TQM850L.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index b3f8f8d835..0000000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h deleted file mode 100644 index 49aaeea44d..0000000000 --- a/include/configs/TQM855L.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index b19285bd43..0000000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h deleted file mode 100644 index f45f3a2f5a..0000000000 --- a/include/configs/TQM85xx.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Wolfgang Denk <wd@denx.de> - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM85xx (8560/40/55/41) board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Only MPC8540 doesn't have CPM module - */ -#ifndef CONFIG_MPC8540 -#define CONFIG_CPM2 1 /* has CPM2 */ -#endif - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 -#define CFG_MEMTEST_END 0x10000000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ - -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) -/* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ -#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ - -/* - * Flash on the Local Bus - */ -#define CFG_FLASH0 0xFC000000 -#define CFG_FLASH1 0xF8000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } - -#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ - -#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ -#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ -#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ -#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ - -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#if defined(CONFIG_TQM8560) - -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#else /* ! TQM8560 */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* PS/2 Keyboard */ -#if !defined(CONFIG_TQM8560) -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R 1 -#endif /* !CONFIG_TQM8560 */ - -#endif /* CONFIG_TQM8560 */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C EEPROM */ -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -/* Options are TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#if defined(CONFIG_TQM8540) -/* - * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. - * The FEC port is connected on the same signals as the FCC3 port - * of the TQM8560 to the baseboard (STK85xx Starterkit). - * - * On the STK85xx Starterkit the X47/X50 jumper has to be set to - * a - d (X50.2 - 3) to enable the FEC port. - */ -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#endif - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) -/* - * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...2 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_TQM8560) -/* - * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...3 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - * FCC3: a - d (X50.2 - 3) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) -#define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -#define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) -#define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - -#if defined(CONFIG_PCI) -# define ADD_PCI_CMD (CFG_CMD_PCI) -#else -# define ADD_PCI_CMD 0 -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - ADD_PCI_CMD | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DTT | \ - CFG_CMD_MII | \ - CFG_CMD_PING ) -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ - "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h deleted file mode 100644 index 9be5db1e42..0000000000 --- a/include/configs/TQM860L.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_NETCONSOLE - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 37f6c985d3..0000000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index f03690a7b2..0000000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_NET_MULTI -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index 495934045f..0000000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_NET_MULTI -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index 148490b586..0000000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) - */ -#define CFG_MAMR_PTA 39 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h deleted file mode 100644 index d470ade847..0000000000 --- a/include/configs/TQM885D.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CFG_I2C_RTC_ADDR 0x68 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CFG_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) - */ -#define CFG_MAMR_PTA 39 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Network configuration - */ -#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#if (CONFIG_COMMANDS & CFG_CMD_MII) -#define CFG_DISCOVER_PHY -#endif - -#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before - switching to another netwok (if the - tried network is unreachable) */ - -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h deleted file mode 100644 index 9f2b30026f..0000000000 --- a/include/configs/Total5200.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Check valid setting of revision define. - * Total5100 and Total5200 Rev.1 are identical except for the processor. - */ -#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) -#error CONFIG_TOTAL5200_REV must be 1 or 2 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SED13806 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* #define CONFIG_VIDEO_BMP_LOGO */ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN - -#define ADD_VIDEO_CMD CFG_CMD_BMP - -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MGT5100 */ - -#define CONFIG_MII 1 -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - ADD_VIDEO_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#if (TEXT_BASE == 0xFE000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "setenv stdout serial;setenv stderr serial;" \ - "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if CONFIG_TOTAL5200_REV==2 -# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */ -# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START } -#else -# define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -# define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#endif -#define CFG_FLASH_EMPTY_INFO -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_FLASH_BASE 0xFE000000 -# define CFG_FLASH_SIZE 0x02000000 -#elif CONFIG_TOTAL5200_REV==2 -# define CFG_FLASH_BASE 0xFA000000 -# define CFG_FLASH_SIZE 0x06000000 -#endif /* CONFIG_TOTAL5200_REV */ - -#if defined(CFG_LOWBOOT) -# define CFG_ENV_ADDR 0xFE040000 -#else /* CFG_LOWBOOT */ -# define CFG_ENV_ADDR 0xFFF40000 -#endif /* CFG_LOWBOOT */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_MBAR 0xF0000000 /* 64 kB */ -#define CFG_FPGA_BASE 0xF0010000 /* 64 kB */ -#define CFG_CPLD_BASE 0xF0020000 /* 64 kB */ -#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */ - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* dummy, 7-wire FEC does not have phy address */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 - * Reserved 0 - * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 - * CS7: Interrupt GPIO on PSC3_5 0 - * CS8: Interrupt GPIO on PSC3_4 0 - * ATA: reset default, changed in ATA driver 00 - * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 - * IRDA: reset default, changed in IrDA driver 000 - * ETHER: reset default, changed in Ethernet driver 0000 - * PCI_DIS: reset default, changed in PCI driver 0 - * USB_SE: reset default, changed in USB driver 0 - * USB: reset default, changed in USB driver 00 - * PSC3: SPI and UART functionality without CD 1100 - * Reserved 0 - * PSC2: CAN1/2 001 - * Reserved 0 - * PSC1: reset default, changed in AC'97 driver 000 - * - */ -#define CFG_GPS_PORT_CONFIG 0x00000C10 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_BOOTCS_START CFG_FLASH_BASE -# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS0_START CFG_FLASH_BASE -# define CFG_CS0_SIZE 0x02000000 /* 32 MB */ -#else -# define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE) -# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE) -# define CFG_CS4_SIZE 0x02000000 /* 32 MB */ -# define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS5_START CFG_FLASH_BASE -# define CFG_CS5_SIZE 0x02000000 /* 32 MB */ -# define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -#endif - -#define CFG_CS1_START CFG_FPGA_BASE -#define CFG_CS1_SIZE 0x00010000 /* 64 kB */ -#define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ - -#define CFG_CS2_START CFG_LCD_BASE -#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */ -#define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_CS3_START CFG_CPLD_BASE -# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ -# define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ -#else -# define CFG_CS3_START CFG_CPLD_BASE -# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ -# define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ -#endif - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h deleted file mode 100644 index 37ef1058f9..0000000000 --- a/include/configs/Yukon8220.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2004 - * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC8220 1 -#define CONFIG_YUKON8220 1 /* ... on Yukon board */ - -/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ - -/* Define this for PSC console -#define CONFIG_PSC_CONSOLE 1 -*/ - -#define CONFIG_EXTUART_CONSOLE 1 - -#ifdef CONFIG_EXTUART_CONSOLE -# define CONFIG_CONS_INDEX 1 -# define CFG_NS16550_SERIAL -# define CFG_NS16550 -# define CFG_NS16550_REG_SIZE 1 -# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) -# define CFG_NS16550_CLK 18432000 -#endif - -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -#define CONFIG_NET_MULTI -#define CONFIG_MII - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" -#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 -#define CONFIG_IPADDR 192.162.1.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.162.1.1 -#define CONFIG_GATEWAYIP 192.162.1.1 -#define CONFIG_HOSTNAME yukon -#define CONFIG_OVERWRITE_ETHADDR_ONCE - - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 -/* -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 256 -*/ - -/* If CFG_AMD_BOOT is defined, the the system will boot from AMD. - else undefined it will boot from Intel Strata flash */ -#define CFG_AMD_BOOT 1 - -/* - * Flexbus Chipselect configuration - */ -#if defined (CFG_AMD_BOOT) -#define CFG_CS0_BASE 0xfff0 -#define CFG_CS0_MASK 0x00080000 /* 512 KB */ -#define CFG_CS0_CTRL 0x003f0d40 - -#define CFG_CS1_BASE 0xfe00 -#define CFG_CS1_MASK 0x01000000 /* 16 MB */ -#define CFG_CS1_CTRL 0x003f1540 -#else -#define CFG_CS0_BASE 0xff00 -#define CFG_CS0_MASK 0x01000000 /* 16 MB */ -#define CFG_CS0_CTRL 0x003f1540 - -#define CFG_CS1_BASE 0xfe08 -#define CFG_CS1_MASK 0x00080000 /* 512 KB */ -#define CFG_CS1_CTRL 0x003f0d40 -#endif - -#define CFG_CS2_BASE 0xf100 -#define CFG_CS2_MASK 0x00040000 -#define CFG_CS2_CTRL 0x003f1140 - -#define CFG_CS3_BASE 0xf200 -#define CFG_CS3_MASK 0x00040000 -#define CFG_CS3_CTRL 0x003f1100 - - -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) - -#if defined (CFG_AMD_BOOT) -#define CFG_AMD_BASE CFG_FLASH0_BASE -#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 -#define CFG_FLASH_BASE CFG_AMD_BASE -#else -#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 -#define CFG_AMD_BASE CFG_FLASH1_BASE -#define CFG_FLASH_BASE CFG_INTEL_BASE -#endif - -#define CFG_CPLD_BASE (CFG_CS2_BASE << 16) -#define CFG_FPGA_BASE (CFG_CS3_BASE << 16) - - -#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ -#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ - -#define CFG_FLASH_CHECKSUM -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#if defined (CFG_AMD_BOOT) -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE -#else -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE -#endif - -#define CONFIG_ENV_OVERWRITE 1 - -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif - -#ifndef CFG_JFFS2_FIRST_SECTOR -#define CFG_JFFS2_FIRST_SECTOR 0 -#endif -#ifndef CFG_JFFS2_FIRST_BANK -#define CFG_JFFS2_FIRST_BANK 0 -#endif -#ifndef CFG_JFFS2_NUM_BANKS -#define CFG_JFFS2_NUM_BANKS 1 -#endif -#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* SDRAM configuration */ -#define CFG_SDRAM_TOTAL_BANKS 2 -#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x40 -#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ - -/* SDRAM drive strength register */ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ - (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC8220_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x18 - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h deleted file mode 100644 index a5085cfb79..0000000000 --- a/include/configs/ZPC1900.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (C) 2003-2005 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * U-Boot configuration for Zephyr Engineering ZPC.1900 board. - * This port was developed and tested on Revision C board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ -#define CPU_ID_STR "MPC8265" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) -/* - * - Rx clock is CLK13 - * - Tx clock is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Full duplex - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 64 - -#define CFG_IMMR 0xF0000000 -#define CFG_LSDRAM_BASE 0xFC000000 -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_BCSR 0xFEA00000 -#define CFG_EEPROM 0xFEB00000 -#define CFG_FLSIMM_BASE 0xFF000000 - -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE } - -#define BCSR_PCI_MODE 0x01 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ - HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ - HRCW_MODCK_H0111 \ - ) /* 0x16848207 */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM) -#define CFG_ENV_IS_IN_NVRAM 1 -#endif - -#ifdef CFG_ENV_IS_IN_FLASH -# define CFG_ENV_SECT_SIZE 0x10000 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#else -# define CFG_ENV_ADDR (CFG_EEPROM + 0x400) -# define CFG_ENV_SIZE 0x1000 -# define CFG_NVRAM_ACCESS_ROUTINE -#endif - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT (HID0_ICFI) -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x42200000 -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90000000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_PSDMR /* 0x834DA43B */0x014DA43A -#define CFG_PSRT 0x0F/* 0x0C */ -#define CFG_LSDMR 0x0085A562 -#define CFG_LSRT 0x0F -#define CFG_MPTPR 0x4000 - -#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 -#define CFG_PSDRAM_OR 0xFC0028C0 -#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 -#define CFG_LSDRAM_OR 0xFF803480 - -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 -#define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 -#define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 -#define CFG_OR6_PRELIM 0xFF000856 -#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 -#define CFG_OR7_PRELIM 0xFFFF83F6 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h deleted file mode 100644 index cbfd07258c..0000000000 --- a/include/configs/ZUMA.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_ETHER_PORT_MII /* use two MII ports */ -#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ - -/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#define CONFIG_ECC /* enable ECC support */ - -#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F -#define CFG_BOARD_ASM_INIT - -#define CFG_BOARD_NAME "Zuma APv2" - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC - -#define CONFIG_MPSC_PORT 0 - -#define CONFIG_NET_MULTI /* attempt all available adapters */ - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none panic=5 && bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MII /* enable MII commands */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_DATE) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" -#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ - -#define CFG_BUS_HZ 133000000 /* 133 MHz */ - -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfff00000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CFG_GT_REGS 0xf8000000 /* later mapped GT_REGS */ -#define CFG_DEV_BASE 0xf0000000 -#define CFG_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ -#define CFG_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ -#define CFG_DEV2_SIZE _8M /* unused */ -#define CFG_DEV3_SIZE _8M /* unused */ - -#define CFG_DEV0_PAR 0xc498243c - /* c 4 9 8 2 4 3 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ - /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ - -#define CFG_DEV1_PAR 0xc01b6ac5 - /* c 0 1 b 6 a c 5 */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ - /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - - -#define CFG_8BIT_BOOT_PAR 0xc00b5e7c - -#define CFG_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ -#define CFG_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ -#define CFG_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ -#define CFG_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ - /* GPP[27:24] (27 is int4, rest are GPP) */ - -#define CFG_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ -#define CFG_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ - -#define CFG_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 1 - pci use buffer 0,0 (pci1->0 pci0->0) - cpu use buffer 1 (R*18) - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 111001 00 111 0 0 00 1 */ - - /* refresh count=0x200 - phy interleave disable (by default, - set later by dram config..) - virt interleave enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ -#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -#define CFG_ENV_ADDR (0xfff80000 - CFG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*------------------------------------------------------------------------ - * Real time clock - */ -#define CONFIG_RTC_DS1302 - - -/*------------------------------------------------------------------------ - * Galileo I2C driver - */ -#define CONFIG_GT_I2C - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h deleted file mode 100644 index c4108912a6..0000000000 --- a/include/configs/adsvix.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Configuation settings for the LUBBOCK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ -#define CONFIG_ADSVIX 1 /* on a Adsvix Board */ -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define RTC - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_DOS_PARTITION 1 - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_SERVERIP 192.168.1.99 -#define CONFIG_BOOTCOMMAND "run boot_flash" -#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ - " rw root=/dev/ram initrd=0xa0800000,5m" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "program_boot_cf=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_cf=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_cf=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_cf=" \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0030000 uzImage && " \ - "fatload ide 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "program_boot_mmc=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_mmc=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_mmc=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa0030000 uzImage && " \ - "fatload mmc 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "boot_flash=" \ - "cp.b 0x1c0000 0xa0800000 0x500000; " \ - "bootm 0x40000\0" \ - -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -/* #define CONFIG_INITRD_TAG 1 */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - -#define CFG_GPSR0_VAL 0x00018004 -#define CFG_GPSR1_VAL 0x004F0080 -#define CFG_GPSR2_VAL 0x13EFC000 -#define CFG_GPSR3_VAL 0x0006E032 -#define CFG_GPCR0_VAL 0x084AFE1A -#define CFG_GPCR1_VAL 0x003003F2 -#define CFG_GPCR2_VAL 0x0C014000 -#define CFG_GPCR3_VAL 0x00000C00 -#define CFG_GPDR0_VAL 0xCBC3BFFC -#define CFG_GPDR1_VAL 0x00FFABF3 -#define CFG_GPDR2_VAL 0x1EEFFC00 -#define CFG_GPDR3_VAL 0x0187EC32 -#define CFG_GAFR0_L_VAL 0x84400000 -#define CFG_GAFR0_U_VAL 0xA51A8010 -#define CFG_GAFR1_L_VAL 0x699A955A -#define CFG_GAFR1_U_VAL 0x0005A0AA -#define CFG_GAFR2_L_VAL 0x40000000 -#define CFG_GAFR2_U_VAL 0x0109A400 -#define CFG_GAFR3_L_VAL 0x54000000 -#define CFG_GAFR3_U_VAL 0x00001409 - -#define CFG_PSSR_VAL 0x20 - -/* - * Clock settings - */ -#define CFG_CKEN 0x00400200 -#define CFG_CCCR 0x02000290 /* 520Mhz */ -/* #define CFG_CCCR 0x02000210 416 Mhz */ - -/* - * Memory settings - */ - -#define CFG_MSC0_VAL 0x23F2B3DB -#define CFG_MSC1_VAL 0x0000CCD1 -#define CFG_MSC2_VAL 0x0000B884 -#define CFG_MDCNFG_VAL 0x08000AC8 -#define CFG_MDREFR_VAL 0x0000001E -#define CFG_MDMRS_VAL 0x00000000 - -#define CFG_FLYCNFG_VAL 0x00010001 -#define CFG_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000002 -#define CFG_MCMEM0_VAL 0x00004204 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00008407 -#define CFG_MCIO1_VAL 0x00000000 - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CFG_PCMCIA_MEM_ADDR 0x28000000 -#define CFG_PCMCIA_MEM_SIZE 0x04000000 - - -#define CFG_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x3f0 - -/* - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 - -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x20000 - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* write flash less slowly */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -/* Flash environment locations */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h deleted file mode 100644 index 8d9f0a1661..0000000000 --- a/include/configs/aev.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ -#define CONFIG_AEVFIFO 1 -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_AEVFIFO -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_AEVFIFO */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - CFG_CMD_PCI | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "console=ttyS0,${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#define CFG_GPS_PORT_CONFIG 0x81500014 - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CFG_CS2_START 0xE5000000 -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ -#define CFG_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h deleted file mode 100644 index 49027da5a4..0000000000 --- a/include/configs/alpr.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_ALPR 1 /* Board is ebony */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - - -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ -#undef CONFIG_SDRAM_ECC /* enable ECC support */ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ - {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) - *----------------------------------------------------------------------*/ -#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth3\0" \ - "hostname=alpr\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ - "mem=193M\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/projects/alpr/nfs_root\0" \ - "bootfile=/alpr/uImage\0" \ - "kernel_addr=fff00000\0" \ - "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "ethprime=ppc_4xx_eth3\0" \ - "ethact=ppc_4xx_eth3\0" \ - "autoload=no\0" \ - "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ - "actkernel=kernel2\0" \ - "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ - "rootfstype=jffs2 init=/sbin/init\0" \ - "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ - ";bootm 200000\0" \ - "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ - "addtty;bootm 200000\0" \ - "kernel1=run ipconfig load_fpga kernel1_mtd\0" \ - "kernel2=run ipconfig load_fpga kernel2_mtd\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run kernel2" - -#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ -#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ -#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ -#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_FPGA | \ - CFG_CMD_NAND | \ - CFG_CMD_REGINFO) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ -#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * FPGA stuff - *-----------------------------------------------------------------------*/ -#define CONFIG_FPGA CFG_ALTERA_CYCLON2 -#define CFG_FPGA_CHECK_CTRLC -#define CFG_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in - Reihe geschaltet -> sollte gehen, - aufpassen mit Datasize ist jetzt - halt doppelt so gross ... Seite 306 - ist das mit den multiple Device in PS - Mode erklaert ...*/ - -/* FPGA program pin configuration */ -#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ -#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ -#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ -#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ -#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ - -#define CFG_GPIO_SEL_DPR 14 /* cpu output */ -#define CFG_GPIO_SEL_AVR 15 /* cpu output */ -#define CFG_GPIO_PROG_EN 23 /* cpu output */ - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup - *-----------------------------------------------------------------------*/ -#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6) -#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9) -#define CFG_GPIO_EREADY (0x80000000 >> 26) -#define CFG_GPIO_REV0 (0x80000000 >> 14) -#define CFG_GPIO_REV1 (0x80000000 >> 15) - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *-----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE -#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ - CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } -#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ -#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/assabet.h b/include/configs/assabet.h deleted file mode 100644 index 1a69ebe0da..0000000000 --- a/include/configs/assabet.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * 2004 (c) MontaVista Software, Inc. - * - * Configuation settings for the Intel Assabet board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ -#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ - -#undef CONFIG_USE_IRQ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ -#define CONFIG_LAN91C96_BASE 0x18000000 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ - -#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_SIZE PHYS_FLASH_SIZE -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#undef CFG_FLASH_PROTECTION -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#define CFG_ENV_IS_IN_FLASH 1 - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h deleted file mode 100644 index 90c74e52a6..0000000000 --- a/include/configs/atstk1002.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * Configuration settings for the ATSTK1002 CPU daughterboard - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_ATSTK1002 1 -#define CONFIG_ATSTK1000 1 - -#define CONFIG_ATSTK1000_EXT_FLASH 1 - -/* - * Timer clock frequency. We're using the CPU-internal COUNT register - * for this, so this is equivalent to the CPU core clock frequency - */ -#define CFG_HZ 1000 - -/* - * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL - * frequency and the peripherals to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL 1 -#define CFG_POWER_MANAGER 1 -#define CFG_OSC0_HZ 20000000 -#define CFG_PLL0_DIV 1 -#define CFG_PLL0_MUL 7 -#define CFG_PLL0_SUPPRESS_CYCLES 16 -#define CFG_CLKDIV_CPU 0 -#define CFG_CLKDIV_HSB 1 -#define CFG_CLKDIV_PBA 2 -#define CFG_CLKDIV_PBB 1 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CFG_PLL0_OPT 0x04 - -#define CFG_USART1 1 - -#define CFG_CONSOLE_UART_DEV DEVICE_USART1 - -/* User serviceable stuff */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" - -#define CONFIG_COMMANDS (CFG_CMD_BDI \ - | CFG_CMD_LOADS \ - | CFG_CMD_LOADB \ - /* | CFG_CMD_IMI */ \ - /* | CFG_CMD_CACHE */ \ - | CFG_CMD_FLASH \ - | CFG_CMD_MEMORY \ - /* | CFG_CMD_NET */ \ - | CFG_CMD_ENV \ - /* | CFG_CMD_IRQ */ \ - | CFG_CMD_BOOTD \ - | CFG_CMD_CONSOLE \ - /* | CFG_CMD_EEPROM */ \ - | CFG_CMD_ASKENV \ - | CFG_CMD_RUN \ - | CFG_CMD_ECHO \ - /* | CFG_CMD_I2C */ \ - | CFG_CMD_REGINFO \ - /* | CFG_CMD_DATE */ \ - /* | CFG_CMD_DHCP */ \ - /* | CFG_CMD_AUTOSCRIPT */ \ - /* | CFG_CMD_MII */ \ - | CFG_CMD_MISC \ - /* | CFG_CMD_SDRAM */ \ - /* | CFG_CMD_DIAG */ \ - /* | CFG_CMD_HWFLOW */ \ - /* | CFG_CMD_SAVES */ \ - /* | CFG_CMD_SPI */ \ - /* | CFG_CMD_PING */ \ - /* | CFG_CMD_MMC */ \ - /* | CFG_CMD_FAT */ \ - /* | CFG_CMD_IMLS */ \ - /* | CFG_CMD_ITEST */ \ - /* | CFG_CMD_EXT2 */ \ - ) - -#include <cmd_confdefs.h> - -#define CONFIG_ATMEL_USART 1 -#define CONFIG_PIO2 1 -#define CFG_NR_PIOS 5 -#define CFG_HSDRAMC 1 - -#define CFG_DCACHE_LINESZ 32 -#define CFG_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -/* External flash on STK1000 */ - -#define CFG_FLASH_BASE 0x00000000 -#define CFG_FLASH_SIZE 0x800000 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 135 - -#define CFG_MONITOR_BASE CFG_FLASH_BASE - -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 65536 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) - -#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) - -#define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - -#define CFG_DMA_ALLOC_LEN (16384) -#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) -#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) -/* Allow 2MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) -#define CFG_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " -#define CFG_CBSIZE 256 -#define CFG_MAXARGS 8 -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_LONGHELP 1 - -#define CFG_MEMTEST_START \ - ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) -#define CFG_MEMTEST_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ - }) -#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h deleted file mode 100644 index 2c160a4489..0000000000 --- a/include/configs/canmb.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#else -# error "TEXT_BASE must be 0xFE000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/canmb/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET (2*128*1024) -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE (128*1024) - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x0 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CFG_GPS_PORT_CONFIG 0x00058444 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047D01 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0x7f000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h deleted file mode 100644 index 83247862f7..0000000000 --- a/include/configs/csb272.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/* - * OS Bootstrap configuration - * - */ - -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm fe000000 fe100000" - - -/* - * BOOTP/DHCP protocol configuration - * - */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) -/* - * U-Boot Monitor Command Line Functions Configuration - * - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ -#endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#undef CFG_BASE_BAUD -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* - * Miscellaneous board specific definitions - * - */ -#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -/* - * Internal Definitions - * - * Boot Flags - * - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h deleted file mode 100644 index 0218a69721..0000000000 --- a/include/configs/csb472.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -/* - * OS Bootstrap configuration - * - */ - -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm ff800000 ff900000" - - -/* - * BOOTP/DHCP protocol configuration - * - */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) -/* - * U-Boot Monitor Command Line Functions Configuration - * - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ -#endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#undef CFG_EXT_SERIAL_CLOCK /* use internal serial clock */ -#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 -#define CFG_FLASH_SIZE 0x00800000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 64 /* max # of sectors on one chip */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -/* - * Internal Definitions - * - * Boot Flags - * - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h deleted file mode 100644 index 071d5b7f36..0000000000 --- a/include/configs/csb637.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> - * Anders Larsen <alarsen@rea.de> - * - * Configuation settings for the Cogent CSB637 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ -#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_CSB637 1 /* on a CSB637 board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ - -/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 -#define CFG_ALT_MEMTEST 1 -#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4 - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_AT91C_USE_RMII - -#undef CONFIG_HAS_DATAFLASH -#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 0 -#define CFG_MAX_DATAFLASH_PAGES 16384 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -/* - * FLASH Device configuration - */ -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_MAX_FLASH_SECT 64 - -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 3 -#define CFG_JFFS2_NUM_BANKS 1 - -#undef CFG_ENV_IS_IN_DATAFLASH - -#ifdef CFG_ENV_IS_IN_DATAFLASH -#define CFG_ENV_OFFSET 0x20000 -#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ -#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */ -#endif /* CFG_ENV_IS_IN_DATAFLASH */ - - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 } - -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif diff --git a/include/configs/delta.h b/include/configs/delta.h deleted file mode 100644 index 91284fdace..0000000000 --- a/include/configs/delta.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Configuation settings for the Delta board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ -#define CONFIG_DELTA 1 /* Delta board */ - -/* #define CONFIG_LCD 1 */ -#ifdef CONFIG_LCD -#define CONFIG_SHARP_LM8V31 -#endif -/* #define CONFIG_MMC 1 */ -#define BOARD_LATE_INIT 1 - -#undef CONFIG_SKIP_RELOCATE_UBOOT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#undef TURN_ON_ETHERNET -#ifdef TURN_ON_ETHERNET -# define CONFIG_DRIVER_SMC91111 1 -# define CONFIG_SMC91111_BASE 0x14000300 -# define CONFIG_SMC91111_EXT_PHY -# define CONFIG_SMC_USE_32_BIT -# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ -#endif - -#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ -#define CFG_I2C_SPEED 400000 /* I2C speed */ -#define CFG_I2C_SLAVE 1 /* I2C controllers address */ -#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ -#define CFG_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */ -#define CFG_I2C_INIT_BOARD 1 -/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ - -#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */ -#define CONFIG_PREBOOT "\0" - -#ifdef DELTA_CHECK_KEYBD -# define KEYBD_DATALEN 4 /* we have four keys */ -# define KEYBD_KP_DKIN0 0x1 /* vol+ */ -# define KEYBD_KP_DKIN1 0x2 /* vol- */ -# define KEYBD_KP_DKIN2 0x3 /* multi */ -# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */ -#endif /* DELTA_CHECK_KEYBD */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ -#ifdef TURN_ON_ETHERNET -# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) -#else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_ENV \ - | CFG_CMD_NAND \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_NET \ - | CFG_CMD_FLASH \ - | CFG_CMD_IMLS)) -#endif - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY -1 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0x80400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ - -#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ - -/* Monahans Core Frequency */ -#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ -#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ - - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* #define CFG_MMC_BASE 0xF0000000 */ - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ - -#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ -#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ - -#undef CFG_SKIP_DRAM_SCRUB - -/* - * NAND Flash - */ -/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ -#undef CFG_NAND_LEGACY - -#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ -#undef CFG_NAND1_BASE - -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -/* nand timeout values */ -#define CFG_NAND_PROG_ERASE_TO 3000 -#define CFG_NAND_OTHER_TO 100 -#define CFG_NAND_SENDCMD_RETRY 3 -#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ - -/* NAND Timing Parameters (in ns) */ -#define NAND_TIMING_tCH 10 -#define NAND_TIMING_tCS 0 -#define NAND_TIMING_tWH 20 -#define NAND_TIMING_tWP 40 - -#define NAND_TIMING_tRH 20 -#define NAND_TIMING_tRP 40 - -#define NAND_TIMING_tR 11123 -#define NAND_TIMING_tWHR 100 -#define NAND_TIMING_tAR 10 - -/* NAND debugging */ -#define CFG_DFC_DEBUG1 /* usefull */ -#undef CFG_DFC_DEBUG2 /* noisy */ -#undef CFG_DFC_DEBUG3 /* extremly noisy */ - -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 1 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NO_FLASH 1 - -#define CFG_ENV_IS_IN_NAND 1 -#define CFG_ENV_OFFSET 0x40000 -#define CFG_ENV_OFFSET_REDUND 0x44000 -#define CFG_ENV_SIZE 0x4000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h deleted file mode 100644 index c22391dab8..0000000000 --- a/include/configs/eXalion.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -/* #define CONFIG_MPC8240 1 */ -#define CONFIG_MPC8245 1 -#define CONFIG_EXALION 1 - -#if defined (CONFIG_MPC8240) - /* #warning ---------- eXalion with MPC8240 --------------- */ -#elif defined (CONFIG_MPC8245) - /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ -#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) -#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) -#else -#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -/* older kernels need clock in MHz newer in Hz */ - /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_BOOTDELAY 10 - - - /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_FLASH | \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ENV | \ - CFG_CMD_PCI ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 8 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_MISC_INIT_R 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ - /* return real value. */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) - -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -#if defined (CONFIG_MPC8240) -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ -#elif defined (CONFIG_MPC8245) -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ -#define CFG_ENV_ADDR 0xFFFC0000 -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#define CFG_ALT_MEMTEST 1 /* use real memory test */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -/* #define CFG_ISA_MEM 0xFD000000 */ -#define CFG_ISA_IO 0xFE000000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE -#define FLASH_BASE1_PRELIM 0 - - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI 1 /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 1 - -#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ -#define PCI_ENET3_IOADDR 0x83000000 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ -#define CFG_NS16550 1 -#define CFG_NS16550_SERIAL 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 38400 - -#define CFG_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1) -#define CFG_NS16550_CLK 1843200 /* COM1 only ! */ -#else -#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) -#endif - -#define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CFG_HZ 1000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ - - /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ - -#if defined (CONFIG_MPC8245) -/* Bit-field values for PMCR2. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ -#define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ -#endif - -/* Bit-field values for MIOCR1. */ -#if !defined (CONFIG_133MHZ_DRAM) -#define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ -#endif -/* Bit-field values for MIOCR2. */ -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ - /* - note bottom 3 bits MUST be 0 */ -#endif - -/* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ - -/* Bit-field values for MCCR2. */ -#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_REFINT 1300 /* no of clock cycles between CBR */ -#else /* refresh cycles */ -#define CFG_REFINT 750 -#endif - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_BSTOPRE 1023 -#else -#define CFG_BSTOPRE 250 -#endif - -/* Bit-field values for MCCR3. */ -/* the following are for SDRAM only */ - -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_REFREC 9 /* Refresh to activate interval */ -#else -#define CFG_REFREC 5 /* Refresh to activate interval */ -#endif -#if defined (CONFIG_MPC8240) -#define CFG_RDLAT 2 /* data latency from read command */ -#endif - -/* Bit-field values for MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 7 /* Activate to Precharge interval */ -#define CFG_ACTORW 5 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#else -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#endif -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGDIMM 0 -#if defined (CONFIG_MPC8240) -#define CFG_REGISTERD_TYPE_BUFFER 0 -#elif defined (CONFIG_MPC8245) -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - -/*----------------------------------------------------------------------- - memory bank settings - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 - -/*----------------------------------------------------------------------- - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#if defined (CONFIG_MPC8240) -#define CFG_ODCR 0xDF /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#elif defined (CONFIG_MPC8245) -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */ -#else -#define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */ -#endif -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/*----------------------------------------------------------------------- - * Block Address Translation (BAT) register settings. - */ -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - */ -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define CONFIG_ATAPI - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide supported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ - -/*----------------------------------------------------------------------- - * DISK Partition support - */ -#define CONFIG_DOS_PARTITION - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h deleted file mode 100644 index 04147a55d1..0000000000 --- a/include/configs/ep8248.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * U-Boot configuration for Embedded Planet EP8248 boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" - -#define CONFIG_EP8248 /* Embedded Planet EP8248 board */ - -#undef DEBUG - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -#define CFG_BCSR 0xFA000000 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) - -/* - Rx clock is CLK10 - * - Tx clock is CLK11 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - Rx clock is CLK13 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Not used - implemented in BCSR */ -#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) -#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) -#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) - -#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFE - -#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFD - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_I2C \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFF800000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_FIRST_SECTOR 0 -#define CFG_JFFS2_LAST_SECTOR 62 -#define CFG_JFFS2_SORT_FRAGMENTS -#define CFG_JFFS_CUSTOM_PART -#endif /* CFG_CMD_JFFS2 */ - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif /* CFG_CMD_I2C */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ - -#define CFG_ENV_IS_IN_FLASH - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#endif /* CFG_ENV_IS_IN_FLASH */ - -#define CFG_DEFAULT_IMMR 0x00010000 - -#define CFG_IMMR 0xF0000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x01240200 -#define CFG_SYPCR 0xFFFF0683 -#define CFG_BCR 0x00000000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_MPTPR 0x1300 -#define CFG_PSDMR 0x82672522 -#define CFG_PSRT 0x4B - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841) -#define CFG_SDRAM_OR 0xFF0030C0 - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) -#define CFG_OR0_PRELIM 0xFF8008C2 -#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801) -#define CFG_OR2_PRELIM 0xFFF00864 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h deleted file mode 100644 index c4134f3a24..0000000000 --- a/include/configs/ep82xxm.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (C) 2006 Embedded Planet, LLC. - * - * U-Boot configuration for Embedded Planet EP82xxM boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 -#define CPU_ID_STR "MPC8270" - -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ - /* 256MB SDRAM / 64MB FLASH */ - -#undef DEBUG - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -#define CFG_BCSR 0xFA000000 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_NET_MULTI - -#define CONFIG_ETHER_ON_FCC2 -#define CONFIG_ETHER_ON_FCC3 - -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Not used - implemented in BCSR */ -#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) -#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) -#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) - -#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFE - -#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFD - -#define MIIDELAY udelay(1) - - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_I2C \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_DATE \ - | CFG_CMD_DTT \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_DIAG \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_ETHADDR 00:10:EC:00:88:65 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 -#define CONFIG_IPADDR 10.0.0.245 -#define CONFIG_HOSTNAME EP82xxM -#define CONFIG_SERVERIP 10.0.0.26 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CFG_ENV_IN_OWN_SECT 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0xFC000000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -/* EEPROM Configuration */ -#define CFG_EEPROM_SIZE 0x1000 -#define CFG_I2C_EEPROM_ADDR 0x54 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -/* RTC Configuration */ -#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ -#define CFG_I2C_RTC_ADDR 0x68 -#define CONFIG_M41T11_BASE_YEAR 1900 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS {0} -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -/*----------------------------------------------------------------------- - * NVRAM Configuration - *----------------------------------------------------------------------- - */ -#define CFG_NVRAM_BASE_ADDR 0xFA080000 -#define CFG_NVRAM_SIZE (128*1024)-16 - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_PCI_BOOTDELAY 0 - -/* PCI Memory map (if different from default map */ -#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ -#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ -#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ -#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) - - -/* PCIBR0 - for PCI IO*/ -#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ -#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ -/* PCIBR1 - prefetch and non-prefetch regions joined together */ -#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL -#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) - - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_FIRST_SECTOR 0 -#define CFG_JFFS2_LAST_SECTOR 62 -#define CFG_JFFS2_SORT_FRAGMENTS -#define CFG_JFFS_CUSTOM_PART -#endif /* CFG_CMD_JFFS2 */ - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif /* CFG_CMD_I2C */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ - -#define CFG_DEFAULT_IMMR 0x00010000 -#define CFG_IMMR 0xF0000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x02610000 -#define CFG_SYPCR 0xFFFF0689 -#define CFG_BCR 0x8080E000 -#define CFG_SCCR 0x00000001 - -#define CFG_RMR 0 -#define CFG_TMCNTSC 0x000000C3 -#define CFG_PISCR 0x00000083 -#define CFG_RCCR 0 - -#define CFG_MPTPR 0x0A00 -#define CFG_PSDMR 0xC432246E -#define CFG_PSRT 0x32 - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) -#define CFG_SDRAM_OR 0xF0002900 - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) -#define CFG_OR0_PRELIM 0xFC000882 -#define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001) -#define CFG_OR4_PRELIM 0xFFF00050 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h deleted file mode 100644 index e0d823f2dc..0000000000 --- a/include/configs/h2_p2_dbg_board.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * TI H2 and P2 Debug Board hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __INCLUDED_H2_P2_DBH_BOARD_H -#define __INCLUDED_H2_P2_DBH_BOARD_H - -#include <asm/arch/sizes.h> - -/* - * The Debug board is designed to function with the P2 Sample, H2 - * Sample and 1610 Innovator boards. The main difference AFAICT is - * the chip selects used with each system ; - * - * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs - * H2 Sample : CS1a is used to select the CPLD registers. - * - */ - -/*************************************************************************** - * CPLD Registers - **************************************************************************/ - -#define H2DBG_CPLD_REVISION 0x04000010 -#define H2DBG_BOARD_REVISION 0x04000012 -#define H2DBG_GPIO_REGISTER 0x04000014 -#define H2DBG_LED_CONTROL 0x04000016 -#define H2DBG_MISC_INPUT 0x04000018 -#define H2DBG_LAN_STATUS 0x0400001A -#define H2DBG_LAN_RESET 0x0400001C -#define H2DBG_ETH_REG_BASE 0x04000300 - -/*************************************************************************** - * Ethernet Control Registers - * These are for the LAN91C96 on the debug board - **************************************************************************/ - -/* Bank 0 in IO space */ - -#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */ -#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */ -#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */ -#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */ -#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */ -#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */ - -/* Bank 1 in IO space */ - -#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */ -#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */ -#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */ -#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */ -#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */ -#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */ -#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */ -#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */ -#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */ -#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */ - -/* Bank 2 in IO space */ - -#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */ -#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */ -#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */ -#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */ -#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */ -#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */ -#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */ -#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */ -#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */ -#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */ -#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */ - - -#ifndef __ASSEMBLY__ - -/* - * A couple of utility inlines to aid debugging using the LED's on the - * debug board. - */ - -static inline void set_led_state(int state) -{ - static unsigned long hw_led_state = 0; - volatile unsigned short *led_address = (volatile unsigned short *)0x04000016; - - hw_led_state = ((unsigned long)state); - *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF); -} - - -static inline void spin_up_leds(void) -{ - volatile int i, j, k; - - for (k = 0; k < 2; k++) { - for (i = 0; i < 16; i++) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - for (i = 15; i >= 0; i--) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - } -} - -#endif /* ! __ASSEMBLY__ */ - -#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h deleted file mode 100644 index cfaf153223..0000000000 --- a/include/configs/hmi1001.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_HMI1001 1 /* HMI1001 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFF800000 - -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_CFI_AMD_RESET - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_DISPLAY_BASE 0x80600000 -#define CFG_STATUS1_BASE 0x80600200 -#define CFG_STATUS2_BASE 0x80600300 - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x01051004 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004FB00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* 8Mbit SRAM @0x80100000 */ -#define CFG_CS1_START 0x80100000 -#define CFG_CS1_SIZE 0x00100000 -#define CFG_CS1_CFG 0x19B00 - -/* FRAM 32Kbyte @0x80700000 */ -#define CFG_CS2_START 0x80700000 -#define CFG_CS2_SIZE 0x00008000 -#define CFG_CS2_CFG 0x19800 - -/* Display H1, Status Inputs, EPLD @0x80600000 */ -#define CFG_CS3_START 0x80600000 -#define CFG_CS3_SIZE 0x00100000 -#define CFG_CS3_CFG 0x00019800 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_LOGO - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CFG_ISA_IO CONFIG_PCI_IO_BUS - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ - -#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) -#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) - -#endif /* __CONFIG_H */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h deleted file mode 100644 index af4ecf621a..0000000000 --- a/include/configs/ixdpg425.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2003 - * Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl - * - * Configuation settings for the IXDPG425 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ -#define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */ - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* - * Ethernet - */ -#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -/* - * Misc configuration options - */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ - -#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ -#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_PING) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* These are u-boot generic parameters */ -#include <cmd_confdefs.h> - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00010000 /* default load address */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*************************************************************** - * Platform/Board specific defines start here. - ***************************************************************/ - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ixdpg425\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/arm\0" \ - "bootfile=/tftpboot/ixdpg425/uImage\0" \ - "kernel_addr=50080000\0" \ - "ramdisk_addr=50200000\0" \ - "load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \ - "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \ - "cp.b 100000 50000000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ - -#define CFG_DRAM_BASE 0x00000000 -#define CFG_DRAM_SIZE 0x01000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -/* - * Expansion bus settings - */ -#define CFG_EXP_CS0 0xbcd23c42 - -/* - * SDRAM settings - */ -#define CFG_SDR_CONFIG 0x18 -#define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ - -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } - -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * GPIO settings - */ -#define CFG_GPIO_PCI_INTA_N 6 -#define CFG_GPIO_PCI_INTB_N 7 -#define CFG_GPIO_SWITCH_RESET_N 8 -#define CFG_GPIO_SLIC_RESET_N 13 -#define CFG_GPIO_PCI_CLK 14 -#define CFG_GPIO_EXTBUS_CLK 15 - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 - -#endif /* __CONFIG_H */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h deleted file mode 100644 index 6590f6f5f0..0000000000 --- a/include/configs/kb9202.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Rick Bronson <rick@efn.org> - * - * Configuation settings for the AT91RM9200DK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ -#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -/* Only define one of the following, based on board type */ -/* #define CONFIG_KB9200 1 KwikByte KB9202 board */ -/* #define CONFIG_KB9201 1 KwikByte KB9202 board */ -#define CONFIG_KB9202 1 /* KwikByte KB9202 board */ - -#define CONFIG_KB920x 1 /* Any KB920x board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CFG_LONGHELP - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 - -#define CFG_FLASH_BASE 0x10000000 - -#ifdef CONFIG_KB9202 -#define PHYS_FLASH_SIZE 0x1000000 -#else -#define PHYS_FLASH_SIZE 0x200000 -#endif - -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 - -#define CONFIG_HARD_I2C - -#define CFG_ENV_IS_IN_EEPROM - -#ifdef CONFIG_KB9202 -#define CFG_ENV_OFFSET 0x3E00 -#define CFG_ENV_SIZE 0x0200 -#else -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x1000 -#endif -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_EEPROM_PAGE_WRITE_BITS 6 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0 /* not used */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h deleted file mode 100644 index 61cf70576d..0000000000 --- a/include/configs/kvme080.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * (C) Copyright 2005 - * Sangmoon Kim, dogoil@etinsys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_KVME080 1 - -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_IPADDR 192.168.0.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.0.1 - -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 " \ - "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \ - "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \ - "kvme080:eth0:none " \ - "mtdparts=phys_mapped_flash:12m(root),-(kernel)" - -#define CONFIG_BOOTCOMMAND \ - "tftp 800000 kvme080/uImage; " \ - "bootm 800000" - -#define CONFIG_LOADADDR 800000 - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_LOADS_ECHO 1 -#undef CFG_LOADS_BAUD_CHANGE - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS164x - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP) - -#define CONFIG_NETCONSOLE - -#include <cmd_confdefs.h> - -#define CFG_LONGHELP -#define CFG_PROMPT "=> " -#define CFG_CBSIZE 256 -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 -#define CFG_BARGSIZE CFG_CBSIZE - -#define CFG_MEMTEST_START 0x00400000 -#define CFG_MEMTEST_END 0x07C00000 - -#define CFG_LOAD_ADDR 0x00100000 -#define CFG_HZ 1000 - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x7C000000 -#define CFG_EUMB_ADDR 0xFC000000 -#define CFG_NVRAM_BASE_ADDR 0xFF000000 -#define CFG_NS16550_COM1 0xFF080000 -#define CFG_NS16550_COM2 0xFF080010 -#define CFG_NS16550_COM3 0xFF080020 -#define CFG_NS16550_COM4 0xFF080030 -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MAX_RAM_SIZE 0x20000000 -#define CFG_FLASH_SIZE (16 * 1024 * 1024) -#define CFG_NVRAM_SIZE 0x7FFF8 - -#define CONFIG_VERY_BIG_RAM - -#define CFG_MONITOR_LEN 0x00040000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (512 << 10) - -#define CFG_BOOTMAPSZ (8 << 20) - -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_USE_BUFFER_WRITE -#define CFG_FLASH_PROTECTION -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_PROTECT_CLEAR - -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 - -#define CFG_FLASH_ERASE_TOUT 120000 -#define CFG_FLASH_WRITE_TOUT 500 - -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 - -#define CFG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CFG_NVRAM_ACCESS_ROUTINE -#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR -#define CFG_ENV_SIZE 0x400 -#define CFG_ENV_OFFSET 0 - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 14745600 - -#define CONFIG_PCI -#define CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 -#define CONFIG_EEPRO100_SROM_WRITE - -#define CFG_RX_ETH_BUFFER 8 - -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 400000 -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_CLK_FREQ 33333333 - -#define CFG_CACHELINE_SIZE 32 -#if CONFIG_COMMANDS & CFG_CMD_KGDB -# define CFG_CACHELINE_SHIFT 5 -#endif - -#define CFG_DLL_EXTEND 0x00 -#define CFG_PCI_HOLD_DEL 0x20 - -#define CFG_ROMNAL 15 -#define CFG_ROMFAL 31 - -#define CFG_REFINT 430 - -#define CFG_DBUS_SIZE2 1 - -#define CFG_BSTOPRE 121 -#define CFG_REFREC 8 -#define CFG_RDLAT 4 -#define CFG_PRETOACT 3 -#define CFG_ACTTOPRE 5 -#define CFG_ACTORW 3 -#define CFG_SDMODE_CAS_LAT 3 -#define CFG_SDMODE_WRAP 0 - -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (0x4000000 - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x04000000 -#define CFG_BANK1_END (0x8000000 - 1) -#define CFG_BANK1_ENABLE 1 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 - -#define CFG_BANK_ENABLE 0x03 - -#define CFG_ODCR 0x75 -#define CFG_PGMAX 0x32 - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -#define BOOTFLAG_COLD 0x01 -#define BOOTFLAG_WARM 0x02 - -#endif /* __CONFIG_H */ diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h deleted file mode 100644 index 3722fd2933..0000000000 --- a/include/configs/lpd7a400-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A400_10_H -#define __LPD7A400_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A400 1 /* Sharp LH7A400 S0C */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CFG_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC_USE_IOFUNCS - -#endif /* __LPD7A400_10_H */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h deleted file mode 100644 index d7d0460ef6..0000000000 --- a/include/configs/lpd7a400.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A400_H_ -#define __LPD7A400_H_ - -#define CONFIG_LPD7A400 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A400-10 card engine - */ -#include <configs/lpd7a400-10.h> - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * select serial console configuration - */ -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) -#endif - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 3 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LPD7A400> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256<<10) - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) -#define CFG_ENV_SIZE 0x40000 - -#endif /* __LPD7A400_H_ */ diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h deleted file mode 100644 index a8af950b65..0000000000 --- a/include/configs/lpd7a404-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A404_10_H -#define __LPD7A404_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CFG_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC_USE_IOFUNCS - -#endif /* __LPD7A404_10_H */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h deleted file mode 100644 index 4002e6849c..0000000000 --- a/include/configs/lpd7a404.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A404_H_ -#define __LPD7A404_H_ - -#define CONFIG_LPD7A404 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A404-10 card engine - */ -#include <configs/lpd7a404-10.h> - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * select serial console configuration - */ -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) -#endif - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 3 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LPD7A404> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256<<10) - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) -#define CFG_ENV_SIZE 0x40000 - -#endif /* __LPD7A404_H_ */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h deleted file mode 100644 index f60973b26d..0000000000 --- a/include/configs/mcc200.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MCC200 1 /* ... on MCC200 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - * - * To select console on the one of 8 external UARTs, - * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, - * or as 5, 6, 7, or 8 for the second Quad UART. - * COM11, COM12, COM13, COM14 are located on the second Quad UART. - * - * CONFIG_PSC_CONSOLE must be undefined in this case. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#ifdef CONFIG_CONSOLE_COM12 -#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ -#else -#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ -#endif -#else -/* PRS200 configuration: */ -#undef CONFIG_QUART_CONSOLE -#endif /* CONFIG_PRS200 */ -/* - * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 - * and undefine CONFIG_QUART_CONSOLE. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ -#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ -#else -/* PRS200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#endif -#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ - !defined(CONFIG_SERIAL_MULTI) -#error "Select only one console device!" -#endif -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII 1 - -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -/* automatic software updates (see board/mcc200/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_USB_CMD | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -#ifdef CONFIG_PRS200 -# define CFG__BOARDNAME "prs200" -# define CFG__LINUX_CONSOLE "ttyS0" -#else -# define CFG__BOARDNAME "mcc200" -# define CFG__LINUX_CONSOLE "ttyEU7" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=" CFG__BOARDNAME "\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "console=" CFG__LINUX_CONSOLE "\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ - "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ - "text_base=" MK_STR(TEXT_BASE) "\0" \ - "update=protect off ${text_base} +${filesize};" \ - "era ${text_base} +${filesize};" \ - "cp.b 200000 ${text_base} ${filesize}\0" \ - "unlock=yes\0" \ - "" -#undef MK_STR -#undef XMK_STR - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CFG_FLASH_BASE 0xfc000000 -#define CFG_FLASH_SIZE 0x04000000 - -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#if TEXT_BASE == CFG_FLASH_BASE -#define CFG_LOWBOOT 1 -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xf0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 1 - -/* - * LCD Splash Screen - */ -#if !defined(CONFIG_PRS200) -#define CONFIG_LCD 1 -#endif - -#if defined(CONFIG_LCD) -#define CONFIG_SPLASH_SCREEN 1 -#define CFG_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME -#endif - -/* - * GPIO configuration - */ -/* 0x10000004 = 32MB SDRAM */ -/* 0x90000004 = 64MB SDRAM */ -#if defined(CONFIG_LCD) -/* set PSC2 in UART mode */ -#define CFG_GPS_PORT_CONFIG 0x00000044 -#else -#define CFG_GPS_PORT_CONFIG 0x00000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004fb00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CFG_CS2_START 0x80000000 -#define CFG_CS2_SIZE 0x00001000 -#define CFG_CS2_CFG 0x1d300 - -/* Second Quad UART @0x80010000 */ -#define CFG_CS1_START 0x80010000 -#define CFG_CS1_SIZE 0x00001000 -#define CFG_CS1_CFG 0x1d300 - -/* - * Select one of quarts as a default - * console. If undefined - PSC console - * wil be default - */ -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/* - * QUART Expanders support - */ -#if defined(CONFIG_QUART_CONSOLE) -/* - * We'll use NS16550 chip routines, - */ -#define CFG_NS16550 1 -#define CFG_NS16550_SERIAL 1 -#define CONFIG_CONS_INDEX 1 -/* - * To achieve necessary offset on SC16C554 - * A0-A2 (register select) pins with NS16550 - * functions (in struct NS16550), REG_SIZE - * should be 4, because A0-A2 pins are connected - * to DA2-DA4 address bus lines. - */ -#define CFG_NS16550_REG_SIZE 4 -/* - * LocalPlus Bus already inited in cpu_init_f(), - * so can work with QUART's chip selects. - * One of four SC16C554 UARTs is selected with - * A3-A4 (DA5-DA6) lines. - */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) -#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) -#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) -#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#elif -#error "Wrong QUART expander number." -#endif - -/* - * SC16C554 chip's external crystal oscillator frequency - * is 7.3728 MHz - */ -#define CFG_NS16550_CLK 7372800 -#endif /* CONFIG_QUART_CONSOLE */ -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h deleted file mode 100644 index 6762cd61ea..0000000000 --- a/include/configs/ml300.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * ML300.h: ML300 specific config options - * - * http://www.xilinx.com/ml300 - * - * Derived from : ML2.h - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR - * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * - * - * (c) Copyright 2002 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ -/* #define ET_DEBUG 1 */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ - -#define CONFIG_SYSTEMACE 1 -#define CONFIG_DOS_PARTITION 1 -#define CFG_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR -#define CFG_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH - -#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ - -/* following are used only if env is in EEPROM */ -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR -#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ -#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ -#endif - -#include "../board/xilinx/ml300/xparameters.h" - -#define CFG_NO_FLASH 1 /* no flash */ -#define CFG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ - "root=/dev/xsysace/disc0/part3 rw" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ - CFG_CMD_IMLS ) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ - & ~REMOVE_COMMANDS) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ -/* 300000000 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_DUART_CHAN 0 -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550 1 -#define CFG_INIT_CHAN1 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0x04000000 -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h deleted file mode 100644 index 2942be84f2..0000000000 --- a/include/configs/omap1510.h +++ /dev/null @@ -1,777 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP hardware map - * - * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <asm/arch/sizes.h> - -/* - There are 2 sets of general I/O --> - 1. GPIO (shared between ARM & DSP, configured by ARM) - 2. MPUIO which can be used only by the ARM. - - Base address FFFB:5000 is where the ARM accesses the MPUIO control registers - (see 7.2.2 of the TRM for MPUIO reg definitions). - - Base address E101:5000 is reserved for ARM access of the same MPUIO control - regs, but via the DSP I/O map. This address is unavailable on 1510. - - Base address FFFC:E000 is where the ARM accesses the GPIO config registers - directly via its own peripheral bus. - - Base address E101:E000 is where the ARM can access the same GPIO config - registers, but the access takes place through the ARM port interface (called - API or MPUI) via the DSP's peripheral bus (DSP I/O space). - - Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses - instead of the E101:E000 addresses. The DSP has only read access of the pin - control register, so this may explain the inability to write to E101:E018. - Try accessing pin control reg at FFFC:E018. - */ -#define OMAP1510_GPIO_BASE 0xfffce000 -#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE -#define OMAP1510_GPIO_SIZE SZ_4K - -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - -/* - * Where's the flush address (for flushing D and I cache?) - */ -#define FLUSH_BASE 0xdf000000 -#define FLUSH_BASE_PHYS 0x00000000 - -#ifndef __ASSEMBLER__ - -#define PCIO_BASE 0 - -/* - * RAM definitions - */ -#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) -#define KERNTOPHYS(a) ((unsigned long)(&a)) -#define KERNEL_BASE (0x10008000) -#endif - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x)) - -/* ---------------------------------------------------------------------------- - * OMAP1510 system registers - * ---------------------------------------------------------------------------- - */ - -#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ -#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ -#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ -#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ -#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ -#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ -#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ - -/* - * OMAP1510 UART3 Registers - */ - -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ - -/* UART3 Registers Maping through MPU bus */ - -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -/* - * Configuration Registers - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define GATE_INH_CTRL_0 0xfffe1050 -#define VOLTAGE_CTRL_0 0xfffe1060 -#define TEST_DBG_CTRL_0 0xfffe1070 - -#define MOD_CONF_CTRL_0 0xfffe1080 - -#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ - -#define USB_OTG_CTRL 0xFFFB040C -#define USB_TRANSCEIVER_CTRL 0xFFFE1064 -#define PULL_DWN_CTRL_4 0xFFFE10AC -#define PU_PD_SEL_0 0xFFFE10B4 -#define PU_PD_SEL_1 0xFFFE10B8 -#define PU_PD_SEL_2 0xFFFE10BC -#define PU_PD_SEL_3 0xFFFE10C0 -#define PU_PD_SEL_4 0xFFFE10C4 - -#endif -/* - * Traffic Controller Memory Interface Registers - */ -#define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) -#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) - -/* - * LCD Panel - */ -#define TI925_LCD_BASE 0xFFFEC000 -#define TI925_LCD_CONTROL (TI925_LCD_BASE) -#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) -#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) -#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) -#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) -#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) - -#define OMAP_LCD_CONTROL TI925_LCD_CONTROL - -/* I2C Registers */ - -#define I2C_BASE 0xfffb3800 - -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ - -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_AD0 (1 << 8) /* Address zero */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Vector Register (I2C_IV): */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* - * MMC/SD Host Controller Registers - */ - -#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ -#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ -#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ -#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ -#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ -#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ -#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ -#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ -#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ -#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ -#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ -#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ -#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ -#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ -#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ -#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ -#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ -#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ -#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ -#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ -#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ -#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ -#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ -#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ - -/* MMC masks */ - -#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ -#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ -#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ -#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ -#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ -#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ -#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ -#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ -#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ -#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ -#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ -#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ -#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ - -/* 2.9.2 MPUI Interface Registers FFFE:C900 */ - -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) - -/* 2.9.6 Traffic Controller Memory Interface Registers: */ -#define OMAP_IMIF_PRIO_REG 0xfffecc00 -#define OMAP_EMIFS_PRIO_REG 0xfffecc04 -#define OMAP_EMIFF_PRIO_REG 0xfffecc08 -#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c -#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 -#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 -#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 -#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c -#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 -#define OMAP_EMIFF_MRS 0xfffecc24 -#define OMAP_TIMEOUT1 0xfffecc28 -#define OMAP_TIMEOUT2 0xfffecc2c -#define OMAP_TIMEOUT3 0xfffecc30 -#define OMAP_ENDIANISM 0xfffecc34 - -/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -/* - * Memory chunk set aside for the Framebuffer in SRAM - */ -#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE - - -/* - * DMA - */ - -#define OMAP1510_DMA_BASE 0xFFFED800 -#define OMAP_DMA_BASE OMAP1510_DMA_BASE - -/* Global Register selection */ -#define NO_GLOBAL_DMA_ACCESS 0 - -/* Channel select field - * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... - */ -#define LCD_CHANNEL 0xc - -/* Register Select Field (LCD) */ -#define DMA_LCD_CTRL 0 -#define DMA_LCD_TOP_F1_L 1 -#define DMA_LCD_TOP_F1_U 2 -#define DMA_LCD_BOT_F1_L 3 -#define DMA_LCD_BOT_F1_U 4 - -#define LCD_FRAME_MODE (1<<0) -#define LCD_FRAME_IT_IE (1<<1) -#define LCD_BUS_ERROR_IT_IE (1<<2) -#define LCD_FRAME_1_IT_COND (1<<3) -#define LCD_FRAME_2_IT_COND (1<<4) -#define LCD_BUS_ERROR_IT_COND (1<<5) -#define LCD_SOURCE_IMIF (1<<6) - -/* - * Real-Time Clock - */ - -#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) -#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) -#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) -#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) -#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) -#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) -#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) - - -/* --------------------------------------------------------------------------- - * OMAP1510 Interrupt Handlers - * --------------------------------------------------------------------------- - * - */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 -#define OMAP1510_ITR 0x0 -#define OMAP1510_MASK 0x4 - -#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE -#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR -#define INTERRUPT_MASK_REGISTER OMAP1510_MASK - - -/* --------------------------------------------------------------------------- - * OMAP1510 TIMERS - * --------------------------------------------------------------------------- - * - */ - -#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP1510_MPUTIMER_BASE 0xfffec500 -#define OMAP1510_MPUTIMER_OFF 0x00000100 - -#define OMAP1510_TIMER1_BASE 0xfffec500 -#define OMAP1510_TIMER2_BASE 0xfffec600 -#define OMAP1510_TIMER3_BASE 0xfffec700 - -/* MPU Timer Registers */ -#define CNTL_TIMER 0 -#define LOAD_TIM 4 -#define READ_TIM 8 - -/* CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7<<PTV_BIT) -#define MPUTIM_PTV_BIT 2 -#define MPUTIM_AR (1<<1) -#define MPUTIM_ST (1<<0) - -/* --------------------------------------------------------------------------- - * OMAP1510 GPIO (SHARED) - * --------------------------------------------------------------------------- - * - */ -#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) -#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) -#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) -#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) -#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) -#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) -#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) - - -/* --------------------------- - * OMAP1510 MPUIO (ARM only) - *---------------------------- - */ -#define OMAP1510_MPUIO_BASE 0xFFFB5000 -#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) -#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) -#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) - -/* --------------------------------------------------------------------------- - * OMAP1510 TIPB (only) - * --------------------------------------------------------------------------- - * - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * OMAP1510 Camera Interface - * --------------------------------------------------------------------------- - */ -#define CAMERA_BASE (IO_BASE + 0x6800) -#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) -#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) -#define CAM_MODE_REG (CAMERA_BASE + 0x08) -#define CAM_STATUS_REG (CAMERA_BASE + 0x0C) -#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) -#define CAM_GPIO_REG (CAMERA_BASE + 0x14) -#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) - - -/* CTRLCLOCK bit shifts */ -#define FOSCMOD_BIT 0 -#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) -#define FOSCMOD_12MHz 0x0 -#define FOSCMOD_6MHz 0x2 -#define FOSCMOD_9_6MHz 0x4 -#define FOSCMOD_24MHz 0x5 -#define FOSCMOD_8MHz 0x6 -#define POLCLK (1<<3) -#define CAMEXCLK_EN (1<<4) -#define MCLK_EN (1<<5) -#define DPLL_EN (1<<6) -#define LCLK_EN (1<<7) - -/* IT_STATUS bit shifts */ -#define V_UP (1<<0) -#define V_DOWN (1<<1) -#define H_UP (1<<2) -#define H_DOWN (1<<3) -#define FIFO_FULL (1<<4) -#define DATA_XFER (1<<5) - -/* MODE bit shifts */ -#define CAMOSC (1<<0) -#define IMGSIZE_BIT 1 -#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) -#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ -#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ -#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ -#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ -#define ORDERCAMD (1<<3) -#define EN_V_UP (1<<4) -#define EN_V_DOWN (1<<5) -#define EN_H_UP (1<<6) -#define EN_H_DOWN (1<<7) -#define EN_DMA (1<<8) -#define THRESHOLD (1<<9) -#define THRESHOLD_BIT 9 -#define THRESHOLD_MASK (0x7f<<9) -#define EN_NIRQ (1<<16) -#define EN_FIFO_FULL (1<<17) -#define RAZ_FIFO (1<<18) - -/* STATUS bit shifts */ -#define VSTATUS (1<<0) -#define HSTATUS (1<<1) - -/* GPIO bit shifts */ -#define CAM_RST (1<<0) - - -/********************* - * Watchdog timer. - *********************/ -#define WDTIM_BASE 0xfffec800 -#define WDTIM_CONTROL (WDTIM_BASE+0x00) -#define WDTIM_LOAD (WDTIM_BASE+0x04) -#define WDTIM_READ (WDTIM_BASE+0x04) -#define WDTIM_MODE (WDTIM_BASE+0x08) - -/* Values to write to mode register to disable the watchdog function. */ -#define DISABLE_SEQ1 0xF5 -#define DISABLE_SEQ2 0xA0 - -/* WDTIM_CONTROL bit definitions. */ -#define WDTIM_CONTROL_ST BIT7 - - -/* --------------------------------------------------------------------------- - * Differentiating processor versions for those who care. - * --------------------------------------------------------------------------- - * - */ -#define OMAP1509 0 -#define OMAP1510 1 - -#define OMAP1510_ID_CODE_REG 0xfffed404 - -#ifndef __ASSEMBLY__ -int cpu_type(void); -#endif - -/* - * EVM Implementation Specifics. - * - * *** NOTE *** - * Any definitions in these files should be prefixed by an identifier - - * eg. OMAP1510P1_FLASH0_BASE . - * - */ -#ifdef CONFIG_OMAP_INNOVATOR -#include "innovator.h" -#endif - -#ifdef CONFIG_OMAP_1510P1 -#include "omap1510p1.h" -#endif - -/*****************************************************************************/ - -#define CLKGEN_RESET_BASE (0xfffece00) -#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) -#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) -#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) -#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) -#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) -#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) -#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) - - -#define CK_CLKIN 12 /* MHz */ -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#ifndef __ASSEMBLER__ -#define CK_DPLL1 ((volatile __u16 *)0xfffecf00) -#else -#define CK_DPLL1 (0xfffecf00) -#endif -#define SETARM_IDLE_SHIFT - -/* ARM_CKCTL bit shifts */ -#define PERDIV 0 -#define LCDDIV 2 -#define ARMDIV 4 -#define DSPDIV 6 -#define TCDIV 8 -#define DSPMMUDIV 10 -#define ARM_TIMXO 12 -#define EN_DSPCK 13 -#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ - -#define ARM_CKCTL_RSRVD_BIT15 (1 << 15) -#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) -#define ARM_CKCTL_EN_DSPCK (1 << 13) -#define ARM_CKCTL_ARM_TIMXO (1 << 12) -#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) -#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) -#define ARM_CKCTL_TCDIV1 (1 << 9) -#define ARM_CKCTL_TCDIV2 (1 << 8) -#define ARM_CKCTL_DSPDIV1 (1 << 7) -#define ARM_CKCTL_DSPDIV0 (1 << 6) -#define ARM_CKCTL_ARMDIV1 (1 << 5) -#define ARM_CKCTL_ARMDIV0 (1 << 4) -#define ARM_CKCTL_LCDDIV1 (1 << 3) -#define ARM_CKCTL_LCDDIV0 (1 << 2) -#define ARM_CKCTL_PERDIV1 (1 << 1) -#define ARM_CKCTL_PERDIV0 (1 << 0) - -/* ARM_IDLECT1 bit shifts */ -#define IDLWDT_ARM 0 -#define IDLXORP_ARM 1 -#define IDLPER_ARM 2 -#define IDLLCD_ARM 3 -#define IDLLB_ARM 4 -#define IDLHSAB_ARM 5 -#define IDLIF_ARM 6 -#define IDLDPLL_ARM 7 -#define IDLAPI_ARM 8 -#define IDLTIM_ARM 9 -#define SETARM_IDLE 11 - -/* ARM_IDLECT2 bit shifts */ -#define EN_WDTCK 0 -#define EN_XORPCK 1 -#define EN_PERCK 2 -#define EN_LCDCK 3 -#define EN_LBCK 4 -#define EN_HSABCK 5 -#define EN_APICK 6 -#define EN_TIMCK 7 -#define DMACK_REQ 8 -#define EN_GPIOCK 9 -#define EN_LBFREECK 10 - -#define ARM_RSTCT1_SW_RST (1 << 3) -#define ARM_RSTCT1_DSP_RST (1 << 2) -#define ARM_RSTCT1_DSP_EN (1 << 1) -#define ARM_RSTCT1_ARM_RST (1 << 0) - -/* ARM_RSTCT2 bit shifts */ -#define EN_PER 0 - -#define ARM_SYSST_RSRVD_BIT15 (1 << 15) -#define ARM_SYSST_RSRVD_BIT14 (1 << 14) -#define ARM_SYSST_CLOCK_SELECT2 (1 << 13) -#define ARM_SYSST_CLOCK_SELECT1 (1 << 12) -#define ARM_SYSST_CLOCK_SELECT0 (1 << 11) -#define ARM_SYSST_RSRVD_BIT10 (1 << 10) -#define ARM_SYSST_RSRVD_BIT9 (1 << 9) -#define ARM_SYSST_RSRVD_BIT8 (1 << 8) -#define ARM_SYSST_RSRVD_BIT7 (1 << 7) -#define ARM_SYSST_IDLE_DSP (1 << 6) -#define ARM_SYSST_POR (1 << 5) -#define ARM_SYSST_EXT_RST (1 << 4) -#define ARM_SYSST_ARM_MCRST (1 << 3) -#define ARM_SYSST_ARM_WDRST (1 << 2) -#define ARM_SYSST_GLOB_SWRST (1 << 1) -#define ARM_SYSST_DSP_WDRST (1 << 0) - -/* Table 15-23. DPLL Control Registers: */ -#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) - -/* Table 15-24. Control Register (CTL_REG): */ - -#define DPLL_CTL_REG_IOB (1 << 13) -#define DPLL_CTL_REG_PLL_MULT Fld(5,0) - -/*****************************************************************************/ - -/* OMAP INTERRUPT REGISTERS */ -#define IRQ_ITR 0x00 -#define IRQ_MIR 0x04 -#define IRQ_SIR_IRQ 0x10 -#define IRQ_SIR_FIQ 0x14 -#define IRQ_CONTROL_REG 0x18 -#define IRQ_ISR 0x9c -#define IRQ_ILR0 0x1c - -#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) -#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) - -/* INTERRUPT LEVEL REGISTER BITS */ -#define ILR_PRIORITY_MASK (0x3c) -#define ILR_PRIORITY_SHIFT (2) -#define ILR_LEVEL_TRIGGER (1<<1) -#define ILR_FIQ (1<<0) - -#define IRQ_LEVEL_INT 1 -#define IRQ_EDGE_INT 0 - -/* Macros to access registers */ -#define outb(v,p) *(volatile u8 *) (p) = v -#define outw(v,p) *(volatile u16 *) (p) = v -#define outl(v,p) *(volatile u32 *) (p) = v - -#define inb(p) *(volatile u8 *) (p) -#define inw(p) *(volatile u16 *) (p) -#define inl(p) *(volatile u32 *) (p) diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h deleted file mode 100644 index 016d3d8bd0..0000000000 --- a/include/configs/omap1510inn.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta <kshitij@ti.com> - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -/* -#define CONFIG_DRIVER_SMC9196 -#define CONFIG_SMC9196_BASE 0x08000300 -#define CONFIG_SMC9196_EXT_PHY -*/ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x08000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> -#include <configs/omap1510.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h deleted file mode 100644 index c6ca689a5f..0000000000 --- a/include/configs/omap1610h2.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Kshitij Gupta <kshitij@ti.com> - * Configuration settings for the TI OMAP 1610 H2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ -#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */ - -/* input clock of PLL */ -/* the OMAP1610 H2 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> -#include <configs/omap1510.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CFG_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h deleted file mode 100644 index 5db4f52beb..0000000000 --- a/include/configs/omap5912osk.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta <kshitij@ti.com> - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ -#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* input clock of PLL */ -/* the OMAP5912 OSK has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04800300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> -#include <configs/omap1510.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ - -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_ENV_IS_IN_FLASH 1 -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap730.h b/include/configs/omap730.h deleted file mode 100644 index 03abcb312e..0000000000 --- a/include/configs/omap730.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP730 hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __INCLUDED_OMAP730_H -#define __INCLUDED_OMAP730_H - -#include <asm/arch/sizes.h> - -/*************************************************************************** - * OMAP730 Configuration Registers - **************************************************************************/ - -#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002)) -#define DSP_CONF ((unsigned int)(0xFFFE1004)) -#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008)) -#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008)) -#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C)) -#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012)) -#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016)) -#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018)) -#define SPECCTL ((unsigned int)(0xFFFE101C)) -#define SPARE1 ((unsigned int)(0xFFFE1020)) -#define SPARE2 ((unsigned int)(0xFFFE1024)) -#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028)) -#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030)) -#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060)) -#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070)) -#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074)) -#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078)) -#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C)) -#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080)) -#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084)) -#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088)) -#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C)) -#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090)) -#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094)) -#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098)) -#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C)) -#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0)) -#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4)) -#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4)) -#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8)) -#define BIST_CONTROL ((unsigned int)(0xFFFE10C0)) -#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4)) -#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8)) -#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0)) -#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4)) -#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8)) -#define DEBUG1 ((unsigned int)(0xFFFE10E0)) -#define DEBUG2 ((unsigned int)(0xFFFE10E4)) -#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8)) - -/*************************************************************************** - * OMAP730 EMIFS Registers (TRM 2.5.7) - **************************************************************************/ - -#define TCMIF_BASE 0xFFFECC00 - -#define EMIFS_LRUREG (TCMIF_BASE + 0x04) -#define EMIFS_CONFIG (TCMIF_BASE + 0x0C) -#define FLASH_CFG_0 (TCMIF_BASE + 0x10) -#define FLASH_CFG_1 (TCMIF_BASE + 0x14) -#define FLASH_CFG_2 (TCMIF_BASE + 0x18) -#define FLASH_CFG_3 (TCMIF_BASE + 0x1C) -#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40) -#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28) -#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C) -#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30) -#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44) -#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48) -#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C) -#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50) -#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54) -#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58) -#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C) - -/*************************************************************************** - * OMAP730 Interrupt handlers - **************************************************************************/ - -#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */ -#define OMAP_IH2_BASE 0xfffe0000 - -/*************************************************************************** - * OMAP730 Timers - * - * There are three general purpose OS timers in the 730 that can be - * configured in autoreload or one-shot modes. - **************************************************************************/ - -#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP730_MPUTIMER_BASE 0xfffec500 -#define OMAP730_MPUTIMER_OFF 0x00000100 - -#define OMAP730_TIMER1_BASE 0xFFFEC500 -#define OMAP730_TIMER2_BASE 0xFFFEC600 -#define OMAP730_TIMER3_BASE 0xFFFEC700 - -/* MPU Timer Register offsets */ -#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */ -#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */ -#define READ_TIM 0x08 /* MPU_READ_TIMER */ - -/* MPU_CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7<<PTV_BIT) -#define MPUTIM_PTV_BIT 2 -#define MPUTIM_AR (1<<1) -#define MPUTIM_ST (1<<0) - -/*************************************************************************** - * OMAP730 GPIO - * - * The GPIO control is split over 6 register bases in the OMAP730 to allow - * access to all the (6 x 32) GPIO pins! - **************************************************************************/ - -#define OMAP730_GPIO_BASE_1 0xFFFBC000 -#define OMAP730_GPIO_BASE_2 0xFFFBC800 -#define OMAP730_GPIO_BASE_3 0xFFFBD000 -#define OMAP730_GPIO_BASE_4 0xFFFBD800 -#define OMAP730_GPIO_BASE_5 0xFFFBE000 -#define OMAP730_GPIO_BASE_6 0xFFFBE800 - -#define GPIO_DATA_INPUT 0x00 -#define GPIO_DATA_OUTPUT 0x04 -#define GPIO_DIRECTION_CONTROL 0x08 -#define GPIO_INTERRUPT_CONTROL 0x0C -#define GPIO_INTERRUPT_MASK 0x10 -#define GPIO_INTERRUPT_STATUS 0x14 - -#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS)) - -#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS)) - -#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS)) - -#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS)) - -#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS)) - -#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT)) -#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT)) -#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL)) -#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL)) -#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK)) -#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS)) - -/*************************************************************************** - * OMAP730 Watchdog timers - **************************************************************************/ - -#define WDTIM_BASE 0xFFFEC800 -#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */ -#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */ -#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */ -#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */ - -/*************************************************************************** - * OMAP730 Interrupt Registers - **************************************************************************/ - -/* Interrupt Register offsets */ - -#define IRQ_ITR 0x00 -#define IRQ_MIR 0x04 -#define IRQ_SIR_IRQ 0x10 -#define IRQ_SIR_FIQ 0x14 -#define IRQ_CONTROL_REG 0x18 -#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */ -#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */ -#define IRQ_GMIR 0xA0 - -#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR) -#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR) - -/*************************************************************************** - * OMAP730 Intersystem Communication Register (TRM 4.5) - **************************************************************************/ - -#define ICR_BASE 0xFFFBB800 - -#define M_ICR (ICR_BASE + 0x00) -#define G_ICR (ICR_BASE + 0x02) -#define M_CTL (ICR_BASE + 0x04) -#define G_CTL (ICR_BASE + 0x06) -#define PM_BA (ICR_BASE + 0x0A) -#define DM_BA (ICR_BASE + 0x0C) -#define RM_BA (ICR_BASE + 0x0E) -#define SSPI_TAS (ICR_BASE + 0x12) - -#endif /* ! __INCLUDED_OMAP730_H */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h deleted file mode 100644 index 262e9d6acf..0000000000 --- a/include/configs/p3mx.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards - * - * The defines: - * CONFIG_P3M750 or - * CONFIG_P3M7448 - * are written into include/config.h by the "make xxx_config" command - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3Mx /* used for both board versions */ - -#if defined (CONFIG_P3M750) -#define CONFIG_750FX /* 750GL/GX/FX */ -#define CFG_BOARD_NAME "P3M750" -#define CFG_BUS_HZ 100000000 -#define CFG_BUS_CLK CFG_BUS_HZ -#define CFG_TCLK 100000000 -#elif defined (CONFIG_P3M7448) -#define CONFIG_74xx -#define CFG_BOARD_NAME "P3M7448" -#define CFG_BUS_HZ 133333333 -#define CFG_BUS_CLK CFG_BUS_HZ -#define CFG_TCLK 133333333 -#endif -#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ - -/* which initialization functions to call for this board */ -#define CFG_BOARD_ASM_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 -#ifdef CONFIG_P3M750 -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#if defined (CONFIG_P3M750) -#define CFG_FLASH_BASE 0xff800000 /* start of flash banks */ -#define CFG_BOOT_SIZE _8M /* boot flash */ -#elif defined (CONFIG_P3M7448) -#define CFG_FLASH_BASE 0xff000000 /* start of flash banks */ -#define CFG_BOOT_SIZE _16M /* boot flash */ -#endif -#define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */ -#define CFG_MONITOR_BASE 0xfff00000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -#define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ -#define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */ -#define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ - /* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x42000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_MPSC /* MV64460 Serial */ -#define CONFIG_MPSC_PORT 0 -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Ethernet - *----------------------------------------------------------------------*/ -/* Change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CFG_ETH_PORT ETH_0 -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 2 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#if defined (CONFIG_P3M750) -#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/ -#elif defined (CONFIG_P3M7448) -#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ -#endif -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_MV64460_ECC - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CFG_I2C_SPEED 100000 /* I2C speed default */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) - -#define CFG_PCI_IDSEL 0x30 - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=p3mx/u-boot/u-boot.bin\0" \ - "load=tftp 100000 ${u-boot}\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "serverip=11.0.0.152\0" - -#if defined (CONFIG_P3M750) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m750\0" \ - "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "vxfile=p3m750/vxWorks\0" \ - "vxuser=ddg\0" \ - "vxpass=ddg\0" \ - "vxtarget=target\0" \ - "vxflags=0x8\0" \ - "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ - "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ - "f=${vxflags}\0" -#elif defined (CONFIG_P3M7448) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m7448\0" -#endif - -#if defined (CONFIG_P3M750) -#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" -#elif defined (CONFIG_P3M7448) -#define CONFIG_BOOTCOMMAND " " -#endif - -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_PCI | \ - CFG_CMD_CACHE | \ - CFG_CMD_SDRAM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x08000000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * Marvell MV64460 config settings - *----------------------------------------------------------------------*/ -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ -#if defined (CONFIG_P3M750) -#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ -#elif defined (CONFIG_P3M7448) -#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ -#endif - -/* - * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) - * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) - * MPP[2] NC - * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) - * MPP[4] PCI Monarch# GPIO IN Connected to P12 - * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) - * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 - * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 - * MPP[8] Reserved Do not use - * MPP[9] Reserved Do not use - * MPP[10] Reserved Do not use - * MPP[11] Reserved Do not use - * MPP[12] Phy 0 Interrupt Int IN - * MPP[13] Phy 1 Interrupt Int IN - * MPP[14] NC - * MPP[15] NC - * MPP[16] PCI Interrupt C Int IN Connected to P11 - * MPP[17] PCI Interrupt D Int IN Connected to P11 - * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] - * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic - * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog - * MPP[21] NC - * MPP[22] GP LED Green GPIO OUT - * MPP[23] GP LED Red GPIO OUT - * MPP[24] Watchdog NMI# Int OUT - * MPP[25] NC - * MPP[26] NC - * MPP[27] PCI Interrupt A Int IN Connected to P11 - * MPP[28] NC - * MPP[29] PCI Interrupt B Int IN Connected to P11 - * MPP[30] Module reset GPIO OUT Board reset - * MPP[31] PCI EReady GPIO IN Connected to P12 - */ -#define CFG_MPP_CONTROL_0 0x00303022 -#define CFG_MPP_CONTROL_1 0x00000000 -#define CFG_MPP_CONTROL_2 0x00004000 -#define CFG_MPP_CONTROL_3 0x00000004 -#define CFG_GPP_LEVEL_CONTROL 0x280730D0 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U - -/* set rest out of range for Linux !!!!!!!!!!! */ - -/* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT7U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ -#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#define CFG_L2 - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h deleted file mode 100644 index aa0901f3ff..0000000000 --- a/include/configs/p3p440.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_p3p440.h - configuration for Prodrive P3P440 - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3P440 1 /* Board is P3P440 */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CONFIG_SDRAM_ECC /* enable ECC support */ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ - {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C RTC - *----------------------------------------------------------------------*/ -#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) for environment - *----------------------------------------------------------------------*/ -#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3p440\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/p3p440/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "unlock=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x1c /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CFG_FLASH0 0xFF800000 -#define CFG_FLASH1 0xFF000000 -#define CFG_FLASH2 0xFE800000 -#define CFG_FLASH3 0xFE000000 -#define CFG_USB 0xF0000000 - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x03050200 -#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x03050200 -#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ -#define CFG_EBC_PB2AP 0x03050200 -#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x03050200 -#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 7 (USB controller) initialization */ -#define CFG_EBC_PB7AP 0x02015000 -#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 } - -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h deleted file mode 100644 index e5e27724e1..0000000000 --- a/include/configs/pxa255_idp.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Copied from lubbock.h - * - * (C) Copyright 2004 - * BEC Systems <http://bec-systems.com> - * Cliff Brake <cliff.brake@gmail.com> - * Configuation settings for the Accelent/Vibren PXA255 IDP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/pxa-regs.h> - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ - -/* - * define the following to enable debug blinks. A debug blink function - * must be defined in memsetup.S - */ -#undef DEBUG_BLINK_ENABLE -#undef DEBUG_BLINKC_ENABLE - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ - -#undef CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_SHARP_LM8V31 -#endif - -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * PXA250 IDP memory map information - */ - -#define IDP_CS5_ETH_OFFSET 0x03400000 - - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) -#define CONFIG_SMC_USE_32_BIT 1 -/* #define CONFIG_SMC_USE_IOFUNCS */ - -/* the following has to be set high -- suspect something is wrong with - * with the tftp timeout routines. FIXME!!! - */ -#define CONFIG_NET_RETRY_COUNT 100 - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG - -/* - * Current memory map for Vibren supplied Linux images: - * - * Flash: - * 0 - 0x3ffff (size = 0x40000): bootloader - * 0x40000 - 0x13ffff (size = 0x100000): kernel - * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs - * - * RAM: - * 0xa0008000 - kernel is loaded - * 0xa3000000 - Uboot runs (48MB into RAM) - * - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "prog_boot_mmc=" \ - "mw.b 0xa0000000 0xff 0x40000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset;" \ - "fi\0" \ - "prog_uzImage_mmc=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_mmc=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa1000000 uzImage && " \ - "then " \ - "bootm 0xa1000000; " \ - "fi\0" \ - "prog_boot_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset; " \ - "fi\0" \ - "prog_uzImage_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_net=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if bootp 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" - - -/* "erase_env=" */ -/* "protect off" */ - - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa0800000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define RTC 1 /* enable 32KHz osc */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - -#define CFG_GAFR0_L_VAL 0x80001005 -#define CFG_GAFR0_U_VAL 0xa5128012 -#define CFG_GAFR1_L_VAL 0x699a9558 -#define CFG_GAFR1_U_VAL 0xaaa5aa6a -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x2 -#define CFG_GPCR0_VAL 0x1800400 -#define CFG_GPCR1_VAL 0x0 -#define CFG_GPCR2_VAL 0x0 -#define CFG_GPDR0_VAL 0xc1818440 -#define CFG_GPDR1_VAL 0xfcffab82 -#define CFG_GPDR2_VAL 0x1ffff -#define CFG_GPSR0_VAL 0x8000 -#define CFG_GPSR1_VAL 0x3f0002 -#define CFG_GPSR2_VAL 0x1c000 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x29DCA4D2 -#define CFG_MSC1_VAL 0x43AC494C -#define CFG_MSC2_VAL 0x39D449D4 -#define CFG_MDCNFG_VAL 0x090009C9 -#define CFG_MDREFR_VAL 0x0085C017 -#define CFG_MDMRS_VAL 0x00220022 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000003 -#define CFG_MCMEM0_VAL 0x00014405 -#define CFG_MCMEM1_VAL 0x00014405 -#define CFG_MCATT0_VAL 0x00014405 -#define CFG_MCATT1_VAL 0x00014405 -#define CFG_MCIO0_VAL 0x00014405 -#define CFG_MCIO1_VAL 0x00014405 - -/* - * FLASH and environment organization - */ -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 - -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x40000 - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* put cfg at end of flash for now */ -#define CFG_ENV_IS_IN_FLASH 1 - /* Addr of Environment Sector */ -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h deleted file mode 100644 index 84db5a5df5..0000000000 --- a/include/configs/quantum.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * changes for 16M board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ -#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* default developmenmt environment */ - -#define CONFIG_ETHADDR 00:0B:17:00:00:00 - -#define CONFIG_IPADDR 10.10.69.10 -#define CONFIG_SERVERIP 10.10.69.49 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME QUANTUM -#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BOOTCOMMAND "bootm ff000000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=12345\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" - -/* - * Select the more full-featured memory test (Barr embedded systems) - */ -#define CFG_ALT_MEMTEST - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ -#define CONFIG_RTC_M48T35A 1 - -#undef CONFIG_WATCHDOG - -/* NVRAM and RTC */ -#define CFG_NVRAM_BASE_ADDR 0xFA000000 -#define CFG_NVRAM_SIZE 2048 - - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "system" -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 - - #define CFG_FLASH_CFI_DRIVER - - -#ifdef CFG_FLASH_CFI_DRIVER - #define CFG_FLASH_CFI 1 - #undef CFG_FLASH_USE_BUFFER_WRITE - #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#endif - -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* FPGA */ -#define CONFIG_MISC_INIT_R -#define CFG_FPGA_SPARTAN2 -#define CFG_FPGA_PROG_FEEDBACK - - -/*----------------------------------------------------------------------- - * Reset address - */ -#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 - -#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */ -#define CFG_OR3_PRELIM 0xFFFF8910 - -#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CFG_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 20 - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h deleted file mode 100644 index e1e406bf9b..0000000000 --- a/include/configs/r5200.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Configuation settings for the R5200 board - * - * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com> - * Based on Motorola MC5272C3 board config - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _R5200_H -#define _R5200_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5271 /* define processor type */ -#define CONFIG_R5200 /* define board type */ - -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_IPADDR 192.168.0.172 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_ETHADDR 00:06:3b:00:44:55 - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 0xFFFF /* clock modulus */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CFG_ENV_OFFSET 0x20000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_IS_EMBEDDED 1 -#else -#define CFG_ENV_ADDR 0xf0020000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#endif - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* Note: We only copy one sectors worth of application code from location - * 10200000 for speed purposes. Increase the size if necessary */ -#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400" -#define CONFIG_BOOTDELAY 1 - -#define CFG_PROMPT "u-boot> " -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00002000 - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -#define CFG_HZ 1000000 -#define CFG_CLK 100000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_MBAR 0x40000000 /* Register Base Addrs */ - -#define CFG_ENET_BD_BASE 0x480000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ -#define CFG_FLASH_BASE 0x10000000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CFG_MONITOR_BASE 0x20000 -#else -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) -#endif - -#define CFG_MONITOR_LEN 0x20001 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 1000 - -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_SIZE 0x800000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CFG_FECI2C 0xF0 - -#endif /* _R5200_H */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h deleted file mode 100644 index beff28ab32..0000000000 --- a/include/configs/sbc405.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * (C) Copyright 2001 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" - -#define CONFIG_RAMBOOT \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOT \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ - - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ - "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ - "f=0x08 tn=sbc405 o=emac \0" \ - "env_startaddr=FF000000\0" \ - "env_endaddr=FF03FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "uboot_startaddr=FFFC0000\0" \ - "uboot_endaddr=FFFFFFFF\0" \ - "update=tftp ${loadaddr} u-boot.bin;" \ - "protect off ${uboot_startaddr} ${uboot_endaddr};" \ - "era ${uboot_startaddr} ${uboot_endaddr};" \ - "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ - "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ - "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ - "era ${env_startaddr} ${env_endaddr};" \ - "protect on ${env_startaddr} ${env_endaddr}\0" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - 0 ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.224 -#define CONFIG_SERVERIP 192.168.193.119 -#define CONFIG_GATEWAYIP 192.168.193.97 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFFC0000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_INCREMENT 0x01000000 -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_ADDR CFG_FLASH_BASE /* starting right at the beginning */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h deleted file mode 100644 index b9d3806027..0000000000 --- a/include/configs/sbc8560.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ - -/* XXX flagging this as something I might want to delete */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ - #define CFG_OR5_PRELIM 0xff000ff7 - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 /* MII PHY management */ -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:01:af:07:9b:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c -#endif - -#define CONFIG_SERVERIP 192.168.0.131 -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH /home/ppc -#define CONFIG_BOOTFILE pImage - -#endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h deleted file mode 100644 index 575373972a..0000000000 --- a/include/configs/sequoia.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * sequoia.h - configuration for Sequoia board (PowerPC440EPx) - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ -#ifndef CONFIG_RAINIER -#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ -#define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#else -#define CONFIG_440GRX 1 /* Specific PPC440GRx */ -#endif -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#define CFG_BOOT_BASE_ADDR 0xf0000000 -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ -#define CFG_OCM_BASE 0xe0010000 /* ocm */ -#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/* Don't change either of these */ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - -#define CFG_USB2D0_BASE 0xe0000100 -#define CFG_USB_DEVICE 0xe0000000 -#define CFG_USB_HOST 0xe0000400 -#define CFG_BCSR_BASE 0xc0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ -#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - -#define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif - -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ -#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ -#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ -#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ -#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ - -#ifdef CFG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE -#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) -#endif - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (256) /* 256MB */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#endif - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=sequoia\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "bootfile=/tftpboot/sequoia/uImage\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ - "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 100000 FFFA0000 60000\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_M88E1111_PHY 1 -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ - -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NET_MULTI 1 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 1 - -/* USB */ -#ifdef CONFIG_440EPX -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* Comment this out to enable USB 1.1 device */ -#define USB_2_0_DEVICE - -#define CMD_USB CFG_CMD_USB -#else -#define CMD_USB 0 /* no USB on 440GRx */ -#endif /* CONFIG_440EPX */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DTT | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CMD_USB) - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 - -/* - * On Sequoia CS0 and CS3 are switched when configuring for NAND booting - */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x03017300 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) - -/* Memory Bank 3 (NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) -#else -#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 3 (NOR-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x03017300 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) -#endif - -/* Memory Bank 2 (CPLD) initialization */ -#define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) - -/*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) -#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ - -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h deleted file mode 100644 index e106b3b574..0000000000 --- a/include/configs/smmaco4.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/smmaco4/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CFG_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CFG_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CFG_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h deleted file mode 100644 index 4937638820..0000000000 --- a/include/configs/sorcery.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * (C) Copyright 2004 - * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC8220 1 -#define CONFIG_SORCERY 1 /* Sorcery board */ - -/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ - -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* PCI */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 - -#define CONFIG_PCI_MEM_BUS 0x80000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x71000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_PCI_CFG_BUS 0x70000000 -#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS -#define CONFIG_PCI_CFG_SIZE 0x01000000 - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP | \ - 0) - -/* CFG_CMD_MII | \ */ -/* CFG_CMD_USB | \ */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Default Environment - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_HOSTNAME sorcery - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/sorcery/uImage\0" \ - "kernel_addr=FFE00000\0" \ - "ramdisk_addr=FFB00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * Flexbus Chipselect configuration - * Beware: Some CS# seem to be mandatory (if these CS# are not set, - * board can hang-up in unpredictable place). - * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS# - */ - -/* Flash */ -#define CFG_CS0_BASE 0xf800 -#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ -#define CFG_CS0_CTRL 0x001019c0 - -/* NVM */ -#define CFG_CS1_BASE 0xf7e8 -#define CFG_CS1_MASK 0x00040000 /* 256K */ -#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ - -/* Atlas2 + Gemini */ -#define CFG_CS2_BASE 0xf7e7 -#define CFG_CS2_MASK 0x00010000 /* 64K*/ -#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ - -/* CAN Controller */ -#define CFG_CS3_BASE 0xf7e6 -#define CFG_CS3_MASK 0x00010000 /* 64K */ -#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ - -/* Foreign interface */ -#define CFG_CS4_BASE 0xf7e5 -#define CFG_CS4_MASK 0x00010000 /* 64K */ -#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ - -/* CPLD */ -#define CFG_CS5_BASE 0xf7e4 -#define CFG_CS5_MASK 0x00010000 /* 64K */ -#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ - -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH_BASE (CFG_FLASH0_BASE) - -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ - CFG_FLASH_BASE+0x04000000 } /* two banks */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) -#define CFG_ENV_SIZE 0x4000 /* 16K */ -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* SDRAM configuration (for SPD) */ -#define CFG_SDRAM_TOTAL_BANKS 1 -#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x100 -#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ - -/* SDRAM drive strength register (for SSTL_2 class II)*/ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC8220_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1F -#define CONFIG_MII 1 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 - -/* -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h deleted file mode 100644 index 8ffcd2f49e..0000000000 --- a/include/configs/spc1920.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de - * - * Configuation settings for the SPC1920 board. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __H -#define __CONFIG_H - -#define CONFIG_SPC1920 1 /* SPC1920 board */ -#define CONFIG_MPC885 1 /* MPC885 CPU */ - -#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MII -/* #define MII_DEBUG */ -/* #define CONFIG_FEC_ENET */ -#undef CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 -#define FEC_ENET -/* #define CONFIG_FEC2_PHY_NORXERR */ -/* #define CFG_DISCOVER_PHY */ -/* #define CONFIG_PHY_ADDR 0x1 */ -#define CONFIG_FEC2_PHY 1 - -#define CONFIG_BAUDRATE 19200 - -/* use PLD CLK4 instead of brg */ -#undef CFG_SPC1920_SMC1_CLK4 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#define CFG_8xx_CPUCLK_MAX 133000000 - -#define CFG_RESET_ADDRESS 0xf8000000 - -#define CONFIG_BOARD_EARLY_INIT_F - - -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ - -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII) - /* & ~( CFG_CMD_NET)) */ - - -#endif /* !CONFIG_COMMANDS */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ - -/* - * Flash - */ -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* #define CFG_SCCR SCCR_TBS */ -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CFG_DER 0 - - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - - -/* - * Init Memory Controller: - */ - -/* BR0 and OR0 (FLASH) */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - - -/* - * SDRAM CS1 UPMB - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE -#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */ - -#define CFG_PRELIM_OR1_AM 0xF0000000 -/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING) -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V) - -/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */ -/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */ - -#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64)) -#define CFG_PTA_PER_CLK 195 -#define CFG_MBMR_PTB 195 -#define CFG_MPTPR MPTPR_PTP_DIV16 -#define CFG_MAR 0x88 - -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - -#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - - -/* PLD CS5 */ -#define CFG_SPC1920_PLD_BASE 0x80000000 -#define CFG_PRELIM_OR5_AM 0xffff8000 - -#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \ - OR_CSNT_SAM | \ - OR_ACS_DIV1 | \ - OR_BI | \ - OR_SCY_0_CLK | \ - OR_TRLX) - -#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - -/* #define CFG_PLD_BASE 0x30000000 */ -/* #define CFG_OR5_PRELIM 0xffff1110 */ -/* #define CFG_BR5_PRELIM 0x30000401 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#endif /* __CONFIG_H */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h deleted file mode 100644 index 417fde4068..0000000000 --- a/include/configs/spieval.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_STK52XX -#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_STK52XX -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - -/* - * Video console - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CFG_CONSOLE_IS_IN_ENV - -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CFG_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_MINIFAP) -#undef I2C_ADDR_LIST -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_HWMON_ADDR, \ - CFG_I2C_SLAVE } -#endif - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CFG_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CFG_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CFG_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CFG_CS2_START 0xE5000000 -#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ -#define CFG_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stamp.h b/include/configs/stamp.h deleted file mode 100644 index 248ca70de0..0000000000 --- a/include/configs/stamp.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * U-boot - stamp.h Configuration file for STAMP board - * having BF533 processor - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_STAMP_H__ -#define __CONFIG_STAMP_H__ - -/* - * Board settings - * - */ - -#define __ADSPLPBLACKFIN__ 1 -#define __ADSPBF533__ 1 -#define CONFIG_STAMP 1 -#define CONFIG_RTC_BF533 1 - -/* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 - -#define CONFIG_VDSP 1 - -/* - * Clock settings - * - */ - -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 45 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 - -/* - * Network Settings - */ -/* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP -#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs - -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ - -/* - * Command settings - * - */ - -#define CFG_LONGHELP 1 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot 0x1000000 linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot 0x1000000 linux;" \ - "run nfsargs;run addip;bootelf\0" \ - "flashboot=bootm 0x20100000\0" \ - "" - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Console settings - * - */ - -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_LOADS_ECHO 1 - -/* - * Network settings - * - */ - -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define HARDCODE_MAC 1 */ - -/* - * Flash settings - * - */ - -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ - -#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ -#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -/* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 - -/* - * following timeouts shall be used once the - * Flash real protection is enabled - */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ - -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF3 -#define PF_SDA PF2 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE - -/* - * Compact Flash settings - */ - -/* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF 1 */ - -#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x20200000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 -#endif - -/* - * SDRAM settings - * - */ - -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x08000000 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HZ 1000 /* 1ms time tick */ - -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_SIZE 0x4000 -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) - -#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/* - * FLASH organization and environment definitions - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) -*/ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 - -#ifdef CONFIG_VDSP -#define ET_EXEC_VDSP 0x8 -#define SHT_STRTAB_VDSP 0x1 -#define ELFSHDRSIZE_VDSP 0x2C -#define VDSP_ENTRY_ADDR 0xFFA00000 -#endif - -#endif diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h deleted file mode 100644 index 916952c1fd..0000000000 --- a/include/configs/stxxtc.h +++ /dev/null @@ -1,587 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * U-Boot port on STx XTc 8xx board - * Mostly copied from Panto's NETTA2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ - -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ - -/* Select one of few clock rates defined later in this file. -*/ -/* #define MPC8XX_HZ 50000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_AUTOSCRIPT -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CFG_DISCOVER_PHY -#define CONFIG_MII 1 -#undef CONFIG_RMII - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ -#undef CONFIG_FEC1_PHY_NORXERR - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 3 -#undef CONFIG_FEC2_PHY_NORXERR - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_NFS) - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -/* yes this is weird, I know :) */ -#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000) -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 } - -#define CFG_FLASH_PROTECTION - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif -#else -#error unsupported freq for XIN (must be 10MHz) -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ - -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ - -#define CFG_REMAP_OR_AM 0x80000000 -#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH) -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR4 and OR4 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE 0xF1000000 - -/****************************************************************/ - -/* NAND */ -#define CFG_NAND_LEGACY -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CFG_MAX_NAND_DEVICE 1 -#undef NAND_NO_RB - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ - } while(0) - -#ifndef NAND_NO_RB -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#else -#define NAND_WAIT_READY(nand) udelay(12) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -/*****************************************************************************/ - -#define CFG_DIRECT_FLASH_TFTP -#define CFG_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, - * CxOE and CxRESET. We use the CxOE. - */ -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ - -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ - else \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/******************************************************************************/ - -#define CFG_CONSOLE_IS_IN_ENV 1 -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 -#define CFG_CONSOLE_ENV_OVERWRITE 1 - -/******************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY - -/*****************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CRC32_VERIFY 1 -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*****************************************************************************/ - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,MPC870@0" -#define OF_TBCLK (MPC8XX_HZ / 16) -#define CONFIG_OF_HAS_BD_T 1 -#define CONFIG_OF_HAS_UBOOT_ENV 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h deleted file mode 100644 index bbeeeb8c57..0000000000 --- a/include/configs/uc100.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 /* enable 862 since the */ -#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */ - -#define CONFIG_UC100 1 /* ...on a UC100 module */ - -#define MPC8XX_FACT 4 /* Multiply by 4 */ -#define MPC8XX_XIN 25000000 /* 25.0 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/uc100/uImage\0" \ - "kernel_addr=40000000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \ - "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \ - "cp.b 100000 40700000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* no status-led */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CFG_POST_CACHE | \ - CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_SPR ) -#undef CONFIG_POST - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) - -#define CONFIG_NETCONSOLE - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CFG_RESET_ADDRESS 0x90000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK 0x00000000 -#define CFG_SCCR (SCCR_EBDF11) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (0x00000d24) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */ -#define CFG_OR1_PRELIM 0xfc000a00 -#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */ -#define CFG_OR2_PRELIM 0xfff00d24 -#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */ -#define CFG_OR3_PRELIM 0xffff8f44 -#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */ -#define CFG_OR4_PRELIM 0xffff0300 -#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */ -#define CFG_OR5_PRELIM 0xffff8db0 - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */ -#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */ - -/*----------------------------------------------------------------------- - * I2C stuff - */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (24C164) - */ -#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CFG_DISCOVER_PHY 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h deleted file mode 100644 index e19591d299..0000000000 --- a/include/configs/v38b.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, - * wd@denx.de. - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ...on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ - -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ - -#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ - -#define CONFIG_NETCONSOLE 1 - -#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ - -#define CFG_XLB_PIPELINING 1 /* gives better performance */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * DDR - */ -#define SDRAM_DDR 1 /* is DDR */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* - * PCI - no suport - */ -#undef CONFIG_PCI - -/* - * Partitions - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * USB - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DATE | \ - CFG_CMD_USB | \ - CFG_CMD_FAT) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Boot low with 16 MB Flash - */ -#define CFG_LOWBOOT 1 -#define CFG_LOWBOOT16 1 - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootcmd=run net_nfs\0" \ - "bootdelay=3\0" \ - "baudrate=115200\0" \ - "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ - "filesystem over NFS; echo\0" \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ - "hostname=v38b\0" \ - "ethact=FEC ETHERNET\0" \ - "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ - "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ - "cp.b 200000 ff000000 $(filesize);" \ - "prot on ff000000 ff03ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.18\0" \ - "serverip=192.168.1.1\0" \ - "ethaddr=00:e0:ee:00:05:2e\0" \ - "bootfile=/tftpboot/v38b/uImage\0" \ - "u-boot=/tftpboot/v38b/u-boot.bin\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - use CFI driver - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x90001404 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/* - * IDE/ATA (supports IDE harddisk) - */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ - -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */ - -#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ - -#define CFG_ATA_STRIDE 4 /* Interval between registers */ - -/* - * Status LED - */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ - else \ - *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ - } while(0) - -#define __led_init(_msk, st) \ - do { \ - *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ - } while(0) -#endif /* __ASSEMBLY__ */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h deleted file mode 100644 index 17fe441e45..0000000000 --- a/include/configs/virtlab2.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ -#define CONFIG_TQM8xxL 1 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_LCD) -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* Map peripheral control registers on CS4 */ -#define CFG_PERIPHERAL_BASE 0xA0000000 -#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK) -#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00) -#endif /* __CONFIG_H */ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h deleted file mode 100644 index 0f6d623c58..0000000000 --- a/include/configs/voiceblue.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * Configuation settings for the TI OMAP VoiceBlue board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <configs/omap1510.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 5910 */ - -/* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ -#define CONFIG_XTAL_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R /* There is nothing to really init */ -#define BOARD_LATE_INIT /* but we flash the LEDs here */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE SZ_64M - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x0c000000 - -#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ - -/* - * FLASH organization - */ -#define CFG_FLASH_CFI /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ -#define CFG_MAX_FLASH_BANKS 1 -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 } -#else -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -/* FIXME: Does not work on AMD flash */ -/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ - -#define CFG_MONITOR_BASE PHYS_FLASH_1 -#define CFG_MONITOR_LEN SZ_128K - -/* - * Environment settings - */ -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_ENV_IS_NOWHERE -#define CFG_ENV_SIZE SZ_1K -#else -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) -#define CFG_ENV_SIZE SZ_8K -#define CFG_ENV_SECT_SIZE SZ_64K -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE - -#endif - -/* - * Size of malloc() pool and stack - */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKSIZE SZ_8K -#define PHYS_SDRAM_1_RESERVED 0 -#else -#define CFG_MALLOC_LEN SZ_4M -#define CONFIG_STACKSIZE SZ_1M -#define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE) -#endif - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x08000300 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#ifdef VOICEBLUE_SMALL_FLASH -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN) -#else -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_ENV | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_JFFS2) -#endif - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#define CONFIG_LOOPW - -#ifdef VOICEBLUE_SMALL_FLASH -#define CONFIG_BOOTDELAY 0 -#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/ -#define CFG_AUTOLOAD "n" /* no autoload */ -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "setup=setenv bootargs console=ttyS0,${baudrate} " \ - "root=/dev/nfs ip=dhcp\0" \ - "update=erase c000000 c03ffff; " \ - "cp.b 10400000 c000000 ${filesize}\0" -#else -#define CONFIG_BOOTDELAY 3 -#undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CFG_AUTOLOAD "n" /* no autoload */ -#define CONFIG_BOOTCOMMAND "run nboot" -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "silent=1\0" \ - "ospart=0\0" \ - "swapos=no\0" \ - "setpart=" \ - "if test $swapos = yes; then " \ - "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\ - "setenv swapos no; saveenv; " \ - "else " \ - "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\ - "fi\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "mtdparts=$mtdparts\0" \ - "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart; setenv bootargs $bootargs " \ - "root=/dev/mtdblock$partition ro " \ - "rootfstype=jffs2\0" \ - "initrdargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs; fsload /boot/uImage; bootm\0" \ - "iboot=bootp; run initrdargs; tftp; bootm\0" \ - "nboot=bootp; run nfsargs; tftp; bootm\0" -#endif - -#ifndef VOICEBLUE_SMALL_FLASH -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ - -/* - * JFFS2 partitions (mtdparts command line support) - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=omapflash.0" -#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)" - -#endif /* VOICEBLUE_SMALL_FLASH */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#ifndef VOICEBLUE_SMALL_FLASH -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE -#endif -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "# " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START PHYS_SDRAM_1 -#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE OMAP1510_TIMER1_BASE -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ - (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) - -#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ -#define OMAP5910_LCD_DIV 2 /* CKL/4 */ -#define OMAP5910_ARM_DIV 0 /* CKL/1 */ -#define OMAP5910_DSP_DIV 0 /* CKL/1 */ -#define OMAP5910_TC_DIV 1 /* CKL/2 */ -#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ -#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ - -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ -#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ - (OMAP5910_LCD_DIV << 2) | \ - (OMAP5910_ARM_DIV << 4) | \ - (OMAP5910_DSP_DIV << 6) | \ - (OMAP5910_TC_DIV << 8) | \ - (OMAP5910_DSP_MMU_DIV << 10) | \ - (OMAP5910_ARM_TIM_SEL << 12)) - -#define VOICEBLUE_LED_REG 0x04030000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h deleted file mode 100644 index 1705d6eb22..0000000000 --- a/include/configs/yellowstone.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * yellowstone.h - configuration for YELLOWSTONE board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ -#define CONFIG_440GR 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_BOARD_RESET 1 /* call board_reset() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) -#define CFG_BOOT_BASE_ADDR 0xf0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) - - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yellowstone\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yellowstone/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h deleted file mode 100644 index 59880fa5e4..0000000000 --- a/include/configs/yosemite.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * yosemite.h - configuration for YOSEMITE board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ -#define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_BOARD_RESET 1 /* call board_reset() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) -#define CFG_BOOT_BASE_ADDR 0xf0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) - - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yosemite\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yosemite/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_USB ) - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ |