ddr_spd: add routine for printing DDR2 SPD contents in human-readable format

---=== SPD EEPROM Information ===---
EEPROM Checksum of bytes 0-62                    OK (0xDF)
Total number of bytes in EEPROM                  256
Fundamental Memory type                          DDR2 SDRAM
SPD Revision                                     1.2

---=== Memory Characteristics ===---
Maximum module speed                             800 MHz (PC2-6400)
Size                                             2048 MB
Banks x Rows x Columns x Bits                    8 x 14 x 10 x 64
Ranks                                            2
SDRAM Device Width                               8 bits
Module Height                                    30.0 mm
Module Type                                      SO-DIMM (67.6 mm)
DRAM Package                                     Planar
Voltage Interface Level                          SSTL 1.8V
Module Configuration Type                        No Parity
Refresh Rate                                     Reduced (7.8 us) - Self Refresh
Supported Burst Lengths                          4, 8
Supported CAS Latencies (tCL)                    6T
tCL-tRCD-tRP-tRAS                                6-6-6-18 as DDR2-800
Minimum Cycle Time                               2.5 ns at CAS 6
Maximum Access Time                              0.40 ns at CAS 6
Maximum Cycle Time (tCK max)                     8 ns

---=== Timing Parameters ===---
Address/Command Setup Time Before Clock (tIS)    0.17 ns
Address/Command Hold Time After Clock (tIH)      0.25 ns
Data Input Setup Time Before Strobe (tDS)        0.05 ns
Data Input Hold Time After Strobe (tDH)          0.12 ns
Minimum Row Precharge Delay (tRP)                15.00 ns
Minimum Row Active to Row Active Delay (tRRD)    7.50 ns
Minimum RAS# to CAS# Delay (tRCD)                15.00 ns
Minimum RAS# Pulse Width (tRAS)                  45.00 ns
Write Recovery Time (tWR)                        15.00 ns
Minimum Write to Read CMD Delay (tWTR)           7.50 ns
Minimum Read to Pre-charge CMD Delay (tRTP)      7.50 ns
Minimum Active to Auto-refresh Delay (tRC)       60.00 ns
Minimum Recovery Delay (tRFC)                    127 ns
Maximum DQS to DQ Skew (tDQSQ)                   0.20 ns
Maximum Read Data Hold Skew (tQHS)               0.30 ns

---=== Manufacturing Information ===---
Manufacturer JEDEC ID                            7f 98 00 00 00 00 00 00
Manufacturing Location Code                      0x05
Part Number
Manufacturing Date                               2014-W47
Assembly Serial Number                           0x43266892

Signed-off-by: Alexander Smirnov <alllecs@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index fc03bacc56..01fe73c615 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -228,6 +228,7 @@ struct ddr3_spd_eeprom_s {
 	uint8_t cust[80];        /* 176-255 Open for Customer Use */
 };
 
+extern void ddr_spd_print(uint8_t *record);
 extern uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd);
 extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);