hw_random: add OMAP RNG driver

To enable proper hardening with stack protector, add support for the
OMAP RNG driver. This has been tested on a Beagle Bone Black.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240313105631.686778-13-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 34 insertions, 0 deletions

diff --git a/include/linux/clk.h b/include/linux/clk.h
index fe0b1ce3e3..7ba0679d03 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -1098,6 +1098,39 @@ static inline struct clk *clk_get_enabled(struct device *dev, const char *id)
 }
 
 /**
+ * clk_get_optional_enabled - clk_get_optional() +
+ *                            clk_prepare_enable()
+ * @dev: device for clock "consumer"
+ * @id: clock consumer ID
+ *
+ * Return: a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.  The implementation
+ * uses @dev and @id to determine the clock consumer, and thereby
+ * the clock producer.  If no such clk is found, it returns NULL
+ * which serves as a dummy clk.  That's the only difference compared
+ * to clk_get_enabled().
+ *
+ * The returned clk (if valid) is enabled.
+ */
+static inline struct clk *clk_get_optional_enabled(struct device *dev, const char *id)
+{
+	struct clk *clk;
+	int ret;
+
+	clk = clk_get_optional(dev, id);
+	if (IS_ERR_OR_NULL(clk))
+		return clk;
+
+	ret = clk_enable(clk);
+	if (ret) {
+		clk_put(clk);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
+/**
  * clk_get_if_available - get clock, ignoring known unavailable clock controller
  * @dev: device for clock "consumer"
  * @id: clock consumer ID
diff --git a/include/mach/omap/am33xx-clock.h b/include/mach/omap/am33xx-clock.h
index b0293db990..af47a0f3e7 100644
--- a/include/mach/omap/am33xx-clock.h
+++ b/include/mach/omap/am33xx-clock.h
@@ -139,6 +139,7 @@
 #define CM_PER_UART4_CLKCTRL            (CM_PER + 0x78) /* UART4 */
 #define CM_PER_I2C1_CLKCTRL             (CM_PER + 0x48) /* I2C1 */
 #define CM_PER_I2C2_CLKCTRL             (CM_PER + 0x44) /* I2C2 */
+#define CM_PER_RNG_CLKCTRL              (CM_PER + 0x90) /* RNG */
 #define CM_WKUP_GPIO0_CLKCTRL           (CM_WKUP + 0x8) /* GPIO0 */
 #define CM_WKUP_ADC_TSC_CLKCTRL         (CM_WKUP + 0xbc)/* TSCADC */