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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2024-03-18 11:18:17 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-03-18 13:17:07 +0100 |
commit | d26f2505c399c9a512036c65dde4ecd8360c4b87 (patch) | |
tree | c7940dcc58c597c827a60f34095dc76db2c724d4 /include | |
parent | 54a4e53cc859aedd266ba7249efcf6296f80a612 (diff) | |
download | barebox-d26f2505c399c9a512036c65dde4ecd8360c4b87.tar.gz barebox-d26f2505c399c9a512036c65dde4ecd8360c4b87.tar.xz |
zynqmp: firmware: add functions to set tap delay
Add a function to set the tap delay for the clk phase of the sd host
controller.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Diffstat (limited to 'include')
-rw-r--r-- | include/mach/zynqmp/firmware-zynqmp.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/mach/zynqmp/firmware-zynqmp.h b/include/mach/zynqmp/firmware-zynqmp.h index 630677285f..00c63058f4 100644 --- a/include/mach/zynqmp/firmware-zynqmp.h +++ b/include/mach/zynqmp/firmware-zynqmp.h @@ -27,6 +27,10 @@ #define ZYNQMP_PCAP_STATUS_FPGA_DONE BIT(3) +/* ZynqMP SD tap delay tuning */ +#define SD_ITAPDLY 0xFF180314 +#define SD_OTAPDLYSEL 0xFF180318 + enum pm_ioctl_id { IOCTL_GET_RPU_OPER_MODE = 0, IOCTL_SET_RPU_OPER_MODE = 1, @@ -80,6 +84,22 @@ struct zynqmp_pm_query_data { u32 arg3; }; +enum pm_node_id { + NODE_SD_0 = 39, + NODE_SD_1 = 40, +}; + +enum tap_delay_type { + PM_TAPDELAY_INPUT = 0, + PM_TAPDELAY_OUTPUT = 1, +}; + +enum dll_reset_type { + PM_DLL_RESET_ASSERT = 0, + PM_DLL_RESET_RELEASE = 1, + PM_DLL_RESET_PULSE = 2, +}; + struct zynqmp_eemi_ops { int (*get_api_version)(u32 *version); int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); @@ -99,6 +119,9 @@ struct zynqmp_eemi_ops { const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); +int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); +int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); + int zynqmp_pm_write_ggs(u32 index, u32 value); int zynqmp_pm_read_ggs(u32 index, u32 *value); int zynqmp_pm_write_pggs(u32 index, u32 value); |