OMAP: Add GPMC NAND support

This patch adds support for a generic GPMC driver
also a GPMC controller driver to allow platforms
to add NAND devices generically.

Signed-off-by: Nishanth Menon <x0nishan@ti.com>

2 files changed, 181 insertions, 4 deletions

diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index e216cd39ec..a658cf00e7 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -1,18 +1,24 @@
 /**
  * @file
- * @brief This file contains the GPMC specific register definitions
+ * @brief This file contains the GPMC's generic definitions
  *
  * FileName: include/asm-arm/arch-omap/gpmc.h
  *
- * Originally from Linux kernel:
- * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
- * include/asm-arm/arch-omap/omap34xx.h
+ * OMAP's General Purpose Memory Controller(GPMC) provides features
+ * allowing us to communicate with memory devices such as NOR, NAND,
+ * OneNAND, SRAM etc.. This file defines certain generic parameters
+ * allowing us to configure the same painlessly.
+ *
  */
 /*
  * (C) Copyright 2008
  * Texas Instruments, <www.ti.com>
  * Nishanth Menon <x0nishan@ti.com>
  *
+ * Originally from Linux kernel:
+ * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
+ * include/asm-arm/arch-omap/omap34xx.h
+ *
  * Copyright (C) 2007 Texas Instruments, <www.ti.com>
  * Copyright (C) 2007 Nokia Corporation.
  *
@@ -39,12 +45,28 @@
 #define GPMC_REG(REGNAME)	(OMAP_GPMC_BASE + GPMC_##REGNAME)
 
 #define GPMC_SYS_CONFIG		(0x10)
+#define GPMC_SYS_STATUS		(0x14)
+#define GPMC_IRQSTATUS		(0x18)
 #define GPMC_IRQ_ENABLE		(0x1C)
 #define GPMC_TIMEOUT_CONTROL	(0x40)
 #define GPMC_CFG		(0x50)
+#define GPMC_STATUS		(0x54)
 #define GPMC_PREFETCH_CONFIG_1	(0x1E0)
 #define GPMC_PREFETCH_CONFIG_2	(0x1E4)
 #define GPMC_PREFETCH_CTRL	(0x1EC)
+#define GPMC_ECC_CONFIG		(0x1F4)
+#define GPMC_ECC_CONTROL	(0x1F8)
+#define GPMC_ECC_SIZE_CONFIG	(0x1FC)
+#define GPMC_ECC1_RESULT	(0x200)
+#define GPMC_ECC2_RESULT	(0x204)
+#define GPMC_ECC3_RESULT	(0x208)
+#define GPMC_ECC4_RESULT	(0x20C)
+#define GPMC_ECC5_RESULT	(0x210)
+#define GPMC_ECC6_RESULT	(0x214)
+#define GPMC_ECC7_RESULT	(0x218)
+#define GPMC_ECC8_RESULT	(0x21C)
+#define GPMC_ECC9_RESULT	(0x220)
+
 #define GPMC_CONFIG1_0		(0x60)
 #define GPMC_CONFIG1_1		(0x90)
 #define GPMC_CONFIG1_2		(0xC0)
@@ -102,4 +124,38 @@
 #define GPMC_CONFIG7_6		(0x198)
 #define GPMC_CONFIG7_7		(0x1C8)
 
+#define GPMC_NUM_CS		8
+#define GPMC_CONFIG_CS_SIZE	(GPMC_CONFIG1_1 - GPMC_CONFIG1_0)
+#define GPMC_CONFIG_REG_OFF	(GPMC_CONFIG2_0 - GPMC_CONFIG1_0)
+
+#define GPMC_CS_NAND_COMMAND	(0x1C)
+#define GPMC_CS_NAND_ADDRESS	(0x20)
+#define GPMC_CS_NAND_DATA	(0x24)
+
+#define GPMC_SIZE_128M		0x08
+#define GPMC_SIZE_64M		0x0C
+#define GPMC_SIZE_32M		0x0E
+#define GPMC_SIZE_16M		0x0F
+
+#define NAND_WP_BIT		0x00000010
+
+#ifndef __ASSEMBLY__
+
+/** Generic GPMC configuration structure to be used to configure a
+ *  chip select
+ */
+struct gpmc_config {
+	unsigned int cfg[6];
+	unsigned int base;
+	unsigned char size;
+};
+
+/** Generic configuration - will reset all the cs configs. */
+void gpmc_generic_init(unsigned int cfg);
+
+/** Configuration for a specific chip select */
+void gpmc_cs_config(char cs, struct gpmc_config *config);
+
+#endif
+
 #endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/include/asm-arm/arch-omap/gpmc_nand.h b/include/asm-arm/arch-omap/gpmc_nand.h
new file mode 100644
index 0000000000..c6c51d5d52
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpmc_nand.h
@@ -0,0 +1,121 @@
+/**
+ * @file
+ * @brief This file contains exported structure for NAND
+ *
+ * FileName: include/asm-arm/arch-omap/gpmc_nand.h
+ *
+ * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller
+ * embedded. this file provides the platform data structure required to
+ * hook on to it.
+ *
+ */
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Nishanth Menon <x0nishan@ti.com>
+ *
+ * Originally from Linux kernel:
+ * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz
+ * include/asm-arm/arch-omap/nand.h
+ *
+ * Copyright (C) 2006 Micron Technology Inc.
+ * Author: Shahrom Sharif-Kashani
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_OMAP_NAND_GPMC_H
+#define  __ASM_OMAP_NAND_GPMC_H
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+
+/** omap nand platform data structure */
+struct gpmc_nand_platform_data {
+	/** Chip select you want to use */
+	int cs;
+	struct mtd_partition *parts;
+	int nr_parts;
+	/** If there are any special setups you'd want to do */
+	int (*nand_setup) (struct gpmc_nand_platform_data *);
+
+	/** set up if we want H/w ECC here and other
+	 * platform specific configs here
+	 */
+	unsigned short plat_options;
+	/** setup any special options */
+	unsigned int options;
+	/** set up device access as 8,16 as per GPMC config */
+	char device_width;
+	/** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */
+	char wait_mon_pin;
+	/** Set this to the max timeout for the device */
+	uint64_t max_timeout;
+
+	/* if you like a custom oob use this. */
+	struct nand_ecclayout *oob;
+	/** platform specific private data */
+	void *priv;
+};
+
+/** Platform specific options definitions */
+/** plat_options: Wait montioring pin low */
+#define NAND_WAITPOL_LOW        (0 << 0)
+/** plat_options: Wait montioring pin high */
+#define NAND_WAITPOL_HIGH       (1 << 0)
+#define NAND_WAITPOL_MASK       (1 << 0)
+
+#ifdef CONFIG_NAND_OMAP_GPMC_HWECC
+/** plat_options: hw ecc enabled */
+#define NAND_HWECC_ENABLE       (1 << 1)
+#endif
+/** plat_options: hw ecc disabled */
+#define NAND_HWECC_DISABLE      (0 << 1)
+#define NAND_HWECC_MASK         (1 << 1)
+
+/* Typical BOOTROM oob layouts-requires hwecc **/
+#ifdef CONFIG_NAND_OMAP_GPMC_HWECC
+/** Large Page x8 NAND device Layout */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+		9, 10, 11, 12},\
+	.oobfree = {\
+		{.offset = 60,\
+		 .length = 2 } } \
+}
+
+/** Large Page x16 NAND device Layout */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+		10, 11, 12, 13},\
+	.oobfree = {\
+		{.offset = 60,\
+		 .length = 2 } } \
+}
+
+/** Small Page x8 NAND device Layout */
+#define GPMC_NAND_ECC_SP_x8_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {1, 2, 3},\
+	.oobfree = {\
+		{.offset = 14,\
+		 .length = 2 } } \
+}
+
+/** Small Page x16 NAND device Layout */
+#define GPMC_NAND_ECC_SP_x16_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {2, 3, 4},\
+	.oobfree = {\
+		{.offset = 14,\
+		 .length = 2 } } \
+}
+
+#endif				/* CONFIG_NAND_OMAP_GPMC_HWECC */
+
+#endif				/* __ASM_OMAP_NAND_GPMC_H */