svn_rev_118

thousands of things

5 files changed, 22 insertions, 140 deletions

diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 318de22a49..ba557d8b0e 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -7,10 +7,8 @@
  */
 
 # ifndef __ASSEMBLY__
-#  define __REG(x)	(*((volatile u32 *)(x)))
-# define __REG2(x,y)	\
-	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-			  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+# define __REG(x)	(*((volatile u32 *)(x)))
+# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
 # else
 #  define __REG(x) (x)
 #  define __REG2(x,y) ((x)+(y))
@@ -430,123 +428,6 @@
 #define LCDISR_ERR_RES (1<<2)
 #define LCDISR_EOF     (1<<1)
 #define LCDISR_BOF     (1<<0)
-/*
- *  UART Module
- */
-#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */
-#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */
-#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */
-#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */
-#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */
-#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */
-#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */
-#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */
-#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */
-#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */
-#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */
-#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */
-#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */
-#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */
-#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */
-#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */
-#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */
-#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */
-#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */
-#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */
-#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */
-#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */
-#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register */
-
-/* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
-#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)	 /* Doze */
-#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8) /* Parity enable */
-#define  UCR2_PROE       (1<<7) /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)	/* Stop */
-#define  UCR2_WS         (1<<5)	/* Word size */
-#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
-#define  UCR2_SRST 	 (1<<0)	/* SW reset */
-#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
-#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC  	 (1<<5) /* IR special case */
-#define  UCR4_TCEN  	 (1<<3) /* Transmit complete interrupt enable */
-#define  UCR4_BKEN  	 (1<<2) /* Break condition interrupt enable */
-#define  UCR4_OREN  	 (1<<1) /* Receiver overrun interrupt enable */
-#define  UCR4_DREN  	 (1<<0) /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
-#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD  	 (1<<12) /* RTS delta */
-#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
-#define  USR1_RXDS  	 (1<<6)	/* Receiver idle interrupt flag */
-#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
-#define  USR1_AWAKE 	 (1<<4)	/* Aysnc wake interrupt flag */
-#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE  	 (1<<12) /* Idle condition */
-#define  USR2_IRINT 	 (1<<8)	/* Serial infrared interrupt flag */
-#define  USR2_WAKE  	 (1<<7)	/* Wake */
-#define  USR2_RTSF  	 (1<<4)	/* RTS edge interrupt flag */
-#define  USR2_TXDC  	 (1<<3)	/* Transmitter complete */
-#define  USR2_BRCD  	 (1<<2)	/* Break condition */
-#define  USR2_ORE        (1<<1)	/* Overrun error */
-#define  USR2_RDR        (1<<0)	/* Recv data ready */
-#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
-#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
-#define  UTS_TXFULL 	 (1<<4)	/* TxFIFO full */
-#define  UTS_RXFULL 	 (1<<3)	/* RxFIFO full */
-#define  UTS_SOFTRST	 (1<<0)	/* Software reset */
 
 /* General purpose timers registers */
 #define TCTL1   __REG(IMX_TIM1_BASE)
diff --git a/include/common.h b/include/common.h
index 7d0dac1d9b..f25643c100 100644
--- a/include/common.h
+++ b/include/common.h
@@ -102,7 +102,6 @@ typedef volatile unsigned char	vu_char;
 #endif
 
 #include <part.h>
-#include <flash.h>
 #include <image.h>
 
 #ifdef	DEBUG
diff --git a/include/driver.h b/include/driver.h
index 428a3b961a..23e84a04c3 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -10,6 +10,7 @@ struct memarea_info;
 
 struct device_d {
 	char name[MAX_DRIVER_NAME];
+        char id[MAX_DRIVER_NAME];
 
 	unsigned long size;
 
@@ -17,36 +18,46 @@ struct device_d {
          * SDRAM.
          */
         unsigned long map_base;
-        unsigned long map_flags;
 
         void *platform_data;
+        void *priv;
 
         /* The driver for this device */
         struct driver_d *driver;
 
 	struct device_d *next;
-
-        struct partition *part;
 };
 
 struct driver_d {
 	char name[MAX_DRIVER_NAME];
 
-        void *priv;
-
 	struct driver_d *next;
 
         int     (*probe) (struct device_d *);
-        ssize_t (*read)  (struct device_d*, void* buf, size_t count, unsigned long offset);
-        ssize_t (*write) (struct device_d*, void* buf, size_t count, unsigned long offset);
-        ssize_t (*erase) (struct device_d*, struct memarea_info *);
+        ssize_t (*read)  (struct device_d*, void* buf, size_t count, ulong offset, ulong flags);
+        ssize_t (*write) (struct device_d*, void* buf, size_t count, ulong offset, ulong flags);
+        ssize_t (*erase) (struct device_d*, size_t count, unsigned long offset);
+
+        void    (*info) (struct device_d *);
+        void    (*shortinfo) (struct device_d *);
 };
 
+#define RW_SIZE(x)      (x)
+#define RW_SIZE_MASK    0x7
+
 int register_driver(struct driver_d *);
 int register_device(struct device_d *);
 void unregister_device(struct device_d *);
 
 struct device_d *device_from_spec_str(const char *str, char **endp);
 struct device_d *get_device_by_name(char *name);
+
+ssize_t read(struct device_d *dev, void *buf, size_t count, ulong offset, ulong flags);
+ssize_t write(struct device_d *dev, void *buf, size_t count, ulong offset, ulong flags);
+ssize_t erase(struct device_d *dev, size_t count, unsigned long offset);
+
+ssize_t mem_read(struct device_d *dev, void *buf, size_t count, ulong offset, ulong flags);
+ssize_t mem_write(struct device_d *dev, void *buf, size_t count, ulong offset, ulong flags);
+
 #endif /* DRIVER_H */
 
diff --git a/include/net.h b/include/net.h
index 3c5343b981..99b3d7d982 100644
--- a/include/net.h
+++ b/include/net.h
@@ -462,6 +462,7 @@ extern void	copy_filename (char *dst, char *src, int size);
 extern void eth_set_current(struct eth_device *eth);
 extern struct eth_device *eth_get_current(void);
 
+extern struct eth_device dm9000_eth;
 extern struct eth_device at91rm9200_eth;
 extern struct eth_device smc91111_eth;
 
diff --git a/include/partition.h b/include/partition.h
index 014529fc07..19116437ef 100644
--- a/include/partition.h
+++ b/include/partition.h
@@ -3,15 +3,5 @@
 
 struct device_d;
 
-struct partition {
-        int num;
-
-        struct device_d *parent;
-
-        struct device_d device;
-
-        struct partition *next;
-};
-
 #endif /* __PARTITION_H */